diff --git a/.gitignore b/.gitignore index 7cc5e99324..3127b15362 100644 --- a/.gitignore +++ b/.gitignore @@ -3,3 +3,8 @@ *~ .dep build +*.vpwhistuxml +*.vpwhistu +*.vtg +*.jdebug +*.jdebug.user diff --git a/.gitmodules b/.gitmodules index e4fb6f42e1..3f80f11b7f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "ext/mcux-sdk"] path = ext/mcux-sdk url = https://github.com/NXPmicro/mcux-sdk +[submodule "ext/gecko_sdk"] + path = ext/gecko_sdk + url = https://github.com/SiliconLabs/gecko_sdk diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/Makefile b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/Makefile new file mode 100644 index 0000000000..01aec41c62 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/Makefile @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg14p23x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG14P/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_SLWSTK6061B/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/EFR32FG14PXF256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DEFR32FG14P233F256GM48 \ + -DEFR32_HFRCO_STARTUP_FREQ=19000000UL \ + -DEFR32_LFXO_FREQ=32768UL \ + -DEFR32_HFXO_FREQ=38400000UL \ + -DCORTEX_ENABLE_WFI_IDLE + +# Define ASM defines here +UADEFS = -DEFR32FG14P233F256GM48=1 \ + -DEFR32_HFRCO_STARTUP_FREQ=19000000UL \ + -DEFR32_LFXO_FREQ=32768UL \ + -DEFR32_HFXO_FREQ=38400000UL \ + -DCORTEX_ENABLE_WFI_IDLE + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/chconf.h b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/chconf.h new file mode 100644 index 0000000000..c309239548 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 16 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1024 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/halconf.h b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/halconf.h new file mode 100644 index 0000000000..f79db30f92 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/halconf.h @@ -0,0 +1,553 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/halconf_community.h b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/halconf_community.h new file mode 100644 index 0000000000..43fdbf8690 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/halconf_community.h @@ -0,0 +1,173 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/mcuconf.h b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/mcuconf.h new file mode 100644 index 0000000000..e57696e3dc --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/cfg/mcuconf.h @@ -0,0 +1,50 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG14P23X_MCUCONF + +/* + * HAL driver system settings. + */ +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_HFRCO_ENABLED TRUE + +/* + * Peripherals clock sources. + */ +#define EFR32_RTCCSEL EFR32_RTCCSEL_LFXO +#define EFR32_LETIM1SEL EFR32_LETIM1SEL_LFXO + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 8 +#define EFR32_ST_USE_TIMER 1 + +#endif /* MCUCONF_H */ diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/main.c b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/main.c new file mode 100644 index 0000000000..128e1dc7db --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/main.c @@ -0,0 +1,44 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +//#include "rt_test_root.h" +//#include "oslib_test_root.h" + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/readme.txt b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/readme.txt new file mode 100644 index 0000000000..418698b496 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG14P-SLWSTK6061B/readme.txt @@ -0,0 +1,23 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 EFR32FG14P. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an SLWSTK6061B EFR32FG 868 MHz 2.4 GHz and Sub-GHz Starter Kit. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port. + +** Build Procedure ** + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Silicon Labs and are licensed under a different license. Also note that not +all the files present in the emlib library are distributed with ChibiOS/RT, +you can find the whole library on the ST web site: + + http://www.silabs.com diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/Makefile b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/Makefile new file mode 100644 index 0000000000..2a3f475766 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/Makefile @@ -0,0 +1,201 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.mk +include emlib/emlib.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +# SL_TRUSTZONE_NONSECURE and SYSTEM_NO_STATIC_MEMORY are only for emlib. +UDEFS = -DEFR32FG23A010F256GM48=1 \ + -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE \ + -DSL_TRUSTZONE_NONSECURE \ + -DSYSTEM_NO_STATIC_MEMORY + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/chconf.h b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/chconf.h new file mode 100644 index 0000000000..e3e4a92e20 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/halconf.h b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/halconf.h new file mode 100644 index 0000000000..caf84a87f3 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/halconf.h @@ -0,0 +1,553 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC TRUE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/halconf_community.h b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/halconf_community.h new file mode 100644 index 0000000000..43fdbf8690 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/halconf_community.h @@ -0,0 +1,173 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/mcuconf.h b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/mcuconf.h new file mode 100644 index 0000000000..f1ce06596d --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/cfg/mcuconf.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_LFXO + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 FALSE +#define EFR32_SIO_USE_EUSART2 FALSE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib.mk b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib.mk new file mode 100644 index 0000000000..958980fa53 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib.mk @@ -0,0 +1,35 @@ +# Required platform files. +GECKO_SDK = $(CHIBIOS_CONTRIB)/ext/gecko_sdk + +EMLIBSRC = \ + emlib/emlib_chibios.c \ + $(GECKO_SDK)/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c \ + $(GECKO_SDK)/platform/common/src/sl_assert.c \ + $(GECKO_SDK)/platform/emlib/src/em_acmp.c \ + $(GECKO_SDK)/platform/emlib/src/em_cryotimer.c \ + $(GECKO_SDK)/platform/emlib/src/em_cmu.c \ + $(GECKO_SDK)/platform/emlib/src/em_emu.c \ + $(GECKO_SDK)/platform/emlib/src/em_eusart.c \ + $(GECKO_SDK)/platform/emlib/src/em_gpio.c \ + $(GECKO_SDK)/platform/emlib/src/em_letimer.c \ + $(GECKO_SDK)/platform/emlib/src/em_pcnt.c \ + $(GECKO_SDK)/platform/emlib/src/em_prs.c \ + $(GECKO_SDK)/platform/emlib/src/em_lesense.c \ + $(GECKO_SDK)/platform/emlib/src/em_lcd.c \ + $(GECKO_SDK)/platform/emlib/src/em_system.c \ + $(GECKO_SDK)/platform/emlib/src/em_vdac.c + + #$(GECKO_SDK)/platform/security/sl_component/sl_trustzone/src/sli_tz_service_syscfg_ns.c \ + +EMLIBINC = \ + emlib \ + $(GECKO_SDK)/platform/security/sl_component/sl_trustzone/inc/common \ + $(GECKO_SDK)/platform/security/sl_component/sl_trustzone/inc/secure \ + $(GECKO_SDK)/platform/security/sl_component/sl_trustzone/inc/nonsecure \ + $(GECKO_SDK)/util/third_party/trusted-firmware-m/interface/include \ + $(GECKO_SDK)/platform/common/inc \ + $(GECKO_SDK)/platform/emlib/inc + +# Shared variables +ALLCSRC += $(EMLIBSRC) +ALLINC += $(EMLIBINC) diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib_chibios.c b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib_chibios.c new file mode 100644 index 0000000000..0cfa9ad9f6 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib_chibios.c @@ -0,0 +1,33 @@ +#include "ch.h" + + +void _start(void) { + + extern int main(void); + main(); + NVIC_SystemReset(); +} + + +unsigned long CORE_EnterCritical(void) { + + chSysLock(); + return 0; +} + + +void CORE_ExitCritical(unsigned long unused) { + + (void)unused; + chSysUnlock(); +} + +uint32_t sli_tz_syscfg_set_systicextclken_cfgsystic(void) { + + return 0; +} + +uint32_t sli_tz_syscfg_clear_systicextclken_cfgsystic(void) { + + return 0; +} \ No newline at end of file diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib_chibios.h b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib_chibios.h new file mode 100644 index 0000000000..013d94c8d9 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/emlib/emlib_chibios.h @@ -0,0 +1,22 @@ +#ifndef EMLIB_CHIBIOS_H +#define EMLIB_CHIBIOS_H + +#include "em_acmp.h" +#include "em_assert.h" +#include "em_cryotimer.h" +#include "em_chip.h" +#include "em_cmu.h" +#include "em_emu.h" +#include "em_eusart.h" +#include "em_gpio.h" +#include "em_letimer.h" +#include "em_lcd.h" +#include "em_pcnt.h" +#include "em_prs.h" +#include "em_lesense.h" +#include "em_system.h" +#include "em_syscfg.h" +#include "em_vdac.h" + +#endif /* EMLIB_CHIBIOS_H */ + diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/main.c b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/main.c new file mode 100644 index 0000000000..f135c3febd --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/main.c @@ -0,0 +1,291 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "cmsis_os.h" +#include "hal.h" +#include "chprintf.h" +#include "rt_test_root.h" +#include "oslib_test_root.h" + +#include "emlib_chibios.h" + +CC_USED CC_SECTION(".ram0") +static int no_init_variable; + +CC_USED +static void gpio_callback(void* arg) { + + (void)arg; + return; +} + +static void dm_callback(void *ptr, uint32_t mask) { + (void)ptr; + (void)mask; + + return; +} + +static void dma_test(BaseSequentialStream* siop) { + uint8_t dma_test_src[16] = {1, 2, 3, 4, 5, 6, 7, 8, 8, 7, 6, 5, 4, 3, 2, 1}; + uint8_t dma_test_dst[32] = {0}; + + const efr32_dma_stream_t *dmastp1 = dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, dm_callback, &dma_test_dst[0]); + const efr32_dma_stream_t *dmastp2 = dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, dm_callback, &dma_test_dst[16]); + + dmaStartMemCopy(dmastp1, 0, &dma_test_src[0], &dma_test_dst[0], 8); + dmaStartMemCopy(dmastp2, 0, &dma_test_src[8], &dma_test_dst[16], 8); + + dmaWaitCompletion(dmastp1); + dmaWaitCompletion(dmastp2); + + dmaStreamFree(dmastp1); + dmaStreamFree(dmastp2); + + for (size_t i = 0; i < sizeof(dma_test_dst); i++) { + chprintf(siop, "0x%02x, ", dma_test_dst[i]); + } + chprintf(siop, "\n"); + + return; +} + +/* + * Application entry point. + */ +int main(void) { + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + #if 0 + //palSetPadMode(GPIOC, 3, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_HCLK)); + //palSetPadMode(GPIOA, 0, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_HCLK)); + //palSetPadMode(GPIOC, 3, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_HFRCOEM23)); + palSetPadMode(GPIOC, 3, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_LFXO)); + while (true); + #endif + + #if 0 + palSetPadMode(GPIOC, 3, PAL_MODE_OUTPUT_PUSHPULL); + palWritePad(GPIOC, 3, PAL_HIGH); + palWritePad(GPIOC, 3, PAL_LOW); + palSetPad(GPIOC, 3); + palClearPad(GPIOC, 3); + palSetPad(GPIOC, 3); + palTogglePad(GPIOC, 3); + palTogglePad(GPIOC, 3); + palSetPadMode(GPIOC, 3, PAL_MODE_RESET); + + palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_PULLUP); + uint32_t pins; + (void)pins; + pins = palReadPad(GPIOC, 3); + pins = palReadPad(GPIOC, 3); + + palSetPadCallback(GPIOC, 3, gpio_callback, NULL); + palEnablePadEvent(GPIOC, 3, PAL_EVENT_MODE_BOTH_EDGES); + #endif + + #if EFR32_SIO_USE_EUSART1 == TRUE + #if 0 + palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART0_TX)); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART0_RX)); + #else + palSetPadMode(GPIOB, 1, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART0_TX)); + palSetPadMode(GPIOB, 2, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART0_RX)); + #endif + + static const SIOConfig sio_config1 = { + #if 1 + .baud = 2400U, /* Baudrate (2400 max. for LF operation) */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (4U << 5), /* Disable oversampling (for LF operation) */ + .framecfg = EFR32_SIO_LLD_EUSART_8E1, + #else + .baud = 115200U, /* Baudrate */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (0U << 5), /* 16x oversampling (for HF operation) */ + .framecfg = EFR32_SIO_LLD_EUSART_8N1, + #endif + }; + + SIODriver* siop = &SIOD1; + sioStart(siop, &sio_config1); + sioStop(siop); + sioStart(siop, &sio_config1); + #endif + + #if EFR32_SIO_USE_EUSART2 == TRUE + palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART1_TX)); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART1_RX)); + + static const SIOConfig sio_config2 = { + .baud = 115200U, /* Baudrate */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (0U << 5), /* 16x oversampling (for HF operation) */ + .framecfg = EFR32_SIO_LLD_EUSART_8N1, + }; + + SIODriver* siop = &SIOD2; + sioStart(siop, &sio_config2); + sioStop(siop); + sioStart(siop, &sio_config2); + #endif + + #if EFR32_SIO_USE_EUSART3 == TRUE + palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART2_TX)); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART2_RX)); + + static const SIOConfig sio_config3 = { + .baud = 115200U, /* Baudrate */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (0U << 5), /* 16x oversampling (for HF operation) */ + .framecfg = EFR32_SIO_LLD_EUSART_8N1, + }; + + SIODriver* siop = &SIOD3; + sioStart(siop, &sio_config3); + sioStop(siop); + sioStart(siop, &sio_config3); + #endif + + #if EFR32_SIO_USE_USART1 == TRUE + #if 1 + palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(USART0_TX)); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(USART0_RX)); + #else + palSetPadMode(GPIOB, 1, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(USART0_TX)); + palSetPadMode(GPIOB, 2, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(USART0_RX)); + #endif + + static const SIOConfig sio_config4 = { + .baud = 115200U, /* Baudrate */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (0U << 5), /* 16x oversampling (for HF operation) */ + .framecfg = EFR32_SIO_LLD_USART_8N1, + }; + + SIODriver* siop = &SIOD4; + sioStart(siop, &sio_config4); + sioStop(siop); + sioStart(siop, &sio_config4); + #endif + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + RTCDateTime ts = { + .year = 44, + .month = 6, + .dstflag = 0, + .dayofweek = 7, + .day = 9, + .millisecond = (19*3600 + 4*60 + 30) * 1000 + 123 + }; + rtcSetTime(&RTCD1, &ts); + struct tm tim; + uint32_t tv_msec; + + RTCAlarm alarmspec = { + .sec = 5, + }; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + + #if 0 + dma_test((BaseSequentialStream*)siop); + #endif + + //lesenseObjectInit(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + //palDisablePadEvent(GPIOC, 3); + #if 1 + //osDelay(1000); + rtcGetAlarm(&RTCD1, 0, &alarmspec); + rtcGetTime(&RTCD1, &ts); + rtcConvertDateTimeToStructTm(&ts, &tim, &tv_msec); + chprintf((BaseSequentialStream*)siop, "%02u-%02u-%02u %02u:%02u:%02u, %d\r\n", + tim.tm_year + 1900, tim.tm_mon + 1, tim.tm_mday, + tim.tm_hour, tim.tm_min, tim.tm_sec, tim.tm_wday); + //chprintf((BaseSequentialStream*)tm_mon siop, "%u\r\n", ts2.millisecond); + //continue; + #endif + if (siop != NULL) { + #if 0 + // Don't execute tests. + palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_PULLUP); + if (palReadPad(GPIOC, 3) == PAL_LOW) { + test_execute((BaseSequentialStream*)siop, &rt_test_suite); + test_execute((BaseSequentialStream*)siop, &oslib_test_suite); + } + #endif + + while (true) { + msg_t msg; + uint8_t buf[32]; + #if 0 + msg = sioGetX(siop); + if (msg == MSG_TIMEOUT) break; + sioPutX(siop, msg); + #elif 0 + msg = sioSynchronizeRX(siop, TIME_MS2I(1000)); + if (msg == MSG_TIMEOUT)break; + msg = sioGetX(siop); + //osalDbgAssert(msg != MSG_TIMEOUT); + sioPutX(siop, msg); + msg = sioSynchronizeTXEnd(siop, TIME_MS2I(1000)); + //osalDbgAssert(msg == MSG_OK); + #elif 1 + msg = sioSynchronizeRX(siop, TIME_MS2I(1000)); + if (msg == SIO_MSG_ERRORS) { + sioGetAndClearErrors(siop); + break; + } + if (msg == MSG_TIMEOUT) break; + size_t rb = sioAsyncRead(siop, buf, sizeof(buf)); + if (rb > 0) { + sioAsyncWrite(siop, buf, rb); + msg = sioSynchronizeTX(siop, TIME_MS2I(1)); + //msg = sioSynchronizeTXEnd(siop, TIME_MS2I(1000)); + } + #elif 0 + buf[0] = '5A'; + sioAsyncWrite(siop, buf, 1); + msg = sioSynchronizeTX(siop, TIME_MS2I(1)); + #endif + } + + //osDelay(1000); + + #if 0 + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + EMU_EnterEM2(true); + #endif + } + } +} \ No newline at end of file diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/post-build.mk b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/post-build.mk new file mode 100644 index 0000000000..6377cf8c54 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23AXXXF256 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/readme.txt b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/readme.txt new file mode 100644 index 0000000000..398d759df5 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/readme.txt @@ -0,0 +1,42 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M33 EFR32FG23. ** +***************************************************************************** + +** TARGET ** + +The demo runs on a CUSTOM board EFR32FG23 equipped with EFR32FG23A010F256QFN48. + +** TODO ** + +HAL in general. Currently the HAL is far from being complete. + +Get RMU reset cause; factory default. + +Use BURTC for time keeping; implement calendar. + +Implement user data page write/read. + +Implement DC/DC mode switching. + +Make HCLK DIV4/8... (CLKOUT) working. + +Create radio driver with underlying RAIL lib. + +** The Demo ** + +What is working now: + * SYSTICK + * LETIMER0 for deep sleep and serial + * serial IO (SIO) implemented + * BURTC works as (software) RTC + +** Build Procedure ** + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Silicon Labs and are licensed under a different license. Also note that not +all the files present in the emlib library are distributed with ChibiOS/RT, +you can find the whole library on the Silicon Labs web site: + + https://www.silabs.com diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/source/lesense.c b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/source/lesense.c new file mode 100644 index 0000000000..94011611fe --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/source/lesense.c @@ -0,0 +1,478 @@ +#include "hal.h" +#include "ch.h" + +#include +#include "em_device.h" +#include "em_acmp.h" +#include "em_chip.h" +#include "em_cmu.h" +#include "em_emu.h" +#include "em_gpio.h" +#include "em_core.h" +#include "em_lesense.h" +#include "em_vdac.h" + + +struct LESENSEDriver { +}; + +typedef struct LESENSEDriver LESENSEDriver; + +#define LCSENSE_STATE0 0 +#define LCSENSE_STATE1 1 +#define LCSENSE_STATE2 2 +#define LCSENSE_STATE3 3 +#define LCSENSE_ERROR_STRING "ERROR" +#define INITIAL_STATE 0 + +/* PRS */ +#define PRS_CHANNEL0 0 +#define PRS_CHANNEL1 1 + +/* PCNT */ +#define PCNT_TOP 0xFFFF +#define PCNT_DIRCHANGE_STRING "DIRCHNG" + + +/**************************************************************************//** + * @brief LESENSE interrupt handler + * This function acknowledges the interrupt and reads the current + * decoder state + ******************************************************************************/ +OSAL_IRQ_HANDLER(EFR32_LESENSE_HANDLER) { + + uint32_t isr; + + OSAL_IRQ_PROLOGUE(); + + // Clear all LESENSE interrupt flag + isr = LESENSE_IntGet(); + LESENSE_IntClear(isr); + + if (isr & LESENSE_IF_DEC) { + // Check current decoder state + //decoder_state = LESENSE_DecoderStateGet(); + } + + OSAL_IRQ_EPILOGUE(); +} + +void initVdac(void) { + + #if 0 + // Enable the VDAC clock + CMU->VDAC0CLKCTRL_SET = CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; //CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; + CMU->CLKEN1_SET = CMU_CLKEN1_VDAC0; + + VDAC_TypeDef *vdac = VDAC0; + + #if 0 + uint32_t config = ( + ((2 << _VDAC_CFG_WARMUPTIME_SHIFT) & _VDAC_CFG_WARMUPTIME_MASK) + | (0 << _VDAC_CFG_DBGHALT_SHIFT) + | (0 << _VDAC_CFG_ONDEMANDCLK_SHIFT) + | (0 << _VDAC_CFG_DMAWU_SHIFT) + | (0 << _VDAC_CFG_BIASKEEPWARM_SHIFT) + | (0 << _VDAC_CFG_REFRESHPERIOD_SHIFT) + | (0 << _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT) + | (0 << _VDAC_CFG_PRESC_SHIFT) & _VDAC_CFG_PRESC_MASK) + | (0 << _VDAC_CFG_REFRSEL_SHIFT) + | (0 << _VDAC_CFG_CH0PRESCRST_SHIFT) + | (0 << _VDAC_CFG_SINERESET_SHIFT) + | (0 << _VDAC_CFG_SINEMODE_SHIFT) + | (0 << _VDAC_CFG_DIFF_SHIFT); + + vdac->CFG = config; + + uint32_t channelConfig = + (0 << _VDAC_CH0CFG_KEEPWARM_SHIFT) + | (0 << _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT) + | ((0 << _VDAC_CH0CFG_FIFODVL_SHIFT) & _VDAC_CH0CFG_FIFODVL_MASK) + | (0 << _VDAC_CH0CFG_REFRESHSOURCE_SHIFT) + | (0 << _VDAC_CH0CFG_TRIGMODE_SHIFT) + | (0 << _VDAC_CH0CFG_POWERMODE_SHIFT) + | (0 << _VDAC_CH0CFG_CONVMODE_SHIFT); + + vdac->CH0CFG = channelConfig; + + vdac->OUTTIMERCFG = ((uint32_t)(vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK))) + | ((5 << _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK); + #endif + + vdac->CFG = (vdac->CFG & _VDAC_CFG_PRESC_MASK) | ((20 << _VDAC_CFG_PRESC_SHIFT) & _VDAC_CFG_PRESC_MASK); + vdac->OUTCTRL_SET = VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC | (3 << _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT) | VDAC_OUTCTRL_AUXOUTENCH0; + vdac->CMD_SET = VDAC_CMD_CH0EN; + + vdac->EN_SET = _VDAC_EN_EN_MASK; + + while (true) { + vdac->CH0F = 512; + //osDelay(1); + for (volatile int i = 0; i < 10000; i++); + } + + #if 0 + vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH0_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK | _VDAC_OUTCTRL_SHORTCH0_MASK | _VDAC_OUTCTRL_AUXOUTENCH0_MASK | _VDAC_OUTCTRL_MAINOUTENCH0_MASK))) + | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH0_MASK) + | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT) + | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH0_SHIFT) + | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT) + | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT); + #endif + #else + // Use the HFRCOEM23 to clock the VDAC in order to operate in EM3 mode + CMU_ClockSelectSet(cmuClock_VDAC0, cmuSelect_HFRCOEM23); + + // Enable the HFRCOEM23 and VDAC clocks + CMU_ClockEnable(cmuClock_HFRCOEM23, true); + CMU_ClockEnable(cmuClock_VDAC0, true); + + // Use default settings + VDAC_Init_TypeDef init = VDAC_INIT_DEFAULT; + VDAC_InitChannel_TypeDef initChannel = VDAC_INITCHANNEL_DEFAULT; + + // Calculate the VDAC clock prescaler value resulting in a 1 MHz VDAC clock + init.prescaler = VDAC_PrescaleCalc(VDAC0, 1000000); + + // Clocking is requested on demand + init.onDemandClk = false; + + // Disable High Capacitance Load mode + initChannel.highCapLoadEnable = false; + + // Use Low Power mode + initChannel.powerMode = vdacPowerModeLowPower; + + initChannel.port = vdacChPortC; + initChannel.pin = 3; + initChannel.auxOutEnable = true; + initChannel.mainOutEnable = false; + initChannel.shortOutput = false; + +#if 0 + GPIO->CDBUSALLOC = GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 + | GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 + | GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 + | GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1; +#endif + GPIO->CDBUSALLOC = GPIO_CDBUSALLOC_CDODD0_VDAC0CH0; + //GPIO->BBUSALLOC = GPIO_BBUSALLOC_BODD0_VDAC0CH0; + + + // Initialize the VDAC and VDAC channel + VDAC_Init(VDAC0, &init); + VDAC_InitChannel(VDAC0, &initChannel, 0); + + // Enable the VDAC + VDAC_Enable(VDAC0, 0, true); + //writeDataDAC(VDAC0, DAC_DATA, DAC_CHANNEL); + //VDAC0->OPA[0].TIMER &= ~0x03F00; + //VDAC0->OPA[0].TIMER |= 1 << 16; //Set Settle time (number of clock cycles DAC is driven) + + VDAC_Channel0OutputSet(VDAC0, 1.0*4095/1.25); + #endif +} + +#if 0 +/**************************************************************************//** + * @brief Sets up the ACMP to count LC sensor pulses + *****************************************************************************/ +void setupACMP(void){ + // ACMP configuration constant table. + static const ACMP_Init_TypeDef initACMP ={ + .fullBias = true, // fullBias + .biasProg = 0x1F, // biasProg + .interruptOnFallingEdge = false, // interrupt on rising edge + .interruptOnRisingEdge = false, // interrupt on falling edge + .inputRange = acmpInputRangeFull, // Full ACMP range + .accuracy = acmpAccuracyHigh, // Low accuracy, low power consumption + .powerSource = acmpPowerSourceAvdd, // Use AVDD as power source + .hysteresisLevel_0 = acmpHysteresisLevel0, // hysteresis level 0 + .hysteresisLevel_1 = acmpHysteresisLevel0, // hysteresis level 1 + .vlpInput = acmpVLPInputVADIV, // Use VADIV as the VLP input source. + .inactiveValue = false, // inactive value + .enable = true // Enable after init. + }; + + static const ACMP_VAConfig_TypeDef initVa ={ + acmpVAInputVDD, // Use VDD as input for VA + 0x0C, // VA divider when ACMP output is 0 + 0x0B // VA divider when ACMP output is 1 + }; + + CMU_ClockEnable(cmuClock_ACMP0, true); + + // Initialize ACMP + ACMP_Init(ACMP0, &initACMP); + + // Setup VADIV + ACMP_VASetup(ACMP0, &initVa); + + // ACMP0 input channels + ACMP_ChannelSet(ACMP0, acmpInputVADIV, acmpInputAPORT0XCH0); + + // Enable LESENSE control of ACMP + ACMP_ExternalInputSelect(ACMP0, acmpExternalInputAPORT0X); +} + +/**************************************************************************//** + * @brief Sets up the LESENSE + *****************************************************************************/ +void setupLESENSE(void){ + // LESENSE configuration structure + static const LESENSE_Init_TypeDef initLesense ={ + .coreCtrl ={ + .scanStart = lesenseScanStartPeriodic, + .prsSel = lesensePRSCh0, + .scanConfSel = lesenseScanConfDirMap, + .invACMP0 = false, + .invACMP1 = false, + .dualSample = false, + .storeScanRes = false, + .bufOverWr = true, + .bufTrigLevel = lesenseBufTrigHalf, + .wakeupOnDMA = lesenseDMAWakeUpDisable, + .biasMode = lesenseBiasModeDutyCycle, + .debugRun = false + }, + + .timeCtrl ={ + .startDelay = 0 + }, + + .perCtrl ={ + .dacCh0Data = lesenseDACIfData, + .dacCh1Data = lesenseDACIfData, + .acmp0Mode = lesenseACMPModeMux, + .acmp1Mode = lesenseACMPModeDisable, + .warmupMode = lesenseWarmupModeNormal, + .dacScan = true, + .dacStartupHalf = true, + .dacCh0En = true + + }, + + .decCtrl ={ + .decInput = lesenseDecInputSensorSt, + .initState = 0, + .chkState = false, + .intMap = false, + .hystPRS0 = false, + .hystPRS1 = false, + .hystPRS2 = false, + .hystIRQ = false, + .prsCount = true, + .prsChSel0 = lesensePRSCh0, + .prsChSel1 = lesensePRSCh1, + .prsChSel2 = lesensePRSCh2, + .prsChSel3 = lesensePRSCh3 + } + }; + // Channel configuration + static LESENSE_ChDesc_TypeDef initLesenseCh ={ + .enaScanCh = true, + .enaPin = true, + .enaInt = false, + .chPinExMode = lesenseChPinExLow, + .chPinIdleMode = lesenseChPinIdleDACC, + .useAltEx = false, + .shiftRes = true, + .invRes = true, + .storeCntRes = true, + .exClk = lesenseClkHF, + .sampleClk = lesenseClkLF, + .exTime = 0x07, + .sampleDelay = 0x02, + .measDelay = 0x00, + .acmpThres = 0x00, + .sampleMode = lesenseSampleModeCounter, + .intMode = lesenseSetIntPosEdge, + .cntThres = 0x0000, + .compMode = lesenseCompModeLess, + .evalMode = lesenseEvalModeSlidingWindow + }; + + // Configure LC sense excitation/measure pin as push pull + GPIO_PinModeSet(LCSENSE_CH_PORT, LCSENSE_CH_PIN, gpioModePushPull, 0); + GPIO_PinModeSet(LCSENSE_CH_PORT, LCSENSE_CH_PIN+1, gpioModePushPull, 0); + GPIO_PinModeSet(LCSENSE_CH_PORT, LCSENSE_CH_PIN+3, gpioModePushPull, 0); + + // Use LFXO as LESENSE clock source since it is already used by the RTCC + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockEnable(cmuClock_CORELE, true); + CMU_ClockEnable(cmuClock_LESENSE, true); + + // Initialize LESENSE interface _with_ RESET + LESENSE_Init(&initLesense, true); + + // Configure channels + LESENSE_ChannelConfig(&initLesenseCh, LCSENSE_CH); + LESENSE_ChannelConfig(&initLesenseCh, LCSENSE_CH+1); + initLesenseCh.shiftRes = false; + initLesenseCh.invRes = true; + LESENSE_ChannelConfig(&initLesenseCh, LCSENSE_CH+3); + + LESENSE_ChannelSlidingWindow(LCSENSE_CH, 4, 20); + LESENSE_ChannelSlidingWindow(LCSENSE_CH+1, 4, 20); + LESENSE_ChannelSlidingWindow(LCSENSE_CH+3, 4, 20); + // Set scan frequency + LESENSE_ScanFreqSet(0, LCSENSE_SCAN_FREQ); + + // Set clock divisor for LF clock + LESENSE_ClkDivSet(lesenseClkLF, lesenseClkDiv_2); + // Set clock divisor for HF clock + LESENSE_ClkDivSet(lesenseClkHF, lesenseClkDiv_1); + + // Enable interrupt in NVIC + NVIC_EnableIRQ(LESENSE_IRQn); + + // Enable LC sensor + LESENSE_ChannelEnable(LCSENSE_CH, true, true); + LESENSE_ChannelEnable(LCSENSE_CH+1, true, true); + LESENSE_ChannelEnable(LCSENSE_CH+3, true, true); + + + /* Configure decoder + * Interrupts will be enabled for transitions between + * states 0 and 3 to show the pulse counter value + * Configuration structure for state 0 */ + LESENSE_DecStDesc_TypeDef decConf ={ + .chainDesc = false, + .confA ={ + .compVal = 0x02, + .compMask = 0x0, + .nextState = LCSENSE_STATE1, + .prsAct = lesenseTransActNone, + .setInt = false + }, + .confB ={ + .compVal = 0x01, + .compMask = 0x0, + .nextState = LCSENSE_STATE3, + .prsAct = lesenseTransActDown, + .setInt = false + } + }; + /* Configure state 0 */ + LESENSE_DecoderStateConfig(&decConf, LCSENSE_STATE0); + + /* Change necessary structure fields for state 1 */ + decConf.confA.compVal = 0x03; + decConf.confA.nextState = LCSENSE_STATE2; + decConf.confA.prsAct = lesenseTransActNone; + decConf.confA.setInt = false; + decConf.confB.compVal = 0x00; + decConf.confB.nextState = LCSENSE_STATE0; + decConf.confB.prsAct = lesenseTransActNone; + decConf.confB.setInt = false; + /* Configure state 1 */ + LESENSE_DecoderStateConfig(&decConf, LCSENSE_STATE1); + + /* Change necessary structure fields for state 2 */ + decConf.confA.compVal = 0x01; + decConf.confA.nextState = LCSENSE_STATE3; + decConf.confA.prsAct = lesenseTransActNone; + decConf.confA.setInt = false; + decConf.confB.compVal = 0x02; + decConf.confB.nextState = LCSENSE_STATE1; + decConf.confB.prsAct = lesenseTransActNone; + decConf.confB.setInt = false; + /* Configure state 2 */ + LESENSE_DecoderStateConfig(&decConf, LCSENSE_STATE2); + + /* Change necessary structure fields for state 3 */ + decConf.confA.compVal = 0x00; + decConf.confA.nextState = LCSENSE_STATE0; + decConf.confA.prsAct = lesenseTransActUp; + decConf.confA.setInt = false; + decConf.confB.compVal = 0x03; + decConf.confB.nextState = LCSENSE_STATE2; + decConf.confB.prsAct = lesenseTransActNone; + decConf.confB.setInt = false; + /* Configure state 3 */ + LESENSE_DecoderStateConfig(&decConf, LCSENSE_STATE3); + + /* Set initial decoder state to 0 */ + LESENSE_DecoderStateSet(INITIAL_STATE); + + + LESENSE_DecoderStart(); + + // Start continuous scan + LESENSE_ScanStart(); +} + +/**************************************************************************//** + * @brief Sets up the PCNT + *****************************************************************************/ +void setupPCNT(void){ + /* PCNT configuration constant table. */ + static const PCNT_Init_TypeDef initPCNT ={ + .mode = pcntModeOvsSingle, /* Oversampling, single mode. */ + .counter = 0, /* Counter value has been initialized to 0. */ + .top = PCNT_TOP, /* Counter top value. */ + .negEdge = false, /* Use positive edge. */ + .countDown = false, /* Up-counting. */ + .filter = false, /* Filter disabled. */ + .hyst = false, /* Hysteresis disabled. */ + .s1CntDir = true, /* Counter direction is given by S1. */ + .cntEvent = pcntCntEventBoth, /* Regular counter counts up on upcount events. */ + .auxCntEvent = pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ + .s0PRS = pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ + .s1PRS = pcntPRSCh1 /* PRS channel 1 selected as S1IN. */ + }; + + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockEnable(cmuClock_PCNT0, true); + + /* Initialize PCNT. */ + PCNT_Init(PCNT0, &initPCNT); + + /* Enable PRS input S0 in PCNT. */ + PCNT_PRSInputEnable(PCNT0, pcntPRSInputS0, true); + + /* Enable PRS input S0 in PCNT. */ + PCNT_PRSInputEnable(PCNT0, pcntPRSInputS1, true); + + /* Clear all pending interrupts */ + PCNT_IntClear(PCNT0, 0xFFFF); + + /* Enable the PCNT overflow interrupt. */ + PCNT_IntEnable(PCNT0, PCNT_IEN_DIRCNG); + + /* Enable the PCNT vector in NVIC */ + NVIC_EnableIRQ(PCNT0_IRQn); +} + +/**************************************************************************//** + * @brief Sets up the PRS + *****************************************************************************/ +void setupPRS(void){ + CMU_ClockEnable(cmuClock_PRS, true); + /* PRS channel 0 configuration. */ + PRS_SourceAsyncSignalSet(PRS_CHANNEL0, PRS_CH_CTRL_SOURCESEL_LESENSED, PRS_CH_CTRL_SIGSEL_LESENSEDEC0); + /* PRS channel 0 configuration. */ + PRS_SourceAsyncSignalSet(PRS_CHANNEL1, PRS_CH_CTRL_SOURCESEL_LESENSED, PRS_CH_CTRL_SIGSEL_LESENSEDEC1); +} +#endif + +void lesenseObjectInit(LESENSEDriver* lesensep) { + + /* + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; + */ + + //CMU->LESENSEHFCLKCTRL_SET = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; + //CMU->LESENSEHFCLKCTRL_SET = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; + + initVdac(); + + //setupACMP(); + + //setupPCNT(); + + //setupPRS(); + + //setupLESENSE(); +} \ No newline at end of file diff --git a/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/source/lesense.h b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/source/lesense.h new file mode 100644 index 0000000000..9314c09ab0 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23A010F256-BRD4001A-REVA01/source/lesense.h @@ -0,0 +1,20 @@ +#ifndef HAL_LESENSE_LLD_H +#define HAL_LESENSE_LLD_H + +struct LESENSEDriver { +}; + +typedef struct LESENSEDriver LESENSEDriver; + +#ifdef __cplusplus +extern "C" { +#endif + + void lesenseInit(void); + void lesenseObjectInit(LESENSEDriver *lesensep); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LESENSE_LLD_H */ diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/Makefile b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/Makefile new file mode 100644 index 0000000000..a47e9503d7 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/Makefile @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +# SL_TRUSTZONE_NONSECURE and SYSTEM_NO_STATIC_MEMORY are only for emlib. +UDEFS = -DEFR32FG23B010F512IM48=1 \ + -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/chconf.h b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/chconf.h new file mode 100644 index 0000000000..1ac166f563 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/halconf.h b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/halconf.h new file mode 100644 index 0000000000..caf84a87f3 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/halconf.h @@ -0,0 +1,553 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC TRUE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/halconf_community.h b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/halconf_community.h new file mode 100644 index 0000000000..43fdbf8690 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/halconf_community.h @@ -0,0 +1,173 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/mcuconf.h b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/mcuconf.h new file mode 100644 index 0000000000..f1ce06596d --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/cfg/mcuconf.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_LFXO + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 FALSE +#define EFR32_SIO_USE_EUSART2 FALSE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/main.c b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/main.c new file mode 100644 index 0000000000..11a88a9ff8 --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/main.c @@ -0,0 +1,47 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "cmsis_os.h" +#include "hal.h" + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + osDelay(1000); + } +} diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/post-build.mk b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/readme.txt b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/readme.txt new file mode 100644 index 0000000000..e7759afbca --- /dev/null +++ b/demos/SILABS/RT-EFR32FG23B010F512-DK2600A/readme.txt @@ -0,0 +1,16 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M33 EFR32FG23. ** +***************************************************************************** + +** TARGET ** + +The demo runs on a DK2600A equipped with EFR32FG23B010F512IM48. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Silicon Labs and are licensed under a different license. Also note that not +all the files present in the emlib library are distributed with ChibiOS/RT, +you can find the whole library on the Silicon Labs web site: + + https://www.silabs.com diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/Makefile b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/Makefile new file mode 100644 index 0000000000..9ab19521f3 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/Makefile @@ -0,0 +1,199 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = -I$(CHIBIOS_CONTRIB)/os/various/devices_lib/ethernet +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +USER_CONTRIB := $(CHIBIOS)/../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep +USE_LWIP := yes + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk +# User application +include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +include $(CHIBIOS_CONTRIB)/os/various/anjay_bindings/anjay.mk +include $(CHIBIOS_CONTRIB)/os/various/mbedtls_bindings/mbedtls.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32L476xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c \ + avs_test_task.c \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS_CONTRIB)/os/various/devices_lib/ethernet/w5500_lld.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) $(CHIBIOS_CONTRIB)/os/various + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/avs_test_task.c b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/avs_test_task.c new file mode 100644 index 0000000000..6ada9dcc85 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/avs_test_task.c @@ -0,0 +1,871 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "cmsis_os.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "avs_test_task.h" + +#define CUSTOM_CONTENT_TYPE 72 + +static const char *dst_ip_addr; +static const char *dst_port_coap_udp; +static const char *dst_coap_udp_ssl; +static const char *dst_coap_tcp; +static const char *dst_coap_tcp_ssl; + +static const char *psk_identity; +static const uint8_t *psk_key; +static size_t psk_key_size; + + +#if defined(AVS_COMMONS_WITH_AVS_STREAM) && defined(WITH_AVS_COAP_STREAMING_API) + +static int avs_buffer_writer(struct avs_stream_struct *out_stream, void *arg) { + avs_payload_buffer_t *buf = arg; + + avs_error_t err = avs_stream_write(out_stream, buf->buffer, buf->length); + + if (avs_is_err(err)) + return -1; + + return 0; +} + +static void anjay_streaming_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + const avs_net_socket_configuration_t sock_cfg = { + .reuse_addr = 0, + .address_family = AVS_NET_AF_INET4, + .forced_mtu = 512, + .preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_udp_socket_create(&sock, &sock_cfg); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_port_coap_udp); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_response_header_t response; + avs_stream_t *out_response_stream = NULL; + + err = avs_coap_streaming_send_request(udp_ctx, &request, &avs_buffer_writer, &payload, &response, + &out_response_stream); + + if (!avs_is_err(err)) { + goto err; + } + + uint8_t buf[128]; + size_t bytes_read; + + if (out_response_stream) { + for (bool finished = false; !finished;) { + //avs_coap_streaming_handle_incoming_packet(avs_coap_ctx_t *coap_ctx, avs_coap_streaming_request_handler_t *handle_request, void *handler_arg); + err = avs_stream_read(out_response_stream, &bytes_read, &finished, buf, sizeof(buf)); + + if (!avs_is_err(err)) { + break; + } + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} +#endif + +static int avs_payload_writer(size_t payload_offset, + void *payload_buf, + size_t payload_buf_size, + size_t *out_payload_chunk_size, + void *arg) { + (void)payload_offset; + + avs_payload_buffer_t *buf = arg; + + size_t payload_bytes = AVS_MIN(buf->length, payload_buf_size); + + memcpy(payload_buf, buf->buffer, payload_bytes); + + + *out_payload_chunk_size = payload_bytes; + + return 0; +} + +static void avs_payload_reader(avs_coap_ctx_t *ctx, + avs_coap_exchange_id_t exchange_id, + avs_coap_client_request_state_t result, + const avs_coap_client_async_response_t *response, + avs_error_t err, + void *finished_) { + (void)ctx; + (void)exchange_id; + (void)result; + (void)response; + (void)err; + + *(bool *)finished_ = true; +} + +static int avs_request_handler(avs_coap_server_ctx_t *ctx, const avs_coap_request_header_t *request, + void *arg) { + + (void)ctx; + (void)request; + (void)arg; + + return 0; +} + +static void anjay_async_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + const avs_net_socket_configuration_t sock_cfg = { + .reuse_addr = 0, + .address_family = AVS_NET_AF_INET4, + .forced_mtu = 512, + .preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_udp_socket_create(&sock, &sock_cfg); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_port_coap_udp); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(udp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(udp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} + +#if defined(WITH_AVS_COAP_TCP) +static void anjay_async_tcp_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_time_duration_t request_timeout = { }; // = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT; + avs_coap_ctx_t *tcp_ctx = avs_coap_tcp_ctx_create(sched, in_buffer, out_buffer, 10, request_timeout, + prng); + + if (!tcp_ctx) { + goto err; + } + + const avs_net_socket_configuration_t sock_cfg = { + .reuse_addr = 0, + .address_family = AVS_NET_AF_INET4, + .forced_mtu = 512, + .preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_tcp_socket_create(&sock, &sock_cfg); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_coap_tcp); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(tcp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(tcp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(tcp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&tcp_ctx); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} +#endif + +static void ssl_psk_anjay_async_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + avs_net_ssl_configuration_t config = { + .version = AVS_NET_SSL_VERSION_DEFAULT, + .security = avs_net_security_info_from_psk((avs_net_psk_info_t) { + .key = avs_crypto_psk_key_info_from_buffer(psk_key, psk_key_size), + .identity = avs_crypto_psk_identity_info_from_buffer(psk_identity, strlen(psk_identity)), + }), + .ciphersuites = { + //.ids = default_ciphersuites, + //.num_ids = default_ciphersuites_num + }, + .prng_ctx = prng, + + .backend_configuration.reuse_addr = 0, + .backend_configuration.address_family = AVS_NET_AF_INET4, + .backend_configuration.forced_mtu = 512, + .backend_configuration.preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_dtls_socket_create(&sock, &config); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_coap_udp_ssl); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(udp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(udp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + //avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} + +static const char *ca_cert = R"()"; +static const char *client_cert = R"()"; +static const char *client_key = R"()"; + +static void ssl_x509_anjay_async_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + const avs_net_ssl_configuration_t config = { + .version = AVS_NET_SSL_VERSION_DEFAULT, + .security = avs_net_security_info_from_certificates((avs_net_certificate_info_t) { + .server_cert_validation = true, + .trusted_certs = avs_crypto_certificate_chain_info_from_buffer(ca_cert, strlen(ca_cert)), + .client_cert = avs_crypto_certificate_chain_info_from_buffer(client_cert, strlen(client_cert)), + .client_key = avs_crypto_private_key_info_from_buffer(client_key, strlen(client_key), NULL) + }), + .ciphersuites = { + //.ids = default_ciphersuites, + //.num_ids = default_ciphersuites_num + }, + .prng_ctx = prng, + + .backend_configuration.reuse_addr = 0, + .backend_configuration.address_family = AVS_NET_AF_INET4, + .backend_configuration.forced_mtu = 512, + .backend_configuration.preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_dtls_socket_create(&sock, &config); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_coap_udp_ssl); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(udp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(udp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + //avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} + +static void avsTestTask(const void *arg) { + (void)arg; + + avs_heap_init(); + + //anjay_async_tcp_test(); + //anjay_streaming_test(); + //anjay_async_test(); + //ssl_psk_anjay_async_test(); + //ssl_x509_anjay_async_test(); + + while (true) { + osDelay(1000); + ssl_psk_anjay_async_test(); + avs_heap_get_free(); + + osDelay(1000); + anjay_async_test(); + avs_heap_get_free(); + } +} + +void avsTestInit(const avs_test_opts_t *avs_test_opts) { + static osThreadDef(avsTestTask, osPriorityNormal, 4u * 1024u, "avs_test_task"); + + dst_ip_addr = avs_test_opts->dst_ip_addr; + dst_port_coap_udp = avs_test_opts->dst_port_coap_udp; + dst_coap_udp_ssl = avs_test_opts->dst_coap_udp_ssl; + dst_coap_tcp = avs_test_opts->dst_coap_tcp; + dst_coap_tcp_ssl = avs_test_opts->dst_coap_tcp_ssl; + + psk_identity = avs_test_opts->psk_identity; + psk_key = avs_test_opts->psk_key; + psk_key_size = avs_test_opts->psk_key_size; + + osThreadCreate(osThread(avsTestTask), NULL); +} diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/avs_test_task.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/avs_test_task.h new file mode 100644 index 0000000000..329c9f0220 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/avs_test_task.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef AVS_TEST_TASK_H +#define AVS_TEST_TASK_H + +typedef struct { + const char *dst_ip_addr; + const char *dst_port_coap_udp; + const char *dst_coap_udp_ssl; + const char *dst_coap_tcp; + const char *dst_coap_tcp_ssl; + + const char *psk_identity; + const uint8_t *psk_key; + size_t psk_key_size; +} avs_test_opts_t; + +typedef struct { + uint8_t *buffer; + size_t length; +} avs_payload_buffer_t; + +void avsTestInit(const avs_test_opts_t *avs_test_opts); + +#endif /* AVS_TEST_TASK_H */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/anjay/anjay_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/anjay/anjay_config.h new file mode 100644 index 0000000000..c41af6f6d4 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/anjay/anjay_config.h @@ -0,0 +1,650 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * All rights reserved. + * + * Licensed under the AVSystem-5-clause License. + * See the attached LICENSE file for details. + */ + +#ifndef ANJAY_CONFIG_H +#define ANJAY_CONFIG_H + +/** + * @file anjay_config.h + * + * Anjay library configuration. + * + * The preferred way to compile Anjay is to use CMake, in which case this file + * will be generated automatically by CMake. + * + * However, to provide compatibility with various build systems used especially + * by embedded platforms, it is alternatively supported to compile Anjay by + * other means, in which case this file will need to be provided manually. + * + * NOTE: To compile this library without using CMake, you need to + * configure avs_commons and avs_coap first. Please refer to documentation in + * the avs_commons_config.h and avs_coap_config.h files (provided + * in the repositories as avs_commons_config.h.in and + * avs_coap_config.h.in, respectively) for details. + * + * Anjay requires the following avs_coap options to be enabled: + * + * - @c WITH_AVS_COAP_UDP + * - @c WITH_AVS_COAP_STREAMING_API + * - @c WITH_AVS_COAP_BLOCK is highly recommended + * - @c WITH_AVS_COAP_OBSERVE (if @c ANJAY_WITH_OBSERVE is enabled) + * - @c WITH_AVS_COAP_OSCORE (if @c ANJAY_WITH_COAP_OSCORE is enabled, available + * only as a commercial feature) + * + * Anjay requires the following avs_commons components to be + * enabled: + * + * - All components required by avs_coap, see avs_coap_config.h + * - @c avs_algorithm + * - @c avs_stream + * - @c avs_url + * - @c avs_persistence is highly recommended + * - @c avs_http (if @c ANJAY_WITH_HTTP_DOWNLOAD is enabled) + * - @c avs_rbtree (if @c ANJAY_WITH_OBSERVE or + * @c ANJAY_WITH_MODULE_ACCESS_CONTROL is enabled) + * + * In the repository, this file is provided as anjay_config.h.in, + * intended to be processed by CMake. If editing this file manually, please copy + * or rename it to anjay_config.h and for each of the + * \#cmakedefine directives, please either replace it with regular + * \#define to enable it, or comment it out to disable. You may also need + * to replace variables wrapped in \@ signs with concrete values. Please + * refer to the comments above each of the specific definition for details. + * + * If you are editing a file previously generated by CMake, these + * \#cmakedefines will be already replaced by either \#define or + * commented out \#undef directives. + */ + +/** + * Enable logging in Anjay. + * + * If this flag is disabled, no logging is compiled into the binary at all. + */ +/* #define ANJAY_WITH_LOGS */ + +/** + * Enable TRACE-level logs in Anjay. + * + * Only meaningful if ANJAY_WITH_LOGS is enabled. + */ +/* #undef ANJAY_WITH_TRACE_LOGS */ + +/** + * Enable core support for Access Control mechanisms. + * + * Requires separate implementation of the Access Control object itself. + * Either the implementation available as part of + * ANJAY_WITH_MODULE_ACCESS_CONTROL, or a custom application-provided one + * may be used. + */ +/* #undef ANJAY_WITH_ACCESS_CONTROL */ + +/** + * Enable automatic attribute storage. + * + * Requires AVS_COMMONS_WITH_AVS_PERSISTENCE to be enabled in avs_commons + * configuration. + */ +/* #define ANJAY_WITH_ATTR_STORAGE */ + +/** + * Enable support for the anjay_download() API. + */ +/* #define ANJAY_WITH_DOWNLOADER */ + +/** + * Enable support for CoAP(S) downloads. + * + * Only meaningful if ANJAY_WITH_DOWNLOADER is enabled. + */ +/* #define ANJAY_WITH_COAP_DOWNLOAD */ + +/** + * Enable support for HTTP(S) downloads. + * + * Only meaningful if ANJAY_WITH_DOWNLOADER is enabled. + */ +/* #undef ANJAY_WITH_HTTP_DOWNLOAD */ + +/** + * Enable support for the LwM2M Bootstrap Interface. + */ +/* #define ANJAY_WITH_BOOTSTRAP */ + +/** + * Enable support for the LwM2M Discover operation. + * + * Note that it is required for full compliance with the LwM2M protocol. + */ +/* #define ANJAY_WITH_DISCOVER */ + +/** + * Enable support for the LwM2M Information Reporting interface (Observe and + * Notify operations). + * + * Requires WITH_AVS_COAP_OBSERVE to be enabled in avs_coap + * configuration. + * + * Note that it is required for full compliance with the LwM2M protocol. + */ +/* #define ANJAY_WITH_OBSERVE */ + +/** + * Enable support for measuring amount of LwM2M traffic + * (anjay_get_tx_bytes(), anjay_get_rx_bytes(), + * anjay_get_num_incoming_retransmissions() and + * anjay_get_num_outgoing_retransmissions() APIs. + */ +/* #undef ANJAY_WITH_NET_STATS */ + +/** + * Enable support for communication timestamp + * (anjay_get_server_last_registration_time() + * anjay_get_server_next_update_time() and + * anjay_get_server_last_communication_time()) APIs. + */ +/* #undef ANJAY_WITH_COMMUNICATION_TIMESTAMP_API */ + +/** + * Enable support for the anjay_resource_observation_status() API. + */ +/* #define ANJAY_WITH_OBSERVATION_STATUS */ + +/** + * Maximum number of servers observing a given Resource listed by + * anjay_resource_observation_status() function. + * + * Only meaningful if ANJAY_WITH_OBSERVATION_STATUS is enabled. + */ +/* #define ANJAY_MAX_OBSERVATION_SERVERS_REPORTED_NUMBER 0 */ + +/** + * Enable guarding of all accesses to anjay_t with a mutex. + */ +/* #undef ANJAY_WITH_THREAD_SAFETY */ + +/** + * Enable standard implementation of an event loop. + * + * Requires C11 stdatomic.h header to be available, and either a platform + * that provides a BSD-compatible socket API, or a compatibility layer file (see + * AVS_COMMONS_POSIX_COMPAT_HEADER in avs_commons_config.h). This + * is designed to best work with the defalt implementation of avs_net sockets + * (see AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET), but alternative socket + * implementations can also be used. + * + * The event loop is most useful when thread safety features + * (@ref ANJAY_WITH_THREAD_SAFETY and AVS_COMMONS_SCHED_THREAD_SAFE) are + * enabled as well, but this is not a hard requirement. See the documentation + * for anjay_event_loop_run() for details. + */ +/* #define ANJAY_WITH_EVENT_LOOP */ + +/** + * Enable support for features new to LwM2M protocol version 1.1. + */ +/* #define ANJAY_WITH_LWM2M11 */ + +/** + * Enable support for OSCORE-based security for LwM2M connections. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled, and + * WITH_AVS_COAP_OSCORE to be enabled in avs_coap configuration. + * + * IMPORTANT: Only available as part of the OSCORE commercial feature. Ignored + * in the open source version. + */ +/* #undef ANJAY_WITH_COAP_OSCORE */ + +/** + * Enable support for the LwM2M Send operation. + * + * Requires ANJAY_WITH_LWM2M11 and either ANJAY_WITH_SENML_JSON or + * ANJAY_WITH_CBOR to be enabled. + */ +/* #undef ANJAY_WITH_SEND */ + +/** + * Enable support for the SMS binding and the SMS trigger mechanism. + * + * Requires WITH_AVS_COAP_UDP to be enabled in avs_coap configuration. + * + * IMPORTANT: Only available as part of the SMS commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_SMS */ + +/** + * Enable support for sending and receiving multipart SMS messages. + * + * Requires ANJAY_WITH_SMS to be enabled. + * + * IMPORTANT: Only available as part of the SMS commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_SMS_MULTIPART */ + +/** + * Enable support for Non-IP Data Delivery. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled, and + * WITH_AVS_COAP_UDP to be enabled in avs_coap configuration. + * + * IMPORTANT: Only available as a commercial feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_NIDD */ + +/** + * Enable support for core state persistence + * (anjay_new_from_core_persistence() and + * anjay_delete_with_core_persistence() APIs). + * + * Requires ANJAY_WITH_OBSERVE to be enabled, + * AVS_COMMONS_WITH_AVS_PERSISTENCE to be enabled in avs_commons, and + * WITH_AVS_COAP_OBSERVE_PERSISTENCE to be enabled in avs_coap + * configuration. + * + * IMPORTANT: Only available as a commercial feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_CORE_PERSISTENCE */ + +/** + * Disable automatic closing of server connection sockets after + * MAX_TRANSMIT_WAIT of inactivity. + */ +/* #undef ANJAY_WITHOUT_QUEUE_MODE_AUTOCLOSE */ + +/** + * Enable support for CoAP Content-Format numerical values 1541-1544 that have + * been used before final LwM2M TS 1.0. + */ +/* #undef ANJAY_WITH_LEGACY_CONTENT_FORMAT_SUPPORT */ + +/** + * Enable support for JSON format as specified in LwM2M TS 1.0. + * + * NOTE: Anjay is only capable of generating this format, there is no parsing + * support regardless of the state of this option. + */ +/* #undef ANJAY_WITH_LWM2M_JSON */ + +/** + * Disable support for TLV format as specified in LwM2M TS 1.0. + * + * NOTE: LwM2M Client using LwM2M 1.0 MUST support this format. It may be + * disabled if LwM2M 1.1 is used and SenML JSON or SenML CBOR is enabled. + */ +/* #undef ANJAY_WITHOUT_TLV */ + +/** + * Disable support for Plain Text format as specified in LwM2M TS 1.0 and 1.1. + * + * NOTE: LwM2M Client SHOULD support this format. It may be disabled to reduce + * library size if LwM2M Server is configured to not use it in requests. + */ +/* #undef ANJAY_WITHOUT_PLAINTEXT */ + +/** + * Disable use of the Deregister message. + */ +/* #undef ANJAY_WITHOUT_DEREGISTER */ + +/** + * Disable support for "IP stickiness", i.e. preference of the same IP address + * when reconnecting to a server using a domain name. + */ +#define ANJAY_WITHOUT_IP_STICKINESS + +/** + * Enable support for SenML JSON format, as specified in LwM2M TS 1.1. + * + * NOTE: As opposed to ANJAY_WITH_LWM2M_JSON, both generating and parsing + * is supported. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled. + */ +/* #undef ANJAY_WITH_SENML_JSON */ + +/** + * Enable support for CBOR and SenML CBOR formats, as specified in LwM2M TS 1.1. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled. + */ +/* #undef ANJAY_WITH_CBOR */ + +/** + * Enable support for Enrollment over Secure Transport. + * + * Requires ANJAY_WITH_BOOTSTRAP to be enabled. + * + * IMPORTANT: Only available as part of the EST commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_EST */ + +/** + * Enable support for hardware security engine in the EST subsystem. + * + * Requires ANJAY_WITH_EST to be enabled in Anjay configuration and + * AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE to be enabled in avs_commons + * configuration. + * + * IMPORTANT: Only available in commercial versions that include both the EST + * and HSM features. Ignored in versions distributed without these features. + */ +/* #undef ANJAY_WITH_EST_ENGINE_SUPPORT */ + +/** + * Enable support for the Confirmable Notification attribute, as specified in + * LwM2M TS 1.2. + * + * Before TS 1.2, this has been supported in Anjay as a custom extension, and + * thus it is available independently from TS 1.2 support itself, including in + * the open source version. + * + * Requires ANJAY_WITH_OBSERVE to be enabled. + */ +/* #undef ANJAY_WITH_CON_ATTR */ + +/** + * Enable support for handling security credentials in the data model using + * structured avs_crypto types. + * + * If the security module is also enabled (see @ref + * ANJAY_WITH_MODULE_SECURITY), it also enables support for passing these + * credentials through such structured types when adding Security object + * instances via the @ref anjay_security_instance_t structure. + */ +/* #undef ANJAY_WITH_SECURITY_STRUCTURED */ + +/** + * Maximum size in bytes supported for the "Public Key or Identity" resource in + * the LwM2M Security object. + * + * If editing this file manually, 256 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 2048. + * Minimal suggested setting for low-resource builds is 256. + */ +#define ANJAY_MAX_PK_OR_IDENTITY_SIZE 256 + +/** + * Maximum size in bytes supported for the "Secret Key" resource in the LwM2M + * Security Object. + * + * If editing this file manually, 128 shall be replaced + * with a positive integer literal. + * + * The default value defined in CMake build scripts is 256. + * Minimal suggested setting for low-resource builds is 128. + */ +#define ANJAY_MAX_SECRET_KEY_SIZE 128 + +/** + * Maximum length supported for stringified floating-point values. + * + * Used when parsing plaintext and SenML JSON content formats - when parsing a + * floating-point value, any string of length equal or greater than this setting + * will automatically be considered invalid, even if it could in theory be + * parsed as a valid number. + * + * If editing this file manually, 64 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 512. + * Minimal suggested setting for low-resource builds is 64. + */ +#define ANJAY_MAX_DOUBLE_STRING_SIZE 64 + +/** + * Maximum length supported for a single Uri-Path or Location-Path segment. + * + * When handling incoming CoAP messages, any Uri-Path or Location-Path option of + * length equal or greater than this setting will be considered invalid. + * + * If editing this file manually, 64 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 256. + * Minimal suggested setting for low-resource builds is 64. + */ +#define ANJAY_MAX_URI_SEGMENT_SIZE 64 + +/** + * Maximum length supported for a single Uri-Query segment. + * + * When handling incoming CoAP messages, any Uri-Query option of length equal or + * greater than this setting will be considered invalid. + * + * If editing this file manually, 64 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 256. + * Minimal suggested setting for low-resource builds is 64. + */ +#define ANJAY_MAX_URI_QUERY_SEGMENT_SIZE 64 + +/** + * Size of buffer allocated for storing DTLS session state when connection is + * not in use (e.g. during queue mode operation). + * + * If editing this file manually, 1024 shall be + * replaced with a positive integer literal. The default value defined in CMake + * build scripts is 1024. + */ +#define ANJAY_DTLS_SESSION_BUFFER_SIZE 1024 + +/** + * Value of Content-Format used in Send messages. Only a few specific values are + * supported: + * + * - @c AVS_COAP_FORMAT_NONE means no default value is used and Anjay will + * decide the format based on the what is available. + * - @c AVS_COAP_FORMAT_OMA_LWM2M_CBOR Anjay will generate a Send message in + * LwM2M CBOR format. + * - @c AVS_COAP_FORMAT_SENML_CBOR Anjay will generate a Send message in SenML + * CBOR format. + * - @c AVS_COAP_FORMAT_SENML_JSON Anjay will generate a Send message in SenML + * JSON format. + * + * Note that to use a specific format it must be available during compilation. + * + * The default value defined in CMake build scripts is + * AVS_COAP_FORMAT_NONE. + */ +#define ANJAY_DEFAULT_SEND_FORMAT AVS_COAP_FORMAT_NONE + +/** + * Optional Anjay modules. + */ +/**@{*/ +/** + * Enable access_control module (implementation of the Access Control object). + * + * Requires ANJAY_WITH_ACCESS_CONTROL to be enabled. + */ +/* #undef ANJAY_WITH_MODULE_ACCESS_CONTROL */ + +/** + * Enable security module (implementation of the LwM2M Security object). + */ +/* #define ANJAY_WITH_MODULE_SECURITY */ + +/** + * Enable support for hardware security engine in the security module. + * + * This feature allows security credentials provisioned into the LwM2M Security + * object to be automatically moved into a hardware security module. + * + * Requires ANJAY_WITH_MODULE_SECURITY to be enabled in Anjay + * configuration, and at least one of + * AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE or + * AVS_COMMONS_WITH_AVS_CRYPTO_PSK_ENGINE to be enabled in avs_commons + * configuration. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in versions distributed without this feature. + */ +/* #undef ANJAY_WITH_MODULE_SECURITY_ENGINE_SUPPORT */ + +/** + * Enable server module (implementation of the LwM2M Server object). + */ +/* #define ANJAY_WITH_MODULE_SERVER */ + +/** + * Enable fw_update module (implementation of the Firmware Update object). + */ +/* #define ANJAY_WITH_MODULE_FW_UPDATE */ + +/** + * Enable advanced_fw_update module (implementation of the 33629 custom + * Advanced Firmware Update object). + */ +/* #undef ANJAY_WITH_MODULE_ADVANCED_FW_UPDATE */ + +/** + * Disable support for PUSH mode Firmware Update. + * + * Only meaningful if ANJAY_WITH_MODULE_FW_UPDATE is enabled. Requires + * ANJAY_WITH_DOWNLOADER to be enabled. + */ +/* #undef ANJAY_WITHOUT_MODULE_FW_UPDATE_PUSH_MODE */ + +/** + * Enables ipso_objects module (generic implementation of the following kinds of + * the basic sensor and three axis sensor IPSO objects). + */ +/* #define ANJAY_WITH_MODULE_IPSO_OBJECTS */ + +/** + * Enable at_sms module (implementation of an SMS driver for AT modem devices). + * + * Requires ANJAY_WITH_SMS to be enabled and the operating system to + * support the POSIX poll() function. + * + * IMPORTANT: Only available as part of the SMS commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_MODULE_AT_SMS */ + +/** + * Enable bg96_nidd module (implementation of NB-IoT-based NIDD driver for + * Quectel BG96). + * + * Requires ANJAY_WITH_NIDD to be enabled. + * + * IMPORTANT: Only available as part of the NIDD commercial feature. Ignored + * in the open source version. + */ +/* #undef ANJAY_WITH_MODULE_BG96_NIDD */ + +/** + * Enable bootstrapper module (loader for bootstrap information formatted as per + * the "Storage of LwM2M Bootstrap Information on the Smartcard" appendix to the + * LwM2M TS). + * + * Requires ANJAY_WITH_BOOTSTRAP to be enabled and + * AVS_COMMONS_WITH_AVS_PERSISTENCE to be enabled in avs_commons + * configuration. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_MODULE_BOOTSTRAPPER */ + +/** + * Enable the SIM bootstrap module, which enables reading the SIM bootstrap + * information from a smartcard, which can then be passed through to the + * bootstrapper module. + * + * Requires ANJAY_WITH_MODULE_BOOTSTRAPPER to be enabled. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_MODULE_SIM_BOOTSTRAP */ + +/** + * Forced ID of the file to read the SIM bootstrap information from. + * + * If not defined (default), the bootstrap information file will be discovered + * through the ODF file, as mandated by the specification. + * + * Requires ANJAY_WITH_MODULE_BOOTSTRAPPER to be enabled. At most one of + * ANJAY_MODULE_SIM_BOOTSTRAP_HARDCODED_FILE_ID and + * ANJAY_MODULE_SIM_BOOTSTRAP_DATA_OID_OVERRIDE_HEX may be defined at the + * same time. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_MODULE_SIM_BOOTSTRAP_HARDCODED_FILE_ID */ + +/** + * Overridden OID of the SIM bootstrap information to look for in the DODF file, + * expressed as a hexlified DER representation (without the header). + * + * This is the hexlified expected value of the 'id' field within the 'OidDO' + * sequence in the DODF file (please refer to the PKCS #15 document for more + * information). + * + * If not defined, the default value of "672b0901", which corresponds to + * OID 2.23.43.9.1 {joint-iso-itu-t(2) international-organizations(23) wap(43) + * oma-lwm2m(9) lwm2m-bootstrap(1)}, will be used. + * + * No other values than the default are valid according to the specification, + * but some SIM cards are known to use other non-standard values, e.g. + * "0604672b0901" - including a superfluous nested BER-TLV header, as + * erroneously illustrated in the EF(DODF-bootstrap) file coding example in + * LwM2M TS 1.2 and earlier (fixed in LwM2M TS 1.2.1) - which is interpreted as + * OID 0.6.4.103.43.9.1 (note that it is invalid as the 0.6 tree does not exist + * in the repository as of writing this note). + * + * Requires ANJAY_WITH_MODULE_BOOTSTRAPPER to be enabled. At most one of + * ANJAY_MODULE_SIM_BOOTSTRAP_HARDCODED_FILE_ID and + * ANJAY_MODULE_SIM_BOOTSTRAP_DATA_OID_OVERRIDE_HEX may be defined at the + * same time. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_MODULE_SIM_BOOTSTRAP_DATA_OID_OVERRIDE_HEX */ + +/** + * Enable factory provisioning module. Data provided during provisioning uses + * SenML CBOR format. + */ +/* #undef ANJAY_WITH_MODULE_FACTORY_PROVISIONING */ + +/** + * Enable oscore module (implementation of the OSCORE object). + * + * IMPORTANT: Only available as part of the OSCORE commercial feature. Ignored + * in the open source version. + */ +/* #undef ANJAY_WITH_MODULE_OSCORE */ +/**@}*/ + +#endif // ANJAY_CONFIG_H diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/coap/avs_coap_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/coap/avs_coap_config.h new file mode 100644 index 0000000000..901d29171a --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/coap/avs_coap_config.h @@ -0,0 +1,171 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Licensed under the AVSystem-5-clause License. + * See the attached LICENSE file for details. + */ + +#ifndef AVS_COAP_CONFIG_H +#define AVS_COAP_CONFIG_H + +/** + * @file avs_coap_config.h + * + * avs_coap library configuration. + * + * The preferred way to compile avs_coap is to use CMake, in which case this + * file will be generated automatically by CMake. + * + * However, to provide compatibility with various build systems used especially + * by embedded platforms, it is alternatively supported to compile avs_coap by + * other means, in which case this file will need to be provided manually. + * + * NOTE: To compile this library without using CMake, you need to + * configure avs_commons first. Please refer to documentation in the + * avs_commons_config.h file (provided in the repository as + * avs_commons_config.h.in) for details. + * + * avs_coap requires the following avs_commons components to be + * enabled: + * + * - @c avs_buffer + * - @c avs_compat_threading + * - @c avs_list + * - @c avs_net + * - @c avs_sched + * - @c avs_stream + * - @c avs_utils + * - @c avs_log (if @c WITH_AVS_COAP_LOGS is enabled) + * - @c avs_persistence (if @c WITH_AVS_COAP_OBSERVE_PERSISTENCE is enabled) + * - @c avs_crypto (if @c WITH_AVS_COAP_OSCORE is enabled) + * + * In the repository, this file is provided as avs_coap_config.h.in, + * intended to be processed by CMake. If editing this file manually, please copy + * or rename it to avs_coap_config.h and for each of the + * \#cmakedefine directives, please either replace it with regular + * \#define to enable it, or comment it out to disable. You may also need + * to replace variables wrapped in \@ signs with concrete values. Please + * refer to the comments above each of the specific definition for details. + * + * If you are editing a file previously generated by CMake, these + * \#cmakedefines will be already replaced by either \#define or + * commented out \#undef directives. + */ + +/** + * Enable support for block-wise transfers (RFC 7959). + * + * If this flag is disabled, attempting to send a message bigger than the + * internal buffer will fail; incoming messages may still carry BLOCK1 or BLOCK2 + * options, but they will not be interpreted by the library in any way. + */ +#define WITH_AVS_COAP_BLOCK + +/** + * Enable support for observations (RFC 7641). + */ +/* #define WITH_AVS_COAP_OBSERVE */ + +/** + * Enable support for observation persistence (avs_coap_observe_persist() + * and avs_coap_observe_restore() calls). + * + * Only meaningful WITH_AVS_COAP_OBSERVE is enabled. + */ +/* #undef WITH_AVS_COAP_OBSERVE_PERSISTENCE */ + +/** + * Enable support for the streaming API + */ +/* #define WITH_AVS_COAP_STREAMING_API */ + +/** + * Enable support for UDP transport. + * + * NOTE: Enabling at least one transport is necessary for the library to be + * useful. + */ +#define WITH_AVS_COAP_UDP + +/** + * Enable support for TCP transport (RFC 8323). + * + * NOTE: Enabling at least one transport is necessary for the library to be + * useful. + */ +/* #define WITH_AVS_COAP_TCP */ + +/** + * Enable support for OSCORE (RFC 8613). + * + * IMPORTANT: Only available with the OSCORE feature. Ignored in the open + * source version. + */ +/* #undef WITH_AVS_COAP_OSCORE */ + +/** + * Use OSCORE version from draft-ietf-core-object-security-08 instead of the + * final version (RFC 8613). + * + * Only meaningful if WITH_AVS_COAP_OSCORE is enabled. + * + * IMPORTANT: Only available with the OSCORE feature. Ignored in the open + * source version. + */ +/* #undef WITH_AVS_COAP_OSCORE_DRAFT_8 */ + +/** + * Maximum number of notification tokens stored to match Reset responses to. + * + * Only meaningful if WITH_AVS_COAP_OBSERVE and WITH_AVS_COAP_UDP + * are enabled. + * + * If editing this file manually, 4 shall be + * replaced with a positive integer literal. The default value defined in CMake + * build scripts is 4. + */ +#define AVS_COAP_UDP_NOTIFY_CACHE_SIZE 4 + +/** + * Enable sending diagnostic payload in error responses. + */ +/* #define WITH_AVS_COAP_DIAGNOSTIC_MESSAGES */ + +/** + * Enable logging in avs_coap. + * + * If this flag is disabled, no logging is compiled into the binary at all. + */ +/* #define WITH_AVS_COAP_LOGS */ + +/** + * Enable TRACE-level logs in avs_coap. + * + * Only meaningful if WITH_AVS_COAP_LOGS is enabled. + */ +/* #undef WITH_AVS_COAP_TRACE_LOGS */ + +/** + * Enable poisoning of unwanted symbols when compiling avs_coap. + * + * Requires a compiler that supports \#pragma GCC poison. + * + * This is mostly useful during development, to ensure that avs_commons do not + * attempt to call functions considered harmful in this library, such as printf. + * This is not guaranteed to work as intended on every platform. + */ +/* #undef WITH_AVS_COAP_POISONING */ + +#endif // AVS_COAP_CONFIG_H diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_commons_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_commons_config.h new file mode 100644 index 0000000000..bd33e0dccc --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_commons_config.h @@ -0,0 +1,861 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef AVS_COMMONS_CONFIG_H +#define AVS_COMMONS_CONFIG_H + +/** + * @file avs_commons_config.h + * + * avs_commons library configuration. + * + * The preferred way to compile avs_commons is to use CMake, in which case this + * file will be generated automatically by CMake. + * + * However, to provide compatibility with various build systems used especially + * by embedded platforms, it is alternatively supported to compile avs_commons + * by other means, in which case this file will need to be provided manually. + * + * In the repository, this file is provided as avs_commons_config.h.in, + * intended to be processed by CMake. If editing this file manually, please copy + * or rename it to avs_commons_config.h and for each of the + * #cmakedefine directives, please either replace it with regular + * #define to enable it, or comment it out to disable. You may also need + * to replace variables wrapped in @ signs with concrete values. Please + * refer to the comments above each of the specific definition for details. + * + * If you are editing a file previously generated by CMake, these + * #cmakedefines will be already replaced by either #define or + * commented out #undef directives. + */ + +/** + * Options that describe capabilities of the build environment. + * + * NOTE: If you leave some of these macros undefined, even though the given + * feature is actually available in the system, avs_commons will attempt to use + * its own substitutes, which may be incompatible with the definition in the + * system and lead to undefined behaviour. + */ +/**@{*/ +/** + * Is the target platform big-endian? + * + * If undefined, little-endian is assumed. Mixed-endian architectures are not + * supported. + * + * Affects avs_convert_be*() and avs_[hn]to[hn]*() calls in + * avs_utils and, by extension, avs_persistence. + */ +/* #undef AVS_COMMONS_BIG_ENDIAN */ + +/** + * Is GNU __builtin_add_overflow() extension available? + * + * Affects time handling functions in avs_utils. If disabled, software overflow + * checking will be compiled. Note that this software overflow checking code + * relies on U2 representation of signed integers. + */ +/* #undef AVS_COMMONS_HAVE_BUILTIN_ADD_OVERFLOW */ + +/** + * Is GNU __builtin_mul_overflow() extension available? + * + * Affects time handling functions in avs_utils. If disabled, software overflow + * checking will be compiled. Note that this software overflow checking code + * relies on U2 representation of signed integers. + */ +/* #undef AVS_COMMONS_HAVE_BUILTIN_MUL_OVERFLOW */ + +/** + * Is net/if.h available in the system? + * + * NOTE: If the header is indeed available, but this option is not defined, the + * IF_NAMESIZE macro will be defined publicly by avs_commons + * headers, which may conflict with system definitions. + */ +/* #undef AVS_COMMONS_HAVE_NET_IF_H */ + +/** + * Are GNU diagnostic pragmas (#pragma GCC diagnostic push/pop/ignored) + * available? + * + * If defined, those pragmas will be used to suppress compiler warnings for some + * code known to generate them and cannot be improved in a more robust way, e.g. + * for code that is known to generate warnings from within system headers. + */ +/* #undef AVS_COMMONS_HAVE_PRAGMA_DIAGNOSTIC */ + +/** + * Are GNU visibility pragmas (#pragma GCC visibility push/pop) available? + * + * Meaningful mostly if avs_commons will be directly or indirectly linked into + * a shared library. Causes all symbols except those declared in public headers + * to be hidden, i.e. not exported outside the shared library. If not defined, + * default compiler visibility settings will be used, but you still may use + * compiler flags and linker version scripts to replicate this manually if + * needed. + */ +/* #undef AVS_COMMONS_HAVE_VISIBILITY */ + +/** + * Specify an optional compatibility header that allows use of POSIX-specific + * code that is not compliant with POSIX enough to be compiled directly. + * + * This header, if specified, will be included only by the following components, + * which may be enabled or disabled depending on state of the referenced flags: + * - avs_compat_threading implementation based on POSIX Threads + * (@ref AVS_COMMONS_COMPAT_THREADING_WITH_PTHREAD) + * - default avs_net socket implementation + * (@ref AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET) + * - avs_unit (@ref AVS_COMMONS_WITH_AVS_UNIT) + * - default implementation of avs_time routines + * (@ref AVS_COMMONS_UTILS_WITH_POSIX_AVS_TIME) + * + * Compatibility headers for lwIP and Microsoft Windows are provided with the + * library (see the compat directory). + * + * If this macro is not defined, the afore-mentioned components, if enabled, + * will use system headers directly, assuming they are POSIX-compliant. + * + * If this macro is enabled, the specified file will be included through an + * #include AVS_COMMONS_POSIX_COMPAT_HEADER statement. Thus, if editing + * this file manually, avsystem/commons/lwip-posix-compat.h shall be + * replaced with a path to such file. + */ +#define AVS_COMMONS_POSIX_COMPAT_HEADER \ + "compat/lwip-posix-compat.h" + +/** + * Set if printf implementation doesn't support 64-bit format specifiers. + * If defined, custom implementation of conversion is used in + * @c AVS_UINT64_AS_STRING instead of using @c snprintf . + */ +#define AVS_COMMONS_WITHOUT_64BIT_FORMAT_SPECIFIERS + +/** + * Set if printf implementation doesn't support floating-point numbers. + * If defined, custom implementation of conversion is used in + * @c AVS_DOUBLE_AS_STRING instead of using @c snprintf . This might increase + * compatibility with some embedded libc implementations that do not provide + * this functionality. + * + * NOTE: In order to keep the custom implementation small in code size, it is + * not intended to be 100% accurate. Rounding errors may occur - according to + * empirical checks, they show up around the 16th significant decimal digit. + */ +#define AVS_COMMONS_WITHOUT_FLOAT_FORMAT_SPECIFIERS + +/**@}*/ + +/** + * Enable poisoning of unwanted symbols when compiling avs_commons. + * + * Requires a compiler that supports #pragma GCC poison. + * + * This is mostly useful during development, to ensure that avs_commons do not + * attempt to call functions considered harmful in this library, such as printf. + * This is not guaranteed to work as intended on every platform, e.g. on macOS + * it is known to generate false positives due to different dependencies between + * system headers. + */ +/* #undef AVS_COMMONS_WITH_POISONING */ + +/** + * Options that control compilation of avs_commons components. + * + * Each of the configuration options below enables, if defined, one of the core + * components of the avs_commons library. + * + * NOTE: Enabling avs_unit will cause an object file with an implementation of + * main() to be generated. + */ +/**@{*/ +/* #define AVS_COMMONS_WITH_AVS_ALGORITHM */ +#define AVS_COMMONS_WITH_AVS_BUFFER +#define AVS_COMMONS_WITH_AVS_COMPAT_THREADING +#define AVS_COMMONS_WITH_AVS_CRYPTO +/* #undef AVS_COMMONS_WITH_AVS_HTTP */ +#define AVS_COMMONS_WITH_AVS_LIST +/* #define AVS_COMMONS_WITH_AVS_LOG */ +#define AVS_COMMONS_WITH_AVS_NET +/* #define AVS_COMMONS_WITH_AVS_PERSISTENCE */ +/* #undef AVS_COMMONS_WITH_AVS_RBTREE */ +/* #define AVS_COMMONS_WITH_AVS_SORTED_SET */ +#define AVS_COMMONS_WITH_AVS_SCHED +/* #define AVS_COMMONS_WITH_AVS_STREAM */ +/* #undef AVS_COMMONS_WITH_AVS_UNIT */ +#define AVS_COMMONS_WITH_AVS_URL +#define AVS_COMMONS_WITH_AVS_UTILS +/* #undef AVS_COMMONS_WITH_AVS_VECTOR */ +/**@}*/ + +/** + * Options that control compilation of avs_compat_threading implementations. + * + * If CMake is not used, in the typical scenario at most one of the following + * implementations may be enabled at the same time. If none is enabled, the + * relevant symbols will need to be provided by the user, if used. + * + * These are meaningful only if AVS_COMMONS_WITH_AVS_COMPAT_THREADING is + * defined. + */ +/**@{*/ +/** + * Enable implementation based on spinlocks. + * + * This implementation is usually very inefficient, and requires C11 stdatomic.h + * header to be available. + */ +/* #undef AVS_COMMONS_COMPAT_THREADING_WITH_ATOMIC_SPINLOCK */ + +/** + * Enable implementation based on the POSIX Threads library. + * + * This implementation is preferred over the spinlock-based one, but the POSIX + * Threads library is normally available only in UNIX-like environments. + */ +/* #undef AVS_COMMONS_COMPAT_THREADING_WITH_PTHREAD */ + +/** + * Is the pthread_condattr_setclock() function available? + * + * This flag only makes sense when + * AVS_COMMONS_COMPAT_THREADING_WITH_PTHREAD is enabled. + * + * If this flag is disabled, or if CLOCK_MONOTONIC macro is not + * available, the avs_condvar_wait() will internally use the real-time + * clock instead of the monotonic clock. Time values will be converted so that + * this change does not affect API usage. + */ +/* #undef AVS_COMMONS_COMPAT_THREADING_PTHREAD_HAVE_PTHREAD_CONDATTR_SETCLOCK */ +/**@}*/ + +/** + * Options that control compilation of code depending on TLS backend library. + * + * If CMake is not used, in the typical scenario at most one of the following + * DTLS backends may be enabled at the same time. If none is enabled, + * functionalities that depends on cryptography will be disabled. + * + * Affects avs_crypto, avs_net, and avs_stream (for the MD5 implementation). + * + * mbed TLS is the main development backend, and is preferred as such. OpenSSL + * backend supports most functionality as well, but is not as thoroughly tested. + * TinyDTLS support is only rudimentary. + */ +/**@{*/ +#define AVS_COMMONS_WITH_MBEDTLS +/* #undef AVS_COMMONS_WITH_OPENSSL */ +/* #undef AVS_COMMONS_WITH_TINYDTLS */ + +/** + * Enable support for custom TLS socket implementation. + * + * If enabled, the user needs to provide their own implementations of + * _avs_net_create_ssl_socket(), _avs_net_create_dtls_socket(), + * _avs_net_initialize_global_ssl_state() and + * _avs_net_cleanup_global_ssl_state(). + */ +/* #undef AVS_COMMONS_WITH_CUSTOM_TLS */ +/**@}*/ + +/** + * Options related to avs_crypto. + */ +/**@{*/ +/** + * Enable AEAD and HKDF support in avs_crypto. Requires MbedTLS in version at + * least 2.14.0, OpenSSL in version at least 1.1.0, or custom implementation in + * case of AVS_COMMONS_WITH_CUSTOM_TLS. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_ADVANCED_FEATURES */ + +/** + * If the TLS backend is either mbed TLS or OpenSSL, enables APIs related to + * public-key cryptography. + * + * Public-key cryptography is not currently supported with TinyDTLS. + * + * It also enables support for X.509 certificates in avs_net, if that module is + * also enabled. + */ +/* #define AVS_COMMONS_WITH_AVS_CRYPTO_PKI */ + +/** + * If the TLS backend is either mbed TLS, OpenSSL or TinyDTLS, enables support + * of pre-shared key security. + * + * PSK is the only supported security mode for the TinyDTLS backend, so this + * option MUST be enabled to utilize it. + * + * It also enables support for pre-shared key security in avs_net, if that + * module is also enabled. + */ +#define AVS_COMMONS_WITH_AVS_CRYPTO_PSK + +/** + * Enables usage of Valgrind API to suppress some of the false positives + * generated by the OpenSSL backend. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_VALGRIND */ + +/** + * Enables high-level support for hardware-based PKI security, i.e. loading, + * generating and managing key pairs and certificates via external engines. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI to be enabled. + * + * An actual implementation is required to use this feature. You may provide + * your own, or use one of the default ones that come with the HSM engine + * commercial feature (see @ref AVS_COMMONS_WITH_MBEDTLS_PKCS11_ENGINE, + * @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE and + * @ref AVS_COMMONS_WITH_OPENSSL_PKCS11_ENGINE). + * + * The functions that need to be provided in case of a custom implementation: + * - avs_crypto_pki_engine_certificate_rm() + * - avs_crypto_pki_engine_certificate_store() + * - avs_crypto_pki_engine_key_gen() + * - avs_crypto_pki_engine_key_rm() + * - avs_crypto_pki_engine_key_store() + * - When targeting the Mbed TLS backend: + * - _avs_crypto_mbedtls_engine_initialize_global_state() + * - _avs_crypto_mbedtls_engine_cleanup_global_state() + * - _avs_crypto_mbedtls_engine_append_cert() + * - _avs_crypto_mbedtls_engine_append_crl() + * - _avs_crypto_mbedtls_engine_load_private_key() + * - When targeting the OpenSSL backend: + * - _avs_crypto_openssl_engine_initialize_global_state() + * - _avs_crypto_openssl_engine_cleanup_global_state() + * - _avs_crypto_openssl_engine_load_certs() + * - _avs_crypto_openssl_engine_load_crls() + * - _avs_crypto_openssl_engine_load_private_key() + * + * External PKI engines are NOT supported in the TinyDTLS backend. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE */ + +/** + * Enables high-level support for hardware-based PSK security, i.e. loading + * and managing PSK keys and identities via external engine. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI to be enabled. + * + * An actual implementation is required to use this feature. You may provide + * your own, or use the default PSA-based one that comes with the HSM engine + * commercial feature (see @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE). + * + * The functions that need to be provided in case of a custom implementation: + * - avs_crypto_psk_engine_identity_store() + * - avs_crypto_psk_engine_identity_rm() + * - avs_crypto_psk_engine_key_store() + * - avs_crypto_psk_engine_key_rm() + * - When targeting the Mbed TLS backend: + * - _avs_crypto_mbedtls_engine_initialize_global_state() + * - _avs_crypto_mbedtls_engine_cleanup_global_state() + * - _avs_crypto_mbedtls_engine_load_psk_key() + * + * External PSK engines are NOT supported in the OpenSSL and TinyDTLS backend. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_PSK_ENGINE */ + +/** + * Enables the default implementation of avs_crypto engine, based on Mbed TLS + * and PKCS#11. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE to be enabled. + * + * NOTE: Query string format for this engine is a subset of the PKCS#11 URI + * scheme (see RFC 7512), modelled after the format accepted by libp11 OpenSSL + * engine. + * + * NOTE: The unit tests for this feature depend on SoftHSM and pkcs11-tool. + * These must be installed for the tests to pass. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_MBEDTLS_PKCS11_ENGINE */ + +/** + * Enables the default implementation of avs_crypto engine, based on Mbed TLS + * and Platform Security Architecture (PSA). + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE or + * @ref AVS_COMMONS_WITH_AVS_CRYPTO_PSK_ENGINE to be enabled. + * + * NOTE: Query string format for this engine is: + * + * 
+ * kid=[,lifetime=]|uid=
+ *
+ * + * The values are parsed using strtoull() with base=0, so may be in decimal, + * 0-prefixed octal or 0x-prefixed hexadecimal. On key generation and + * certificate storage, the specified lifetime will be used, or lifetime 1 + * (default persistent storage) will be used if not. On key or certificate use, + * the lifetime of the actual key will be verified if present on the query + * string and the key will be rejected if different. + * + * Certificates are stored as PSA_KEY_TYPE_RAW_DATA key entries containing + * X.509 DER data. Alternatively, the PSA Protected Storage API can be used if + * @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE_PROTECTED_STORAGE is enabled, by + * using the uid=... syntax. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE */ + +/** + * Enables support for the PSA Protected Storage API in the PSA-based avs_crypto + * engine. + * + * Requires @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE to be enabled. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE_PROTECTED_STORAGE */ + +/** + * Is the dlsym() function available? + * + * This is currently only used if @ref AVS_COMMONS_WITH_MBEDTLS_PKCS11_ENGINE is + * enabled. If enabled, the PKCS#11 module is loaded dynamically from a library + * specified by the PKCS11_MODULE_PATH environment variable. If disabled, + * a function with the following signature, realizing the PKCS#11 + * C_GetFunctionList method, must be provided manually: + * + * 
+ * CK_RV _avs_crypto_mbedtls_pkcs11_get_function_list(CK_FUNCTION_LIST_PTR_PTR);
+ *
+ */ +/* #undef AVS_COMMONS_HAVE_DLSYM */ + +/** + * Enables the default implementation of avs_crypto engine, based on OpenSSL and + * PKCS#11. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE to be enabled. + * + * NOTE: Query string format for this engine is a subset of the PKCS#11 URI + * scheme (see RFC 7512), modelled after the format accepted by libp11 OpenSSL + * engine. + * + * NOTE: The unit tests for this feature depend on SoftHSM and pkcs11-tool. + * These must be installed for the tests to pass. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_OPENSSL_PKCS11_ENGINE */ +/**@}*/ + +/** + * Enable support for HTTP content compression in avs_http. + * + * Requires linking with zlib. + */ +/* #undef AVS_COMMONS_HTTP_WITH_ZLIB */ + +/** + * Options related to avs_log and logging support within avs_commons. + */ +/**@{*/ +/* clang-format off */ +/** + * Size, in bytes, of the avs_log buffer. + * + * Log messages that would (including the level, module name and code location) + * otherwise be longer than this value minus one (for the terminating null + * character) will be truncated. + * + * NOTE: This macro MUST be defined if avs_log is enabled. + * + * If editing this file manually, 512 shall + * be replaced with a positive integer literal. The default value defined in + * CMake build scripts is 512. + */ +#define AVS_COMMONS_LOG_MAX_LINE_LENGTH 256 +/* clang-format on */ + +/** + * Configures avs_log to use a synchronized global buffer instead of allocating + * a buffer on the stack when constructing log messages. + * + * Requires avs_compat_threading to be enabled. + * + * Enabling this option would reduce the stack space required to use avs_log, at + * the expense of global storage and the complexity of using a mutex. + */ +/* #define AVS_COMMONS_LOG_USE_GLOBAL_BUFFER */ + +/** + * Provides a default avs_log handler that prints log messages on stderr. + * + * Disabling this option will cause logs to be discarded by default, until a + * custom log handler is set using avs_log_set_handler(). + */ +/* #undef AVS_COMMONS_LOG_WITH_DEFAULT_HANDLER */ + +/** + * Enables the "micro logs" feature. + * + * Replaces all occurrences of the AVS_DISPOSABLE_LOG() macro with single + * space strings. This is intended to reduce the size of the compiled code, by + * stripping it of almost all log string data. + * + * Note that this setting will propagate both to avs_commons components + * themselves (as all its internal logs make use of AVS_DISPOSABLE_LOG()) + * and the user code that uses it. + */ +/* #undef AVS_COMMONS_WITH_MICRO_LOGS */ + +/** + * Enables logging inside avs_commons. + * + * Requires @ref AVS_COMMONS_WITH_AVS_LOG to be enabled. + * + * If this macro is not defined at avs_commons compile time, calls to avs_log + * will not be generated inside avs_commons components. + */ +/* #define AVS_COMMONS_WITH_INTERNAL_LOGS */ + +/** + * Enables TRACE-level logs inside avs_commons. + * + * Only meaningful if AVS_COMMONS_WITH_INTERNAL_LOGS is enabled. + * + * If this macro is not defined at avs_commons compile time, calls to avs_log + * with the level set to TRACE will not be generated inside avs_commons + * components. + */ +/* #undef AVS_COMMONS_WITH_INTERNAL_TRACE */ + +/** + * Enables external implementation of logger subsystem with provided header. + * + * Default logger implementation can be found in avs_log_impl.h + */ +/* #undef AVS_COMMONS_WITH_EXTERNAL_LOGGER_HEADER */ + +/** + * If specified, the process of checking if avs_log should be written out + * takes place in compile time. + * + * Specify an optional header with a list of modules for which log level + * is set. If a log level for specific module is not set, the DEFAULT level + * will be taken into account. Value of the default logging level is set to + * DEBUG, but can be overwritten in this header file with AVS_LOG_LEVEL_DEFAULT + * define. Messages with lower level than the one set will be removed during + * compile time. Possible values match @ref avs_log_level_t. + * + * That file should contain C preprocesor defines in the: + * - "#define AVS_LOG_LEVEL_FOR_MODULE_ " format, + * where is the module name and is allowed logging level + * - "#define AVS_LOG_LEVEL_DEFAULT " format, where is the + * allowed logging level + * + * Example file content: + * + * + * #ifndef AVS_COMMONS_EXTERNAL_LOG_LEVELS_H + * #define AVS_COMMONS_EXTERNAL_LOG_LEVELS_H + * + * // global log level value + * #define AVS_LOG_LEVEL_DEFAULT INFO + * + * //for "coap" messages only WARNING and ERROR messages will be present + * #define AVS_LOG_LEVEL_FOR_MODULE_coap WARNING + * + * //logs are disable for "net" module + * #define AVS_LOG_LEVEL_FOR_MODULE_net QUIET + * + * #endif + * + */ +#define AVS_COMMONS_WITH_EXTERNAL_LOG_LEVELS_HEADER \ + "avsystem/commons/avs_log_levels.h" + +/** + * Disable log level check in runtime. Allows to save at least 1.3kB of memory. + * + * The macros avs_log_set_level and avs_log_set_default_level + * will not be available. + * + */ +#define AVS_COMMONS_WITHOUT_LOG_CHECK_IN_RUNTIME +/**@}*/ + +/** + * Options related to avs_net. + */ +/**@{*/ +/** + * Enables support for IPv4 connectivity. + * + * At least one of AVS_COMMONS_NET_WITH_IPV4 and AVS_COMMONS_NET_WITH_IPV6 + * MUST be defined if avs_net is enabled. + */ +#define AVS_COMMONS_NET_WITH_IPV4 + +/** + * Enables support for IPv6 connectivity. + * + * At least one of AVS_COMMONS_NET_WITH_IPV4 and AVS_COMMONS_NET_WITH_IPV6 + * MUST be defined if avs_net is enabled. + */ +/* #undef AVS_COMMONS_NET_WITH_IPV6 */ + +/** + * If the TLS backend is set to OpenSSL, enables support for DTLS. + * + * DTLS is always enabled for the mbed TLS and TinyDTLS backends. + */ +/* #undef AVS_COMMONS_NET_WITH_DTLS */ + +/** + * Enables debug logs generated by mbed TLS. + * + * An avs_log-backed handler, logging for the "mbedtls" module on the TRACE + * level, is installed using mbedtls_ssl_conf_dbg() for each (D)TLS + * socket created if this option is enabled. + */ +/* #undef AVS_COMMONS_NET_WITH_MBEDTLS_LOGS */ + +/** + * Enables the default implementation of avs_net TCP and UDP sockets. + * + * Requires either a UNIX-like operating environment, or a compatibility layer + * with a high degree of compatibility with standard BSD sockets with an + * appropriate compatibility header (see @ref AVS_COMMONS_POSIX_COMPAT_HEADER) - + * lwIP and Winsock are currently supported for this scenario. + */ +#define AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET + +/** + * Enables support for logging socket communication to file. + * + * If this option is enabled, avs_net_socket_debug() can be used to enable + * logging all communication to a file called DEBUG.log. If disabled, + * avs_net_socket_debug() will always return an error. + */ +/* #define AVS_COMMONS_NET_WITH_SOCKET_LOG */ + +/** + * If the TLS backend is either mbed TLS or OpenSSL, enables support for (D)TLS + * session persistence. + * + * Session persistence is not currently supported for the TinyDTLS backend. + */ +/* #define AVS_COMMONS_NET_WITH_TLS_SESSION_PERSISTENCE */ +/**@}*/ + +/** + * Options related to avs_net's default implementation of TCP and UDP sockets. + * + * These options make sense only when @ref AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET + * is enabled. They describe capabilities of the Unix-like environment in which + * the library is built. + * + * Note that if @ref AVS_COMMONS_POSIX_COMPAT_HEADER is defined, it might + * redefine these flags independently of the settings in this file. + */ +/**@{*/ +/** + * Is the gai_strerror() function available? + * + * Enabling this flag will provide more detailed log messages in case that + * getaddrinfo() fails. If this flag is disabled, numeric error codes + * values will be logged. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_GAI_STRERROR */ + +/** + * Is the getifaddrs() function available? + * + * Disabling this flag will cause avs_net_socket_interface_name() to use + * a less optimal implementation based on the SIOCGIFCONF ioctl. + * + * If SIOCGIFCONF is not defined, either, then + * avs_net_socket_interface_name() will always return an error. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_GETIFADDRS */ + +/** + * Is the getnameinfo() function available? + * + * Disabling this flag will cause avs_net_socket_receive_from(), + * avs_net_socket_accept(), + * avs_net_resolved_endpoint_get_host_port(), + * avs_net_resolved_endpoint_get_host() and + * avs_net_resolve_host_simple() to use a custom reimplementation of + * getnameinfo() based on inet_ntop(). + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_GETNAMEINFO */ + +/** + * Is the IN6_IS_ADDR_V4MAPPED macro available and usable? + * + * Disabling this flag will cause a custom code that compares IPv6 addresses + * with the ::ffff:0.0.0.0/32 mask to be used instead. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_IN6_IS_ADDR_V4MAPPED */ + +/** + * Should be defined if IPv4-mapped IPv6 addresses (::ffff:0.0.0.0/32) + * are NOT supported by the underlying platform. + * + * Enabling this flag will prevent avs_net from using IPv4-mapped IPv6 addresses + * and instead re-open and re-bind the socket if a connection to an IPv4 address + * is requested on a previously created IPv6 socket. + * + * This may result in otherwise redundant socket(), bind() and + * close() system calls to be performed, but may be necessary for + * interoperability with some platforms. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_WITHOUT_IN6_V4MAPPED_SUPPORT */ + +/** + * Is the inet_ntop() function available? + * + * Disabling this flag will cause an internal implementation of this function + * adapted from BIND 4.9.4 to be used instead. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_INET_NTOP */ + +/** + * Is the poll() function available? + * + * Disabling this flag will cause a less robust code based on select() to + * be used instead. + */ +/* #define AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_POLL */ + +/** + * Is the recvmsg() function available? + * + * Disabling this flag will cause recvfrom() to be used instead. Note + * that for UDP sockets, this will cause false positives for datagram truncation + * detection (AVS_EMSGSIZE) to be reported when the received message is + * exactly the size of the buffer. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_RECVMSG */ +/**@}*/ + +/** + * Enable thread safety in avs_sched. + * + * Makes all scheduler accesses synchronized and thread-safe, at the cost of + * requiring avs_compat_threading to be enabled, and higher resource usage. + */ +/* #define AVS_COMMONS_SCHED_THREAD_SAFE */ + +/** + * Enable support for file I/O in avs_stream. + * + * Disabling this flag will cause the functions declared in + * avs_stream_file.h to not be defined. + */ +/* #undef AVS_COMMONS_STREAM_WITH_FILE */ + +/** + * Enable usage of backtrace() and backtrace_symbols() when + * reporting assertion failures from avs_unit. + * + * Requires the afore-mentioned GNU-specific functions to be available. + * + * If this flag is disabled, stack traces will not be displayed with assertion + * failures. + */ +/* #undef AVS_COMMONS_UNIT_POSIX_HAVE_BACKTRACE */ + +/** + * Options related to avs_utils. + */ +/**@{*/ +/** + * Enable the default implementation of avs_time_real_now() and + * avs_time_monotonic_now(). + * + * Requires an operating environment that supports a clock_gettime() call + * compatible with POSIX. + */ +/* #undef AVS_COMMONS_UTILS_WITH_POSIX_AVS_TIME */ + +/** + * Enable the default implementation of avs_malloc(), avs_free(), avs_calloc() + * and avs_realloc() that forwards to system malloc(), free(), calloc() and + * realloc() calls. + * + * You might disable this option if for any reason you need to use a custom + * allocator. + */ +/* #define AVS_COMMONS_UTILS_WITH_STANDARD_ALLOCATOR */ + +/** + * Enable the alternate implementation of avs_malloc(), avs_free(), avs_calloc() + * and avs_realloc() that uses system malloc(), free() and realloc() calls, but + * includes additional fixup code that ensures proper alignment to + * AVS_ALIGNOF(avs_max_align_t) (usually 8 bytes on common platforms). + * + * AVS_COMMONS_UTILS_WITH_STANDARD_ALLOCATOR and + * AVS_COMMONS_UTILS_WITH_ALIGNFIX_ALLOCATOR cannot be enabled at the + * same time. + * + * NOTE: This implementation is only intended for platforms where the system + * allocator does not properly conform to the alignment requirements. + * + * It comes with an additional runtime costs: + * + * - AVS_ALIGNOF(avs_max_align_t) bytes (usually 8) of additional + * overhead for each allocated memory block + * - Additional memmove() for every realloc() that returned a block that is not + * properly aligned + * - avs_calloc() is implemented as avs_malloc() followed by an explicit + * memset(); this may be suboptimal on some platforms + * + * If these costs are unacceptable for you, you may want to consider fixing, + * replacing or reconfiguring your system allocator for conformance, or + * implementing a custom one instead. + * + * Please note that some code in avs_commons and dependent projects (e.g. Anjay) + * may include runtime assertions for proper memory alignment that will be + * triggered when using a non-conformant standard allocator. Such allocators are + * relatively common in embedded SDKs. This "alignfix" allocator is intended to + * work around these issues. On some platforms (e.g. x86) those alignment issues + * may not actually cause any problems - so you may want to consider disabling + * runtime assertions instead. Please carefully examine your target platform's + * alignment requirements and behavior of misaligned memory accesses (including + * 64-bit data types such as int64_t and double) before doing so. + */ +/* #undef AVS_COMMONS_UTILS_WITH_ALIGNFIX_ALLOCATOR */ +/**@}*/ + +#endif /* AVS_COMMONS_CONFIG_H */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_log_levels.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_log_levels.h new file mode 100644 index 0000000000..db051626f8 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_log_levels.h @@ -0,0 +1,51 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef AVS_COMMONS_EXTERNAL_LOG_LEVELS_H +#define AVS_COMMONS_EXTERNAL_LOG_LEVELS_H + +// global log level value +#define AVS_LOG_LEVEL_DEFAULT INFO + +#ifdef __GNUC__ + +// HACK: Replace path to whole file with just the filename to save up on flash +// usage. +// Older versions of STM32CubeIDE (e.g. 1.7.0) provide __FILENAME__ definition. +// It was later replaced by __FILE_NAME__ which appeared in upstream gcc for +// compability with clang. +// +// Both definitions are not standard. + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wbuiltin-macro-redefined" + +#if defined(__FILE_NAME__) +#undef __FILE__ +#define __FILE__ __FILE_NAME__ +#elif defined(__FILENAME__) +#undef __FILE__ +#define __FILE__ __FILENAME__ +#else +#pragma GCC warning \ + "Both __FILE_NAME__ and __FILENAME__ macros are not available. Logs will include full file paths, which may affect the size of the application binary depending on where the project is located." +#endif // defined(__FILE_NAME__) + +#pragma GCC diagnostic pop + +#endif // __GNUC__ + +#endif diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/chconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/chconf.h new file mode 100644 index 0000000000..f4cabc3577 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/chconf.h @@ -0,0 +1,817 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/halconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/halconf.h new file mode 100644 index 0000000000..35fa7bc75c --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/halconf.h @@ -0,0 +1,553 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/lwipopts.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/lwipopts.h new file mode 100644 index 0000000000..4a7c469181 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/lwipopts.h @@ -0,0 +1,2138 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +#ifndef LWIP_DNS_SECURE +#define LWIP_DNS_SECURE 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE (10*1024) +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 1 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +//#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#define DHCP_DOES_ARP_CHECK 0 +#endif + +#ifndef LWIP_DHCP_GETS_NTP +#define LWIP_DHCP_GETS_NTP 1 +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 1 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS (1500 - 40) +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 1 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 1 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_RCVRCVTIMEO_NONSTANDARD 1 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 1 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/mbedtls/mbedtls_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/mbedtls/mbedtls_config.h new file mode 100644 index 0000000000..d34c44a816 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/mbedtls/mbedtls_config.h @@ -0,0 +1,112 @@ +/** + * \file config-ccm-psk-dtls1_2.h + * + * \brief Small configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Minimal configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites + * + * Distinguishing features: + * - Optimized for small code size, low bandwidth (on an unreliable transport), + * and low RAM usage. + * - No asymmetric cryptography (no certificates, no Diffie-Hellman key + * exchange). + * - Fully modern and secure (provided the pre-shared keys are generated and + * stored securely). + * - Very low record overhead with CCM-8. + * - Includes several optional DTLS features typically used in IoT. + * + * See README.txt for usage instructions. + */ + +/* System support */ +//#define MBEDTLS_HAVE_TIME /* Optionally used in Hello messages */ +/* Other MBEDTLS_HAVE_XXX flags irrelevant for this configuration */ + +/* Mbed TLS modules */ +#define MBEDTLS_AES_C +#define MBEDTLS_CCM_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_MD_C +#define MBEDTLS_NET_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_SSL_TLS_C +#define MBEDTLS_TIMING_C + +/* TLS protocol feature support */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#define MBEDTLS_SSL_DTLS_CONNECTION_ID +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/* + * Use only CCM_8 ciphersuites, and + * save ROM and a few bytes of RAM by specifying our own ciphersuite list + */ +#define MBEDTLS_SSL_CIPHERSUITES \ + MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8, \ + MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8 + +/* + * Save RAM at the expense of interoperability: do this only if you control + * both ends of the connection! (See comments in "mbedtls/ssl.h".) + * The optimal size here depends on the typical size of records. + */ +#define MBEDTLS_SSL_IN_CONTENT_LEN 256 +#define MBEDTLS_SSL_OUT_CONTENT_LEN 256 + +/* Save RAM at the expense of ROM */ +#define MBEDTLS_AES_ROM_TABLES + +/* Save some RAM by adjusting to your exact needs */ +#define MBEDTLS_PSK_MAX_LEN 16 /* 128-bits keys are generally enough */ + +/* + * You should adjust this to the exact number of sources you're using: default + * is the "platform_entropy_poll" source, but you may want to add other ones + * Minimum is 2 for the entropy test suite. + */ +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 + +/* These defines are present so that the config modifying scripts can enable + * them during tests/scripts/test-ref-configs.pl */ +//#define MBEDTLS_USE_PSA_CRYPTO +//#define MBEDTLS_PSA_CRYPTO_C + +/* Error messages and TLS debugging traces + * (huge code size increase, needed for tests/ssl-opt.sh) */ +//#define MBEDTLS_DEBUG_C +//#define MBEDTLS_ERROR_C + +/* To prevent using the libc standard calloc() and free(). */ +//#define MBEDTLS_PLATFORM_C +//#define MBEDTLS_PLATFORM_MEMORY + +/* If your system does not have a libc equivalent, you will get compile errors as calloc() or free() cannot be found.* */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/mcuconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/mcuconf.h new file mode 100644 index 0000000000..62969ad8ba --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/cfg/mcuconf.h @@ -0,0 +1,353 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define STM32L4xx_MCUCONF +#define STM32L475_MCUCONF +#define STM32L476_MCUCONF +#define STM32L486_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI16_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_MSIPLL_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_4M +#define STM32_MSISRANGE STM32_MSISRANGE_4M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_MSI +#define STM32_PLLM_VALUE 1 +#define STM32_PLLN_VALUE 80 +#define STM32_PLLP_VALUE 7 +#define STM32_PLLQ_VALUE 6 +#define STM32_PLLR_VALUE 4 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_STOPWUCK STM32_STOPWUCK_MSI +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#define STM32_PLLSAI1N_VALUE 72 +#define STM32_PLLSAI1P_VALUE 7 +#define STM32_PLLSAI1Q_VALUE 6 +#define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2N_VALUE 72 +#define STM32_PLLSAI2P_VALUE 7 +#define STM32_PLLSAI2R_VALUE 6 + +/* + * Peripherals clock sources. + */ +#define STM32_USART1SEL STM32_USART1SEL_SYSCLK +#define STM32_USART2SEL STM32_USART2SEL_SYSCLK +#define STM32_USART3SEL STM32_USART3SEL_SYSCLK +#define STM32_UART4SEL STM32_UART4SEL_SYSCLK +#define STM32_UART5SEL STM32_UART5SEL_SYSCLK +#define STM32_LPUART1SEL STM32_LPUART1SEL_LSE +#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK +#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_LSE +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_LSE +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_ADCSEL STM32_ADCSEL_SYSCLK +#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 +#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI1635_38_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_22_PRIORITY 15 + +#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_LPUART1_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_LPUART1 TRUE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 TRUE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_LPUART1 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_LPUART1_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 + +#endif /* MCUCONF_H */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/main.c b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/main.c new file mode 100644 index 0000000000..aad5924602 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/main.c @@ -0,0 +1,120 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "hal.h" +#include "cmsis_os.h" +#include "avs_test_task.h" +#include "lwipthread.h" + + +/* + * 1) The MAC address usually comes from factory settings which are stored somewhere in ROM. + * 2) The MAC address can be generated by https://gist.githubusercontent.com/pklaus/9638536/raw/2fe075503fda54fc00f5b6d2a4398a7208e085f4/randmac.py + */ +static uint8_t mac_address[6] = { 0x7e, 0x2f, 0xa2, 0xc0, 0xd0, 0xf8 }; + +static const SPIConfig spi_config = { + .circular = false, + .slave = false, + .ssport = PAL_PORT(LINE_W5500_NSS), + .sspad = PAL_PAD(LINE_W5500_NSS), + /* W5500 supports SPI mode 0 and 3. Here we go with mode 3. */ + .cr1 = SPI_CR1_MSTR | /* Master Configuration */ + SPI_CR1_CPHA | /* The second clock transition is the first data capture edge */ + SPI_CR1_CPOL | /* Clock Polarity to 1 when idle */ + SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_BR_2, /* Baud Rate is fPCLK /256 */ + .cr2 = SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2 /* Data size is 8-bit */ +}; + +static const ETHSPIConfig eth_config = { + .driver = &SPID1, + .config = &spi_config, + + .reset_line = LINE_W5500_RST, + .reset_trc_delay_ms = 100, + .reset_tpl_delay_ms = 300, + +#if ETH_USE_CALLBACKS == TRUE + .irq_line = LINE_W5500_INT, +#endif +}; + +static const ETHPhyConfig phy_config = { + .conf_by = ETH_PHY_CONF_BY_SW, + .mode = ETH_PHY_MODE_AUTO, + .speed = ETH_PHY_SPEED_100, + .duplex = ETH_PHY_DUPLEX_FULL +}; + +MACDriver ETHD1 = { + .spi_config = ð_config, + .phy_config = &phy_config, +}; + +static const lwipthread_opts_t lwip_opts = { + .macaddress = mac_address, + .addrMode = NET_ADDRESS_DHCP, +}; + +static const uint8_t PSK_KEY[] = { 5, 4, 3, 2, 1 }; + +static const avs_test_opts_t avs_test_opts = { + .dst_ip_addr = "192.168.2.136", + .dst_port_coap_udp = "5683", + .dst_coap_udp_ssl = "5684", + .dst_coap_tcp = "6683", + .dst_coap_tcp_ssl = "6684", + + .psk_identity = "12345", + .psk_key = PSK_KEY, + .psk_key_size = sizeof(PSK_KEY), +}; + +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + */ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal by default.*/ + osKernelStart(); + + trngStart(&TRNGD1, NULL); + + lwipInit(&lwip_opts); + + avsTestInit(&avs_test_opts); + + /* + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + while (true) { + osDelay(osWaitForever); + } + + return 0; +} diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/readme.txt b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/readme.txt new file mode 100644 index 0000000000..0ea20d5c12 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/readme.txt @@ -0,0 +1,24 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32L476. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STM32 Nucleo64-L476RG board. + +** The Demo ** + +ETH WIZ CLICK (with W5500) stacked on top of Arduino Uno click shield. + +** Build Procedure ** + +Nothing special, just make it! + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/.gitignore b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/.gitignore new file mode 100644 index 0000000000..0300da9e3c --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/.gitignore @@ -0,0 +1 @@ +SimpleCoAPServer diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/SimpleCoAPServer.zip b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/SimpleCoAPServer.zip new file mode 100644 index 0000000000..201e20dbb1 Binary files /dev/null and b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/SimpleCoAPServer.zip differ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/readme.txt b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/readme.txt new file mode 100644 index 0000000000..dd1697406d --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS/res/readme.txt @@ -0,0 +1,4 @@ +SimpleCoAPServer is a small Java(tm) application to test LWIP, +Anjay and mbedtls against it. + +Created with IntelliJ IDEA Community Edition - just to say thanks to JetBrains! \ No newline at end of file diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/Makefile b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/Makefile new file mode 100644 index 0000000000..915616e678 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/Makefile @@ -0,0 +1,195 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +USER_CONTRIB := $(CHIBIOS)/../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk +# User application +include $(CHIBIOS_CONTRIB)/os/various/wiznet-iolibrary-driver_bindings/wiznet.mk +include $(CHIBIOS_CONTRIB)/os/various/anjay_bindings/anjay.mk +include $(CHIBIOS_CONTRIB)/os/various/mbedtls_bindings/mbedtls.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32L476xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c \ + avs_test_task.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/avs_test_task.c b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/avs_test_task.c new file mode 100644 index 0000000000..6ada9dcc85 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/avs_test_task.c @@ -0,0 +1,871 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "cmsis_os.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "avs_test_task.h" + +#define CUSTOM_CONTENT_TYPE 72 + +static const char *dst_ip_addr; +static const char *dst_port_coap_udp; +static const char *dst_coap_udp_ssl; +static const char *dst_coap_tcp; +static const char *dst_coap_tcp_ssl; + +static const char *psk_identity; +static const uint8_t *psk_key; +static size_t psk_key_size; + + +#if defined(AVS_COMMONS_WITH_AVS_STREAM) && defined(WITH_AVS_COAP_STREAMING_API) + +static int avs_buffer_writer(struct avs_stream_struct *out_stream, void *arg) { + avs_payload_buffer_t *buf = arg; + + avs_error_t err = avs_stream_write(out_stream, buf->buffer, buf->length); + + if (avs_is_err(err)) + return -1; + + return 0; +} + +static void anjay_streaming_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + const avs_net_socket_configuration_t sock_cfg = { + .reuse_addr = 0, + .address_family = AVS_NET_AF_INET4, + .forced_mtu = 512, + .preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_udp_socket_create(&sock, &sock_cfg); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_port_coap_udp); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_response_header_t response; + avs_stream_t *out_response_stream = NULL; + + err = avs_coap_streaming_send_request(udp_ctx, &request, &avs_buffer_writer, &payload, &response, + &out_response_stream); + + if (!avs_is_err(err)) { + goto err; + } + + uint8_t buf[128]; + size_t bytes_read; + + if (out_response_stream) { + for (bool finished = false; !finished;) { + //avs_coap_streaming_handle_incoming_packet(avs_coap_ctx_t *coap_ctx, avs_coap_streaming_request_handler_t *handle_request, void *handler_arg); + err = avs_stream_read(out_response_stream, &bytes_read, &finished, buf, sizeof(buf)); + + if (!avs_is_err(err)) { + break; + } + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} +#endif + +static int avs_payload_writer(size_t payload_offset, + void *payload_buf, + size_t payload_buf_size, + size_t *out_payload_chunk_size, + void *arg) { + (void)payload_offset; + + avs_payload_buffer_t *buf = arg; + + size_t payload_bytes = AVS_MIN(buf->length, payload_buf_size); + + memcpy(payload_buf, buf->buffer, payload_bytes); + + + *out_payload_chunk_size = payload_bytes; + + return 0; +} + +static void avs_payload_reader(avs_coap_ctx_t *ctx, + avs_coap_exchange_id_t exchange_id, + avs_coap_client_request_state_t result, + const avs_coap_client_async_response_t *response, + avs_error_t err, + void *finished_) { + (void)ctx; + (void)exchange_id; + (void)result; + (void)response; + (void)err; + + *(bool *)finished_ = true; +} + +static int avs_request_handler(avs_coap_server_ctx_t *ctx, const avs_coap_request_header_t *request, + void *arg) { + + (void)ctx; + (void)request; + (void)arg; + + return 0; +} + +static void anjay_async_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + const avs_net_socket_configuration_t sock_cfg = { + .reuse_addr = 0, + .address_family = AVS_NET_AF_INET4, + .forced_mtu = 512, + .preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_udp_socket_create(&sock, &sock_cfg); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_port_coap_udp); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(udp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(udp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} + +#if defined(WITH_AVS_COAP_TCP) +static void anjay_async_tcp_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_time_duration_t request_timeout = { }; // = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT; + avs_coap_ctx_t *tcp_ctx = avs_coap_tcp_ctx_create(sched, in_buffer, out_buffer, 10, request_timeout, + prng); + + if (!tcp_ctx) { + goto err; + } + + const avs_net_socket_configuration_t sock_cfg = { + .reuse_addr = 0, + .address_family = AVS_NET_AF_INET4, + .forced_mtu = 512, + .preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_tcp_socket_create(&sock, &sock_cfg); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_coap_tcp); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(tcp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(tcp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(tcp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&tcp_ctx); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} +#endif + +static void ssl_psk_anjay_async_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + avs_net_ssl_configuration_t config = { + .version = AVS_NET_SSL_VERSION_DEFAULT, + .security = avs_net_security_info_from_psk((avs_net_psk_info_t) { + .key = avs_crypto_psk_key_info_from_buffer(psk_key, psk_key_size), + .identity = avs_crypto_psk_identity_info_from_buffer(psk_identity, strlen(psk_identity)), + }), + .ciphersuites = { + //.ids = default_ciphersuites, + //.num_ids = default_ciphersuites_num + }, + .prng_ctx = prng, + + .backend_configuration.reuse_addr = 0, + .backend_configuration.address_family = AVS_NET_AF_INET4, + .backend_configuration.forced_mtu = 512, + .backend_configuration.preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_dtls_socket_create(&sock, &config); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_coap_udp_ssl); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(udp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(udp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + //avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} + +static const char *ca_cert = R"()"; +static const char *client_cert = R"()"; +static const char *client_key = R"()"; + +static void ssl_x509_anjay_async_test(void) { + avs_error_t err; + + avs_sched_t *sched = avs_sched_new(NULL, NULL); + + if (!sched) { + goto err; + } + + avs_crypto_prng_ctx_t *prng = avs_crypto_prng_new(NULL, NULL); + + if (!prng) { + goto err; + } + + avs_shared_buffer_t *in_buffer = avs_shared_buffer_new(2 * 1024); + + if (!in_buffer) { + goto err; + } + + avs_shared_buffer_t *out_buffer = avs_shared_buffer_new(2 * 1024); + + if (!out_buffer) { + goto err; + } + + avs_coap_udp_response_cache_t *cache = avs_coap_udp_response_cache_create(2 * 1024); + + if (!cache) { + goto err; + } + + const avs_coap_udp_tx_params_t tx_params = { + .ack_timeout = AVS_NET_SOCKET_DEFAULT_RECV_TIMEOUT, + .ack_random_factor = 1.0, + .max_retransmit = 2, + .nstart = 1, + }; + avs_coap_ctx_t *udp_ctx = avs_coap_udp_ctx_create(sched, &tx_params, in_buffer, out_buffer, cache, + prng); + + if (!udp_ctx) { + goto err; + } + + const avs_net_ssl_configuration_t config = { + .version = AVS_NET_SSL_VERSION_DEFAULT, + .security = avs_net_security_info_from_certificates((avs_net_certificate_info_t) { + .server_cert_validation = true, + .trusted_certs = avs_crypto_certificate_chain_info_from_buffer(ca_cert, strlen(ca_cert)), + .client_cert = avs_crypto_certificate_chain_info_from_buffer(client_cert, strlen(client_cert)), + .client_key = avs_crypto_private_key_info_from_buffer(client_key, strlen(client_key), NULL) + }), + .ciphersuites = { + //.ids = default_ciphersuites, + //.num_ids = default_ciphersuites_num + }, + .prng_ctx = prng, + + .backend_configuration.reuse_addr = 0, + .backend_configuration.address_family = AVS_NET_AF_INET4, + .backend_configuration.forced_mtu = 512, + .backend_configuration.preferred_family = AVS_NET_AF_INET4 + }; + + avs_net_socket_t *sock = NULL; + + err = avs_net_dtls_socket_create(&sock, &config); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_connect(sock, dst_ip_addr, dst_coap_udp_ssl); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_coap_ctx_set_socket(udp_ctx, sock); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __payload[] = { 0x00, 0x01, 0x02, 0x03 }; + avs_payload_buffer_t payload = { .buffer = __payload, .length = sizeof(__payload), }; + + avs_coap_request_header_t request = { .code = AVS_COAP_CODE_POST, + .options = avs_coap_options_create_empty(NULL, 0), + }; + + err = avs_coap_options_dynamic_init(&request.options); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_HOST, "localhost"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_1"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2"); + err = avs_coap_options_add_string(&request.options, AVS_COAP_OPTION_URI_PATH, "res_lvl_2a"); + err = avs_coap_options_set_content_format(&request.options, CUSTOM_CONTENT_TYPE); + //err = avs_coap_options_set_content_format(&request.options, AVS_COAP_FORMAT_CBOR); + err = avs_coap_options_add_uint(&request.options, AVS_COAP_OPTION_SIZE1, &payload.length, + sizeof(payload.length)); + + avs_coap_exchange_id_t id; + bool finished = false; + + err = avs_coap_client_send_async_request(udp_ctx, &id, &request, + &avs_payload_writer, &payload, &avs_payload_reader, &finished); + + if (avs_is_err(err)) { + goto err; + } + + uint8_t __read_payload[64] = {0}; + avs_payload_buffer_t read_payload = { .buffer = __read_payload, .length = sizeof(__read_payload), }; + + if (!avs_coap_exchange_id_valid(id)) { + goto err; + } + + for (int i = 0; i < 50 && !finished; ++i) { + avs_sched_run(sched); + + osDelay(100); + + err = avs_coap_async_handle_incoming_packet(udp_ctx, &avs_request_handler, &read_payload); + + if (avs_is_err(err)) { + goto err; + } + } + + err = avs_net_socket_shutdown(sock); + + if (avs_is_err(err)) { + goto err; + } + + err = avs_net_socket_close(sock); + + if (avs_is_err(err)) { + goto err; + } + +err: + //avs_coap_options_cleanup(&request.options); + avs_net_socket_cleanup(&sock); + avs_coap_ctx_cleanup(&udp_ctx); + avs_coap_udp_response_cache_release(&cache); + avs_free(out_buffer); + avs_free(in_buffer); + avs_crypto_prng_free(&prng); + avs_sched_cleanup(&sched); +} + +static void avsTestTask(const void *arg) { + (void)arg; + + avs_heap_init(); + + //anjay_async_tcp_test(); + //anjay_streaming_test(); + //anjay_async_test(); + //ssl_psk_anjay_async_test(); + //ssl_x509_anjay_async_test(); + + while (true) { + osDelay(1000); + ssl_psk_anjay_async_test(); + avs_heap_get_free(); + + osDelay(1000); + anjay_async_test(); + avs_heap_get_free(); + } +} + +void avsTestInit(const avs_test_opts_t *avs_test_opts) { + static osThreadDef(avsTestTask, osPriorityNormal, 4u * 1024u, "avs_test_task"); + + dst_ip_addr = avs_test_opts->dst_ip_addr; + dst_port_coap_udp = avs_test_opts->dst_port_coap_udp; + dst_coap_udp_ssl = avs_test_opts->dst_coap_udp_ssl; + dst_coap_tcp = avs_test_opts->dst_coap_tcp; + dst_coap_tcp_ssl = avs_test_opts->dst_coap_tcp_ssl; + + psk_identity = avs_test_opts->psk_identity; + psk_key = avs_test_opts->psk_key; + psk_key_size = avs_test_opts->psk_key_size; + + osThreadCreate(osThread(avsTestTask), NULL); +} diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/avs_test_task.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/avs_test_task.h new file mode 100644 index 0000000000..329c9f0220 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/avs_test_task.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef AVS_TEST_TASK_H +#define AVS_TEST_TASK_H + +typedef struct { + const char *dst_ip_addr; + const char *dst_port_coap_udp; + const char *dst_coap_udp_ssl; + const char *dst_coap_tcp; + const char *dst_coap_tcp_ssl; + + const char *psk_identity; + const uint8_t *psk_key; + size_t psk_key_size; +} avs_test_opts_t; + +typedef struct { + uint8_t *buffer; + size_t length; +} avs_payload_buffer_t; + +void avsTestInit(const avs_test_opts_t *avs_test_opts); + +#endif /* AVS_TEST_TASK_H */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/anjay/anjay_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/anjay/anjay_config.h new file mode 100644 index 0000000000..c41af6f6d4 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/anjay/anjay_config.h @@ -0,0 +1,650 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * All rights reserved. + * + * Licensed under the AVSystem-5-clause License. + * See the attached LICENSE file for details. + */ + +#ifndef ANJAY_CONFIG_H +#define ANJAY_CONFIG_H + +/** + * @file anjay_config.h + * + * Anjay library configuration. + * + * The preferred way to compile Anjay is to use CMake, in which case this file + * will be generated automatically by CMake. + * + * However, to provide compatibility with various build systems used especially + * by embedded platforms, it is alternatively supported to compile Anjay by + * other means, in which case this file will need to be provided manually. + * + * NOTE: To compile this library without using CMake, you need to + * configure avs_commons and avs_coap first. Please refer to documentation in + * the avs_commons_config.h and avs_coap_config.h files (provided + * in the repositories as avs_commons_config.h.in and + * avs_coap_config.h.in, respectively) for details. + * + * Anjay requires the following avs_coap options to be enabled: + * + * - @c WITH_AVS_COAP_UDP + * - @c WITH_AVS_COAP_STREAMING_API + * - @c WITH_AVS_COAP_BLOCK is highly recommended + * - @c WITH_AVS_COAP_OBSERVE (if @c ANJAY_WITH_OBSERVE is enabled) + * - @c WITH_AVS_COAP_OSCORE (if @c ANJAY_WITH_COAP_OSCORE is enabled, available + * only as a commercial feature) + * + * Anjay requires the following avs_commons components to be + * enabled: + * + * - All components required by avs_coap, see avs_coap_config.h + * - @c avs_algorithm + * - @c avs_stream + * - @c avs_url + * - @c avs_persistence is highly recommended + * - @c avs_http (if @c ANJAY_WITH_HTTP_DOWNLOAD is enabled) + * - @c avs_rbtree (if @c ANJAY_WITH_OBSERVE or + * @c ANJAY_WITH_MODULE_ACCESS_CONTROL is enabled) + * + * In the repository, this file is provided as anjay_config.h.in, + * intended to be processed by CMake. If editing this file manually, please copy + * or rename it to anjay_config.h and for each of the + * \#cmakedefine directives, please either replace it with regular + * \#define to enable it, or comment it out to disable. You may also need + * to replace variables wrapped in \@ signs with concrete values. Please + * refer to the comments above each of the specific definition for details. + * + * If you are editing a file previously generated by CMake, these + * \#cmakedefines will be already replaced by either \#define or + * commented out \#undef directives. + */ + +/** + * Enable logging in Anjay. + * + * If this flag is disabled, no logging is compiled into the binary at all. + */ +/* #define ANJAY_WITH_LOGS */ + +/** + * Enable TRACE-level logs in Anjay. + * + * Only meaningful if ANJAY_WITH_LOGS is enabled. + */ +/* #undef ANJAY_WITH_TRACE_LOGS */ + +/** + * Enable core support for Access Control mechanisms. + * + * Requires separate implementation of the Access Control object itself. + * Either the implementation available as part of + * ANJAY_WITH_MODULE_ACCESS_CONTROL, or a custom application-provided one + * may be used. + */ +/* #undef ANJAY_WITH_ACCESS_CONTROL */ + +/** + * Enable automatic attribute storage. + * + * Requires AVS_COMMONS_WITH_AVS_PERSISTENCE to be enabled in avs_commons + * configuration. + */ +/* #define ANJAY_WITH_ATTR_STORAGE */ + +/** + * Enable support for the anjay_download() API. + */ +/* #define ANJAY_WITH_DOWNLOADER */ + +/** + * Enable support for CoAP(S) downloads. + * + * Only meaningful if ANJAY_WITH_DOWNLOADER is enabled. + */ +/* #define ANJAY_WITH_COAP_DOWNLOAD */ + +/** + * Enable support for HTTP(S) downloads. + * + * Only meaningful if ANJAY_WITH_DOWNLOADER is enabled. + */ +/* #undef ANJAY_WITH_HTTP_DOWNLOAD */ + +/** + * Enable support for the LwM2M Bootstrap Interface. + */ +/* #define ANJAY_WITH_BOOTSTRAP */ + +/** + * Enable support for the LwM2M Discover operation. + * + * Note that it is required for full compliance with the LwM2M protocol. + */ +/* #define ANJAY_WITH_DISCOVER */ + +/** + * Enable support for the LwM2M Information Reporting interface (Observe and + * Notify operations). + * + * Requires WITH_AVS_COAP_OBSERVE to be enabled in avs_coap + * configuration. + * + * Note that it is required for full compliance with the LwM2M protocol. + */ +/* #define ANJAY_WITH_OBSERVE */ + +/** + * Enable support for measuring amount of LwM2M traffic + * (anjay_get_tx_bytes(), anjay_get_rx_bytes(), + * anjay_get_num_incoming_retransmissions() and + * anjay_get_num_outgoing_retransmissions() APIs. + */ +/* #undef ANJAY_WITH_NET_STATS */ + +/** + * Enable support for communication timestamp + * (anjay_get_server_last_registration_time() + * anjay_get_server_next_update_time() and + * anjay_get_server_last_communication_time()) APIs. + */ +/* #undef ANJAY_WITH_COMMUNICATION_TIMESTAMP_API */ + +/** + * Enable support for the anjay_resource_observation_status() API. + */ +/* #define ANJAY_WITH_OBSERVATION_STATUS */ + +/** + * Maximum number of servers observing a given Resource listed by + * anjay_resource_observation_status() function. + * + * Only meaningful if ANJAY_WITH_OBSERVATION_STATUS is enabled. + */ +/* #define ANJAY_MAX_OBSERVATION_SERVERS_REPORTED_NUMBER 0 */ + +/** + * Enable guarding of all accesses to anjay_t with a mutex. + */ +/* #undef ANJAY_WITH_THREAD_SAFETY */ + +/** + * Enable standard implementation of an event loop. + * + * Requires C11 stdatomic.h header to be available, and either a platform + * that provides a BSD-compatible socket API, or a compatibility layer file (see + * AVS_COMMONS_POSIX_COMPAT_HEADER in avs_commons_config.h). This + * is designed to best work with the defalt implementation of avs_net sockets + * (see AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET), but alternative socket + * implementations can also be used. + * + * The event loop is most useful when thread safety features + * (@ref ANJAY_WITH_THREAD_SAFETY and AVS_COMMONS_SCHED_THREAD_SAFE) are + * enabled as well, but this is not a hard requirement. See the documentation + * for anjay_event_loop_run() for details. + */ +/* #define ANJAY_WITH_EVENT_LOOP */ + +/** + * Enable support for features new to LwM2M protocol version 1.1. + */ +/* #define ANJAY_WITH_LWM2M11 */ + +/** + * Enable support for OSCORE-based security for LwM2M connections. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled, and + * WITH_AVS_COAP_OSCORE to be enabled in avs_coap configuration. + * + * IMPORTANT: Only available as part of the OSCORE commercial feature. Ignored + * in the open source version. + */ +/* #undef ANJAY_WITH_COAP_OSCORE */ + +/** + * Enable support for the LwM2M Send operation. + * + * Requires ANJAY_WITH_LWM2M11 and either ANJAY_WITH_SENML_JSON or + * ANJAY_WITH_CBOR to be enabled. + */ +/* #undef ANJAY_WITH_SEND */ + +/** + * Enable support for the SMS binding and the SMS trigger mechanism. + * + * Requires WITH_AVS_COAP_UDP to be enabled in avs_coap configuration. + * + * IMPORTANT: Only available as part of the SMS commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_SMS */ + +/** + * Enable support for sending and receiving multipart SMS messages. + * + * Requires ANJAY_WITH_SMS to be enabled. + * + * IMPORTANT: Only available as part of the SMS commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_SMS_MULTIPART */ + +/** + * Enable support for Non-IP Data Delivery. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled, and + * WITH_AVS_COAP_UDP to be enabled in avs_coap configuration. + * + * IMPORTANT: Only available as a commercial feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_NIDD */ + +/** + * Enable support for core state persistence + * (anjay_new_from_core_persistence() and + * anjay_delete_with_core_persistence() APIs). + * + * Requires ANJAY_WITH_OBSERVE to be enabled, + * AVS_COMMONS_WITH_AVS_PERSISTENCE to be enabled in avs_commons, and + * WITH_AVS_COAP_OBSERVE_PERSISTENCE to be enabled in avs_coap + * configuration. + * + * IMPORTANT: Only available as a commercial feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_CORE_PERSISTENCE */ + +/** + * Disable automatic closing of server connection sockets after + * MAX_TRANSMIT_WAIT of inactivity. + */ +/* #undef ANJAY_WITHOUT_QUEUE_MODE_AUTOCLOSE */ + +/** + * Enable support for CoAP Content-Format numerical values 1541-1544 that have + * been used before final LwM2M TS 1.0. + */ +/* #undef ANJAY_WITH_LEGACY_CONTENT_FORMAT_SUPPORT */ + +/** + * Enable support for JSON format as specified in LwM2M TS 1.0. + * + * NOTE: Anjay is only capable of generating this format, there is no parsing + * support regardless of the state of this option. + */ +/* #undef ANJAY_WITH_LWM2M_JSON */ + +/** + * Disable support for TLV format as specified in LwM2M TS 1.0. + * + * NOTE: LwM2M Client using LwM2M 1.0 MUST support this format. It may be + * disabled if LwM2M 1.1 is used and SenML JSON or SenML CBOR is enabled. + */ +/* #undef ANJAY_WITHOUT_TLV */ + +/** + * Disable support for Plain Text format as specified in LwM2M TS 1.0 and 1.1. + * + * NOTE: LwM2M Client SHOULD support this format. It may be disabled to reduce + * library size if LwM2M Server is configured to not use it in requests. + */ +/* #undef ANJAY_WITHOUT_PLAINTEXT */ + +/** + * Disable use of the Deregister message. + */ +/* #undef ANJAY_WITHOUT_DEREGISTER */ + +/** + * Disable support for "IP stickiness", i.e. preference of the same IP address + * when reconnecting to a server using a domain name. + */ +#define ANJAY_WITHOUT_IP_STICKINESS + +/** + * Enable support for SenML JSON format, as specified in LwM2M TS 1.1. + * + * NOTE: As opposed to ANJAY_WITH_LWM2M_JSON, both generating and parsing + * is supported. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled. + */ +/* #undef ANJAY_WITH_SENML_JSON */ + +/** + * Enable support for CBOR and SenML CBOR formats, as specified in LwM2M TS 1.1. + * + * Requires ANJAY_WITH_LWM2M11 to be enabled. + */ +/* #undef ANJAY_WITH_CBOR */ + +/** + * Enable support for Enrollment over Secure Transport. + * + * Requires ANJAY_WITH_BOOTSTRAP to be enabled. + * + * IMPORTANT: Only available as part of the EST commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_EST */ + +/** + * Enable support for hardware security engine in the EST subsystem. + * + * Requires ANJAY_WITH_EST to be enabled in Anjay configuration and + * AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE to be enabled in avs_commons + * configuration. + * + * IMPORTANT: Only available in commercial versions that include both the EST + * and HSM features. Ignored in versions distributed without these features. + */ +/* #undef ANJAY_WITH_EST_ENGINE_SUPPORT */ + +/** + * Enable support for the Confirmable Notification attribute, as specified in + * LwM2M TS 1.2. + * + * Before TS 1.2, this has been supported in Anjay as a custom extension, and + * thus it is available independently from TS 1.2 support itself, including in + * the open source version. + * + * Requires ANJAY_WITH_OBSERVE to be enabled. + */ +/* #undef ANJAY_WITH_CON_ATTR */ + +/** + * Enable support for handling security credentials in the data model using + * structured avs_crypto types. + * + * If the security module is also enabled (see @ref + * ANJAY_WITH_MODULE_SECURITY), it also enables support for passing these + * credentials through such structured types when adding Security object + * instances via the @ref anjay_security_instance_t structure. + */ +/* #undef ANJAY_WITH_SECURITY_STRUCTURED */ + +/** + * Maximum size in bytes supported for the "Public Key or Identity" resource in + * the LwM2M Security object. + * + * If editing this file manually, 256 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 2048. + * Minimal suggested setting for low-resource builds is 256. + */ +#define ANJAY_MAX_PK_OR_IDENTITY_SIZE 256 + +/** + * Maximum size in bytes supported for the "Secret Key" resource in the LwM2M + * Security Object. + * + * If editing this file manually, 128 shall be replaced + * with a positive integer literal. + * + * The default value defined in CMake build scripts is 256. + * Minimal suggested setting for low-resource builds is 128. + */ +#define ANJAY_MAX_SECRET_KEY_SIZE 128 + +/** + * Maximum length supported for stringified floating-point values. + * + * Used when parsing plaintext and SenML JSON content formats - when parsing a + * floating-point value, any string of length equal or greater than this setting + * will automatically be considered invalid, even if it could in theory be + * parsed as a valid number. + * + * If editing this file manually, 64 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 512. + * Minimal suggested setting for low-resource builds is 64. + */ +#define ANJAY_MAX_DOUBLE_STRING_SIZE 64 + +/** + * Maximum length supported for a single Uri-Path or Location-Path segment. + * + * When handling incoming CoAP messages, any Uri-Path or Location-Path option of + * length equal or greater than this setting will be considered invalid. + * + * If editing this file manually, 64 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 256. + * Minimal suggested setting for low-resource builds is 64. + */ +#define ANJAY_MAX_URI_SEGMENT_SIZE 64 + +/** + * Maximum length supported for a single Uri-Query segment. + * + * When handling incoming CoAP messages, any Uri-Query option of length equal or + * greater than this setting will be considered invalid. + * + * If editing this file manually, 64 shall be + * replaced with a positive integer literal. + * + * The default value defined in CMake build scripts is 256. + * Minimal suggested setting for low-resource builds is 64. + */ +#define ANJAY_MAX_URI_QUERY_SEGMENT_SIZE 64 + +/** + * Size of buffer allocated for storing DTLS session state when connection is + * not in use (e.g. during queue mode operation). + * + * If editing this file manually, 1024 shall be + * replaced with a positive integer literal. The default value defined in CMake + * build scripts is 1024. + */ +#define ANJAY_DTLS_SESSION_BUFFER_SIZE 1024 + +/** + * Value of Content-Format used in Send messages. Only a few specific values are + * supported: + * + * - @c AVS_COAP_FORMAT_NONE means no default value is used and Anjay will + * decide the format based on the what is available. + * - @c AVS_COAP_FORMAT_OMA_LWM2M_CBOR Anjay will generate a Send message in + * LwM2M CBOR format. + * - @c AVS_COAP_FORMAT_SENML_CBOR Anjay will generate a Send message in SenML + * CBOR format. + * - @c AVS_COAP_FORMAT_SENML_JSON Anjay will generate a Send message in SenML + * JSON format. + * + * Note that to use a specific format it must be available during compilation. + * + * The default value defined in CMake build scripts is + * AVS_COAP_FORMAT_NONE. + */ +#define ANJAY_DEFAULT_SEND_FORMAT AVS_COAP_FORMAT_NONE + +/** + * Optional Anjay modules. + */ +/**@{*/ +/** + * Enable access_control module (implementation of the Access Control object). + * + * Requires ANJAY_WITH_ACCESS_CONTROL to be enabled. + */ +/* #undef ANJAY_WITH_MODULE_ACCESS_CONTROL */ + +/** + * Enable security module (implementation of the LwM2M Security object). + */ +/* #define ANJAY_WITH_MODULE_SECURITY */ + +/** + * Enable support for hardware security engine in the security module. + * + * This feature allows security credentials provisioned into the LwM2M Security + * object to be automatically moved into a hardware security module. + * + * Requires ANJAY_WITH_MODULE_SECURITY to be enabled in Anjay + * configuration, and at least one of + * AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE or + * AVS_COMMONS_WITH_AVS_CRYPTO_PSK_ENGINE to be enabled in avs_commons + * configuration. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in versions distributed without this feature. + */ +/* #undef ANJAY_WITH_MODULE_SECURITY_ENGINE_SUPPORT */ + +/** + * Enable server module (implementation of the LwM2M Server object). + */ +/* #define ANJAY_WITH_MODULE_SERVER */ + +/** + * Enable fw_update module (implementation of the Firmware Update object). + */ +/* #define ANJAY_WITH_MODULE_FW_UPDATE */ + +/** + * Enable advanced_fw_update module (implementation of the 33629 custom + * Advanced Firmware Update object). + */ +/* #undef ANJAY_WITH_MODULE_ADVANCED_FW_UPDATE */ + +/** + * Disable support for PUSH mode Firmware Update. + * + * Only meaningful if ANJAY_WITH_MODULE_FW_UPDATE is enabled. Requires + * ANJAY_WITH_DOWNLOADER to be enabled. + */ +/* #undef ANJAY_WITHOUT_MODULE_FW_UPDATE_PUSH_MODE */ + +/** + * Enables ipso_objects module (generic implementation of the following kinds of + * the basic sensor and three axis sensor IPSO objects). + */ +/* #define ANJAY_WITH_MODULE_IPSO_OBJECTS */ + +/** + * Enable at_sms module (implementation of an SMS driver for AT modem devices). + * + * Requires ANJAY_WITH_SMS to be enabled and the operating system to + * support the POSIX poll() function. + * + * IMPORTANT: Only available as part of the SMS commercial feature. Ignored in + * the open source version. + */ +/* #undef ANJAY_WITH_MODULE_AT_SMS */ + +/** + * Enable bg96_nidd module (implementation of NB-IoT-based NIDD driver for + * Quectel BG96). + * + * Requires ANJAY_WITH_NIDD to be enabled. + * + * IMPORTANT: Only available as part of the NIDD commercial feature. Ignored + * in the open source version. + */ +/* #undef ANJAY_WITH_MODULE_BG96_NIDD */ + +/** + * Enable bootstrapper module (loader for bootstrap information formatted as per + * the "Storage of LwM2M Bootstrap Information on the Smartcard" appendix to the + * LwM2M TS). + * + * Requires ANJAY_WITH_BOOTSTRAP to be enabled and + * AVS_COMMONS_WITH_AVS_PERSISTENCE to be enabled in avs_commons + * configuration. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_MODULE_BOOTSTRAPPER */ + +/** + * Enable the SIM bootstrap module, which enables reading the SIM bootstrap + * information from a smartcard, which can then be passed through to the + * bootstrapper module. + * + * Requires ANJAY_WITH_MODULE_BOOTSTRAPPER to be enabled. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_WITH_MODULE_SIM_BOOTSTRAP */ + +/** + * Forced ID of the file to read the SIM bootstrap information from. + * + * If not defined (default), the bootstrap information file will be discovered + * through the ODF file, as mandated by the specification. + * + * Requires ANJAY_WITH_MODULE_BOOTSTRAPPER to be enabled. At most one of + * ANJAY_MODULE_SIM_BOOTSTRAP_HARDCODED_FILE_ID and + * ANJAY_MODULE_SIM_BOOTSTRAP_DATA_OID_OVERRIDE_HEX may be defined at the + * same time. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_MODULE_SIM_BOOTSTRAP_HARDCODED_FILE_ID */ + +/** + * Overridden OID of the SIM bootstrap information to look for in the DODF file, + * expressed as a hexlified DER representation (without the header). + * + * This is the hexlified expected value of the 'id' field within the 'OidDO' + * sequence in the DODF file (please refer to the PKCS #15 document for more + * information). + * + * If not defined, the default value of "672b0901", which corresponds to + * OID 2.23.43.9.1 {joint-iso-itu-t(2) international-organizations(23) wap(43) + * oma-lwm2m(9) lwm2m-bootstrap(1)}, will be used. + * + * No other values than the default are valid according to the specification, + * but some SIM cards are known to use other non-standard values, e.g. + * "0604672b0901" - including a superfluous nested BER-TLV header, as + * erroneously illustrated in the EF(DODF-bootstrap) file coding example in + * LwM2M TS 1.2 and earlier (fixed in LwM2M TS 1.2.1) - which is interpreted as + * OID 0.6.4.103.43.9.1 (note that it is invalid as the 0.6 tree does not exist + * in the repository as of writing this note). + * + * Requires ANJAY_WITH_MODULE_BOOTSTRAPPER to be enabled. At most one of + * ANJAY_MODULE_SIM_BOOTSTRAP_HARDCODED_FILE_ID and + * ANJAY_MODULE_SIM_BOOTSTRAP_DATA_OID_OVERRIDE_HEX may be defined at the + * same time. + * + * IMPORTANT: Only available with the bootstrapper feature. Ignored in the open + * source version. + */ +/* #undef ANJAY_MODULE_SIM_BOOTSTRAP_DATA_OID_OVERRIDE_HEX */ + +/** + * Enable factory provisioning module. Data provided during provisioning uses + * SenML CBOR format. + */ +/* #undef ANJAY_WITH_MODULE_FACTORY_PROVISIONING */ + +/** + * Enable oscore module (implementation of the OSCORE object). + * + * IMPORTANT: Only available as part of the OSCORE commercial feature. Ignored + * in the open source version. + */ +/* #undef ANJAY_WITH_MODULE_OSCORE */ +/**@}*/ + +#endif // ANJAY_CONFIG_H diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/coap/avs_coap_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/coap/avs_coap_config.h new file mode 100644 index 0000000000..901d29171a --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/coap/avs_coap_config.h @@ -0,0 +1,171 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Licensed under the AVSystem-5-clause License. + * See the attached LICENSE file for details. + */ + +#ifndef AVS_COAP_CONFIG_H +#define AVS_COAP_CONFIG_H + +/** + * @file avs_coap_config.h + * + * avs_coap library configuration. + * + * The preferred way to compile avs_coap is to use CMake, in which case this + * file will be generated automatically by CMake. + * + * However, to provide compatibility with various build systems used especially + * by embedded platforms, it is alternatively supported to compile avs_coap by + * other means, in which case this file will need to be provided manually. + * + * NOTE: To compile this library without using CMake, you need to + * configure avs_commons first. Please refer to documentation in the + * avs_commons_config.h file (provided in the repository as + * avs_commons_config.h.in) for details. + * + * avs_coap requires the following avs_commons components to be + * enabled: + * + * - @c avs_buffer + * - @c avs_compat_threading + * - @c avs_list + * - @c avs_net + * - @c avs_sched + * - @c avs_stream + * - @c avs_utils + * - @c avs_log (if @c WITH_AVS_COAP_LOGS is enabled) + * - @c avs_persistence (if @c WITH_AVS_COAP_OBSERVE_PERSISTENCE is enabled) + * - @c avs_crypto (if @c WITH_AVS_COAP_OSCORE is enabled) + * + * In the repository, this file is provided as avs_coap_config.h.in, + * intended to be processed by CMake. If editing this file manually, please copy + * or rename it to avs_coap_config.h and for each of the + * \#cmakedefine directives, please either replace it with regular + * \#define to enable it, or comment it out to disable. You may also need + * to replace variables wrapped in \@ signs with concrete values. Please + * refer to the comments above each of the specific definition for details. + * + * If you are editing a file previously generated by CMake, these + * \#cmakedefines will be already replaced by either \#define or + * commented out \#undef directives. + */ + +/** + * Enable support for block-wise transfers (RFC 7959). + * + * If this flag is disabled, attempting to send a message bigger than the + * internal buffer will fail; incoming messages may still carry BLOCK1 or BLOCK2 + * options, but they will not be interpreted by the library in any way. + */ +#define WITH_AVS_COAP_BLOCK + +/** + * Enable support for observations (RFC 7641). + */ +/* #define WITH_AVS_COAP_OBSERVE */ + +/** + * Enable support for observation persistence (avs_coap_observe_persist() + * and avs_coap_observe_restore() calls). + * + * Only meaningful WITH_AVS_COAP_OBSERVE is enabled. + */ +/* #undef WITH_AVS_COAP_OBSERVE_PERSISTENCE */ + +/** + * Enable support for the streaming API + */ +/* #define WITH_AVS_COAP_STREAMING_API */ + +/** + * Enable support for UDP transport. + * + * NOTE: Enabling at least one transport is necessary for the library to be + * useful. + */ +#define WITH_AVS_COAP_UDP + +/** + * Enable support for TCP transport (RFC 8323). + * + * NOTE: Enabling at least one transport is necessary for the library to be + * useful. + */ +/* #define WITH_AVS_COAP_TCP */ + +/** + * Enable support for OSCORE (RFC 8613). + * + * IMPORTANT: Only available with the OSCORE feature. Ignored in the open + * source version. + */ +/* #undef WITH_AVS_COAP_OSCORE */ + +/** + * Use OSCORE version from draft-ietf-core-object-security-08 instead of the + * final version (RFC 8613). + * + * Only meaningful if WITH_AVS_COAP_OSCORE is enabled. + * + * IMPORTANT: Only available with the OSCORE feature. Ignored in the open + * source version. + */ +/* #undef WITH_AVS_COAP_OSCORE_DRAFT_8 */ + +/** + * Maximum number of notification tokens stored to match Reset responses to. + * + * Only meaningful if WITH_AVS_COAP_OBSERVE and WITH_AVS_COAP_UDP + * are enabled. + * + * If editing this file manually, 4 shall be + * replaced with a positive integer literal. The default value defined in CMake + * build scripts is 4. + */ +#define AVS_COAP_UDP_NOTIFY_CACHE_SIZE 4 + +/** + * Enable sending diagnostic payload in error responses. + */ +/* #define WITH_AVS_COAP_DIAGNOSTIC_MESSAGES */ + +/** + * Enable logging in avs_coap. + * + * If this flag is disabled, no logging is compiled into the binary at all. + */ +/* #define WITH_AVS_COAP_LOGS */ + +/** + * Enable TRACE-level logs in avs_coap. + * + * Only meaningful if WITH_AVS_COAP_LOGS is enabled. + */ +/* #undef WITH_AVS_COAP_TRACE_LOGS */ + +/** + * Enable poisoning of unwanted symbols when compiling avs_coap. + * + * Requires a compiler that supports \#pragma GCC poison. + * + * This is mostly useful during development, to ensure that avs_commons do not + * attempt to call functions considered harmful in this library, such as printf. + * This is not guaranteed to work as intended on every platform. + */ +/* #undef WITH_AVS_COAP_POISONING */ + +#endif // AVS_COAP_CONFIG_H diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_commons_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_commons_config.h new file mode 100644 index 0000000000..dc1c523f75 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_commons_config.h @@ -0,0 +1,861 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef AVS_COMMONS_CONFIG_H +#define AVS_COMMONS_CONFIG_H + +/** + * @file avs_commons_config.h + * + * avs_commons library configuration. + * + * The preferred way to compile avs_commons is to use CMake, in which case this + * file will be generated automatically by CMake. + * + * However, to provide compatibility with various build systems used especially + * by embedded platforms, it is alternatively supported to compile avs_commons + * by other means, in which case this file will need to be provided manually. + * + * In the repository, this file is provided as avs_commons_config.h.in, + * intended to be processed by CMake. If editing this file manually, please copy + * or rename it to avs_commons_config.h and for each of the + * #cmakedefine directives, please either replace it with regular + * #define to enable it, or comment it out to disable. You may also need + * to replace variables wrapped in @ signs with concrete values. Please + * refer to the comments above each of the specific definition for details. + * + * If you are editing a file previously generated by CMake, these + * #cmakedefines will be already replaced by either #define or + * commented out #undef directives. + */ + +/** + * Options that describe capabilities of the build environment. + * + * NOTE: If you leave some of these macros undefined, even though the given + * feature is actually available in the system, avs_commons will attempt to use + * its own substitutes, which may be incompatible with the definition in the + * system and lead to undefined behaviour. + */ +/**@{*/ +/** + * Is the target platform big-endian? + * + * If undefined, little-endian is assumed. Mixed-endian architectures are not + * supported. + * + * Affects avs_convert_be*() and avs_[hn]to[hn]*() calls in + * avs_utils and, by extension, avs_persistence. + */ +/* #undef AVS_COMMONS_BIG_ENDIAN */ + +/** + * Is GNU __builtin_add_overflow() extension available? + * + * Affects time handling functions in avs_utils. If disabled, software overflow + * checking will be compiled. Note that this software overflow checking code + * relies on U2 representation of signed integers. + */ +/* #undef AVS_COMMONS_HAVE_BUILTIN_ADD_OVERFLOW */ + +/** + * Is GNU __builtin_mul_overflow() extension available? + * + * Affects time handling functions in avs_utils. If disabled, software overflow + * checking will be compiled. Note that this software overflow checking code + * relies on U2 representation of signed integers. + */ +/* #undef AVS_COMMONS_HAVE_BUILTIN_MUL_OVERFLOW */ + +/** + * Is net/if.h available in the system? + * + * NOTE: If the header is indeed available, but this option is not defined, the + * IF_NAMESIZE macro will be defined publicly by avs_commons + * headers, which may conflict with system definitions. + */ +/* #undef AVS_COMMONS_HAVE_NET_IF_H */ + +/** + * Are GNU diagnostic pragmas (#pragma GCC diagnostic push/pop/ignored) + * available? + * + * If defined, those pragmas will be used to suppress compiler warnings for some + * code known to generate them and cannot be improved in a more robust way, e.g. + * for code that is known to generate warnings from within system headers. + */ +/* #undef AVS_COMMONS_HAVE_PRAGMA_DIAGNOSTIC */ + +/** + * Are GNU visibility pragmas (#pragma GCC visibility push/pop) available? + * + * Meaningful mostly if avs_commons will be directly or indirectly linked into + * a shared library. Causes all symbols except those declared in public headers + * to be hidden, i.e. not exported outside the shared library. If not defined, + * default compiler visibility settings will be used, but you still may use + * compiler flags and linker version scripts to replicate this manually if + * needed. + */ +/* #undef AVS_COMMONS_HAVE_VISIBILITY */ + +/** + * Specify an optional compatibility header that allows use of POSIX-specific + * code that is not compliant with POSIX enough to be compiled directly. + * + * This header, if specified, will be included only by the following components, + * which may be enabled or disabled depending on state of the referenced flags: + * - avs_compat_threading implementation based on POSIX Threads + * (@ref AVS_COMMONS_COMPAT_THREADING_WITH_PTHREAD) + * - default avs_net socket implementation + * (@ref AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET) + * - avs_unit (@ref AVS_COMMONS_WITH_AVS_UNIT) + * - default implementation of avs_time routines + * (@ref AVS_COMMONS_UTILS_WITH_POSIX_AVS_TIME) + * + * Compatibility headers for lwIP and Microsoft Windows are provided with the + * library (see the compat directory). + * + * If this macro is not defined, the afore-mentioned components, if enabled, + * will use system headers directly, assuming they are POSIX-compliant. + * + * If this macro is enabled, the specified file will be included through an + * #include AVS_COMMONS_POSIX_COMPAT_HEADER statement. Thus, if editing + * this file manually, avsystem/commons/lwip-posix-compat.h shall be + * replaced with a path to such file. + */ +#define AVS_COMMONS_POSIX_COMPAT_HEADER \ + "avsystem/commons/xcc_wiznet_posix_compat.h" + +/** + * Set if printf implementation doesn't support 64-bit format specifiers. + * If defined, custom implementation of conversion is used in + * @c AVS_UINT64_AS_STRING instead of using @c snprintf . + */ +#define AVS_COMMONS_WITHOUT_64BIT_FORMAT_SPECIFIERS + +/** + * Set if printf implementation doesn't support floating-point numbers. + * If defined, custom implementation of conversion is used in + * @c AVS_DOUBLE_AS_STRING instead of using @c snprintf . This might increase + * compatibility with some embedded libc implementations that do not provide + * this functionality. + * + * NOTE: In order to keep the custom implementation small in code size, it is + * not intended to be 100% accurate. Rounding errors may occur - according to + * empirical checks, they show up around the 16th significant decimal digit. + */ +#define AVS_COMMONS_WITHOUT_FLOAT_FORMAT_SPECIFIERS + +/**@}*/ + +/** + * Enable poisoning of unwanted symbols when compiling avs_commons. + * + * Requires a compiler that supports #pragma GCC poison. + * + * This is mostly useful during development, to ensure that avs_commons do not + * attempt to call functions considered harmful in this library, such as printf. + * This is not guaranteed to work as intended on every platform, e.g. on macOS + * it is known to generate false positives due to different dependencies between + * system headers. + */ +/* #undef AVS_COMMONS_WITH_POISONING */ + +/** + * Options that control compilation of avs_commons components. + * + * Each of the configuration options below enables, if defined, one of the core + * components of the avs_commons library. + * + * NOTE: Enabling avs_unit will cause an object file with an implementation of + * main() to be generated. + */ +/**@{*/ +/* #define AVS_COMMONS_WITH_AVS_ALGORITHM */ +#define AVS_COMMONS_WITH_AVS_BUFFER +#define AVS_COMMONS_WITH_AVS_COMPAT_THREADING +#define AVS_COMMONS_WITH_AVS_CRYPTO +/* #undef AVS_COMMONS_WITH_AVS_HTTP */ +#define AVS_COMMONS_WITH_AVS_LIST +/* #define AVS_COMMONS_WITH_AVS_LOG */ +#define AVS_COMMONS_WITH_AVS_NET +/* #define AVS_COMMONS_WITH_AVS_PERSISTENCE */ +/* #undef AVS_COMMONS_WITH_AVS_RBTREE */ +/* #define AVS_COMMONS_WITH_AVS_SORTED_SET */ +#define AVS_COMMONS_WITH_AVS_SCHED +/* #define AVS_COMMONS_WITH_AVS_STREAM */ +/* #undef AVS_COMMONS_WITH_AVS_UNIT */ +#define AVS_COMMONS_WITH_AVS_URL +#define AVS_COMMONS_WITH_AVS_UTILS +/* #undef AVS_COMMONS_WITH_AVS_VECTOR */ +/**@}*/ + +/** + * Options that control compilation of avs_compat_threading implementations. + * + * If CMake is not used, in the typical scenario at most one of the following + * implementations may be enabled at the same time. If none is enabled, the + * relevant symbols will need to be provided by the user, if used. + * + * These are meaningful only if AVS_COMMONS_WITH_AVS_COMPAT_THREADING is + * defined. + */ +/**@{*/ +/** + * Enable implementation based on spinlocks. + * + * This implementation is usually very inefficient, and requires C11 stdatomic.h + * header to be available. + */ +/* #undef AVS_COMMONS_COMPAT_THREADING_WITH_ATOMIC_SPINLOCK */ + +/** + * Enable implementation based on the POSIX Threads library. + * + * This implementation is preferred over the spinlock-based one, but the POSIX + * Threads library is normally available only in UNIX-like environments. + */ +/* #undef AVS_COMMONS_COMPAT_THREADING_WITH_PTHREAD */ + +/** + * Is the pthread_condattr_setclock() function available? + * + * This flag only makes sense when + * AVS_COMMONS_COMPAT_THREADING_WITH_PTHREAD is enabled. + * + * If this flag is disabled, or if CLOCK_MONOTONIC macro is not + * available, the avs_condvar_wait() will internally use the real-time + * clock instead of the monotonic clock. Time values will be converted so that + * this change does not affect API usage. + */ +/* #undef AVS_COMMONS_COMPAT_THREADING_PTHREAD_HAVE_PTHREAD_CONDATTR_SETCLOCK */ +/**@}*/ + +/** + * Options that control compilation of code depending on TLS backend library. + * + * If CMake is not used, in the typical scenario at most one of the following + * DTLS backends may be enabled at the same time. If none is enabled, + * functionalities that depends on cryptography will be disabled. + * + * Affects avs_crypto, avs_net, and avs_stream (for the MD5 implementation). + * + * mbed TLS is the main development backend, and is preferred as such. OpenSSL + * backend supports most functionality as well, but is not as thoroughly tested. + * TinyDTLS support is only rudimentary. + */ +/**@{*/ +#define AVS_COMMONS_WITH_MBEDTLS +/* #undef AVS_COMMONS_WITH_OPENSSL */ +/* #undef AVS_COMMONS_WITH_TINYDTLS */ + +/** + * Enable support for custom TLS socket implementation. + * + * If enabled, the user needs to provide their own implementations of + * _avs_net_create_ssl_socket(), _avs_net_create_dtls_socket(), + * _avs_net_initialize_global_ssl_state() and + * _avs_net_cleanup_global_ssl_state(). + */ +/* #undef AVS_COMMONS_WITH_CUSTOM_TLS */ +/**@}*/ + +/** + * Options related to avs_crypto. + */ +/**@{*/ +/** + * Enable AEAD and HKDF support in avs_crypto. Requires MbedTLS in version at + * least 2.14.0, OpenSSL in version at least 1.1.0, or custom implementation in + * case of AVS_COMMONS_WITH_CUSTOM_TLS. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_ADVANCED_FEATURES */ + +/** + * If the TLS backend is either mbed TLS or OpenSSL, enables APIs related to + * public-key cryptography. + * + * Public-key cryptography is not currently supported with TinyDTLS. + * + * It also enables support for X.509 certificates in avs_net, if that module is + * also enabled. + */ +/* #define AVS_COMMONS_WITH_AVS_CRYPTO_PKI */ + +/** + * If the TLS backend is either mbed TLS, OpenSSL or TinyDTLS, enables support + * of pre-shared key security. + * + * PSK is the only supported security mode for the TinyDTLS backend, so this + * option MUST be enabled to utilize it. + * + * It also enables support for pre-shared key security in avs_net, if that + * module is also enabled. + */ +#define AVS_COMMONS_WITH_AVS_CRYPTO_PSK + +/** + * Enables usage of Valgrind API to suppress some of the false positives + * generated by the OpenSSL backend. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_VALGRIND */ + +/** + * Enables high-level support for hardware-based PKI security, i.e. loading, + * generating and managing key pairs and certificates via external engines. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI to be enabled. + * + * An actual implementation is required to use this feature. You may provide + * your own, or use one of the default ones that come with the HSM engine + * commercial feature (see @ref AVS_COMMONS_WITH_MBEDTLS_PKCS11_ENGINE, + * @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE and + * @ref AVS_COMMONS_WITH_OPENSSL_PKCS11_ENGINE). + * + * The functions that need to be provided in case of a custom implementation: + * - avs_crypto_pki_engine_certificate_rm() + * - avs_crypto_pki_engine_certificate_store() + * - avs_crypto_pki_engine_key_gen() + * - avs_crypto_pki_engine_key_rm() + * - avs_crypto_pki_engine_key_store() + * - When targeting the Mbed TLS backend: + * - _avs_crypto_mbedtls_engine_initialize_global_state() + * - _avs_crypto_mbedtls_engine_cleanup_global_state() + * - _avs_crypto_mbedtls_engine_append_cert() + * - _avs_crypto_mbedtls_engine_append_crl() + * - _avs_crypto_mbedtls_engine_load_private_key() + * - When targeting the OpenSSL backend: + * - _avs_crypto_openssl_engine_initialize_global_state() + * - _avs_crypto_openssl_engine_cleanup_global_state() + * - _avs_crypto_openssl_engine_load_certs() + * - _avs_crypto_openssl_engine_load_crls() + * - _avs_crypto_openssl_engine_load_private_key() + * + * External PKI engines are NOT supported in the TinyDTLS backend. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE */ + +/** + * Enables high-level support for hardware-based PSK security, i.e. loading + * and managing PSK keys and identities via external engine. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI to be enabled. + * + * An actual implementation is required to use this feature. You may provide + * your own, or use the default PSA-based one that comes with the HSM engine + * commercial feature (see @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE). + * + * The functions that need to be provided in case of a custom implementation: + * - avs_crypto_psk_engine_identity_store() + * - avs_crypto_psk_engine_identity_rm() + * - avs_crypto_psk_engine_key_store() + * - avs_crypto_psk_engine_key_rm() + * - When targeting the Mbed TLS backend: + * - _avs_crypto_mbedtls_engine_initialize_global_state() + * - _avs_crypto_mbedtls_engine_cleanup_global_state() + * - _avs_crypto_mbedtls_engine_load_psk_key() + * + * External PSK engines are NOT supported in the OpenSSL and TinyDTLS backend. + */ +/* #undef AVS_COMMONS_WITH_AVS_CRYPTO_PSK_ENGINE */ + +/** + * Enables the default implementation of avs_crypto engine, based on Mbed TLS + * and PKCS#11. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE to be enabled. + * + * NOTE: Query string format for this engine is a subset of the PKCS#11 URI + * scheme (see RFC 7512), modelled after the format accepted by libp11 OpenSSL + * engine. + * + * NOTE: The unit tests for this feature depend on SoftHSM and pkcs11-tool. + * These must be installed for the tests to pass. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_MBEDTLS_PKCS11_ENGINE */ + +/** + * Enables the default implementation of avs_crypto engine, based on Mbed TLS + * and Platform Security Architecture (PSA). + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE or + * @ref AVS_COMMONS_WITH_AVS_CRYPTO_PSK_ENGINE to be enabled. + * + * NOTE: Query string format for this engine is: + * + * 
+ * kid=[,lifetime=]|uid=
+ *
+ * + * The values are parsed using strtoull() with base=0, so may be in decimal, + * 0-prefixed octal or 0x-prefixed hexadecimal. On key generation and + * certificate storage, the specified lifetime will be used, or lifetime 1 + * (default persistent storage) will be used if not. On key or certificate use, + * the lifetime of the actual key will be verified if present on the query + * string and the key will be rejected if different. + * + * Certificates are stored as PSA_KEY_TYPE_RAW_DATA key entries containing + * X.509 DER data. Alternatively, the PSA Protected Storage API can be used if + * @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE_PROTECTED_STORAGE is enabled, by + * using the uid=... syntax. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE */ + +/** + * Enables support for the PSA Protected Storage API in the PSA-based avs_crypto + * engine. + * + * Requires @ref AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE to be enabled. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_MBEDTLS_PSA_ENGINE_PROTECTED_STORAGE */ + +/** + * Is the dlsym() function available? + * + * This is currently only used if @ref AVS_COMMONS_WITH_MBEDTLS_PKCS11_ENGINE is + * enabled. If enabled, the PKCS#11 module is loaded dynamically from a library + * specified by the PKCS11_MODULE_PATH environment variable. If disabled, + * a function with the following signature, realizing the PKCS#11 + * C_GetFunctionList method, must be provided manually: + * + * 
+ * CK_RV _avs_crypto_mbedtls_pkcs11_get_function_list(CK_FUNCTION_LIST_PTR_PTR);
+ *
+ */ +/* #undef AVS_COMMONS_HAVE_DLSYM */ + +/** + * Enables the default implementation of avs_crypto engine, based on OpenSSL and + * PKCS#11. + * + * Requires @ref AVS_COMMONS_WITH_AVS_CRYPTO_PKI_ENGINE to be enabled. + * + * NOTE: Query string format for this engine is a subset of the PKCS#11 URI + * scheme (see RFC 7512), modelled after the format accepted by libp11 OpenSSL + * engine. + * + * NOTE: The unit tests for this feature depend on SoftHSM and pkcs11-tool. + * These must be installed for the tests to pass. + * + * IMPORTANT: Only available as part of the HSM support commercial feature. + * Ignored in the open source version. + */ +/* #undef AVS_COMMONS_WITH_OPENSSL_PKCS11_ENGINE */ +/**@}*/ + +/** + * Enable support for HTTP content compression in avs_http. + * + * Requires linking with zlib. + */ +/* #undef AVS_COMMONS_HTTP_WITH_ZLIB */ + +/** + * Options related to avs_log and logging support within avs_commons. + */ +/**@{*/ +/* clang-format off */ +/** + * Size, in bytes, of the avs_log buffer. + * + * Log messages that would (including the level, module name and code location) + * otherwise be longer than this value minus one (for the terminating null + * character) will be truncated. + * + * NOTE: This macro MUST be defined if avs_log is enabled. + * + * If editing this file manually, 512 shall + * be replaced with a positive integer literal. The default value defined in + * CMake build scripts is 512. + */ +#define AVS_COMMONS_LOG_MAX_LINE_LENGTH 256 +/* clang-format on */ + +/** + * Configures avs_log to use a synchronized global buffer instead of allocating + * a buffer on the stack when constructing log messages. + * + * Requires avs_compat_threading to be enabled. + * + * Enabling this option would reduce the stack space required to use avs_log, at + * the expense of global storage and the complexity of using a mutex. + */ +/* #define AVS_COMMONS_LOG_USE_GLOBAL_BUFFER */ + +/** + * Provides a default avs_log handler that prints log messages on stderr. + * + * Disabling this option will cause logs to be discarded by default, until a + * custom log handler is set using avs_log_set_handler(). + */ +/* #undef AVS_COMMONS_LOG_WITH_DEFAULT_HANDLER */ + +/** + * Enables the "micro logs" feature. + * + * Replaces all occurrences of the AVS_DISPOSABLE_LOG() macro with single + * space strings. This is intended to reduce the size of the compiled code, by + * stripping it of almost all log string data. + * + * Note that this setting will propagate both to avs_commons components + * themselves (as all its internal logs make use of AVS_DISPOSABLE_LOG()) + * and the user code that uses it. + */ +/* #undef AVS_COMMONS_WITH_MICRO_LOGS */ + +/** + * Enables logging inside avs_commons. + * + * Requires @ref AVS_COMMONS_WITH_AVS_LOG to be enabled. + * + * If this macro is not defined at avs_commons compile time, calls to avs_log + * will not be generated inside avs_commons components. + */ +/* #define AVS_COMMONS_WITH_INTERNAL_LOGS */ + +/** + * Enables TRACE-level logs inside avs_commons. + * + * Only meaningful if AVS_COMMONS_WITH_INTERNAL_LOGS is enabled. + * + * If this macro is not defined at avs_commons compile time, calls to avs_log + * with the level set to TRACE will not be generated inside avs_commons + * components. + */ +/* #undef AVS_COMMONS_WITH_INTERNAL_TRACE */ + +/** + * Enables external implementation of logger subsystem with provided header. + * + * Default logger implementation can be found in avs_log_impl.h + */ +/* #undef AVS_COMMONS_WITH_EXTERNAL_LOGGER_HEADER */ + +/** + * If specified, the process of checking if avs_log should be written out + * takes place in compile time. + * + * Specify an optional header with a list of modules for which log level + * is set. If a log level for specific module is not set, the DEFAULT level + * will be taken into account. Value of the default logging level is set to + * DEBUG, but can be overwritten in this header file with AVS_LOG_LEVEL_DEFAULT + * define. Messages with lower level than the one set will be removed during + * compile time. Possible values match @ref avs_log_level_t. + * + * That file should contain C preprocesor defines in the: + * - "#define AVS_LOG_LEVEL_FOR_MODULE_ " format, + * where is the module name and is allowed logging level + * - "#define AVS_LOG_LEVEL_DEFAULT " format, where is the + * allowed logging level + * + * Example file content: + * + * + * #ifndef AVS_COMMONS_EXTERNAL_LOG_LEVELS_H + * #define AVS_COMMONS_EXTERNAL_LOG_LEVELS_H + * + * // global log level value + * #define AVS_LOG_LEVEL_DEFAULT INFO + * + * //for "coap" messages only WARNING and ERROR messages will be present + * #define AVS_LOG_LEVEL_FOR_MODULE_coap WARNING + * + * //logs are disable for "net" module + * #define AVS_LOG_LEVEL_FOR_MODULE_net QUIET + * + * #endif + * + */ +#define AVS_COMMONS_WITH_EXTERNAL_LOG_LEVELS_HEADER \ + "avsystem/commons/avs_log_levels.h" + +/** + * Disable log level check in runtime. Allows to save at least 1.3kB of memory. + * + * The macros avs_log_set_level and avs_log_set_default_level + * will not be available. + * + */ +#define AVS_COMMONS_WITHOUT_LOG_CHECK_IN_RUNTIME +/**@}*/ + +/** + * Options related to avs_net. + */ +/**@{*/ +/** + * Enables support for IPv4 connectivity. + * + * At least one of AVS_COMMONS_NET_WITH_IPV4 and AVS_COMMONS_NET_WITH_IPV6 + * MUST be defined if avs_net is enabled. + */ +#define AVS_COMMONS_NET_WITH_IPV4 + +/** + * Enables support for IPv6 connectivity. + * + * At least one of AVS_COMMONS_NET_WITH_IPV4 and AVS_COMMONS_NET_WITH_IPV6 + * MUST be defined if avs_net is enabled. + */ +/* #undef AVS_COMMONS_NET_WITH_IPV6 */ + +/** + * If the TLS backend is set to OpenSSL, enables support for DTLS. + * + * DTLS is always enabled for the mbed TLS and TinyDTLS backends. + */ +/* #undef AVS_COMMONS_NET_WITH_DTLS */ + +/** + * Enables debug logs generated by mbed TLS. + * + * An avs_log-backed handler, logging for the "mbedtls" module on the TRACE + * level, is installed using mbedtls_ssl_conf_dbg() for each (D)TLS + * socket created if this option is enabled. + */ +/* #undef AVS_COMMONS_NET_WITH_MBEDTLS_LOGS */ + +/** + * Enables the default implementation of avs_net TCP and UDP sockets. + * + * Requires either a UNIX-like operating environment, or a compatibility layer + * with a high degree of compatibility with standard BSD sockets with an + * appropriate compatibility header (see @ref AVS_COMMONS_POSIX_COMPAT_HEADER) - + * lwIP and Winsock are currently supported for this scenario. + */ +/* #undef AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET */ + +/** + * Enables support for logging socket communication to file. + * + * If this option is enabled, avs_net_socket_debug() can be used to enable + * logging all communication to a file called DEBUG.log. If disabled, + * avs_net_socket_debug() will always return an error. + */ +/* #define AVS_COMMONS_NET_WITH_SOCKET_LOG */ + +/** + * If the TLS backend is either mbed TLS or OpenSSL, enables support for (D)TLS + * session persistence. + * + * Session persistence is not currently supported for the TinyDTLS backend. + */ +/* #define AVS_COMMONS_NET_WITH_TLS_SESSION_PERSISTENCE */ +/**@}*/ + +/** + * Options related to avs_net's default implementation of TCP and UDP sockets. + * + * These options make sense only when @ref AVS_COMMONS_NET_WITH_POSIX_AVS_SOCKET + * is enabled. They describe capabilities of the Unix-like environment in which + * the library is built. + * + * Note that if @ref AVS_COMMONS_POSIX_COMPAT_HEADER is defined, it might + * redefine these flags independently of the settings in this file. + */ +/**@{*/ +/** + * Is the gai_strerror() function available? + * + * Enabling this flag will provide more detailed log messages in case that + * getaddrinfo() fails. If this flag is disabled, numeric error codes + * values will be logged. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_GAI_STRERROR */ + +/** + * Is the getifaddrs() function available? + * + * Disabling this flag will cause avs_net_socket_interface_name() to use + * a less optimal implementation based on the SIOCGIFCONF ioctl. + * + * If SIOCGIFCONF is not defined, either, then + * avs_net_socket_interface_name() will always return an error. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_GETIFADDRS */ + +/** + * Is the getnameinfo() function available? + * + * Disabling this flag will cause avs_net_socket_receive_from(), + * avs_net_socket_accept(), + * avs_net_resolved_endpoint_get_host_port(), + * avs_net_resolved_endpoint_get_host() and + * avs_net_resolve_host_simple() to use a custom reimplementation of + * getnameinfo() based on inet_ntop(). + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_GETNAMEINFO */ + +/** + * Is the IN6_IS_ADDR_V4MAPPED macro available and usable? + * + * Disabling this flag will cause a custom code that compares IPv6 addresses + * with the ::ffff:0.0.0.0/32 mask to be used instead. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_IN6_IS_ADDR_V4MAPPED */ + +/** + * Should be defined if IPv4-mapped IPv6 addresses (::ffff:0.0.0.0/32) + * are NOT supported by the underlying platform. + * + * Enabling this flag will prevent avs_net from using IPv4-mapped IPv6 addresses + * and instead re-open and re-bind the socket if a connection to an IPv4 address + * is requested on a previously created IPv6 socket. + * + * This may result in otherwise redundant socket(), bind() and + * close() system calls to be performed, but may be necessary for + * interoperability with some platforms. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_WITHOUT_IN6_V4MAPPED_SUPPORT */ + +/** + * Is the inet_ntop() function available? + * + * Disabling this flag will cause an internal implementation of this function + * adapted from BIND 4.9.4 to be used instead. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_INET_NTOP */ + +/** + * Is the poll() function available? + * + * Disabling this flag will cause a less robust code based on select() to + * be used instead. + */ +/* #define AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_POLL */ + +/** + * Is the recvmsg() function available? + * + * Disabling this flag will cause recvfrom() to be used instead. Note + * that for UDP sockets, this will cause false positives for datagram truncation + * detection (AVS_EMSGSIZE) to be reported when the received message is + * exactly the size of the buffer. + */ +/* #undef AVS_COMMONS_NET_POSIX_AVS_SOCKET_HAVE_RECVMSG */ +/**@}*/ + +/** + * Enable thread safety in avs_sched. + * + * Makes all scheduler accesses synchronized and thread-safe, at the cost of + * requiring avs_compat_threading to be enabled, and higher resource usage. + */ +/* #define AVS_COMMONS_SCHED_THREAD_SAFE */ + +/** + * Enable support for file I/O in avs_stream. + * + * Disabling this flag will cause the functions declared in + * avs_stream_file.h to not be defined. + */ +/* #undef AVS_COMMONS_STREAM_WITH_FILE */ + +/** + * Enable usage of backtrace() and backtrace_symbols() when + * reporting assertion failures from avs_unit. + * + * Requires the afore-mentioned GNU-specific functions to be available. + * + * If this flag is disabled, stack traces will not be displayed with assertion + * failures. + */ +/* #undef AVS_COMMONS_UNIT_POSIX_HAVE_BACKTRACE */ + +/** + * Options related to avs_utils. + */ +/**@{*/ +/** + * Enable the default implementation of avs_time_real_now() and + * avs_time_monotonic_now(). + * + * Requires an operating environment that supports a clock_gettime() call + * compatible with POSIX. + */ +/* #undef AVS_COMMONS_UTILS_WITH_POSIX_AVS_TIME */ + +/** + * Enable the default implementation of avs_malloc(), avs_free(), avs_calloc() + * and avs_realloc() that forwards to system malloc(), free(), calloc() and + * realloc() calls. + * + * You might disable this option if for any reason you need to use a custom + * allocator. + */ +/* #define AVS_COMMONS_UTILS_WITH_STANDARD_ALLOCATOR */ + +/** + * Enable the alternate implementation of avs_malloc(), avs_free(), avs_calloc() + * and avs_realloc() that uses system malloc(), free() and realloc() calls, but + * includes additional fixup code that ensures proper alignment to + * AVS_ALIGNOF(avs_max_align_t) (usually 8 bytes on common platforms). + * + * AVS_COMMONS_UTILS_WITH_STANDARD_ALLOCATOR and + * AVS_COMMONS_UTILS_WITH_ALIGNFIX_ALLOCATOR cannot be enabled at the + * same time. + * + * NOTE: This implementation is only intended for platforms where the system + * allocator does not properly conform to the alignment requirements. + * + * It comes with an additional runtime costs: + * + * - AVS_ALIGNOF(avs_max_align_t) bytes (usually 8) of additional + * overhead for each allocated memory block + * - Additional memmove() for every realloc() that returned a block that is not + * properly aligned + * - avs_calloc() is implemented as avs_malloc() followed by an explicit + * memset(); this may be suboptimal on some platforms + * + * If these costs are unacceptable for you, you may want to consider fixing, + * replacing or reconfiguring your system allocator for conformance, or + * implementing a custom one instead. + * + * Please note that some code in avs_commons and dependent projects (e.g. Anjay) + * may include runtime assertions for proper memory alignment that will be + * triggered when using a non-conformant standard allocator. Such allocators are + * relatively common in embedded SDKs. This "alignfix" allocator is intended to + * work around these issues. On some platforms (e.g. x86) those alignment issues + * may not actually cause any problems - so you may want to consider disabling + * runtime assertions instead. Please carefully examine your target platform's + * alignment requirements and behavior of misaligned memory accesses (including + * 64-bit data types such as int64_t and double) before doing so. + */ +/* #undef AVS_COMMONS_UTILS_WITH_ALIGNFIX_ALLOCATOR */ +/**@}*/ + +#endif /* AVS_COMMONS_CONFIG_H */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_log_levels.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_log_levels.h new file mode 100644 index 0000000000..db051626f8 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/avsystem/commons/avs_log_levels.h @@ -0,0 +1,51 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef AVS_COMMONS_EXTERNAL_LOG_LEVELS_H +#define AVS_COMMONS_EXTERNAL_LOG_LEVELS_H + +// global log level value +#define AVS_LOG_LEVEL_DEFAULT INFO + +#ifdef __GNUC__ + +// HACK: Replace path to whole file with just the filename to save up on flash +// usage. +// Older versions of STM32CubeIDE (e.g. 1.7.0) provide __FILENAME__ definition. +// It was later replaced by __FILE_NAME__ which appeared in upstream gcc for +// compability with clang. +// +// Both definitions are not standard. + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wbuiltin-macro-redefined" + +#if defined(__FILE_NAME__) +#undef __FILE__ +#define __FILE__ __FILE_NAME__ +#elif defined(__FILENAME__) +#undef __FILE__ +#define __FILE__ __FILENAME__ +#else +#pragma GCC warning \ + "Both __FILE_NAME__ and __FILENAME__ macros are not available. Logs will include full file paths, which may affect the size of the application binary depending on where the project is located." +#endif // defined(__FILE_NAME__) + +#pragma GCC diagnostic pop + +#endif // __GNUC__ + +#endif diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/chconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/chconf.h new file mode 100644 index 0000000000..91a965a24c --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/chconf.h @@ -0,0 +1,817 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/halconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/halconf.h new file mode 100644 index 0000000000..5a3df87457 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/halconf.h @@ -0,0 +1,553 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/mbedtls/mbedtls_config.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/mbedtls/mbedtls_config.h new file mode 100644 index 0000000000..d34c44a816 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/mbedtls/mbedtls_config.h @@ -0,0 +1,112 @@ +/** + * \file config-ccm-psk-dtls1_2.h + * + * \brief Small configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Minimal configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites + * + * Distinguishing features: + * - Optimized for small code size, low bandwidth (on an unreliable transport), + * and low RAM usage. + * - No asymmetric cryptography (no certificates, no Diffie-Hellman key + * exchange). + * - Fully modern and secure (provided the pre-shared keys are generated and + * stored securely). + * - Very low record overhead with CCM-8. + * - Includes several optional DTLS features typically used in IoT. + * + * See README.txt for usage instructions. + */ + +/* System support */ +//#define MBEDTLS_HAVE_TIME /* Optionally used in Hello messages */ +/* Other MBEDTLS_HAVE_XXX flags irrelevant for this configuration */ + +/* Mbed TLS modules */ +#define MBEDTLS_AES_C +#define MBEDTLS_CCM_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_MD_C +#define MBEDTLS_NET_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_SSL_TLS_C +#define MBEDTLS_TIMING_C + +/* TLS protocol feature support */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#define MBEDTLS_SSL_DTLS_CONNECTION_ID +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/* + * Use only CCM_8 ciphersuites, and + * save ROM and a few bytes of RAM by specifying our own ciphersuite list + */ +#define MBEDTLS_SSL_CIPHERSUITES \ + MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8, \ + MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8 + +/* + * Save RAM at the expense of interoperability: do this only if you control + * both ends of the connection! (See comments in "mbedtls/ssl.h".) + * The optimal size here depends on the typical size of records. + */ +#define MBEDTLS_SSL_IN_CONTENT_LEN 256 +#define MBEDTLS_SSL_OUT_CONTENT_LEN 256 + +/* Save RAM at the expense of ROM */ +#define MBEDTLS_AES_ROM_TABLES + +/* Save some RAM by adjusting to your exact needs */ +#define MBEDTLS_PSK_MAX_LEN 16 /* 128-bits keys are generally enough */ + +/* + * You should adjust this to the exact number of sources you're using: default + * is the "platform_entropy_poll" source, but you may want to add other ones + * Minimum is 2 for the entropy test suite. + */ +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 + +/* These defines are present so that the config modifying scripts can enable + * them during tests/scripts/test-ref-configs.pl */ +//#define MBEDTLS_USE_PSA_CRYPTO +//#define MBEDTLS_PSA_CRYPTO_C + +/* Error messages and TLS debugging traces + * (huge code size increase, needed for tests/ssl-opt.sh) */ +//#define MBEDTLS_DEBUG_C +//#define MBEDTLS_ERROR_C + +/* To prevent using the libc standard calloc() and free(). */ +//#define MBEDTLS_PLATFORM_C +//#define MBEDTLS_PLATFORM_MEMORY + +/* If your system does not have a libc equivalent, you will get compile errors as calloc() or free() cannot be found.* */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/mcuconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/mcuconf.h new file mode 100644 index 0000000000..62969ad8ba --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/cfg/mcuconf.h @@ -0,0 +1,353 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define STM32L4xx_MCUCONF +#define STM32L475_MCUCONF +#define STM32L476_MCUCONF +#define STM32L486_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI16_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_MSIPLL_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_4M +#define STM32_MSISRANGE STM32_MSISRANGE_4M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_MSI +#define STM32_PLLM_VALUE 1 +#define STM32_PLLN_VALUE 80 +#define STM32_PLLP_VALUE 7 +#define STM32_PLLQ_VALUE 6 +#define STM32_PLLR_VALUE 4 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_STOPWUCK STM32_STOPWUCK_MSI +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#define STM32_PLLSAI1N_VALUE 72 +#define STM32_PLLSAI1P_VALUE 7 +#define STM32_PLLSAI1Q_VALUE 6 +#define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2N_VALUE 72 +#define STM32_PLLSAI2P_VALUE 7 +#define STM32_PLLSAI2R_VALUE 6 + +/* + * Peripherals clock sources. + */ +#define STM32_USART1SEL STM32_USART1SEL_SYSCLK +#define STM32_USART2SEL STM32_USART2SEL_SYSCLK +#define STM32_USART3SEL STM32_USART3SEL_SYSCLK +#define STM32_UART4SEL STM32_UART4SEL_SYSCLK +#define STM32_UART5SEL STM32_UART5SEL_SYSCLK +#define STM32_LPUART1SEL STM32_LPUART1SEL_LSE +#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK +#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_LSE +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_LSE +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_ADCSEL STM32_ADCSEL_SYSCLK +#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 +#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI1635_38_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_22_PRIORITY 15 + +#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_LPUART1_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_LPUART1 TRUE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 TRUE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_LPUART1 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_LPUART1_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 + +#endif /* MCUCONF_H */ diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/main.c b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/main.c new file mode 100644 index 0000000000..298008f8f5 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/main.c @@ -0,0 +1,147 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "hal.h" +#include "cmsis_os.h" +#include "avs_test_task.h" +#include "wiznet_chibios.h" + + +/* + * 1) The MAC address usually comes from factory settings which are stored somewhere in ROM. + * 2) The MAC address can be generated by https://gist.githubusercontent.com/pklaus/9638536/raw/2fe075503fda54fc00f5b6d2a4398a7208e085f4/randmac.py + */ +static uint8_t mac_address[6] = { 0x7e, 0x2f, 0xa2, 0xc0, 0xd0, 0xf8 }; + +static const SPIConfig spi_config = { + .circular = false, + .slave = false, + .ssport = PAL_PORT(LINE_W5500_NSS), + .sspad = PAL_PAD(LINE_W5500_NSS), + /* W5500 supports SPI mode 0 and 3. Here we go with mode 3. */ + .cr1 = SPI_CR1_MSTR | /* Master Configuration */ + SPI_CR1_CPHA | /* The second clock transition is the first data capture edge */ + SPI_CR1_CPOL | /* Clock Polarity to 1 when idle */ + SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_BR_2, /* Baud Rate is fPCLK /256 */ + .cr2 = SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2 /* Data size is 8-bit */ +}; + +static const WIZCHIP_ETHSPIConfig eth_config = { + .driver = &SPID1, + .config = &spi_config, + + .reset_line = LINE_W5500_RST, + .reset_trc_delay_ms = 100, + .reset_tpl_delay_ms = 300, + +#if ETH_USE_CALLBACKS == TRUE + .irq_line = LINE_W5500_INT, +#endif +}; + +static const WIZCHIP_ETHPhyConfig phy_config = { + .conf_by = ETH_PHY_CONF_BY_SW, + .mode = ETH_PHY_MODE_AUTO, + .speed = ETH_PHY_SPEED_100, + .duplex = ETH_PHY_DUPLEX_FULL +}; + +static WIZCHIP_NetworkConfig net_config = { + .ip = { .ip = { 0, 0, 0, 0 } }, + .sn = { .sn = { 0, 0, 0, 0 } }, + .gw = { .ip = { 0, 0, 0, 0 } }, + .dns = { .ip = { 0, 0, 0, 0 } }, + .mode = WIZCHIP_NET_ADDRESS_DHCP +}; + +WIZCHIP_MACDriver WIZCHIP0 = { + .spi_config = ð_config, + .phy_config = &phy_config, + .net_config = &net_config, +}; + +static const WIZCHIP_MACConfig mac_config = { + .mac_address = mac_address, +}; + +static const uint8_t PSK_KEY[] = { 5, 4, 3, 2, 1 }; + +static const avs_test_opts_t avs_test_opts = { + .dst_ip_addr = "192.168.2.136", + .dst_port_coap_udp = "5683", + .dst_coap_udp_ssl = "5684", + .dst_coap_tcp = "6683", + .dst_coap_tcp_ssl = "6684", + + .psk_identity = "12345", + .psk_key = PSK_KEY, + .psk_key_size = sizeof(PSK_KEY), +}; + +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + */ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal by default.*/ + osKernelStart(); + + trngStart(&TRNGD1, NULL); + + wizchipInit(); + wizchipStart(&WIZCHIP0, &mac_config); + + wizchipReset(&WIZCHIP0); + + while (!wizchipPhyLinkIsUp(&WIZCHIP0)); + + char chipid[6] = { }; + wizchipGetId(&WIZCHIP0, chipid); + + wizchipSetIPMode(&WIZCHIP0, WIZCHIP_NET_ADDRESS_DHCP); + + uint32_t dhcp_lease_time = 0; + IP_Address_t remote_peer_ip_addr = {}; + const uint32_t dhcp_waittime_sec = 30; + wizchipRefreshDHCPLease(&WIZCHIP0, dhcp_waittime_sec, &dhcp_lease_time); + + const uint32_t dns_waittime_sec = 5; + const char *remote_peer = "www.google.com"; + wizchipDNSQuery(&WIZCHIP0, dns_waittime_sec, remote_peer, &remote_peer_ip_addr); + + avsTestInit(&avs_test_opts); + + /* + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + while (true) { + osDelay(osWaitForever); + } + + return 0; +} diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/readme.txt b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/readme.txt new file mode 100644 index 0000000000..0ea20d5c12 --- /dev/null +++ b/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-WIZNETIOLIBRARY-ANJAY-MBEDTLS/readme.txt @@ -0,0 +1,24 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32L476. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STM32 Nucleo64-L476RG board. + +** The Demo ** + +ETH WIZ CLICK (with W5500) stacked on top of Arduino Uno click shield. + +** Build Procedure ** + +Nothing special, just make it! + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/Makefile b/demos/TI/RT-CC1310-LAUNCHPAD/Makefile new file mode 100644 index 0000000000..b2c14f3979 --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/Makefile @@ -0,0 +1,190 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fno-omit-frame-pointer -falign-functions=16 -fvar-tracking -fvar-tracking-assignments +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m3 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_cc13x0fxx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TI/CC13x0Fxx/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/TI_CC1310_LAUNCHPAD/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/CC13X0F128.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/cfg/chconf.h b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/chconf.h new file mode 100644 index 0000000000..c483489dac --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/cfg/halconf.h b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/halconf.h new file mode 100644 index 0000000000..fcf261aa62 --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/halconf.h @@ -0,0 +1,533 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/cfg/halconf_community.h b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/halconf_community.h new file mode 100644 index 0000000000..43fdbf8690 --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/halconf_community.h @@ -0,0 +1,173 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/cfg/mcuconf.h b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/mcuconf.h new file mode 100644 index 0000000000..28e866694e --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/cfg/mcuconf.h @@ -0,0 +1,38 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +#define CC13x0_MCUCONF + +/* + * HAL driver system settings. + */ +#define TI_SCLK_LF_ENABLED FALSE +#define TI_SCLK_HF_ENABLED TRUE +#define TI_SCLK_LF_AUX_ENABLED TI_SCLK_LF_ENABLED +#define TI_ACLK_ADC_ENABLED TI_SCLK_HF_ENABLED +#define TI_ACLK_REF_ENABLED FALSE +#define TI_ACLK_TDC_ENABLED FALSE + + + +/* + * Peripherals clock sources. + */ + +#endif /* _MCUCONF_H_ */ diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/main.c b/demos/TI/RT-CC1310-LAUNCHPAD/main.c new file mode 100644 index 0000000000..5c386caeb8 --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/main.c @@ -0,0 +1,88 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +//#include "ch_test.h" +//#include "rt_test_root.h" +//#include "oslib_test_root.h" + +static THD_WORKING_AREA(waThread1, 64); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("RedBlinker"); + while (true) { + //palTogglePad(IOPORT3, 3); + chThdSleepMilliseconds(300); + } +} + +static THD_WORKING_AREA(waThread2, 64); +static THD_FUNCTION(Thread2, arg) { + + (void)arg; + chRegSetThreadName("GreenBlinker"); + while (true) { + //palTogglePad(IOPORT4, 4); + chThdSleepMilliseconds(600); + } +} + +static THD_WORKING_AREA(waThread3, 64); +static THD_FUNCTION(Thread3, arg) { + + (void)arg; + chRegSetThreadName("BlueBlinker"); + while (true) { + //palTogglePad(IOPORT1, 2); + chThdSleepMilliseconds(900); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates serial 1 (UART0) using the driver default configuration. + */ + //sdStart(&SD1, NULL); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + chThdCreateStatic(waThread3, sizeof(waThread3), NORMALPRIO, Thread3, NULL); + + //test_execute((BaseSequentialStream *)&SD1, &rt_test_suite); + //test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite); + while (1) { + chThdSleepMilliseconds(2000); + } +} diff --git a/demos/TI/RT-CC1310-LAUNCHPAD/readme.txt b/demos/TI/RT-CC1310-LAUNCHPAD/readme.txt new file mode 100644 index 0000000000..3103fdf836 --- /dev/null +++ b/demos/TI/RT-CC1310-LAUNCHPAD/readme.txt @@ -0,0 +1,12 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 CC1310 Launchpad. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Texas Instruments CC1310 Launchpad. + +** The Demo ** + + +** Build Procedure ** diff --git a/ext/.gitignore b/ext/.gitignore index 2ef4973112..8b242fb614 100644 --- a/ext/.gitignore +++ b/ext/.gitignore @@ -1 +1,6 @@ -SEGGER \ No newline at end of file +SEGGER +wiznet-iolibrary-driver +mbedtls-mbedtls-3.5.0 +avs_commons-5.4.1 +Anjay-3.5.0 +svd diff --git a/ext/Anjay-3.5.0.zip b/ext/Anjay-3.5.0.zip new file mode 100644 index 0000000000..e2d7697753 Binary files /dev/null and b/ext/Anjay-3.5.0.zip differ diff --git a/ext/NUC123AE_v1.svd b/ext/NUC123AE_v1.svd deleted file mode 100755 index 5129b0401a..0000000000 --- a/ext/NUC123AE_v1.svd +++ /dev/null @@ -1,32378 +0,0 @@ - - - NUC123AE_v1 - 1.0 - NUC123AE_v1 SVD file - - - 8 - - 32 - - - - 32 - - read-write - - 0 - - 0 - - - - GCR - GCR Register Map - GCR - 0x50000000 - - - 0x0 - 0x10 - registers - - - 0x18 - 0x4 - registers - - - 0x24 - 0x4 - registers - - - 0x30 - 0x10 - registers - - - 0x44 - 0x4 - registers - - - 0x50 - 0x8 - registers - - - 0xA0 - 0x4 - registers - - - 0xC0 - 0x8 - registers - - - 0xCC - 0x4 - registers - - - 0x100 - 0x4 - registers - - - 0x12C - 0x4 - registers - - - 0x134 - 0x1C - registers - - - 0x158 - 0x4 - registers - - - - PDID - - PDID - Part Device Identification Number Register - 0x0 - read-only - 0x00010000 - 0xFFFF0000 - - - PDID - Part Device Identification Number\nThis register reflects the device part number code. S/W can read this register to identify which device is used. - 0 - 32 - read-only - - - - - RSTSRC - - RSTSRC - System Reset Source Register - 0x4 - read-write - 0x00000000 - 0xFFFFFF00 - - - RSTS_POR - The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No reset from POR or CHIP_RST - #0 - - - 1 - Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_RESET - The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - No reset from /RESET pin - #0 - - - 1 - Pin /RESET had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_WDT - The RSTS_WDT flag is set by the "reset signal" from the watchdog timer to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 2 - 1 - - - 0 - No reset from watchdog timer - #0 - - - 1 - Watchdog timer had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_LVR - The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 3 - 1 - - - 0 - No reset from LVR - #0 - - - 1 - LVR controller had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_BOD - The RSTS_BOD flag is set by the "reset signal" from the Brown-out-Detector to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 4 - 1 - - - 0 - No reset from BOD - #0 - - - 1 - BOD had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_SYS - The RSTS_SYS flag is set by the "reset signal" from the Cortex_M0 kernel to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 5 - 1 - - - 0 - No reset from Cortex_M0 - #0 - - - 1 - Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel - #1 - - - read-write - - - RSTS_CPU - The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero. - 7 - 1 - - - 0 - No reset from CPU - #0 - - - 1 - Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 - #1 - - - read-write - - - - - IPRSTC1 - - IPRSTC1 - IP Reset Control Register1 - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - CHIP_RST - CHIP One-shot Reset (Write-protection Bit)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nFor the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100 - 0 - 1 - - - 0 - CHIP normal operation - #0 - - - 1 - CHIP one-shot reset - #1 - - - read-write - - - CPU_RST - CPU kernel one-shot reset (Write-protection Bit)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100 - 1 - 1 - - - 0 - CPU normal operation - #0 - - - 1 - CPU one-shot reset - #1 - - - read-write - - - PDMA_RST - PDMA Controller Reset (Write-protection)\nSetting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 2 - 1 - - - 0 - PDMA controller normal operation - #0 - - - 1 - PDMA controller reset - #1 - - - read-write - - - - - IPRSTC2 - - IPRSTC2 - IP Reset Control Register2 - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - GPIO_RST - GPIO controller Reset - 1 - 1 - - - 0 - GPIO controller normal operation - #0 - - - 1 - GPIO controller reset - #1 - - - read-write - - - TMR0_RST - Timer0 controller Reset - 2 - 1 - - - 0 - Timer0 controller normal operation - #0 - - - 1 - Timer0 controller reset - #1 - - - read-write - - - TMR1_RST - Timer1 controller Reset - 3 - 1 - - - 0 - Timer1 controller normal operation - #0 - - - 1 - Timer1 controller reset - #1 - - - read-write - - - TMR2_RST - Timer2 controller Reset - 4 - 1 - - - 0 - Timer2 controller normal operation - #0 - - - 1 - Timer2 controller reset - #1 - - - read-write - - - TMR3_RST - Timer3 controller Reset - 5 - 1 - - - 0 - Timer3 controller normal operation - #0 - - - 1 - Timer3 controller reset - #1 - - - read-write - - - I2C0_RST - I2C0 controller Reset - 8 - 1 - - - 0 - I2C0 controller normal operation - #0 - - - 1 - I2C0 controller reset - #1 - - - read-write - - - I2C1_RST - I2C1 controller Reset - 9 - 1 - - - 0 - I2C1 controller normal operation - #0 - - - 1 - I2C1 controller reset - #1 - - - read-write - - - SPI0_RST - SPI0 controller Reset - 12 - 1 - - - 0 - SPI0 controller normal operation - #0 - - - 1 - SPI0 controller reset - #1 - - - read-write - - - SPI1_RST - SPI1 controller Reset - 13 - 1 - - - 0 - SPI1 controller normal operation - #0 - - - 1 - SPI1 controller reset - #1 - - - read-write - - - SPI2_RST - SPI2 controller Reset - 14 - 1 - - - 0 - SPI2 controller normal operation - #0 - - - 1 - SPI2 controller reset - #1 - - - read-write - - - UART0_RST - UART0 controller Reset - 16 - 1 - - - 0 - UART0 controller normal operation - #0 - - - 1 - UART0 controller reset - #1 - - - read-write - - - UART1_RST - UART1 controller Reset - 17 - 1 - - - 0 - UART1 controller normal operation - #0 - - - 1 - UART1 controller reset - #1 - - - read-write - - - PWM03_RST - PWM03 controller Reset - 20 - 1 - - - 0 - PWM03 controller normal operation - #0 - - - 1 - PWM03 controller reset - #1 - - - read-write - - - PS2_RST - PS/2 Controller Reset - 23 - 1 - - - 0 - PS/2 controller normal operation - #0 - - - 1 - PS/2 controller reset - #1 - - - read-write - - - USBD_RST - USB Device Controller Reset - 27 - 1 - - - 0 - USB device controller normal operation - #0 - - - 1 - USB device controller reset - #1 - - - read-write - - - ADC_RST - ADC Controller Reset - 28 - 1 - - - 0 - ADC controller normal operation - #0 - - - 1 - ADC controller reset - #1 - - - read-write - - - I2S_RST - I2S Controller Reset - 29 - 1 - - - 0 - I2S controller normal operation - #0 - - - 1 - I2S controller reset - #1 - - - read-write - - - - - BODCR - - BODCR - Brown-out Detector Control Register - 0x18 - read-write - 0x00000080 - 0xFFFFFFF0 - - - BOD_EN - Brown-out Detector Enable (Write-protection Bit)\nThe default value is set by flash controller user configuration register config0 bit[23].\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 1 - - - 0 - Brown-out Detector function Disabled - #0 - - - 1 - Brown-out Detector function Enabled - #1 - - - read-write - - - BOD_VL - Brown-out Detector Threshold Voltage Selection (Write-protection Bits) - 1 - 2 - read-write - - - BOD_RSTEN - Brown-out Reset Enable (Write-protection Bit)\nWhile the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).\nThe default value is set by flash controller user configuration register config0 bit[20].\nThis bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 3 - 1 - - - 0 - Brown-out "INTERRUPT" function Enabled - #0 - - - 1 - Brown-out "RESET" function Enabled - #1 - - - read-write - - - BOD_INTF - Brown-out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 4 - 1 - - - 0 - Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting - #0 - - - 1 - When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled - #1 - - - read-write - - - BOD_LPM - Brown-out Detector Low power Mode (Write-protection Bit)\nThe BOD consumes about 100 uA in Normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 5 - 1 - - - 0 - BOD operated in Normal mode (Default) - #0 - - - 1 - BOD low power mode Enabled - #1 - - - read-write - - - BOD_OUT - Brown-out Detector Output Status - 6 - 1 - - - 0 - Brown-out Detector output status is 0, which means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 - #0 - - - 1 - Brown-out Detector output status is 1, which means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0 - #1 - - - read-write - - - LVR_EN - Low Voltage Reset Enable (Write-protection Bit)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 7 - 1 - - - 0 - Low Voltage Reset function Disabled - #0 - - - 1 - Low Voltage Reset function Enabled- After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (Default) - #1 - - - read-write - - - - - PORCR - - PORCR - Power-On-Reset Controller Register - 0x24 - read-write - 0x00000000 - 0xFFFFFF00 - - - POR_DIS_CODE - The register is used for the Power-On-Reset enable control (Write-protection Bits)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will become active again when this field is set to another value or chip is reset by other reset source, including:\n/RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 16 - read-write - - - - - GPA_MFP - - GPA_MFP - GPIOA Multiple Function and Input Type Control Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPA_MFP10 - PA.10 Pin Function Selection - 10 - 1 - read-write - - - GPA_MFP11 - PA.11 Pin Function Selection - 11 - 1 - read-write - - - GPA_MFP12 - PA.12 Pin Function Selection - 12 - 1 - read-write - - - GPA_MFP13 - PA.13 Pin Function Selection - 13 - 1 - read-write - - - GPA_MFP14 - PA.14 Pin Function Selection - 14 - 1 - read-write - - - GPA_MFP15 - PA.15 Pin Function Selection - 15 - 1 - read-write - - - GPA_TYPEn - GPA[9:0] are reserved in this chip. - 16 - 16 - - - 0 - GPIOA[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOA[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPB_MFP - - GPB_MFP - GPIOB Multiple Function and Input Type Control Register - 0x34 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPB_MFP0 - PB.0 Pin Function Selection - 0 - 1 - - - 0 - GPIOB[0] is selected to the pin PB.0 - #0 - - - 1 - UART0 RXD0 function is selected to the pin PB.0 - #1 - - - read-write - - - GPB_MFP1 - PB.1 Pin Function Selection - 1 - 1 - - - 0 - GPIOB[1] is selected to the pin PB.1 - #0 - - - 1 - UART0 TXD0 function is selected to the pin PB.1 - #1 - - - read-write - - - GPB_MFP2 - PB.2 Pin Function Selection - 2 - 1 - read-write - - - GPB_MFP3 - PB.3 Pin Function Selection - 3 - 1 - read-write - - - GPB_MFP4 - PB.4 Pin Function Selection - 4 - 1 - read-write - - - GPB_MFP5 - PB. - 5 - 1 - read-write - - - GPB_MFP6 - PB.6 Pin Function Selection - 6 - 1 - read-write - - - GPB_MFP7 - PB.7 Pin Function Selection - 7 - 1 - read-write - - - GPB_MFP8 - PB.8 Pin Function Selection - 8 - 1 - read-write - - - GPB_MFP9 - PB.9 Pin Function Selection - 9 - 1 - read-write - - - GPB_MFP10 - PB.10 Pin Function Selection - 10 - 1 - read-write - - - GPB_MFP12 - PB.12 Pin Function Selection - 12 - 1 - read-write - - - GPB_MFP13 - PB.13 Pin Function Selection - 13 - 1 - read-write - - - GPB_MFP14 - PB.14 Pin Function Selection - 14 - 1 - read-write - - - GPB_MFP15 - PB.15 Pin Function Selection - 15 - 1 - read-write - - - GPB_TYPEn - - 16 - 16 - - - 0 - GPIOB[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOB[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPC_MFP - - GPC_MFP - GPIOC Multiple Function and Input Type Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPC_MFP0 - PC.0 Pin Function Selection - 0 - 1 - read-write - - - GPC_MFP1 - PC.1 Pin Function Selection - 1 - 1 - read-write - - - GPC_MFP2 - PC.2 Pin Function Selection - 2 - 1 - read-write - - - GPC_MFP3 - PC.3 Pin Function Selection - 3 - 1 - read-write - - - GPC_MFP4 - PC.4 Pin Function Selection - 4 - 1 - read-write - - - GPC_MFP5 - PC.5 Pin Function Selection - 5 - 1 - read-write - - - GPC_MFP8 - PC.8 Pin Function Selection - 8 - 1 - read-write - - - GPC_MFP9 - PC.9 Pin Function Selection - 9 - 1 - - - 0 - GPIOC[9] is selected to the pin PC.9 - #0 - - - 1 - SPICLK1 (SPI1) function is selected to the pin PC.9 - #1 - - - read-write - - - GPC_MFP10 - PC.10 Pin Function Selection - 10 - 1 - - - 0 - The GPIOC[10] is selected to the pin PC.10 - #0 - - - 1 - MISO10 (SPI1 master input, slave output pin-0) function is selected to the pin PC.10 - #1 - - - read-write - - - GPC_MFP11 - PC.11 Pin Function Selection - 11 - 1 - - - 0 - GPIOC[11] is selected to the pin PC.11 - #0 - - - 1 - MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PC.11 - #1 - - - read-write - - - GPC_MFP12 - PC.12 Pin Function Selection - 12 - 1 - read-write - - - GPC_MFP13 - PC.13 Pin Function Selection - 13 - 1 - read-write - - - GPC_TYPEn - - 16 - 16 - - - 0 - GPIOC[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOC[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPD_MFP - - GPD_MFP - GPIOD Multiple Function and Input Type Control Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - GPD_MFP0 - PD.0 Pin Function Selection - 0 - 1 - read-write - - - GPD_MFP1 - PD.1 Pin Function Selection - 1 - 1 - read-write - - - GPD_MFP2 - PD.2 Pin Function Selection - 2 - 1 - read-write - - - GPD_MFP3 - PD.3 Pin Function Selection - 3 - 1 - read-write - - - GPD_MFP4 - PD.4 Pin Function Selection - 4 - 1 - read-write - - - GPD_MFP5 - PD.5 Pin Function Selection - 5 - 1 - read-write - - - GPD_MFP8 - PD.8 Pin Function Selection - 8 - 1 - - - 0 - GPIOD[8] is selected to the pin PD8 - #0 - - - 1 - MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PD8 - #1 - - - read-write - - - GPD_MFP9 - PD.9 Pin Function Selection - 9 - 1 - read-write - - - GPD_MFP10 - PD.10 Pin Function Selection - 10 - 1 - - - 0 - GPIOD[10] is selected to the pin PD.10 - #0 - - - 1 - CLKO function is selected to the pin PD.10 - #1 - - - read-write - - - GPD_MFP11 - PD.11 Pin Function Selection - 11 - 1 - - - 0 - GPIOD[11] is selected to the pin PD.11 - #0 - - - 1 - /INT1 function is selected to the pin PD.11 - #1 - - - read-write - - - GPD_TYPEn - - 16 - 16 - - - 0 - GPIOD[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOD[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPF_MFP - - GPF_MFP - GPIOF Multiple Function and Input Type Control Register - 0x44 - read-write - 0x00000000 - 0xFFFFFFF0 - - - GPF_MFP0 - PF.0 Pin Function Selection\nThe value of this bit controlled by CGPFMFP of Config0[27]. This is a read only bit. - 0 - 1 - - - 0 - GPIOF[0] is selected to the pin PF.0 - #0 - - - 1 - XT1_OUT function is selected to the pin PF.0 - #1 - - - read-write - - - GPF_MFP1 - PF.1 Pin Function Selection \nThe value of this bit controlled by CGPFMFP of Config0[27]. This is a read only bit. - 1 - 1 - - - 0 - GPIOF[1] is selected to the pin PF.1 - #0 - - - 1 - XT1_IN function is selected to the pin PF.1 - #1 - - - read-write - - - GPF_MFP2 - PF.2 Pin Function Selection - 2 - 1 - read-write - - - GPF_MFP3 - PF.3 Pin Function Selection - 3 - 1 - read-write - - - GPF_TYPEn - - 16 - 4 - - - 0 - GPIOF[3:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOF[3:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - ALT_MFP - - ALT_MFP - Alternative Multiple Function Pin Control Register - 0x50 - read-write - 0x00000000 - 0xFFFFFFFF - - - PB10_MFP1 - PB.10 Pin Alternate Function Selection - 0 - 1 - read-write - - - PB9_MFP1 - PB.9 Pin Alternate Function Selection - 1 - 1 - read-write - - - PC0_MFP1 - PC.0 Pin Function Selection - 5 - 1 - read-write - - - PC1_MFP1 - PC.1 Pin Alternate Function Selection - 6 - 1 - read-write - - - PC2_MFP1 - PC.2 Pin Alternate Function Selection - 7 - 1 - read-write - - - PC3_MFP1 - PC.3 Pin Alternate Function Selection - 8 - 1 - read-write - - - PA15_MFP1 - PA.15 Pin Alternate Function Selection - 9 - 1 - read-write - - - PB12_MFP1 - PB.12 Pin Alternate Function Selection - 10 - 1 - read-write - - - PA11_MFP1 - PA.11 Pin Function Selection - 11 - 1 - read-write - - - PA10_MFP1 - PA.10 Pin Function Selection - 12 - 1 - read-write - - - PB4_MFP1 - PB.4 Pin Function Selection - 15 - 1 - read-write - - - PB7_MFP1 - PB.7 Pin Alternate Function Selection - 16 - 1 - read-write - - - PB6_MFP1 - PB.6 Pin Alternate Function Selection - 17 - 1 - read-write - - - PB5_MFP1 - PB. - 18 - 1 - read-write - - - PC12_MFP1 - PC.12 Pin Function Selection - 20 - 1 - read-write - - - PC13_MFP1 - PC.13 Pin Function Selection - 21 - 1 - read-write - - - PB15_MFP1 - PB.15 Pin Alternate Function Selection - 24 - 1 - read-write - - - PB2_MFP1 - PB.2 Pin Alternate Function Selection - 26 - 1 - read-write - - - PB3_MFP1 - PB.3 Pin Alternate Function Selection - 27 - 1 - read-write - - - PC4_MFP1 - PC.4 Pin Function Selection - 29 - 1 - read-write - - - PC5_MFP1 - PC.5 Pin Function Selection - 30 - 1 - read-write - - - - - ALT_MFP1 - - ALT_MFP1 - Alternative Multiple Function Pin Control Register1 - 0x54 - read-write - 0x00000000 - 0xFFFFFFFF - - - PD0_MFP1 - PD.0 Pin Function Selection - 16 - 1 - read-write - - - PD1_MFP1 - PD.1 Pin Function Selection - 17 - 1 - read-write - - - PD2_MFP1 - PD.2 Pin Function Selection - 18 - 1 - read-write - - - PD3_MFP1 - PD.3 Pin Function Selection - 19 - 1 - read-write - - - PD4_MFP1 - PD.4 Pin Function Selection - 20 - 1 - read-write - - - PD5_MFP1 - PD.5 Pin Function Selection - 21 - 1 - read-write - - - PF2_MFP1 - PF.2 Pin Function Selection - 24 - 2 - read-write - - - PF3_MFP1 - PF.3 Pin Function Selection - 26 - 2 - read-write - - - - - DFP_CSR - - DFP_CSR - Pin Conflict Status - 0xA0 - read-only - 0x00000000 - 0xFFFFFFFF - - - DFP0_CST - Conflict Status of PD.9 - 0 - 1 - - - 0 - PD.9 worked normally - #0 - - - 1 - PD.9 is conflicted - #1 - - - read-only - - - DFP1_CST - Conflict Status of PD.10 - 1 - 1 - - - 0 - PD.10 worked normally - #0 - - - 1 - PD.10 is conflicted - #1 - - - read-only - - - DFP2_CST - Conflict Status of PD.11 - 2 - 1 - - - 0 - PD.11 worked normally - #0 - - - 1 - PD.11 is conflicted - #1 - - - read-only - - - DFP3_CST - Conflict Status of PB.4 - 3 - 1 - - - 0 - PB.4 worked normally - #0 - - - 1 - PB.4 is conflicted - #1 - - - read-only - - - DFP4_CST - Conflict Status of PB.5 - 4 - 1 - - - 0 - PB.5 worked normally - #0 - - - 1 - PB.5 is conflicted - #1 - - - read-only - - - DFP5_CST - Conflict Status of PB.6 - 5 - 1 - - - 0 - PB.6 worked normally - #0 - - - 1 - PB.6 is conflicted - #1 - - - read-only - - - DFP6_CST - Conflict Status of PB.7 - 6 - 1 - - - 0 - PB.7 worked normally - #0 - - - 1 - PB.7 is conflicted - #1 - - - read-only - - - - - GPA_IOCR - - GPA_IOCR - GPIOA IO Control Register - 0xC0 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPA10_DS - PA.10 Pin Driving Strength Selection - 10 - 1 - - - 0 - PA.10 strong driving strength mode Disabled - #0 - - - 1 - PA.10 strong driving strength mode Enabled - #1 - - - read-write - - - GPA11_DS - PA.11 Pin Driving Strength Selection - 11 - 1 - - - 0 - PA.11 strong driving strength mode Disabled - #0 - - - 1 - PA.11 strong driving strength mode Enabled - #1 - - - read-write - - - - - GPB_IOCR - - GPB_IOCR - GPIOB IO Control Register - 0xC4 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPB4_DS - PB.4 Pin Driving Strength Selection - 4 - 1 - - - 0 - PB.4 strong driving strength mode Disabled - #0 - - - 1 - PB.4 strong driving strength mode Enabled - #1 - - - read-write - - - GPB5_DS - PB.5 Pin Driving Strength Selection - 5 - 1 - - - 0 - PB.5 strong driving strength mode Disabled - #0 - - - 1 - PB.5 strong driving strength mode Enabled - #1 - - - read-write - - - GPB6_DS - PB.6 Pin Driving Strength Selection - 6 - 1 - - - 0 - PB.6 strong driving strength mode Disabled - #0 - - - 1 - PB.6 strong driving strength mode Enabled - #1 - - - read-write - - - GPB7_DS - PB.7 Pin Driving Strength Selection - 7 - 1 - - - 0 - PB.7 strong driving strength mode Disabled - #0 - - - 1 - PB.7 strong driving strength mode Enabled - #1 - - - read-write - - - GPB8_DS - PB.8 Pin Driving Strength Selection - 8 - 1 - - - 0 - PB.8 strong driving strength mode Disabled - #0 - - - 1 - PB.8 strong driving strength mode Enabled - #1 - - - read-write - - - GPB12_DS - PB.12 Pin Driving Strength Selection - 12 - 1 - - - 0 - PB.12 strong driving strength mode Disabled - #0 - - - 1 - PB.12 strong driving strength mode Enabled - #1 - - - read-write - - - GPB13_DS - PB.13 Pin Driving Strength Selection - 13 - 1 - - - 0 - PB.13 strong driving strength mode Disabled - #0 - - - 1 - PB.13 strong driving strength mode Enabled - #1 - - - read-write - - - GPB14_DS - PB.14 Pin Driving Strength Selection - 14 - 1 - - - 0 - PB.14 strong driving strength mode Disabled - #0 - - - 1 - PB.14 strong driving strength mode Enabled - #1 - - - read-write - - - - - GPD_IOCR - - GPD_IOCR - GPIOD IO Control Register - 0xCC - read-write - 0x00000000 - 0xFFFFFFFF - - - GPD8_DS - PD.8 Pin Driving Strength Selection - 8 - 1 - - - 0 - PD.8 strong driving strength mode Disabled - #0 - - - 1 - PD.8 strong driving strength mode Enabled - #1 - - - read-write - - - GPD9_DS - PD.9 Pin Driving Strength Selection - 9 - 1 - - - 0 - PD.9 strong driving strength mode Disabled - #0 - - - 1 - PD.9 strong driving strength mode Enabled - #1 - - - read-write - - - GPD10_DS - PD.10 Pin Driving Strength Selection - 10 - 1 - - - 0 - PD.10 strong driving strength mode Disabled - #0 - - - 1 - PD.10 strong driving strength mode Enabled - #1 - - - read-write - - - GPD11_DS - PD.11 Pin Driving Strength Selection - 11 - 1 - - - 0 - PD.11 strong driving strength mode Disabled - #0 - - - 1 - PD.11 strong driving strength mode Enabled - #1 - - - read-write - - - - - REGWRPROT - - REGWRPROT - Register Write-Protection Control Register - 0x100 - read-write - 0x00000000 - 0xFFFFFFFF - - - REGPROTDIS - Register Write-Protection Disable index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enabled)\nCLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018 - 0 - 1 - - - 0 - Write-protection Enabled for writing protected registers. Any write to the protected register is ignored - #0 - - - 1 - Write-protection Disabled for writing protected registers - #1 - - - read-only - - - REGWRPROT - Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers has to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. - 0 - 8 - write-only - - - - - MFP_CSS - - MFP_CSS - GPIO Multiple Function Control Select Status Register - 0x12C - read-only - 0x00000000 - 0xFFFFFFFF - - - NEW_MFP - New Multiple Function Control Select\nThis is read only bit\nWhen software write any one of new multiple function control registers, this bit will auto set to 1 and the pin's multiple function is controlled by new multiple function control register - 0 - 1 - - - 0 - Old multiple function control is selected - #0 - - - 1 - New multiple function control is selected - #1 - - - read-only - - - - - GPA_MFPH - - GPA_MFPH - GPIOA Multiple Function High Byte Control Register - 0x134 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPA10_MFP - PA.10 Pin Function Selection - 8 - 3 - read-write - - - GPA11_MFP - PA.11 Pin Function Selection - 12 - 3 - read-write - - - GPA12_MFP - PA.12 Pin Function Selection - 16 - 3 - read-write - - - GPA13_MFP - PA.13 Pin Function Selection - 20 - 3 - read-write - - - GPA14_MFP - PA.14 Pin Function Selection - 24 - 3 - read-write - - - GPA15_MFP - PA.15 Pin Function Selection - 28 - 3 - read-write - - - - - GPB_MFPL - - GPB_MFPL - GPIOB Multiple Function Low Byte Control Register - 0x138 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPB0_MFP - PB.0 Pin Function Selection - 0 - 3 - read-write - - - GPB1_MFP - PB.1 Pin Function Selection - 4 - 3 - read-write - - - GPB2_MFP - PB.2 Pin Function Selection - 8 - 3 - read-write - - - GPB3_MFP - PB.3 Pin Function Selection - 12 - 3 - read-write - - - GPB4_MFP - PB.4 Pin Function Selection - 16 - 3 - read-write - - - GPB5_MFP - PB. - 20 - 3 - read-write - - - GPB6_MFP - PB.6 Pin Function Selection - 24 - 3 - read-write - - - GPB7_MFP - PB.7 Pin Function Selection - 28 - 3 - read-write - - - - - GPB_MFPH - - GPB_MFPH - GPIOB Multiple Function High Byte Control Register - 0x13C - read-write - 0x00000000 - 0xFFFFFFFF - - - GPB8_MFP - PB.8 Pin Function Selection - 0 - 3 - read-write - - - GPB9_MFP - PB.9 Pin Function Selection - 4 - 3 - read-write - - - GPB10_MFP - PB.10 Pin Function Selection - 8 - 3 - read-write - - - GPB12_MFP - PB.12 Pin Function Selection - 16 - 3 - read-write - - - GPB13_MFP - PB.13 Pin Function Selection - 20 - 3 - read-write - - - GPB14_MFP - PB.14 Pin Function Selection - 24 - 3 - read-write - - - GPB15_MFP - PB.15 Pin Function Selection - 28 - 3 - read-write - - - - - GPC_MFPL - - GPC_MFPL - GPIOC Multiple Function Low Byte Control Register - 0x140 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPC0_MFP - PC.0 Pin Function Selection - 0 - 3 - read-write - - - GPC1_MFP - PC.1 Pin Function Selection - 4 - 3 - read-write - - - GPC2_MFP - PC.2 Pin Function Selection - 8 - 3 - read-write - - - GPC3_MFP - PC.3 Pin Function Selection - 12 - 3 - read-write - - - GPC4_MFP - PC.4 Pin Function Selection - 16 - 3 - read-write - - - GPC5_MFP - PC.5 Pin Function Selection - 20 - 3 - read-write - - - - - GPC_MFPH - - GPC_MFPH - GPIOC Multiple Function High Byte Control Register - 0x144 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPC8_MFP - PC.8 Pin Function Selection - 0 - 3 - read-write - - - GPC9_MFP - PC.9 Pin Function Selection - 4 - 3 - read-write - - - GPC10_MFP - PC.10 Pin Function Selection - 8 - 3 - read-write - - - GPC11_MFP - PC.11 Pin Function Selection - 12 - 3 - read-write - - - GPC12_MFP - PC.12 Pin Function Selection - 16 - 3 - read-write - - - GPC13_MFP - PC.13 Pin Function Selection - 20 - 3 - read-write - - - - - GPD_MFPL - - GPD_MFPL - GPIOD Multiple Function Low Byte Control Register - 0x148 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPD0_MFP - PD.0 Pin Function Selection - 0 - 3 - read-write - - - GPD1_MFP - PD.1 Pin Function Selection - 4 - 3 - read-write - - - GPD2_MFP - PD.2 Pin Function Selection - 8 - 3 - read-write - - - GPD3_MFP - PD.3 Pin Function Selection - 12 - 3 - read-write - - - GPD4_MFP - PD.4 Pin Function Selection - 16 - 3 - read-write - - - GPD5_MFP - PD.5 Pin Function Selection - 20 - 3 - read-write - - - - - GPD_MFPH - - GPD_MFPH - GPIOD Multiple Function High Byte Control Register - 0x14C - read-write - 0x00000000 - 0xFFFFFFFF - - - GPD8_MFP - PD.8 Pin Function Selection - 0 - 3 - read-write - - - GPD9_MFP - PD.9 Pin Function Selection - 4 - 3 - read-write - - - GPD10_MFP - PD.10 Pin Function Selection - 8 - 3 - read-write - - - GPD11_MFP - PD.11 Pin Function Selection - 12 - 3 - read-write - - - - - GPF_MFPL - - GPF_MFPL - GPIOF Multiple Function Low Byte Control Register - 0x158 - read-write - 0x00001100 - 0xFFFFFF00 - - - GPF0_MFP - PF.0 Pin Function Selection - 0 - 3 - - - 0 - GPIOF[0] is selected to the pin PF.0 - 0 - - - 1 - XT1_OUT function is selected to the pin PF.0 - 1 - - - read-write - - - GPF1_MFP - PF.1 Pin Function Selection - 4 - 3 - - - 0 - GPIOF[1] is selected to the pin PF.1 - 0 - - - 1 - XT1_IN function is selected to the pin PF.1 - 1 - - - read-write - - - GPF2_MFP - PF.2 Pin Function Selection - 8 - 3 - read-write - - - GPF3_MFP - PF.3 Pin Function Selection - 12 - 3 - read-write - - - - - - - SCS - SCS Register Map - SCS - 0xE000E000 - - - 0x10 - 0xC - registers - - - 0x100 - 0x4 - registers - - - 0x180 - 0x4 - registers - - - 0x200 - 0x4 - registers - - - 0x280 - 0x4 - registers - - - 0x400 - 0x20 - registers - - - 0xD00 - 0x8 - registers - - - 0xD0C - 0x8 - registers - - - 0xD1C - 0x8 - registers - - - - SYST_CSR - - SYST_CSR - SysTick Control and Status Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - ENABLE - - 0 - 1 - - - 0 - Counter Disabled - #0 - - - 1 - Counter will operate in a multi-shot manner - #1 - - - read-write - - - TICKINT - - 1 - 1 - - - 0 - Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred - #0 - - - 1 - Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended - #1 - - - read-write - - - CLKSRC - - 2 - 1 - - - 0 - Clock source is (optional) external reference clock - #0 - - - 1 - Core clock used for SysTick - #1 - - - read-write - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. - 16 - 1 - read-write - - - - - SYST_RVR - - SYST_RVR - SysTick Reload Value Register - 0x14 - read-write - 0x00000000 - 0x00000000 - - - RELOAD - The value to load into the Current Value register when the counter reaches 0. - 0 - 24 - read-write - - - - - SYST_CVR - - SYST_CVR - SysTick Current Value Register - 0x18 - read-write - 0x00000000 - 0x00000000 - - - CURRENT - Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). - 0 - 24 - read-write - - - - - NVIC_ISER - - NVIC_ISER - IRQ0 ~ IRQ31 Set-Enable Control Register - 0x100 - read-write - 0x00000000 - 0xFFFFFFFF - - - SETENA - Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Associated interrupt Enabled - 1 - - - read-write - - - - - NVIC_ICER - - NVIC_ICER - IRQ0 ~ IRQ31 Clear-Enable Control Register - 0x180 - read-write - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Associated interrupt Disabled - 1 - - - read-write - - - - - NVIC_ISPR - - NVIC_ISPR - IRQ0 ~ IRQ31 Set-Pending Control Register - 0x200 - read-write - 0x00000000 - 0xFFFFFFFF - - - SETPEND - The register reads back with the current pending state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) - 1 - - - read-write - - - - - NVIC_ICPR - - NVIC_ICPR - IRQ0 ~ IRQ31 Clear-Pending Control Register - 0x280 - read-write - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - The register reads back with the current pending state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Removes the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) - 1 - - - read-write - - - - - NVIC_IPR0 - - NVIC_IPR0 - IRQ0 ~ IRQ3 Interrupt Priority Control Register - 0x400 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority of IRQ0\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_1 - Priority of IRQ1\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_2 - Priority of IRQ2\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_3 - Priority of IRQ3\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR1 - - NVIC_IPR1 - IRQ4 ~ IRQ7 Interrupt Priority Control Register - 0x404 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_4 - Priority of IRQ4\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_5 - Priority of IRQ5\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_6 - Priority of IRQ6\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_7 - Priority of IRQ7\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR2 - - NVIC_IPR2 - IRQ8 ~ IRQ11 Interrupt Priority Control Register - 0x408 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_8 - Priority of IRQ8\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_9 - Priority of IRQ9\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_10 - Priority of IRQ10\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_11 - Priority of IRQ11\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR3 - - NVIC_IPR3 - IRQ12 ~ IRQ15 Interrupt Priority Control Register - 0x40C - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_12 - Priority of IRQ12\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_13 - Priority of IRQ13\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_14 - Priority of IRQ14\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_15 - Priority of IRQ15\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR4 - - NVIC_IPR4 - IRQ16 ~ IRQ19 Interrupt Priority Control Register - 0x410 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_16 - Priority of IRQ16\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_17 - Priority of IRQ17\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_18 - Priority of IRQ18\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_19 - Priority of IRQ19\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR5 - - NVIC_IPR5 - IRQ20 ~ IRQ23 Interrupt Priority Control Register - 0x414 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_20 - Priority of IRQ20\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_21 - Priority of IRQ21\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_22 - Priority of IRQ22\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_23 - Priority of IRQ23\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR6 - - NVIC_IPR6 - IRQ24 ~ IRQ27 Interrupt Priority Control Register - 0x418 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_24 - Priority of IRQ24\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_25 - Priority of IRQ25\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_26 - Priority of IRQ26\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_27 - Priority of IRQ27\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR7 - - NVIC_IPR7 - IRQ28 ~ IRQ31 Interrupt Priority Control Register - 0x41C - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_28 - Priority of IRQ28\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_29 - Priority of IRQ29\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_30 - Priority of IRQ30\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_31 - Priority of IRQ31\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - CPUID - - CPUID - CPUID Register - 0xD00 - read-only - 0x410CC200 - 0xFFFFFFFF - - - REVISION - Reads as 0x0 - 0 - 4 - read-only - - - PARTNO - Reads as 0xC20. - 4 - 12 - read-only - - - PART - Reads as 0xC for ARMv6-M parts - 16 - 4 - read-only - - - IMPLEMENTER - - 24 - 8 - read-only - - - - - ICSR - - ICSR - Interrupt Control and State Register - 0xD04 - read-write - 0x00000000 - 0xFFFFFFFF - - - VECTACTIVE - Contains the active exception number. - 0 - 6 - - - 0 - Thread mode - 0 - - - read-write - - - VECTPENDING - Indicates the exception number of the highest priority pending enabled exception: - 12 - 6 - - - 0 - No pending exceptions - 0 - - - read-write - - - ISRPENDING - Interrupt Pending Flag, Rxcluding NMI and Faults\nThis is a read only bit. - 22 - 1 - - - 0 - Interrupt not pending - #0 - - - 1 - Interrupt pending - #1 - - - read-write - - - ISRPREEMPT - If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit. - 23 - 1 - read-write - - - PENDSTCLR - SysTick Exception Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDST bit, you must "write 0 to PENDSTSET and write 1 to PENDSTCLR" at the same time. - 25 - 1 - - - 0 - No effect - #0 - - - 1 - Removes the pending state from the SysTick exception - #1 - - - read-write - - - PENDSTSET - SysTick Exception Set-pending Bit\nWrite: - 26 - 1 - - - 0 - No effect.\nSysTick exception is not pending - #0 - - - 1 - Changes SysTick exception state to pending.\nSysTick exception is pending - #1 - - - read-write - - - PENDSVCLR - PendSV Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDSV bit, you must "write 0 to PENDSVSET and write 1 to PENDSVCLR" at the same time. - 27 - 1 - - - 0 - No effect - #0 - - - 1 - Removes the pending state from the PendSV exception - #1 - - - read-write - - - PENDSVSET - PendSV Set-pending Bit\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending. - 28 - 1 - - - 0 - No effect.\nPendSV exception is not pending - #0 - - - 1 - Changes PendSV exception state to pending.\nPendSV exception is pending - #1 - - - read-write - - - NMIPENDSET - NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. - 31 - 1 - - - 0 - No effect.\nNMI exception is not pending - #0 - - - 1 - Changes NMI exception state to pending.\nNMI exception is pending - #1 - - - read-write - - - - - AIRCR - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - read-write - 0xFA050000 - 0xFFFFFFFF - - - VECTCLRACTIVE - Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. - 1 - 1 - read-write - - - SYSRESETREQ - Writing this bit 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested.\nThe bit is a write only and self-cleared as part of the reset sequence. - 2 - 1 - read-write - - - VECTORKEY - When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. - 16 - 16 - read-write - - - - - SCR - - SCR - System Control Register - 0xD10 - read-write - 0x00000000 - 0xFFFFFFFF - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - 1 - 1 - - - 0 - Do not sleep when returning to Thread mode - #0 - - - 1 - Enters sleep, or deep sleep, on return from an ISR to Thread mode - #1 - - - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode: - 2 - 1 - - - 0 - Sleep - #0 - - - 1 - Deep sleep - #1 - - - read-write - - - SEVONPEND - Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. - 4 - 1 - - - 0 - Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded - #0 - - - 1 - Enabled events and all interrupts, including disabled interrupts, can wake up the processor - #1 - - - read-write - - - - - SHPR2 - - SHPR2 - System Handler Priority Register 2 - 0xD1C - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_11 - Priority of system handler 11 - SVCall\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - SHPR3 - - SHPR3 - System Handler Priority Register 3 - 0xD20 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_14 - Priority of System Handler 14 - PendSV\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_15 - Priority of System Handler 15 - SysTick\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - - - INT - INT Register Map - INT - 0x50000300 - - - 0x0 - 0x88 - registers - - - - IRQ0_SRC - - IRQ0_SRC - IRQ0 (BOD) interrupt source identity - 0x0 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Interrupt Source\nDefine the interrupt sources for interrupt event. - 0 - 4 - read-only - - - - - IRQ1_SRC - IRQ1_SRC - IRQ1 (BOD) interrupt source identity - 0x4 - - - IRQ2_SRC - IRQ2_SRC - IRQ2 (BOD) interrupt source identity - 0x8 - - - IRQ3_SRC - IRQ3_SRC - IRQ3 (BOD) interrupt source identity - 0xC - - - IRQ4_SRC - IRQ4_SRC - IRQ4 (BOD) interrupt source identity - 0x10 - - - IRQ5_SRC - IRQ5_SRC - IRQ5 (BOD) interrupt source identity - 0x14 - - - IRQ6_SRC - IRQ6_SRC - IRQ6 (BOD) interrupt source identity - 0x18 - - - IRQ7_SRC - IRQ7_SRC - IRQ7 (BOD) interrupt source identity - 0x1C - - - IRQ8_SRC - IRQ8_SRC - IRQ8 (BOD) interrupt source identity - 0x20 - - - IRQ9_SRC - IRQ9_SRC - IRQ9 (BOD) interrupt source identity - 0x24 - - - IRQ10_SRC - IRQ10_SRC - IRQ10 (BOD) interrupt source identity - 0x28 - - - IRQ11_SRC - IRQ11_SRC - IRQ11 (BOD) interrupt source identity - 0x2C - - - IRQ12_SRC - IRQ12_SRC - IRQ12 (BOD) interrupt source identity - 0x30 - - - IRQ13_SRC - IRQ13_SRC - IRQ13 (BOD) interrupt source identity - 0x34 - - - IRQ14_SRC - IRQ14_SRC - IRQ14 (BOD) interrupt source identity - 0x38 - - - IRQ15_SRC - IRQ15_SRC - IRQ15 (BOD) interrupt source identity - 0x3C - - - IRQ16_SRC - IRQ16_SRC - IRQ16 (BOD) interrupt source identity - 0x40 - - - IRQ17_SRC - IRQ17_SRC - IRQ17 (BOD) interrupt source identity - 0x44 - - - IRQ18_SRC - IRQ18_SRC - IRQ18 (BOD) interrupt source identity - 0x48 - - - IRQ19_SRC - IRQ19_SRC - IRQ19 (BOD) interrupt source identity - 0x4C - - - IRQ20_SRC - IRQ20_SRC - IRQ20 (BOD) interrupt source identity - 0x50 - - - IRQ21_SRC - IRQ21_SRC - IRQ21 (BOD) interrupt source identity - 0x54 - - - IRQ22_SRC - IRQ22_SRC - IRQ22 (BOD) interrupt source identity - 0x58 - - - IRQ23_SRC - IRQ23_SRC - IRQ23 (BOD) interrupt source identity - 0x5C - - - IRQ24_SRC - IRQ24_SRC - IRQ24 (BOD) interrupt source identity - 0x60 - - - IRQ25_SRC - IRQ25_SRC - IRQ25 (BOD) interrupt source identity - 0x64 - - - IRQ26_SRC - IRQ26_SRC - IRQ26 (BOD) interrupt source identity - 0x68 - - - IRQ27_SRC - IRQ27_SRC - IRQ27 (BOD) interrupt source identity - 0x6C - - - IRQ28_SRC - IRQ28_SRC - IRQ28 (BOD) interrupt source identity - 0x70 - - - IRQ29_SRC - IRQ29_SRC - IRQ29 (BOD) interrupt source identity - 0x74 - - - IRQ30_SRC - IRQ30_SRC - IRQ30 (BOD) interrupt source identity - 0x78 - - - IRQ31_SRC - IRQ31_SRC - IRQ31 (BOD) interrupt source identity - 0x7C - - - NMI_SEL - - NMI_SEL - NMI Source Interrupt Select Control Register - 0x80 - read-write - 0x00000000 - 0xFFFFFFFF - - - NMI_SEL - NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. - 0 - 5 - read-write - - - NMI_EN - NMI Interrupt Enable - 8 - 1 - - - 0 - NMI interrupt Disabled - #0 - - - 1 - NMI interrupt Enabled - #1 - - - read-write - - - - - MCU_IRQ - - MCU_IRQ - MCU Interrupt Request Source Register - 0x84 - read-write - 0x00000000 - 0xFFFFFFFF - - - MCU_IRQ - MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, Normal mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect. - 0 - 32 - read-write - - - - - - - CLK - CLK Register Map - CLK - 0x50000200 - - - 0x0 - 0x28 - registers - - - 0x2C - 0x4 - registers - - - - PWRCON - - PWRCON - System Power-down Control Register - 0x0 - read-write - 0x00000010 - 0xFFFFFFF0 - - - XTL12M_EN - External 4~24 MHz High Speed Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically - 0 - 1 - - - 0 - External 4~24 MHz high speed crystal Disabled - #0 - - - 1 - External 4~24 MHz high speed crystal Enabled - #1 - - - read-write - - - OSC22M_EN - Internal 22.1184 MHz High Speed Oscillator Enable (Write-protection Bit) - 2 - 1 - - - 0 - Internal 22.1184 MHz high speed oscillator Disabled - #0 - - - 1 - Internal 22.1184 MHz high speed oscillator Enabled - #1 - - - read-write - - - OSC10K_EN - Internal 10 kHz Low Speed Oscillator Enable (Write-protection Bit) - 3 - 1 - - - 0 - Internal 10 kHz low speed oscillator Disabled - #0 - - - 1 - Internal 10 kHz low speed oscillator Enabled - #1 - - - read-write - - - PD_WU_DLY - Enable the Wake-up Delay Counter (Write-protection Bit)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator. - 4 - 1 - - - 0 - Clock cycles delay Disabled - #0 - - - 1 - Clock cycles delay Enabled - #1 - - - read-write - - - PD_WU_INT_EN - Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. - 5 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PD_WU_STS - Power-down Mode Wake-up Interrupt Status\nSet by "Power-down wake-up event", which indicates that resume from Power-down mode" \nThe flag is set if the GPIO, USB, UART, WDT or BOD wake-up occurred.\nWrite 1 to clear the bit to zero.\nNote: This bit works only when PD_WU_INT_EN (PWRCON[5]) set to 1. - 6 - 1 - read-write - - - PWR_DOWN_EN - System Power-down Enable Bit (Write-protection Bit)\nWhen this bit is set to 1, the chip Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit.\n(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) If the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. User needs to set this bit again for next Power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the external 32.768 kHz low speed crystal and internal 10 kHz low speed oscillator are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low speed crystal or the internal 10 kHz low speed oscillator. - 7 - 1 - - - 0 - Chip operating normally or chip in Idle mode because of WFI command - #0 - - - 1 - Chip entering the Power-down mode instantly or wait CPU sleep command WFI - #1 - - - read-write - - - PD_WAIT_CPU - Power-down Entry Conditions Control (Write-protection Bit) - 8 - 1 - - - 0 - Chip entering Power-down mode when the PWR_DOWN_EN bit is set to 1 - #0 - - - 1 - Chip entering Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction - #1 - - - read-write - - - - - AHBCLK - - AHBCLK - AHB Devices Clock Enable Control Register - 0x4 - read-write - 0x00000004 - 0xFFFFFFFF - - - PDMA_EN - PDMA Controller Clock Enable Control - 1 - 1 - - - 0 - PDMA engine clock Disabled - #0 - - - 1 - PDMA engine clock Enabled - #1 - - - read-write - - - ISP_EN - Flash ISP Controller Clock Enable Control - 2 - 1 - - - 0 - Flash ISP engine clock Disabled - #0 - - - 1 - Flash ISP engine clock Enabled - #1 - - - read-write - - - - - APBCLK - - APBCLK - APB Devices Clock Enable Control Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFF0 - - - WDT_EN - Watchdog Timer Clock Enable (Write-protection Bit)\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 1 - - - 0 - Watchdog Timer Clock Disabled - #0 - - - 1 - Watchdog Timer Clock Enabled - #1 - - - read-write - - - TMR0_EN - Timer0 Clock Enable - 2 - 1 - - - 0 - Timer0 clock Disabled - #0 - - - 1 - Timer0 clock Enabled - #1 - - - read-write - - - TMR1_EN - Timer1 Clock Enable - 3 - 1 - - - 0 - Timer1 clock Disabled - #0 - - - 1 - Timer1 clock Enabled - #1 - - - read-write - - - TMR2_EN - Timer2 Clock Enable - 4 - 1 - - - 0 - Timer2 clock Disabled - #0 - - - 1 - Timer2 clock Enabled - #1 - - - read-write - - - TMR3_EN - Timer3 Clock Enable - 5 - 1 - - - 0 - Timer3 clock Disabled - #0 - - - 1 - Timer3 clock Enabled - #1 - - - read-write - - - FDIV_EN - Frequency Divider Output Clock Enable - 6 - 1 - - - 0 - FDIV clock Disabled - #0 - - - 1 - FDIV clock Enabled - #1 - - - read-write - - - I2C0_EN - I2C0 Clock Enable - 8 - 1 - - - 0 - I2C0 clock Disabled - #0 - - - 1 - I2C0 clock Enabled - #1 - - - read-write - - - I2C1_EN - I2C1 Clock Enable - 9 - 1 - - - 0 - I2C1 clock Disabled - #0 - - - 1 - I2C1 clock Enabled - #1 - - - read-write - - - SPI0_EN - SPI0 Clock Enable - 12 - 1 - - - 0 - SPI0 clock Disabled - #0 - - - 1 - SPI0 clock Enabled - #1 - - - read-write - - - SPI1_EN - SPI1 Clock Enable - 13 - 1 - - - 0 - SPI1 clock Disabled - #0 - - - 1 - SPI1 clock Enabled - #1 - - - read-write - - - SPI2_EN - SPI2 Clock Enable - 14 - 1 - - - 0 - SPI2 clock Disabled - #0 - - - 1 - SPI2 clock Enabled - #1 - - - read-write - - - UART0_EN - UART0 Clock Enable - 16 - 1 - - - 0 - UART0 clock Disabled - #0 - - - 1 - UART0 clock Enabled - #1 - - - read-write - - - UART1_EN - UART1 Clock Enable - 17 - 1 - - - 0 - UART1 clock Disabled - #0 - - - 1 - UART1 clock Enabled - #1 - - - read-write - - - PWM01_EN - PWM_01 Clock Enable - 20 - 1 - - - 0 - PWM01 clock Disabled - #0 - - - 1 - PWM01 clock Enabled - #1 - - - read-write - - - PWM23_EN - PWM_23 Clock Enable - 21 - 1 - - - 0 - PWM23 clock Disabled - #0 - - - 1 - PWM23 clock Enabled - #1 - - - read-write - - - USBD_EN - USB 2.0 FS Device Controller Clock Enable - 27 - 1 - - - 0 - USB clock Disabled - #0 - - - 1 - USB clock Enabled - #1 - - - read-write - - - ADC_EN - Analog-Digital-Converter (ADC) Clock Enable - 28 - 1 - - - 0 - ADC clock Disabled - #0 - - - 1 - ADC clock Enabled - #1 - - - read-write - - - I2S_EN - I2S Clock Enable - 29 - 1 - - - 0 - I2S Clock Disabled - #0 - - - 1 - I2S Clock Enabled - #1 - - - read-write - - - PS2_EN - PS/2 Clock Enable - 31 - 1 - - - 0 - PS/2 clock Disabled - #0 - - - 1 - PS/2 clock Enabled - #1 - - - read-write - - - - - CLKSTATUS - - CLKSTATUS - Clock Status Monitor Register - 0xC - read-write - 0x00000000 - 0xFFFFFF00 - - - XTL12M_STB - External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis is read only bit. - 0 - 1 - - - 0 - External 4~24 MHz high speed crystal clock is not stable or disabled - #0 - - - 1 - External 4~24 MHz high speed crystal clock is stable - #1 - - - read-write - - - PLL_STB - Internal PLL Clock Source Stable Flag\nThis is read only bit. - 2 - 1 - - - 0 - Internal PLL clock is not stable or disabled - #0 - - - 1 - Internal PLL clock is stable - #1 - - - read-write - - - OSC10K_STB - Internal 10 kHz Low Speed Oscillator Clock Source Stable Flag\nThis is read only bit. - 3 - 1 - - - 0 - Internal 10 kHz low speed oscillator clock is not stable or disabled - #0 - - - 1 - Internal 10 kHz low speed oscillator clock is stable - #1 - - - read-write - - - OSC22M_STB - Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis is read only bit - 4 - 1 - - - 0 - Internal 22.1184 MHz high speed oscillator clock is not stable or disabled - #0 - - - 1 - Internal 22.1184 MHz high speed oscillator clock is stable - #1 - - - read-write - - - CLK_SW_FAIL - Clock Switching Fail Flag\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switch system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted.\nThis bit is read only. - 7 - 1 - - - 0 - Clock switching success - #0 - - - 1 - Clock switching failure - #1 - - - read-write - - - - - CLKSEL0 - - CLKSEL0 - Clock Source Select Control Register 0 - 0x10 - read-write - 0x00000030 - 0xFFFFFFF0 - - - HCLK_S - HCLK Clock Source Selection (Write-protection Bits)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 1 - Clock source from PLL clock/2 - #001 - - - 2 - Clock source from PLL clock - #010 - - - 3 - Clock source from internal 10 kHz low speed oscillator clock - #011 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - STCLK_S - Cortex_M0 SysTick Clock Source Selection (Write-protection Bits) - 3 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from external 4~24 MHz high speed crystal clock/2 - #010 - - - 3 - Clock source from HCLK/2 - #011 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock/2 - #111 - - - read-write - - - - - CLKSEL1 - - CLKSEL1 - Clock Source Select Control Register 1 - 0x14 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - WDT_S - Watchdog Timer Clock Source Selection (Write-protection Bits)\nThese bits are protected bits and programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 2 - - - 2 - Clock source from HCLK/2048 clock - #10 - - - 3 - Clock source from internal 10 kHz low speed oscillator clock - #11 - - - read-write - - - ADC_S - ADC Clock Source Selection - 2 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Clock source from PLL clock - #01 - - - 2 - Clock source from HCLK - #10 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - SPI0_S - SPI0 Clock Source Selection - 4 - 1 - - - 0 - Clock source from PLL clock - #0 - - - 1 - Clock source from HCLK - #1 - - - read-write - - - SPI1_S - SPI1 Clock Source Selection - 5 - 1 - - - 0 - Clock source from PLL clock - #0 - - - 1 - Clock source from HCLK - #1 - - - read-write - - - SPI2_S - SPI2 Clock Source Selection - 6 - 1 - - - 0 - Clock source from PLL clock - #0 - - - 1 - Clock source from HCLK - #1 - - - read-write - - - TMR0_S - TIMER0 Clock Source Selection - 8 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Clock source from external clock source TM0 - #011 - - - 5 - Clock source from internal 10 kHz low speed oscillator clock - #101 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - TMR1_S - TIMER1 Clock Source Selection - 12 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Clock source from external clock source TM1 - #011 - - - 5 - Clock source from internal 10 kHz low speed oscillator clock - #101 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - TMR2_S - TIMER2 Clock Source Selection - 16 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Clock source from external clock source TM2 - #011 - - - 5 - Clock source from internal 10 kHz low speed oscillator clock - #101 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - TMR3_S - TIMER3 Clock Source Selection - 20 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Reserved - #011 - - - 5 - Clock source from internal 10 kHz low speed oscillator clock - #101 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - UART_S - UART Clock Source Selection - 24 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Clock source from PLL clock - #01 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - PWM01_S - PWM0 and PWM1 Clock Source Select Bit [1:0]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28]. - 28 - 2 - read-write - - - PWM23_S - PWM2 and PWM3 Clock Source Select Bit [1:0]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30]. - 30 - 2 - read-write - - - - - CLKDIV - - CLKDIV - Clock Divider Number Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - HCLK_N - HCLK Clock Divide Number from HCLK Clock Source - 0 - 4 - read-write - - - USB_N - USB Clock Divide Number from PLL Clock - 4 - 4 - read-write - - - UART_N - UART Clock Divide Number from UART Clock Source - 8 - 4 - read-write - - - ADC_N - ADC Clock Divide Number from ADC Clock Source - 16 - 8 - read-write - - - - - CLKSEL2 - - CLKSEL2 - Clock Source Select Control Register 2 - 0x1C - read-write - 0x000200FF - 0xFFFFFFFF - - - I2S_S - I2S Clock Source Selection - 0 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Clock source from PLL clock - #01 - - - 2 - Clock source from HCLK - #10 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - FRQDIV_S - Clock Divider Clock Source Selection - 2 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Reserved - #01 - - - 2 - Clock source from HCLK - #10 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - PWM01_S - PWM0 and PWM1 Clock Source Select Bit [2]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28]. - 8 - 1 - read-write - - - PWM23_S - PWM2 and PWM3 Clock Source Select Bit [2]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30]. - 9 - 1 - read-write - - - WWDT_S - Windowed-Watchdog Timer Clock Source Selection (Write-protection Bits) - 16 - 2 - - - 2 - Clock source from HCLK/2048 clock - #10 - - - 3 - Clock source from internal 10 kHz low speed oscillator clock - #11 - - - read-write - - - - - PLLCON - - PLLCON - PLL Control Register - 0x20 - read-write - 0x0005C22E - 0xFFFFFFFF - - - FB_DV - PLL Feedback Divider Control Pins\nRefer to the formulas below the table. - 0 - 9 - read-write - - - IN_DV - PLL Input Divider Control Pins\nRefer to the formulas below the table. - 9 - 5 - read-write - - - OUT_DV - PLL Output Divider Control Pins\nRefer to the formulas below the table. - 14 - 2 - read-write - - - PD - Power-down Mode\nIf the PWR_DOWN_EN bit set to 1 in PWRCON register, the PLL will also enter Power-down mode. - 16 - 1 - - - 0 - PLL is in Normal mode - #0 - - - 1 - PLL is in Power-down mode (default) - #1 - - - read-write - - - BP - PLL Bypass Control - 17 - 1 - - - 0 - PLL is in Normal mode (default) - #0 - - - 1 - PLL clock output is the same as clock input (XTALin) - #1 - - - read-write - - - OE - PLL OE (FOUT Enable) Pin Control - 18 - 1 - - - 0 - PLL FOUT Enabled - #0 - - - 1 - PLL FOUT is fixed low - #1 - - - read-write - - - PLL_SRC - PLL Source Clock Selection - 19 - 1 - - - 0 - PLL source clock from external 4~24 MHz high speed crystal - #0 - - - 1 - PLL source clock from internal 22.1184 MHz high speed oscillator - #1 - - - read-write - - - - - FRQDIV - - FRQDIV - Frequency Divider Control Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - FSEL - Divider Output Frequency Select Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]. - 0 - 4 - read-write - - - DIVIDER_EN - Frequency Divider Enable Bit - 4 - 1 - - - 0 - Frequency Divider Disabled - #0 - - - 1 - Frequency Divider Enabled - #1 - - - read-write - - - - - APBDIV - - APBDIV - APB Divider Control Register - 0x2C - read-write - 0x00000000 - 0xFFFFFFFF - - - APBDIV - APB Divider Enable Bit - 0 - 1 - read-write - - - - - - - USB - USB Register Map - USB - 0x40060000 - - - 0x0 - 0x1C - registers - - - 0x90 - 0x4 - registers - - - 0xA4 - 0x4 - registers - - - 0x500 - 0x80 - registers - - - - USB_INTEN - - USB_INTEN - USB Interrupt Enable Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUS_IE - Bus Event Interrupt Enable - 0 - 1 - - - 0 - BUS event interrupt Disabled - #0 - - - 1 - BUS event interrupt Enabled - #1 - - - read-write - - - USB_IE - USB Event Interrupt Enable - 1 - 1 - - - 0 - USB event interrupt Disabled - #0 - - - 1 - USB event interrupt Enabled - #1 - - - read-write - - - FLDET_IE - Floating Detected Interrupt Enable - 2 - 1 - - - 0 - Floating detect Interrupt Disabled - #0 - - - 1 - Floating detect Interrupt Enabled - #1 - - - read-write - - - WAKEUP_IE - USB Wake-up Interrupt Enable - 3 - 1 - - - 0 - Wake-up Interrupt Disabled - #0 - - - 1 - Wake-up Interrupt Enabled - #1 - - - read-write - - - WAKEUP_EN - Wake-up Function Enable - 8 - 1 - - - 0 - USB wake-up function Disabled - #0 - - - 1 - USB wake-up function Enabled - #1 - - - read-write - - - INNAK_EN - Active NAK Function and its Status in IN Token - 15 - 1 - - - 0 - NAK status wasn't updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds NAK after receiving IN token - #0 - - - 1 - NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enables the interrupt event when the device responds NAK after receiving IN token - #1 - - - read-write - - - - - USB_INTSTS - - USB_INTSTS - USB Interrupt Event Status Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUS_STS - BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus. - 0 - 1 - - - 0 - No BUS event occurred - #0 - - - 1 - Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USB_INTSTS[0] - #1 - - - read-write - - - USB_STS - USB event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. - 1 - 1 - - - 0 - No USB event occurred - #0 - - - 1 - USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31]) - #1 - - - read-write - - - FLDET_STS - Floating Detected Interrupt Status - 2 - 1 - - - 0 - There is not attached/detached event in the USB - #0 - - - 1 - There is attached/detached event in the USB bus and it is cleared by writing 1 to USB_INTSTS[2] - #1 - - - read-write - - - WAKEUP_STS - Wake-up Interrupt Status - 3 - 1 - - - 0 - No Wake-up event occurred - #0 - - - 1 - Wake-up event occurred, cleared by writing 1 to USB_INTSTS[3] - #1 - - - read-write - - - EPEVT0 - Endpoint 0's USB Event Status - 16 - 1 - - - 0 - No event occurred on Endpoint 0 - #0 - - - 1 - USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[16] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT1 - Endpoint 1's USB Event Status - 17 - 1 - - - 0 - No event occurred on Endpoint 1 - #0 - - - 1 - USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[17] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT2 - Endpoint 2's USB Event Status - 18 - 1 - - - 0 - No event occurred on Endpoint 2 - #0 - - - 1 - USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[18] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT3 - Endpoint 3's USB Event Status - 19 - 1 - - - 0 - No event occurred on Endpoint 3 - #0 - - - 1 - USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[19] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT4 - Endpoint 4's USB Event Status - 20 - 1 - - - 0 - No event occurred on Endpoint 4 - #0 - - - 1 - USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[20] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT5 - Endpoint 5's USB Event Status - 21 - 1 - - - 0 - No event occurred on Endpoint 5 - #0 - - - 1 - USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[21] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT6 - Endpoint 6's USB Event Status - 22 - 1 - - - 0 - No event occurred on Endpoint 6 - #0 - - - 1 - USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[22] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT7 - Endpoint 7's USB Event Status - 23 - 1 - - - 0 - No event occurred in endpoint 7 - #0 - - - 1 - USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[23] or USB_INTSTS[1] - #1 - - - read-write - - - SETUP - Setup Event Status - 31 - 1 - - - 0 - No Setup event - #0 - - - 1 - Setup event occurred, and cleared by writing 1 to USB_INTSTS[31] - #1 - - - read-write - - - - - USB_FADDR - - USB_FADDR - USB Device Function Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - FADDR - USB device's Function Address - 0 - 7 - read-write - - - - - USB_EPSTS - - USB_EPSTS - USB Endpoint Status Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - OVERRUN - Overrun\nIt indicates that the received data is over the maximum payload number or not. - 7 - 1 - - - 0 - No overrun - #0 - - - 1 - Out data is more than the Max Payload in MXPLD register or the Setup data is more than 8 Bytes - #1 - - - read-only - - - EPSTS0 - Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 8 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS1 - Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 11 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS2 - Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 14 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS3 - Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 17 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS4 - Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 20 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS5 - Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 23 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS6 - Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 26 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS7 - Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint. - 29 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - - - USB_ATTR - - USB_ATTR - USB Bus Status and Attribution Register - 0x10 - read-write - 0x00000040 - 0xFFFFFFFF - - - USBRST - USB Reset Status\nIt is a read only bit. - 0 - 1 - - - 0 - No bus reset - #0 - - - 1 - Bus reset when SE0 (single-ended 0) more than 2.5 us - #1 - - - read-write - - - SUSPEND - Suspend Status\nIt is a read only bit. - 1 - 1 - - - 0 - No bus suspend - #0 - - - 1 - Bus idle more than 3ms, either cable is plugged off or host is sleeping - #1 - - - read-write - - - RESUME - Resume Status\nIt is a read only bit. - 2 - 1 - - - 0 - No bus resume - #0 - - - 1 - Resume from suspend - #1 - - - read-write - - - TIME_OUT - Time Out Status\nIt is a read only bit. - 3 - 1 - - - 0 - No time-out - #0 - - - 1 - No Bus response more than 18 bits time - #1 - - - read-write - - - PHY_EN - PHY Transceiver Function Enable - 4 - 1 - - - 0 - PHY transceiver function Disabled - #0 - - - 1 - PHY transceiver function Enabled - #1 - - - read-write - - - RWAKEUP - Remote Wake-up - 5 - 1 - - - 0 - Release the USB bus from K state - #0 - - - 1 - Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up - #1 - - - read-write - - - USB_EN - USB Controller Enable - 7 - 1 - - - 0 - USB Controller Disabled - #0 - - - 1 - USB Controller Enabled - #1 - - - read-write - - - DPPU_EN - Pull-up resistor on USB_DP enable - 8 - 1 - - - 0 - the pull-up resistor in USB_DP bus Disabled - #0 - - - 1 - Pull-up resistor in USB_DP bus Enabled - #1 - - - read-write - - - PWRDN - Power-down PHY Transceiver, Low Active - 9 - 1 - - - 0 - Power-down related circuit of PHY transceiver - #0 - - - 1 - Turn-on related circuit of PHY transceiver - #1 - - - read-write - - - BYTEM - CPU access USB SRAM Size Mode Selection - 10 - 1 - - - 0 - Word Mode: The size of the transfer from CPU to USB SRAM can be Word only - #0 - - - 1 - Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only - #1 - - - read-write - - - - - USB_FLDET - - USB_FLDET - USB Floating Detected Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - FLDET - Device Floating Detected - 0 - 1 - - - 0 - Controller isn't attached to the USB host - #0 - - - 1 - Controller is attached to the BUS - #1 - - - read-only - - - - - USB_BUFSEG - - USB_BUFSEG - Setup Token Buffer Segmentation Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUFSEG - It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only. - 3 - 6 - read-write - - - - - USB_DRVSE0 - - USB_DRVSE0 - USB Drive SE0 Control Register - 0x90 - read-write - 0x00000001 - 0xFFFFFFFF - - - DRVSE0 - Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low. - 0 - 1 - - - 0 - None - #0 - - - 1 - Force USB PHY transceiver to drive SE0 - #1 - - - read-write - - - - - USB_PDMA - - USB_PDMA - USB PDMA Control Register - 0xA4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_RW - PDMA_RW - 0 - 1 - - - 0 - The PDMA will read data from memory to USB buffer - #0 - - - 1 - The PDMA will read data from USB buffer to memory - #1 - - - read-write - - - PDMA_EN - PDMA Function Enable\nThis bit will be automatically cleared after PDMA transfer done. - 1 - 1 - - - 0 - The PDMA function is not active - #0 - - - 1 - The PDMA function in USB is active - #1 - - - read-write - - - - - USB_BUFSEG0 - - USB_BUFSEG0 - Endpoint 0 Buffer Segmentation Register - 0x500 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUFSEGx - It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description. - 3 - 6 - read-write - - - - - USB_MXPLD0 - - USB_MXPLD0 - Endpoint 0 Maximal Payload Register - 0x504 - read-write - 0x00000000 - 0xFFFFFFFF - - - MXPLD - Maximal Payload\nIt is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It is also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD indicates the data length be transmitted to host\nFor OUT token, the value of MXPLD indicates the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. - 0 - 9 - read-write - - - - - USB_CFG0 - - USB_CFG0 - Endpoint 0 Configuration Register - 0x508 - read-write - 0x00000000 - 0xFFFFFFFF - - - EP_NUM - Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint. - 0 - 4 - read-write - - - ISOCH - Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake. - 4 - 1 - - - 0 - No Isochronous endpoint - #0 - - - 1 - Isochronous endpoint - #1 - - - read-write - - - STATE - Endpoint STATE - 5 - 2 - - - 0 - Endpoint Disabled - #00 - - - 1 - Out endpoint - #01 - - - 2 - IN endpoint - #10 - - - 3 - Undefined - #11 - - - read-write - - - DSQ_SYNC - Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit. - 7 - 1 - - - 0 - DATA0 PID - #0 - - - 1 - DATA1 PID - #1 - - - read-write - - - CSTALL - Clear STALL Response - 9 - 1 - - - 0 - Device Disabled to clear the STALL handshake in the setup stage - #0 - - - 1 - Clear the device to respond STALL handshake in the setup stage - #1 - - - read-write - - - - - USB_CFGP0 - - USB_CFGP0 - Endpoint 0 Set Stall and Clear In/Out Ready Control Register - 0x50C - read-write - 0x00000000 - 0xFFFFFFFF - - - CLRRDY - Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, user can set this bit to 1 to turn it off and it is automatically cleared to 0.\nFor IN token, writing '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, writing '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is written 1 only and is always 0 when it was read back. - 0 - 1 - read-write - - - SSTALL - Set STALL - 1 - 1 - - - 0 - Device Disabled to respond STALL - #0 - - - 1 - Set the device to respond STALL automatically - #1 - - - read-write - - - - - USB_BUFSEG1 - USB_BUFSEG1 - Endpoint 1 Buffer Segmentation Register - 0x510 - - - USB_MXPLD1 - USB_MXPLD1 - Endpoint 1 Maximal Payload Register - 0x514 - - - USB_CFG1 - USB_CFG1 - Endpoint 1 Configuration Register - 0x518 - - - USB_CFGP1 - USB_CFGP1 - Endpoint 1 Set Stall and Clear In/Out Ready Control Register - 0x51C - - - USB_BUFSEG2 - USB_BUFSEG2 - Endpoint 2 Buffer Segmentation Register - 0x520 - - - USB_MXPLD2 - USB_MXPLD2 - Endpoint 2 Maximal Payload Register - 0x524 - - - USB_CFG2 - USB_CFG2 - Endpoint 2 Configuration Register - 0x528 - - - USB_CFGP2 - USB_CFGP2 - Endpoint 2 Set Stall and Clear In/Out Ready Control Register - 0x52C - - - USB_BUFSEG3 - USB_BUFSEG3 - Endpoint 3 Buffer Segmentation Register - 0x530 - - - USB_MXPLD3 - USB_MXPLD3 - Endpoint 3 Maximal Payload Register - 0x534 - - - USB_CFG3 - USB_CFG3 - Endpoint 3 Configuration Register - 0x538 - - - USB_CFGP3 - USB_CFGP3 - Endpoint 3 Set Stall and Clear In/Out Ready Control Register - 0x53C - - - USB_BUFSEG4 - USB_BUFSEG4 - Endpoint 4 Buffer Segmentation Register - 0x540 - - - USB_MXPLD4 - USB_MXPLD4 - Endpoint 4 Maximal Payload Register - 0x544 - - - USB_CFG4 - USB_CFG4 - Endpoint 4 Configuration Register - 0x548 - - - USB_CFGP4 - USB_CFGP4 - Endpoint 4 Set Stall and Clear In/Out Ready Control Register - 0x54C - - - USB_BUFSEG5 - USB_BUFSEG5 - Endpoint 5 Buffer Segmentation Register - 0x550 - - - USB_MXPLD5 - USB_MXPLD5 - Endpoint 5 Maximal Payload Register - 0x554 - - - USB_CFG5 - USB_CFG5 - Endpoint 5 Configuration Register - 0x558 - - - USB_CFGP5 - USB_CFGP5 - Endpoint 5 Set Stall and Clear In/Out Ready Control Register - 0x55C - - - USB_BUFSEG6 - USB_BUFSEG6 - Endpoint 6 Buffer Segmentation Register - 0x560 - - - USB_MXPLD6 - USB_MXPLD6 - Endpoint 6 Maximal Payload Register - 0x564 - - - USB_CFG6 - USB_CFG6 - Endpoint 6 Configuration Register - 0x568 - - - USB_CFGP6 - USB_CFGP6 - Endpoint 6 Set Stall and Clear In/Out Ready Control Register - 0x56C - - - USB_BUFSEG7 - USB_BUFSEG7 - Endpoint 7 Buffer Segmentation Register - 0x570 - - - USB_MXPLD7 - USB_MXPLD7 - Endpoint 7 Maximal Payload Register - 0x574 - - - USB_CFG7 - USB_CFG7 - Endpoint 7 Configuration Register - 0x578 - - - USB_CFGP7 - USB_CFGP7 - Endpoint 7 Set Stall and Clear In/Out Ready Control Register - 0x57C - - - - - GP - GP Register Map - GP - 0x50004000 - - - 0x0 - 0x24 - registers - - - 0x40 - 0x24 - registers - - - 0x80 - 0x24 - registers - - - 0xC0 - 0x24 - registers - - - 0x140 - 0x24 - registers - - - 0x180 - 0x4 - registers - - - 0x228 - 0x90 - registers - - - 0x2C0 - 0x30 - registers - - - 0x340 - 0x10 - registers - - - - GPIOA_PMD - - GPIOA_PMD - GPIO Port A Pin I/O Mode Control - 0x0 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD11 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD12 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD13 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD14 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD15 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOA_OFFD - - GPIOA_OFFD - GPIO Port A Pin OFF Digital Enable - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD11 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD12 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD13 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD14 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD15 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOA_DOUT - - GPIOA_DOUT - GPIO Port A Data Output Value - 0x8 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT11 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT12 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT13 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT14 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT15 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOA_DMASK - - GPIOA_DMASK - GPIO Port A Data Output Write Mask - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK11 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK12 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK13 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK14 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK15 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOA_PIN - - GPIOA_PIN - GPIO Port A Pin Value - 0x10 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN11 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - read-only - - - PIN12 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - read-only - - - PIN13 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - read-only - - - PIN14 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - read-only - - - PIN15 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - read-only - - - - - GPIOA_DBEN - - GPIOA_DBEN - GPIO Port A De-bounce Enable - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN11 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN12 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN13 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN14 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN15 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOA_IMD - - GPIOA_IMD - GPIO Port A Interrupt Mode Control - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD11 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD12 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD13 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD14 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD15 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOA_IEN - - GPIOA_IEN - GPIO Port A Interrupt Enable - 0x1C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOA_ISRC - - GPIOA_ISRC - GPIO Port A Interrupt Trigger Source Indicator - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC11 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC12 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC13 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC14 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC15 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOB_PMD - - GPIOB_PMD - GPIO Port B Pin I/O Mode Control - 0x40 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD4 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD5 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD6 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD7 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD8 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD9 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD12 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD13 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD14 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD15 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOB_OFFD - - GPIOB_OFFD - GPIO Port B Pin OFF Digital Enable - 0x44 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD4 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD5 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD6 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD7 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 23 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD8 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD9 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD12 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD13 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD14 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD15 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOB_DOUT - - GPIOB_DOUT - GPIO Port B Data Output Value - 0x48 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT4 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT5 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT6 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT7 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT8 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT9 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT12 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT13 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT14 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT15 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOB_DMASK - - GPIOB_DMASK - GPIO Port B Data Output Write Mask - 0x4C - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK4 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK5 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK6 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK7 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK8 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK9 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK12 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK13 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK14 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK15 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOB_PIN - - GPIOB_PIN - GPIO Port B Pin Value - 0x50 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - PIN4 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - read-only - - - PIN5 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - read-only - - - PIN6 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - read-only - - - PIN7 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - read-only - - - PIN8 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - read-only - - - PIN9 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - read-only - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN12 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - read-only - - - PIN13 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - read-only - - - PIN14 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - read-only - - - PIN15 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - read-only - - - - - GPIOB_DBEN - - GPIOB_DBEN - GPIO Port B De-bounce Enable - 0x54 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN4 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN5 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN6 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN7 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN8 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN9 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN12 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN13 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN14 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN15 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOB_IMD - - GPIOB_IMD - GPIO Port B Interrupt Mode Control - 0x58 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD4 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD5 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD6 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD7 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD8 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD9 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD12 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD13 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD14 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD15 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOB_IEN - - GPIOB_IEN - GPIO Port B Interrupt Enable - 0x5C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN6 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN7 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN6 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 22 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN7 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 23 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOB_ISRC - - GPIOB_ISRC - GPIO Port B Interrupt Trigger Source Indicator - 0x60 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC4 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC5 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC6 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC7 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC8 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC9 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC12 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC13 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC14 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC15 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOC_PMD - - GPIOC_PMD - GPIO Port C Pin I/O Mode Control - 0x80 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD4 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD5 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD8 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD9 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD11 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD12 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD13 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOC_OFFD - - GPIOC_OFFD - GPIO Port C Pin OFF Digital Enable - 0x84 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD4 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD5 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD8 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD9 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD11 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD12 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD13 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOC_DOUT - - GPIOC_DOUT - GPIO Port C Data Output Value - 0x88 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT4 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT5 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT8 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT9 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT11 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT12 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT13 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOC_DMASK - - GPIOC_DMASK - GPIO Port C Data Output Write Mask - 0x8C - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK4 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK5 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK8 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK9 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK11 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK12 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK13 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOC_PIN - - GPIOC_PIN - GPIO Port C Pin Value - 0x90 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - PIN4 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - read-only - - - PIN5 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - read-only - - - PIN8 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - read-only - - - PIN9 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - read-only - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN11 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - read-only - - - PIN12 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - read-only - - - PIN13 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - read-only - - - - - GPIOC_DBEN - - GPIOC_DBEN - GPIO Port C De-bounce Enable - 0x94 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN4 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN5 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN8 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN9 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN11 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN12 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN13 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOC_IMD - - GPIOC_IMD - GPIO Port C Interrupt Mode Control - 0x98 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD4 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD5 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD8 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD9 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD11 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD12 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD13 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOC_IEN - - GPIOC_IEN - GPIO Port C Interrupt Enable - 0x9C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOC_ISRC - - GPIOC_ISRC - GPIO Port C Interrupt Trigger Source Indicator - 0xA0 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC4 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC5 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC8 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC9 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC11 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC12 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC13 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOD_PMD - - GPIOD_PMD - GPIO Port D Pin I/O Mode Control - 0xC0 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD4 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD5 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD8 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD9 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD11 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOD_OFFD - - GPIOD_OFFD - GPIO Port D Pin OFF Digital Enable - 0xC4 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD4 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD5 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD8 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD9 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD11 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOD_DOUT - - GPIOD_DOUT - GPIO Port D Data Output Value - 0xC8 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT4 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT5 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT8 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT9 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT11 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOD_DMASK - - GPIOD_DMASK - GPIO Port D Data Output Write Mask - 0xCC - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK4 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK5 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK8 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK9 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK11 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOD_PIN - - GPIOD_PIN - GPIO Port D Pin Value - 0xD0 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - PIN4 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - read-only - - - PIN5 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - read-only - - - PIN8 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - read-only - - - PIN9 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - read-only - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN11 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - read-only - - - - - GPIOD_DBEN - - GPIOD_DBEN - GPIO Port D De-bounce Enable - 0xD4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN4 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN5 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN8 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN9 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN11 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOD_IMD - - GPIOD_IMD - GPIO Port D Interrupt Mode Control - 0xD8 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD4 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD5 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD8 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD9 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD11 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOD_IEN - - GPIOD_IEN - GPIO Port D Interrupt Enable - 0xDC - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOD_ISRC - - GPIOD_ISRC - GPIO Port D Interrupt Trigger Source Indicator - 0xE0 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC4 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC5 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC8 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC9 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC11 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOF_PMD - - GPIOF_PMD - GPIO Port F Pin I/O Mode Control - 0x140 - read-write - 0x000000FF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOF_OFFD - - GPIOF_OFFD - GPIO Port F Pin OFF Digital Enable - 0x144 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOF_DOUT - - GPIOF_DOUT - GPIO Port F Data Output Value - 0x148 - read-write - 0x0000000F - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOF_DMASK - - GPIOF_DMASK - GPIO Port F Data Output Write Mask - 0x14C - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOF_PIN - - GPIOF_PIN - GPIO Port F Pin Value - 0x150 - read-only - 0x00000000 - 0xFFFFFFF0 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - - - GPIOF_DBEN - - GPIOF_DBEN - GPIO Port F De-bounce Enable - 0x154 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOF_IMD - - GPIOF_IMD - GPIO Port F Interrupt Mode Control - 0x158 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOF_IEN - - GPIOF_IEN - GPIO Port F Interrupt Enable - 0x15C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOF_ISRC - - GPIOF_ISRC - GPIO Port F Interrupt Trigger Source Indicator - 0x160 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - DBNCECON - - DBNCECON - De-bounce Cycle Control - 0x180 - read-write - 0x00000020 - 0xFFFFFFFF - - - DBCLKSEL - De-bounce sampling cycle selection - 0 - 4 - read-write - - - DBCLKSRC - De-bounce counter clock source select - 4 - 1 - - - 0 - De-bounce counter clock source is the HCLK - #0 - - - 1 - De-bounce counter clock source is the internal 10 kHz low speed oscillator - #1 - - - read-write - - - ICLK_ON - Interrupt clock On mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled - 5 - 1 - - - 0 - Clock Disabled if the GPIOA/B/C/D/F[n] interrupt is disabled - #0 - - - 1 - Interrupt generated circuit clock always Enabled - #1 - - - read-write - - - - - GPIOA10_DOUT - - GPIOA10_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x228 - read-write - 0x00000001 - 0xFFFFFFFF - - - GPIOxx_DOUT - GPIOxx I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\nRead this register to get IO pin status.\nFor example: Writing GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0] - 0 - 1 - - - 0 - Set the corresponding GPIO pin to low - #0 - - - 1 - Set the corresponding GPIO pin to high - #1 - - - read-write - - - - - GPIOA11_DOUT - GPIOA11_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x22C - - - GPIOA12_DOUT - GPIOA12_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x230 - - - GPIOA13_DOUT - GPIOA13_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x234 - - - GPIOA14_DOUT - GPIOA14_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x238 - - - GPIOA15_DOUT - GPIOA15_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x23C - - - GPIOB0_DOUT - GPIOB0_DOUT - GPIO Port A Pin I/O Bit Output/Input Control - 0x240 - - - GPIOB1_DOUT - GPIOB1_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x244 - - - GPIOB2_DOUT - GPIOB2_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x248 - - - GPIOB3_DOUT - GPIOB3_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x24C - - - GPIOB4_DOUT - GPIOB4_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x250 - - - GPIOB5_DOUT - GPIOB5_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x254 - - - GPIOB6_DOUT - GPIOB6_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x258 - - - GPIOB7_DOUT - GPIOB7_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x25C - - - GPIOB8_DOUT - GPIOB8_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x260 - - - GPIOB9_DOUT - GPIOB9_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x264 - - - GPIOB10_DOUT - GPIOB10_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x268 - - - GPIOB11_DOUT - GPIOB11_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x26C - - - GPIOB12_DOUT - GPIOB12_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x270 - - - GPIOB13_DOUT - GPIOB13_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x274 - - - GPIOB14_DOUT - GPIOB14_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x278 - - - GPIOB15_DOUT - GPIOB15_DOUT - GPIO Port B Pin I/O Bit Output/Input Control - 0x27C - - - GPIOC0_DOUT - GPIOC0_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x280 - - - GPIOC1_DOUT - GPIOC1_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x284 - - - GPIOC2_DOUT - GPIOC2_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x288 - - - GPIOC3_DOUT - GPIOC3_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x28C - - - GPIOC4_DOUT - GPIOC4_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x290 - - - GPIOC5_DOUT - GPIOC5_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x294 - - - GPIOC6_DOUT - GPIOC6_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x298 - - - GPIOC7_DOUT - GPIOC7_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x29C - - - GPIOC8_DOUT - GPIOC8_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x2A0 - - - GPIOC9_DOUT - GPIOC9_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x2A4 - - - GPIOC10_DOUT - GPIOC10_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x2A8 - - - GPIOC11_DOUT - GPIOC11_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x2AC - - - GPIOC12_DOUT - GPIOC12_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x2B0 - - - GPIOC13_DOUT - GPIOC13_DOUT - GPIO Port C Pin I/O Bit Output/Input Control - 0x2B4 - - - GPIOD0_DOUT - GPIOD0_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2C0 - - - GPIOD1_DOUT - GPIOD1_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2C4 - - - GPIOD2_DOUT - GPIOD2_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2C8 - - - GPIOD3_DOUT - GPIOD3_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2CC - - - GPIOD4_DOUT - GPIOD4_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2D0 - - - GPIOD5_DOUT - GPIOD5_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2D4 - - - GPIOD6_DOUT - GPIOD6_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2D8 - - - GPIOD7_DOUT - GPIOD7_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2DC - - - GPIOD8_DOUT - GPIOD8_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2E0 - - - GPIOD9_DOUT - GPIOD9_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2E4 - - - GPIOD10_DOUT - GPIOD10_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2E8 - - - GPIOD11_DOUT - GPIOD11_DOUT - GPIO Port D Pin I/O Bit Output/Input Control - 0x2EC - - - GPIOF0_DOUT - GPIOF0_DOUT - GPIO Port F Pin I/O Bit Output/Input Control - 0x340 - - - GPIOF1_DOUT - GPIOF1_DOUT - GPIO Port F Pin I/O Bit Output/Input Control - 0x344 - - - GPIOF2_DOUT - GPIOF2_DOUT - GPIO Port F Pin I/O Bit Output/Input Control - 0x348 - - - GPIOF3_DOUT - GPIOF3_DOUT - GPIO Port F Pin I/O Bit Output/Input Control - 0x34C - - - - - I2C0 - I2C Register Map - I2C - 0x40020000 - - - 0x0 - 0x34 - registers - - - 0x3C - 0x8 - registers - - - - I2CON - - I2CON - I2C Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - AA - Assert Acknowledge Control Bit - 2 - 1 - read-write - - - SI - I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. - 3 - 1 - read-write - - - STO - I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. - 4 - 1 - read-write - - - STA - I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. - 5 - 1 - read-write - - - ENS1 - I2C Controller Enable Bit - 6 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - EI - Enable Interrupt - 7 - 1 - - - 0 - I2C interrupt Disabled - #0 - - - 1 - I2C interrupt Enabled - #1 - - - read-write - - - - - I2CADDR0 - - I2CADDR0 - I2C Slave Address Register0 - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - GC - General Call Function - 0 - 1 - - - 0 - General Call function Disabled - #0 - - - 1 - General Call function Enabled - #1 - - - read-write - - - I2CADDR - I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched. - 1 - 7 - read-write - - - - - I2CDAT - - I2CDAT - I2C Data Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CDAT - I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. - 0 - 8 - read-write - - - - - I2CSTATUS - - I2CSTATUS - I2C Status Register - 0xC - read-only - 0x000000F8 - 0xFFFFFFFF - - - I2CSTATUS - I2C Status Register\nThe status register of I2C: - 0 - 8 - read-only - - - - - I2CLK - - I2CLK - I2C Clock Divided Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CLK - I2C clock divided Register - 0 - 8 - read-write - - - - - I2CTOC - - I2CTOC - I2C Time-Out Counter Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Time-Out Flag - 0 - 1 - - - 0 - Software can clear the flag - #0 - - - 1 - Time-out flag is set by H/W. It can interrupt CPU - #1 - - - read-write - - - DIV4 - Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times. - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - ENTI - Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared. - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - - - I2CADDR1 - I2CADDR1 - I2C Slave Address Register1 - 0x18 - - - I2CADDR2 - I2CADDR2 - I2C Slave Address Register2 - 0x1C - - - I2CADDR3 - I2CADDR3 - I2C Slave Address Register3 - 0x20 - - - I2CADM0 - - I2CADM0 - I2C Slave Address Mask Register0 - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CADM - I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register. - 1 - 7 - - - 0 - Mask Disabled (the received corresponding register bit should be exactly the same as address register.) - 0 - - - 1 - Mask Enabled (the received corresponding address bit is don't care.) - 1 - - - read-write - - - - - I2CADM1 - I2CADM1 - I2C Slave Address Mask Register1 - 0x28 - - - I2CADM2 - I2CADM2 - I2C Slave Address Mask Register2 - 0x2C - - - I2CADM3 - I2CADM3 - I2C Slave Address Mask Register3 - 0x30 - - - I2CWKUPCON - - I2CWKUPCON - I2C Wake-up Control Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - WKUPEN - I2C Wake-up Function Enable - 0 - 1 - - - 0 - I2C wake-up function Disabled - #0 - - - 1 - I2C wake-up function Enabled - #1 - - - read-write - - - - - I2CWKUPSTS - - I2CWKUPSTS - I2C Wake-up Status Register - 0x40 - read-only - 0x00000000 - 0xFFFFFFFF - - - WKUPIF - Wake-up Interrupt Flag\nSoftware can write one to clear this flag - 0 - 1 - - - 0 - Wake-up flag inactive - #0 - - - 1 - Wake-up flag active - #1 - - - read-only - - - - - - - I2C1 - I2C Register Map - I2C - 0x40120000 - - - 0x0 - 0x34 - registers - - - 0x3C - 0x8 - registers - - - - I2CON - - I2CON - I2C Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - AA - Assert Acknowledge Control Bit - 2 - 1 - read-write - - - SI - I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. - 3 - 1 - read-write - - - STO - I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. - 4 - 1 - read-write - - - STA - I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. - 5 - 1 - read-write - - - ENS1 - I2C Controller Enable Bit - 6 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - EI - Enable Interrupt - 7 - 1 - - - 0 - I2C interrupt Disabled - #0 - - - 1 - I2C interrupt Enabled - #1 - - - read-write - - - - - I2CADDR0 - - I2CADDR0 - I2C Slave Address Register0 - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - GC - General Call Function - 0 - 1 - - - 0 - General Call function Disabled - #0 - - - 1 - General Call function Enabled - #1 - - - read-write - - - I2CADDR - I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched. - 1 - 7 - read-write - - - - - I2CDAT - - I2CDAT - I2C Data Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CDAT - I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. - 0 - 8 - read-write - - - - - I2CSTATUS - - I2CSTATUS - I2C Status Register - 0xC - read-only - 0x000000F8 - 0xFFFFFFFF - - - I2CSTATUS - I2C Status Register\nThe status register of I2C: - 0 - 8 - read-only - - - - - I2CLK - - I2CLK - I2C Clock Divided Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CLK - I2C clock divided Register - 0 - 8 - read-write - - - - - I2CTOC - - I2CTOC - I2C Time-Out Counter Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Time-Out Flag - 0 - 1 - - - 0 - Software can clear the flag - #0 - - - 1 - Time-out flag is set by H/W. It can interrupt CPU - #1 - - - read-write - - - DIV4 - Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times. - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - ENTI - Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared. - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - - - I2CADDR1 - I2CADDR1 - I2C Slave Address Register1 - 0x18 - - - I2CADDR2 - I2CADDR2 - I2C Slave Address Register2 - 0x1C - - - I2CADDR3 - I2CADDR3 - I2C Slave Address Register3 - 0x20 - - - I2CADM0 - - I2CADM0 - I2C Slave Address Mask Register0 - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CADM - I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register. - 1 - 7 - - - 0 - Mask Disabled (the received corresponding register bit should be exactly the same as address register.) - 0 - - - 1 - Mask Enabled (the received corresponding address bit is don't care.) - 1 - - - read-write - - - - - I2CADM1 - I2CADM1 - I2C Slave Address Mask Register1 - 0x28 - - - I2CADM2 - I2CADM2 - I2C Slave Address Mask Register2 - 0x2C - - - I2CADM3 - I2CADM3 - I2C Slave Address Mask Register3 - 0x30 - - - I2CWKUPCON - - I2CWKUPCON - I2C Wake-up Control Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - WKUPEN - I2C Wake-up Function Enable - 0 - 1 - - - 0 - I2C wake-up function Disabled - #0 - - - 1 - I2C wake-up function Enabled - #1 - - - read-write - - - - - I2CWKUPSTS - - I2CWKUPSTS - I2C Wake-up Status Register - 0x40 - read-only - 0x00000000 - 0xFFFFFFFF - - - WKUPIF - Wake-up Interrupt Flag\nSoftware can write one to clear this flag - 0 - 1 - - - 0 - Wake-up flag inactive - #0 - - - 1 - Wake-up flag active - #1 - - - read-only - - - - - - - PWMA - PWMA Register Map - PWMA - 0x40040000 - - - 0x0 - 0x48 - registers - - - 0x50 - 0x48 - registers - - - 0xC0 - 0x14 - registers - - - - PPR - - PPR - PWM Group A Pre-scale Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - CP01 - Clock Prescaler 0 (PWM-timer 0 / 1 for Group A)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer. - 0 - 8 - read-write - - - CP23 - Clock Prescaler 2 (PWM Timer2 / 3 for Group A)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer. - 8 - 8 - read-write - - - DZI01 - Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits. - 16 - 8 - read-write - - - DZI23 - Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair for PWM Group A)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits. - 24 - 8 - read-write - - - - - CSR - - CSR - PWM Group A Clock Selector Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - CSR0 - PWM Timer 0 Clock Source Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) - 0 - 3 - read-write - - - CSR1 - PWM Timer 1 Clock Source Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) - 4 - 3 - read-write - - - CSR2 - PWM Timer 2 Clock Source Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) - 8 - 3 - read-write - - - CSR3 - PWM Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B) - 12 - 3 - read-write - - - - - PCR - - PCR - PWM Group A Control Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - CH0EN - PWM-Timer 0 Enable (PWM timer 0 for group A) - 0 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH0PINV - PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 for Group A) - 1 - 1 - - - 0 - PWM0 output polar inverse Disabled - #0 - - - 1 - PWM0 output polar inverse Enabled - #1 - - - read-write - - - CH0INV - PWM-Timer 0 Output Inverter Enable (PWM Timer 0 for Group A) - 2 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH0MOD - PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0 for Group A)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be clear. - 3 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-reload mode - #1 - - - read-write - - - DZEN01 - Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A )\nNote: When dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A. - 4 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - DZEN23 - Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A)\nNote: When dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. - 5 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CH1EN - PWM-Timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) - 8 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH1PINV - PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A) - 9 - 1 - - - 0 - PWM1 output polar inverse Disabled - #0 - - - 1 - PWM1 output polar inverse Enabled - #1 - - - read-write - - - CH1INV - PWM-Timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) - 10 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH1MOD - PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1 for Group A)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be clear. - 11 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-load mode - #1 - - - read-write - - - CH2EN - PWM-Timer 2 Enable (PWM Timer 2 for Group A) - 16 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH2PINV - PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A) - 17 - 1 - - - 0 - PWM2 output polar inverse Disabled - #0 - - - 1 - PWM2 output polar inverse Enabled - #1 - - - read-write - - - CH2INV - PWM-Timer 2 Output Inverter Enable (PWM Timer 2 for Group A) - 18 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH2MOD - PWM-Timer 2 Auto-reload/One-Shot Mode (PWM Timer 2 for Group A)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be clear. - 19 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-reload mode - #1 - - - read-write - - - CH3EN - PWM-Timer 3 Enable (PWM Timer 3 for Group A) - 24 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH3PINV - PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 for Group A) - 25 - 1 - - - 0 - PWM3 output polar inverse Disabled - #0 - - - 1 - PWM3 output polar inverse Enabled - #1 - - - read-write - - - CH3INV - PWM-Timer 3 Output Inverter Enable (PWM Timer 3 for Group A) - 26 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH3MOD - PWM-Timer 3 Auto-reload/One-Shot Mode (PWM Timer 3 for Group A)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be clear. - 27 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-reload mode - #1 - - - read-write - - - PWMTYPE01 - PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A) - 30 - 1 - - - 0 - Edge-aligned type - #0 - - - 1 - Center-aligned type - #1 - - - read-write - - - PWMTYPE23 - PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A) - 31 - 1 - - - 0 - Edge-aligned type - #0 - - - 1 - Center-aligned type - #1 - - - read-write - - - - - CNR0 - - CNR0 - PWM Group A Counter Register 0 - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - CNRx - PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in the next PWM cycle. \nNote: When PWM operating at center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high. - 0 - 16 - read-write - - - - - CMR0 - - CMR0 - PWM Group A Comparator Register 0 - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - CMRx - PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in the next PWM cycle. - 0 - 16 - read-write - - - - - PDR0 - - PDR0 - PWM Group A Data Register 0 - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDRx - PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter. - 0 - 16 - read-only - - - - - CNR1 - CNR1 - PWM Group A Counter Register 1 - 0x18 - - - CMR1 - CMR1 - PWM Group A Comparator Register 1 - 0x1C - - - PDR1 - PDR1 - PWM Group A Data Register 1 - 0x20 - - - CNR2 - CNR2 - PWM Group A Counter Register 2 - 0x24 - - - CMR2 - CMR2 - PWM Group A Comparator Register 2 - 0x28 - - - PDR2 - PDR2 - PWM Group A Data Register 2 - 0x2C - - - CNR3 - CNR3 - PWM Group A Counter Register 3 - 0x30 - - - CMR3 - CMR3 - PWM Group A Comparator Register 3 - 0x34 - - - PDR3 - PDR3 - PWM Group A Data Register 3 - 0x38 - - - PBCR - - PBCR - PWM Group A backward compatible Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - - - PIER - - PIER - PWM Group A Interrupt Enable Register - 0x40 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWMIE0 - PWM Channel 0 Interrupt Enable - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMIE1 - PWM Channel 1 Interrupt Enable - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMIE2 - PWM Channel 2 Interrupt Enable - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMIE3 - PWM Channel 3 Interrupt Enable - 3 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE0 - PWM Channel 0 Duty Interrupt Enable - 8 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE1 - PWM Channel 1 Duty Interrupt Enable - 9 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE2 - PWM Channel 2 Duty Interrupt Enable - 10 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE3 - PWM Channel 3 Duty Interrupt Enable - 11 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - INTTYPE01 - PWM01 Interrupt Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A)\nNote: This bit is effective when PWM in central align mode only. - 16 - 1 - - - 0 - PWMIFn will be set if PWM counter underflow - #0 - - - 1 - PWMIFn will be set if PWM counter matches CNRn register - #1 - - - read-write - - - INTTYPE23 - PWM12 Interrupt Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: This bit is effective when PWM in central align mode only. - 17 - 1 - - - 0 - PWMIFn will be set if PWM counter underflow - #0 - - - 1 - PWMIFn will be set if PWM counter matches CNRn register - #1 - - - read-write - - - - - PIIR - - PIIR - PWM Group A Interrupt Indication Register - 0x44 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWMIF0 - PWM channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM0 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero - 0 - 1 - read-write - - - PWMIF1 - PWM channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM1 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero - 1 - 1 - read-write - - - PWMIF2 - PWM channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM2 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero - 2 - 1 - read-write - - - PWMIF3 - PWM channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero - 3 - 1 - read-write - - - PWMDIF0 - PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 8 - 1 - read-write - - - PWMDIF1 - PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 9 - 1 - read-write - - - PWMDIF2 - PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 10 - 1 - read-write - - - PWMDIF3 - PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 11 - 1 - read-write - - - - - CCR0 - - CCR0 - PWM Group A Capture Control Register 0 - 0x50 - read-write - 0x00000000 - 0xFFFFFFFF - - - INV0 - Channel 0 Inverter Enable - 0 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE0 - Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has rising transition, capture issues an Interrupt. - 1 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE0 - Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has falling transition, capture issues an Interrupt. - 2 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH0EN - Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. - 3 - 1 - - - 0 - Capture function on PWM group channel 0 Disabled - #0 - - - 1 - Capture function on PWM group channel 0 Enabled - #1 - - - read-write - - - CAPIF0 - Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 4 - 1 - read-write - - - CRLRI0 - CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 6 - 1 - read-write - - - CFLRI0 - CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 7 - 1 - read-write - - - INV1 - Channel 1 Inverter Enable - 16 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE1 - Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, capture issues an Interrupt. - 17 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE1 - Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, capture issues an Interrupt. - 18 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH1EN - Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. - 19 - 1 - - - 0 - Capture function on PWM group channel 1 Disabled - #0 - - - 1 - Capture function on PWM group channel 1 Enabled - #1 - - - read-write - - - CAPIF1 - Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 20 - 1 - read-write - - - CRLRI1 - CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 22 - 1 - read-write - - - CFLRI1 - CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 23 - 1 - read-write - - - - - CCR2 - - CCR2 - PWM Group A Capture Control Register 2 - 0x54 - read-write - 0x00000000 - 0xFFFFFFFF - - - INV2 - Channel 2 Inverter Enable - 0 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE2 - Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. - 1 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE2 - Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 2 has falling transition, capture issues an Interrupt. - 2 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH2EN - Channel 2 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. - 3 - 1 - - - 0 - Capture function on PWM group channel 2 Disabled - #0 - - - 1 - Capture function on PWM group channel 2 Enabled - #1 - - - read-write - - - CAPIF2 - Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 4 - 1 - read-write - - - CRLRI2 - CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 6 - 1 - read-write - - - CFLRI2 - CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 7 - 1 - read-write - - - INV3 - Channel 3 Inverter Enable - 16 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE3 - Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, capture issues an Interrupt. - 17 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE3 - Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 3 has falling transition, capture issues an Interrupt. - 18 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH3EN - Channel 3 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. - 19 - 1 - - - 0 - Capture function on PWM group channel 3 Disabled - #0 - - - 1 - Capture function on PWM group channel 3 Enabled - #1 - - - read-write - - - CAPIF3 - Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 20 - 1 - read-write - - - CRLRI3 - CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 22 - 1 - read-write - - - CFLRI3 - CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to zero. - 23 - 1 - read-write - - - - - CRLR0 - - CRLR0 - PWM Group A Capture Rising Latch Register (Channel 0) - 0x58 - read-only - 0x00000000 - 0xFFFFFFFF - - - CRLRx - Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. - 0 - 16 - read-only - - - - - CFLR0 - - CFLR0 - PWM Group A Capture Falling Latch Register (Channel 0) - 0x5C - read-only - 0x00000000 - 0xFFFFFFFF - - - CFLRx - Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. - 0 - 16 - read-only - - - - - CRLR1 - CRLR1 - PWM Group A Capture Rising Latch Register (Channel 1) - 0x60 - - - CFLR1 - CFLR1 - PWM Group A Capture Falling Latch Register (Channel 1) - 0x64 - - - CRLR2 - CRLR2 - PWM Group A Capture Rising Latch Register (Channel 2) - 0x68 - - - CFLR2 - CFLR2 - PWM Group A Capture Falling Latch Register (Channel 2) - 0x6C - - - CRLR3 - CRLR3 - PWM Group A Capture Rising Latch Register (Channel 3) - 0x70 - - - CFLR3 - CFLR3 - PWM Group A Capture Falling Latch Register (Channel 3) - 0x74 - - - CAPENR - - CAPENR - PWM Group A Capture Input 0~3 Enable Register - 0x78 - read-write - 0x00000000 - 0xFFFFFFFF - - - CAPENR - Capture Input Enable Register\nThere are four capture inputs from pad. Bit0~Bit3 are used to control each input enable or disable. \n\nCAPENR\nBit 3210 for PWM group A\nBit xxx1 ( Capture channel 0 is from pin PA.12\nBit xx1x ( Capture channel 1 is from pin PA.13\nBit x1xx ( Capture channel 2 is from pin PA.14\nBit 1xxx ( Capture channel 3 is from pin PA.15\nBit 3210 for PWM group B\nBit xxx1 ( Capture channel 0 is from pin PB.11\nBit xx1x ( Capture channel 1 is from pin PE.5\nBit x1xx ( Capture channel 2 is from pin PE.0\nBit 1xxx ( Capture channel 3 is from pin PE.1 - 0 - 4 - - - 0 - Disabled (PWMx multi-function pin input does not affect input capture function.) - 0 - - - 1 - Enabled (PWMx multi-function pin input will affect its input capture function.) - 1 - - - read-write - - - - - POE - - POE - PWM Group A Output Enable Register for channel 0~3 - 0x7C - read-write - 0x00000000 - 0xFFFFFFFF - - - PWM0 - Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 0 - 1 - - - 0 - PWM channel 0 output to pin Disabled - #0 - - - 1 - PWM channel 0 output to pin Enabled - #1 - - - read-write - - - PWM1 - Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 1 - 1 - - - 0 - PWM channel 1 output to pin Disabled - #0 - - - 1 - PWM channel 1 output to pin Enabled - #1 - - - read-write - - - PWM2 - Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 2 - 1 - - - 0 - PWM channel 2 output to pin Disabled - #0 - - - 1 - PWM channel 2 output to pin Enabled - #1 - - - read-write - - - PWM3 - Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 3 - 1 - - - 0 - PWM channel 3 output to pin Disabled - #0 - - - 1 - PWM channel 3 output to pin Enabled - #1 - - - read-write - - - - - TCON - - TCON - PWM Group A Trigger Control Register for channel 0~3 - 0x80 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWM0TEN - Channel 0 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. - 0 - 1 - - - 0 - PWM channel 0 trigger ADC function Disabled - #0 - - - 1 - PWM channel 0 trigger ADC function Enabled - #1 - - - read-write - - - PWM1TEN - Channel 1 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode - 1 - 1 - - - 0 - PWM channel 1 trigger ADC function Disabled - #0 - - - 1 - PWM channel 1 trigger ADC function Enabled - #1 - - - read-write - - - PWM2TEN - Channel 2 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. - 2 - 1 - - - 0 - PWM channel 2 trigger ADC function Disabled - #0 - - - 1 - PWM channel 2 trigger ADC function Enabled - #1 - - - read-write - - - PWM3TEN - Channel 3 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. - 3 - 1 - - - 0 - PWM channel 3 trigger ADC function Disabled - #0 - - - 1 - PWM channel 3 trigger ADC function Enabled - #1 - - - read-write - - - - - TSTATUS - - TSTATUS - PWM Group A Trigger Status Register - 0x84 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWM0TF - Channel 0 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 0 - 1 - read-write - - - PWM1TF - Channel 1 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 1 - 1 - read-write - - - PWM2TF - Channel 2 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 2 - 1 - read-write - - - PWM3TF - Channel 3 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 3 - 1 - read-write - - - - - SYNCBUSY0 - - SYNCBUSY0 - PWM0 Group A Synchronous Busy Status Register - 0x88 - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) to make sure previous setting has been update completely.\nThis bit will be set when software write CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely. - 0 - 1 - read-only - - - - - SYNCBUSY1 - - SYNCBUSY1 - PWM1 Group A Synchronous Busy Status Register - 0x8C - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR1/CMR1/PPR or switch PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM updates these value completely. - 0 - 1 - read-only - - - - - SYNCBUSY2 - - SYNCBUSY2 - PWM2 Group A Synchronous Busy Status Register - 0x90 - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM updates these value completely. - 0 - 1 - read-only - - - - - SYNCBUSY3 - - SYNCBUSY3 - PWM3 Group A Synchronous Busy Status Register - 0x94 - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM updates these value completely. - 0 - 1 - read-only - - - - - CAPPDMACTL - - CAPPDMACTL - PWM Group A PDMA control register - 0xC0 - read-write - 0x00000000 - 0xFFFFFFFF - - - CAP0PDMAEN - Channel 0 PDMA Enable - 0 - 1 - - - 0 - Channel 0 PDMA function Disabled - #0 - - - 1 - Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory - #1 - - - read-write - - - CAP0PDMAMOD - Select CRLR0 or CFLR0 to Transfer PDMA - 1 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR0 - #01 - - - 2 - CFLR0 - #10 - - - 3 - Both CRLR0 and CFLR0 - #11 - - - read-write - - - CAP0RFORDER - - 3 - 1 - - - 0 - CFLR0 is the first captured data to memory - #0 - - - 1 - CRLR0 is the first captured data to memory - #1 - - - read-write - - - CAP1PDMAEN - Channel 1 PDMA Enable - 8 - 1 - - - 0 - Channel 1 PDMA function Disabled - #0 - - - 1 - Channel 1 PDMA function Enabled for the channel 1 captured data and transfer to memory - #1 - - - read-write - - - CAP1PDMAMOD - Select CRLR1 or CFLR1 to Transfer PDMA - 9 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR1 - #01 - - - 2 - CFLR1 - #10 - - - 3 - both CRLR1 and CFLR1 - #11 - - - read-write - - - CAP1RFORDER - Capture channel 1 Rising/Falling Order - 11 - 1 - - - 0 - CFLR1 is the first captured data to memory - #0 - - - 1 - CRLR1 is the first captured data to memory - #1 - - - read-write - - - CAP2PDMAEN - Channel 2 PDMA Enable - 16 - 1 - - - 0 - Channel 2 PDMA function Disabled - #0 - - - 1 - Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory - #1 - - - read-write - - - CAP2PDMAMOD - Select CRLR2 or CFLR2 to do PDMA Transfer - 17 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR2 - #01 - - - 2 - CFLR2 - #10 - - - 3 - Both CRLR2 and CFLR2 - #11 - - - read-write - - - CAP2RFORDER - Capture channel 2 Rising/Falling Order - 19 - 1 - - - 0 - CFLR2 is the first captured data to memory - #0 - - - 1 - CRLR2 is the first captured data to memory - #1 - - - read-write - - - CAP3PDMAEN - Channel 3 PDMA enable - 24 - 1 - - - 0 - Channel 3 PDMA function Disabled - #0 - - - 1 - Channel 3 PDMA function Enabled for the channel 3 captured data and transfer to memory - #1 - - - read-write - - - CAP3PDMAMOD - Select CRLR3 or CFLR3 to do PDMA Transfer - 25 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR3 - #01 - - - 2 - CFLR3 - #10 - - - 3 - Both CRLR3 and CFLR3 - #11 - - - read-write - - - CAP3RFORDER - Capture Channel 3 Rising/Falling Order - 27 - 1 - - - 0 - CFLR3 is the first captured data to memory - #0 - - - 1 - CRLR3 is the first captured data to memory - #1 - - - read-write - - - - - CAP0PDMA - - CAP0PDMA - PWM Group A PDMA channel 0 Data Register - 0xC4 - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP0RFPDMA - PDMA data register for channel 0\nit is the capturing value(CFLR0/CRLR0) for channel 0 - 0 - 16 - read-only - - - - - CAP1PDMA - - CAP1PDMA - PWM Group A PDMA channel 1 Data Register - 0xC8 - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP1RFPDMA - PDMA data register for channel 1\nit is the capturing value(CFLR1/CRLR1) for channel 1 - 0 - 16 - read-only - - - - - CAP2PDMA - - CAP2PDMA - PWM Group A PDMA channel 2 Data Register - 0xCC - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP2RFPDMA - PDMA data register for channel 2\nit is the capturing value(CFLR2/CRLR2) for channel 2 - 0 - 16 - read-only - - - - - CAP3PDMA - - CAP3PDMA - PWM Group A PDMA channel 3 Data Register - 0xD0 - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP3RFPDMA - PDMA data register for channel 3\nit is the capturing value(CFLR3/CRLR3) for channel 3 - 0 - 16 - read-only - - - - - - - SPI0 - SPI Register Map - SPI - 0x40030000 - - - 0x0 - 0xC - registers - - - 0x10 - 0x8 - registers - - - 0x20 - 0x8 - registers - - - 0x34 - 0x14 - registers - - - - SPI_CNTRL - - SPI_CNTRL - Control and Status Register - 0x0 - read-write - 0x05003004 - 0xFFFFFFFF - - - GO_BUSY - SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI.\nNotes:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA block finishes the data transfer. - 0 - 1 - - - 0 - Data transfer stopped if SPI is transferring - #0 - - - 1 - In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master - #1 - - - read-write - - - RX_NEG - Receive on Negative Edge - 1 - 1 - - - 0 - Received data input signal is latched on the rising edge of SPICLK - #0 - - - 1 - Received data input signal is latched on the falling edge of SPICLK - #1 - - - read-write - - - TX_NEG - Transmit on Negative Edge - 2 - 1 - - - 0 - Transmitted data output signal is changed on the rising edge of SPICLK - #0 - - - 1 - Transmitted data output signal is changed on the falling edge of SPICLK - #1 - - - read-write - - - TX_BIT_LEN - Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. - 3 - 5 - read-write - - - LSB - LSB First - 10 - 1 - - - 0 - The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register depending on the TX_BIT_LEN field) - #0 - - - 1 - The LSB, bit 0 of the SPI TX0/1 register is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) - #1 - - - read-write - - - CLKP - Clock Polarity - 11 - 1 - - - 0 - SPICLK idle low - #0 - - - 1 - SPICLK idle high - #1 - - - read-write - - - SP_CYCLE - Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. - 12 - 4 - read-write - - - IF - Transfer Done Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - It indicates that the transfer does not finish yet - #0 - - - 1 - It indicates that the SPI controller has finished one unit transfer - #1 - - - read-write - - - IE - Transfer Interrupt Enable - 17 - 1 - - - 0 - SPI transfer done Interrupt Disabled - #0 - - - 1 - SPI transfer done Interrupt Enabled - #1 - - - read-write - - - SLAVE - Slave mode - 18 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - REORDER - Byte Reorder Mode Function\nNotes:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or the dual I/O mode is enabled. - 19 - 1 - - - 0 - Byte reorder functions Disabled - #0 - - - 1 - Byte reorder function Enabled and a byte suspend interval inserted among each byte depending on the setting of SP_CYCLE. The period of the byte suspend interval depends on the setting of SP_CYCLE - #1 - - - read-write - - - FIFO - FIFO Mode\nNotes:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set "1" automatically after the data was written into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.. - 21 - 1 - - - 0 - FIFO mode Disabled - #0 - - - 1 - FIFO mode Enabled - #1 - - - read-write - - - TWOB - Two-Bit Transfer Mode Enable\nNote: When TWOB is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. - 22 - 1 - - - 0 - Two-bit transfer mode Disabled - #0 - - - 1 - Two-bit transfer mode Enabled - #1 - - - read-write - - - VARCLK_EN - Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode) - 23 - 1 - - - 0 - Serial clock output frequency is fixed and decided only by the value of DIVIDER - #0 - - - 1 - Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER1, and DIVIDER2 - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 24 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25]. - 25 - 1 - - - 0 - Indicates that the receive FIOF buffer is not full - #0 - - - 1 - Indicates that the receive FIFO buffer is full - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26]. - 26 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not empty - #0 - - - 1 - Indicates that the transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_STATUS[27]. - 27 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not full - #0 - - - 1 - Indicates that the transmit FIFO buffer is full - #1 - - - read-only - - - - - SPI_DIVIDER - - SPI_DIVIDER - Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DIVIDER - Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTR2[31], is set to'0'.\n\nelse if BCn is set to '1',\n_\nwhere \n is the SPI engine clock source. It is defined in the CLK_SEL1 register. - 0 - 8 - read-write - - - DIVIDER2 - Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation:\n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. - 16 - 8 - read-write - - - - - SPI_SSR - - SPI_SSR - Slave Select Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - SSR - Slave Select Control Bits (Master only)\nIf AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. - 0 - 2 - read-write - - - SS_LVL - Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1). - 2 - 1 - - - 0 - The slave select signal SPISSx0/1 is active on low-level/falling-edge - #0 - - - 1 - The slave select signal SPISSx0/1 is active on high-level/rising-edge - #1 - - - read-write - - - AUTOSS - Automatic Slave Select (Master only) - 3 - 1 - - - 0 - If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] - #0 - - - 1 - If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished - #1 - - - read-write - - - SS_LTRIG - Slave Select Level Trigger (Slave only) - 4 - 1 - - - 0 - Input slave select signal is edge-trigger. This is the default value. It depends on the SS_LVL bit to decide the signal is active at falling-edge or rising-edge - #0 - - - 1 - Slave select signal will be level-trigger, which depends on the SS_LVL bit to decide the signal is active low or active high - #1 - - - read-write - - - LTRIG_FLAG - Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. - 5 - 1 - - - 0 - The transferred bit length of one transaction does not meet the specified requirement - #0 - - - 1 - The transferred bit length meets the specified requirement which defined in TX_BIT_LEN. - #1 - - - read-write - - - - - SPI_RX0 - - SPI_RX0 - Data Receive Register 0 - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - RX - Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register. - 0 - 32 - read-only - - - - - SPI_RX1 - SPI_RX1 - Data Receive Register 1 - 0x14 - - - SPI_TX0 - - SPI_TX0 - Data Transmit Register 0 - 0x20 - write-only - 0x00000000 - 0xFFFFFFFF - - - TX - Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the setting of transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1. - 0 - 32 - write-only - - - - - SPI_TX1 - SPI_TX1 - Data Transmit Register 1 - 0x24 - - - SPI_VARCLK - - SPI_VARCLK - Variable Clock Pattern Register - 0x34 - read-write - 0x007FFF87 - 0xFFFFFFFF - - - VARCLK - Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. - 0 - 32 - read-write - - - - - SPI_DMA - - SPI_DMA - SPI DMA Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_DMA_GO - Transmit DMA Start\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf uses SPI transmit PDMA function to transfer data, the software should not set the GO_BUSY bit to 1. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn slave mode and the FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. - 0 - 1 - read-write - - - RX_DMA_GO - Receive DMA Start\nSet this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. Hardware will clear this bit to 0 automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit shall be set by software.\nEnable the FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn slave mode and the FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. - 1 - 1 - read-write - - - PDMA_RST - PDMA Reset - 2 - 1 - - - 0 - No Reset PDMA. Reset Disabled - #0 - - - 1 - Reset the PDMA control logic in this SPI controller. This bit will be cleared to 0 automatically - #1 - - - read-write - - - - - SPI_CNTRL2 - - SPI_CNTRL2 - Control and Status Register 2 - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - NOSLVSEL - No Slave Selected (3-Wire) in Slave mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.\nNote: In No Slave Select Signal mode, the SS_LTRIG, SPI_SSR[4], will be set as 1 automatically. - 8 - 1 - - - 0 - 4-wire bi-direction interface - #0 - - - 1 - 3-wire bi-direction interface - #1 - - - read-write - - - SLV_ABORT - Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1 - 9 - 1 - read-write - - - SSTA_INTEN - Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done. - 10 - 1 - - - 0 - Disable the transfer start interrupt - #0 - - - 1 - Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared - #1 - - - read-write - - - SLV_START_INTSTS - Slave 3-Wire Mode Start Interrupt Status\nIt indicates that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_STATUS[11]. - 11 - 1 - - - 0 - It indicates that the SPI transfer is not active - #0 - - - 1 - It indicates that the transfer start in slave mode with no slave select. It will be cleared automatically when the transfer is done or writing one to this bit - #1 - - - read-write - - - DUAL_IO_DIR - Dual IO Mode Direction - 12 - 1 - - - 0 - Dual input mode - #0 - - - 1 - Dual output mode - #1 - - - read-write - - - DUAL_IO_EN - Dual IO Mode - 13 - 1 - - - 0 - Dual IO Mode function Disabled - #0 - - - 1 - Dual IO Mode function Enabled - #1 - - - read-write - - - SS_INT_OPT - Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device. - 16 - 1 - - - 0 - As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 - #0 - - - 1 - As the slave select signal goes to inactive level, the IF bit will be set to 1 - #1 - - - read-write - - - BCn - SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. - 31 - 1 - - - 0 - Backward compatible clock configuration - #0 - - - 1 - The clock configuration is not backward compatible - #1 - - - read-write - - - - - SPI_FIFO_CTL - - SPI_FIFO_CTL - FIFO Control Register - 0x40 - read-write - 0x44000000 - 0xFFFFFFFF - - - RX_CLR - Clear Receive FIFO Buffer - 0 - 1 - - - 1 - Clear Receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect - #1 - - - read-write - - - TX_CLR - Clear Transmit FIFO Buffer - 1 - 1 - - - 1 - Clear Transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect - #1 - - - read-write - - - RX_INTEN - RX Threshold Interrupt Enable - 2 - 1 - - - 1 - RX threshold interrupt Enabled.0 = RX threshold interrupt Disabled - #1 - - - read-write - - - TX_INTEN - TX Threshold Interrupt Enable - 3 - 1 - - - 1 - TX threshold interrupt Enabled.0 = TX threshold interrupt Disabled - #1 - - - read-write - - - RXOV_INTEN - Receive FIFO Over Run Interrupt Enable - 6 - 1 - - - 0 - Receive FIFO over run interrupt Disabled - #0 - - - 1 - Receive FIFO over run interrupt Enabled - #1 - - - read-write - - - TIMEOUT_INTEN - Receive FIFO Time-out Interrupt Enable - 21 - 1 - - - 0 - Time-out function Disabled - #0 - - - 1 - Time-out function Enabled - #1 - - - read-write - - - RXTHRESHOLD - Received FIFO Threshold\n\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. - 24 - 3 - read-write - - - TXTHRESHOLD - Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. - 28 - 3 - read-write - - - - - SPI_STATUS - - SPI_STATUS - SPI Status Register - 0x44 - read-write - 0x05000000 - 0xFFFFFFFF - - - RX_INTSTS - Receive FIFO Threshold Interrupt Status (Read Only) - 0 - 1 - - - 0 - It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD - #0 - - - 1 - It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD - #1 - - - read-only - - - RX_OVER_RUN - Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. - 2 - 1 - read-write - - - TX_INTSTS - Transmit FIFO Threshold Interrupt Status (Read Only) - 4 - 1 - - - 0 - It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD - #0 - - - 1 - It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD - #1 - - - read-only - - - SLV_START_INTSTS - Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11]. - 11 - 1 - - - 0 - It indicates that the transfer is not started - #0 - - - 1 - It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit - #1 - - - read-write - - - RX_FIFO_COUNT - Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer. - 12 - 4 - read-only - - - IF - SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - It indicates that the transfer does not finish yet - #0 - - - 1 - It indicates that the SPI controller has finished one unit transfer - #1 - - - read-write - - - TIMEOUT - Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 20 - 1 - - - 0 - No receive FIFO time-out event - #0 - - - 1 - It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 24 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 25 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[26]. - 26 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not empty - #0 - - - 1 - Indicates that the transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[27]. - 27 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not full - #0 - - - 1 - Indicates that the transmit FIFO buffer is full - #1 - - - read-only - - - TX_FIFO_COUNT - Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer. - 28 - 4 - read-only - - - - - - - SPI1 - SPI Register Map - SPI - 0x40034000 - - - 0x0 - 0xC - registers - - - 0x10 - 0x8 - registers - - - 0x20 - 0x8 - registers - - - 0x34 - 0x14 - registers - - - - SPI_CNTRL - - SPI_CNTRL - Control and Status Register - 0x0 - read-write - 0x05003004 - 0xFFFFFFFF - - - GO_BUSY - SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI.\nNotes:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA block finishes the data transfer. - 0 - 1 - - - 0 - Data transfer stopped if SPI is transferring - #0 - - - 1 - In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master - #1 - - - read-write - - - RX_NEG - Receive on Negative Edge - 1 - 1 - - - 0 - Received data input signal is latched on the rising edge of SPICLK - #0 - - - 1 - Received data input signal is latched on the falling edge of SPICLK - #1 - - - read-write - - - TX_NEG - Transmit on Negative Edge - 2 - 1 - - - 0 - Transmitted data output signal is changed on the rising edge of SPICLK - #0 - - - 1 - Transmitted data output signal is changed on the falling edge of SPICLK - #1 - - - read-write - - - TX_BIT_LEN - Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. - 3 - 5 - read-write - - - LSB - LSB First - 10 - 1 - - - 0 - The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register depending on the TX_BIT_LEN field) - #0 - - - 1 - The LSB, bit 0 of the SPI TX0/1 register is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) - #1 - - - read-write - - - CLKP - Clock Polarity - 11 - 1 - - - 0 - SPICLK idle low - #0 - - - 1 - SPICLK idle high - #1 - - - read-write - - - SP_CYCLE - Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. - 12 - 4 - read-write - - - IF - Transfer Done Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - It indicates that the transfer does not finish yet - #0 - - - 1 - It indicates that the SPI controller has finished one unit transfer - #1 - - - read-write - - - IE - Transfer Interrupt Enable - 17 - 1 - - - 0 - SPI transfer done Interrupt Disabled - #0 - - - 1 - SPI transfer done Interrupt Enabled - #1 - - - read-write - - - SLAVE - Slave mode - 18 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - REORDER - Byte Reorder Mode Function\nNotes:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or the dual I/O mode is enabled. - 19 - 1 - - - 0 - Byte reorder functions Disabled - #0 - - - 1 - Byte reorder function Enabled and a byte suspend interval inserted among each byte depending on the setting of SP_CYCLE. The period of the byte suspend interval depends on the setting of SP_CYCLE - #1 - - - read-write - - - FIFO - FIFO Mode\nNotes:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set "1" automatically after the data was written into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.. - 21 - 1 - - - 0 - FIFO mode Disabled - #0 - - - 1 - FIFO mode Enabled - #1 - - - read-write - - - TWOB - Two-Bit Transfer Mode Enable\nNote: When TWOB is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. - 22 - 1 - - - 0 - Two-bit transfer mode Disabled - #0 - - - 1 - Two-bit transfer mode Enabled - #1 - - - read-write - - - VARCLK_EN - Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode) - 23 - 1 - - - 0 - Serial clock output frequency is fixed and decided only by the value of DIVIDER - #0 - - - 1 - Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER1, and DIVIDER2 - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 24 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25]. - 25 - 1 - - - 0 - Indicates that the receive FIOF buffer is not full - #0 - - - 1 - Indicates that the receive FIFO buffer is full - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26]. - 26 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not empty - #0 - - - 1 - Indicates that the transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_STATUS[27]. - 27 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not full - #0 - - - 1 - Indicates that the transmit FIFO buffer is full - #1 - - - read-only - - - - - SPI_DIVIDER - - SPI_DIVIDER - Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DIVIDER - Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTR2[31], is set to'0'.\n\nelse if BCn is set to '1',\n_\nwhere \n is the SPI engine clock source. It is defined in the CLK_SEL1 register. - 0 - 8 - read-write - - - DIVIDER2 - Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation:\n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. - 16 - 8 - read-write - - - - - SPI_SSR - - SPI_SSR - Slave Select Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - SSR - Slave Select Control Bits (Master only)\nIf AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. - 0 - 2 - read-write - - - SS_LVL - Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1). - 2 - 1 - - - 0 - The slave select signal SPISSx0/1 is active on low-level/falling-edge - #0 - - - 1 - The slave select signal SPISSx0/1 is active on high-level/rising-edge - #1 - - - read-write - - - AUTOSS - Automatic Slave Select (Master only) - 3 - 1 - - - 0 - If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] - #0 - - - 1 - If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished - #1 - - - read-write - - - SS_LTRIG - Slave Select Level Trigger (Slave only) - 4 - 1 - - - 0 - Input slave select signal is edge-trigger. This is the default value. It depends on the SS_LVL bit to decide the signal is active at falling-edge or rising-edge - #0 - - - 1 - Slave select signal will be level-trigger, which depends on the SS_LVL bit to decide the signal is active low or active high - #1 - - - read-write - - - LTRIG_FLAG - Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. - 5 - 1 - - - 0 - The transferred bit length of one transaction does not meet the specified requirement - #0 - - - 1 - The transferred bit length meets the specified requirement which defined in TX_BIT_LEN - #1 - - - read-write - - - - - SPI_RX0 - - SPI_RX0 - Data Receive Register 0 - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - RX - Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register. - 0 - 32 - read-only - - - - - SPI_RX1 - SPI_RX1 - Data Receive Register 1 - 0x14 - - - SPI_TX0 - - SPI_TX0 - Data Transmit Register 0 - 0x20 - write-only - 0x00000000 - 0xFFFFFFFF - - - TX - Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the setting of transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1. - 0 - 32 - write-only - - - - - SPI_TX1 - SPI_TX1 - Data Transmit Register 1 - 0x24 - - - SPI_VARCLK - - SPI_VARCLK - Variable Clock Pattern Register - 0x34 - read-write - 0x007FFF87 - 0xFFFFFFFF - - - VARCLK - Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. - 0 - 32 - read-write - - - - - SPI_DMA - - SPI_DMA - SPI DMA Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_DMA_GO - Transmit DMA Start\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf uses SPI transmit PDMA function to transfer data, the software should not set the GO_BUSY bit to 1. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn slave mode and the FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. - 0 - 1 - read-write - - - RX_DMA_GO - Receive DMA Start\nSet this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. Hardware will clear this bit to 0 automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit shall be set by software.\nEnable the FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn slave mode and the FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. - 1 - 1 - read-write - - - PDMA_RST - PDMA Reset - 2 - 1 - - - 0 - No Reset PDMA. Reset Disabled - #0 - - - 1 - Reset the PDMA control logic in this SPI controller. This bit will be cleared to 0 automatically - #1 - - - read-write - - - - - SPI_CNTRL2 - - SPI_CNTRL2 - Control and Status Register 2 - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - NOSLVSEL - No Slave Selected (3-Wire) in Slave mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.\nNote: In No Slave Select Signal mode, the SS_LTRIG, SPI_SSR[4], will be set as 1 automatically. - 8 - 1 - - - 0 - 4-wire bi-direction interface - #0 - - - 1 - 3-wire bi-direction interface - #1 - - - read-write - - - SLV_ABORT - Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1 - 9 - 1 - read-write - - - SSTA_INTEN - Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done. - 10 - 1 - - - 0 - Disable the transfer start interrupt - #0 - - - 1 - Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared - #1 - - - read-write - - - SLV_START_INTSTS - Slave 3-Wire Mode Start Interrupt Status\nIt indicates that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_STATUS[11]. - 11 - 1 - - - 0 - It indicates that the SPI transfer is not active - #0 - - - 1 - It indicates that the transfer start in slave mode with no slave select. It will be cleared automatically when the transfer is done or writing one to this bit - #1 - - - read-write - - - DUAL_IO_DIR - Dual IO Mode Direction - 12 - 1 - - - 0 - Dual input mode - #0 - - - 1 - Dual output mode - #1 - - - read-write - - - DUAL_IO_EN - Dual IO Mode - 13 - 1 - - - 0 - Dual IO Mode function Disabled - #0 - - - 1 - Dual IO Mode function Enabled - #1 - - - read-write - - - SS_INT_OPT - Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device. - 16 - 1 - - - 0 - As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 - #0 - - - 1 - As the slave select signal goes to inactive level, the IF bit will be set to 1 - #1 - - - read-write - - - BCn - SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. - 31 - 1 - - - 0 - Backward compatible clock configuration - #0 - - - 1 - The clock configuration is not backward compatible - #1 - - - read-write - - - - - SPI_FIFO_CTL - - SPI_FIFO_CTL - FIFO Control Register - 0x40 - read-write - 0x44000000 - 0xFFFFFFFF - - - RX_CLR - Clear Receive FIFO Buffer - 0 - 1 - - - 1 - Clear Receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect - #1 - - - read-write - - - TX_CLR - Clear Transmit FIFO Buffer - 1 - 1 - - - 1 - Clear Transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect - #1 - - - read-write - - - RX_INTEN - RX Threshold Interrupt Enable - 2 - 1 - - - 1 - RX threshold interrupt Enabled.0 = RX threshold interrupt Disabled - #1 - - - read-write - - - TX_INTEN - TX Threshold Interrupt Enable - 3 - 1 - - - 1 - TX threshold interrupt Enabled.0 = TX threshold interrupt Disabled - #1 - - - read-write - - - RXOV_INTEN - Receive FIFO Over Run Interrupt Enable - 6 - 1 - - - 0 - Receive FIFO over run interrupt Disabled - #0 - - - 1 - Receive FIFO over run interrupt Enabled - #1 - - - read-write - - - TIMEOUT_INTEN - Receive FIFO Time-out Interrupt Enable - 21 - 1 - - - 0 - Time-out function Disabled - #0 - - - 1 - Time-out function Enabled - #1 - - - read-write - - - RXTHRESHOLD - Received FIFO Threshold\n\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. - 24 - 3 - read-write - - - TXTHRESHOLD - Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. - 28 - 3 - read-write - - - - - SPI_STATUS - - SPI_STATUS - SPI Status Register - 0x44 - read-write - 0x05000000 - 0xFFFFFFFF - - - RX_INTSTS - Receive FIFO Threshold Interrupt Status (Read Only) - 0 - 1 - - - 0 - It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD - #0 - - - 1 - It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD - #1 - - - read-only - - - RX_OVER_RUN - Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. - 2 - 1 - read-write - - - TX_INTSTS - Transmit FIFO Threshold Interrupt Status (Read Only) - 4 - 1 - - - 0 - It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD - #0 - - - 1 - It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD - #1 - - - read-only - - - SLV_START_INTSTS - Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11]. - 11 - 1 - - - 0 - It indicates that the transfer is not started - #0 - - - 1 - It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit - #1 - - - read-write - - - RX_FIFO_COUNT - Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer. - 12 - 4 - read-only - - - IF - SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - It indicates that the transfer does not finish yet - #0 - - - 1 - It indicates that the SPI controller has finished one unit transfer - #1 - - - read-write - - - TIMEOUT - Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 20 - 1 - - - 0 - No receive FIFO time-out event - #0 - - - 1 - It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 24 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 25 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[26]. - 26 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not empty - #0 - - - 1 - Indicates that the transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[27]. - 27 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not full - #0 - - - 1 - Indicates that the transmit FIFO buffer is full - #1 - - - read-only - - - TX_FIFO_COUNT - Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer. - 28 - 4 - read-only - - - - - - - SPI2 - SPI Register Map - SPI - 0x40130000 - - - 0x0 - 0xC - registers - - - 0x10 - 0x8 - registers - - - 0x20 - 0x8 - registers - - - 0x34 - 0x14 - registers - - - - SPI_CNTRL - - SPI_CNTRL - Control and Status Register - 0x0 - read-write - 0x05003004 - 0xFFFFFFFF - - - GO_BUSY - SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI.\nNotes:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA block finishes the data transfer. - 0 - 1 - - - 0 - Data transfer stopped if SPI is transferring - #0 - - - 1 - In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master - #1 - - - read-write - - - RX_NEG - Receive on Negative Edge - 1 - 1 - - - 0 - Received data input signal is latched on the rising edge of SPICLK - #0 - - - 1 - Received data input signal is latched on the falling edge of SPICLK - #1 - - - read-write - - - TX_NEG - Transmit on Negative Edge - 2 - 1 - - - 0 - Transmitted data output signal is changed on the rising edge of SPICLK - #0 - - - 1 - Transmitted data output signal is changed on the falling edge of SPICLK - #1 - - - read-write - - - TX_BIT_LEN - Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. - 3 - 5 - read-write - - - LSB - LSB First - 10 - 1 - - - 0 - The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register depending on the TX_BIT_LEN field) - #0 - - - 1 - The LSB, bit 0 of the SPI TX0/1 register is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) - #1 - - - read-write - - - CLKP - Clock Polarity - 11 - 1 - - - 0 - SPICLK idle low - #0 - - - 1 - SPICLK idle high - #1 - - - read-write - - - SP_CYCLE - Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. - 12 - 4 - read-write - - - IF - Transfer Done Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - It indicates that the transfer does not finish yet - #0 - - - 1 - It indicates that the SPI controller has finished one unit transfer - #1 - - - read-write - - - IE - Transfer Interrupt Enable - 17 - 1 - - - 0 - SPI transfer done Interrupt Disabled - #0 - - - 1 - SPI transfer done Interrupt Enabled - #1 - - - read-write - - - SLAVE - Slave mode - 18 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - REORDER - Byte Reorder Mode Function\nNotes:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or the dual I/O mode is enabled. - 19 - 1 - - - 0 - Byte reorder functions Disabled - #0 - - - 1 - Byte reorder function Enabled and a byte suspend interval inserted among each byte depending on the setting of SP_CYCLE. The period of the byte suspend interval depends on the setting of SP_CYCLE - #1 - - - read-write - - - FIFO - FIFO Mode\nNotes:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set "1" automatically after the data was written into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.. - 21 - 1 - - - 0 - FIFO mode Disabled - #0 - - - 1 - FIFO mode Enabled - #1 - - - read-write - - - TWOB - Two-Bit Transfer Mode Enable\nNote: When TWOB is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. - 22 - 1 - - - 0 - Two-bit transfer mode Disabled - #0 - - - 1 - Two-bit transfer mode Enabled - #1 - - - read-write - - - VARCLK_EN - Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode) - 23 - 1 - - - 0 - Serial clock output frequency is fixed and decided only by the value of DIVIDER - #0 - - - 1 - Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER1, and DIVIDER2 - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 24 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25]. - 25 - 1 - - - 0 - Indicates that the receive FIOF buffer is not full - #0 - - - 1 - Indicates that the receive FIFO buffer is full - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26]. - 26 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not empty - #0 - - - 1 - Indicates that the transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_STATUS[27]. - 27 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not full - #0 - - - 1 - Indicates that the transmit FIFO buffer is full - #1 - - - read-only - - - - - SPI_DIVIDER - - SPI_DIVIDER - Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DIVIDER - Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTR2[31], is set to'0'.\n\nelse if BCn is set to '1',\n_\nwhere \n is the SPI engine clock source. It is defined in the CLK_SEL1 register. - 0 - 8 - read-write - - - DIVIDER2 - Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation:\n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. - 16 - 8 - read-write - - - - - SPI_SSR - - SPI_SSR - Slave Select Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - SSR - Slave Select Control Bits (Master only)\nIf AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. - 0 - 2 - read-write - - - SS_LVL - Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1). - 2 - 1 - - - 0 - The slave select signal SPISSx0/1 is active on low-level/falling-edge - #0 - - - 1 - The slave select signal SPISSx0/1 is active on high-level/rising-edge - #1 - - - read-write - - - AUTOSS - Automatic Slave Select (Master only) - 3 - 1 - - - 0 - If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] - #0 - - - 1 - If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished - #1 - - - read-write - - - SS_LTRIG - Slave Select Level Trigger (Slave only) - 4 - 1 - - - 0 - Input slave select signal is edge-trigger. This is the default value. It depends on the SS_LVL bit to decide the signal is active at falling-edge or rising-edge - #0 - - - 1 - Slave select signal will be level-trigger, which depends on the SS_LVL bit to decide the signal is active low or active high - #1 - - - read-write - - - LTRIG_FLAG - Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning. - 5 - 1 - - - 0 - The transferred bit length of one transaction does not meet the specified requirement - #0 - - - 1 - The transferred bit length meets the specified requirement which defined in TX_BIT_LEN - #1 - - - read-write - - - - - SPI_RX0 - - SPI_RX0 - Data Receive Register 0 - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - RX - Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register. - 0 - 32 - read-only - - - - - SPI_RX1 - SPI_RX1 - Data Receive Register 1 - 0x14 - - - SPI_TX0 - - SPI_TX0 - Data Transmit Register 0 - 0x20 - write-only - 0x00000000 - 0xFFFFFFFF - - - TX - Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the setting of transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1. - 0 - 32 - write-only - - - - - SPI_TX1 - SPI_TX1 - Data Transmit Register 1 - 0x24 - - - SPI_VARCLK - - SPI_VARCLK - Variable Clock Pattern Register - 0x34 - read-write - 0x007FFF87 - 0xFFFFFFFF - - - VARCLK - Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. - 0 - 32 - read-write - - - - - SPI_DMA - - SPI_DMA - SPI DMA Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_DMA_GO - Transmit DMA Start\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf uses SPI transmit PDMA function to transfer data, the software should not set the GO_BUSY bit to 1. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn slave mode and the FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. - 0 - 1 - read-write - - - RX_DMA_GO - Receive DMA Start\nSet this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. Hardware will clear this bit to 0 automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit shall be set by software.\nEnable the FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn slave mode and the FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. - 1 - 1 - read-write - - - PDMA_RST - PDMA Reset - 2 - 1 - - - 0 - No Reset PDMA. Reset Disabled - #0 - - - 1 - Reset the PDMA control logic in this SPI controller. This bit will be cleared to 0 automatically - #1 - - - read-write - - - - - SPI_CNTRL2 - - SPI_CNTRL2 - Control and Status Register 2 - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - NOSLVSEL - No Slave Selected (3-Wire) in Slave mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.\nNote: In No Slave Select Signal mode, the SS_LTRIG, SPI_SSR[4], will be set as 1 automatically. - 8 - 1 - - - 0 - 4-wire bi-direction interface - #0 - - - 1 - 3-wire bi-direction interface - #1 - - - read-write - - - SLV_ABORT - Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1 - 9 - 1 - read-write - - - SSTA_INTEN - Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done. - 10 - 1 - - - 0 - Disable the transfer start interrupt - #0 - - - 1 - Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared - #1 - - - read-write - - - SLV_START_INTSTS - Slave 3-Wire Mode Start Interrupt Status\nIt indicates that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_STATUS[11]. - 11 - 1 - - - 0 - It indicates that the SPI transfer is not active - #0 - - - 1 - It indicates that the transfer start in slave mode with no slave select. It will be cleared automatically when the transfer is done or writing one to this bit - #1 - - - read-write - - - DUAL_IO_DIR - Dual IO Mode Direction - 12 - 1 - - - 0 - Dual input mode - #0 - - - 1 - Dual output mode - #1 - - - read-write - - - DUAL_IO_EN - Dual IO Mode - 13 - 1 - - - 0 - Dual IO Mode function Disabled - #0 - - - 1 - Dual IO Mode function Enabled - #1 - - - read-write - - - SS_INT_OPT - Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device. - 16 - 1 - - - 0 - As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 - #0 - - - 1 - As the slave select signal goes to inactive level, the IF bit will be set to 1 - #1 - - - read-write - - - BCn - SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. - 31 - 1 - - - 0 - Backward compatible clock configuration - #0 - - - 1 - The clock configuration is not backward compatible - #1 - - - read-write - - - - - SPI_FIFO_CTL - - SPI_FIFO_CTL - FIFO Control Register - 0x40 - read-write - 0x44000000 - 0xFFFFFFFF - - - RX_CLR - Clear Receive FIFO Buffer - 0 - 1 - - - 1 - Clear Receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect - #1 - - - read-write - - - TX_CLR - Clear Transmit FIFO Buffer - 1 - 1 - - - 1 - Clear Transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect - #1 - - - read-write - - - RX_INTEN - RX Threshold Interrupt Enable - 2 - 1 - - - 1 - RX threshold interrupt Enabled.0 = RX threshold interrupt Disabled - #1 - - - read-write - - - TX_INTEN - TX Threshold Interrupt Enable - 3 - 1 - - - 1 - TX threshold interrupt Enabled.0 = TX threshold interrupt Disabled - #1 - - - read-write - - - RXOV_INTEN - Receive FIFO Over Run Interrupt Enable - 6 - 1 - - - 0 - Receive FIFO over run interrupt Disabled - #0 - - - 1 - Receive FIFO over run interrupt Enabled - #1 - - - read-write - - - TIMEOUT_INTEN - Receive FIFO Time-out Interrupt Enable - 21 - 1 - - - 0 - Time-out function Disabled - #0 - - - 1 - Time-out function Enabled - #1 - - - read-write - - - RXTHRESHOLD - Received FIFO Threshold\n\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. - 24 - 3 - read-write - - - TXTHRESHOLD - Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. - 28 - 3 - read-write - - - - - SPI_STATUS - - SPI_STATUS - SPI Status Register - 0x44 - read-write - 0x05000000 - 0xFFFFFFFF - - - RX_INTSTS - Receive FIFO Threshold Interrupt Status (Read Only) - 0 - 1 - - - 0 - It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD - #0 - - - 1 - It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD - #1 - - - read-only - - - RX_OVER_RUN - Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. - 2 - 1 - read-write - - - TX_INTSTS - Transmit FIFO Threshold Interrupt Status (Read Only) - 4 - 1 - - - 0 - It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD - #0 - - - 1 - It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD - #1 - - - read-only - - - SLV_START_INTSTS - Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11]. - 11 - 1 - - - 0 - It indicates that the transfer is not started - #0 - - - 1 - It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit - #1 - - - read-write - - - RX_FIFO_COUNT - Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer. - 12 - 4 - read-only - - - IF - SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - It indicates that the transfer does not finish yet - #0 - - - 1 - It indicates that the SPI controller has finished one unit transfer - #1 - - - read-write - - - TIMEOUT - Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 20 - 1 - - - 0 - No receive FIFO time-out event - #0 - - - 1 - It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 24 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24]. - 25 - 1 - - - 0 - Indicates that the receive FIFO buffer is not empty - #0 - - - 1 - Indicates that the receive FIFO buffer is empty - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[26]. - 26 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not empty - #0 - - - 1 - Indicates that the transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[27]. - 27 - 1 - - - 0 - Indicates that the transmit FIFO buffer is not full - #0 - - - 1 - Indicates that the transmit FIFO buffer is full - #1 - - - read-only - - - TX_FIFO_COUNT - Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer. - 28 - 4 - read-only - - - - - - - TMR01 - TMR Register Map - TMR - 0x40010000 - - - 0x0 - 0x1C - registers - - - 0x20 - 0x1C - registers - - - - TCSR0 - - TCSR0 - Timer0 Control and Status Register - 0x0 - read-write - 0x00000005 - 0xFFFFFFFF - - - PRESCALE - Pre-scale Counter - 0 - 8 - read-write - - - TDR_EN - Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. - 16 - 1 - - - 0 - Timer Data Register update Disabled - #0 - - - 1 - Timer Data Register update Enabled - #1 - - - read-write - - - WAKE_EN - Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU. - 23 - 1 - - - 0 - Wake-up trigger event Disabled - #0 - - - 1 - Wake-up trigger event Enabled - #1 - - - read-write - - - CTB - Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field. - 24 - 1 - - - 0 - Counter mode Disabled - #0 - - - 1 - Counter mode Enabled - #1 - - - read-write - - - CACT - Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status. - 25 - 1 - - - 0 - Timer is not active - #0 - - - 1 - Timer is active - #1 - - - read-only - - - CRST - Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. - 26 - 1 - - - 0 - No effect - #0 - - - 1 - Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit - #1 - - - read-write - - - MODE - Timer Operating Mode - 27 - 2 - read-write - - - IE - Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. - 29 - 1 - - - 0 - Timer Interrupt Disabled - #0 - - - 1 - Timer Interrupt Enabled - #1 - - - read-write - - - CEN - Timer Enable Bit - 30 - 1 - - - 0 - Stops/Suspends counting - #0 - - - 1 - Starts counting - #1 - - - read-write - - - DBGACK_TMR - ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not. - 31 - 1 - - - 0 - ICE debug mode acknowledgement effects TIMER counting - #0 - - - 1 - ICE debug mode acknowledgement disabled - #1 - - - read-write - - - - - TCMPR0 - - TCMPR0 - Timer0 Compare Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - TCMP - Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. - 0 - 24 - read-write - - - - - TISR0 - - TISR0 - Timer0 Interrupt Status Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. - 0 - 1 - read-write - - - TWF - Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit. - 1 - 1 - - - 0 - Timer does not cause CPU wakeup - #0 - - - 1 - CPU wakes up from sleep or power-down mode by timer time-out - #1 - - - read-write - - - - - TDR0 - - TDR0 - Timer0 Data Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - TDR - Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1 - 0 - 24 - read-only - - - - - TCAP0 - - TCAP0 - Timer0 Capture Data Register - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - TCAP - Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value. - 0 - 24 - read-only - - - - - TEXCON0 - - TEXCON0 - Timer0 External Control Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_PHASE - Timer External Count Phase \nThis bit indicates the external count pin phase. - 0 - 1 - - - 0 - A falling edge of external count pin will be counted - #0 - - - 1 - A rising edge of external count pin will be counted - #1 - - - read-write - - - TEX_EDGE - Timer External Pin Edge Detect - 1 - 2 - - - 0 - 1 to 0 transition on TEX will be detected - #00 - - - 1 - 0 to 1 transition on TEX will be detected - #01 - - - 2 - Either 1 to 0 or 0 to 1 transition on TEX will be detected - #10 - - - 3 - Reserved - #11 - - - read-write - - - TEXEN - Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. - 3 - 1 - - - 0 - TEX pin will be ignored - #0 - - - 1 - Transition detected on the TEX pin will result in capture or reset of timer counter - #1 - - - read-write - - - RSTCAPn - Timer External Reset Counter/Capture Mode Selection - 4 - 1 - - - 0 - TEX transition is used as the timer capture function - #0 - - - 1 - TEX transition is used as the timer counter reset function - #1 - - - read-write - - - TEXIEN - Timer External Interrupt Enable Bit - 5 - 1 - - - 0 - Timer external interrupt Disabled - #0 - - - 1 - Timer external interrupt Enabled - #1 - - - read-write - - - TEXDB - Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit. - 6 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - TCDB - Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit. - 7 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - - - TEXISR0 - - TEXISR0 - Timer0 External Interrupt Status Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - TEXIF - Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit. - 0 - 1 - read-write - - - - - TCSR1 - TCSR1 - Timer1 Control and Status Register - 0x20 - - - TCMPR1 - TCMPR1 - Timer1 Compare Register - 0x24 - - - TISR1 - TISR1 - Timer1 Interrupt Status Register - 0x28 - - - TDR1 - TDR1 - Timer1 Data Register - 0x2C - - - TCAP1 - TCAP1 - Timer1 Capture Data Register - 0x30 - - - TEXCON1 - TEXCON1 - Timer1 External Control Register - 0x34 - - - TEXISR1 - TEXISR1 - Timer1 External Interrupt Status Register - 0x38 - - - - - TMR23 - TMR Register Map - TMR - 0x40110000 - - - 0x0 - 0x1C - registers - - - 0x20 - 0x1C - registers - - - - TCSR2 - - TCSR2 - Timer2 Control and Status Register - 0x0 - read-write - 0x00000005 - 0xFFFFFFFF - - - PRESCALE - Pre-scale Counter - 0 - 8 - read-write - - - TDR_EN - Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. - 16 - 1 - - - 0 - Timer Data Register update Disabled - #0 - - - 1 - Timer Data Register update Enabled - #1 - - - read-write - - - WAKE_EN - Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU. - 23 - 1 - - - 0 - Wake-up trigger event Disabled - #0 - - - 1 - Wake-up trigger event Enabled - #1 - - - read-write - - - CTB - Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field. - 24 - 1 - - - 0 - Counter mode Disabled - #0 - - - 1 - Counter mode Enabled - #1 - - - read-write - - - CACT - Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status. - 25 - 1 - - - 0 - Timer is not active - #0 - - - 1 - Timer is active - #1 - - - read-only - - - CRST - Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. - 26 - 1 - - - 0 - No effect - #0 - - - 1 - Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit - #1 - - - read-write - - - MODE - Timer Operating Mode - 27 - 2 - read-write - - - IE - Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. - 29 - 1 - - - 0 - Timer Interrupt Disabled - #0 - - - 1 - Timer Interrupt Enabled - #1 - - - read-write - - - CEN - Timer Enable Bit - 30 - 1 - - - 0 - Stops/Suspends counting - #0 - - - 1 - Starts counting - #1 - - - read-write - - - DBGACK_TMR - ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not. - 31 - 1 - - - 0 - ICE debug mode acknowledgement effects TIMER counting - #0 - - - 1 - ICE debug mode acknowledgement disabled - #1 - - - read-write - - - - - TCMPR2 - - TCMPR2 - Timer2 Compare Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - TCMP - Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. - 0 - 24 - read-write - - - - - TISR2 - - TISR2 - Timer2 Interrupt Status Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. - 0 - 1 - read-write - - - TWF - Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit. - 1 - 1 - - - 0 - Timer does not cause CPU wakeup - #0 - - - 1 - CPU wakes up from sleep or power-down mode by timer time-out - #1 - - - read-write - - - - - TDR2 - - TDR2 - Timer2 Data Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - TDR - Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1 - 0 - 24 - read-only - - - - - TCAP2 - - TCAP2 - Timer2 Capture Data Register - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - TCAP - Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value. - 0 - 24 - read-only - - - - - TEXCON2 - - TEXCON2 - Timer2 External Control Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_PHASE - Timer External Count Phase \nThis bit indicates the external count pin phase. - 0 - 1 - - - 0 - A falling edge of external count pin will be counted - #0 - - - 1 - A rising edge of external count pin will be counted - #1 - - - read-write - - - TEX_EDGE - Timer External Pin Edge Detect - 1 - 2 - - - 0 - 1 to 0 transition on TEX will be detected - #00 - - - 1 - 0 to 1 transition on TEX will be detected - #01 - - - 2 - Either 1 to 0 or 0 to 1 transition on TEX will be detected - #10 - - - 3 - Reserved - #11 - - - read-write - - - TEXEN - Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. - 3 - 1 - - - 0 - TEX pin will be ignored - #0 - - - 1 - Transition detected on the TEX pin will result in capture or reset of timer counter - #1 - - - read-write - - - RSTCAPn - Timer External Reset Counter/Capture Mode Selection - 4 - 1 - - - 0 - TEX transition is used as the timer capture function - #0 - - - 1 - TEX transition is used as the timer counter reset function - #1 - - - read-write - - - TEXIEN - Timer External Interrupt Enable Bit - 5 - 1 - - - 0 - Timer external interrupt Disabled - #0 - - - 1 - Timer external interrupt Enabled - #1 - - - read-write - - - TEXDB - Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit. - 6 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - TCDB - Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit. - 7 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - - - TEXISR2 - - TEXISR2 - Timer2 External Interrupt Status Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - TEXIF - Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit. - 0 - 1 - read-write - - - - - TCSR3 - TCSR3 - Timer3 Control and Status Register - 0x20 - - - TCMPR3 - TCMPR3 - Timer3 Compare Register - 0x24 - - - TISR3 - TISR3 - Timer3 Interrupt Status Register - 0x28 - - - TDR3 - TDR3 - Timer3 Data Register - 0x2C - - - TCAP3 - TCAP3 - Timer3 Capture Data Register - 0x30 - - - TEXCON3 - TEXCON3 - Timer3 External Control Register - 0x34 - - - TEXISR3 - TEXISR3 - Timer3 External Interrupt Status Register - 0x38 - - - - - WDT - WDT Register Map - WDT - 0x40004000 - - - 0x0 - 0x8 - registers - - - - WTCR - - WTCR - Watchdog Timer Control Register - 0x0 - read-write - 0x00000700 - 0xFFFFFFFF - - - WTR - Clear Watchdog Timer (Write-protection Bit)\nSetting this bit will clear the Watchdog timer.\nNote: This bit will be automatically cleared by hardware. - 0 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the contents of the Watchdog timer - #1 - - - read-write - - - WTRE - Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog timer reset function. - 1 - 1 - - - 0 - Watchdog timer reset function Disabled - #0 - - - 1 - Watchdog timer reset function Enabled - #1 - - - read-write - - - WTRF - Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, the Watchdog timer has no effect on this bit.\nNote: This bit is cleared by writing 1 to this bit. - 2 - 1 - - - 0 - Watchdog timer reset did not occur - #0 - - - 1 - Watchdog timer reset occurred - #1 - - - read-write - - - WTIF - Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.\nNote: This bit is cleared by writing 1 to this bit. - 3 - 1 - - - 0 - Watchdog timer interrupt did not occur - #0 - - - 1 - Watchdog timer interrupt occurred - #1 - - - read-write - - - WTWKE - Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nNote: Chip can be woken up by WDT only if WDT clock source select RC10K. - 4 - 1 - - - 0 - Watchdog timer Wake-up chip function Disabled - #0 - - - 1 - Wake-up function Enabled so that Watchdog timer time-out can wake-up chip from Power-down mode - #1 - - - read-write - - - WTWKF - Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip to wake up from Power-down mode, this bit will be set to high. It must be cleared by software by writing 1 to this bit. - 5 - 1 - - - 0 - Watchdog timer does not cause chip wake up - #0 - - - 1 - Chip woken up from Idle or Power-down mode by Watchdog time-out - #1 - - - read-write - - - WTIE - Watchdog Timer Interrupt Enable (Write-protection Bit) - 6 - 1 - - - 0 - Watchdog timer interrupt Disabled - #0 - - - 1 - Watchdog timer interrupt Enabled - #1 - - - read-write - - - WTE - Watchdog Timer Enable (Write-protection Bit) - 7 - 1 - - - 0 - Watchdog timer Disabled (This action will reset the internal counter) - #0 - - - 1 - Watchdog timer Enabled - #1 - - - read-write - - - WTIS - Watchdog Timer Interval Selection (Write-protection Bit) - 8 - 3 - read-write - - - DBGACK_WDT - ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not. - 31 - 1 - - - 0 - ICE debug mode acknowledgement affects Watchdog Timer counting - #0 - - - 1 - ICE debug mode acknowledgement Disabled - #1 - - - read-write - - - - - WTCRALT - - WTCRALT - Watchdog Timer Alternative Control Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - WTRDSEL - Watchdog Timer Reset Delay Select (Write-protection Bits)\nWhen watchdog time-out happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay period for different watchdog time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nThis register will be reset if watchdog reset happened - 0 - 2 - - - 0 - Watchdog reset delay period is 1024 watchdog clock - #00 - - - 1 - Watchdog reset delay period is 128 watchdog clock - #01 - - - 2 - Watchdog reset delay period is 16 watchdog clock - #10 - - - 3 - Watchdog reset delay period is 1 watchdog clock - #11 - - - read-write - - - - - - - WWDT - WWDT Register Map - WWDT - 0x40004100 - - - 0x0 - 0x10 - registers - - - - WWDTRLD - - WWDTRLD - Window Watchdog Timer Reload Counter Register - 0x0 - write-only - 0x00000000 - 0xFFFFFFFF - - - WWDTRLD - WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal. - 0 - 32 - write-only - - - - - WWDTCR - - WWDTCR - Window Watchdog Timer Control Register - 0x4 - read-write - 0x003F0800 - 0xFFFFFFFF - - - WWDTEN - WWDT Enable\nSet this bit to enable the Window Watchdog timer. - 0 - 1 - - - 0 - Window Watchdog timer function Disabled - #0 - - - 1 - Window Watchdog timer function Enabled - #1 - - - read-write - - - WWDTIE - WWDT Interrupt Enable\nSet this bit to enable the Watchdog timer interrupt function. - 1 - 1 - - - 0 - Watchdog timer interrupt function Disabled - #0 - - - 1 - Watchdog timer interrupt function Enabled - #1 - - - read-write - - - PERIODSEL - WWDT Pre-scale Period Select - 8 - 4 - read-write - - - WINCMP - WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value is larger than WWCMP, WWDT will generate RESET signal. - 16 - 6 - read-write - - - DBGACK_WWDT - ICE debug mode acknowledge Disable - 31 - 1 - - - 0 - WWDT count stopped if system is in Debug mode - #0 - - - 1 - WWDT still count even system is in Debug mode - #1 - - - read-write - - - - - WWDTSTS - - WWDTSTS - Window Watchdog Timer Status Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - WWDTIF - WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit will be cleared by software write 1 to this bit. - 0 - 1 - read-write - - - WWDTRF - WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0. - 1 - 1 - read-write - - - - - WWDTCVR - - WWDTCVR - Window Watchdog Timer Counter Value Register - 0xC - read-only - 0x0000003F - 0xFFFFFFFF - - - WWDTCVAL - WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only. - 0 - 6 - read-only - - - - - - - UART0 - UART Register Map - UART - 0x40050000 - - - 0x0 - 0x34 - registers - - - - UA_RBR - - UA_RBR - UART Receive Buffer Register - 0x0 - read-only - 0x00000000 - 0x00000000 - - - RBR - Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). - 0 - 8 - read-only - - - - - UA_THR - UA_RBR - - UA_THR - UART Transmit Holding Register - 0x0 - write-only - 0x00000000 - 0x00000000 - - - THR - Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). - 0 - 8 - write-only - - - - - UA_IER - - UA_IER - UART Interrupt Enable Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - RDA_IEN - Receive Data Available Interrupt Enable. - 0 - 1 - - - 0 - INT_RDA Masked off - #0 - - - 1 - INT_RDA Enabled - #1 - - - read-write - - - THRE_IEN - Transmit Holding Register Empty Interrupt Enable - 1 - 1 - - - 0 - INT_THRE Masked off - #0 - - - 1 - INT_THRE Enabled - #1 - - - read-write - - - RLS_IEN - Receive Line Status Interrupt Enable - 2 - 1 - - - 0 - INT_RLS Masked off - #0 - - - 1 - INT_RLS Enabled - #1 - - - read-write - - - MODEM_IEN - Modem Status Interrupt Enable - 3 - 1 - - - 0 - INT_MODEM Masked off - #0 - - - 1 - INT_MODEM Enabled - #1 - - - read-write - - - RTO_IEN - RX Time Out Interrupt Enable - 4 - 1 - - - 0 - INT_TOUT Masked off - #0 - - - 1 - INT_TOUT Enabled - #1 - - - read-write - - - BUF_ERR_IEN - Buffer Error Interrupt Enable - 5 - 1 - - - 0 - INT_BUF_ERR Masked off - #0 - - - 1 - INT_BUF_ERR Enabled - #1 - - - read-write - - - WAKE_EN - UART Wake-up Function Enable - 6 - 1 - - - 0 - UART wake-up function Disabled - #0 - - - 1 - UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode - #1 - - - read-write - - - TIME_OUT_EN - Time Out Counter Enable - 11 - 1 - - - 0 - Time-out counter Disabled - #0 - - - 1 - Time-out counter Enabled - #1 - - - read-write - - - AUTO_RTS_EN - RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. - 12 - 1 - - - 0 - RTS auto flow control Disabled - #0 - - - 1 - RTS auto flow control Enabled - #1 - - - read-write - - - AUTO_CTS_EN - CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). - 13 - 1 - - - 0 - CTS auto flow control Disabled - #0 - - - 1 - CTS auto flow control Enabled - #1 - - - read-write - - - DMA_TX_EN - TX DMA Enable\nThis bit can enable or disable TX DMA service. - 14 - 1 - - - 0 - TX DMA Disabled - #0 - - - 1 - TX DMA Enabled - #1 - - - read-write - - - DMA_RX_EN - RX DMA Enable\nThis bit can enable or disable RX DMA service. - 15 - 1 - - - 0 - RX DMA Disabled - #0 - - - 1 - RX DMA Enabled - #1 - - - read-write - - - - - UA_FCR - - UA_FCR - UART FIFO Control Register - 0x8 - read-write - 0x00000101 - 0xFFFFFFFF - - - RFR - RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the RX internal state machine and pointers - #1 - - - read-write - - - TFR - TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the TX internal state machine and pointers - #1 - - - read-write - - - RFITL - RX FIFO Interrupt (INT_RDA) Trigger Level - 4 - 4 - read-write - - - RX_DIS - Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. - 8 - 1 - - - 0 - Receiver Enabled - #0 - - - 1 - Receiver Disabled - #1 - - - read-write - - - RTS_TRI_LEV - RTS Trigger Level for Auto-flow Control Use - 16 - 4 - read-write - - - - - UA_LCR - - UA_LCR - UART Line Control Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - WLS - Word Length Selection - 0 - 2 - read-write - - - NSB - Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected. - 2 - 1 - - - 0 - One " STOP bit" is generated in the transmitted data - #0 - - - 1 - One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; - #1 - - - read-write - - - PBE - Parity Bit Enable - 3 - 1 - - - 0 - No parity bit - #0 - - - 1 - Parity bit is generated on each outgoing character and is checked on each incoming data - #1 - - - read-write - - - EPE - Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. - 4 - 1 - - - 0 - Odd number of logic 1's is transmitted and checked in each word - #0 - - - 1 - Even number of logic 1's is transmitted and checked in each word - #1 - - - read-write - - - SPE - Stick Parity Enable - 5 - 1 - - - 0 - Stick parity Disabled - #0 - - - 1 - If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 - #1 - - - read-write - - - BCB - Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. - 6 - 1 - read-write - - - - - UA_MCR - - UA_MCR - UART Modem Control Register - 0x10 - read-write - 0x00000200 - 0xFFFFFFFF - - - RTS - RTS (Request-To-Send) Signal - 1 - 1 - - - 0 - Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) - #0 - - - 1 - Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) - #1 - - - read-write - - - LEV_RTS - RTS Trigger Level\nThis bit can change the RTS trigger level. - 9 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - RTS_ST - RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. - 13 - 1 - read-only - - - - - UA_MSR - - UA_MSR - UART Modem Status Register - 0x14 - read-write - 0x00000110 - 0xFFFFFFFF - - - DCTSF - Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - read-only - - - CTS_ST - CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. - 4 - 1 - read-only - - - LEV_CTS - CTS Trigger Level\nThis bit can change the CTS trigger level. - 8 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - - - UA_FSR - - UA_FSR - UART FIFO Status Register - 0x18 - read-write - 0x10404000 - 0xFFFFFFFF - - - RX_OVER_IF - RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 0 - 1 - read-only - - - RS485_ADD_DETF - RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 3 - 1 - read-only - - - PEF - Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 4 - 1 - read-only - - - FEF - Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 5 - 1 - read-only - - - BIF - Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 6 - 1 - read-only - - - RX_POINTER - RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. - 8 - 6 - read-only - - - RX_EMPTY - Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. - 14 - 1 - read-only - - - RX_FULL - Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 15 - 1 - read-only - - - TX_POINTER - TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. - 16 - 6 - read-only - - - TX_EMPTY - Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). - 22 - 1 - read-only - - - TX_FULL - Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 23 - 1 - read-only - - - TX_OVER_IF - TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. - 24 - 1 - read-only - - - TE_FLAG - Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. - 28 - 1 - read-only - - - - - UA_ISR - - UA_ISR - UART Interrupt Status Register - 0x1C - read-write - 0x00000002 - 0xFFFFFFFF - - - RDA_IF - Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). - 0 - 1 - read-only - - - THRE_IF - Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). - 1 - 1 - read-only - - - RLS_IF - Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 2 - 1 - read-only - - - MODEM_IF - MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 3 - 1 - read-only - - - TOUT_IF - Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 4 - 1 - read-only - - - BUF_ERR_IF - Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 5 - 1 - read-only - - - RDA_INT - Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1. - 8 - 1 - - - 0 - No RDA interrupt is generated - #0 - - - 1 - RDA interrupt is generated - #1 - - - read-only - - - THRE_INT - Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1. - 9 - 1 - - - 0 - No THRE interrupt is generated - #0 - - - 1 - THRE interrupt is generated - #1 - - - read-only - - - RLS_INT - Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1. - 10 - 1 - - - 0 - No RLS interrupt is generated - #0 - - - 1 - RLS interrupt is generated - #1 - - - read-only - - - MODEM_INT - MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1. - 11 - 1 - - - 0 - No Modem interrupt is generated - #0 - - - 1 - Modem interrupt is generated - #1 - - - read-only - - - TOUT_INT - Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1. - 12 - 1 - - - 0 - No Tout interrupt is generated - #0 - - - 1 - Tout interrupt is generated - #1 - - - read-only - - - BUF_ERR_INT - Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1. - 13 - 1 - - - 0 - No buffer error interrupt is generated - #0 - - - 1 - Buffer error interrupt is generated - #1 - - - read-only - - - HW_RLS_IF - In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 18 - 1 - read-only - - - HW_MODEM_IF - In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 19 - 1 - read-only - - - HW_TOUT_IF - In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 20 - 1 - read-only - - - HW_BUF_ERR_IF - In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 21 - 1 - read-only - - - HW_RLS_INT - In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1. - 26 - 1 - - - 0 - No RLS interrupt is generated in DMA mode - #0 - - - 1 - RLS interrupt is generated in DMA mode - #1 - - - read-only - - - HW_MODEM_INT - In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1. - 27 - 1 - - - 0 - No Modem interrupt is generated in DMA mode - #0 - - - 1 - Modem interrupt is generated in DMA mode - #1 - - - read-only - - - HW_TOUT_INT - In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1. - 28 - 1 - - - 0 - No Tout interrupt is generated in DMA mode - #0 - - - 1 - Tout interrupt is generated in DMA mode - #1 - - - read-only - - - HW_BUF_ERR_INT - In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1. - 29 - 1 - - - 0 - No buffer error interrupt is generated in DMA mode - #0 - - - 1 - Buffer error interrupt is generated in DMA mode - #1 - - - read-only - - - - - UA_TOR - - UA_TOR - UART Time Out Register - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - TOIC - Time Out Interrupt Comparator - 0 - 8 - read-write - - - DLY - TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. - 8 - 8 - read-write - - - - - UA_BAUD - - UA_BAUD - UART Baud Rate Divisor Register - 0x24 - read-write - 0x0F000000 - 0xFFFFFFFF - - - BRD - Baud Rate Divider\nThe field indicates the baud rate divider. - 0 - 16 - read-write - - - DIVIDER_X - Divider X - 24 - 4 - read-write - - - DIV_X_ONE - Divider X Equal to 1\nRefer to the Table 512 below for more information. - 28 - 1 - - - 0 - Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) - #0 - - - 1 - Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) - #1 - - - read-write - - - DIV_X_EN - Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled. - 29 - 1 - - - 0 - Divider X Disabled (the equation of M = 16) - #0 - - - 1 - Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) - #1 - - - read-write - - - - - UA_IRCR - - UA_IRCR - UART IrDA Control Register - 0x28 - read-write - 0x00000040 - 0xFFFFFFFF - - - TX_SELECT - TX_SELECT - 1 - 1 - - - 0 - Enable IrDA receiver - #0 - - - 1 - Enable IrDA transmitter - #1 - - - read-write - - - INV_TX - INV_TX - 5 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse TX output signal - #1 - - - read-write - - - INV_RX - INV_RX - 6 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse RX input signal - #1 - - - read-write - - - - - UA_ALT_CSR - - UA_ALT_CSR - UART Alternate Control/Status Register - 0x2C - read-write - 0x00000000 - 0xFFFFFFFF - - - RS485_NMM - RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode. - 8 - 1 - - - 0 - RS-485 Normal Multi-drop Operation mode (NMM) Disabled - #0 - - - 1 - RS-485 Normal Multi-drop Operation mode (NMM) Enabled - #1 - - - read-write - - - RS485_AAD - RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. - 9 - 1 - - - 0 - RS-485 Auto Address Detection Operation mode (AAD) Disabled - #0 - - - 1 - RS-485 Auto Address Detection Operation mode (AAD) Enabled - #1 - - - read-write - - - RS485_AUD - RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. - 10 - 1 - - - 0 - RS-485 Auto Direction Operation mode (AUD) Disabled - #0 - - - 1 - RS-485 Auto Direction Operation mode (AUD) Enabled - #1 - - - read-write - - - RS485_ADD_EN - RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. - 15 - 1 - - - 0 - Address detection mode Disabled - #0 - - - 1 - Address detection mode Enabled - #1 - - - read-write - - - ADDR_MATCH - Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode. - 24 - 8 - read-write - - - - - UA_FUN_SEL - - UA_FUN_SEL - UART Function Select Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - FUN_SEL - Function Selection Enable - 0 - 2 - - - 0 - UART Function - #00 - - - 1 - Reserved - #01 - - - 2 - IrDA Function Enabled - #10 - - - 3 - RS-485 Function Enabled - #11 - - - read-write - - - - - - - UART1 - UART Register Map - UART - 0x40150000 - - - 0x0 - 0x34 - registers - - - - UA_RBR - - UA_RBR - UART Receive Buffer Register - 0x0 - read-only - 0x00000000 - 0x00000000 - - - RBR - Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). - 0 - 8 - read-only - - - - - UA_THR - UA_RBR - - UA_THR - UART Transmit Holding Register - 0x0 - write-only - 0x00000000 - 0x00000000 - - - THR - Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). - 0 - 8 - write-only - - - - - UA_IER - - UA_IER - UART Interrupt Enable Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - RDA_IEN - Receive Data Available Interrupt Enable. - 0 - 1 - - - 0 - INT_RDA Masked off - #0 - - - 1 - INT_RDA Enabled - #1 - - - read-write - - - THRE_IEN - Transmit Holding Register Empty Interrupt Enable - 1 - 1 - - - 0 - INT_THRE Masked off - #0 - - - 1 - INT_THRE Enabled - #1 - - - read-write - - - RLS_IEN - Receive Line Status Interrupt Enable - 2 - 1 - - - 0 - INT_RLS Masked off - #0 - - - 1 - INT_RLS Enabled - #1 - - - read-write - - - MODEM_IEN - Modem Status Interrupt Enable - 3 - 1 - - - 0 - INT_MODEM Masked off - #0 - - - 1 - INT_MODEM Enabled - #1 - - - read-write - - - RTO_IEN - RX Time Out Interrupt Enable - 4 - 1 - - - 0 - INT_TOUT Masked off - #0 - - - 1 - INT_TOUT Enabled - #1 - - - read-write - - - BUF_ERR_IEN - Buffer Error Interrupt Enable - 5 - 1 - - - 0 - INT_BUF_ERR Masked off - #0 - - - 1 - INT_BUF_ERR Enabled - #1 - - - read-write - - - WAKE_EN - UART Wake-up Function Enable - 6 - 1 - - - 0 - UART wake-up function Disabled - #0 - - - 1 - UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode - #1 - - - read-write - - - TIME_OUT_EN - Time Out Counter Enable - 11 - 1 - - - 0 - Time-out counter Disabled - #0 - - - 1 - Time-out counter Enabled - #1 - - - read-write - - - AUTO_RTS_EN - RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. - 12 - 1 - - - 0 - RTS auto flow control Disabled - #0 - - - 1 - RTS auto flow control Enabled - #1 - - - read-write - - - AUTO_CTS_EN - CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). - 13 - 1 - - - 0 - CTS auto flow control Disabled - #0 - - - 1 - CTS auto flow control Enabled - #1 - - - read-write - - - DMA_TX_EN - TX DMA Enable\nThis bit can enable or disable TX DMA service. - 14 - 1 - - - 0 - TX DMA Disabled - #0 - - - 1 - TX DMA Enabled - #1 - - - read-write - - - DMA_RX_EN - RX DMA Enable\nThis bit can enable or disable RX DMA service. - 15 - 1 - - - 0 - RX DMA Disabled - #0 - - - 1 - RX DMA Enabled - #1 - - - read-write - - - - - UA_FCR - - UA_FCR - UART FIFO Control Register - 0x8 - read-write - 0x00000101 - 0xFFFFFFFF - - - RFR - RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the RX internal state machine and pointers - #1 - - - read-write - - - TFR - TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the TX internal state machine and pointers - #1 - - - read-write - - - RFITL - RX FIFO Interrupt (INT_RDA) Trigger Level - 4 - 4 - read-write - - - RX_DIS - Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. - 8 - 1 - - - 0 - Receiver Enabled - #0 - - - 1 - Receiver Disabled - #1 - - - read-write - - - RTS_TRI_LEV - RTS Trigger Level for Auto-flow Control Use - 16 - 4 - read-write - - - - - UA_LCR - - UA_LCR - UART Line Control Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - WLS - Word Length Selection - 0 - 2 - read-write - - - NSB - Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected. - 2 - 1 - - - 0 - One " STOP bit" is generated in the transmitted data - #0 - - - 1 - One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; - #1 - - - read-write - - - PBE - Parity Bit Enable - 3 - 1 - - - 0 - No parity bit - #0 - - - 1 - Parity bit is generated on each outgoing character and is checked on each incoming data - #1 - - - read-write - - - EPE - Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. - 4 - 1 - - - 0 - Odd number of logic 1's is transmitted and checked in each word - #0 - - - 1 - Even number of logic 1's is transmitted and checked in each word - #1 - - - read-write - - - SPE - Stick Parity Enable - 5 - 1 - - - 0 - Stick parity Disabled - #0 - - - 1 - If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 - #1 - - - read-write - - - BCB - Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. - 6 - 1 - read-write - - - - - UA_MCR - - UA_MCR - UART Modem Control Register - 0x10 - read-write - 0x00000200 - 0xFFFFFFFF - - - RTS - RTS (Request-To-Send) Signal - 1 - 1 - - - 0 - Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) - #0 - - - 1 - Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) - #1 - - - read-write - - - LEV_RTS - RTS Trigger Level\nThis bit can change the RTS trigger level. - 9 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - RTS_ST - RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. - 13 - 1 - read-only - - - - - UA_MSR - - UA_MSR - UART Modem Status Register - 0x14 - read-write - 0x00000110 - 0xFFFFFFFF - - - DCTSF - Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - read-only - - - CTS_ST - CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. - 4 - 1 - read-only - - - LEV_CTS - CTS Trigger Level\nThis bit can change the CTS trigger level. - 8 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - - - UA_FSR - - UA_FSR - UART FIFO Status Register - 0x18 - read-write - 0x10404000 - 0xFFFFFFFF - - - RX_OVER_IF - RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 0 - 1 - read-only - - - RS485_ADD_DETF - RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 3 - 1 - read-only - - - PEF - Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 4 - 1 - read-only - - - FEF - Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 5 - 1 - read-only - - - BIF - Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 6 - 1 - read-only - - - RX_POINTER - RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. - 8 - 6 - read-only - - - RX_EMPTY - Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. - 14 - 1 - read-only - - - RX_FULL - Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 15 - 1 - read-only - - - TX_POINTER - TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. - 16 - 6 - read-only - - - TX_EMPTY - Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). - 22 - 1 - read-only - - - TX_FULL - Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 23 - 1 - read-only - - - TX_OVER_IF - TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. - 24 - 1 - read-only - - - TE_FLAG - Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. - 28 - 1 - read-only - - - - - UA_ISR - - UA_ISR - UART Interrupt Status Register - 0x1C - read-write - 0x00000002 - 0xFFFFFFFF - - - RDA_IF - Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). - 0 - 1 - read-only - - - THRE_IF - Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). - 1 - 1 - read-only - - - RLS_IF - Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 2 - 1 - read-only - - - MODEM_IF - MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 3 - 1 - read-only - - - TOUT_IF - Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 4 - 1 - read-only - - - BUF_ERR_IF - Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 5 - 1 - read-only - - - RDA_INT - Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1. - 8 - 1 - - - 0 - No RDA interrupt is generated - #0 - - - 1 - RDA interrupt is generated - #1 - - - read-only - - - THRE_INT - Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1. - 9 - 1 - - - 0 - No THRE interrupt is generated - #0 - - - 1 - THRE interrupt is generated - #1 - - - read-only - - - RLS_INT - Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1. - 10 - 1 - - - 0 - No RLS interrupt is generated - #0 - - - 1 - RLS interrupt is generated - #1 - - - read-only - - - MODEM_INT - MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1. - 11 - 1 - - - 0 - No Modem interrupt is generated - #0 - - - 1 - Modem interrupt is generated - #1 - - - read-only - - - TOUT_INT - Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1. - 12 - 1 - - - 0 - No Tout interrupt is generated - #0 - - - 1 - Tout interrupt is generated - #1 - - - read-only - - - BUF_ERR_INT - Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1. - 13 - 1 - - - 0 - No buffer error interrupt is generated - #0 - - - 1 - Buffer error interrupt is generated - #1 - - - read-only - - - HW_RLS_IF - In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 18 - 1 - read-only - - - HW_MODEM_IF - In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 19 - 1 - read-only - - - HW_TOUT_IF - In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 20 - 1 - read-only - - - HW_BUF_ERR_IF - In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 21 - 1 - read-only - - - HW_RLS_INT - In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1. - 26 - 1 - - - 0 - No RLS interrupt is generated in DMA mode - #0 - - - 1 - RLS interrupt is generated in DMA mode - #1 - - - read-only - - - HW_MODEM_INT - In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1. - 27 - 1 - - - 0 - No Modem interrupt is generated in DMA mode - #0 - - - 1 - Modem interrupt is generated in DMA mode - #1 - - - read-only - - - HW_TOUT_INT - In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1. - 28 - 1 - - - 0 - No Tout interrupt is generated in DMA mode - #0 - - - 1 - Tout interrupt is generated in DMA mode - #1 - - - read-only - - - HW_BUF_ERR_INT - In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1. - 29 - 1 - - - 0 - No buffer error interrupt is generated in DMA mode - #0 - - - 1 - Buffer error interrupt is generated in DMA mode - #1 - - - read-only - - - - - UA_TOR - - UA_TOR - UART Time Out Register - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - TOIC - Time Out Interrupt Comparator - 0 - 8 - read-write - - - DLY - TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. - 8 - 8 - read-write - - - - - UA_BAUD - - UA_BAUD - UART Baud Rate Divisor Register - 0x24 - read-write - 0x0F000000 - 0xFFFFFFFF - - - BRD - Baud Rate Divider\nThe field indicates the baud rate divider. - 0 - 16 - read-write - - - DIVIDER_X - Divider X - 24 - 4 - read-write - - - DIV_X_ONE - Divider X Equal to 1\nRefer to the Table 512 below for more information. - 28 - 1 - - - 0 - Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) - #0 - - - 1 - Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) - #1 - - - read-write - - - DIV_X_EN - Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled. - 29 - 1 - - - 0 - Divider X Disabled (the equation of M = 16) - #0 - - - 1 - Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) - #1 - - - read-write - - - - - UA_IRCR - - UA_IRCR - UART IrDA Control Register - 0x28 - read-write - 0x00000040 - 0xFFFFFFFF - - - TX_SELECT - TX_SELECT - 1 - 1 - - - 0 - Enable IrDA receiver - #0 - - - 1 - Enable IrDA transmitter - #1 - - - read-write - - - INV_TX - INV_TX - 5 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse TX output signal - #1 - - - read-write - - - INV_RX - INV_RX - 6 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse RX input signal - #1 - - - read-write - - - - - UA_ALT_CSR - - UA_ALT_CSR - UART Alternate Control/Status Register - 0x2C - read-write - 0x00000000 - 0xFFFFFFFF - - - RS485_NMM - RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode. - 8 - 1 - - - 0 - RS-485 Normal Multi-drop Operation mode (NMM) Disabled - #0 - - - 1 - RS-485 Normal Multi-drop Operation mode (NMM) Enabled - #1 - - - read-write - - - RS485_AAD - RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. - 9 - 1 - - - 0 - RS-485 Auto Address Detection Operation mode (AAD) Disabled - #0 - - - 1 - RS-485 Auto Address Detection Operation mode (AAD) Enabled - #1 - - - read-write - - - RS485_AUD - RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. - 10 - 1 - - - 0 - RS-485 Auto Direction Operation mode (AUD) Disabled - #0 - - - 1 - RS-485 Auto Direction Operation mode (AUD) Enabled - #1 - - - read-write - - - RS485_ADD_EN - RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. - 15 - 1 - - - 0 - Address detection mode Disabled - #0 - - - 1 - Address detection mode Enabled - #1 - - - read-write - - - ADDR_MATCH - Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode. - 24 - 8 - read-write - - - - - UA_FUN_SEL - - UA_FUN_SEL - UART Function Select Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - FUN_SEL - Function Selection Enable - 0 - 2 - - - 0 - UART Function - #00 - - - 1 - Reserved - #01 - - - 2 - IrDA Function Enabled - #10 - - - 3 - RS-485 Function Enabled - #11 - - - read-write - - - - - - - PS2 - PS2 Register Map - PS2 - 0x40100000 - - - 0x0 - 0x20 - registers - - - - PS2CON - - PS2CON - PS/2 Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PS2EN - Enable PS/2 Device\nEnable PS/2 device controller. - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - TXINTEN - Enable Transmit Interrupt - 1 - 1 - - - 0 - Data transmit complete interrupt Disabled - #0 - - - 1 - Data transmit complete interrupt Enabled - #1 - - - read-write - - - RXINTEN - Enable Receive Interrupt - 2 - 1 - - - 0 - Data receive complete interrupt Disabled - #0 - - - 1 - Data receive complete interrupt Enabled - #1 - - - read-write - - - TXFIFODIPTH - Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application. - 3 - 4 - - - 0 - 1 byte - 0 - - - 1 - 2 bytes - 1 - - - 14 - 15 bytes - 14 - - - 15 - 16 bytes - 15 - - - read-write - - - ACK - Acknowledge Enable - 7 - 1 - - - 0 - Always sends acknowledge to host at 12th clock for host to device communication - #0 - - - 1 - If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock - #1 - - - read-write - - - CLRFIFO - Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared. - 8 - 1 - - - 0 - Not active - #0 - - - 1 - Clear FIFO - #1 - - - read-write - - - OVERRIDE - Software Override PS/2 CLK/DATA Pin State - 9 - 1 - - - 0 - PS2CLK and PS2DATA pins are controlled by internal state machine - #0 - - - 1 - PS2CLK and PS2DATA pins are controlled by software - #1 - - - read-write - - - FPS2CLK - Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high. - 10 - 1 - - - 0 - Force PS2CLK line low - #0 - - - 1 - Force PS2CLK line high - #1 - - - read-write - - - FPS2DAT - Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high. - 11 - 1 - - - 0 - Force PS2DATA low - #0 - - - 1 - Force PS2DATA high - #1 - - - read-write - - - - - PS2TXDATA0 - - PS2TXDATA0 - PS/2 Transmit Data Register 0 - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PS2TXDATAx - Transmit data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer. - 0 - 32 - read-write - - - - - PS2TXDATA1 - PS2TXDATA1 - PS/2 Transmit Data Register 1 - 0x8 - - - PS2TXDATA2 - PS2TXDATA2 - PS/2 Transmit Data Register 2 - 0xC - - - PS2TXDATA3 - PS2TXDATA3 - PS/2 Transmit Data Register 3 - 0x10 - - - PS2RXDATA - - PS2RXDATA - PS/2 Receive Data Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PS2RXDATA - Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1. - 0 - 8 - read-only - - - - - PS2STATUS - - PS2STATUS - PS/2 Status Register - 0x18 - read-write - 0x00000083 - 0xFFFFFFFF - - - PS2CLK - CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing. - 0 - 1 - read-write - - - PS2DATA - DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling. - 1 - 1 - read-write - - - FRAMERR - Frame Error\nFor host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a "Resend" command to host.\nWrite 1 to clear this bit. - 2 - 1 - - - 0 - No frame error - #0 - - - 1 - Frame error occurred - #1 - - - read-write - - - RXPARITY - Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit. - 3 - 1 - read-write - - - RXBUSY - Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit. - 4 - 1 - - - 0 - Idle - #0 - - - 1 - Currently receiving data - #1 - - - read-write - - - TXBUSY - Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit. - 5 - 1 - - - 0 - Idle - #0 - - - 1 - Currently sending data - #1 - - - read-write - - - RXOVF - RX Buffer Overwrite\nWrite 1 to clear this bit. - 6 - 1 - - - 0 - No overwrite - #0 - - - 1 - Data in PS2RXDATA register is overwritten by new received data - #1 - - - read-write - - - TXEMPTY - TX FIFO Empty\nWhen software writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit. - 7 - 1 - - - 0 - There is data to be transmitted - #0 - - - 1 - FIFO is empty - #1 - - - read-write - - - BYTEIDX - Byte Index - 8 - 4 - read-write - - - - - PS2INTID - - PS2INTID - PS/2 Interrupt Identification Register - 0x1C - read-write - 0x00000000 - 0xFFFFFFFF - - - RXINT - Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. - 0 - 1 - - - 0 - No interrupt - #0 - - - 1 - Receive interrupt occurs - #1 - - - read-write - - - TXINT - Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. - 1 - 1 - - - 0 - No interrupt - #0 - - - 1 - Transmit interrupt occurs - #1 - - - read-write - - - - - - - I2S - I2S Register Map - I2S - 0x401A0000 - - - 0x0 - 0x18 - registers - - - - I2S_CON - - I2S_CON - I2S Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2SEN - I2S Controller Enable - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - TXEN - Transmit enable - 1 - 1 - - - 0 - Data transmission Disabled - #0 - - - 1 - Data transmission Enabled - #1 - - - read-write - - - RXEN - Receive enable - 2 - 1 - - - 0 - Data receiving Disabled - #0 - - - 1 - Data receiving Enabled - #1 - - - read-write - - - MUTE - Transmit Mute Enable - 3 - 1 - - - 0 - Transmit data is shifted from buffer - #0 - - - 1 - Transmit channel zero - #1 - - - read-write - - - WORDWIDTH - Word Width - 4 - 2 - - - 0 - Data is 8-bit - #00 - - - 1 - Data is 16-bit - #01 - - - 2 - Data is 24-bit - #10 - - - 3 - Data is 32-bit - #11 - - - read-write - - - MONO - Monaural Data - 6 - 1 - - - 0 - Data is stereo format - #0 - - - 1 - Data is monaural format - #1 - - - read-write - - - FORMAT - Data format Selection - 7 - 1 - - - 0 - I2S data format\nPCM mode A - #0 - - - 1 - MSB justified data format\nPCM mode B - #1 - - - read-write - - - SLAVE - Slave mode\nI2S can be operated as Master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC123 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. - 8 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - TXTH - Transmit FIFO threshold level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level, the TXTHF flag is set. - 9 - 3 - - - 0 - 0 word data in transmit FIFO - #000 - - - 1 - 1 word data in transmit FIFO - #001 - - - 2 - 2 words data in transmit FIFO - #010 - - - 3 - 3 words data in transmit FIFO - #011 - - - 4 - 4 words data in transmit FIFO - #100 - - - 5 - 5 words data in transmit FIFO - #101 - - - 6 - 6 words data in transmit FIFO - #110 - - - 7 - 7 words data in transmit FIFO - #111 - - - read-write - - - RXTH - Receive FIFO threshold level\nWhen received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set. - 12 - 3 - - - 0 - 1 word data in receive FIFO - #000 - - - 1 - 2 word data in receive FIFO - #001 - - - 2 - 3 word data in receive FIFO - #010 - - - 3 - 4 word data in receive FIFO - #011 - - - 4 - 5 word data in receive FIFO - #100 - - - 5 - 6 word data in receive FIFO - #101 - - - 6 - 7 word data in receive FIFO - #110 - - - 7 - 8 word data in receive FIFO - #111 - - - read-write - - - MCLKEN - Master clock enable\nFor NuMicro( NUC123 series, if the external crystal clock is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip. - 15 - 1 - - - 0 - Master clock Disabled - #0 - - - 1 - Master clock Enabled - #1 - - - read-write - - - RCHZCEN - Right Channel Zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1. - 16 - 1 - - - 0 - Right channel zero-cross detect Disabled - #0 - - - 1 - Right channel zero-cross detect Enabled - #1 - - - read-write - - - LCHZCEN - Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1. - 17 - 1 - - - 0 - Left channel zero-cross detect Disabled - #0 - - - 1 - Left channel zero-cross detect Enabled - #1 - - - read-write - - - CLR_TXFIFO - Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically, reading it returns zero. - 18 - 1 - read-write - - - CLR_RXFIFO - Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, reading it returns zero. - 19 - 1 - read-write - - - TXDMA - Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full. - 20 - 1 - - - 0 - TX DMA Disabled - #0 - - - 1 - TX DMA Enabled - #1 - - - read-write - - - RXDMA - Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty. - 21 - 1 - - - 0 - RX DMA Disabled - #0 - - - 1 - RX DMA Enabled - #1 - - - read-write - - - RXLCH - Receive Left Channel Enable - 23 - 1 - - - 0 - Receives right channel data when monaural format is selected - #0 - - - 1 - Receives left channel data when monaural format is selected - #1 - - - read-write - - - PCM - PCM Interface Enable - 24 - 1 - - - 0 - I2S Interface - #0 - - - 1 - PCM interface - #1 - - - read-write - - - - - I2S_CLKDIV - - I2S_CLKDIV - I2S Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - MCLK_DIV - Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input. - 0 - 3 - read-write - - - BCLK_DIV - Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by NuMicro( NUC123 series. Software can program these bits to generate sampling rate clock frequency. - 8 - 8 - read-write - - - - - I2S_IE - - I2S_IE - I2S Interrupt Enable Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - RXUDFIE - Receive FIFO Underflow Interrupt Enable\nIf software reads the received FIFO when it is empty, RXUDF flag in I2SSTATUS register is set to 1. - 0 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - RXOVFIE - Receive FIFO Overflow Interrupt Enable - 1 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - RXTHIE - Received FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs. - 2 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - TXUDFIE - Transmitted FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO underflow flag is set to 1. - 8 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - TXOVFIE - Transmitted FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO overflow flag is set to 1. - 9 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - TXTHIE - Transmitted FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO are less than TXTH[2:0]. - 10 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - RZCIE - Right Channel Zero-cross Interrupt Enable - 11 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - LZCIE - Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross. - 12 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - - - I2S_STATUS - - I2S_STATUS - I2S Status Register - 0xC - read-write - 0x00141000 - 0xFFFFFFFF - - - I2SINT - I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only. - 0 - 1 - - - 0 - No I2S interrupt - #0 - - - 1 - I2S interrupt - #1 - - - read-write - - - I2SRXINT - I2S Receive Interrupt\nThis bit is read only. - 1 - 1 - - - 0 - No receive interrupt - #0 - - - 1 - Receive interrupt - #1 - - - read-write - - - I2STXINT - I2S Transmit Interrupt\nThis bit is read only. - 2 - 1 - - - 0 - No transmit interrupt - #0 - - - 1 - Transmit interrupt - #1 - - - read-write - - - RIGHT - Right Channel\nThis bit indicates the current transmit data is belong to right channel.\nThis bit is read only. - 3 - 1 - - - 0 - Left channel - #0 - - - 1 - Right channel - #1 - - - read-write - - - RXUDF - Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nSoftware can write 1 to clear this bit to zero. - 8 - 1 - - - 0 - No underflow occurred - #0 - - - 1 - Underflow occurred - #1 - - - read-write - - - RXOVF - Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nSoftware can write 1 to clear this bit to zero. - 9 - 1 - - - 0 - No overflow occurred - #0 - - - 1 - Overflow occurred - #1 - - - read-write - - - RXTHF - Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only. - 10 - 1 - - - 0 - Data word(s) in FIFO is lower than threshold level - #0 - - - 1 - Data word(s) in FIFO is equal or higher than threshold level - #1 - - - read-write - - - RXFULL - Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8.\nThis bit is read only. - 11 - 1 - - - 0 - Not full - #0 - - - 1 - Full - #1 - - - read-write - - - RXEMPTY - Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero.\nThis bit is read only. - 12 - 1 - - - 0 - Not empty - #0 - - - 1 - Empty - #1 - - - read-write - - - TXUDF - Transmit FIFO underflow flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to zero - 16 - 1 - - - 0 - No underflow - #0 - - - 1 - Underflow - #1 - - - read-write - - - TXOVF - Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1.\nSoftware can write 1 to clear this bit to zero. - 17 - 1 - - - 0 - No overflow - #0 - - - 1 - Overflow - #1 - - - read-write - - - TXTHF - Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only. - 18 - 1 - - - 0 - Data word(s) in FIFO is higher than threshold level - #0 - - - 1 - Data word(s) in FIFO is equal or lower than threshold level - #1 - - - read-write - - - TXFULL - Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8.\nThis bit is read only - 19 - 1 - - - 0 - Not full - #0 - - - 1 - Full - #1 - - - read-write - - - TXEMPTY - Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero.\nThis bit is read only. - 20 - 1 - - - 0 - Not empty - #0 - - - 1 - Empty - #1 - - - read-write - - - TXBUSY - Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out, and set to 1 when the 1st data is load to shift buffer. \nThis bit is read only. - 21 - 1 - - - 0 - Transmit shift buffer is empty - #0 - - - 1 - Transmit shift buffer is busy - #1 - - - read-write - - - RZCF - Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero. - 22 - 1 - - - 0 - No zero-cross - #0 - - - 1 - Right channel zero-cross is detected - #1 - - - read-write - - - LZCF - Left Channel Zero-cross Flag\nIt indicates left channel next the sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero - 23 - 1 - - - 0 - No zero-cross - #0 - - - 1 - Left channel zero-cross is detected - #1 - - - read-write - - - RX_LEVEL - Receive FIFO Level\nThese bits indicate word number in receive FIFO. - 24 - 4 - - - 0 - No data - #0000 - - - 1 - 1 word in receive FIFO - #0001 - - - 8 - 8 words in receive FIFO - #1000 - - - read-write - - - TX_LEVEL - Transmit FIFO Level\nThese bits indicate word number in transmit FIFO. - 28 - 4 - - - 0 - No data - #0000 - - - 1 - 1 word in transmit FIFO - #0001 - - - 8 - 8 words in transmit FIFO - #1000 - - - read-write - - - - - I2S_TXFIFO - - I2S_TXFIFO - I2S Transmit FIFO Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - Transmit FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data transmission. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2S_STATUS. - 0 - 32 - read-write - - - - - I2S_RXFIFO - - I2S_RXFIFO - I2S Receive FIFO Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2S_STATUS register. - 0 - 32 - read-write - - - - - - - ADC - ADC Register Map - ADC - 0x400E0000 - - - 0x0 - 0x34 - registers - - - 0x40 - 0x4 - registers - - - - ADDR0 - - ADDR0 - A/D Data Register 0 - 0x0 - read-only - 0x00000000 - 0xFFFFFFFF - - - RSLT - A/D Conversion Result\nThis field contains 10 bits conversion result of ADC. - 0 - 10 - read-only - - - OVERRUN - Over Run Flag\nIf converted data in RSLT[9:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit. - 16 - 1 - - - 0 - Data in RSLT[9:0] is recent conversion result - #0 - - - 1 - Data in RSLT[9:0] is overwritten - #1 - - - read-only - - - VALID - Valid Flag\nThis bit is set to 1 when the corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit. - 17 - 1 - - - 0 - Data in RSLT[9:0] bits is not valid - #0 - - - 1 - Data in RSLT[9:0] bits is valid - #1 - - - read-only - - - - - ADDR1 - ADDR1 - A/D Data Register 1 - 0x4 - - - ADDR2 - ADDR2 - A/D Data Register 2 - 0x8 - - - ADDR3 - ADDR3 - A/D Data Register 3 - 0xC - - - ADDR4 - ADDR4 - A/D Data Register 4 - 0x10 - - - ADDR5 - ADDR5 - A/D Data Register 5 - 0x14 - - - ADDR6 - ADDR6 - A/D Data Register 6 - 0x18 - - - ADDR7 - ADDR7 - A/D Data Register 7 - 0x1C - - - ADCR - - ADCR - A/D Control Register - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADEN - A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption. - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - ADIE - A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1. - 1 - 1 - - - 0 - A/D interrupt function Disabled - #0 - - - 1 - A/D interrupt function Enabled - #1 - - - read-write - - - ADMD - A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit firstly. - 2 - 2 - - - 0 - Single conversion - #00 - - - 1 - Reserved - #01 - - - 2 - Single-cycle scan - #10 - - - 3 - Continuous scan - #11 - - - read-write - - - TRGS - Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS. - 4 - 2 - - - 0 - A/D conversion is started by external STADC pin - #00 - - - 3 - A/D conversion is started by PWM center-aligned trigger - #11 - - - read-write - - - TRGCOND - External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger. - 6 - 2 - - - 0 - Low level - #00 - - - 1 - High level - #01 - - - 2 - Falling edge - #10 - - - 3 - Rising edge - #11 - - - read-write - - - TRGEN - External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in Single-cycle Scan mode.\nIf hardware trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source. - 8 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PTEN - PDMA Transfer Enable - 9 - 1 - - - 0 - PDMA data transfer Disabled - #0 - - - 1 - PDMA data transfer in ADDR 0~7 Enabled - #1 - - - read-write - - - ADST - A/D Conversion Start\nADST bit can be set to 1 from three sources: software and external pin STADC, and pwm output. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset. - 11 - 1 - - - 0 - Conversion stopped and A/D converter entering Idle state - #0 - - - 1 - Conversion started - #1 - - - read-write - - - - - ADCHER - - ADCHER - A/D Channel Enable Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - CHEN - Analog Input Channel Enable\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. - 0 - 8 - - - 0 - Disabled - 0 - - - 1 - Enabled - 1 - - - read-write - - - PRESEL - Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 kHz. - 8 - 1 - - - 0 - External analog input - #0 - - - 1 - Internal band-gap voltage - #1 - - - read-write - - - - - ADCMPR0 - - ADCMPR0 - A/D Compare Register 0 - 0x28 - read-write - 0x00000000 - 0xFFFFFFFF - - - CMPEN - Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register. - 0 - 1 - - - 0 - Compare function Disabled - #0 - - - 1 - Compare function Enabled - #1 - - - read-write - - - CMPIE - Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. - 1 - 1 - - - 0 - Compare function interrupt Disabled - #0 - - - 1 - Compare function interrupt Enabled - #1 - - - read-write - - - CMPCOND - Compare Conditions\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. - 2 - 1 - - - 0 - Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one - #0 - - - 1 - Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one - #1 - - - read-write - - - CMPCH - Compare Channel Selection - 3 - 3 - - - 0 - Channel 0 conversion result is selected to be compared - #000 - - - 1 - Channel 1 conversion result is selected to be compared - #001 - - - 2 - Channel 2 conversion result is selected to be compared - #010 - - - 3 - Channel 3 conversion result is selected to be compared - #011 - - - 4 - Channel 4 conversion result is selected to be compared - #100 - - - 5 - Channel 5 conversion result is selected to be compared - #101 - - - 6 - Channel 6 conversion result is selected to be compared - #110 - - - 7 - Channel 7 conversion result is selected to be compared - #111 - - - read-write - - - CMPMATCNT - Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. - 8 - 4 - read-write - - - CMPD - Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format. - 16 - 12 - read-write - - - - - ADCMPR1 - ADCMPR1 - A/D Compare Register 1 - 0x2C - - - ADSR - - ADSR - A/D Status Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADF - A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself. - 0 - 1 - read-write - - - CMPF0 - Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to itself. - 1 - 1 - - - 0 - Conversion result in ADDR does not meet ADCMPR0 setting - #0 - - - 1 - Conversion result in ADDR meets ADCMPR0 setting - #1 - - - read-write - - - CMPF1 - Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. It is cleared by writing 1 to itself. - 2 - 1 - - - 0 - Conversion result in ADDR does not meet ADCMPR1 setting - #0 - - - 1 - Conversion result in ADDR meets ADCMPR1 setting - #1 - - - read-write - - - BUSY - BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only. - 3 - 1 - - - 0 - A/D converter is in Idle state - #0 - - - 1 - A/D converter is busy at conversion - #1 - - - read-write - - - CHANNEL - Current Conversion Channel\nIt is read only. - 4 - 3 - read-write - - - VALID - Data Valid flag\nIt is a mirror of VALID bit in ADDRx.\nIt is read only. - 8 - 8 - read-write - - - OVERRUN - Over Run Flag\nIt is a mirror to OVERRUN bit in ADDRx.\nIt is read only. - 16 - 8 - read-write - - - - - ADPDMA - - ADPDMA - A/D PDMA current transfer data Register - 0x40 - read-only - 0x00000000 - 0xFFFFFFFF - - - AD_PDMA - ADC PDMA current transfer data register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nThis is a read only register. - 0 - 10 - read-only - - - - - - - PDMA_ch0 - PDMA Register Map - PDMA - 0x50008000 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control and Status Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Transfer Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal Buffer Pointer Register - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch1 - PDMA Register Map - PDMA - 0x50008100 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control and Status Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Transfer Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal Buffer Pointer Register - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch2 - PDMA Register Map - PDMA - 0x50008200 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control and Status Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Transfer Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal Buffer Pointer Register - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch3 - PDMA Register Map - PDMA - 0x50008300 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control and Status Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Transfer Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal Buffer Pointer Register - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch4 - PDMA Register Map - PDMA - 0x50008400 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control and Status Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Transfer Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal Buffer Pointer Register - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch5 - PDMA Register Map - PDMA - 0x50008500 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control and Status Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Transfer Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal Buffer Pointer Register - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - CRC - PDMA Register Map - PDMA - 0x50008E00 - - - 0x0 - 0x8 - registers - - - 0xC - 0x4 - registers - - - 0x14 - 0x4 - registers - - - 0x1C - 0xC - registers - - - 0x80 - 0xC - registers - - - - CRC_CTL - - CRC_CTL - CRC Control Register - 0x0 - read-write - 0x20000000 - 0xFFFFFFFF - - - CRCCEN - CRC Channel Enable\nSetting this bit to 1 enables CRC's operation. - 0 - 1 - read-write - - - CRC_RST - CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value. - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles - #1 - - - read-write - - - TRIG_EN - TRIG_EN\nNote1: If this bit assert indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer is completed, this bit will be cleared automatically.\nNote3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - CRC DMA data read or write transfer Enabled - #1 - - - read-write - - - WDATA_RVS - Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB - 24 - 1 - - - 0 - No bit order reversed for CRC write data in - #0 - - - 1 - Bit order reversed for CRC write data in (per byte) - #1 - - - read-write - - - CHECKSUM_RVS - Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB. - 25 - 1 - - - 0 - No bit order reverse for CRC checksum - #0 - - - 1 - Bit order reverse for CRC checksum - #1 - - - read-write - - - WDATA_COM - Write Data Complement - 26 - 1 - - - 0 - No 1's complement for CRC write data in - #0 - - - 1 - 1's complement for CRC write data in - #1 - - - read-write - - - CHECKSUM_COM - Checksum Complement - 27 - 1 - - - 0 - No 1's complement for CRC checksum - #0 - - - 1 - 1's complement for CRC checksum - #1 - - - read-write - - - CPU_WDLEN - CPU Write Data Length\nNote1: This field is used for CPU PIO mode.\nNote2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0]; if the data length is 16-bit mode, the valid data is CRC_WDATA [15:0]. - 28 - 2 - - - 0 - Data length is 8-bit mode - #00 - - - 1 - Data length is 16-bit mode\nData length is 32-bit mode - #01 - - - read-write - - - CRC_MODE - CRC Polynomial Mode - 30 - 2 - - - 0 - CRC-CCITT Polynomial mode - #00 - - - 1 - CRC-8 Polynomial mode - #01 - - - 2 - CRC-16 Polynomial mode - #10 - - - 3 - CRC-32 Polynomial mode - #11 - - - read-write - - - - - CRC_DMASAR - - CRC_DMASAR - CRC DMA Transfer Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRC_DMASAR - CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - CRC_DMABCR - - CRC_DMABCR - CRC DMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - CRC_DMABCR - CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA. - 0 - 16 - read-write - - - - - CRC_DMACSAR - - CRC_DMACSAR - CRC DMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - CRC_DMACSAR - CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer just occurs. - 0 - 32 - read-only - - - - - CRC_DMACBCR - - CRC_DMACBCR - CRC DMA Current Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - CRC_DMACBCR - CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value. - 0 - 16 - read-only - - - - - CRC_DMAIER - - CRC_DMAIER - CRC DMA Interrupt Enable Control Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - CRC DMA Read/Write Target Abort Interrupt Enable - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during CRC DMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during CRC DMA transfer - #1 - - - read-write - - - BLKD_IE - CRC DMA Transfer Done Interrupt Enable - 1 - 1 - - - 0 - Interrupt generator Disabled when CRC DMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when CRC DMA transfer is done - #1 - - - read-write - - - - - CRC_DMAISR - - CRC_DMAISR - CRC DMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - CRC_WDATA - - CRC_WDATA - CRC Write Data Register - 0x80 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRC_WDATA - CRC Write Data Register - 0 - 32 - read-write - - - - - CRC_SEED - - CRC_SEED - CRC Seed Register - 0x84 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - CRC_SEED - CRC Seed Register\nThis field indicates the CRC seed value. - 0 - 32 - read-write - - - - - CRC_CHECKSUM - - CRC_CHECKSUM - CRC Checksum Register - 0x88 - read-only - 0x00000000 - 0xFFFFFFFF - - - CRC_CHECKSUM - CRC Checksum Register\nThis field indicates the CRC checksum. - 0 - 32 - read-only - - - - - - - DMA_GCR - PDMA Register Map - PDMA - 0x50008F00 - - - 0x0 - 0x14 - registers - - - - DMA_GCRCSR - - DMA_GCRCSR - DMA Global Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - CLK0_EN - PDMA Controller Channel 0 Clock Enable Control - 8 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK1_EN - PDMA Controller Channel 1 Clock Enable Control - 9 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK2_EN - PDMA Controller Channel 2 Clock Enable Control - 10 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK3_EN - PDMA Controller Channel 3 Clock Enable Control - 11 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK4_EN - PDMA Controller Channel 4 Clock Enable Control - 12 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK5_EN - PDMA Controller Channel 5 Clock Enable Control - 13 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CRC_CLK_EN - CRC Controller Clock Enable Control - 24 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - - - DMA_PDSSR0 - - DMA_PDSSR0 - DMA Service Selection Control Register 0 - 0x4 - read-write - 0x00FFFFFF - 0xFFFFFFFF - - - SPI0_RXSEL - PDMA SPI0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers: Reserved - 0 - 4 - read-write - - - SPI0_TXSEL - PDMA SPI0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 4 - 4 - read-write - - - SPI1_RXSEL - PDMA SPI1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 8 - 4 - read-write - - - SPI1_TXSEL - PDMA SPI1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 12 - 4 - read-write - - - SPI2_RXSEL - PDMA SPI2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 16 - 4 - read-write - - - SPI2_TXSEL - PDMA SPI2 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 20 - 4 - read-write - - - - - DMA_PDSSR1 - - DMA_PDSSR1 - DMA Service Selection Control Register 1 - 0x8 - read-write - 0x0FFFFFFF - 0xFFFFFFFF - - - UART0_RXSEL - This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers : Reserved - 0 - 4 - read-write - - - UART0_TXSEL - PDMA UART0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 4 - 4 - read-write - - - UART1_RXSEL - PDMA UART1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 8 - 4 - read-write - - - UART1_TXSEL - PDMA UART1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 12 - 4 - read-write - - - ADC_RXSEL - PDMA ADC RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 24 - 4 - read-write - - - - - DMA_GCRISR - - DMA_GCRISR - DMA Global Interrupt Status Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - INTR0 - Interrupt Pin Status of Channel 0\nThis bit is the Interrupt status of PDMA channel 0.\nNote: This bit is read only. - 0 - 1 - read-only - - - INTR1 - Interrupt Pin Status of Channel 1\nThis bit is the Interrupt status of PDMA channel 1.\nNote: This bit is read only. - 1 - 1 - read-only - - - INTR2 - Interrupt Pin Status of Channel 2\nThis bit is the Interrupt status of PDMA channel 2.\nNote: This bit is read only. - 2 - 1 - read-only - - - INTR3 - Interrupt Pin Status of Channel 3\nThis bit is the Interrupt status of PDMA channel 3.\nNote: This bit is read only. - 3 - 1 - read-only - - - INTR4 - Interrupt Pin Status of Channel 4\nThis bit is the Interrupt status of PDMA channel 4.\nNote: This bit is read only. - 4 - 1 - read-only - - - INTR5 - Interrupt Pin Status of Channel 5 \nThis bit is the Interrupt status of PDMA channel 5.\nNote: This bit is read only. - 5 - 1 - read-only - - - CRC_INTR - Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller.\nNote: This bit is read only. - 6 - 1 - read-only - - - INTR - Interrupt Pin Status\nThis bit is the Interrupt status of PDMA controller.\nNote: This bit is read only - 31 - 1 - read-only - - - - - DMA_PDSSR2 - - DMA_PDSSR2 - DMA Service Selection Control Register 2 - 0x10 - read-write - 0x00FFFFFF - 0xFFFFFFFF - - - I2S_RXSEL - PDMA I2S RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3\n4'b0100: CH4\n4'b0101: CH5\nOthers : Reserved - 0 - 4 - read-write - - - I2S_TXSEL - PDMA I2S TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 4 - 4 - read-write - - - PWM0_RXSEL - PDMA PWM0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM0 RX. Software can configure the RX channel setting by PWM0_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 8 - 4 - read-write - - - PWM1_RXSEL - PDMA PWM1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM1 RX. Software can configure the RX channel setting by PWM1_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 12 - 4 - read-write - - - PWM2_RXSEL - PDMA PWM2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM2 RX. Software can configure the RX channel setting by PWM2_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 16 - 4 - read-write - - - PWM3_RXSEL - PDMA PWM3 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM3 RX. Software can configure the RX channel setting by PWM3_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 20 - 4 - read-write - - - - - - - FMC - FMC Register Map - FMC - 0x5000C000 - - - 0x0 - 0x1C - registers - - - 0x40 - 0x4 - registers - - - - ISPCON - - ISPCON - ISP Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPEN - ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function. - 0 - 1 - - - 0 - ISP function Disabled - #0 - - - 1 - ISP function Enabled - #1 - - - read-write - - - BS - Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened - 1 - 1 - - - 0 - Boot from APROM - #0 - - - 1 - Boot from LDROM - #1 - - - read-write - - - APUEN - APROM Update Enable (Write-protection Bit) - 3 - 1 - - - 0 - APROM cannot be updated when the chip runs in APROM - #0 - - - 1 - APROM can be updated when the chip runs in APROM - #1 - - - read-write - - - CFGUEN - Enable Config-bits Update by ISP (Write-protection Bit) - 4 - 1 - - - 0 - ISP Disabled to update config-bits - #0 - - - 1 - ISP Enabled to update config-bits - #1 - - - read-write - - - LDUEN - LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit. - 5 - 1 - - - 0 - LDROM cannot be updated - #0 - - - 1 - LDROM can be updated - #1 - - - read-write - - - ISPFF - ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear. - 6 - 1 - read-write - - - - - ISPADR - - ISPADR - ISP Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPADR - ISP Address\nThe NuMicro( NUC123 Series is equipped with an embedded flash, and it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. - 0 - 32 - read-write - - - - - ISPDAT - - ISPDAT - ISP Data Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPDAT - ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. - 0 - 32 - read-write - - - - - ISPCMD - - ISPCMD - ISP Command Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPCMD - ISP Command - 0 - 6 - read-write - - - - - ISPTRG - - ISPTRG - ISP Trigger Control Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPGO - ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. - 0 - 1 - - - 0 - ISP operation is finished - #0 - - - 1 - ISP is progressed - #1 - - - read-write - - - - - DFBADR - - DFBADR - Data Flash Base Address Register - 0x14 - read-only - 0x0001F000 - 0xFFFFFFFF - - - DFBADR - Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nWhen DFVSEN is set to 0, the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is loaded from Config1.\nWhen DFVSEN is set to 1, the data flash size is fixed as 4K and the start address can be read from this register is fixed at 0x0001_F000. - 0 - 32 - read-only - - - - - FATCON - - FATCON - Flash Access Time Control Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - LFOM - Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1 - 4 - 1 - - - 0 - Low Frequency Optimization mode Disabled - #0 - - - 1 - Low Frequency Optimization mode Enabled - #1 - - - read-write - - - MFOM - Middle Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 50 MHz, chip can work more efficiently by setting this bit to 1 - 6 - 1 - - - 0 - Middle Frequency Optimization mode Disabled - #0 - - - 1 - Middle Frequency Optimization mode Enabled - #1 - - - read-write - - - - - ISPSTA - - ISPSTA - ISP Status Register - 0x40 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPGO - ISP Start Trigger (Read only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit 0. - 0 - 1 - - - 0 - ISP operation is finished - #0 - - - 1 - ISP is progressed - #1 - - - read-only - - - CBS - Config Boot Selection (Read only) - 1 - 2 - read-only - - - ISPFF - ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear.\nNote: This bit functions the same as ISPCON bit 6. - 6 - 1 - read-write - - - VECMAP - Vector Page Mapping Address (Read only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF} - 9 - 12 - read-only - - - - - - - diff --git a/ext/NUC123AN_v1.svd b/ext/NUC123AN_v1.svd deleted file mode 100755 index 7de15878b1..0000000000 --- a/ext/NUC123AN_v1.svd +++ /dev/null @@ -1,32352 +0,0 @@ - - - NUC123AN_v1 - 1.0 - NUC123AN_v1 SVD file - - - 8 - - 32 - - - - 32 - - read-write - - 0 - - 0 - - - - SCS - SCS Register Map - SCS - 0xE000E000 - - - 0x10 - 0xC - registers - - - 0x100 - 0x4 - registers - - - 0x180 - 0x4 - registers - - - 0x200 - 0x4 - registers - - - 0x280 - 0x4 - registers - - - 0x400 - 0x20 - registers - - - 0xD00 - 0x8 - registers - - - 0xD0C - 0x8 - registers - - - 0xD1C - 0x8 - registers - - - - SYST_CSR - - SYST_CSR - SysTick Control and Status Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - ENABLE - - 0 - 1 - - - 0 - Counter Disabled - #0 - - - 1 - Counter will operate in a multi-shot manner - #1 - - - read-write - - - TICKINT - - 1 - 1 - - - 0 - Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred - #0 - - - 1 - Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended - #1 - - - read-write - - - CLKSRC - - 2 - 1 - - - 0 - Clock source is (optional) external reference clock - #0 - - - 1 - Core clock used for SysTick - #1 - - - read-write - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. - 16 - 1 - read-write - - - - - SYST_RVR - - SYST_RVR - SysTick Reload Value Register - 0x14 - read-write - 0x00000000 - 0x00000000 - - - RELOAD - The value to load into the Current Value register when the counter reaches 0. - 0 - 24 - read-write - - - - - SYST_CVR - - SYST_CVR - SysTick Current Value Register - 0x18 - read-write - 0x00000000 - 0x00000000 - - - CURRENT - Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). - 0 - 24 - read-write - - - - - NVIC_ISER - - NVIC_ISER - IRQ0 ~ IRQ31 Set-Enable Control Register - 0x100 - read-write - 0x00000000 - 0xFFFFFFFF - - - SETENA - Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Associated interrupt Enabled - 1 - - - read-write - - - - - NVIC_ICER - - NVIC_ICER - IRQ0 ~ IRQ31 Clear-Enable Control Register - 0x180 - read-write - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Associated interrupt Disabled - 1 - - - read-write - - - - - NVIC_ISPR - - NVIC_ISPR - IRQ0 ~ IRQ31 Set-Pending Control Register - 0x200 - read-write - 0x00000000 - 0xFFFFFFFF - - - SETPEND - The register reads back with the current pending state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) - 1 - - - read-write - - - - - NVIC_ICPR - - NVIC_ICPR - IRQ0 ~ IRQ31 Clear-Pending Control Register - 0x280 - read-write - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - The register reads back with the current pending state. - 0 - 32 - - - 0 - No effect - 0 - - - 1 - Removes the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) - 1 - - - read-write - - - - - NVIC_IPR0 - - NVIC_IPR0 - IRQ0 ~ IRQ3 Priority Control Register - 0x400 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority of IRQ0\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_1 - Priority of IRQ1\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_2 - Priority of IRQ2\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_3 - Priority of IRQ3\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR1 - - NVIC_IPR1 - IRQ4 ~ IRQ7 Priority Control Register - 0x404 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_4 - Priority of IRQ4\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_5 - Priority of IRQ5\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_6 - Priority of IRQ6\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_7 - Priority of IRQ7\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR2 - - NVIC_IPR2 - IRQ8 ~ IRQ11 Priority Control Register - 0x408 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_8 - Priority of IRQ8\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_9 - Priority of IRQ9\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_10 - Priority of IRQ10\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_11 - Priority of IRQ11\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR3 - - NVIC_IPR3 - IRQ12 ~ IRQ15 Priority Control Register - 0x40C - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_12 - Priority of IRQ12\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_13 - Priority of IRQ13\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_14 - Priority of IRQ14\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_15 - Priority of IRQ15\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR4 - - NVIC_IPR4 - IRQ16 ~ IRQ19 Priority Control Register - 0x410 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_16 - Priority of IRQ16\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_17 - Priority of IRQ17\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_18 - Priority of IRQ18\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_19 - Priority of IRQ19\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR5 - - NVIC_IPR5 - IRQ20 ~ IRQ23 Priority Control Register - 0x414 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_20 - Priority of IRQ20\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_21 - Priority of IRQ21\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_22 - Priority of IRQ22\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_23 - Priority of IRQ23\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR6 - - NVIC_IPR6 - IRQ24 ~ IRQ27 Priority Control Register - 0x418 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_24 - Priority of IRQ24\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_25 - Priority of IRQ25\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_26 - Priority of IRQ26\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_27 - Priority of IRQ27\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - NVIC_IPR7 - - NVIC_IPR7 - IRQ28 ~ IRQ31 Priority Control Register - 0x41C - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_28 - Priority of IRQ28\n"0" denotes the highest priority and "3" denotes the lowest priority. - 6 - 2 - read-write - - - PRI_29 - Priority of IRQ29\n"0" denotes the highest priority and "3" denotes the lowest priority. - 14 - 2 - read-write - - - PRI_30 - Priority of IRQ30\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_31 - Priority of IRQ31\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - CPUID - - CPUID - CPUID Register - 0xD00 - read-only - 0x410CC200 - 0xFFFFFFFF - - - REVISION - Reads as 0x0 - 0 - 4 - read-only - - - PARTNO - Reads as 0xC20. - 4 - 12 - read-only - - - PART - Reads as 0xC for ARMv6-M parts - 16 - 4 - read-only - - - IMPLEMENTER - - 24 - 8 - read-only - - - - - ICSR - - ICSR - Interrupt Control and State Register - 0xD04 - read-write - 0x00000000 - 0xFFFFFFFF - - - VECTACTIVE - Contains the active exception number.\n - 0 - 6 - - - 0 - Thread mode - 0 - - - read-write - - - VECTPENDING - Indicates the exception number of the highest priority pending enabled exception:\n - 12 - 6 - - - 0 - No pending exceptions - 0 - - - read-write - - - ISRPENDING - Interrupt Pending Flag, Rxcluding NMI and Faults\nThis is a read only bit. - 22 - 1 - - - 0 - Interrupt not pending - #0 - - - 1 - Interrupt pending - #1 - - - read-write - - - ISRPREEMPT - If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit. - 23 - 1 - read-write - - - PENDSTCLR - SysTick Exception Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDST bit, you must "write 0 to PENDSTSET and write 1 to PENDSTCLR" at the same time. - 25 - 1 - - - 0 - No effect - #0 - - - 1 - Removes the pending state from the SysTick exception - #1 - - - read-write - - - PENDSTSET - SysTick Exception Set-pending Bit\nWrite:\n - 26 - 1 - - - 0 - No effect.\nSysTick exception is not pending - #0 - - - 1 - Changes SysTick exception state to pending.\nSysTick exception is pending - #1 - - - read-write - - - PENDSVCLR - PendSV Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDSV bit, you must "write 0 to PENDSVSET and write 1 to PENDSVCLR" at the same time. - 27 - 1 - - - 0 - No effect - #0 - - - 1 - Removes the pending state from the PendSV exception - #1 - - - read-write - - - PENDSVSET - PendSV Set-pending Bit\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending. - 28 - 1 - - - 0 - No effect.\nPendSV exception is not pending - #0 - - - 1 - Changes PendSV exception state to pending.\nPendSV exception is pending - #1 - - - read-write - - - NMIPENDSET - NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. - 31 - 1 - - - 0 - No effect.\nNMI exception is not pending - #0 - - - 1 - Changes NMI exception state to pending.\nNMI exception is pending - #1 - - - read-write - - - - - AIRCR - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - read-write - 0xFA050000 - 0xFFFFFFFF - - - VECTCLRACTIVE - Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. - 1 - 1 - read-write - - - SYSRESETREQ - Writing this bit 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested.\nThe bit is a write only and self-cleared as part of the reset sequence. - 2 - 1 - read-write - - - VECTORKEY - When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. - 16 - 16 - read-write - - - - - SCR - - SCR - System Control Register - 0xD10 - read-write - 0x00000000 - 0xFFFFFFFF - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - 1 - 1 - - - 0 - Do not sleep when returning to Thread mode - #0 - - - 1 - Enters sleep, or deep sleep, on return from an ISR to Thread mode - #1 - - - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode:\n - 2 - 1 - - - 0 - Sleep - #0 - - - 1 - Deep sleep - #1 - - - read-write - - - SEVONPEND - Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. - 4 - 1 - - - 0 - Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded - #0 - - - 1 - Enabled events and all interrupts, including disabled interrupts, can wake up the processor - #1 - - - read-write - - - - - SHPR2 - - SHPR2 - System Handler Priority Register 2 - 0xD1C - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_11 - Priority of system handler 11 - SVCall\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - SHPR3 - - SHPR3 - System Handler Priority Register 3 - 0xD20 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRI_14 - Priority of System Handler 14 - PendSV\n"0" denotes the highest priority and "3" denotes the lowest priority. - 22 - 2 - read-write - - - PRI_15 - Priority of System Handler 15 - SysTick\n"0" denotes the highest priority and "3" denotes the lowest priority. - 30 - 2 - read-write - - - - - - - INT - INT Register Map - INT - 0x50000300 - - - 0x0 - 0x88 - registers - - - - IRQ0_SRC - - IRQ0_SRC - IRQ0 (BOD) interrupt source identity - 0x0 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: BOD_INT - 0 - 3 - read-only - - - - - IRQ1_SRC - - IRQ1_SRC - IRQ1 (WDT) interrupt source identity - 0x4 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: WDT_INT - 0 - 3 - read-only - - - - - IRQ2_SRC - - IRQ2_SRC - IRQ2 (EINT0) interrupt source identity - 0x8 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: EINT0 - external interrupt 0 from PB.14 - 0 - 3 - read-only - - - - - IRQ3_SRC - - IRQ3_SRC - IRQ3 (EINT1) interrupt source identity - 0xC - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: EINT1 - external interrupt 1 from PB.15 or PD.11 - 0 - 3 - read-only - - - - - IRQ4_SRC - - IRQ4_SRC - IRQ4 (GPA/B) interrupt source identity - 0x10 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: GPB_INT\nBit0: GPA_INT - 0 - 3 - read-only - - - - - IRQ5_SRC - - IRQ5_SRC - IRQ5 (GPC/D/F) interrupt source identity - 0x14 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit3: GPF_INT\nBit2: 0\nBit1: GPD_INT\nBit0: GPC_INT - 0 - 3 - read-only - - - - - IRQ6_SRC - - IRQ6_SRC - IRQ6 (PWMA) interrupt source identity - 0x18 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT - 0 - 4 - read-only - - - - - IRQ7_SRC - - IRQ7_SRC - IRQ7 (Reserved) interrupt source identity - 0x1C - read-only - 0x00000000 - 0x00000000 - - - - IRQ8_SRC - - IRQ8_SRC - IRQ8 (TMR0) interrupt source identity - 0x20 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: TMR0_INT - 0 - 3 - read-only - - - - - IRQ9_SRC - - IRQ9_SRC - IRQ9 (TMR1) interrupt source identity - 0x24 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: TMR1_INT - 0 - 3 - read-only - - - - - IRQ10_SRC - - IRQ10_SRC - IRQ10 (TMR2) interrupt source identity - 0x28 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: TMR2_INT - 0 - 3 - read-only - - - - - IRQ11_SRC - - IRQ11_SRC - IRQ11 (TMR3) interrupt source identity - 0x2C - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: TMR3_INT - 0 - 3 - read-only - - - - - IRQ12_SRC - - IRQ12_SRC - IRQ12 (UART0) interrupt source identity - 0x30 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: URT0_INT - 0 - 3 - read-only - - - - - IRQ13_SRC - - IRQ13_SRC - IRQ13 (UART1) interrupt source identity - 0x34 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: UART1_INT - 0 - 3 - read-only - - - - - IRQ14_SRC - - IRQ14_SRC - IRQ14 (SPI0) interrupt source identity - 0x38 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: SPI0_INT - 0 - 3 - read-only - - - - - IRQ15_SRC - - IRQ15_SRC - IRQ15 (SPI1) interrupt source identity - 0x3C - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: SPI1_INT - 0 - 3 - read-only - - - - - IRQ16_SRC - - IRQ16_SRC - IRQ16 (SPI2) interrupt source identity - 0x40 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: SPI2_INT - 0 - 3 - read-only - - - - - IRQ17_SRC - - IRQ17_SRC - IRQ17 (Reserved) interrupt source identity - 0x44 - read-only - 0x00000000 - 0x00000000 - - - - IRQ18_SRC - - IRQ18_SRC - IRQ18 (I2C0) interrupt source identity - 0x48 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: I2C0_INT - 0 - 3 - read-only - - - - - IRQ19_SRC - - IRQ19_SRC - IRQ19 (I2C1) interrupt source identity - 0x4C - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: I2C1_INT - 0 - 3 - read-only - - - - - IRQ20_SRC - - IRQ20_SRC - IRQ20 (Reserved) interrupt source identity - 0x50 - read-only - 0x00000000 - 0x00000000 - - - - IRQ21_SRC - - IRQ21_SRC - IRQ21 (Reserved) interrupt source identity - 0x54 - read-only - 0x00000000 - 0x00000000 - - - - IRQ22_SRC - - IRQ22_SRC - IRQ22 (Reserved ) interrupt source identity - 0x58 - read-only - 0x00000000 - 0x00000000 - - - - IRQ23_SRC - - IRQ23_SRC - IRQ23 (USBD) interrupt source identity - 0x5C - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: USB_INT - 0 - 3 - read-only - - - - - IRQ24_SRC - - IRQ24_SRC - IRQ24 (PS/2) interrupt source identity - 0x60 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: PS2_INT - 0 - 3 - read-only - - - - - IRQ25_SRC - - IRQ25_SRC - IRQ25 (Reserved) interrupt source identity - 0x64 - read-only - 0x00000000 - 0x00000000 - - - - IRQ26_SRC - - IRQ26_SRC - IRQ26 (PDMA) interrupt source identity - 0x68 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: PDMA_INT - 0 - 3 - read-only - - - - - IRQ27_SRC - - IRQ27_SRC - IRQ27 (I2S) interrupt source identity - 0x6C - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: I2S_INT - 0 - 3 - read-only - - - - - IRQ28_SRC - - IRQ28_SRC - IRQ28 (PWRWU) interrupt source identity - 0x70 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: PWRWU_INT - 0 - 3 - read-only - - - - - IRQ29_SRC - - IRQ29_SRC - IRQ29 (ADC) interrupt source identity - 0x74 - read-only - 0x00000000 - 0x00000000 - - - INT_SRC - Bit2: 0\nBit1: 0\nBit0: ADC_INT - 0 - 3 - read-only - - - - - IRQ30_SRC - - IRQ30_SRC - IRQ30 (Reserved) interrupt source identity - 0x78 - read-only - 0x00000000 - 0x00000000 - - - - IRQ31_SRC - - IRQ31_SRC - IRQ31 (Reserved) interrupt source identity - 0x7C - read-only - 0x00000000 - 0x00000000 - - - - NMI_SEL - - NMI_SEL - NMI source interrupt select control register - 0x80 - read-write - 0x00000000 - 0xFFFFFFFF - - - NMI_SEL - NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. - 0 - 5 - read-write - - - NMI_EN - NMI Interrupt Enable\n - 8 - 1 - - - 0 - NMI interrupt Disabled - #0 - - - 1 - NMI interrupt Enabled - #1 - - - read-write - - - - - MCU_IRQ - - MCU_IRQ - MCU IRQ Number identity register - 0x84 - read-write - 0x00000000 - 0xFFFFFFFF - - - MCU_IRQ - MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, Normal mode and Test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect. - 0 - 32 - read-write - - - - - - - GCR - GCR Register Map - GCR - 0x50000000 - - - 0x0 - 0x10 - registers - - - 0x18 - 0x4 - registers - - - 0x24 - 0x4 - registers - - - 0x30 - 0x10 - registers - - - 0x44 - 0x4 - registers - - - 0x50 - 0x8 - registers - - - 0xA0 - 0x4 - registers - - - 0xC0 - 0x8 - registers - - - 0xCC - 0x4 - registers - - - 0x100 - 0x4 - registers - - - - PDID - - PDID - Part Device Identification Number Register - 0x0 - read-only - 0x00012300 - 0xFFFFFF00 - - - PDID - Part Device Identification Number\nThis register reflects the device part number code. S/W can read this register to identify which device is used. - 0 - 32 - read-only - - - - - RSTSRC - - RSTSRC - System Reset Source Register - 0x4 - read-write - 0x00000000 - 0xFFFFFF00 - - - RSTS_POR - The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No reset from POR or CHIP_RST - #0 - - - 1 - Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_RESET - The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - No reset from /RESET pin - #0 - - - 1 - Pin /RESET had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_WDT - The RSTS_WDT flag is set by the "reset signal" from the watchdog timer to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 2 - 1 - - - 0 - No reset from watchdog timer - #0 - - - 1 - Watchdog timer had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_LVR - The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 3 - 1 - - - 0 - No reset from LVR - #0 - - - 1 - LVR controller had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_BOD - The RSTS_BOD flag is set by the "reset signal" from the Brown-out-Detector to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 4 - 1 - - - 0 - No reset from BOD - #0 - - - 1 - BOD had issued the reset signal to reset the system - #1 - - - read-write - - - RSTS_SYS - The RSTS_SYS flag is set by the "reset signal" from the Cortex_M0 kernel to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. - 5 - 1 - - - 0 - No reset from Cortex_M0 - #0 - - - 1 - Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel - #1 - - - read-write - - - RSTS_CPU - The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero. - 7 - 1 - - - 0 - No reset from CPU - #0 - - - 1 - Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 - #1 - - - read-write - - - - - IPRSTC1 - - IPRSTC1 - IP Reset Control Register1 - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - CHIP_RST - CHIP One-shot Reset (Write-protection Bit)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nFor the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100\n - 0 - 1 - - - 0 - CHIP normal operation - #0 - - - 1 - CHIP one-shot reset - #1 - - - read-write - - - CPU_RST - CPU kernel one-shot reset (Write-protection Bit)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100\n - 1 - 1 - - - 0 - CPU normal operation - #0 - - - 1 - CPU one-shot reset - #1 - - - read-write - - - PDMA_RST - PDMA Controller Reset (Write-protection)\nSetting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n - 2 - 1 - - - 0 - PDMA controller normal operation - #0 - - - 1 - PDMA controller reset - #1 - - - read-write - - - - - IPRSTC2 - - IPRSTC2 - IP Reset Control Register2 - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - GPIO_RST - GPIO controller Reset\n - 1 - 1 - - - 0 - GPIO controller normal operation - #0 - - - 1 - GPIO controller reset - #1 - - - read-write - - - TMR0_RST - Timer0 controller Reset\n - 2 - 1 - - - 0 - Timer0 controller normal operation - #0 - - - 1 - Timer0 controller reset - #1 - - - read-write - - - TMR1_RST - Timer1 controller Reset\n - 3 - 1 - - - 0 - Timer1 controller normal operation - #0 - - - 1 - Timer1 controller reset - #1 - - - read-write - - - TMR2_RST - Timer2 controller Reset\n - 4 - 1 - - - 0 - Timer2 controller normal operation - #0 - - - 1 - Timer2 controller reset - #1 - - - read-write - - - TMR3_RST - Timer3 controller Reset\n - 5 - 1 - - - 0 - Timer3 controller normal operation - #0 - - - 1 - Timer3 controller reset - #1 - - - read-write - - - I2C0_RST - I2C0 controller Reset\n - 8 - 1 - - - 0 - I2C0 controller normal operation - #0 - - - 1 - I2C0 controller reset - #1 - - - read-write - - - I2C1_RST - I2C1 controller Reset\n - 9 - 1 - - - 0 - I2C1 controller normal operation - #0 - - - 1 - I2C1 controller reset - #1 - - - read-write - - - SPI0_RST - SPI0 controller Reset\n - 12 - 1 - - - 0 - SPI0 controller normal operation - #0 - - - 1 - SPI0 controller reset - #1 - - - read-write - - - SPI1_RST - SPI1 controller Reset\n - 13 - 1 - - - 0 - SPI1 controller normal operation - #0 - - - 1 - SPI1 controller reset - #1 - - - read-write - - - SPI2_RST - SPI2 controller Reset \n - 14 - 1 - - - 0 - SPI2 controller normal operation - #0 - - - 1 - SPI2 controller reset - #1 - - - read-write - - - UART0_RST - UART0 controller Reset\n - 16 - 1 - - - 0 - UART0 controller normal operation - #0 - - - 1 - UART0 controller reset - #1 - - - read-write - - - UART1_RST - UART1 controller Reset\n - 17 - 1 - - - 0 - UART1 controller normal operation - #0 - - - 1 - UART1 controller reset - #1 - - - read-write - - - PWM03_RST - PWM03 controller Reset\n - 20 - 1 - - - 0 - PWM03 controller normal operation - #0 - - - 1 - PWM03 controller reset - #1 - - - read-write - - - PS2_RST - PS/2 Controller Reset\n - 23 - 1 - - - 0 - PS/2 controller normal operation - #0 - - - 1 - PS/2 controller reset - #1 - - - read-write - - - USBD_RST - USB Device Controller Reset\n - 27 - 1 - - - 0 - USB device controller normal operation - #0 - - - 1 - USB device controller reset - #1 - - - read-write - - - ADC_RST - ADC Controller Reset\n - 28 - 1 - - - 0 - ADC controller normal operation - #0 - - - 1 - ADC controller reset - #1 - - - read-write - - - I2S_RST - I2S Controller Reset\n - 29 - 1 - - - 0 - I2S controller normal operation - #0 - - - 1 - I2S controller reset - #1 - - - read-write - - - - - BODCR - - BODCR - Brown-out Detector Control Register - 0x18 - read-write - 0x00000080 - 0xFFFFFFF0 - - - BOD_EN - Brown-out Detector Enable (Write-protection Bit)\nThe default value is set by flash controller user configuration register config0 bit[23].\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 1 - - - 0 - Brown-out Detector function Disabled - #0 - - - 1 - Brown-out Detector function Enabled - #1 - - - read-write - - - BOD_VL - Brown-out Detector Threshold Voltage Selection (Write-protection Bits)\n - 1 - 2 - read-write - - - BOD_RSTEN - Brown-out Reset Enable (Write-protection Bit)\nWhile the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).\nThe default value is set by flash controller user configuration register config0 bit[20].\nThis bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 3 - 1 - - - 0 - Brown-out "INTERRUPT" function Enabled - #0 - - - 1 - Brown-out "RESET" function Enabled - #1 - - - read-write - - - BOD_INTF - Brown-out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 4 - 1 - - - 0 - Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting - #0 - - - 1 - When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled - #1 - - - read-write - - - BOD_LPM - Brown-out Detector Low power Mode (Write-protection Bit)\nThe BOD consumes about 100 uA in Normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 5 - 1 - - - 0 - BOD operated in Normal mode (Default) - #0 - - - 1 - BOD low power mode Enabled - #1 - - - read-write - - - BOD_OUT - Brown-out Detector Output Status\n - 6 - 1 - - - 0 - Brown-out Detector output status is 0, which means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 - #0 - - - 1 - Brown-out Detector output status is 1, which means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0 - #1 - - - read-write - - - LVR_EN - Low Voltage Reset Enable (Write-protection Bit)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 7 - 1 - - - 0 - Low Voltage Reset function Disabled - #0 - - - 1 - Low Voltage Reset function Enabled- After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (Default) - #1 - - - read-write - - - - - PORCR - - PORCR - Power-On-Reset Controller Register - 0x24 - read-write - 0x00000000 - 0xFFFFFF00 - - - POR_DIS_CODE - The register is used for the Power-On-Reset enable control (Write-protection Bits)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will become active again when this field is set to another value or chip is reset by other reset source, including:\n/RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. - 0 - 16 - read-write - - - - - GPA_MFP - - GPA_MFP - GPIOA Multiple Function and Input Type Control Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPA_MFP10 - PA.10 Pin Function Selection\n - 10 - 1 - read-write - - - GPA_MFP11 - PA.11 Pin Function Selection\n - 11 - 1 - read-write - - - GPA_MFP12 - PA.12 Pin Function Selection\n - 12 - 1 - read-write - - - GPA_MFP13 - PA.13 Pin Function Selection\n - 13 - 1 - read-write - - - GPA_MFP14 - PA.14 Pin Function Selection\n - 14 - 1 - read-write - - - GPA_MFP15 - PA.15 Pin Function Selection\n - 15 - 1 - read-write - - - GPA_TYPEn - GPA[9:0] are reserved in this chip. - 16 - 16 - - - 0 - GPIOA[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOA[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPB_MFP - - GPB_MFP - GPIOB Multiple Function and Input Type Control Register - 0x34 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPB_MFP0 - PB.0 Pin Function Selection\n - 0 - 1 - - - 0 - GPIOB[0] is selected to the pin PB.0 - #0 - - - 1 - UART0 RXD0 function is selected to the pin PB.0 - #1 - - - read-write - - - GPB_MFP1 - PB.1 Pin Function Selection\n - 1 - 1 - - - 0 - GPIOB[1] is selected to the pin PB.1 - #0 - - - 1 - UART0 TXD0 function is selected to the pin PB.1 - #1 - - - read-write - - - GPB_MFP2 - PB.2 Pin Function Selection\n - 2 - 1 - read-write - - - GPB_MFP3 - PB.3 Pin Function Selection\n - 3 - 1 - read-write - - - GPB_MFP4 - PB.4 Pin Function Selection\n - 4 - 1 - read-write - - - GPB_MFP5 - PB. - 5 - 1 - read-write - - - GPB_MFP6 - PB.6 Pin Function Selection\n - 6 - 1 - read-write - - - GPB_MFP7 - PB.7 Pin Function Selection\n - 7 - 1 - read-write - - - GPB_MFP8 - PB.8 Pin Function Selection\n - 8 - 1 - read-write - - - GPB_MFP9 - PB.9 Pin Function Selection\n - 9 - 1 - read-write - - - GPB_MFP10 - PB.10 Pin Function Selection\n - 10 - 1 - read-write - - - GPB_MFP12 - PB.12 Pin Function Selection\n - 12 - 1 - read-write - - - GPB_MFP13 - PB.13 Pin Function Selection\n - 13 - 1 - read-write - - - GPB_MFP14 - PB.14 Pin Function Selection\n - 14 - 1 - read-write - - - GPB_MFP15 - PB.15 Pin Function Selection\n - 15 - 1 - read-write - - - GPB_TYPEn - - 16 - 16 - - - 0 - GPIOB[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOB[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPC_MFP - - GPC_MFP - GPIOC Multiple Function and Input Type Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPC_MFP0 - PC.0 Pin Function Selection\n - 0 - 1 - read-write - - - GPC_MFP1 - PC.1 Pin Function Selection\n - 1 - 1 - read-write - - - GPC_MFP2 - PC.2 Pin Function Selection\n - 2 - 1 - read-write - - - GPC_MFP3 - PC.3 Pin Function Selection\n - 3 - 1 - read-write - - - GPC_MFP4 - PC.4 Pin Function Selection\n - 4 - 1 - read-write - - - GPC_MFP5 - PC.5 Pin Function Selection\n - 5 - 1 - read-write - - - GPC_MFP8 - PC.8 Pin Function Selection\n - 8 - 1 - read-write - - - GPC_MFP9 - PC.9 Pin Function Selection\n - 9 - 1 - - - 0 - GPIOC[9] is selected to the pin PC.9 - #0 - - - 1 - SPICLK1 (SPI1) function is selected to the pin PC.9 - #1 - - - read-write - - - GPC_MFP10 - PC.10 Pin Function Selection\n - 10 - 1 - - - 0 - The GPIOC[10] is selected to the pin PC.10 - #0 - - - 1 - MISO10 (SPI1 master input, slave output pin-0) function is selected to the pin PC.10 - #1 - - - read-write - - - GPC_MFP11 - PC.11 Pin Function Selection\n - 11 - 1 - - - 0 - GPIOC[11] is selected to the pin PC.11 - #0 - - - 1 - MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PC.11 - #1 - - - read-write - - - GPC_MFP12 - PC.12 Pin Function Selection\n - 12 - 1 - read-write - - - GPC_MFP13 - PC.13 Pin Function Selection\n - 13 - 1 - read-write - - - GPC_TYPEn - - 16 - 16 - - - 0 - GPIOC[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOC[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPD_MFP - - GPD_MFP - GPIOD Multiple Function and Input Type Control Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - GPD_MFP0 - PD.0 Pin Function Selection \n - 0 - 1 - read-write - - - GPD_MFP1 - PD.1 Pin Function Selection\n - 1 - 1 - read-write - - - GPD_MFP2 - PD.2 Pin Function Selection\n - 2 - 1 - read-write - - - GPD_MFP3 - PD.3 Pin Function Selection\n - 3 - 1 - read-write - - - GPD_MFP4 - PD.4 Pin Function Selection \n - 4 - 1 - read-write - - - GPD_MFP5 - PD.5 Pin Function Selection \n - 5 - 1 - read-write - - - GPD_MFP8 - PD.8 Pin Function Selection\n - 8 - 1 - - - 0 - GPIOD[8] is selected to the pin PD8 - #0 - - - 1 - MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PD8 - #1 - - - read-write - - - GPD_MFP9 - PD.9 Pin Function Selection\n - 9 - 1 - read-write - - - GPD_MFP10 - PD.10 Pin Function Selection \n - 10 - 1 - - - 0 - GPIOD[10] is selected to the pin PD.10 - #0 - - - 1 - CLKO function is selected to the pin PD.10 - #1 - - - read-write - - - GPD_MFP11 - PD.11 Pin Function Selection\n - 11 - 1 - - - 0 - GPIOD[11] is selected to the pin PD.11 - #0 - - - 1 - /INT1 function is selected to the pin PD.11 - #1 - - - read-write - - - GPD_TYPEn - - 16 - 16 - - - 0 - GPIOD[15:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOD[15:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - GPF_MFP - - GPF_MFP - GPIOF Multiple Function and Input Type Control Register - 0x44 - read-write - 0x00000000 - 0xFFFFFFF0 - - - GPF_MFP0 - PF.0 Pin Function Selection\n - 0 - 1 - - - 0 - GPIOF[0] is selected to the pin PF.0 - #0 - - - 1 - XT1_OUT function is selected to the pin PF.0 - #1 - - - read-write - - - GPF_MFP1 - PF.1 Pin Function Selection \n - 1 - 1 - - - 0 - GPIOF[1] is selected to the pin PF.1 - #0 - - - 1 - XT1_IN function is selected to the pin PF.1 - #1 - - - read-write - - - GPF_MFP2 - PF.2 Pin Function Selection\n - 2 - 1 - read-write - - - GPF_MFP3 - PF.3 Pin Function Selection \n - 3 - 1 - read-write - - - GPF_TYPEn - - 16 - 4 - - - 0 - GPIOF[3:0] I/O input Schmitt Trigger function Disabled - 0 - - - 1 - GPIOF[3:0] I/O input Schmitt Trigger function Enabled - 1 - - - read-write - - - - - ALT_MFP - - ALT_MFP - Alternative Multiple Function Pin Control Register - 0x50 - read-write - 0x00000000 - 0xFFFFFFFF - - - PB10_MFP1 - PB.10 Pin Alternate Function Selection\n - 0 - 1 - read-write - - - PB9_MFP1 - PB.9 Pin Alternate Function Selection\n - 1 - 1 - read-write - - - PC0_MFP1 - PC.0 Pin Function Selection\n - 5 - 1 - read-write - - - PC1_MFP1 - PC.1 Pin Alternate Function Selection\n - 6 - 1 - read-write - - - PC2_MFP1 - PC.2 Pin Alternate Function Selection\n - 7 - 1 - read-write - - - PC3_MFP1 - PC.3 Pin Alternate Function Selection\n - 8 - 1 - read-write - - - PA15_MFP1 - PA.15 Pin Alternate Function Selection\n - 9 - 1 - read-write - - - PB12_MFP1 - PB.12 Pin Alternate Function Selection\n - 10 - 1 - read-write - - - PA11_MFP1 - PA.11 Pin Function Selection\n - 11 - 1 - read-write - - - PA10_MFP1 - PA.10 Pin Function Selection\n - 12 - 1 - read-write - - - PB4_MFP1 - PB.4 Pin Function Selection\n - 15 - 1 - read-write - - - PB7_MFP1 - PB.7 Pin Alternate Function Selection\n - 16 - 1 - read-write - - - PB6_MFP1 - PB.6 Pin Alternate Function Selection\n - 17 - 1 - read-write - - - PB5_MFP1 - PB. - 18 - 1 - read-write - - - PC12_MFP1 - PC.12 Pin Function Selection\n - 20 - 1 - read-write - - - PC13_MFP1 - PC.13 Pin Function Selection\n - 21 - 1 - read-write - - - PB15_MFP1 - PB.15 Pin Alternate Function Selection\n - 24 - 1 - read-write - - - PB2_MFP1 - PB.2 Pin Alternate Function Selection\n - 26 - 1 - read-write - - - PB3_MFP1 - PB.3 Pin Alternate Function Selection\n - 27 - 1 - read-write - - - PC4_MFP1 - PC.4 Pin Function Selection\n - 29 - 1 - read-write - - - PC5_MFP1 - PC.5 Pin Function Selection\n - 30 - 1 - read-write - - - - - ALT_MFP1 - - ALT_MFP1 - Alternative Multiple Function Pin Control Register 1 - 0x54 - read-write - 0x00000000 - 0xFFFFFFFF - - - PD0_MFP1 - PD.0 Pin Function Selection \n - 16 - 1 - read-write - - - PD1_MFP1 - PD.1 Pin Function Selection\n - 17 - 1 - read-write - - - PD2_MFP1 - PD.2 Pin Function Selection\n - 18 - 1 - read-write - - - PD3_MFP1 - PD.3 Pin Function Selection\n - 19 - 1 - read-write - - - PD4_MFP1 - PD.4 Pin Function Selection \n - 20 - 1 - read-write - - - PD5_MFP1 - PD.5 Pin Function Selection \n - 21 - 1 - read-write - - - PF2_MFP1 - PF.2 Pin Function Selection\n - 24 - 2 - read-write - - - PF3_MFP1 - PF.3 Pin Function Selection \n - 26 - 2 - read-write - - - - - DFP_CSR - - DFP_CSR - Pin Conflict Status - 0xA0 - read-only - 0x00000000 - 0xFFFFFFFF - - - DFP0_CST - Conflict Status of PD.9\n - 0 - 1 - - - 0 - PD.9 worked normally - #0 - - - 1 - PD.9 is conflicted - #1 - - - read-only - - - DFP1_CST - Conflict Status of PD.10\n - 1 - 1 - - - 0 - PD.10 worked normally - #0 - - - 1 - PD.10 is conflicted - #1 - - - read-only - - - DFP2_CST - Conflict Status of PD.11\n - 2 - 1 - - - 0 - PD.11 worked normally - #0 - - - 1 - PD.11 is conflicted - #1 - - - read-only - - - DFP3_CST - Conflict Status of PB.4\n - 3 - 1 - - - 0 - PB.4 worked normally - #0 - - - 1 - PB.4 is conflicted - #1 - - - read-only - - - DFP4_CST - Conflict Status of PB.5\n - 4 - 1 - - - 0 - PB.5 worked normally - #0 - - - 1 - PB.5 is conflicted - #1 - - - read-only - - - DFP5_CST - Conflict Status of PB.6\n - 5 - 1 - - - 0 - PB.6 worked normally - #0 - - - 1 - PB.6 is conflicted - #1 - - - read-only - - - DFP6_CST - Conflict Status of PB.7\n - 6 - 1 - - - 0 - PB.7 worked normally - #0 - - - 1 - PB.7 is conflicted - #1 - - - read-only - - - - - GPA_IOCR - - GPA_IOCR - GPIOA IO Control Register - 0xC0 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPA10_DS - PA.10 Pin Driving Strength Selection\n - 10 - 1 - - - 0 - PA.10 strong driving strength mode Disabled - #0 - - - 1 - PA.10 strong driving strength mode Enabled - #1 - - - read-write - - - GPA11_DS - PA.11 Pin Driving Strength Selection\n - 11 - 1 - - - 0 - PA.11 strong driving strength mode Disabled - #0 - - - 1 - PA.11 strong driving strength mode Enabled - #1 - - - read-write - - - - - GPB_IOCR - - GPB_IOCR - GPIOB IO Control Register - 0xC4 - read-write - 0x00000000 - 0xFFFFFFFF - - - GPB4_DS - PB.4 Pin Driving Strength Selection\n - 4 - 1 - - - 0 - PB.4 strong driving strength mode Disabled - #0 - - - 1 - PB.4 strong driving strength mode Enabled - #1 - - - read-write - - - GPB5_DS - PB.5 Pin Driving Strength Selection\n - 5 - 1 - - - 0 - PB.5 strong driving strength mode Disabled - #0 - - - 1 - PB.5 strong driving strength mode Enabled - #1 - - - read-write - - - GPB6_DS - PB.6 Pin Driving Strength Selection\n - 6 - 1 - - - 0 - PB.6 strong driving strength mode Disabled - #0 - - - 1 - PB.6 strong driving strength mode Enabled - #1 - - - read-write - - - GPB7_DS - PB.7 Pin Driving Strength Selection\n - 7 - 1 - - - 0 - PB.7 strong driving strength mode Disabled - #0 - - - 1 - PB.7 strong driving strength mode Enabled - #1 - - - read-write - - - GPB8_DS - PB.8 Pin Driving Strength Selection\n - 8 - 1 - - - 0 - PB.8 strong driving strength mode Disabled - #0 - - - 1 - PB.8 strong driving strength mode Enabled - #1 - - - read-write - - - GPB12_DS - PB.12 Pin Driving Strength Selection\n - 12 - 1 - - - 0 - PB.12 strong driving strength mode Disabled - #0 - - - 1 - PB.12 strong driving strength mode Enabled - #1 - - - read-write - - - GPB13_DS - PB.13 Pin Driving Strength Selection\n - 13 - 1 - - - 0 - PB.13 strong driving strength mode Disabled - #0 - - - 1 - PB.13 strong driving strength mode Enabled - #1 - - - read-write - - - GPB14_DS - PB.14 Pin Driving Strength Selection\n - 14 - 1 - - - 0 - PB.14 strong driving strength mode Disabled - #0 - - - 1 - PB.14 strong driving strength mode Enabled - #1 - - - read-write - - - - - GPD_IOCR - - GPD_IOCR - GPIOD IO Control Register - 0xCC - read-write - 0x00000000 - 0xFFFFFFFF - - - GPD8_DS - PD.8 Pin Driving Strength Selection\n - 8 - 1 - - - 0 - PD.8 strong driving strength mode Disabled - #0 - - - 1 - PD.8 strong driving strength mode Enabled - #1 - - - read-write - - - GPD9_DS - PD.9 Pin Driving Strength Selection\n - 9 - 1 - - - 0 - PD.9 strong driving strength mode Disabled - #0 - - - 1 - PD.9 strong driving strength mode Enabled - #1 - - - read-write - - - GPD10_DS - PD.10 Pin Driving Strength Selection\n - 10 - 1 - - - 0 - PD.10 strong driving strength mode Disabled - #0 - - - 1 - PD.10 strong driving strength mode Enabled - #1 - - - read-write - - - GPD11_DS - PD.11 Pin Driving Strength Selection\n - 11 - 1 - - - 0 - PD.11 strong driving strength mode Disabled - #0 - - - 1 - PD.11 strong driving strength mode Enabled - #1 - - - read-write - - - - - REGWRPROT - - REGWRPROT - Register Write Protect register - 0x100 - read-write - 0x00000000 - 0xFFFFFFFF - - - REGPROTDIS - Register Write-Protection Disable index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enabled)\nCLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018 - 0 - 1 - - - 0 - Write-protection Enabled for writing protected registers. Any write to the protected register is ignored - #0 - - - 1 - Write-protection Disabled for writing protected registers - #1 - - - read-only - - - REGWRPROT - Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers has to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. - 0 - 8 - write-only - - - - - - - CLK - CLK Register Map - CLK - 0x50000200 - - - 0x0 - 0x28 - registers - - - 0x2C - 0x4 - registers - - - - PWRCON - - PWRCON - System Power-down Control Register - 0x0 - read-write - 0x00000010 - 0xFFFFFFF0 - - - XTL12M_EN - External 4~24 MHz High Speed Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically\n - 0 - 1 - - - 0 - External 4~24 MHz high speed crystal Disabled - #0 - - - 1 - External 4~24 MHz high speed crystal Enabled - #1 - - - read-write - - - OSC22M_EN - Internal 22.1184 MHz High Speed Oscillator Enable (Write-protection Bit)\n - 2 - 1 - - - 0 - Internal 22.1184 MHz high speed oscillator Disabled - #0 - - - 1 - Internal 22.1184 MHz high speed oscillator Enabled - #1 - - - read-write - - - OSC10K_EN - Internal 10 kHz Low Speed Oscillator Enable (Write-protection Bit)\n - 3 - 1 - - - 0 - Internal 10 kHz low speed oscillator Disabled - #0 - - - 1 - Internal 10 kHz low speed oscillator Enabled - #1 - - - read-write - - - PD_WU_DLY - Enable the Wake-up Delay Counter (Write-protection Bit)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n - 4 - 1 - - - 0 - Clock cycles delay Disabled - #0 - - - 1 - Clock cycles delay Enabled - #1 - - - read-write - - - PD_WU_INT_EN - Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. - 5 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PD_WU_STS - Power-down Mode Wake-up Interrupt Status\nSet by "Power-down wake-up event", which indicates that resume from Power-down mode" \nThe flag is set if the GPIO, USB, UART, WDT, CAN, ACMP or BOD wake-up occurred.\nWrite 1 to clear the bit to zero.\nNote: This bit works only when PD_WU_INT_EN (PWRCON[5]) set to 1. - 6 - 1 - read-write - - - PWR_DOWN_EN - System Power-down Enable Bit (Write-protection Bit)\nWhen this bit is set to 1, the chip Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit.\n(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) If the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. User needs to set this bit again for next Power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the internal 10 kHz low speed oscillator is not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator.\n - 7 - 1 - - - 0 - Chip operating normally or chip in Idle mode because of WFI command - #0 - - - 1 - Chip entering the Power-down mode instantly or wait CPU sleep command WFI - #1 - - - read-write - - - PD_WAIT_CPU - Power-down Entry Conditions Control (Write-protection Bit)\n - 8 - 1 - - - 0 - Chip entering Power-down mode when the PWR_DOWN_EN bit is set to 1 - #0 - - - 1 - Chip entering Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction - #1 - - - read-write - - - - - AHBCLK - - AHBCLK - AHB Devices Clock Enable Control Register - 0x4 - read-write - 0x0000000D - 0xFFFFFFFF - - - PDMA_EN - PDMA Controller Clock Enable Control\n - 1 - 1 - - - 0 - PDMA engine clock Disabled - #0 - - - 1 - PDMA engine clock Enabled - #1 - - - read-write - - - ISP_EN - Flash ISP Controller Clock Enable Control\n - 2 - 1 - - - 0 - Flash ISP engine clock Disabled - #0 - - - 1 - Flash ISP engine clock Enabled - #1 - - - read-write - - - - - APBCLK - - APBCLK - APB Devices Clock Enable Control Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFF0 - - - WDT_EN - Watchdog Timer Clock Enable (Write-protection Bit)\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n - 0 - 1 - - - 0 - Watchdog Timer Clock Disabled - #0 - - - 1 - Watchdog Timer Clock Enabled - #1 - - - read-write - - - TMR0_EN - Timer0 Clock Enable\n - 2 - 1 - - - 0 - Timer0 clock Disabled - #0 - - - 1 - Timer0 clock Enabled - #1 - - - read-write - - - TMR1_EN - Timer1 Clock Enable\n - 3 - 1 - - - 0 - Timer1 clock Disabled - #0 - - - 1 - Timer1 clock Enabled - #1 - - - read-write - - - TMR2_EN - Timer2 Clock Enable\n - 4 - 1 - - - 0 - Timer2 clock Disabled - #0 - - - 1 - Timer2 clock Enabled - #1 - - - read-write - - - TMR3_EN - Timer3 Clock Enable\n - 5 - 1 - - - 0 - Timer3 clock Disabled - #0 - - - 1 - Timer3 clock Enabled - #1 - - - read-write - - - FDIV_EN - Frequency Divider Output Clock Enable\n - 6 - 1 - - - 0 - FDIV clock Disabled - #0 - - - 1 - FDIV clock Enabled - #1 - - - read-write - - - I2C0_EN - I2C0 Clock Enable\n - 8 - 1 - - - 0 - I2C0 clock Disabled - #0 - - - 1 - I2C0 clock Enabled - #1 - - - read-write - - - I2C1_EN - I2C1 Clock Enable\n - 9 - 1 - - - 0 - I2C1 clock Disabled - #0 - - - 1 - I2C1 clock Enabled - #1 - - - read-write - - - SPI0_EN - SPI0 Clock Enable\n - 12 - 1 - - - 0 - SPI0 clock Disabled - #0 - - - 1 - SPI0 clock Enabled - #1 - - - read-write - - - SPI1_EN - SPI1 Clock Enable\n - 13 - 1 - - - 0 - SPI1 clock Disabled - #0 - - - 1 - SPI1 clock Enabled - #1 - - - read-write - - - SPI2_EN - SPI2 Clock Enable\n - 14 - 1 - - - 0 - SPI2 clock Disabled - #0 - - - 1 - SPI2 clock Enabled - #1 - - - read-write - - - UART0_EN - UART0 Clock Enable\n - 16 - 1 - - - 0 - UART0 clock Disabled - #0 - - - 1 - UART0 clock Enabled - #1 - - - read-write - - - UART1_EN - UART1 Clock Enable\n - 17 - 1 - - - 0 - UART1 clock Disabled - #0 - - - 1 - UART1 clock Enabled - #1 - - - read-write - - - PWM01_EN - PWM_01 Clock Enable\n - 20 - 1 - - - 0 - PWM01 clock Disabled - #0 - - - 1 - PWM01 clock Enabled - #1 - - - read-write - - - PWM23_EN - PWM_23 Clock Enable\n - 21 - 1 - - - 0 - PWM23 clock Disabled - #0 - - - 1 - PWM23 clock Enabled - #1 - - - read-write - - - USBD_EN - USB 2.0 FS Device Controller Clock Enable\n - 27 - 1 - - - 0 - USB clock Disabled - #0 - - - 1 - USB clock Enabled - #1 - - - read-write - - - ADC_EN - Analog-Digital-Converter (ADC) Clock Enable\n - 28 - 1 - - - 0 - ADC clock Disabled - #0 - - - 1 - ADC clock Enabled - #1 - - - read-write - - - I2S_EN - I2S Clock Enable\n - 29 - 1 - - - 0 - I2S Clock Disabled - #0 - - - 1 - I2S Clock Enabled - #1 - - - read-write - - - PS2_EN - PS/2 Clock Enable\n - 31 - 1 - - - 0 - PS/2 clock Disabled - #0 - - - 1 - PS/2 clock Enabled - #1 - - - read-write - - - - - CLKSTATUS - - CLKSTATUS - Clock status monitor Register - 0xC - read-write - 0x00000000 - 0xFFFFFF00 - - - XTL12M_STB - External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis is read only bit. - 0 - 1 - - - 0 - External 4~24 MHz high speed crystal clock is not stable or disabled - #0 - - - 1 - External 4~24 MHz high speed crystal clock is stable - #1 - - - read-write - - - PLL_STB - Internal PLL Clock Source Stable Flag\nThis is read only bit. - 2 - 1 - - - 0 - Internal PLL clock is not stable or disabled - #0 - - - 1 - Internal PLL clock is stable - #1 - - - read-write - - - OSC10K_STB - Internal 10 kHz Low Speed Oscillator Clock Source Stable Flag\nThis is read only bit. - 3 - 1 - - - 0 - Internal 10 kHz low speed oscillator clock is not stable or disabled - #0 - - - 1 - Internal 10 kHz low speed oscillator clock is stable - #1 - - - read-write - - - OSC22M_STB - Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis is read only bit - 4 - 1 - - - 0 - Internal 22.1184 MHz high speed oscillator clock is not stable or disabled - #0 - - - 1 - Internal 22.1184 MHz high speed oscillator clock is stable - #1 - - - read-write - - - CLK_SW_FAIL - Clock Switching Fail Flag (Write-protection Bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero. - 7 - 1 - - - 0 - Clock switching success - #0 - - - 1 - Clock switching failed - #1 - - - read-write - - - - - CLKSEL0 - - CLKSEL0 - Clock Source Select Control Register 0 - 0x10 - read-write - 0x00000030 - 0xFFFFFFF0 - - - HCLK_S - HCLK Clock Source Selection (Write-protection Bits)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n - 0 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 1 - Clock source from PLL clock/2 - #001 - - - 2 - Clock source from PLL clock - #010 - - - 3 - Clock source from internal 10 kHz low speed oscillator clock - #011 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - STCLK_S - Cortex_M0 SysTick Clock Source Selection (Write-protection Bits)\n - 3 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from external 4~24 MHz high speed crystal clock/2 - #010 - - - 3 - Clock source from HCLK/2 - #011 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock/2 - #111 - - - read-write - - - - - CLKSEL1 - - CLKSEL1 - Clock Source Select Control Register 1 - 0x14 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - WDT_S - Watchdog Timer Clock Source Selection (Write-protection Bits)\nThese bits are protected bits and programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n - 0 - 2 - - - 2 - Clock source from HCLK/2048 clock - #10 - - - 3 - Clock source from internal 10 kHz low speed oscillator clock - #11 - - - read-write - - - ADC_S - ADC Clock Source Selection\n - 2 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Clock source from PLL clock - #01 - - - 2 - Clock source from HCLK - #10 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - SPI0_S - SPI0 Clock Source Selection\n - 4 - 1 - - - 0 - Clock source from PLL clock - #0 - - - 1 - Clock source from HCLK - #1 - - - read-write - - - SPI1_S - SPI1 Clock Source Selection\n - 5 - 1 - - - 0 - Clock source from PLL clock - #0 - - - 1 - Clock source from HCLK - #1 - - - read-write - - - SPI2_S - SPI2 Clock Source Selection\n - 6 - 1 - - - 0 - Clock source from PLL clock - #0 - - - 1 - Clock source from HCLK - #1 - - - read-write - - - TMR0_S - TIMER0 Clock Source Selection\n - 8 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Clock source from external clock source TM0 - #011 - - - 4 - Clock source from internal 10 kHz low speed oscillator clock - #100 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - TMR1_S - TIMER1 Clock Source Selection\n - 12 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Clock source from external clock source TM1 - #011 - - - 4 - Clock source from internal 10 kHz low speed oscillator clock - #100 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - TMR2_S - TIMER2 Clock Source Selection\n - 16 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Clock source from external clock source TM2 - #011 - - - 4 - Clock source from internal 10 kHz low speed oscillator clock - #100 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - TMR3_S - TIMER3 Clock Source Selection\n - 20 - 3 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #000 - - - 2 - Clock source from HCLK - #010 - - - 3 - Reserved - #011 - - - 4 - Clock source from internal 10 kHz low speed oscillator clock - #100 - - - 7 - Clock source from internal 22.1184 MHz high speed oscillator clock - #111 - - - read-write - - - UART_S - UART Clock Source Selection\n - 24 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Clock source from PLL clock - #01 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - PWM01_S - PWM0 and PWM1 Clock Source Select Bit [1:0]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n - 28 - 2 - read-write - - - PWM23_S - PWM2 and PWM3 Clock Source Select Bit [1:0]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].\n - 30 - 2 - read-write - - - - - CLKDIV - - CLKDIV - Clock Divider Number Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - HCLK_N - HCLK Clock Divide Number from HCLK Clock Source\n - 0 - 4 - read-write - - - USB_N - USB Clock Divide Number from PLL Clock\n - 4 - 4 - read-write - - - UART_N - UART Clock Divide Number from UART Clock Source\n - 8 - 4 - read-write - - - ADC_N - ADC Clock Divide Number from ADC Clock Source\n - 16 - 8 - read-write - - - - - CLKSEL2 - - CLKSEL2 - Clock Source Select Control Register 2 - 0x1C - read-write - 0x000000FF - 0xFFFFFFFF - - - I2S_S - I2S Clock Source Selection\n - 0 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Clock source from PLL clock - #01 - - - 2 - Clock source from HCLK - #10 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - FRQDIV_S - Clock Divider Clock Source Selection\n - 2 - 2 - - - 0 - Clock source from external 4~24 MHz high speed crystal clock - #00 - - - 1 - Reserved - #01 - - - 2 - Clock source from HCLK - #10 - - - 3 - Clock source from internal 22.1184 MHz high speed oscillator clock - #11 - - - read-write - - - PWM01_S - PWM0 and PWM1 Clock Source Select Bit [2]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n - 8 - 1 - read-write - - - PWM23_S - PWM2 and PWM3 Clock Source Select Bit [2]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].\n - 9 - 1 - read-write - - - WWDT_S - Windowed-Watchdog Timer Clock Source Selection (Write-protection Bits)\n - 16 - 2 - - - 2 - Clock source from HCLK/2048 clock - #10 - - - 3 - Clock source from internal 10 kHz low speed oscillator clock - #11 - - - read-write - - - - - PLLCON - - PLLCON - PLL Control Register - 0x20 - read-write - 0x0005C22E - 0xFFFFFFFF - - - FB_DV - PLL Feedback Divider Control Pins\nRefer to the formulas below the table. - 0 - 9 - read-write - - - IN_DV - PLL Input Divider Control Pins\nRefer to the formulas below the table. - 9 - 5 - read-write - - - OUT_DV - PLL Output Divider Control Pins\nRefer to the formulas below the table. - 14 - 2 - read-write - - - PD - Power-down Mode\nIf the PWR_DOWN_EN bit set to 1 in PWRCON register, the PLL will also enter Power-down mode.\n - 16 - 1 - - - 0 - PLL is in Normal mode - #0 - - - 1 - PLL is in Power-down mode (default) - #1 - - - read-write - - - BP - PLL Bypass Control\n - 17 - 1 - - - 0 - PLL is in Normal mode (default) - #0 - - - 1 - PLL clock output is the same as clock input (XTALin) - #1 - - - read-write - - - OE - PLL OE (FOUT Enable) Pin Control\n - 18 - 1 - - - 0 - PLL FOUT Enabled - #0 - - - 1 - PLL FOUT is fixed low - #1 - - - read-write - - - PLL_SRC - PLL Source Clock Selection\n - 19 - 1 - - - 0 - PLL source clock from external 4~24 MHz high speed crystal - #0 - - - 1 - PLL source clock from internal 22.1184 MHz high speed oscillator - #1 - - - read-write - - - - - FRQDIV - - FRQDIV - Frequency Divider Control Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - FSEL - Divider Output Frequency Select Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]. - 0 - 4 - read-write - - - DIVIDER_EN - Frequency Divider Enable Bit\n - 4 - 1 - - - 0 - Frequency Divider Disabled - #0 - - - 1 - Frequency Divider Enabled - #1 - - - read-write - - - - - APBDIV - - APBDIV - APB Divider Control Register - 0x2C - read-write - 0x00000000 - 0xFFFFFFFF - - - APBDIV - APB Divider Enable Bit\n - 0 - 1 - read-write - - - - - - - FMC - FMC Register Map - FMC - 0x5000C000 - - - 0x0 - 0x1C - registers - - - - ISPCON - - ISPCON - ISP Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPEN - ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n - 0 - 1 - - - 0 - ISP function Disabled - #0 - - - 1 - ISP function Enabled - #1 - - - read-write - - - BS - Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n - 1 - 1 - - - 0 - Boot from APROM - #0 - - - 1 - Boot from LDROM - #1 - - - read-write - - - APUEN - APROM Update Enable (Write-protection Bit)\n - 3 - 1 - - - 0 - APROM cannot be updated when the chip runs in APROM - #0 - - - 1 - APROM can be updated when the chip runs in APROM - #1 - - - read-write - - - CFGUEN - Enable Config-bits Update by ISP (Write-protection Bit)\n - 4 - 1 - - - 0 - ISP Disabled to update config-bits - #0 - - - 1 - ISP Enabled to update config-bits - #1 - - - read-write - - - LDUEN - LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.\n - 5 - 1 - - - 0 - LDROM cannot be updated - #0 - - - 1 - LDROM can be updated - #1 - - - read-write - - - ISPFF - ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear. - 6 - 1 - read-write - - - - - ISPADR - - ISPADR - ISP Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPADR - ISP Address\nThe NuMicro( NUC123 Series is equipped with an embedded flash, and it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. - 0 - 32 - read-write - - - - - ISPDAT - - ISPDAT - ISP Data Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPDAT - ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. - 0 - 32 - read-write - - - - - ISPCMD - - ISPCMD - ISP Command Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPCMD - ISP Command\n - 0 - 6 - read-write - - - - - ISPTRG - - ISPTRG - ISP Trigger Control Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISPGO - ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n - 0 - 1 - - - 0 - ISP operation is finished - #0 - - - 1 - ISP is progressed - #1 - - - read-write - - - - - DFBADR - - DFBADR - Data Flash Start Address - 0x14 - read-only - 0x00000000 - 0x00000000 - - - DFBADR - Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nWhen DFVSEN is set to 0, the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is loaded from Config1.\nWhen DFVSEN is set to 1, the data flash size is fixed as 4K and the start address can be read from this register is fixed at 0x0001_F000. - 0 - 32 - read-only - - - - - FATCON - - FATCON - Flash Access Time Control Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - LFOM - Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n - 4 - 1 - - - 0 - Low Frequency Optimization mode Disabled - #0 - - - 1 - Low Frequency Optimization mode Enabled - #1 - - - read-write - - - MFOM - Middle Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 50 MHz, chip can work more efficiently by setting this bit to 1\n - 6 - 1 - - - 0 - Middle Frequency Optimization mode Disabled - #0 - - - 1 - Middle Frequency Optimization mode Enabled - #1 - - - read-write - - - - - - - USB - USB Register Map - USB - 0x40060000 - - - 0x0 - 0x1C - registers - - - 0x90 - 0x4 - registers - - - 0xA4 - 0x4 - registers - - - 0x500 - 0x80 - registers - - - - USB_INTEN - - USB_INTEN - USB Interrupt Enable Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUS_IE - Bus Event Interrupt Enable\n - 0 - 1 - - - 0 - BUS event interrupt Disabled - #0 - - - 1 - BUS event interrupt Enabled - #1 - - - read-write - - - USB_IE - USB Event Interrupt Enable\n - 1 - 1 - - - 0 - USB event interrupt Disabled - #0 - - - 1 - USB event interrupt Enabled - #1 - - - read-write - - - FLDET_IE - Floating Detected Interrupt Enable\n - 2 - 1 - - - 0 - Floating detect Interrupt Disabled - #0 - - - 1 - Floating detect Interrupt Enabled - #1 - - - read-write - - - WAKEUP_IE - USB Wake-up Interrupt Enable\n - 3 - 1 - - - 0 - Wake-up Interrupt Disabled - #0 - - - 1 - Wake-up Interrupt Enabled - #1 - - - read-write - - - WAKEUP_EN - Wake-up Function Enable\n - 8 - 1 - - - 0 - USB wake-up function Disabled - #0 - - - 1 - USB wake-up function Enabled - #1 - - - read-write - - - INNAK_EN - Active NAK Function and its Status in IN Token\n - 15 - 1 - - - 0 - NAK status wasn't updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds NAK after receiving IN token - #0 - - - 1 - NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enables the interrupt event when the device responds NAK after receiving IN token - #1 - - - read-write - - - - - USB_INTSTS - - USB_INTSTS - USB Interrupt Event Status Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUS_STS - BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n - 0 - 1 - - - 0 - No BUS event occurred - #0 - - - 1 - Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USB_INTSTS[0] - #1 - - - read-write - - - USB_STS - USB event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n - 1 - 1 - - - 0 - No USB event occurred - #0 - - - 1 - USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31]) - #1 - - - read-write - - - FLDET_STS - Floating Detected Interrupt Status\n - 2 - 1 - - - 0 - There is not attached/detached event in the USB - #0 - - - 1 - There is attached/detached event in the USB bus and it is cleared by writing 1 to USB_INTSTS[2] - #1 - - - read-write - - - WAKEUP_STS - Wake-up Interrupt Status\n - 3 - 1 - - - 0 - No Wake-up event occurred - #0 - - - 1 - Wake-up event occurred, cleared by writing 1 to USB_INTSTS[3] - #1 - - - read-write - - - EPEVT0 - Endpoint 0's USB Event Status\n - 16 - 1 - - - 0 - No event occurred on Endpoint 0 - #0 - - - 1 - USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[16] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT1 - Endpoint 1's USB Event Status\n - 17 - 1 - - - 0 - No event occurred on Endpoint 1 - #0 - - - 1 - USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[17] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT2 - Endpoint 2's USB Event Status\n - 18 - 1 - - - 0 - No event occurred on Endpoint 2 - #0 - - - 1 - USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[18] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT3 - Endpoint 3's USB Event Status\n - 19 - 1 - - - 0 - No event occurred on Endpoint 3 - #0 - - - 1 - USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[19] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT4 - Endpoint 4's USB Event Status\n - 20 - 1 - - - 0 - No event occurred on Endpoint 4 - #0 - - - 1 - USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[20] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT5 - Endpoint 5's USB Event Status\n - 21 - 1 - - - 0 - No event occurred on Endpoint 5 - #0 - - - 1 - USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[21] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT6 - Endpoint 6's USB Event Status\n - 22 - 1 - - - 0 - No event occurred on Endpoint 6 - #0 - - - 1 - USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[22] or USB_INTSTS[1] - #1 - - - read-write - - - EPEVT7 - Endpoint 7's USB Event Status\n - 23 - 1 - - - 0 - No event occurred in endpoint 7 - #0 - - - 1 - USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[23] or USB_INTSTS[1] - #1 - - - read-write - - - SETUP - Setup Event Status\n - 31 - 1 - - - 0 - No Setup event - #0 - - - 1 - Setup event occurred, and cleared by writing 1 to USB_INTSTS[31] - #1 - - - read-write - - - - - USB_FADDR - - USB_FADDR - USB Device Function Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - FADDR - USB device's Function Address - 0 - 7 - read-write - - - - - USB_EPSTS - - USB_EPSTS - USB Endpoint Status Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - OVERRUN - Overrun\nIt indicates that the received data is over the maximum payload number or not.\n - 7 - 1 - - - 0 - No overrun - #0 - - - 1 - Out data is more than the Max Payload in MXPLD register or the Setup data is more than 8 Bytes - #1 - - - read-only - - - EPSTS0 - Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 8 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS1 - Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 11 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS2 - Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 14 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS3 - Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 17 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS4 - Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 20 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS5 - Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 23 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS6 - Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 26 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - EPSTS7 - Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n - 29 - 3 - - - 0 - In ACK - #000 - - - 1 - In NAK - #001 - - - 2 - Out Packet Data0 ACK - #010 - - - 3 - Setup ACK - #011 - - - 6 - Out Packet Data1 ACK - #110 - - - 7 - Isochronous transfer end - #111 - - - read-only - - - - - USB_ATTR - - USB_ATTR - USB Bus Status and Attribution Register - 0x10 - read-write - 0x00000040 - 0xFFFFFFFF - - - USBRST - USB Reset Status\nIt is a read only bit. - 0 - 1 - - - 0 - No bus reset - #0 - - - 1 - Bus reset when SE0 (single-ended 0) more than 2.5 us - #1 - - - read-write - - - SUSPEND - Suspend Status\nIt is a read only bit. - 1 - 1 - - - 0 - No bus suspend - #0 - - - 1 - Bus idle more than 3ms, either cable is plugged off or host is sleeping - #1 - - - read-write - - - RESUME - Resume Status\nIt is a read only bit. - 2 - 1 - - - 0 - No bus resume - #0 - - - 1 - Resume from suspend - #1 - - - read-write - - - TIME_OUT - Time Out Status\nIt is a read only bit. - 3 - 1 - - - 0 - No time-out - #0 - - - 1 - No Bus response more than 18 bits time - #1 - - - read-write - - - PHY_EN - PHY Transceiver Function Enable\n - 4 - 1 - - - 0 - PHY transceiver function Disabled - #0 - - - 1 - PHY transceiver function Enabled - #1 - - - read-write - - - RWAKEUP - Remote Wake-up\n - 5 - 1 - - - 0 - Release the USB bus from K state - #0 - - - 1 - Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up - #1 - - - read-write - - - USB_EN - USB Controller Enable\n - 7 - 1 - - - 0 - USB Controller Disabled - #0 - - - 1 - USB Controller Enabled - #1 - - - read-write - - - DPPU_EN - Pull-up resistor on USB_DP enable\n - 8 - 1 - - - 0 - the pull-up resistor in USB_DP bus Disabled - #0 - - - 1 - Pull-up resistor in USB_DP bus Enabled - #1 - - - read-write - - - PWRDN - Power-down PHY Transceiver, Low Active\n - 9 - 1 - - - 0 - Power-down related circuit of PHY transceiver - #0 - - - 1 - Turn-on related circuit of PHY transceiver - #1 - - - read-write - - - BYTEM - CPU access USB SRAM Size Mode Selection\n - 10 - 1 - - - 0 - Word Mode: The size of the transfer from CPU to USB SRAM can be Word only - #0 - - - 1 - Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only - #1 - - - read-write - - - - - USB_FLDET - - USB_FLDET - USB Floating Detected Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - FLDET - Device Floating Detected\n - 0 - 1 - - - 0 - Controller isn't attached to the USB host - #0 - - - 1 - Controller is attached to the BUS - #1 - - - read-only - - - - - USB_BUFSEG - - USB_BUFSEG - Setup Token Buffer Segmentation Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUFSEG - It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only. - 3 - 6 - read-write - - - - - USB_DRVSE0 - - USB_DRVSE0 - USB Drive SE0 Control Register - 0x90 - read-write - 0x00000001 - 0xFFFFFFFF - - - DRVSE0 - Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n - 0 - 1 - - - 0 - None - #0 - - - 1 - Force USB PHY transceiver to drive SE0 - #1 - - - read-write - - - - - USB_PDMA - - USB_PDMA - USB PDMA Control Register - 0xA4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_RW - PDMA_RW\n - 0 - 1 - - - 0 - The PDMA will read data from memory to USB buffer - #0 - - - 1 - The PDMA will read data from USB buffer to memory - #1 - - - read-write - - - PDMA_EN - PDMA Function Enable\nThis bit will be automatically cleared after PDMA transfer done. - 1 - 1 - - - 0 - The PDMA function is not active - #0 - - - 1 - The PDMA function in USB is active - #1 - - - read-write - - - - - USB_BUFSEG0 - - USB_BUFSEG0 - Endpoint 0 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x500 - read-write - 0x00000000 - 0xFFFFFFFF - - - BUFSEGx - It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description. - 3 - 6 - read-write - - - - - USB_MXPLD0 - - USB_MXPLD0 - Endpoint 0 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x504 - read-write - 0x00000000 - 0xFFFFFFFF - - - MXPLD - Maximal Payload\nIt is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It is also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD indicates the data length be transmitted to host\nFor OUT token, the value of MXPLD indicates the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. - 0 - 9 - read-write - - - - - USB_CFG0 - - USB_CFG0 - Endpoint 0 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x508 - read-write - 0x00000000 - 0xFFFFFFFF - - - EP_NUM - Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint. - 0 - 4 - read-write - - - ISOCH - Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n - 4 - 1 - - - 0 - No Isochronous endpoint - #0 - - - 1 - Isochronous endpoint - #1 - - - read-write - - - STATE - Endpoint STATE\n - 5 - 2 - - - 0 - Endpoint Disabled - #00 - - - 1 - Out endpoint - #01 - - - 2 - IN endpoint - #10 - - - 3 - Undefined - #11 - - - read-write - - - DSQ_SYNC - Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit. - 7 - 1 - - - 0 - DATA0 PID - #0 - - - 1 - DATA1 PID - #1 - - - read-write - - - CSTALL - Clear STALL Response\n - 9 - 1 - - - 0 - Device Disabled to clear the STALL handshake in the setup stage - #0 - - - 1 - Clear the device to respond STALL handshake in the setup stage - #1 - - - read-write - - - - - USB_CFGP0 - - USB_CFGP0 - Endpoint 0 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x50C - read-write - 0x00000000 - 0xFFFFFFFF - - - CLRRDY - Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, user can set this bit to 1 to turn it off and it is automatically cleared to 0.\nFor IN token, writing '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, writing '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is written 1 only and is always 0 when it was read back. - 0 - 1 - read-write - - - SSTALL - Set STALL\n - 1 - 1 - - - 0 - Device Disabled to respond STALL - #0 - - - 1 - Set the device to respond STALL automatically - #1 - - - read-write - - - - - USB_BUFSEG1 - USB_BUFSEG1 - Endpoint 1 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x510 - - - USB_MXPLD1 - USB_MXPLD1 - Endpoint 1 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x514 - - - USB_CFG1 - USB_CFG1 - Endpoint 1 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x518 - - - USB_CFGP1 - USB_CFGP1 - Endpoint 1 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x51C - - - USB_BUFSEG2 - USB_BUFSEG2 - Endpoint 2 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x520 - - - USB_MXPLD2 - USB_MXPLD2 - Endpoint 2 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x524 - - - USB_CFG2 - USB_CFG2 - Endpoint 2 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x528 - - - USB_CFGP2 - USB_CFGP2 - Endpoint 2 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x52C - - - USB_BUFSEG3 - USB_BUFSEG3 - Endpoint 3 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x530 - - - USB_MXPLD3 - USB_MXPLD3 - Endpoint 3 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x534 - - - USB_CFG3 - USB_CFG3 - Endpoint 3 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x538 - - - USB_CFGP3 - USB_CFGP3 - Endpoint 3 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x53C - - - USB_BUFSEG4 - USB_BUFSEG4 - Endpoint 4 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x540 - - - USB_MXPLD4 - USB_MXPLD4 - Endpoint 4 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x544 - - - USB_CFG4 - USB_CFG4 - Endpoint 4 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x548 - - - USB_CFGP4 - USB_CFGP4 - Endpoint 4 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x54C - - - USB_BUFSEG5 - USB_BUFSEG5 - Endpoint 5 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x550 - - - USB_MXPLD5 - USB_MXPLD5 - Endpoint 5 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x554 - - - USB_CFG5 - USB_CFG5 - Endpoint 5 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x558 - - - USB_CFGP5 - USB_CFGP5 - Endpoint 5 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x55C - - - USB_BUFSEG6 - USB_BUFSEG6 - Endpoint 6 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x560 - - - USB_MXPLD6 - USB_MXPLD6 - Endpoint 6 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x564 - - - USB_CFG6 - USB_CFG6 - Endpoint 6 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x568 - - - USB_CFGP6 - USB_CFGP6 - Endpoint 6 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x56C - - - USB_BUFSEG7 - USB_BUFSEG7 - Endpoint 7 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. - 0x570 - - - USB_MXPLD7 - USB_MXPLD7 - Endpoint 7 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. - 0x574 - - - USB_CFG7 - USB_CFG7 - Endpoint 7 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. - 0x578 - - - USB_CFGP7 - USB_CFGP7 - Endpoint 7 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. - 0x57C - - - - - GP - GP Register Map - GP - 0x50004000 - - - 0x0 - 0x24 - registers - - - 0x40 - 0x24 - registers - - - 0x80 - 0x24 - registers - - - 0xC0 - 0x24 - registers - - - 0x140 - 0x24 - registers - - - 0x180 - 0x4 - registers - - - 0x228 - 0x90 - registers - - - 0x2C0 - 0x30 - registers - - - 0x340 - 0x10 - registers - - - - GPIOA_PMD - - GPIOA_PMD - GPIO Port A Pin I/O Mode Control - 0x0 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD11 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD12 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD13 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD14 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD15 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOA_OFFD - - GPIOA_OFFD - GPIO Port A Pin OFF Digital Enable - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD11 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD12 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD13 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD14 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD15 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOA_DOUT - - GPIOA_DOUT - GPIO Port A Data Output Value - 0x8 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT11 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT12 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT13 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT14 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT15 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOA_DMASK - - GPIOA_DMASK - GPIO Port A Data Output Write Mask - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK11 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK12 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK13 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK14 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK15 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOA_PIN - - GPIOA_PIN - GPIO Port A Pin Value - 0x10 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN11 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - read-only - - - PIN12 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - read-only - - - PIN13 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - read-only - - - PIN14 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - read-only - - - PIN15 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - read-only - - - - - GPIOA_DBEN - - GPIOA_DBEN - GPIO Port A De-bounce Enable - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN11 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN12 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN13 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN14 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN15 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOA_IMD - - GPIOA_IMD - GPIO Port A Interrupt Mode Control - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD11 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD12 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD13 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD14 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD15 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOA_IEN - - GPIOA_IEN - GPIO Port A Interrupt Enable - 0x1C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOA_ISRC - - GPIOA_ISRC - GPIO Port A Interrupt Source Flag - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC11 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC12 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC13 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC14 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC15 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOB_PMD - - GPIOB_PMD - GPIO Port B Pin I/O Mode Control - 0x40 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD4 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD5 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD6 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD7 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD8 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD9 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD12 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD13 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD14 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD15 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOB_OFFD - - GPIOB_OFFD - GPIO Port B Pin OFF Digital Enable - 0x44 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD4 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD5 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD6 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD7 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 23 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD8 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD9 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD12 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD13 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD14 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD15 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOB_DOUT - - GPIOB_DOUT - GPIO Port B Data Output Value - 0x48 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT4 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT5 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT6 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT7 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT8 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT9 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT12 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT13 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT14 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT15 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOB_DMASK - - GPIOB_DMASK - GPIO Port B Data Output Write Mask - 0x4C - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK4 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK5 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK6 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK7 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK8 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK9 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK12 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK13 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK14 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK15 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOB_PIN - - GPIOB_PIN - GPIO Port B Pin Value - 0x50 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - PIN4 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - read-only - - - PIN5 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - read-only - - - PIN6 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - read-only - - - PIN7 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - read-only - - - PIN8 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - read-only - - - PIN9 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - read-only - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN12 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - read-only - - - PIN13 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - read-only - - - PIN14 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - read-only - - - PIN15 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - read-only - - - - - GPIOB_DBEN - - GPIOB_DBEN - GPIO Port B De-bounce Enable - 0x54 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN4 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN5 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN6 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN7 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN8 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN9 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN12 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN13 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN14 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN15 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOB_IMD - - GPIOB_IMD - GPIO Port B Interrupt Mode Control - 0x58 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD4 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD5 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD6 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD7 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD8 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD9 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD12 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD13 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD14 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD15 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOB_IEN - - GPIOB_IEN - GPIO Port B Interrupt Enable - 0x5C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN6 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN7 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN6 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 22 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN7 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 23 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN14 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 30 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN15 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 31 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOB_ISRC - - GPIOB_ISRC - GPIO Port B Interrupt Source Flag - 0x60 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC4 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC5 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC6 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 6 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC7 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 7 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC8 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC9 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC12 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC13 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC14 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 14 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC15 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 15 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOC_PMD - - GPIOC_PMD - GPIO Port C Pin I/O Mode Control - 0x80 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD4 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD5 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD8 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD9 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD11 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD12 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD13 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOC_OFFD - - GPIOC_OFFD - GPIO Port C Pin OFF Digital Enable - 0x84 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD4 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD5 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD8 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD9 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD11 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD12 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD13 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOC_DOUT - - GPIOC_DOUT - GPIO Port C Data Output Value - 0x88 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT4 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT5 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT8 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT9 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT11 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT12 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT13 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOC_DMASK - - GPIOC_DMASK - GPIO Port C Data Output Write Mask - 0x8C - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK4 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK5 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK8 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK9 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK11 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK12 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK13 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOC_PIN - - GPIOC_PIN - GPIO Port C Pin Value - 0x90 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - PIN4 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - read-only - - - PIN5 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - read-only - - - PIN8 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - read-only - - - PIN9 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - read-only - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN11 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - read-only - - - PIN12 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - read-only - - - PIN13 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - read-only - - - - - GPIOC_DBEN - - GPIOC_DBEN - GPIO Port C De-bounce Enable - 0x94 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN4 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN5 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN8 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN9 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN11 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN12 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN13 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOC_IMD - - GPIOC_IMD - GPIO Port C Interrupt Mode Control - 0x98 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD4 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD5 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD8 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD9 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD11 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD12 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD13 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOC_IEN - - GPIOC_IEN - GPIO Port C Interrupt Enable - 0x9C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN12 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 28 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN13 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 29 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOC_ISRC - - GPIOC_ISRC - GPIO Port C Interrupt Source Flag - 0xA0 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC4 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC5 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC8 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC9 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC11 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC12 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 12 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC13 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 13 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOD_PMD - - GPIOD_PMD - GPIO Port D Pin I/O Mode Control - 0xC0 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD4 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD5 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD8 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD9 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD10 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD11 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 22 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOD_OFFD - - GPIOD_OFFD - GPIO Port D Pin OFF Digital Enable - 0xC4 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD4 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD5 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD8 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD9 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD10 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD11 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOD_DOUT - - GPIOD_DOUT - GPIO Port D Data Output Value - 0xC8 - read-write - 0x0000FFFF - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT4 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT5 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT8 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT9 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT10 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT11 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOD_DMASK - - GPIOD_DMASK - GPIO Port D Data Output Write Mask - 0xCC - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK4 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK5 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK8 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK9 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK10 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK11 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOD_PIN - - GPIOD_PIN - GPIO Port D Pin Value - 0xD0 - read-only - 0x00000000 - 0xFFFF0000 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - PIN4 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - read-only - - - PIN5 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - read-only - - - PIN8 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - read-only - - - PIN9 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - read-only - - - PIN10 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - read-only - - - PIN11 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - read-only - - - - - GPIOD_DBEN - - GPIOD_DBEN - GPIO Port D De-bounce Enable - 0xD4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN4 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN5 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN8 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN9 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN10 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN11 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOD_IMD - - GPIOD_IMD - GPIO Port D Interrupt Mode Control - 0xD8 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD4 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD5 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD8 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD9 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD10 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD11 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOD_IEN - - GPIOD_IEN - GPIO Port D Interrupt Enable - 0xDC - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN4 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 20 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN5 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 21 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN8 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 24 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN9 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 25 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN10 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 26 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN11 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 27 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOD_ISRC - - GPIOD_ISRC - GPIO Port D Interrupt Source Flag - 0xE0 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC4 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 4 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC5 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 5 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC8 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 8 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC9 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 9 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC10 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 10 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC11 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 11 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - GPIOF_PMD - - GPIOF_PMD - GPIO Port F Pin I/O Mode Control - 0x140 - read-write - 0x000000FF - 0xFFFFFFFF - - - PMD0 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD1 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD2 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 4 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - PMD3 - GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 6 - 2 - - - 0 - GPIO port [n] pin is in INPUT mode - #00 - - - 1 - GPIO port [n] pin is in OUTPUT mode - #01 - - - 2 - GPIO port [n] pin is in Open-Drain mode - #10 - - - 3 - GPIO port [n] pin is in Quasi-bidirectional mode - #11 - - - read-write - - - - - GPIOF_OFFD - - GPIOF_OFFD - GPIO Port F Pin OFF Digital Enable - 0x144 - read-write - 0x00000000 - 0xFFFFFFFF - - - OFFD0 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD1 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD2 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - OFFD3 - GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - IO digital input path Enabled - #0 - - - 1 - IO digital input path Disabled (digital input tied to low) - #1 - - - read-write - - - - - GPIOF_DOUT - - GPIOF_DOUT - GPIO Port F Data Output Value - 0x148 - read-write - 0x0000000F - 0xFFFFFFFF - - - DOUT0 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT1 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT2 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - DOUT3 - GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode - #0 - - - 1 - GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode - #1 - - - read-write - - - - - GPIOF_DMASK - - GPIOF_DMASK - GPIO Port F Data Output Write Mask - 0x14C - read-write - 0x00000000 - 0xFFFFFFFF - - - DMASK0 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK1 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK2 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - DMASK3 - Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The corresponding GPIOx_DOUT[n] bit can be updated - #0 - - - 1 - The corresponding GPIOx_DOUT[n] bit is protected - #1 - - - read-write - - - - - GPIOF_PIN - - GPIOF_PIN - GPIO Port F Pin Value - 0x150 - read-only - 0x00000000 - 0xFFFFFFF0 - - - PIN0 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - read-only - - - PIN1 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - read-only - - - PIN2 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - read-only - - - PIN3 - Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - read-only - - - - - GPIOF_DBEN - - GPIOF_DBEN - GPIO Port F De-bounce Enable - 0x154 - read-write - 0x00000000 - 0xFFFFFFFF - - - DBEN0 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN1 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN2 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - DBEN3 - Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - The bit[n] de-bounce function is disabled - #0 - - - 1 - The bit[n] de-bounce function is enabled - #1 - - - read-write - - - - - GPIOF_IMD - - GPIOF_IMD - GPIO Port F Interrupt Mode Control - 0x158 - read-write - 0x00000000 - 0xFFFFFFFF - - - IMD0 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD1 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD2 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - IMD3 - Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - Edge trigger interrupt - #0 - - - 1 - Level trigger interrupt - #1 - - - read-write - - - - - GPIOF_IEN - - GPIOF_IEN - GPIO Port F Interrupt Enable - 0x15C - read-write - 0x00000000 - 0xFFFFFFFF - - - IF_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IF_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - PIN[n] state low-level or high-to-low change interrupt Disabled - #0 - - - 1 - PIN[n] state low-level or high-to-low change interrupt Enabled - #1 - - - read-write - - - IR_EN0 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 16 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN1 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 17 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN2 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 18 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - IR_EN3 - Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 19 - 1 - - - 0 - PIN[n] level-high or low-to-high interrupt Disabled - #0 - - - 1 - PIN[n] level-high or low-to-high interrupt Enabled - #1 - - - read-write - - - - - GPIOF_ISRC - - GPIOF_ISRC - GPIO Port F Interrupt Source Flag - 0x160 - read-write - 0x00000000 - 0xFFFFFFFF - - - ISRC0 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 0 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC1 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 1 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC2 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 2 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - ISRC3 - Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. - 3 - 1 - - - 0 - No interrupt at GPIOx[n].\nNo action - #0 - - - 1 - Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt - #1 - - - read-write - - - - - DBNCECON - - DBNCECON - De-bounce Cycle Control - 0x180 - read-write - 0x00000020 - 0xFFFFFFFF - - - DBCLKSEL - De-bounce sampling cycle selection\n - 0 - 4 - read-write - - - DBCLKSRC - De-bounce counter clock source select\n - 4 - 1 - - - 0 - De-bounce counter clock source is the HCLK - #0 - - - 1 - De-bounce counter clock source is the internal 10 kHz low speed oscillator - #1 - - - read-write - - - ICLK_ON - Interrupt clock On mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled\n - 5 - 1 - - - 0 - Clock Disabled if the GPIOA/B/C/D/F[n] interrupt is disabled - #0 - - - 1 - Interrupt generated circuit clock always Enabled - #1 - - - read-write - - - - - PA10_PDIO - - PA10_PDIO - GPIO PA.n Pin Data Input/Output - 0x228 - read-write - 0x00000000 - 0xFFFFFFF0 - - - GPIOxx_DOUT - GPIOxx I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\nRead this register to get IO pin status.\nFor example: Writing GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0] - 0 - 1 - - - 0 - Set the corresponding GPIO pin to low - #0 - - - 1 - Set the corresponding GPIO pin to high - #1 - - - read-write - - - - - PA11_PDIO - PA11_PDIO - GPIO PA.n Pin Data Input/Output - 0x22C - - - PA12_PDIO - PA12_PDIO - GPIO PA.n Pin Data Input/Output - 0x230 - - - PA13_PDIO - PA13_PDIO - GPIO PA.n Pin Data Input/Output - 0x234 - - - PA14_PDIO - PA14_PDIO - GPIO PA.n Pin Data Input/Output - 0x238 - - - PA15_PDIO - PA15_PDIO - GPIO PA.n Pin Data Input/Output - 0x23C - - - PB0_PDIO - PB0_PDIO - GPIO PB.n Pin Data Input/Output - 0x240 - - - PB1_PDIO - PB1_PDIO - GPIO PB.n Pin Data Input/Output - 0x244 - - - PB2_PDIO - PB2_PDIO - GPIO PB.n Pin Data Input/Output - 0x248 - - - PB3_PDIO - PB3_PDIO - GPIO PB.n Pin Data Input/Output - 0x24C - - - PB4_PDIO - PB4_PDIO - GPIO PB.n Pin Data Input/Output - 0x250 - - - PB5_PDIO - PB5_PDIO - GPIO PB.n Pin Data Input/Output - 0x254 - - - PB6_PDIO - PB6_PDIO - GPIO PB.n Pin Data Input/Output - 0x258 - - - PB7_PDIO - PB7_PDIO - GPIO PB.n Pin Data Input/Output - 0x25C - - - PB8_PDIO - PB8_PDIO - GPIO PB.n Pin Data Input/Output - 0x260 - - - PB9_PDIO - PB9_PDIO - GPIO PB.n Pin Data Input/Output - 0x264 - - - PB10_PDIO - PB10_PDIO - GPIO PB.n Pin Data Input/Output - 0x268 - - - PB11_PDIO - PB11_PDIO - GPIO PB.n Pin Data Input/Output - 0x26C - - - PB12_PDIO - PB12_PDIO - GPIO PB.n Pin Data Input/Output - 0x270 - - - PB13_PDIO - PB13_PDIO - GPIO PB.n Pin Data Input/Output - 0x274 - - - PB14_PDIO - PB14_PDIO - GPIO PB.n Pin Data Input/Output - 0x278 - - - PB15_PDIO - PB15_PDIO - GPIO PB.n Pin Data Input/Output - 0x27C - - - PC0_PDIO - PC0_PDIO - GPIO PC.n Pin Data Input/Output - 0x280 - - - PC1_PDIO - PC1_PDIO - GPIO PC.n Pin Data Input/Output - 0x284 - - - PC2_PDIO - PC2_PDIO - GPIO PC.n Pin Data Input/Output - 0x288 - - - PC3_PDIO - PC3_PDIO - GPIO PC.n Pin Data Input/Output - 0x28C - - - PC4_PDIO - PC4_PDIO - GPIO PC.n Pin Data Input/Output - 0x290 - - - PC5_PDIO - PC5_PDIO - GPIO PC.n Pin Data Input/Output - 0x294 - - - PC6_PDIO - PC6_PDIO - GPIO PC.n Pin Data Input/Output - 0x298 - - - PC7_PDIO - PC7_PDIO - GPIO PC.n Pin Data Input/Output - 0x29C - - - PC8_PDIO - PC8_PDIO - GPIO PC.n Pin Data Input/Output - 0x2A0 - - - PC9_PDIO - PC9_PDIO - GPIO PC.n Pin Data Input/Output - 0x2A4 - - - PC10_PDIO - PC10_PDIO - GPIO PC.n Pin Data Input/Output - 0x2A8 - - - PC11_PDIO - PC11_PDIO - GPIO PC.n Pin Data Input/Output - 0x2AC - - - PC12_PDIO - PC12_PDIO - GPIO PC.n Pin Data Input/Output - 0x2B0 - - - PC13_PDIO - PC13_PDIO - GPIO PC.n Pin Data Input/Output - 0x2B4 - - - PD0_PDIO - PD0_PDIO - GPIO PD.n Pin Data Input/Output - 0x2C0 - - - PD1_PDIO - PD1_PDIO - GPIO PD.n Pin Data Input/Output - 0x2C4 - - - PD2_PDIO - PD2_PDIO - GPIO PD.n Pin Data Input/Output - 0x2C8 - - - PD3_PDIO - PD3_PDIO - GPIO PD.n Pin Data Input/Output - 0x2CC - - - PD4_PDIO - PD4_PDIO - GPIO PD.n Pin Data Input/Output - 0x2D0 - - - PD5_PDIO - PD5_PDIO - GPIO PD.n Pin Data Input/Output - 0x2D4 - - - PD6_PDIO - PD6_PDIO - GPIO PD.n Pin Data Input/Output - 0x2D8 - - - PD7_PDIO - PD7_PDIO - GPIO PD.n Pin Data Input/Output - 0x2DC - - - PD8_PDIO - PD8_PDIO - GPIO PD.n Pin Data Input/Output - 0x2E0 - - - PD9_PDIO - PD9_PDIO - GPIO PD.n Pin Data Input/Output - 0x2E4 - - - PD10_PDIO - PD10_PDIO - GPIO PD.n Pin Data Input/Output - 0x2E8 - - - PD11_PDIO - PD11_PDIO - GPIO PD.n Pin Data Input/Output - 0x2EC - - - PF0_PDIO - PF0_PDIO - GPIO PF.n Pin Data Input/Output - 0x340 - - - PF1_PDIO - PF1_PDIO - GPIO PF.n Pin Data Input/Output - 0x344 - - - PF2_PDIO - PF2_PDIO - GPIO PF.n Pin Data Input/Output - 0x348 - - - PF3_PDIO - PF3_PDIO - GPIO PF.n Pin Data Input/Output - 0x34C - - - - - I2C0 - I2C Register Map - I2C - 0x40020000 - - - 0x0 - 0x34 - registers - - - 0x3C - 0x8 - registers - - - - I2CON - - I2CON - I2C Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - AA - Assert Acknowledge Control Bit\n - 2 - 1 - read-write - - - SI - I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. - 3 - 1 - read-write - - - STO - I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. - 4 - 1 - read-write - - - STA - I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. - 5 - 1 - read-write - - - ENS1 - I2C Controller Enable Bit\n - 6 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - EI - Enable Interrupt\n - 7 - 1 - - - 0 - I2C interrupt Disabled - #0 - - - 1 - I2C interrupt Enabled - #1 - - - read-write - - - - - I2CADDR0 - - I2CADDR0 - I2C Slave Address Register0 - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - GC - General Call Function\n - 0 - 1 - - - 0 - General Call function Disabled - #0 - - - 1 - General Call function Enabled - #1 - - - read-write - - - I2CADDR - I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched. - 1 - 7 - read-write - - - - - I2CDAT - - I2CDAT - I2C Data Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CDAT - I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. - 0 - 8 - read-write - - - - - I2CSTATUS - - I2CSTATUS - I2C Status Register - 0xC - read-only - 0x000000F8 - 0xFFFFFFFF - - - I2CSTATUS - I2C Status Register\nThe status register of I2C:\n - 0 - 8 - read-only - - - - - I2CLK - - I2CLK - I2C Clock Divided Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CLK - I2C clock divided Register\n - 0 - 8 - read-write - - - - - I2CTOC - - I2CTOC - I2C Time-Out Counter Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Time-Out Flag\n - 0 - 1 - - - 0 - Software can clear the flag - #0 - - - 1 - Time-out flag is set by H/W. It can interrupt CPU - #1 - - - read-write - - - DIV4 - Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times. - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - ENTI - Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared. - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - - - I2CADDR1 - I2CADDR1 - I2C Slave Address Register1 - 0x18 - - - I2CADDR2 - I2CADDR2 - I2C Slave Address Register2 - 0x1C - - - I2CADDR3 - I2CADDR3 - I2C Slave Address Register3 - 0x20 - - - I2CADM0 - - I2CADM0 - I2C Slave Address Mask Register0 - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CADM - I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register. - 1 - 7 - - - 0 - Mask Disabled (the received corresponding register bit should be exactly the same as address register.) - 0 - - - 1 - Mask Enabled (the received corresponding address bit is don't care.) - 1 - - - read-write - - - - - I2CADM1 - I2CADM1 - I2C Slave Address Mask Register1 - 0x28 - - - I2CADM2 - I2CADM2 - I2C Slave Address Mask Register2 - 0x2C - - - I2CADM3 - I2CADM3 - I2C Slave Address Mask Register3 - 0x30 - - - I2CWKUPCON - - I2CWKUPCON - I2C Wake-up Control Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - WKUPEN - I2C Wake-up Function Enable\n - 0 - 1 - - - 0 - I2C wake-up function Disabled - #0 - - - 1 - I2C wake-up function Enabled - #1 - - - read-write - - - - - I2CWKUPSTS - - I2CWKUPSTS - I2C Wake-up Status Register - 0x40 - read-only - 0x00000000 - 0xFFFFFFFF - - - WKUPIF - Wake-up Interrupt Flag\nSoftware can write one to clear this flag - 0 - 1 - - - 0 - Wake-up flag inactive - #0 - - - 1 - Wake-up flag active - #1 - - - read-only - - - - - - - I2C1 - I2C Register Map - I2C - 0x40120000 - - - 0x0 - 0x34 - registers - - - 0x3C - 0x8 - registers - - - - I2CON - - I2CON - I2C Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - AA - Assert Acknowledge Control Bit\n - 2 - 1 - read-write - - - SI - I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. - 3 - 1 - read-write - - - STO - I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. - 4 - 1 - read-write - - - STA - I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. - 5 - 1 - read-write - - - ENS1 - I2C Controller Enable Bit\n - 6 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - EI - Enable Interrupt\n - 7 - 1 - - - 0 - I2C interrupt Disabled - #0 - - - 1 - I2C interrupt Enabled - #1 - - - read-write - - - - - I2CADDR0 - - I2CADDR0 - I2C Slave Address Register0 - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - GC - General Call Function\n - 0 - 1 - - - 0 - General Call function Disabled - #0 - - - 1 - General Call function Enabled - #1 - - - read-write - - - I2CADDR - I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched. - 1 - 7 - read-write - - - - - I2CDAT - - I2CDAT - I2C Data Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CDAT - I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. - 0 - 8 - read-write - - - - - I2CSTATUS - - I2CSTATUS - I2C Status Register - 0xC - read-only - 0x000000F8 - 0xFFFFFFFF - - - I2CSTATUS - I2C Status Register\nThe status register of I2C:\n - 0 - 8 - read-only - - - - - I2CLK - - I2CLK - I2C Clock Divided Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CLK - I2C clock divided Register\n - 0 - 8 - read-write - - - - - I2CTOC - - I2CTOC - I2C Time-Out Counter Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Time-Out Flag\n - 0 - 1 - - - 0 - Software can clear the flag - #0 - - - 1 - Time-out flag is set by H/W. It can interrupt CPU - #1 - - - read-write - - - DIV4 - Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times. - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - ENTI - Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared. - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - - - I2CADDR1 - I2CADDR1 - I2C Slave Address Register1 - 0x18 - - - I2CADDR2 - I2CADDR2 - I2C Slave Address Register2 - 0x1C - - - I2CADDR3 - I2CADDR3 - I2C Slave Address Register3 - 0x20 - - - I2CADM0 - - I2CADM0 - I2C Slave Address Mask Register0 - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2CADM - I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register. - 1 - 7 - - - 0 - Mask Disabled (the received corresponding register bit should be exactly the same as address register.) - 0 - - - 1 - Mask Enabled (the received corresponding address bit is don't care.) - 1 - - - read-write - - - - - I2CADM1 - I2CADM1 - I2C Slave Address Mask Register1 - 0x28 - - - I2CADM2 - I2CADM2 - I2C Slave Address Mask Register2 - 0x2C - - - I2CADM3 - I2CADM3 - I2C Slave Address Mask Register3 - 0x30 - - - I2CWKUPCON - - I2CWKUPCON - I2C Wake-up Control Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - WKUPEN - I2C Wake-up Function Enable\n - 0 - 1 - - - 0 - I2C wake-up function Disabled - #0 - - - 1 - I2C wake-up function Enabled - #1 - - - read-write - - - - - I2CWKUPSTS - - I2CWKUPSTS - I2C Wake-up Status Register - 0x40 - read-only - 0x00000000 - 0xFFFFFFFF - - - WKUPIF - Wake-up Interrupt Flag\nSoftware can write one to clear this flag - 0 - 1 - - - 0 - Wake-up flag inactive - #0 - - - 1 - Wake-up flag active - #1 - - - read-only - - - - - - - PWMA - PWM Register Map - PWM - 0x40040000 - - - 0x0 - 0x48 - registers - - - 0x50 - 0x48 - registers - - - 0xC0 - 0x14 - registers - - - - PPR - - PPR - PWM Prescaler Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - CP01 - Clock Prescaler 0 (PWM-timer 0 / 1)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer.\n - 0 - 8 - read-write - - - CP23 - Clock Prescaler 2 (PWM Timer2 / 3)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer.\n - 8 - 8 - read-write - - - DZI01 - Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits. - 16 - 8 - read-write - - - DZI23 - Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits. - 24 - 8 - read-write - - - - - CSR - - CSR - PWM Clock Selector Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - CSR0 - PWM Timer 0 Clock Source Selection (PWM Timer 0)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) - 0 - 3 - read-write - - - CSR1 - PWM Timer 1 Clock Source Selection (PWM Timer 1)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) - 4 - 3 - read-write - - - CSR2 - PWM Timer 2 Clock Source Selection (PWM Timer 2)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) - 8 - 3 - read-write - - - CSR3 - PWM Timer 3 Clock Source Selection (PWM timer 3)\n - 12 - 3 - read-write - - - - - PCR - - PCR - PWM Control Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - CH0EN - PWM-Timer 0 Enable (PWM timer 0)\n - 0 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH0PINV - PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0)\n - 1 - 1 - - - 0 - PWM0 output polar inverse Disabled - #0 - - - 1 - PWM0 output polar inverse Enabled - #1 - - - read-write - - - CH0INV - PWM-Timer 0 Output Inverter Enable (PWM Timer 0)\n - 2 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH0MOD - PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be clear. - 3 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-reload mode - #1 - - - read-write - - - DZEN01 - Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair)\nNote: When dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A. - 4 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - DZEN23 - Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair)\nNote: When dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. - 5 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CH1EN - PWM-Timer 1 Enable (PWM Timer 1)\n - 8 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH1PINV - PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1)\n - 9 - 1 - - - 0 - PWM1 output polar inverse Disabled - #0 - - - 1 - PWM1 output polar inverse Enabled - #1 - - - read-write - - - CH1INV - PWM-Timer 1 Output Inverter Enable (PWM Timer 1)\n - 10 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH1MOD - PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be clear. - 11 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-load mode - #1 - - - read-write - - - CH2EN - PWM-Timer 2 Enable (PWM Timer 2)\n - 16 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH2PINV - PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2)\n - 17 - 1 - - - 0 - PWM2 output polar inverse Disabled - #0 - - - 1 - PWM2 output polar inverse Enabled - #1 - - - read-write - - - CH2INV - PWM-Timer 2 Output Inverter Enable (PWM Timer 2)\n - 18 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH2MOD - PWM-Timer 2 Auto-reload/One-Shot Mode (PWM Timer 2)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be clear. - 19 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-reload mode - #1 - - - read-write - - - CH3EN - PWM-Timer 3 Enable (PWM Timer 3)\n - 24 - 1 - - - 0 - Corresponding PWM-Timer Running Stopped - #0 - - - 1 - Corresponding PWM-Timer Start Run Enabled - #1 - - - read-write - - - CH3PINV - PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3)\n - 25 - 1 - - - 0 - PWM3 output polar inverse Disabled - #0 - - - 1 - PWM3 output polar inverse Enabled - #1 - - - read-write - - - CH3INV - PWM-Timer 3 Output Inverter Enable (PWM Timer 3)\n - 26 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled - #1 - - - read-write - - - CH3MOD - PWM-Timer 3 Auto-reload/One-Shot Mode (PWM Timer 3)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be clear. - 27 - 1 - - - 0 - One-shot mode - #0 - - - 1 - Auto-reload mode - #1 - - - read-write - - - PWMTYPE01 - PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair)\n - 30 - 1 - - - 0 - Edge-aligned type - #0 - - - 1 - Center-aligned type - #1 - - - read-write - - - PWMTYPE23 - PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair)\n - 31 - 1 - - - 0 - Edge-aligned type - #0 - - - 1 - Center-aligned type - #1 - - - read-write - - - - - CNR0 - - CNR0 - PWM Counter Register 0 - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - CNRx - PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in the next PWM cycle.\nNote: When PWM operating at center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high. - 0 - 16 - read-write - - - - - CMR0 - - CMR0 - PWM Comparator Register 0 - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - CMRx - PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in the next PWM cycle. - 0 - 16 - read-write - - - - - PDR0 - - PDR0 - PWM Data Register 0 - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDRx - PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter. - 0 - 16 - read-only - - - - - CNR1 - CNR1 - PWM Counter Register 1 - 0x18 - - - CMR1 - CMR1 - PWM Comparator Register 1 - 0x1C - - - PDR1 - PDR1 - PWM Data Registe 1 - 0x20 - - - CNR2 - CNR2 - PWM Counter Register 2 - 0x24 - - - CMR2 - CMR2 - PWM Comparator Register 2 - 0x28 - - - PDR2 - PDR2 - PWM Data Register 2 - 0x2C - - - CNR3 - CNR3 - PWM Counter Register 3 - 0x30 - - - CMR3 - CMR3 - PWM Comparator Register 3 - 0x34 - - - PDR3 - PDR3 - PWM Data Register 3 - 0x38 - - - PBCR - - PBCR - PWM backward compatible Register - 0x3C - read-write - 0x00000000 - 0xFFFFFFFF - - - - PIER - - PIER - PWM Interrupt Enable Register - 0x40 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWMIE0 - PWM Channel 0 Interrupt Enable\n - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMIE1 - PWM Channel 1 Interrupt Enable\n - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMIE2 - PWM Channel 2 Interrupt Enable\n - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMIE3 - PWM Channel 3 Interrupt Enable\n - 3 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE0 - PWM Channel 0 Duty Interrupt Enable\n - 8 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE1 - PWM Channel 1 Duty Interrupt Enable\n - 9 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE2 - PWM Channel 2 Duty Interrupt Enable\n - 10 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PWMDIE3 - PWM Channel 3 Duty Interrupt Enable\n - 11 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - INTTYPE01 - PWM01 Interrupt Type Selection Bit (PWM0 and PWM1 Pair)\nNote: This bit is effective when PWM in central align mode only. - 16 - 1 - - - 0 - PWMIFn will be set if PWM counter underflow - #0 - - - 1 - PWMIFn will be set if PWM counter matches CNRn register - #1 - - - read-write - - - INTTYPE23 - PWM12 Interrupt Type Selection Bit (PWM2 and PWM3 Pair)\nNote: This bit is effective when PWM in central align mode only. - 17 - 1 - - - 0 - PWMIFn will be set if PWM counter underflow - #0 - - - 1 - PWMIFn will be set if PWM counter matches CNRn register - #1 - - - read-write - - - - - PIIR - - PIIR - PWM Interrupt Indication Register - 0x44 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWMIF0 - PWM channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM0 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero - 0 - 1 - read-write - - - PWMIF1 - PWM channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM1 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero - 1 - 1 - read-write - - - PWMIF2 - PWM channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM2 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero - 2 - 1 - read-write - - - PWMIF3 - PWM channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero - 3 - 1 - read-write - - - PWMDIF0 - PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 8 - 1 - read-write - - - PWMDIF1 - PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 9 - 1 - read-write - - - PWMDIF2 - PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 10 - 1 - read-write - - - PWMDIF3 - PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working - 11 - 1 - read-write - - - - - CCR0 - - CCR0 - PWM Capture Control Register 0 - 0x50 - read-write - 0x00000000 - 0xFFFFFFFF - - - INV0 - Channel 0 Inverter Enable\n - 0 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE0 - Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has rising transition, capture issues an Interrupt. - 1 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE0 - Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has falling transition, capture issues an Interrupt. - 2 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH0EN - Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. - 3 - 1 - - - 0 - Capture function on PWM group channel 0 Disabled - #0 - - - 1 - Capture function on PWM group channel 0 Enabled - #1 - - - read-write - - - CAPIF0 - Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 4 - 1 - read-write - - - CRLRI0 - CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 6 - 1 - read-write - - - CFLRI0 - CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 7 - 1 - read-write - - - INV1 - Channel 1 Inverter Enable\n - 16 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE1 - Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, capture issues an Interrupt. - 17 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE1 - Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, capture issues an Interrupt. - 18 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH1EN - Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. - 19 - 1 - - - 0 - Capture function on PWM group channel 1 Disabled - #0 - - - 1 - Capture function on PWM group channel 1 Enabled - #1 - - - read-write - - - CAPIF1 - Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 20 - 1 - read-write - - - CRLRI1 - CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 22 - 1 - read-write - - - CFLRI1 - CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 23 - 1 - read-write - - - - - CCR2 - - CCR2 - PWM Capture Control Register 2 - 0x54 - read-write - 0x00000000 - 0xFFFFFFFF - - - INV2 - Channel 2 Inverter Enable\n - 0 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE2 - Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. - 1 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE2 - Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 2 has falling transition, capture issues an Interrupt. - 2 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH2EN - Channel 2 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. - 3 - 1 - - - 0 - Capture function on PWM group channel 2 Disabled - #0 - - - 1 - Capture function on PWM group channel 2 Enabled - #1 - - - read-write - - - CAPIF2 - Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 4 - 1 - read-write - - - CRLRI2 - CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 6 - 1 - read-write - - - CFLRI2 - CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 7 - 1 - read-write - - - INV3 - Channel 3 Inverter Enable\n - 16 - 1 - - - 0 - Inverter Disabled - #0 - - - 1 - Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer - #1 - - - read-write - - - CRL_IE3 - Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, capture issues an Interrupt. - 17 - 1 - - - 0 - Rising latch interrupt Disabled - #0 - - - 1 - Rising latch interrupt Enabled - #1 - - - read-write - - - CFL_IE3 - Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 3 has falling transition, capture issues an Interrupt. - 18 - 1 - - - 0 - Falling latch interrupt Disabled - #0 - - - 1 - Falling latch interrupt Enabled - #1 - - - read-write - - - CAPCH3EN - Channel 3 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. - 19 - 1 - - - 0 - Capture function on PWM group channel 3 Disabled - #0 - - - 1 - Capture function on PWM group channel 3 Enabled - #1 - - - read-write - - - CAPIF3 - Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero - 20 - 1 - read-write - - - CRLRI3 - CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 22 - 1 - read-write - - - CFLRI3 - CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. - 23 - 1 - read-write - - - - - CRLR0 - - CRLR0 - PWM Capture Rising Latch Register (Channel 0) - 0x58 - read-only - 0x00000000 - 0xFFFFFFFF - - - CRLRx - Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. - 0 - 16 - read-only - - - - - CFLR0 - - CFLR0 - PWM Capture Falling Latch Register (Channel 0) - 0x5C - read-only - 0x00000000 - 0xFFFFFFFF - - - CFLRx - Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. - 0 - 16 - read-only - - - - - CRLR1 - CRLR1 - PWM Capture Rising Latch Register (Channel 1) - 0x60 - - - CFLR1 - CFLR1 - PWM Capture Falling Latch Register (Channel 1) - 0x64 - - - CRLR2 - CRLR2 - PWM Capture Rising Latch Register (Channel 2) - 0x68 - - - CFLR2 - CFLR2 - PWM Capture Falling Latch Register (Channel 2) - 0x6C - - - CRLR3 - CRLR3 - PWM Capture Rising Latch Register (Channel 3) - 0x70 - - - CFLR3 - CFLR3 - PWM Capture Falling Latch Register (Channel 3) - 0x74 - - - CAPENR - - CAPENR - PWM Capture Input 0~3 Enable Register - 0x78 - read-write - 0x00000000 - 0xFFFFFFFF - - - CAPENR - Capture Input Enable Register\nThere are four capture inputs from pad. Bit0~Bit3 are used to control each input enable or disable. \n\nCAPENR\nBit 3210 for PWM group A\nBit xxx1 ( Capture channel 0 is from pin PA.12\nBit xx1x ( Capture channel 1 is from pin PA.13\nBit x1xx ( Capture channel 2 is from pin PA.14\nBit 1xxx ( Capture channel 3 is from pin PA.15\nBit 3210 for PWM group B\nBit xxx1 ( Capture channel 0 is from pin PB.11\nBit xx1x ( Capture channel 1 is from pin PE.5\nBit x1xx ( Capture channel 2 is from pin PE.0\nBit 1xxx ( Capture channel 3 is from pin PE.1 - 0 - 4 - - - 0 - Disabled (PWMx multi-function pin input does not affect input capture function.) - 0 - - - 1 - Enabled (PWMx multi-function pin input will affect its input capture function.) - 1 - - - read-write - - - - - POE - - POE - PWM Output Enable for channel 0~3 - 0x7C - read-write - 0x00000000 - 0xFFFFFFFF - - - PWM0 - Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 0 - 1 - - - 0 - PWM channel 0 output to pin Disabled - #0 - - - 1 - PWM channel 0 output to pin Enabled - #1 - - - read-write - - - PWM1 - Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 1 - 1 - - - 0 - PWM channel 1 output to pin Disabled - #0 - - - 1 - PWM channel 1 output to pin Enabled - #1 - - - read-write - - - PWM2 - Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 2 - 1 - - - 0 - PWM channel 2 output to pin Disabled - #0 - - - 1 - PWM channel 2 output to pin Enabled - #1 - - - read-write - - - PWM3 - Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. - 3 - 1 - - - 0 - PWM channel 3 output to pin Disabled - #0 - - - 1 - PWM channel 3 output to pin Enabled - #1 - - - read-write - - - - - TCON - - TCON - PWM Trigger Control for channel 0~3 - 0x80 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWM0TEN - Channel 0 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. - 0 - 1 - - - 0 - PWM channel 0 trigger ADC function Disabled - #0 - - - 1 - PWM channel 0 trigger ADC function Enabled - #1 - - - read-write - - - PWM1TEN - Channel 1 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode - 1 - 1 - - - 0 - PWM channel 1 trigger ADC function Disabled - #0 - - - 1 - PWM channel 1 trigger ADC function Enabled - #1 - - - read-write - - - PWM2TEN - Channel 2 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. - 2 - 1 - - - 0 - PWM channel 2 trigger ADC function Disabled - #0 - - - 1 - PWM channel 2 trigger ADC function Enabled - #1 - - - read-write - - - PWM3TEN - Channel 3 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. - 3 - 1 - - - 0 - PWM channel 3 trigger ADC function Disabled - #0 - - - 1 - PWM channel 3 trigger ADC function Enabled - #1 - - - read-write - - - - - TSTATUS - - TSTATUS - PWM Trigger Status Register - 0x84 - read-write - 0x00000000 - 0xFFFFFFFF - - - PWM0TF - Channel 0 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 0 - 1 - read-write - - - PWM1TF - Channel 1 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 1 - 1 - read-write - - - PWM2TF - Channel 2 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 2 - 1 - read-write - - - PWM3TF - Channel 3 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. - 3 - 1 - read-write - - - - - SYNCBUSY0 - - SYNCBUSY0 - PWM0 Synchronous Busy Status Register - 0x88 - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) to make sure previous setting has been update completely.\nThis bit will be set when software write CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely. - 0 - 1 - read-only - - - - - SYNCBUSY1 - - SYNCBUSY1 - PWM1 Synchronous Busy Status Register - 0x8C - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR1/CMR1/PPR or switch PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM updates these value completely. - 0 - 1 - read-only - - - - - SYNCBUSY2 - - SYNCBUSY2 - PWM2 Synchronous Busy Status Register - 0x90 - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM updates these value completely. - 0 - 1 - read-only - - - - - SYNCBUSY3 - - SYNCBUSY3 - PWM3 Synchronous Busy Status Register - 0x94 - read-only - 0x00000000 - 0xFFFFFFFF - - - S_BUSY - PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM updates these value completely. - 0 - 1 - read-only - - - - - CAPPDMACTL - - CAPPDMACTL - PWM PDMA Control Register - 0xC0 - read-write - 0x00000000 - 0xFFFFFFFF - - - CAP0PDMAEN - Channel 0 PDMA Enable\n - 0 - 1 - - - 0 - Channel 0 PDMA function Disabled - #0 - - - 1 - Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory - #1 - - - read-write - - - CAP0PDMAMOD - Select CRLR0 or CFLR0 to Transfer PDMA\n - 1 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR0 - #01 - - - 2 - CFLR0 - #10 - - - 3 - Both CRLR0 and CFLR0 - #11 - - - read-write - - - CAP0RFORDER - - 3 - 1 - - - 0 - CFLR0 is the first captured data to memory - #0 - - - 1 - CRLR0 is the first captured data to memory - #1 - - - read-write - - - CAP1PDMAEN - Channel 1 PDMA Enable\n - 8 - 1 - - - 0 - Channel 1 PDMA function Disabled - #0 - - - 1 - Channel 1 PDMA function Enabled for the channel 1 captured data and transfer to memory - #1 - - - read-write - - - CAP1PDMAMOD - Select CRLR1 or CFLR1 to Transfer PDMA\n - 9 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR1 - #01 - - - 2 - CFLR1 - #10 - - - 3 - both CRLR1 and CFLR1 - #11 - - - read-write - - - CAP1RFORDER - Capture channel 1 Rising/Falling Order\n - 11 - 1 - - - 0 - CFLR1 is the first captured data to memory - #0 - - - 1 - CRLR1 is the first captured data to memory - #1 - - - read-write - - - CAP2PDMAEN - Channel 2 PDMA Enable\n - 16 - 1 - - - 0 - Channel 2 PDMA function Disabled - #0 - - - 1 - Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory - #1 - - - read-write - - - CAP2PDMAMOD - Select CRLR2 or CFLR2 to do PDMA Transfer\n - 17 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR2 - #01 - - - 2 - CFLR2 - #10 - - - 3 - Both CRLR2 and CFLR2 - #11 - - - read-write - - - CAP2RFORDER - Capture channel 2 Rising/Falling Order\n - 19 - 1 - - - 0 - CFLR2 is the first captured data to memory - #0 - - - 1 - CRLR2 is the first captured data to memory - #1 - - - read-write - - - CAP3PDMAEN - Channel 3 PDMA enable\n - 24 - 1 - - - 0 - Channel 3 PDMA function Disabled - #0 - - - 1 - Channel 3 PDMA function Enabled for the channel 3 captured data and transfer to memory - #1 - - - read-write - - - CAP3PDMAMOD - Select CRLR3 or CFLR3 to do PDMA Transfer\n - 25 - 2 - - - 0 - Reserved - #00 - - - 1 - CRLR3 - #01 - - - 2 - CFLR3 - #10 - - - 3 - Both CRLR3 and CFLR3 - #11 - - - read-write - - - CAP3RFORDER - Capture Channel 3 Rising/Falling Order\n - 27 - 1 - - - 0 - CFLR3 is the first captured data to memory - #0 - - - 1 - CRLR3 is the first captured data to memory - #1 - - - read-write - - - - - CAP0PDMA - - CAP0PDMA - PWM PDMA Channel 0 Data Register - 0xC4 - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP0RFPDMA - PDMA data register for channel 0\nit is the capturing value(CFLR0/CRLR0) for channel 0 - 0 - 16 - read-only - - - - - CAP1PDMA - - CAP1PDMA - PWM PDMA Channel 1 Data Register - 0xC8 - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP1RFPDMA - PDMA data register for channel 1\nit is the capturing value(CFLR1/CRLR1) for channel 1 - 0 - 16 - read-only - - - - - CAP2PDMA - - CAP2PDMA - PWM PDMA Channel 2 Data Register - 0xCC - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP2RFPDMA - PDMA data register for channel 2\nit is the capturing value(CFLR2/CRLR2) for channel 2 - 0 - 16 - read-only - - - - - CAP3PDMA - - CAP3PDMA - PWM PDMA Channel 3 Data Register - 0xD0 - read-only - 0x00000000 - 0xFFFFFFFF - - - CAP3RFPDMA - PDMA data register for channel 3\nit is the capturing value(CFLR3/CRLR3) for channel 3 - 0 - 16 - read-only - - - - - - - SPI0 - SPI Register Map - SPI - 0x40030000 - - - 0x0 - 0xC - registers - - - 0x10 - 0x8 - registers - - - 0x20 - 0x8 - registers - - - 0x34 - 0x14 - registers - - - - SPI_CNTRL - - SPI_CNTRL - Control and Status Register - 0x0 - read-write - 0x05003004 - 0xFFFFFFFF - - - GO_BUSY - SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer. - 0 - 1 - - - 0 - Data transfer stopped - #0 - - - 1 - In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master - #1 - - - read-write - - - RX_NEG - Receive on Negative Edge\n - 1 - 1 - - - 0 - Received data input signal is latched on the rising edge of SPICLK - #0 - - - 1 - Received data input signal is latched on the falling edge of SPICLK - #1 - - - read-write - - - TX_NEG - Transmit on Negative Edge\n - 2 - 1 - - - 0 - Transmitted data output signal is changed on the rising edge of SPICLK - #0 - - - 1 - Transmitted data output signal is changed on the falling edge of SPICLK - #1 - - - read-write - - - TX_BIT_LEN - Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n - 3 - 5 - read-write - - - LSB - Send LSB First\n - 10 - 1 - - - 0 - The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first - #0 - - - 1 - The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) - #1 - - - read-write - - - CLKP - Clock Polarity\n - 11 - 1 - - - 0 - SPICLK is idle low - #0 - - - 1 - SPICLK is idle high - #1 - - - read-write - - - SP_CYCLE - Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. - 12 - 4 - read-write - - - IF - Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - No transaction has been finished since this bit was cleared to 0 - #0 - - - 1 - SPI controller has finished one unit transfer - #1 - - - read-write - - - IE - Unit Transfer Interrupt Enable\n - 17 - 1 - - - 0 - SPI unit transfer interrupt Disabled - #0 - - - 1 - SPI unit transfer interrupt Enabled - #1 - - - read-write - - - SLAVE - Slave Mode Enable\n - 18 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - REORDER - Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled. - 19 - 1 - - - 0 - Byte reorder function Disabled - #0 - - - 1 - Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE - #1 - - - read-write - - - FIFO - FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. - 21 - 1 - - - 0 - FIFO mode Disabled - #0 - - - 1 - FIFO mode Enabled - #1 - - - read-write - - - TWOB - 2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. - 22 - 1 - - - 0 - 2-bit mode Disabled - #0 - - - 1 - 2-bit mode Enabled - #1 - - - read-write - - - VARCLK_EN - Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). - 23 - 1 - - - 0 - Serial clock output frequency is fixed and decided only by the value of DIVIDER - #0 - - - 1 - Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 24 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n - 25 - 1 - - - 0 - Receive FIOF buffer is not full - #0 - - - 1 - Receive FIFO buffer is full - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n - 26 - 1 - - - 0 - Transmit FIFO buffer is not empty - #0 - - - 1 - Transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n - 27 - 1 - - - 0 - Transmit FIFO buffer is not full - #0 - - - 1 - Transmit FIFO buffer is full - #1 - - - read-only - - - - - SPI_DIVIDER - - SPI_DIVIDER - Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DIVIDER - Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register. - 0 - 8 - read-write - - - DIVIDER2 - Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. - 16 - 8 - read-write - - - - - SPI_SSR - - SPI_SSR - Slave Select Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - SSR - Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. - 0 - 2 - read-write - - - SS_LVL - Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n - 2 - 1 - - - 0 - The slave select signal SPISSx0/1 is active on low-level/falling-edge - #0 - - - 1 - The slave select signal SPISSx0/1 is active on high-level/rising-edge - #1 - - - read-write - - - AUTOSS - Automatic Slave Select Function Enable (Master Only)\n - 3 - 1 - - - 0 - If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] - #0 - - - 1 - If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished - #1 - - - read-write - - - SS_LTRIG - Slave Select Level Trigger Enable (Slave Only)\n - 4 - 1 - - - 0 - Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge - #0 - - - 1 - Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high - #1 - - - read-write - - - LTRIG_FLAG - Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. - 5 - 1 - - - 0 - Transferred bit length of one transaction does not meet the specified requirement - #0 - - - 1 - Transferred bit length meets the specified requirement which defined in TX_BIT_LEN - #1 - - - read-write - - - - - SPI_RX0 - - SPI_RX0 - Data Receive Register 0 - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - RX - Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. - 0 - 32 - read-only - - - - - SPI_RX1 - SPI_RX1 - Data Receive Registe 1 - 0x14 - - - SPI_TX0 - - SPI_TX0 - Data Transmit Register 0 - 0x20 - write-only - 0x00000000 - 0xFFFFFFFF - - - TX - Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 - 0 - 32 - write-only - - - - - SPI_TX1 - SPI_TX1 - Data Transmit Register 1 - 0x24 - - - SPI_VARCLK - - SPI_VARCLK - Variable Clock Pattern Register - 0x34 - read-write - 0x007FFF87 - 0xFFFFFFFF - - - VARCLK - Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. - 0 - 32 - read-write - - - - - SPI_DMA - - SPI_DMA - SPI DMA Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_DMA_GO - Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. - 0 - 1 - read-write - - - RX_DMA_GO - Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. - 1 - 1 - read-write - - - PDMA_RST - PDMA Reset\n - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically - #1 - - - read-write - - - - - SPI_CNTRL2 - - SPI_CNTRL2 - Control and Status Register 2 - 0x3C - read-write - 0x00001000 - 0xFFFFFFFF - - - NOSLVSEL - Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. - 8 - 1 - - - 0 - 4-wire bi-direction interface - #0 - - - 1 - 3-wire bi-direction interface - #1 - - - read-write - - - SLV_ABORT - Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. - 9 - 1 - read-write - - - SSTA_INTEN - Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n - 10 - 1 - - - 0 - Transaction start interrupt Disabled - #0 - - - 1 - Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared - #1 - - - read-write - - - SLV_START_INTSTS - Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n - 11 - 1 - - - 0 - Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 - #0 - - - 1 - A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit - #1 - - - read-write - - - DUAL_IO_DIR - Dual I/O Mode Direction Control\n - 12 - 1 - - - 0 - Dual Input mode - #0 - - - 1 - Dual Output mode - #1 - - - read-write - - - DUAL_IO_EN - Dual I/O Mode Enable\n - 13 - 1 - - - 0 - Dual I/O mode Disabled - #0 - - - 1 - Dual I/O mode Enabled - #1 - - - read-write - - - SS_INT_OPT - Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n - 16 - 1 - - - 0 - As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 - #0 - - - 1 - As the slave select signal goes to inactive level, the IF bit will be set to 1 - #1 - - - read-write - - - BCn - SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. - 31 - 1 - - - 0 - Backward compatible clock configuration - #0 - - - 1 - Clock configuration is not backward compatible - #1 - - - read-write - - - - - SPI_FIFO_CTL - - SPI_FIFO_CTL - SPI FIFO Control Register - 0x40 - read-write - 0x44000000 - 0xFFFFFFFF - - - RX_CLR - Clear Receive FIFO Buffer\n - 0 - 1 - - - 0 - No effect - #0 - - - 1 - Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software - #1 - - - read-write - - - TX_CLR - Clear Transmit FIFO Buffer\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software - #1 - - - read-write - - - RX_INTEN - Receive Threshold Interrupt Enable\n - 2 - 1 - - - 0 - RX threshold interrupt Disabled - #0 - - - 1 - RX threshold interrupt Enabled - #1 - - - read-write - - - TX_INTEN - Transmit Threshold Interrupt Enable\n - 3 - 1 - - - 0 - TX threshold interrupt Disabled - #0 - - - 1 - TX threshold interrupt Enabled - #1 - - - read-write - - - RXOV_INTEN - Receive FIFO Overrun Interrupt Enable\n - 6 - 1 - - - 0 - Receive FIFO overrun interrupt Disabled - #0 - - - 1 - Receive FIFO overrun interrupt Enabled - #1 - - - read-write - - - TIMEOUT_INTEN - Receive FIFO Time-out Interrupt Enable \n - 21 - 1 - - - 0 - Time-out interrupt Disabled - #0 - - - 1 - Time-out interrupt Enabled - #1 - - - read-write - - - RX_THRESHOLD - Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. - 24 - 3 - read-write - - - TX_THRESHOLD - Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. - 28 - 3 - read-write - - - - - SPI_STATUS - - SPI_STATUS - SPI Status Register - 0x44 - read-write - 0x05000000 - 0xFFFFFFFF - - - RX_INTSTS - Receive FIFO Threshold Interrupt Status (Read Only)\n - 0 - 1 - - - 0 - The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD - #0 - - - 1 - The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD - #1 - - - read-only - - - RX_OVERRUN - Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. - 2 - 1 - read-write - - - TX_INTSTS - Transmit FIFO Threshold Interrupt Status (Read Only)\n - 4 - 1 - - - 0 - The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD - #0 - - - 1 - The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD - #1 - - - read-only - - - SLV_START_INTSTS - Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n - 11 - 1 - - - 0 - Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 - #0 - - - 1 - A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit - #1 - - - read-write - - - RX_FIFO_COUNT - Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. - 12 - 4 - read-only - - - IF - SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - No transaction has been finished since this bit was cleared to 0 - #0 - - - 1 - SPI controller has finished one unit transfer - #1 - - - read-write - - - TIMEOUT - Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 20 - 1 - - - 0 - No receive FIFO time-out event - #0 - - - 1 - Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 24 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 25 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n - 26 - 1 - - - 0 - Transmit FIFO buffer is not empty - #0 - - - 1 - Transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n - 27 - 1 - - - 0 - Transmit FIFO buffer is not full - #0 - - - 1 - Transmit FIFO buffer is full - #1 - - - read-only - - - TX_FIFO_COUNT - Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. - 28 - 4 - read-only - - - - - - - SPI1 - SPI Register Map - SPI - 0x40034000 - - - 0x0 - 0xC - registers - - - 0x10 - 0x8 - registers - - - 0x20 - 0x8 - registers - - - 0x34 - 0x14 - registers - - - - SPI_CNTRL - - SPI_CNTRL - Control and Status Register - 0x0 - read-write - 0x05003004 - 0xFFFFFFFF - - - GO_BUSY - SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer. - 0 - 1 - - - 0 - Data transfer stopped - #0 - - - 1 - In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master - #1 - - - read-write - - - RX_NEG - Receive on Negative Edge\n - 1 - 1 - - - 0 - Received data input signal is latched on the rising edge of SPICLK - #0 - - - 1 - Received data input signal is latched on the falling edge of SPICLK - #1 - - - read-write - - - TX_NEG - Transmit on Negative Edge\n - 2 - 1 - - - 0 - Transmitted data output signal is changed on the rising edge of SPICLK - #0 - - - 1 - Transmitted data output signal is changed on the falling edge of SPICLK - #1 - - - read-write - - - TX_BIT_LEN - Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n - 3 - 5 - read-write - - - LSB - Send LSB First\n - 10 - 1 - - - 0 - The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first - #0 - - - 1 - The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) - #1 - - - read-write - - - CLKP - Clock Polarity\n - 11 - 1 - - - 0 - SPICLK is idle low - #0 - - - 1 - SPICLK is idle high - #1 - - - read-write - - - SP_CYCLE - Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. - 12 - 4 - read-write - - - IF - Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - No transaction has been finished since this bit was cleared to 0 - #0 - - - 1 - SPI controller has finished one unit transfer - #1 - - - read-write - - - IE - Unit Transfer Interrupt Enable\n - 17 - 1 - - - 0 - SPI unit transfer interrupt Disabled - #0 - - - 1 - SPI unit transfer interrupt Enabled - #1 - - - read-write - - - SLAVE - Slave Mode Enable\n - 18 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - REORDER - Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled. - 19 - 1 - - - 0 - Byte reorder function Disabled - #0 - - - 1 - Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE - #1 - - - read-write - - - FIFO - FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. - 21 - 1 - - - 0 - FIFO mode Disabled - #0 - - - 1 - FIFO mode Enabled - #1 - - - read-write - - - TWOB - 2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. - 22 - 1 - - - 0 - 2-bit mode Disabled - #0 - - - 1 - 2-bit mode Enabled - #1 - - - read-write - - - VARCLK_EN - Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). - 23 - 1 - - - 0 - Serial clock output frequency is fixed and decided only by the value of DIVIDER - #0 - - - 1 - Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 24 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n - 25 - 1 - - - 0 - Receive FIOF buffer is not full - #0 - - - 1 - Receive FIFO buffer is full - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n - 26 - 1 - - - 0 - Transmit FIFO buffer is not empty - #0 - - - 1 - Transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n - 27 - 1 - - - 0 - Transmit FIFO buffer is not full - #0 - - - 1 - Transmit FIFO buffer is full - #1 - - - read-only - - - - - SPI_DIVIDER - - SPI_DIVIDER - Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DIVIDER - Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register. - 0 - 8 - read-write - - - DIVIDER2 - Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. - 16 - 8 - read-write - - - - - SPI_SSR - - SPI_SSR - Slave Select Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - SSR - Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. - 0 - 2 - read-write - - - SS_LVL - Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n - 2 - 1 - - - 0 - The slave select signal SPISSx0/1 is active on low-level/falling-edge - #0 - - - 1 - The slave select signal SPISSx0/1 is active on high-level/rising-edge - #1 - - - read-write - - - AUTOSS - Automatic Slave Select Function Enable (Master Only)\n - 3 - 1 - - - 0 - If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] - #0 - - - 1 - If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished - #1 - - - read-write - - - SS_LTRIG - Slave Select Level Trigger Enable (Slave Only)\n - 4 - 1 - - - 0 - Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge - #0 - - - 1 - Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high - #1 - - - read-write - - - LTRIG_FLAG - Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. - 5 - 1 - - - 0 - Transferred bit length of one transaction does not meet the specified requirement - #0 - - - 1 - Transferred bit length meets the specified requirement which defined in TX_BIT_LEN - #1 - - - read-write - - - - - SPI_RX0 - - SPI_RX0 - Data Receive Register 0 - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - RX - Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. - 0 - 32 - read-only - - - - - SPI_RX1 - SPI_RX1 - Data Receive Register 1 - 0x14 - - - SPI_TX0 - - SPI_TX0 - Data Transmit Register 0 - 0x20 - write-only - 0x00000000 - 0xFFFFFFFF - - - TX - Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 - 0 - 32 - write-only - - - - - SPI_TX1 - SPI_TX1 - Data Transmit Register 1 - 0x24 - - - SPI_VARCLK - - SPI_VARCLK - Variable Clock Pattern Register - 0x34 - read-write - 0x007FFF87 - 0xFFFFFFFF - - - VARCLK - Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. - 0 - 32 - read-write - - - - - SPI_DMA - - SPI_DMA - SPI DMA Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_DMA_GO - Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. - 0 - 1 - read-write - - - RX_DMA_GO - Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. - 1 - 1 - read-write - - - PDMA_RST - PDMA Reset\n - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically - #1 - - - read-write - - - - - SPI_CNTRL2 - - SPI_CNTRL2 - Control and Status Register 2 - 0x3C - read-write - 0x00001000 - 0xFFFFFFFF - - - NOSLVSEL - Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. - 8 - 1 - - - 0 - 4-wire bi-direction interface - #0 - - - 1 - 3-wire bi-direction interface - #1 - - - read-write - - - SLV_ABORT - Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. - 9 - 1 - read-write - - - SSTA_INTEN - Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n - 10 - 1 - - - 0 - Transaction start interrupt Disabled - #0 - - - 1 - Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared - #1 - - - read-write - - - SLV_START_INTSTS - Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n - 11 - 1 - - - 0 - Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 - #0 - - - 1 - A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit - #1 - - - read-write - - - DUAL_IO_DIR - Dual I/O Mode Direction Control\n - 12 - 1 - - - 0 - Dual Input mode - #0 - - - 1 - Dual Output mode - #1 - - - read-write - - - DUAL_IO_EN - Dual I/O Mode Enable\n - 13 - 1 - - - 0 - Dual I/O mode Disabled - #0 - - - 1 - Dual I/O mode Enabled - #1 - - - read-write - - - SS_INT_OPT - Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n - 16 - 1 - - - 0 - As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 - #0 - - - 1 - As the slave select signal goes to inactive level, the IF bit will be set to 1 - #1 - - - read-write - - - BCn - SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. - 31 - 1 - - - 0 - Backward compatible clock configuration - #0 - - - 1 - Clock configuration is not backward compatible - #1 - - - read-write - - - - - SPI_FIFO_CTL - - SPI_FIFO_CTL - SPI FIFO Control Register - 0x40 - read-write - 0x44000000 - 0xFFFFFFFF - - - RX_CLR - Clear Receive FIFO Buffer\n - 0 - 1 - - - 0 - No effect - #0 - - - 1 - Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software - #1 - - - read-write - - - TX_CLR - Clear Transmit FIFO Buffer\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software - #1 - - - read-write - - - RX_INTEN - Receive Threshold Interrupt Enable\n - 2 - 1 - - - 0 - RX threshold interrupt Disabled - #0 - - - 1 - RX threshold interrupt Enabled - #1 - - - read-write - - - TX_INTEN - Transmit Threshold Interrupt Enable\n - 3 - 1 - - - 0 - TX threshold interrupt Disabled - #0 - - - 1 - TX threshold interrupt Enabled - #1 - - - read-write - - - RXOV_INTEN - Receive FIFO Overrun Interrupt Enable\n - 6 - 1 - - - 0 - Receive FIFO overrun interrupt Disabled - #0 - - - 1 - Receive FIFO overrun interrupt Enabled - #1 - - - read-write - - - TIMEOUT_INTEN - Receive FIFO Time-out Interrupt Enable \n - 21 - 1 - - - 0 - Time-out interrupt Disabled - #0 - - - 1 - Time-out interrupt Enabled - #1 - - - read-write - - - RX_THRESHOLD - Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. - 24 - 3 - read-write - - - TX_THRESHOLD - Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. - 28 - 3 - read-write - - - - - SPI_STATUS - - SPI_STATUS - SPI Status Register - 0x44 - read-write - 0x05000000 - 0xFFFFFFFF - - - RX_INTSTS - Receive FIFO Threshold Interrupt Status (Read Only)\n - 0 - 1 - - - 0 - The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD - #0 - - - 1 - The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD - #1 - - - read-only - - - RX_OVERRUN - Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. - 2 - 1 - read-write - - - TX_INTSTS - Transmit FIFO Threshold Interrupt Status (Read Only)\n - 4 - 1 - - - 0 - The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD - #0 - - - 1 - The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD - #1 - - - read-only - - - SLV_START_INTSTS - Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n - 11 - 1 - - - 0 - Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 - #0 - - - 1 - A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit - #1 - - - read-write - - - RX_FIFO_COUNT - Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. - 12 - 4 - read-only - - - IF - SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - No transaction has been finished since this bit was cleared to 0 - #0 - - - 1 - SPI controller has finished one unit transfer - #1 - - - read-write - - - TIMEOUT - Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 20 - 1 - - - 0 - No receive FIFO time-out event - #0 - - - 1 - Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 24 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 25 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n - 26 - 1 - - - 0 - Transmit FIFO buffer is not empty - #0 - - - 1 - Transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n - 27 - 1 - - - 0 - Transmit FIFO buffer is not full - #0 - - - 1 - Transmit FIFO buffer is full - #1 - - - read-only - - - TX_FIFO_COUNT - Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. - 28 - 4 - read-only - - - - - - - SPI2 - SPI Register Map - SPI - 0x40130000 - - - 0x0 - 0xC - registers - - - 0x10 - 0x8 - registers - - - 0x20 - 0x8 - registers - - - 0x34 - 0x14 - registers - - - - SPI_CNTRL - - SPI_CNTRL - Control and Status Register - 0x0 - read-write - 0x05003004 - 0xFFFFFFFF - - - GO_BUSY - SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer. - 0 - 1 - - - 0 - Data transfer stopped - #0 - - - 1 - In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master - #1 - - - read-write - - - RX_NEG - Receive on Negative Edge\n - 1 - 1 - - - 0 - Received data input signal is latched on the rising edge of SPICLK - #0 - - - 1 - Received data input signal is latched on the falling edge of SPICLK - #1 - - - read-write - - - TX_NEG - Transmit on Negative Edge\n - 2 - 1 - - - 0 - Transmitted data output signal is changed on the rising edge of SPICLK - #0 - - - 1 - Transmitted data output signal is changed on the falling edge of SPICLK - #1 - - - read-write - - - TX_BIT_LEN - Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n - 3 - 5 - read-write - - - LSB - Send LSB First\n - 10 - 1 - - - 0 - The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first - #0 - - - 1 - The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) - #1 - - - read-write - - - CLKP - Clock Polarity\n - 11 - 1 - - - 0 - SPICLK is idle low - #0 - - - 1 - SPICLK is idle high - #1 - - - read-write - - - SP_CYCLE - Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. - 12 - 4 - read-write - - - IF - Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - No transaction has been finished since this bit was cleared to 0 - #0 - - - 1 - SPI controller has finished one unit transfer - #1 - - - read-write - - - IE - Unit Transfer Interrupt Enable\n - 17 - 1 - - - 0 - SPI unit transfer interrupt Disabled - #0 - - - 1 - SPI unit transfer interrupt Enabled - #1 - - - read-write - - - SLAVE - Slave Mode Enable\n - 18 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - REORDER - Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled. - 19 - 1 - - - 0 - Byte reorder function Disabled - #0 - - - 1 - Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE - #1 - - - read-write - - - FIFO - FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. - 21 - 1 - - - 0 - FIFO mode Disabled - #0 - - - 1 - FIFO mode Enabled - #1 - - - read-write - - - TWOB - 2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. - 22 - 1 - - - 0 - 2-bit mode Disabled - #0 - - - 1 - 2-bit mode Enabled - #1 - - - read-write - - - VARCLK_EN - Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). - 23 - 1 - - - 0 - Serial clock output frequency is fixed and decided only by the value of DIVIDER - #0 - - - 1 - Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 24 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n - 25 - 1 - - - 0 - Receive FIOF buffer is not full - #0 - - - 1 - Receive FIFO buffer is full - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n - 26 - 1 - - - 0 - Transmit FIFO buffer is not empty - #0 - - - 1 - Transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n - 27 - 1 - - - 0 - Transmit FIFO buffer is not full - #0 - - - 1 - Transmit FIFO buffer is full - #1 - - - read-only - - - - - SPI_DIVIDER - - SPI_DIVIDER - Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - DIVIDER - Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register. - 0 - 8 - read-write - - - DIVIDER2 - Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. - 16 - 8 - read-write - - - - - SPI_SSR - - SPI_SSR - Slave Select Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - SSR - Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. - 0 - 2 - read-write - - - SS_LVL - Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n - 2 - 1 - - - 0 - The slave select signal SPISSx0/1 is active on low-level/falling-edge - #0 - - - 1 - The slave select signal SPISSx0/1 is active on high-level/rising-edge - #1 - - - read-write - - - AUTOSS - Automatic Slave Select Function Enable (Master Only)\n - 3 - 1 - - - 0 - If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] - #0 - - - 1 - If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished - #1 - - - read-write - - - SS_LTRIG - Slave Select Level Trigger Enable (Slave Only)\n - 4 - 1 - - - 0 - Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge - #0 - - - 1 - Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high - #1 - - - read-write - - - LTRIG_FLAG - Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. - 5 - 1 - - - 0 - Transferred bit length of one transaction does not meet the specified requirement - #0 - - - 1 - Transferred bit length meets the specified requirement which defined in TX_BIT_LEN - #1 - - - read-write - - - - - SPI_RX0 - - SPI_RX0 - Data Receive Register 0 - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - RX - Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. - 0 - 32 - read-only - - - - - SPI_RX1 - SPI_RX1 - Data Receive Register 1 - 0x14 - - - SPI_TX0 - - SPI_TX0 - Data Transmit Register 0 - 0x20 - write-only - 0x00000000 - 0xFFFFFFFF - - - TX - Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 - 0 - 32 - write-only - - - - - SPI_TX1 - SPI_TX1 - Data Transmit Register 1 - 0x24 - - - SPI_VARCLK - - SPI_VARCLK - Variable Clock Pattern Register - 0x34 - read-write - 0x007FFF87 - 0xFFFFFFFF - - - VARCLK - Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. - 0 - 32 - read-write - - - - - SPI_DMA - - SPI_DMA - SPI DMA Control Register - 0x38 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_DMA_GO - Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. - 0 - 1 - read-write - - - RX_DMA_GO - Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. - 1 - 1 - read-write - - - PDMA_RST - PDMA Reset\n - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically - #1 - - - read-write - - - - - SPI_CNTRL2 - - SPI_CNTRL2 - Control and Status Register 2 - 0x3C - read-write - 0x00001000 - 0xFFFFFFFF - - - NOSLVSEL - Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. - 8 - 1 - - - 0 - 4-wire bi-direction interface - #0 - - - 1 - 3-wire bi-direction interface - #1 - - - read-write - - - SLV_ABORT - Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. - 9 - 1 - read-write - - - SSTA_INTEN - Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n - 10 - 1 - - - 0 - Transaction start interrupt Disabled - #0 - - - 1 - Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared - #1 - - - read-write - - - SLV_START_INTSTS - Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n - 11 - 1 - - - 0 - Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 - #0 - - - 1 - A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit - #1 - - - read-write - - - DUAL_IO_DIR - Dual I/O Mode Direction Control\n - 12 - 1 - - - 0 - Dual Input mode - #0 - - - 1 - Dual Output mode - #1 - - - read-write - - - DUAL_IO_EN - Dual I/O Mode Enable\n - 13 - 1 - - - 0 - Dual I/O mode Disabled - #0 - - - 1 - Dual I/O mode Enabled - #1 - - - read-write - - - SS_INT_OPT - Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n - 16 - 1 - - - 0 - As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 - #0 - - - 1 - As the slave select signal goes to inactive level, the IF bit will be set to 1 - #1 - - - read-write - - - BCn - SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. - 31 - 1 - - - 0 - Backward compatible clock configuration - #0 - - - 1 - Clock configuration is not backward compatible - #1 - - - read-write - - - - - SPI_FIFO_CTL - - SPI_FIFO_CTL - SPI FIFO Control Register - 0x40 - read-write - 0x44000000 - 0xFFFFFFFF - - - RX_CLR - Clear Receive FIFO Buffer\n - 0 - 1 - - - 0 - No effect - #0 - - - 1 - Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software - #1 - - - read-write - - - TX_CLR - Clear Transmit FIFO Buffer\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software - #1 - - - read-write - - - RX_INTEN - Receive Threshold Interrupt Enable\n - 2 - 1 - - - 0 - RX threshold interrupt Disabled - #0 - - - 1 - RX threshold interrupt Enabled - #1 - - - read-write - - - TX_INTEN - Transmit Threshold Interrupt Enable\n - 3 - 1 - - - 0 - TX threshold interrupt Disabled - #0 - - - 1 - TX threshold interrupt Enabled - #1 - - - read-write - - - RXOV_INTEN - Receive FIFO Overrun Interrupt Enable\n - 6 - 1 - - - 0 - Receive FIFO overrun interrupt Disabled - #0 - - - 1 - Receive FIFO overrun interrupt Enabled - #1 - - - read-write - - - TIMEOUT_INTEN - Receive FIFO Time-out Interrupt Enable \n - 21 - 1 - - - 0 - Time-out interrupt Disabled - #0 - - - 1 - Time-out interrupt Enabled - #1 - - - read-write - - - RX_THRESHOLD - Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. - 24 - 3 - read-write - - - TX_THRESHOLD - Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. - 28 - 3 - read-write - - - - - SPI_STATUS - - SPI_STATUS - SPI Status Register - 0x44 - read-write - 0x05000000 - 0xFFFFFFFF - - - RX_INTSTS - Receive FIFO Threshold Interrupt Status (Read Only)\n - 0 - 1 - - - 0 - The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD - #0 - - - 1 - The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD - #1 - - - read-only - - - RX_OVERRUN - Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. - 2 - 1 - read-write - - - TX_INTSTS - Transmit FIFO Threshold Interrupt Status (Read Only)\n - 4 - 1 - - - 0 - The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD - #0 - - - 1 - The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD - #1 - - - read-only - - - SLV_START_INTSTS - Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n - 11 - 1 - - - 0 - Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 - #0 - - - 1 - A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit - #1 - - - read-write - - - RX_FIFO_COUNT - Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. - 12 - 4 - read-only - - - IF - SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. - 16 - 1 - - - 0 - No transaction has been finished since this bit was cleared to 0 - #0 - - - 1 - SPI controller has finished one unit transfer - #1 - - - read-write - - - TIMEOUT - Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. - 20 - 1 - - - 0 - No receive FIFO time-out event - #0 - - - 1 - Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically - #1 - - - read-write - - - RX_EMPTY - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 24 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - RX_FULL - Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n - 25 - 1 - - - 0 - Receive FIFO buffer is not empty - #0 - - - 1 - Receive FIFO buffer is empty - #1 - - - read-only - - - TX_EMPTY - Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n - 26 - 1 - - - 0 - Transmit FIFO buffer is not empty - #0 - - - 1 - Transmit FIFO buffer is empty - #1 - - - read-only - - - TX_FULL - Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n - 27 - 1 - - - 0 - Transmit FIFO buffer is not full - #0 - - - 1 - Transmit FIFO buffer is full - #1 - - - read-only - - - TX_FIFO_COUNT - Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. - 28 - 4 - read-only - - - - - - - TMR01 - TIMER Register Map - TIMER - 0x40010000 - - - 0x0 - 0x1C - registers - - - 0x20 - 0x1C - registers - - - - TCSR0 - - TCSR0 - Timer0 Control and Status Register - 0x0 - read-write - 0x00000005 - 0xFFFFFFFF - - - PRESCALE - Pre-scale Counter\n - 0 - 8 - read-write - - - TDR_EN - Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n - 16 - 1 - - - 0 - Timer Data Register update Disabled - #0 - - - 1 - Timer Data Register update Enabled - #1 - - - read-write - - - WAKE_EN - Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n - 23 - 1 - - - 0 - Wake-up trigger event Disabled - #0 - - - 1 - Wake-up trigger event Enabled - #1 - - - read-write - - - CTB - Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n - 24 - 1 - - - 0 - Counter mode Disabled - #0 - - - 1 - Counter mode Enabled - #1 - - - read-write - - - CACT - Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n - 25 - 1 - - - 0 - Timer is not active - #0 - - - 1 - Timer is active - #1 - - - read-only - - - CRST - Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n - 26 - 1 - - - 0 - No effect - #0 - - - 1 - Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit - #1 - - - read-write - - - MODE - Timer Operating Mode\n - 27 - 2 - read-write - - - IE - Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. - 29 - 1 - - - 0 - Timer Interrupt Disabled - #0 - - - 1 - Timer Interrupt Enabled - #1 - - - read-write - - - CEN - Timer Enable Bit\n - 30 - 1 - - - 0 - Stops/Suspends counting - #0 - - - 1 - Starts counting - #1 - - - read-write - - - DBGACK_TMR - ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not. - 31 - 1 - - - 0 - ICE debug mode acknowledgement effects TIMER counting - #0 - - - 1 - ICE debug mode acknowledgement disabled - #1 - - - read-write - - - - - TCMPR0 - - TCMPR0 - Timer0 Compare Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - TCMP - Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. - 0 - 24 - read-write - - - - - TISR0 - - TISR0 - Timer0 Interrupt Status Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. - 0 - 1 - read-write - - - TWF - Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n - 1 - 1 - - - 0 - Timer does not cause CPU wakeup - #0 - - - 1 - CPU wakes up from sleep or power-down mode by timer time-out - #1 - - - read-write - - - - - TDR0 - - TDR0 - Timer0 Data Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - TDR - Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1 - 0 - 24 - read-only - - - - - TCAP0 - - TCAP0 - Timer0 Capture Data Register - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - TCAP - Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value. - 0 - 24 - read-only - - - - - TEXCON0 - - TEXCON0 - Timer0 External Control Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_PHASE - Timer External Count Phase \nThis bit indicates the external count pin phase.\n - 0 - 1 - - - 0 - A falling edge of external count pin will be counted - #0 - - - 1 - A rising edge of external count pin will be counted - #1 - - - read-write - - - TEX_EDGE - Timer External Pin Edge Detect\n - 1 - 2 - - - 0 - 1 to 0 transition on TEX will be detected - #00 - - - 1 - 0 to 1 transition on TEX will be detected - #01 - - - 2 - Either 1 to 0 or 0 to 1 transition on TEX will be detected - #10 - - - 3 - Reserved - #11 - - - read-write - - - TEXEN - Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n - 3 - 1 - - - 0 - TEX pin will be ignored - #0 - - - 1 - Transition detected on the TEX pin will result in capture or reset of timer counter - #1 - - - read-write - - - RSTCAPn - Timer External Reset Counter/Capture Mode Selection\n - 4 - 1 - - - 0 - TEX transition is used as the timer capture function - #0 - - - 1 - TEX transition is used as the timer counter reset function - #1 - - - read-write - - - TEXIEN - Timer External Interrupt Enable Bit\n - 5 - 1 - - - 0 - Timer external interrupt Disabled - #0 - - - 1 - Timer external interrupt Enabled - #1 - - - read-write - - - TEXDB - Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit. - 6 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - TCDB - Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit. - 7 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - - - TEXISR0 - - TEXISR0 - Timer0 External Interrupt Status Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - TEXIF - Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n - 0 - 1 - read-write - - - - - TCSR1 - TCSR1 - Timer1 Control and Status Register - 0x20 - - - TCMPR1 - TCMPR1 - Timer1 Compare Register - 0x24 - - - TISR1 - TISR1 - Timer1 Interrupt Status Register - 0x28 - - - TDR1 - TDR1 - Timer1 Data Register - 0x2C - - - TCAP1 - TCAP1 - Timer1 Capture Data Register - 0x30 - - - TEXCON1 - TEXCON1 - Timer1 External Control Register - 0x34 - - - TEXISR1 - TEXISR1 - Timer1 External Interrupt Status Register - 0x38 - - - - - TMR23 - TIMER Register Map - TIMER - 0x40110000 - - - 0x0 - 0x1C - registers - - - 0x20 - 0x1C - registers - - - - TCSR2 - - TCSR2 - Timer2 Control and Status Register - 0x0 - read-write - 0x00000005 - 0xFFFFFFFF - - - PRESCALE - Pre-scale Counter\n - 0 - 8 - read-write - - - TDR_EN - Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n - 16 - 1 - - - 0 - Timer Data Register update Disabled - #0 - - - 1 - Timer Data Register update Enabled - #1 - - - read-write - - - WAKE_EN - Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n - 23 - 1 - - - 0 - Wake-up trigger event Disabled - #0 - - - 1 - Wake-up trigger event Enabled - #1 - - - read-write - - - CTB - Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n - 24 - 1 - - - 0 - Counter mode Disabled - #0 - - - 1 - Counter mode Enabled - #1 - - - read-write - - - CACT - Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n - 25 - 1 - - - 0 - Timer is not active - #0 - - - 1 - Timer is active - #1 - - - read-only - - - CRST - Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n - 26 - 1 - - - 0 - No effect - #0 - - - 1 - Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit - #1 - - - read-write - - - MODE - Timer Operating Mode\n - 27 - 2 - read-write - - - IE - Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. - 29 - 1 - - - 0 - Timer Interrupt Disabled - #0 - - - 1 - Timer Interrupt Enabled - #1 - - - read-write - - - CEN - Timer Enable Bit\n - 30 - 1 - - - 0 - Stops/Suspends counting - #0 - - - 1 - Starts counting - #1 - - - read-write - - - DBGACK_TMR - ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not. - 31 - 1 - - - 0 - ICE debug mode acknowledgement effects TIMER counting - #0 - - - 1 - ICE debug mode acknowledgement disabled - #1 - - - read-write - - - - - TCMPR2 - - TCMPR2 - Timer2 Compare Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - TCMP - Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. - 0 - 24 - read-write - - - - - TISR2 - - TISR2 - Timer2 Interrupt Status Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIF - Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. - 0 - 1 - read-write - - - TWF - Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n - 1 - 1 - - - 0 - Timer does not cause CPU wakeup - #0 - - - 1 - CPU wakes up from sleep or power-down mode by timer time-out - #1 - - - read-write - - - - - TDR2 - - TDR2 - Timer2 Data Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - TDR - Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1 - 0 - 24 - read-only - - - - - TCAP2 - - TCAP2 - Timer2 Capture Data Register - 0x10 - read-only - 0x00000000 - 0xFFFFFFFF - - - TCAP - Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value. - 0 - 24 - read-only - - - - - TEXCON2 - - TEXCON2 - Timer2 External Control Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - TX_PHASE - Timer External Count Phase \nThis bit indicates the external count pin phase.\n - 0 - 1 - - - 0 - A falling edge of external count pin will be counted - #0 - - - 1 - A rising edge of external count pin will be counted - #1 - - - read-write - - - TEX_EDGE - Timer External Pin Edge Detect\n - 1 - 2 - - - 0 - 1 to 0 transition on TEX will be detected - #00 - - - 1 - 0 to 1 transition on TEX will be detected - #01 - - - 2 - Either 1 to 0 or 0 to 1 transition on TEX will be detected - #10 - - - 3 - Reserved - #11 - - - read-write - - - TEXEN - Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n - 3 - 1 - - - 0 - TEX pin will be ignored - #0 - - - 1 - Transition detected on the TEX pin will result in capture or reset of timer counter - #1 - - - read-write - - - RSTCAPn - Timer External Reset Counter/Capture Mode Selection\n - 4 - 1 - - - 0 - TEX transition is used as the timer capture function - #0 - - - 1 - TEX transition is used as the timer counter reset function - #1 - - - read-write - - - TEXIEN - Timer External Interrupt Enable Bit\n - 5 - 1 - - - 0 - Timer external interrupt Disabled - #0 - - - 1 - Timer external interrupt Enabled - #1 - - - read-write - - - TEXDB - Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit. - 6 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - TCDB - Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit. - 7 - 1 - - - 0 - De-bounce Disabled - #0 - - - 1 - De-bounce Enabled - #1 - - - read-write - - - - - TEXISR2 - - TEXISR2 - Timer2 External Interrupt Status Register - 0x18 - read-write - 0x00000000 - 0xFFFFFFFF - - - TEXIF - Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n - 0 - 1 - read-write - - - - - TCSR3 - TCSR3 - Timer3 Control and Status Register - 0x20 - - - TCMPR3 - TCMPR3 - Timer3 Compare Register - 0x24 - - - TISR3 - TISR3 - Timer3 Interrupt Status Register - 0x28 - - - TDR3 - TDR3 - Timer3 Data Register - 0x2C - - - TCAP3 - TCAP3 - Timer3 Capture Data Register - 0x30 - - - TEXCON3 - TEXCON3 - Timer3 External Control Register - 0x34 - - - TEXISR3 - TEXISR3 - Timer3 External Interrupt Status Register - 0x38 - - - - - WDT - WDT Register Map - WDT - 0x40004000 - - - 0x0 - 0x8 - registers - - - - WTCR - - WTCR - Watchdog Timer Control Register - 0x0 - read-write - 0x00000700 - 0xFFFFFFFF - - - WTR - Clear Watchdog Timer (Write-protection Bit)\nSetting this bit will clear the Watchdog timer.\nNote: This bit will be automatically cleared by hardware. - 0 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the contents of the Watchdog timer - #1 - - - read-write - - - WTRE - Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog timer reset function.\n - 1 - 1 - - - 0 - Watchdog timer reset function Disabled - #0 - - - 1 - Watchdog timer reset function Enabled - #1 - - - read-write - - - WTRF - Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, the Watchdog timer has no effect on this bit.\nNote: This bit is cleared by writing 1 to this bit. - 2 - 1 - - - 0 - Watchdog timer reset did not occur - #0 - - - 1 - Watchdog timer reset occurred - #1 - - - read-write - - - WTIF - Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.\nNote: This bit is cleared by writing 1 to this bit. - 3 - 1 - - - 0 - Watchdog timer interrupt did not occur - #0 - - - 1 - Watchdog timer interrupt occurred - #1 - - - read-write - - - WTWKE - Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nNote: Chip can be woken up by WDT only if WDT clock source select RC10K. - 4 - 1 - - - 0 - Watchdog timer Wake-up chip function Disabled - #0 - - - 1 - Wake-up function Enabled so that Watchdog timer time-out can wake-up chip from Power-down mode - #1 - - - read-write - - - WTWKF - Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip to wake up from Power-down mode, this bit will be set to high. It must be cleared by software by writing 1 to this bit.\n - 5 - 1 - - - 0 - Watchdog timer does not cause chip wake up - #0 - - - 1 - Chip woken up from Idle or Power-down mode by Watchdog time-out - #1 - - - read-write - - - WTIE - Watchdog Timer Interrupt Enable (Write-protection Bit)\n - 6 - 1 - - - 0 - Watchdog timer interrupt Disabled - #0 - - - 1 - Watchdog timer interrupt Enabled - #1 - - - read-write - - - WTE - Watchdog Timer Enable (Write-protection Bit)\n - 7 - 1 - - - 0 - Watchdog timer Disabled (This action will reset the internal counter) - #0 - - - 1 - Watchdog timer Enabled - #1 - - - read-write - - - WTIS - Watchdog Timer Interval Selection (Write-protection Bit)\n - 8 - 3 - read-write - - - DBGACK_WDT - ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not. - 31 - 1 - - - 0 - ICE debug mode acknowledgement affects Watchdog Timer counting - #0 - - - 1 - ICE debug mode acknowledgement Disabled - #1 - - - read-write - - - - - WTCRALT - - WTCRALT - Watchdog Timer Alternative Control Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - WTRDSEL - Watchdog Timer Reset Delay Select (Write-protection Bits)\nWhen watchdog time-out happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay period for different watchdog time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nThis register will be reset if watchdog reset happened - 0 - 2 - - - 0 - Watchdog reset delay period is 1024 watchdog clock - #00 - - - 1 - Watchdog reset delay period is 128 watchdog clock - #01 - - - 2 - Watchdog reset delay period is 16 watchdog clock - #10 - - - 3 - Watchdog reset delay period is 1 watchdog clock - #11 - - - read-write - - - - - - - WWDT - WWDT Register Map - WWDT - 0x40004100 - - - 0x0 - 0x10 - registers - - - - WWDTRLD - - WWDTRLD - Window Watchdog Timer Reload Counter Register - 0x0 - write-only - 0x00000000 - 0xFFFFFFFF - - - WWDTRLD - WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal. - 0 - 32 - write-only - - - - - WWDTCR - - WWDTCR - Window Watchdog Timer Control Register - 0x4 - read-write - 0x003F0800 - 0xFFFFFFFF - - - WWDTEN - WWDT Enable\nSet this bit to enable the Window Watchdog timer.\n - 0 - 1 - - - 0 - Window Watchdog timer function Disabled - #0 - - - 1 - Window Watchdog timer function Enabled - #1 - - - read-write - - - WWDTIE - WWDT Interrupt Enable\nSet this bit to enable the Watchdog timer interrupt function.\n - 1 - 1 - - - 0 - Watchdog timer interrupt function Disabled - #0 - - - 1 - Watchdog timer interrupt function Enabled - #1 - - - read-write - - - PERIODSEL - WWDT Pre-scale Period Select\n - 8 - 4 - read-write - - - WINCMP - WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value is larger than WWCMP, WWDT will generate RESET signal. - 16 - 6 - read-write - - - DBGACK_WWDT - ICE debug mode acknowledge Disable\n - 31 - 1 - - - 0 - WWDT count stopped if system is in Debug mode - #0 - - - 1 - WWDT still count even system is in Debug mode - #1 - - - read-write - - - - - WWDTSTS - - WWDTSTS - Window Watchdog Timer Status Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - WWDTIF - WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit will be cleared by software write 1 to this bit. - 0 - 1 - read-write - - - WWDTRF - WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0. - 1 - 1 - read-write - - - - - WWDTCVR - - WWDTCVR - Window Watchdog Counter Value Register - 0xC - read-only - 0x0000003F - 0xFFFFFFFF - - - WWDTCVAL - WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only. - 0 - 6 - read-only - - - - - - - UART0 - UART Register Map - UART - 0x40050000 - - - 0x0 - 0x34 - registers - - - - UA_RBR - - UA_RBR - UART Receive Buffer Register - 0x0 - read-only - 0x00000000 - 0x00000000 - - - RBR - Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). - 0 - 8 - read-only - - - - - UA_THR - UA_RBR - - UA_THR - UART Transmit Holding Register - 0x0 - write-only - 0x00000000 - 0x00000000 - - - THR - Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). - 0 - 8 - write-only - - - - - UA_IER - - UA_IER - UART Interrupt Enable Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - RDA_IEN - Receive Data Available Interrupt Enable.\n - 0 - 1 - - - 0 - INT_RDA Masked off - #0 - - - 1 - INT_RDA Enabled - #1 - - - read-write - - - THRE_IEN - Transmit Holding Register Empty Interrupt Enable\n - 1 - 1 - - - 0 - INT_THRE Masked off - #0 - - - 1 - INT_THRE Enabled - #1 - - - read-write - - - RLS_IEN - Receive Line Status Interrupt Enable \n - 2 - 1 - - - 0 - INT_RLS Masked off - #0 - - - 1 - INT_RLS Enabled - #1 - - - read-write - - - MODEM_IEN - Modem Status Interrupt Enable\n - 3 - 1 - - - 0 - INT_MODEM Masked off - #0 - - - 1 - INT_MODEM Enabled - #1 - - - read-write - - - RTO_IEN - RX Time Out Interrupt Enable\n - 4 - 1 - - - 0 - INT_TOUT Masked off - #0 - - - 1 - INT_TOUT Enabled - #1 - - - read-write - - - BUF_ERR_IEN - Buffer Error Interrupt Enable\n - 5 - 1 - - - 0 - INT_BUF_ERR Masked off - #0 - - - 1 - INT_BUF_ERR Enabled - #1 - - - read-write - - - WAKE_EN - UART Wake-up Function Enable\n - 6 - 1 - - - 0 - UART wake-up function Disabled - #0 - - - 1 - UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode - #1 - - - read-write - - - TIME_OUT_EN - Time Out Counter Enable\n - 11 - 1 - - - 0 - Time-out counter Disabled - #0 - - - 1 - Time-out counter Enabled - #1 - - - read-write - - - AUTO_RTS_EN - RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. - 12 - 1 - - - 0 - RTS auto flow control Disabled - #0 - - - 1 - RTS auto flow control Enabled - #1 - - - read-write - - - AUTO_CTS_EN - CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). - 13 - 1 - - - 0 - CTS auto flow control Disabled - #0 - - - 1 - CTS auto flow control Enabled - #1 - - - read-write - - - DMA_TX_EN - TX DMA Enable\nThis bit can enable or disable TX DMA service.\n - 14 - 1 - - - 0 - TX DMA Disabled - #0 - - - 1 - TX DMA Enabled - #1 - - - read-write - - - DMA_RX_EN - RX DMA Enable\nThis bit can enable or disable RX DMA service.\n - 15 - 1 - - - 0 - RX DMA Disabled - #0 - - - 1 - RX DMA Enabled - #1 - - - read-write - - - - - UA_FCR - - UA_FCR - UART FIFO Control Register - 0x8 - read-write - 0x00000101 - 0xFFFFFFFF - - - RFR - RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the RX internal state machine and pointers - #1 - - - read-write - - - TFR - TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the TX internal state machine and pointers - #1 - - - read-write - - - RFITL - RX FIFO Interrupt (INT_RDA) Trigger Level\n - 4 - 4 - read-write - - - RX_DIS - Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. - 8 - 1 - - - 0 - Receiver Enabled - #0 - - - 1 - Receiver Disabled - #1 - - - read-write - - - RTS_TRI_LEV - RTS Trigger Level for Auto-flow Control Use\n - 16 - 4 - read-write - - - - - UA_LCR - - UA_LCR - UART Line Control Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - WLS - Word Length Selection\n - 0 - 2 - read-write - - - NSB - Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected. - 2 - 1 - - - 0 - One " STOP bit" is generated in the transmitted data - #0 - - - 1 - One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; - #1 - - - read-write - - - PBE - Parity Bit Enable\n - 3 - 1 - - - 0 - No parity bit - #0 - - - 1 - Parity bit is generated on each outgoing character and is checked on each incoming data - #1 - - - read-write - - - EPE - Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. - 4 - 1 - - - 0 - Odd number of logic 1's is transmitted and checked in each word - #0 - - - 1 - Even number of logic 1's is transmitted and checked in each word - #1 - - - read-write - - - SPE - Stick Parity Enable\n - 5 - 1 - - - 0 - Stick parity Disabled - #0 - - - 1 - If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 - #1 - - - read-write - - - BCB - Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. - 6 - 1 - read-write - - - - - UA_MCR - - UA_MCR - UART Modem Control Register - 0x10 - read-write - 0x00000200 - 0xFFFFFFFF - - - RTS - RTS (Request-To-Send) Signal\n - 1 - 1 - - - 0 - Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) - #0 - - - 1 - Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) - #1 - - - read-write - - - LEV_RTS - RTS Trigger Level\nThis bit can change the RTS trigger level.\n - 9 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - RTS_ST - RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. - 13 - 1 - read-only - - - - - UA_MSR - - UA_MSR - UART Modem Status Register - 0x14 - read-write - 0x00000110 - 0xFFFFFFFF - - - DCTSF - Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - read-only - - - CTS_ST - CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. - 4 - 1 - read-only - - - LEV_CTS - CTS Trigger Level\nThis bit can change the CTS trigger level.\n - 8 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - - - UA_FSR - - UA_FSR - UART FIFO Status Register - 0x18 - read-write - 0x10404000 - 0xFFFFFFFF - - - RX_OVER_IF - RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 0 - 1 - read-only - - - RS485_ADD_DETF - RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 3 - 1 - read-only - - - PEF - Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 4 - 1 - read-only - - - FEF - Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 5 - 1 - read-only - - - BIF - Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 6 - 1 - read-only - - - RX_POINTER - RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. - 8 - 6 - read-only - - - RX_EMPTY - Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. - 14 - 1 - read-only - - - RX_FULL - Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 15 - 1 - read-only - - - TX_POINTER - TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. - 16 - 6 - read-only - - - TX_EMPTY - Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). - 22 - 1 - read-only - - - TX_FULL - Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 23 - 1 - read-only - - - TX_OVER_IF - TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. - 24 - 1 - read-only - - - TE_FLAG - Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. - 28 - 1 - read-only - - - - - UA_ISR - - UA_ISR - UART Interrupt Status Register - 0x1C - read-write - 0x00000002 - 0xFFFFFFFF - - - RDA_IF - Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). - 0 - 1 - read-only - - - THRE_IF - Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). - 1 - 1 - read-only - - - RLS_IF - Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 2 - 1 - read-only - - - MODEM_IF - MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 3 - 1 - read-only - - - TOUT_IF - Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 4 - 1 - read-only - - - BUF_ERR_IF - Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 5 - 1 - read-only - - - RDA_INT - Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n - 8 - 1 - - - 0 - No RDA interrupt is generated - #0 - - - 1 - RDA interrupt is generated - #1 - - - read-only - - - THRE_INT - Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n - 9 - 1 - - - 0 - No THRE interrupt is generated - #0 - - - 1 - THRE interrupt is generated - #1 - - - read-only - - - RLS_INT - Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n - 10 - 1 - - - 0 - No RLS interrupt is generated - #0 - - - 1 - RLS interrupt is generated - #1 - - - read-only - - - MODEM_INT - MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n - 11 - 1 - - - 0 - No Modem interrupt is generated - #0 - - - 1 - Modem interrupt is generated - #1 - - - read-only - - - TOUT_INT - Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n - 12 - 1 - - - 0 - No Tout interrupt is generated - #0 - - - 1 - Tout interrupt is generated - #1 - - - read-only - - - BUF_ERR_INT - Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n - 13 - 1 - - - 0 - No buffer error interrupt is generated - #0 - - - 1 - Buffer error interrupt is generated - #1 - - - read-only - - - HW_RLS_IF - In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 18 - 1 - read-only - - - HW_MODEM_IF - In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 19 - 1 - read-only - - - HW_TOUT_IF - In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 20 - 1 - read-only - - - HW_BUF_ERR_IF - In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 21 - 1 - read-only - - - HW_RLS_INT - In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n - 26 - 1 - - - 0 - No RLS interrupt is generated in DMA mode - #0 - - - 1 - RLS interrupt is generated in DMA mode - #1 - - - read-only - - - HW_MODEM_INT - In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n - 27 - 1 - - - 0 - No Modem interrupt is generated in DMA mode - #0 - - - 1 - Modem interrupt is generated in DMA mode - #1 - - - read-only - - - HW_TOUT_INT - In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n - 28 - 1 - - - 0 - No Tout interrupt is generated in DMA mode - #0 - - - 1 - Tout interrupt is generated in DMA mode - #1 - - - read-only - - - HW_BUF_ERR_INT - In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n - 29 - 1 - - - 0 - No buffer error interrupt is generated in DMA mode - #0 - - - 1 - Buffer error interrupt is generated in DMA mode - #1 - - - read-only - - - - - UA_TOR - - UA_TOR - UART Time Out Register - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - TOIC - Time Out Interrupt Comparator\n - 0 - 8 - read-write - - - DLY - TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. - 8 - 8 - read-write - - - - - UA_BAUD - - UA_BAUD - UART Baud Rate Divisor Register - 0x24 - read-write - 0x0F000000 - 0xFFFFFFFF - - - BRD - Baud Rate Divider\nThe field indicates the baud rate divider. - 0 - 16 - read-write - - - DIVIDER_X - Divider X\n - 24 - 4 - read-write - - - DIV_X_ONE - Divider X Equal to 1\nRefer to the Table 515 below for more information. - 28 - 1 - - - 0 - Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) - #0 - - - 1 - Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) - #1 - - - read-write - - - DIV_X_EN - Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled. - 29 - 1 - - - 0 - Divider X Disabled (the equation of M = 16) - #0 - - - 1 - Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) - #1 - - - read-write - - - - - UA_IRCR - - UA_IRCR - UART IrDA Control Register - 0x28 - read-write - 0x00000040 - 0xFFFFFFFF - - - TX_SELECT - TX_SELECT\n - 1 - 1 - - - 0 - Enable IrDA receiver - #0 - - - 1 - Enable IrDA transmitter - #1 - - - read-write - - - INV_TX - INV_TX\n - 5 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse TX output signal - #1 - - - read-write - - - INV_RX - INV_RX\n - 6 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse RX input signal - #1 - - - read-write - - - - - UA_ALT_CSR - - UA_ALT_CSR - UART Alternate Control/Status Register - 0x2C - read-write - 0x00000000 - 0xFFFFFFFF - - - RS485_NMM - RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode. - 8 - 1 - - - 0 - RS-485 Normal Multi-drop Operation mode (NMM) Disabled - #0 - - - 1 - RS-485 Normal Multi-drop Operation mode (NMM) Enabled - #1 - - - read-write - - - RS485_AAD - RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. - 9 - 1 - - - 0 - RS-485 Auto Address Detection Operation mode (AAD) Disabled - #0 - - - 1 - RS-485 Auto Address Detection Operation mode (AAD) Enabled - #1 - - - read-write - - - RS485_AUD - RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. - 10 - 1 - - - 0 - RS-485 Auto Direction Operation mode (AUD) Disabled - #0 - - - 1 - RS-485 Auto Direction Operation mode (AUD) Enabled - #1 - - - read-write - - - RS485_ADD_EN - RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. - 15 - 1 - - - 0 - Address detection mode Disabled - #0 - - - 1 - Address detection mode Enabled - #1 - - - read-write - - - ADDR_MATCH - Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode. - 24 - 8 - read-write - - - - - UA_FUN_SEL - - UA_FUN_SEL - UART Function Select Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - FUN_SEL - Function Selection Enable\n - 0 - 2 - - - 0 - UART Function - #00 - - - 1 - Reserved - #01 - - - 2 - IrDA Function Enabled - #10 - - - 3 - RS-485 Function Enabled - #11 - - - read-write - - - - - - - UART1 - UART Register Map - UART - 0x40150000 - - - 0x0 - 0x34 - registers - - - - UA_RBR - - UA_RBR - UART Receive Buffer Register - 0x0 - read-only - 0x00000000 - 0x00000000 - - - RBR - Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). - 0 - 8 - read-only - - - - - UA_THR - UA_RBR - - UA_THR - UART Transmit Holding Register - 0x0 - write-only - 0x00000000 - 0x00000000 - - - THR - Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). - 0 - 8 - write-only - - - - - UA_IER - - UA_IER - UART Interrupt Enable Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - RDA_IEN - Receive Data Available Interrupt Enable.\n - 0 - 1 - - - 0 - INT_RDA Masked off - #0 - - - 1 - INT_RDA Enabled - #1 - - - read-write - - - THRE_IEN - Transmit Holding Register Empty Interrupt Enable\n - 1 - 1 - - - 0 - INT_THRE Masked off - #0 - - - 1 - INT_THRE Enabled - #1 - - - read-write - - - RLS_IEN - Receive Line Status Interrupt Enable \n - 2 - 1 - - - 0 - INT_RLS Masked off - #0 - - - 1 - INT_RLS Enabled - #1 - - - read-write - - - MODEM_IEN - Modem Status Interrupt Enable\n - 3 - 1 - - - 0 - INT_MODEM Masked off - #0 - - - 1 - INT_MODEM Enabled - #1 - - - read-write - - - RTO_IEN - RX Time Out Interrupt Enable\n - 4 - 1 - - - 0 - INT_TOUT Masked off - #0 - - - 1 - INT_TOUT Enabled - #1 - - - read-write - - - BUF_ERR_IEN - Buffer Error Interrupt Enable\n - 5 - 1 - - - 0 - INT_BUF_ERR Masked off - #0 - - - 1 - INT_BUF_ERR Enabled - #1 - - - read-write - - - WAKE_EN - UART Wake-up Function Enable\n - 6 - 1 - - - 0 - UART wake-up function Disabled - #0 - - - 1 - UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode - #1 - - - read-write - - - TIME_OUT_EN - Time Out Counter Enable\n - 11 - 1 - - - 0 - Time-out counter Disabled - #0 - - - 1 - Time-out counter Enabled - #1 - - - read-write - - - AUTO_RTS_EN - RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. - 12 - 1 - - - 0 - RTS auto flow control Disabled - #0 - - - 1 - RTS auto flow control Enabled - #1 - - - read-write - - - AUTO_CTS_EN - CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). - 13 - 1 - - - 0 - CTS auto flow control Disabled - #0 - - - 1 - CTS auto flow control Enabled - #1 - - - read-write - - - DMA_TX_EN - TX DMA Enable\nThis bit can enable or disable TX DMA service.\n - 14 - 1 - - - 0 - TX DMA Disabled - #0 - - - 1 - TX DMA Enabled - #1 - - - read-write - - - DMA_RX_EN - RX DMA Enable\nThis bit can enable or disable RX DMA service.\n - 15 - 1 - - - 0 - RX DMA Disabled - #0 - - - 1 - RX DMA Enabled - #1 - - - read-write - - - - - UA_FCR - - UA_FCR - UART FIFO Control Register - 0x8 - read-write - 0x00000101 - 0xFFFFFFFF - - - RFR - RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the RX internal state machine and pointers - #1 - - - read-write - - - TFR - TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. - 2 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the TX internal state machine and pointers - #1 - - - read-write - - - RFITL - RX FIFO Interrupt (INT_RDA) Trigger Level\n - 4 - 4 - read-write - - - RX_DIS - Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. - 8 - 1 - - - 0 - Receiver Enabled - #0 - - - 1 - Receiver Disabled - #1 - - - read-write - - - RTS_TRI_LEV - RTS Trigger Level for Auto-flow Control Use\n - 16 - 4 - read-write - - - - - UA_LCR - - UA_LCR - UART Line Control Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - WLS - Word Length Selection\n - 0 - 2 - read-write - - - NSB - Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected. - 2 - 1 - - - 0 - One " STOP bit" is generated in the transmitted data - #0 - - - 1 - One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; - #1 - - - read-write - - - PBE - Parity Bit Enable\n - 3 - 1 - - - 0 - No parity bit - #0 - - - 1 - Parity bit is generated on each outgoing character and is checked on each incoming data - #1 - - - read-write - - - EPE - Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. - 4 - 1 - - - 0 - Odd number of logic 1's is transmitted and checked in each word - #0 - - - 1 - Even number of logic 1's is transmitted and checked in each word - #1 - - - read-write - - - SPE - Stick Parity Enable\n - 5 - 1 - - - 0 - Stick parity Disabled - #0 - - - 1 - If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 - #1 - - - read-write - - - BCB - Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. - 6 - 1 - read-write - - - - - UA_MCR - - UA_MCR - UART Modem Control Register - 0x10 - read-write - 0x00000200 - 0xFFFFFFFF - - - RTS - RTS (Request-To-Send) Signal\n - 1 - 1 - - - 0 - Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) - #0 - - - 1 - Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) - #1 - - - read-write - - - LEV_RTS - RTS Trigger Level\nThis bit can change the RTS trigger level.\n - 9 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - RTS_ST - RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. - 13 - 1 - read-only - - - - - UA_MSR - - UA_MSR - UART Modem Status Register - 0x14 - read-write - 0x00000110 - 0xFFFFFFFF - - - DCTSF - Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - read-only - - - CTS_ST - CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. - 4 - 1 - read-only - - - LEV_CTS - CTS Trigger Level\nThis bit can change the CTS trigger level.\n - 8 - 1 - - - 0 - Low level triggered - #0 - - - 1 - High level triggered - #1 - - - read-write - - - - - UA_FSR - - UA_FSR - UART FIFO Status Register - 0x18 - read-write - 0x10404000 - 0xFFFFFFFF - - - RX_OVER_IF - RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 0 - 1 - read-only - - - RS485_ADD_DETF - RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 3 - 1 - read-only - - - PEF - Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 4 - 1 - read-only - - - FEF - Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 5 - 1 - read-only - - - BIF - Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. - 6 - 1 - read-only - - - RX_POINTER - RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. - 8 - 6 - read-only - - - RX_EMPTY - Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. - 14 - 1 - read-only - - - RX_FULL - Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 15 - 1 - read-only - - - TX_POINTER - TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. - 16 - 6 - read-only - - - TX_EMPTY - Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). - 22 - 1 - read-only - - - TX_FULL - Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. - 23 - 1 - read-only - - - TX_OVER_IF - TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. - 24 - 1 - read-only - - - TE_FLAG - Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. - 28 - 1 - read-only - - - - - UA_ISR - - UA_ISR - UART Interrupt Status Register - 0x1C - read-write - 0x00000002 - 0xFFFFFFFF - - - RDA_IF - Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). - 0 - 1 - read-only - - - THRE_IF - Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). - 1 - 1 - read-only - - - RLS_IF - Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 2 - 1 - read-only - - - MODEM_IF - MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 3 - 1 - read-only - - - TOUT_IF - Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 4 - 1 - read-only - - - BUF_ERR_IF - Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 5 - 1 - read-only - - - RDA_INT - Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n - 8 - 1 - - - 0 - No RDA interrupt is generated - #0 - - - 1 - RDA interrupt is generated - #1 - - - read-only - - - THRE_INT - Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n - 9 - 1 - - - 0 - No THRE interrupt is generated - #0 - - - 1 - THRE interrupt is generated - #1 - - - read-only - - - RLS_INT - Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n - 10 - 1 - - - 0 - No RLS interrupt is generated - #0 - - - 1 - RLS interrupt is generated - #1 - - - read-only - - - MODEM_INT - MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n - 11 - 1 - - - 0 - No Modem interrupt is generated - #0 - - - 1 - Modem interrupt is generated - #1 - - - read-only - - - TOUT_INT - Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n - 12 - 1 - - - 0 - No Tout interrupt is generated - #0 - - - 1 - Tout interrupt is generated - #1 - - - read-only - - - BUF_ERR_INT - Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n - 13 - 1 - - - 0 - No buffer error interrupt is generated - #0 - - - 1 - Buffer error interrupt is generated - #1 - - - read-only - - - HW_RLS_IF - In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. - 18 - 1 - read-only - - - HW_MODEM_IF - In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. - 19 - 1 - read-only - - - HW_TOUT_IF - In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. - 20 - 1 - read-only - - - HW_BUF_ERR_IF - In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. - 21 - 1 - read-only - - - HW_RLS_INT - In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n - 26 - 1 - - - 0 - No RLS interrupt is generated in DMA mode - #0 - - - 1 - RLS interrupt is generated in DMA mode - #1 - - - read-only - - - HW_MODEM_INT - In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n - 27 - 1 - - - 0 - No Modem interrupt is generated in DMA mode - #0 - - - 1 - Modem interrupt is generated in DMA mode - #1 - - - read-only - - - HW_TOUT_INT - In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n - 28 - 1 - - - 0 - No Tout interrupt is generated in DMA mode - #0 - - - 1 - Tout interrupt is generated in DMA mode - #1 - - - read-only - - - HW_BUF_ERR_INT - In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n - 29 - 1 - - - 0 - No buffer error interrupt is generated in DMA mode - #0 - - - 1 - Buffer error interrupt is generated in DMA mode - #1 - - - read-only - - - - - UA_TOR - - UA_TOR - UART Time Out Register - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - TOIC - Time Out Interrupt Comparator\n - 0 - 8 - read-write - - - DLY - TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. - 8 - 8 - read-write - - - - - UA_BAUD - - UA_BAUD - UART Baud Rate Divisor Register - 0x24 - read-write - 0x0F000000 - 0xFFFFFFFF - - - BRD - Baud Rate Divider\nThe field indicates the baud rate divider. - 0 - 16 - read-write - - - DIVIDER_X - Divider X\n - 24 - 4 - read-write - - - DIV_X_ONE - Divider X Equal to 1\nRefer to the Table 515 below for more information. - 28 - 1 - - - 0 - Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) - #0 - - - 1 - Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) - #1 - - - read-write - - - DIV_X_EN - Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled. - 29 - 1 - - - 0 - Divider X Disabled (the equation of M = 16) - #0 - - - 1 - Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) - #1 - - - read-write - - - - - UA_IRCR - - UA_IRCR - UART IrDA Control Register - 0x28 - read-write - 0x00000040 - 0xFFFFFFFF - - - TX_SELECT - TX_SELECT\n - 1 - 1 - - - 0 - Enable IrDA receiver - #0 - - - 1 - Enable IrDA transmitter - #1 - - - read-write - - - INV_TX - INV_TX\n - 5 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse TX output signal - #1 - - - read-write - - - INV_RX - INV_RX\n - 6 - 1 - - - 0 - No inversion - #0 - - - 1 - Inverse RX input signal - #1 - - - read-write - - - - - UA_ALT_CSR - - UA_ALT_CSR - UART Alternate Control/Status Register - 0x2C - read-write - 0x00000000 - 0xFFFFFFFF - - - RS485_NMM - RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode. - 8 - 1 - - - 0 - RS-485 Normal Multi-drop Operation mode (NMM) Disabled - #0 - - - 1 - RS-485 Normal Multi-drop Operation mode (NMM) Enabled - #1 - - - read-write - - - RS485_AAD - RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. - 9 - 1 - - - 0 - RS-485 Auto Address Detection Operation mode (AAD) Disabled - #0 - - - 1 - RS-485 Auto Address Detection Operation mode (AAD) Enabled - #1 - - - read-write - - - RS485_AUD - RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. - 10 - 1 - - - 0 - RS-485 Auto Direction Operation mode (AUD) Disabled - #0 - - - 1 - RS-485 Auto Direction Operation mode (AUD) Enabled - #1 - - - read-write - - - RS485_ADD_EN - RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. - 15 - 1 - - - 0 - Address detection mode Disabled - #0 - - - 1 - Address detection mode Enabled - #1 - - - read-write - - - ADDR_MATCH - Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode. - 24 - 8 - read-write - - - - - UA_FUN_SEL - - UA_FUN_SEL - UART Function Select Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - FUN_SEL - Function Selection Enable\n - 0 - 2 - - - 0 - UART Function - #00 - - - 1 - Reserved - #01 - - - 2 - IrDA Function Enabled - #10 - - - 3 - RS-485 Function Enabled - #11 - - - read-write - - - - - - - PS2 - PS2 Register Map - PS2 - 0x40100000 - - - 0x0 - 0x20 - registers - - - - PS2CON - - PS2CON - PS/2 Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PS2EN - Enable PS/2 Device\nEnable PS/2 device controller.\n - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - TXINTEN - Enable Transmit Interrupt\n - 1 - 1 - - - 0 - Data transmit complete interrupt Disabled - #0 - - - 1 - Data transmit complete interrupt Enabled - #1 - - - read-write - - - RXINTEN - Enable Receive Interrupt\n - 2 - 1 - - - 0 - Data receive complete interrupt Disabled - #0 - - - 1 - Data receive complete interrupt Enabled - #1 - - - read-write - - - TXFIFODIPTH - Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application.\n - 3 - 4 - - - 0 - 1 byte - 0 - - - 1 - 2 bytes - 1 - - - 14 - 15 bytes - 14 - - - 15 - 16 bytes - 15 - - - read-write - - - ACK - Acknowledge Enable\n - 7 - 1 - - - 0 - Always sends acknowledge to host at 12th clock for host to device communication - #0 - - - 1 - If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock - #1 - - - read-write - - - CLRFIFO - Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n - 8 - 1 - - - 0 - Not active - #0 - - - 1 - Clear FIFO - #1 - - - read-write - - - OVERRIDE - Software Override PS/2 CLK/DATA Pin State\n - 9 - 1 - - - 0 - PS2CLK and PS2DATA pins are controlled by internal state machine - #0 - - - 1 - PS2CLK and PS2DATA pins are controlled by software - #1 - - - read-write - - - FPS2CLK - Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n - 10 - 1 - - - 0 - Force PS2CLK line low - #0 - - - 1 - Force PS2CLK line high - #1 - - - read-write - - - FPS2DAT - Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n - 11 - 1 - - - 0 - Force PS2DATA low - #0 - - - 1 - Force PS2DATA high - #1 - - - read-write - - - - - PS2TXDATA0 - - PS2TXDATA0 - PS/2 Transmit Data Register 0 - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PS2TXDATAx - Transmit data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer. - 0 - 32 - read-write - - - - - PS2TXDATA1 - PS2TXDATA1 - PS/2 Transmit Data Register 1 - 0x8 - - - PS2TXDATA2 - PS2TXDATA2 - PS/2 Transmit Data Register 2 - 0xC - - - PS2TXDATA3 - PS2TXDATA3 - PS/2 Transmit Data Register 3 - 0x10 - - - PS2RXDATA - - PS2RXDATA - PS/2 Receive Data Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PS2RXDATA - Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1. - 0 - 8 - read-only - - - - - PS2STATUS - - PS2STATUS - PS/2 Status Register - 0x18 - read-write - 0x00000083 - 0xFFFFFFFF - - - PS2CLK - CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing. - 0 - 1 - read-write - - - PS2DATA - DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling. - 1 - 1 - read-write - - - FRAMERR - Frame Error\nFor host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a "Resend" command to host.\nWrite 1 to clear this bit. - 2 - 1 - - - 0 - No frame error - #0 - - - 1 - Frame error occurred - #1 - - - read-write - - - RXPARITY - Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit. - 3 - 1 - read-write - - - RXBUSY - Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit. - 4 - 1 - - - 0 - Idle - #0 - - - 1 - Currently receiving data - #1 - - - read-write - - - TXBUSY - Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit. - 5 - 1 - - - 0 - Idle - #0 - - - 1 - Currently sending data - #1 - - - read-write - - - RXOVF - RX Buffer Overwrite\nWrite 1 to clear this bit. - 6 - 1 - - - 0 - No overwrite - #0 - - - 1 - Data in PS2RXDATA register is overwritten by new received data - #1 - - - read-write - - - TXEMPTY - TX FIFO Empty\nWhen software writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit. - 7 - 1 - - - 0 - There is data to be transmitted - #0 - - - 1 - FIFO is empty - #1 - - - read-write - - - BYTEIDX - Byte Index\n - 8 - 4 - read-write - - - - - PS2INTID - - PS2INTID - PS/2 Interrupt Identification Register - 0x1C - read-write - 0x00000000 - 0xFFFFFFFF - - - RXINT - Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. - 0 - 1 - - - 0 - No interrupt - #0 - - - 1 - Receive interrupt occurs - #1 - - - read-write - - - TXINT - Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. - 1 - 1 - - - 0 - No interrupt - #0 - - - 1 - Transmit interrupt occurs - #1 - - - read-write - - - - - - - I2S - I2S Register Map - I2S - 0x401A0000 - - - 0x0 - 0x18 - registers - - - - I2S_CON - - I2S_CON - I2S Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - I2SEN - I2S Controller Enable\n - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - TXEN - Transmit enable\n - 1 - 1 - - - 0 - Data transmission Disabled - #0 - - - 1 - Data transmission Enabled - #1 - - - read-write - - - RXEN - Receive enable\n - 2 - 1 - - - 0 - Data receiving Disabled - #0 - - - 1 - Data receiving Enabled - #1 - - - read-write - - - MUTE - Transmit Mute Enable\n - 3 - 1 - - - 0 - Transmit data is shifted from buffer - #0 - - - 1 - Transmit channel zero - #1 - - - read-write - - - WORDWIDTH - Word Width\n - 4 - 2 - - - 0 - Data is 8-bit - #00 - - - 1 - Data is 16-bit - #01 - - - 2 - Data is 24-bit - #10 - - - 3 - Data is 32-bit - #11 - - - read-write - - - MONO - Monaural Data\n - 6 - 1 - - - 0 - Data is stereo format - #0 - - - 1 - Data is monaural format - #1 - - - read-write - - - FORMAT - Data format Selection\n - 7 - 1 - - - 0 - I2S data format\nPCM mode A - #0 - - - 1 - MSB justified data format\nPCM mode B - #1 - - - read-write - - - SLAVE - Slave mode\nI2S can be operated as Master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC123 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n - 8 - 1 - - - 0 - Master mode - #0 - - - 1 - Slave mode - #1 - - - read-write - - - TXTH - Transmit FIFO threshold level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level, the TXTHF flag is set.\n - 9 - 3 - - - 0 - 0 word data in transmit FIFO - #000 - - - 1 - 1 word data in transmit FIFO - #001 - - - 2 - 2 words data in transmit FIFO - #010 - - - 3 - 3 words data in transmit FIFO - #011 - - - 4 - 4 words data in transmit FIFO - #100 - - - 5 - 5 words data in transmit FIFO - #101 - - - 6 - 6 words data in transmit FIFO - #110 - - - 7 - 7 words data in transmit FIFO - #111 - - - read-write - - - RXTH - Receive FIFO threshold level\nWhen received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set.\n - 12 - 3 - - - 0 - 1 word data in receive FIFO - #000 - - - 1 - 2 word data in receive FIFO - #001 - - - 2 - 3 word data in receive FIFO - #010 - - - 3 - 4 word data in receive FIFO - #011 - - - 4 - 5 word data in receive FIFO - #100 - - - 5 - 6 word data in receive FIFO - #101 - - - 6 - 7 word data in receive FIFO - #110 - - - 7 - 8 word data in receive FIFO - #111 - - - read-write - - - MCLKEN - Master clock enable\nFor NuMicro( NUC123 series, if the external crystal clock is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip.\n - 15 - 1 - - - 0 - Master clock Disabled - #0 - - - 1 - Master clock Enabled - #1 - - - read-write - - - RCHZCEN - Right Channel Zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n - 16 - 1 - - - 0 - Right channel zero-cross detect Disabled - #0 - - - 1 - Right channel zero-cross detect Enabled - #1 - - - read-write - - - LCHZCEN - Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n - 17 - 1 - - - 0 - Left channel zero-cross detect Disabled - #0 - - - 1 - Left channel zero-cross detect Enabled - #1 - - - read-write - - - CLR_TXFIFO - Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically, reading it returns zero. - 18 - 1 - read-write - - - CLR_RXFIFO - Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, reading it returns zero. - 19 - 1 - read-write - - - TXDMA - Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n - 20 - 1 - - - 0 - TX DMA Disabled - #0 - - - 1 - TX DMA Enabled - #1 - - - read-write - - - RXDMA - Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n - 21 - 1 - - - 0 - RX DMA Disabled - #0 - - - 1 - RX DMA Enabled - #1 - - - read-write - - - RXLCH - Receive Left Channel Enable\n - 23 - 1 - - - 0 - Receives right channel data when monaural format is selected - #0 - - - 1 - Receives left channel data when monaural format is selected - #1 - - - read-write - - - PCM - PCM Interface Enable\n - 24 - 1 - - - 0 - I2S Interface - #0 - - - 1 - PCM interface - #1 - - - read-write - - - - - I2S_CLKDIV - - I2S_CLKDIV - I2S Clock Divider Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - MCLK_DIV - Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input.\n - 0 - 3 - read-write - - - BCLK_DIV - Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by NuMicro( NUC123 series. Software can program these bits to generate sampling rate clock frequency.\n - 8 - 8 - read-write - - - - - I2S_IE - - I2S_IE - I2S Interrupt Enable Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - RXUDFIE - Receive FIFO Underflow Interrupt Enable\nIf software reads the received FIFO when it is empty, RXUDF flag in I2SSTATUS register is set to 1.\n - 0 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - RXOVFIE - Receive FIFO Overflow Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - RXTHIE - Received FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs.\n - 2 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - TXUDFIE - Transmitted FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO underflow flag is set to 1.\n - 8 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - TXOVFIE - Transmitted FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO overflow flag is set to 1.\n - 9 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - TXTHIE - Transmitted FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO are less than TXTH[2:0].\n - 10 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - RZCIE - Right Channel Zero-cross Interrupt Enable\n - 11 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - LZCIE - Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n - 12 - 1 - - - 0 - Interrupt Disabled - #0 - - - 1 - Interrupt Enabled - #1 - - - read-write - - - - - I2S_STATUS - - I2S_STATUS - I2S Status Register - 0xC - read-write - 0x00141000 - 0xFFFFFFFF - - - I2SINT - I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only. - 0 - 1 - - - 0 - No I2S interrupt - #0 - - - 1 - I2S interrupt - #1 - - - read-write - - - I2SRXINT - I2S Receive Interrupt\nThis bit is read only. - 1 - 1 - - - 0 - No receive interrupt - #0 - - - 1 - Receive interrupt - #1 - - - read-write - - - I2STXINT - I2S Transmit Interrupt\nThis bit is read only. - 2 - 1 - - - 0 - No transmit interrupt - #0 - - - 1 - Transmit interrupt - #1 - - - read-write - - - RIGHT - Right Channel\nThis bit indicates the current transmit data is belong to right channel.\nThis bit is read only. - 3 - 1 - - - 0 - Left channel - #0 - - - 1 - Right channel - #1 - - - read-write - - - RXUDF - Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nSoftware can write 1 to clear this bit to zero. - 8 - 1 - - - 0 - No underflow occurred - #0 - - - 1 - Underflow occurred - #1 - - - read-write - - - RXOVF - Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nSoftware can write 1 to clear this bit to zero. - 9 - 1 - - - 0 - No overflow occurred - #0 - - - 1 - Overflow occurred - #1 - - - read-write - - - RXTHF - Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only. - 10 - 1 - - - 0 - Data word(s) in FIFO is lower than threshold level - #0 - - - 1 - Data word(s) in FIFO is equal or higher than threshold level - #1 - - - read-write - - - RXFULL - Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8.\nThis bit is read only. - 11 - 1 - - - 0 - Not full - #0 - - - 1 - Full - #1 - - - read-write - - - RXEMPTY - Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero.\nThis bit is read only. - 12 - 1 - - - 0 - Not empty - #0 - - - 1 - Empty - #1 - - - read-write - - - TXUDF - Transmit FIFO underflow flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to zero - 16 - 1 - - - 0 - No underflow - #0 - - - 1 - Underflow - #1 - - - read-write - - - TXOVF - Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1.\nSoftware can write 1 to clear this bit to zero. - 17 - 1 - - - 0 - No overflow - #0 - - - 1 - Overflow - #1 - - - read-write - - - TXTHF - Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only. - 18 - 1 - - - 0 - Data word(s) in FIFO is higher than threshold level - #0 - - - 1 - Data word(s) in FIFO is equal or lower than threshold level - #1 - - - read-write - - - TXFULL - Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8.\nThis bit is read only - 19 - 1 - - - 0 - Not full - #0 - - - 1 - Full - #1 - - - read-write - - - TXEMPTY - Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero.\nThis bit is read only. - 20 - 1 - - - 0 - Not empty - #0 - - - 1 - Empty - #1 - - - read-write - - - TXBUSY - Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out, and set to 1 when the 1st data is load to shift buffer. \nThis bit is read only. - 21 - 1 - - - 0 - Transmit shift buffer is empty - #0 - - - 1 - Transmit shift buffer is busy - #1 - - - read-write - - - RZCF - Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero. - 22 - 1 - - - 0 - No zero-cross - #0 - - - 1 - Right channel zero-cross is detected - #1 - - - read-write - - - LZCF - Left Channel Zero-cross Flag\nIt indicates left channel next the sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero - 23 - 1 - - - 0 - No zero-cross - #0 - - - 1 - Left channel zero-cross is detected - #1 - - - read-write - - - RX_LEVEL - Receive FIFO Level\nThese bits indicate word number in receive FIFO.\n - 24 - 4 - - - 0 - No data - #0000 - - - 1 - 1 word in receive FIFO - #0001 - - - 8 - 8 words in receive FIFO - #1000 - - - read-write - - - TX_LEVEL - Transmit FIFO Level\nThese bits indicate word number in transmit FIFO.\n - 28 - 4 - - - 0 - No data - #0000 - - - 1 - 1 word in transmit FIFO - #0001 - - - 8 - 8 words in transmit FIFO - #1000 - - - read-write - - - - - I2S_TXFIFO - - I2S_TXFIFO - I2S Transmit FIFO Register - 0x10 - read-write - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - Transmit FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data transmission. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2S_STATUS. - 0 - 32 - read-write - - - - - I2S_RXFIFO - - I2S_RXFIFO - I2S Receive FIFO Register - 0x14 - read-write - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2S_STATUS register. - 0 - 32 - read-write - - - - - - - ADC - ADC Register Map - ADC - 0x400E0000 - - - 0x0 - 0x34 - registers - - - 0x40 - 0x4 - registers - - - - ADDR0 - - ADDR0 - A/D Data Register 0 - 0x0 - read-only - 0x00000000 - 0xFFFFFFFF - - - RSLT - A/D Conversion Result\nThis field contains 10 bits conversion result of ADC. - 0 - 16 - read-only - - - OVERRUN - Over Run Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit. - 16 - 1 - - - 0 - Data in RSLT[15:0] is recent conversion result - #0 - - - 1 - Data in RSLT[15:0] is overwritten - #1 - - - read-only - - - VALID - Valid Flag\nThis bit is set to 1 when the corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit. - 17 - 1 - - - 0 - Data in RSLT[15:0] bits is not valid - #0 - - - 1 - Data in RSLT[15:0] bits is valid - #1 - - - read-only - - - - - ADDR1 - ADDR1 - A/D Data Register 1 - 0x4 - - - ADDR2 - ADDR2 - A/D Data Register 2 - 0x8 - - - ADDR3 - ADDR3 - A/D Data Register 3 - 0xC - - - ADDR4 - ADDR4 - A/D Data Register 4 - 0x10 - - - ADDR5 - ADDR5 - A/D Data Register 5 - 0x14 - - - ADDR6 - ADDR6 - A/D Data Register 6 - 0x18 - - - ADDR7 - ADDR7 - A/D Data Register 7 - 0x1C - - - ADCR - - ADCR - A/D Control Register - 0x20 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADEN - A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption. - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - ADIE - A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1. - 1 - 1 - - - 0 - A/D interrupt function Disabled - #0 - - - 1 - A/D interrupt function Enabled - #1 - - - read-write - - - ADMD - A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit firstly. - 2 - 2 - - - 0 - Single conversion - #00 - - - 1 - Reserved - #01 - - - 2 - Single-cycle scan - #10 - - - 3 - Continuous scan - #11 - - - read-write - - - TRGS - Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC. - 4 - 2 - - - 0 - A/D conversion is started by external STADC pin.\nA/D conversion is started by PWM center-aligned trigger - #00 - - - read-write - - - TRGCOND - External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n - 6 - 2 - - - 0 - Low level - #00 - - - 1 - High level - #01 - - - 2 - Falling edge - #10 - - - 3 - Rising edge - #11 - - - read-write - - - TRGEN - External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in Single-cycle Scan mode. - 8 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PTEN - PDMA Transfer Enable\n - 9 - 1 - - - 0 - PDMA data transfer Disabled - #0 - - - 1 - PDMA data transfer in ADDR 0~7 Enabled - #1 - - - read-write - - - ADST - A/D Conversion Start\nADST bit can be set to 1 from three sources: software and external pin STADC, and pwm output. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset. - 11 - 1 - - - 0 - Conversion stopped and A/D converter entering Idle state - #0 - - - 1 - Conversion started - #1 - - - read-write - - - - - ADCHER - - ADCHER - A/D Channel Enable Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - CHEN0 - Analog Input Channel 0 Enable\n - 0 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN1 - Analog Input Channel 1 Enable\n - 1 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN2 - Analog Input Channel 2 Enable\n - 2 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN3 - Analog Input Channel 3 Enable\n - 3 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN4 - Analog Input Channel 4 Enable\n - 4 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN5 - Analog Input Channel 5 Enable\n - 5 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN6 - Analog Input Channel 6 Enable\n - 6 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CHEN7 - Analog Input Channel 7 Enable\n - 7 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - PRESEL - Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 kHz. - 8 - 1 - - - 0 - External analog input - #0 - - - 1 - Internal band-gap voltage - #1 - - - read-write - - - - - ADCMPR0 - - ADCMPR0 - A/D Compare Register 0 - 0x28 - read-write - 0x00000000 - 0xFFFFFFFF - - - CMPEN - Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register. - 0 - 1 - - - 0 - Compare function Disabled - #0 - - - 1 - Compare function Enabled - #1 - - - read-write - - - CMPIE - Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. - 1 - 1 - - - 0 - Compare function interrupt Disabled - #0 - - - 1 - Compare function interrupt Enabled - #1 - - - read-write - - - CMPCOND - Compare Conditions\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. - 2 - 1 - - - 0 - Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one - #0 - - - 1 - Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one - #1 - - - read-write - - - CMPCH - Compare Channel Selection\n - 3 - 3 - - - 0 - Channel 0 conversion result is selected to be compared - #000 - - - 1 - Channel 1 conversion result is selected to be compared - #001 - - - 2 - Channel 2 conversion result is selected to be compared - #010 - - - 3 - Channel 3 conversion result is selected to be compared - #011 - - - 4 - Channel 4 conversion result is selected to be compared - #100 - - - 5 - Channel 5 conversion result is selected to be compared - #101 - - - 6 - Channel 6 conversion result is selected to be compared - #110 - - - 7 - Channel 7 conversion result is selected to be compared - #111 - - - read-write - - - CMPMATCNT - Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. - 8 - 4 - read-write - - - CMPD - Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format. - 16 - 12 - read-write - - - - - ADCMPR1 - ADCMPR1 - A/D Compare Register 1 - 0x2C - - - ADSR - - ADSR - A/D Status Register - 0x30 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADF - A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself. - 0 - 1 - read-write - - - CMPF0 - Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to itself.\n - 1 - 1 - - - 0 - Conversion result in ADDR does not meet ADCMPR0 setting - #0 - - - 1 - Conversion result in ADDR meets ADCMPR0 setting - #1 - - - read-write - - - CMPF1 - Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. It is cleared by writing 1 to itself.\n - 2 - 1 - - - 0 - Conversion result in ADDR does not meet ADCMPR1 setting - #0 - - - 1 - Conversion result in ADDR meets ADCMPR1 setting - #1 - - - read-write - - - BUSY - BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only. - 3 - 1 - - - 0 - A/D converter is in Idle state - #0 - - - 1 - A/D converter is busy at conversion - #1 - - - read-write - - - CHANNEL - Current Conversion Channel\nIt is read only. - 4 - 3 - read-write - - - VALID - Data Valid flag\nIt is a mirror of VALID bit in ADDRx.\nIt is read only. - 8 - 8 - read-write - - - OVERRUN - Over Run Flag\nIt is a mirror to OVERRUN bit in ADDRx.\nIt is read only. - 16 - 8 - read-write - - - - - ADPDMA - - ADPDMA - ADC PDMA current transfer data - 0x40 - read-only - 0x00000000 - 0xFFFFFFFF - - - AD_PDMA - ADC PDMA current transfer data register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nThis is a read only register. - 0 - 10 - read-only - - - - - - - PDMA_ch0 - PDMA Register Map - PDMA - 0x50008000 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection\n - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection\n - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection\n - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal buffer pointer - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch1 - PDMA Register Map - PDMA - 0x50008100 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection\n - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection\n - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection\n - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal buffer pointer - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch2 - PDMA Register Map - PDMA - 0x50008200 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection\n - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection\n - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection\n - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal buffer pointer - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch3 - PDMA Register Map - PDMA - 0x50008300 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection\n - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection\n - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection\n - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal buffer pointer - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch4 - PDMA Register Map - PDMA - 0x50008400 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection\n - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection\n - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection\n - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal buffer pointer - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - PDMA_ch5 - PDMA Register Map - PDMA - 0x50008500 - - - 0x0 - 0x28 - registers - - - 0x80 - 0x4 - registers - - - - PDMA_CSRx - - PDMA_CSRx - PDMA Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMACEN - PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. - 0 - 1 - read-write - - - SW_RST - Software Engine Reset\n - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles - #1 - - - read-write - - - MODE_SEL - PDMA Mode Selection\n - 2 - 2 - - - 0 - Memory to Memory mode (Memory-to-Memory) - #00 - - - 1 - Peripheral to Memory mode (Peripheral-to-Memory) - #01 - - - 2 - Memory to Peripheral mode (Memory-to-Peripheral) - #10 - - - read-write - - - SAD_SEL - Transfer Source Address Direction Selection\n - 4 - 2 - - - 0 - Transfer source address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) - #10 - - - 3 - Reserved - #11 - - - read-write - - - DAD_SEL - Transfer Destination Address Direction Selection\n - 6 - 2 - - - 0 - Transfer destination address is increasing successively - #00 - - - 1 - Reserved - #01 - - - 2 - Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) - #10 - - - 3 - Reserved - #11 - - - read-write - - - APB_TWS - Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). - 19 - 2 - - - 0 - One word (32-bit) is transferred for every PDMA operation - #00 - - - 1 - One byte (8-bit) is transferred for every PDMA operation - #01 - - - 2 - One half-word (16-bit) is transferred for every PDMA operation - #10 - - - 3 - Reserved - #11 - - - read-write - - - TRIG_EN - TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - PDMA data read or write transfer Enabled - #1 - - - read-write - - - - - PDMA_SARx - - PDMA_SARx - PDMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_SAR - PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_DARx - - PDMA_DARx - PDMA Destination Address Register - 0x8 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_DAR - PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. - 0 - 32 - read-write - - - - - PDMA_BCRx - - PDMA_BCRx - PDMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - PDMA_BCR - PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. - 0 - 16 - read-write - - - - - PDMA_POINTx - - PDMA_POINTx - PDMA Internal buffer pointer - 0x10 - read-only - 0x00000000 - 0x0000FFFF - - - PDMA_POINT - PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. - 0 - 2 - read-only - - - - - PDMA_CSARx - - PDMA_CSARx - PDMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CSAR - PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CDARx - - PDMA_CDARx - PDMA Current Destination Address Register - 0x18 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CDAR - PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. - 0 - 32 - read-only - - - - - PDMA_CBCRx - - PDMA_CBCRx - PDMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_CBCR - PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. - 0 - 16 - read-only - - - - - PDMA_IERx - - PDMA_IERx - PDMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - PDMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during PDMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during PDMA transfer - #1 - - - read-write - - - BLKD_IE - PDMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when PDMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when PDMA transfer is done - #1 - - - read-write - - - - - PDMA_ISRx - - PDMA_ISRx - PDMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - PDMA_SBUF_cx - - PDMA_SBUF_cx - PDMA Shared Buffer FIFO - 0x80 - read-only - 0x00000000 - 0xFFFFFFFF - - - PDMA_SBUF - PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. - 0 - 32 - read-only - - - - - - - CRC - PDMA Register Map - PDMA - 0x50008E00 - - - 0x0 - 0x8 - registers - - - 0xC - 0x4 - registers - - - 0x14 - 0x4 - registers - - - 0x1C - 0xC - registers - - - 0x80 - 0xC - registers - - - - CRC_CTL - - CRC_CTL - CRC Control Register - 0x0 - read-write - 0x20000000 - 0xFFFFFFFF - - - CRCCEN - CRC Channel Enable\nSetting this bit to 1 enables CRC's operation.\n - 0 - 1 - read-write - - - CRC_RST - CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value. - 1 - 1 - - - 0 - No effect - #0 - - - 1 - Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles - #1 - - - read-write - - - TRIG_EN - TRIG_EN\nNote1: If this bit assert indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer is completed, this bit will be cleared automatically.\nNote3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again. - 23 - 1 - - - 0 - No effect - #0 - - - 1 - CRC DMA data read or write transfer Enabled - #1 - - - read-write - - - WDATA_RVS - Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB - 24 - 1 - - - 0 - No bit order reversed for CRC write data in - #0 - - - 1 - Bit order reversed for CRC write data in (per byte) - #1 - - - read-write - - - CHECKSUM_RVS - Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB. - 25 - 1 - - - 0 - No bit order reverse for CRC checksum - #0 - - - 1 - Bit order reverse for CRC checksum - #1 - - - read-write - - - WDATA_COM - Write Data Complement\n - 26 - 1 - - - 0 - No 1's complement for CRC write data in - #0 - - - 1 - 1's complement for CRC write data in - #1 - - - read-write - - - CHECKSUM_COM - Checksum Complement\n - 27 - 1 - - - 0 - No 1's complement for CRC checksum - #0 - - - 1 - 1's complement for CRC checksum - #1 - - - read-write - - - CPU_WDLEN - CPU Write Data Length\nNote1: This field is used for CPU PIO mode.\nNote2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0]; if the data length is 16-bit mode, the valid data is CRC_WDATA [15:0]. - 28 - 2 - - - 0 - Data length is 8-bit mode - #00 - - - 1 - Data length is 16-bit mode\nData length is 32-bit mode - #01 - - - read-write - - - CRC_MODE - CRC Polynomial Mode\n - 30 - 2 - - - 0 - CRC-CCITT Polynomial mode - #00 - - - 1 - CRC-8 Polynomial mode - #01 - - - 2 - CRC-16 Polynomial mode - #10 - - - 3 - CRC-32 Polynomial mode - #11 - - - read-write - - - - - CRC_DMASAR - - CRC_DMASAR - CRC DMA Source Address Register - 0x4 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRC_DMASAR - CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment. - 0 - 32 - read-write - - - - - CRC_DMABCR - - CRC_DMABCR - CRC DMA Transfer Byte Count Register - 0xC - read-write - 0x00000000 - 0xFFFFFFFF - - - CRC_DMABCR - CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA. - 0 - 16 - read-write - - - - - CRC_DMACSAR - - CRC_DMACSAR - CRC DMA Current Source Address Register - 0x14 - read-only - 0x00000000 - 0xFFFFFFFF - - - CRC_DMACSAR - CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer just occurs. - 0 - 32 - read-only - - - - - CRC_DMACBCR - - CRC_DMACBCR - CRC DMA Current Transfer Byte Count Register - 0x1C - read-only - 0x00000000 - 0xFFFFFFFF - - - CRC_DMACBCR - CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value. - 0 - 16 - read-only - - - - - CRC_DMAIER - - CRC_DMAIER - CRC DMA Interrupt Enable Register - 0x20 - read-write - 0x00000001 - 0xFFFFFFFF - - - TABORT_IE - CRC DMA Read/Write Target Abort Interrupt Enable\n - 0 - 1 - - - 0 - Target abort interrupt generation Disabled during CRC DMA transfer - #0 - - - 1 - Target abort interrupt generation Enabled during CRC DMA transfer - #1 - - - read-write - - - BLKD_IE - CRC DMA Transfer Done Interrupt Enable\n - 1 - 1 - - - 0 - Interrupt generator Disabled when CRC DMA transfer is done - #0 - - - 1 - Interrupt generator Enabled when CRC DMA transfer is done - #1 - - - read-write - - - - - CRC_DMAISR - - CRC_DMAISR - CRC DMA Interrupt Status Register - 0x24 - read-write - 0x00000000 - 0xFFFFFFFF - - - TABORT_IF - CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. - 0 - 1 - - - 0 - No bus ERROR response received - #0 - - - 1 - Bus ERROR response received - #1 - - - read-write - - - BLKD_IF - Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. - 1 - 1 - - - 0 - Not finished - #0 - - - 1 - Done - #1 - - - read-write - - - - - CRC_WDATA - - CRC_WDATA - CRC Write Data Register - 0x80 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRC_WDATA - CRC Write Data Register\n - 0 - 32 - read-write - - - - - CRC_SEED - - CRC_SEED - CRC Seed Register - 0x84 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - CRC_SEED - CRC Seed Register\nThis field indicates the CRC seed value. - 0 - 32 - read-write - - - - - CRC_CHECKSUM - - CRC_CHECKSUM - CRC Checksum Register - 0x88 - read-only - 0x00000000 - 0xFFFFFFFF - - - CRC_CHECKSUM - CRC Checksum Register\nThis field indicates the CRC checksum. - 0 - 32 - read-only - - - - - - - DMA_GCR - PDMA Register Map - PDMA - 0x50008F00 - - - 0x0 - 0x14 - registers - - - - DMA_GCRCSR - - DMA_GCRCSR - DMA Global Control Register - 0x0 - read-write - 0x00000000 - 0xFFFFFFFF - - - CLK0_EN - PDMA Controller Channel 0 Clock Enable Control\n - 8 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK1_EN - PDMA Controller Channel 1 Clock Enable Control\n - 9 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK2_EN - PDMA Controller Channel 2 Clock Enable Control \n - 10 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK3_EN - PDMA Controller Channel 3 Clock Enable Control\n - 11 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK4_EN - PDMA Controller Channel 4 Clock Enable Control\n - 12 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CLK5_EN - PDMA Controller Channel 5 Clock Enable Control\n - 13 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - CRC_CLK_EN - CRC Controller Clock Enable Control\n - 24 - 1 - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - read-write - - - - - DMA_PDSSR0 - - DMA_PDSSR0 - DMA Service Selection Control Register 0 - 0x4 - read-write - 0x00FFFFFF - 0xFFFFFFFF - - - SPI0_RXSEL - PDMA SPI0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers: Reserved\n - 0 - 4 - read-write - - - SPI0_TXSEL - PDMA SPI0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 4 - 4 - read-write - - - SPI1_RXSEL - PDMA SPI1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 8 - 4 - read-write - - - SPI1_TXSEL - PDMA SPI1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 12 - 4 - read-write - - - SPI2_RXSEL - PDMA SPI2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 16 - 4 - read-write - - - SPI2_TXSEL - PDMA SPI2 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. - 20 - 4 - read-write - - - - - DMA_PDSSR1 - - DMA_PDSSR1 - DMA Service Selection Control Register 1 - 0x8 - read-write - 0x0FFFFFFF - 0xFFFFFFFF - - - UART0_RXSEL - This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers : Reserved\n - 0 - 4 - read-write - - - UART0_TXSEL - PDMA UART0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 4 - 4 - read-write - - - UART1_RXSEL - PDMA UART1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 8 - 4 - read-write - - - UART1_TXSEL - PDMA UART1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 12 - 4 - read-write - - - ADC_RXSEL - PDMA ADC RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. - 24 - 4 - read-write - - - - - DMA_GCRISR - - DMA_GCRISR - DMA Global Interrupt Status Register - 0xC - read-only - 0x00000000 - 0xFFFFFFFF - - - INTR0 - Interrupt Pin Status of Channel 0\nThis bit is the Interrupt status of PDMA channel 0.\nNote: This bit is read only. - 0 - 1 - read-only - - - INTR1 - Interrupt Pin Status of Channel 1\nThis bit is the Interrupt status of PDMA channel 1.\nNote: This bit is read only. - 1 - 1 - read-only - - - INTR2 - Interrupt Pin Status of Channel 2\nThis bit is the Interrupt status of PDMA channel 2.\nNote: This bit is read only. - 2 - 1 - read-only - - - INTR3 - Interrupt Pin Status of Channel 3\nThis bit is the Interrupt status of PDMA channel 3.\nNote: This bit is read only. - 3 - 1 - read-only - - - INTR4 - Interrupt Pin Status of Channel 4\nThis bit is the Interrupt status of PDMA channel 4.\nNote: This bit is read only. - 4 - 1 - read-only - - - INTR5 - Interrupt Pin Status of Channel 5 \nThis bit is the Interrupt status of PDMA channel 5.\nNote: This bit is read only. - 5 - 1 - read-only - - - CRC_INTR - Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller.\nNote: This bit is read only. - 6 - 1 - read-only - - - INTR - Interrupt Pin Status\nThis bit is the Interrupt status of PDMA controller.\nNote: This bit is read only - 31 - 1 - read-only - - - - - DMA_PDSSR2 - - DMA_PDSSR2 - DMA Service Selection Control Register 2 - 0x10 - read-write - 0x00FFFFFF - 0xFFFFFFFF - - - I2S_RXSEL - PDMA I2S RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3\n4'b0100: CH4\n4'b0101: CH5\nOthers : Reserved\n - 0 - 4 - read-write - - - I2S_TXSEL - PDMA I2S TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 4 - 4 - read-write - - - PWM0_RXSEL - PDMA PWM0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM0 RX. Software can configure the RX channel setting by PWM0_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 8 - 4 - read-write - - - PWM1_RXSEL - PDMA PWM1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM1 RX. Software can configure the RX channel setting by PWM1_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 12 - 4 - read-write - - - PWM2_RXSEL - PDMA PWM2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM2 RX. Software can configure the RX channel setting by PWM2_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 16 - 4 - read-write - - - PWM3_RXSEL - PDMA PWM3 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM3 RX. Software can configure the RX channel setting by PWM3_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. - 20 - 4 - read-write - - - - - - - diff --git a/ext/avs_commons-5.4.1.zip b/ext/avs_commons-5.4.1.zip new file mode 100644 index 0000000000..064f8a0343 Binary files /dev/null and b/ext/avs_commons-5.4.1.zip differ diff --git a/ext/gecko_sdk b/ext/gecko_sdk new file mode 160000 index 0000000000..d95099f4c0 --- /dev/null +++ b/ext/gecko_sdk @@ -0,0 +1 @@ +Subproject commit d95099f4c05b3c40cece93d8a261dd471e642086 diff --git a/ext/mbedtls-mbedtls-3.5.0.zip b/ext/mbedtls-mbedtls-3.5.0.zip new file mode 100644 index 0000000000..300bc5a9c9 Binary files /dev/null and b/ext/mbedtls-mbedtls-3.5.0.zip differ diff --git a/ext/svd.zip b/ext/svd.zip new file mode 100644 index 0000000000..bdd5d47d5d Binary files /dev/null and b/ext/svd.zip differ diff --git a/ext/wiznet-iolibrary-driver.zip b/ext/wiznet-iolibrary-driver.zip new file mode 100644 index 0000000000..8eca4fc4be Binary files /dev/null and b/ext/wiznet-iolibrary-driver.zip differ diff --git a/ext/xmlmbus/include/xmlmbus_buffer.h b/ext/xmlmbus/include/xmlmbus_buffer.h new file mode 100644 index 0000000000..2e56ec0521 --- /dev/null +++ b/ext/xmlmbus/include/xmlmbus_buffer.h @@ -0,0 +1,39 @@ +#pragma once + +#include +#include + +#include + +struct xmlmbus_buffer { + + uint8_t data[MBUS_FRAME_SIZE_MAX]; + size_t length; /** Number of bytes used in data. */ +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +int xmlmbus_buffer_write_u8(struct xmlmbus_buffer*, uint8_t); + +int xmlmbus_buffer_write_u16(struct xmlmbus_buffer*, uint16_t); + +int xmlmbus_buffer_write_u24(struct xmlmbus_buffer *buffer, uint32_t); + +int xmlmbus_buffer_write_u32(struct xmlmbus_buffer*, uint32_t); + +int xmlmbus_buffer_write_u64(struct xmlmbus_buffer*, uint64_t); + +int xmlmbus_buffer_write_blob(struct xmlmbus_buffer*, const void*, size_t); + +int xmlmbus_buffer_write_cfield(struct xmlmbus_buffer*, uint8_t); + +int xmlmbus_buffer_write_afield(struct xmlmbus_buffer*, uint8_t); + +int xmlmbus_buffer_write_cifield(struct xmlmbus_buffer*, uint8_t); + +#ifdef __cplusplus +} +#endif diff --git a/ext/xmlmbus/include/xmlmbus_mbus_common.h b/ext/xmlmbus/include/xmlmbus_mbus_common.h new file mode 100644 index 0000000000..f615714804 --- /dev/null +++ b/ext/xmlmbus/include/xmlmbus_mbus_common.h @@ -0,0 +1,89 @@ +#pragma once + +#include + +#define MBUS_FRAME_SINGLE_START 0xE5u +#define MBUS_FRAME_SHORT_START 0x10u +#define MBUS_FRAME_LONG_START 0x68u +#define MBUS_FRAME_STOP 0x16u + +#define MBUS_ACK 0xE5u + +#define MBUS_FRAME_SIZE_SINGLE_CHARACTER 1u +#define MBUS_FRAME_SIZE_SHORT 5u +#define MBUS_FRAME_SIZE_CONTROL 9u +#define MBUS_FRAME_SIZE_DATA_SHORT (MBUS_FRAME_SIZE_SHORT - 3u) +#define MBUS_FRAME_SIZE_DATA_MAX 252u +#define MBUS_FRAME_SIZE_MAX (9u + MBUS_FRAME_SIZE_DATA_MAX) + +#define MBUS_ADDRESS_UNCONFIGURED 0u +#define MBUS_ADDRESS_MIN 1u +#define MBUS_ADDRESS_MAX 250u +#define MBUS_ADDRESS_RESERVED_251 251u +#define MBUS_ADDRESS_RESERVED_252 252u +#define MBUS_ADDRESS_IN_NETWORK_LAYER 253u +#define MBUS_ADDRESS_BROADCAST_ALL_REPLY 254u +#define MBUS_ADDRESS_BROADCAST_NO_REPLY 255u + +#define MBUS_CFIELD_REQUEST (1u << 6) /**< Calling direction. */ +#define MBUS_CFIELD_RESPONSE (0u << 6) /**< Reply direction. */ + +#define MBUS_CFIELD_FCB (1u << 5) /**< Frame Count Bit indicates successful transmission procedures. */ +#define MBUS_CFIELD_FCV (1u << 4) /**< Frame Count Valid is set -> FCB is used; FCV is not set -> FCB is ignored. */ + +#define MBUS_CFIELD_ACD (1u << 5) /**< With Access Demand bit set the slave shows that it wants to transmit Class 1 data. */ +#define MBUS_CFIELD_DFC (1u << 4) /**< With Data Flow Control bit is set the slave indicates that it can't accept any further data. */ + +#define MBUS_CFIELD_FUNCTION(f) (((f) & 0xFu) << 0) + +/** Initialization of Slave */ +#define MBUS_SND_NKE (MBUS_CFIELD_REQUEST | MBUS_CFIELD_FUNCTION(0x0)) + +/** Send User Data to Slave */ +#define MBUS_SND_UD (MBUS_CFIELD_REQUEST | MBUS_CFIELD_FUNCTION(0x3)) + +/** Request for Class 2 Data */ +#define MBUS_REQ_UD2 (MBUS_CFIELD_REQUEST | MBUS_CFIELD_FUNCTION(0xB)) + +/** Request for Class1 Data */ +#define MBUS_REQ_UD1 (MBUS_CFIELD_REQUEST | MBUS_CFIELD_FUNCTION(0xA)) + +/** Data Transfer from Slave to Master after Request */ +#define RSP_UD (MBUS_CFIELD_RESPONSE | MBUS_CFIELD_FUNCTION(0x8)) + +/* CI-Field codes used by the master. */ +#define MBUS_CI_DATA_SEND 0x51u +#define MBUS_CI_SELECTION_OF_SLAVES 0x52u +#define MBUS_CI_APPLICATION_RESET 0x50u +#define MBUS_CI_SYNCHRONIZE_ACTION 0x54u +#define MBUS_CI_SET_BAUDRATE_TO_300 0xB8u +#define MBUS_CI_SET_BAUDRATE_TO_600 0xB9u +#define MBUS_CI_SET_BAUDRATE_TO_1200 0xBAu +#define MBUS_CI_SET_BAUDRATE_TO_2400 0xBBu +#define MBUS_CI_SET_BAUDRATE_TO_4800 0xBCu +#define MBUS_CI_SET_BAUDRATE_TO_9600 0xBDu +#define MBUS_CI_SET_BAUDRATE_TO_19200 0xBEu +#define MBUS_CI_SET_BAUDRATE_TO_38400 0xBFu +#define MBUS_CI_RAM_READOUT 0xB1u +#define MBUS_CI_RAM_WRITE 0xB2u +#define MBUS_CI_INIT_TEST_MODE 0xB3u +#define MBUS_CI_EEPROM_READ 0xB4u +#define MBUS_CI_START_SOFTWARE_TEST 0xB6u + +/* CI-Field codes used by the slave. */ +#define MBUS_CI_REPORT_GENERAL_APPLICATION_ERROR 0x70u +#define MBUS_CI_REPORT_ALARM_STATUS 0x71u +#define MBUS_CI_VARIABLE_DATA_RESPOND 0x72u +#define MBUS_CI_FIXED_DATA_RESPOND 0x73u + +/* 6.3.1 Fixed Data Header */ +struct mbus_fixed_data_header { + uint32_t ident_no; + uint16_t manufacturer; + uint8_t version; + uint8_t medium; + uint8_t access_number; + uint8_t status; + uint16_t signature; +}; + diff --git a/ext/xmlmbus/include/xmlmbus_mbus_frame.h b/ext/xmlmbus/include/xmlmbus_mbus_frame.h new file mode 100644 index 0000000000..ebcf71aa92 --- /dev/null +++ b/ext/xmlmbus/include/xmlmbus_mbus_frame.h @@ -0,0 +1,108 @@ +#pragma once + +#include + +#include + +typedef enum { + + XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1 = 0, + XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_LENGTH_1, + XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_LENGTH_2, + XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_2, + XMLMBUS_MBUS_RX_FRAME_STATE_RX_DATA, + XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_CRC, + XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_STOP +} xmlmbus_mbus_rx_frame_state_t; + +struct xmlmbus_mbus_frame_state_machine_data { + int state; + uint8_t length_1; + uint8_t length_2; + uint8_t checksum; + unsigned bytes_to_receive; + unsigned datalen; + + union { + unsigned info; + + struct { + + unsigned length_error: 1; + unsigned start2_error: 1; + unsigned checksum_error: 1; + unsigned stop_error: 1; + unsigned rx_complete: 1; + } status; + }; + + uint8_t data[MBUS_FRAME_SIZE_MAX]; +}; + +struct mbus_single_frame { + uint8_t start; +}; + +struct mbus_short_frame { + uint8_t start; + uint8_t c; + uint8_t a; + uint8_t checksum; + uint8_t stop; +}; + +struct mbus_control_frame { + uint8_t start; + uint8_t length_1; + uint8_t length_2; + uint8_t start_2; + uint8_t c; + uint8_t a; + uint8_t ci; + uint8_t checksum; + uint8_t stop; +}; + +struct mbus_long_frame_header { + uint8_t start; + uint8_t length_1; + uint8_t length_2; + uint8_t start_2; + uint8_t c; + uint8_t a; + uint8_t ci; +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +void xmlmbus_reset_state_machine(struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_process_state_machine(struct xmlmbus_mbus_frame_state_machine_data *mach, uint8_t b); + +void xmlmbus_mbus_frame_clear_error_mask(struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_mbus_frame_is_length_error(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_mbus_frame_is_start2_error(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_mbus_frame_is_stop_error(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_mbus_frame_is_checksum_error(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_mbus_frame_is_good(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +int xmlmbus_mbus_frame_is_rx_complete(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +uint8_t xmlmbus_mbus_checksum(const uint8_t *buf, unsigned buflen); + +const uint8_t* xmlmbus_mbus_frame_get_data(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +unsigned xmlmbus_mbus_frame_get_datalen(const struct xmlmbus_mbus_frame_state_machine_data *mach); + +#ifdef __cplusplus +} +#endif + diff --git a/ext/xmlmbus/include/xmlmbus_server.h b/ext/xmlmbus/include/xmlmbus_server.h new file mode 100644 index 0000000000..d9e44b3978 --- /dev/null +++ b/ext/xmlmbus/include/xmlmbus_server.h @@ -0,0 +1,87 @@ +#pragma once + +#include +#include + +#include + +enum xmlmbus_server_error { + XMLMBUS_SERVER_OK = 0, /* Must have the same value as XMLMBUS_OK. */ + + XMLMBUS_SERVER_ERROR = 0x1000, /* Must be "above" all other XMLLMBUS_ERROR_x. */ + XMLMBUS_SERVER_ERROR_NO_MEMORY, + XMLMBUS_SERVER_ERROR_WRONG_DIRECTION_IN_CFIELD, + + XMLMBUS_SERVER_NOT_FOR_ME = 0x1010, + + XMLMBUS_SERVER_UNIMPLEMENTED_SINGLE_CHARACTER_FRAME_HANDLER = 0x1020, + XMLMBUS_SERVER_UNIMPLEMENTED_SHORT_FRAME_HANDLER, + XMLMBUS_SERVER_UNIMPLEMENTED_LONG_FRAME_HANDLER, + XMLMBUS_SERVER_ERROR_IN_SHORT_FRAME_HANDLER, + XMLMBUS_SERVER_ERROR_IN_LONG_FRAME_HANDLER, + + XMLMBUS_SERVER_CANT_OPEN_INTERFACE = 0x1030, +}; + +struct xmlmbus_server_ctx; /* Forward declaration. */ + +typedef int (*ci_cmd_func)(struct xmlmbus_server_ctx *ctx, const uint8_t **in, size_t inlen, void *arg); + +typedef int (*ctrl_cmd_func)(struct xmlmbus_server_ctx *ctx, void *arg); + +typedef int (*single_character_handler_func)(struct xmlmbus_server_ctx* ctx); + +struct ctrl_cmd +{ + uint8_t cfield; + ctrl_cmd_func func; + void *func_arg; +}; + +struct ci_cmd +{ + uint8_t cfield; + uint8_t ci; + ci_cmd_func func; + void *func_arg; +}; + +struct xmlmbus_server_ctx +{ + struct xmlmbus_buffer buffer; + + uint8_t address; + + uint32_t ident_no; + uint16_t manufacturer; + uint8_t version; + uint8_t medium; + + uint8_t access_number; + uint8_t status; + + const struct ctrl_cmd *ctrl_cmd_table; + size_t ctrl_cmd_table_size; + + const struct ci_cmd* ci_cmd_table; + size_t ci_cmd_table_size; + + single_character_handler_func single_character_handler; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +uint8_t* xmlmbus_server_get_response_buffer(struct xmlmbus_server_ctx *ctx); + +size_t xmlmbus_server_get_response_buffer_size(const struct xmlmbus_server_ctx *ctx); + +size_t xmlmbus_server_get_response_buffer_used(const struct xmlmbus_server_ctx *ctx); + +int xmlmbus_server_process_client_request(struct xmlmbus_server_ctx *ctx, const uint8_t *in, size_t inlen); + +#ifdef __cplusplus +} +#endif + diff --git a/ext/xmlmbus/src/xmlmbus_buffer.c b/ext/xmlmbus/src/xmlmbus_buffer.c new file mode 100644 index 0000000000..6c16ef7d03 --- /dev/null +++ b/ext/xmlmbus/src/xmlmbus_buffer.c @@ -0,0 +1,99 @@ +#include + +static inline int _xmlmbus_buffer_write_u8(struct xmlmbus_buffer *buffer, uint8_t src) { + + if (buffer->length >= sizeof(buffer->data)) + return (-1); + buffer->data[buffer->length++] = src; + return 0; +} + +int xmlmbus_buffer_write_u8(struct xmlmbus_buffer *buffer, uint8_t src) { + + return (_xmlmbus_buffer_write_u8(buffer, src)); +} + +int xmlmbus_buffer_write_u16(struct xmlmbus_buffer *buffer, uint16_t src) { + + int rc = 0; + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 8)); + return rc; +} + +int xmlmbus_buffer_write_u24(struct xmlmbus_buffer *buffer, uint32_t src) { + + int rc = 0; + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 8)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 16)); + return rc; +} + +int xmlmbus_buffer_write_u32(struct xmlmbus_buffer *buffer, uint32_t src) { + + int rc = 0; + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 8)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 16)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 24)); + return rc; +} + +int xmlmbus_buffer_write_u64(struct xmlmbus_buffer *buffer, uint64_t src) { + + int rc = 0; + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 8)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 16)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 24)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 32)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 40)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 48)); + if (rc == 0) + rc = _xmlmbus_buffer_write_u8(buffer, (uint8_t)(src >> 56)); + return rc; +} + +int xmlmbus_buffer_write_blob(struct xmlmbus_buffer *buffer, const void *_src, size_t src_size) { + + int rc = 0; + const uint8_t *src = _src; + + while (rc == 0 && src_size--) + rc = _xmlmbus_buffer_write_u8(buffer, *src++); + + return rc; +} + +int xmlmbus_buffer_write_cfield(struct xmlmbus_buffer *packet, uint8_t src) { + + return (_xmlmbus_buffer_write_u8(packet, src)); +} + +int xmlmbus_buffer_write_afield(struct xmlmbus_buffer *packet, uint8_t src) { + + return (_xmlmbus_buffer_write_u8(packet, src)); +} + +int xmlmbus_buffer_write_cifield(struct xmlmbus_buffer *packet, uint8_t src) { + + return (_xmlmbus_buffer_write_u8(packet, src)); +} + diff --git a/ext/xmlmbus/src/xmlmbus_mbus_frame.c b/ext/xmlmbus/src/xmlmbus_mbus_frame.c new file mode 100644 index 0000000000..3a342c777a --- /dev/null +++ b/ext/xmlmbus/src/xmlmbus_mbus_frame.c @@ -0,0 +1,238 @@ +#include + +static uint8_t _xmlmbus_mbus_checksum(const uint8_t *buf, unsigned buflen) { + + uint8_t checksum = 0; + + while (buflen--) { + checksum += *buf++; + } + + return checksum; +} + +static void _xmlmbus_clear_error_mask(struct xmlmbus_mbus_frame_state_machine_data *mach) { + + mach->info = 0; +} + +static void _xmlmbus_reset_state_machine(struct xmlmbus_mbus_frame_state_machine_data *mach) { + + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1; + mach->length_1 = 0u; + mach->length_2 = 0u; + mach->checksum = 0u; + + mach->bytes_to_receive = 0u; + mach->datalen = 0u; + + _xmlmbus_clear_error_mask(mach); +} + +static int _xmlmbus_is_length_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->status.length_error); +} + +static int _xmlmbus_is_start2_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->status.start2_error); +} + +static int _xmlmbus_is_checksum_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->status.checksum_error); +} + +static int _xmlmbus_is_stop_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->status.stop_error); +} + +void xmlmbus_reset_state_machine(struct xmlmbus_mbus_frame_state_machine_data *mach) { + + _xmlmbus_reset_state_machine(mach); +} + +int xmlmbus_process_state_machine(struct xmlmbus_mbus_frame_state_machine_data *mach, uint8_t b) { + + if (mach->status.rx_complete != 0) + _xmlmbus_reset_state_machine(mach); + + switch (mach->state) { + case XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1: + mach->bytes_to_receive = 0u; + mach->datalen = 0u; + mach->data[mach->datalen++] = b; + + if (MBUS_FRAME_SINGLE_START == b) { + mach->bytes_to_receive = 0u; + mach->status.rx_complete = 1u; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1; + } + else if (MBUS_FRAME_SHORT_START == b) { + /* One byte is already received. */ + mach->bytes_to_receive = MBUS_FRAME_SIZE_SHORT - 1u; + mach->status.rx_complete = 0u; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_RX_DATA; + } + else if (MBUS_FRAME_LONG_START == b) { + /* One byte is already received. */ + mach->bytes_to_receive = MBUS_FRAME_SIZE_MAX - 1u; + mach->status.rx_complete = 0u; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_LENGTH_1; + } + break; + + case XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_LENGTH_1: + mach->bytes_to_receive--; + mach->data[mach->datalen++] = b; + + mach->length_1 = b; + + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_LENGTH_2; + break; + + case XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_LENGTH_2: + mach->bytes_to_receive--; + mach->data[mach->datalen++] = b; + + mach->length_2 = b; + + if (mach->length_1 == mach->length_2) { + mach->status.length_error = 0; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_2; + } + else { + mach->status.length_error = 1; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1; + } + break; + + case XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_2: + mach->bytes_to_receive--; + mach->data[mach->datalen++] = b; + + if (MBUS_FRAME_LONG_START == b) { + /* There are C, A, CI, data, CRC and STOP bytes to receive. */ + mach->bytes_to_receive = mach->length_1 + 2u; + mach->status.start2_error = 0; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_RX_DATA; + } + else { + mach->status.start2_error = 1; + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1; + } + break; + + case XMLMBUS_MBUS_RX_FRAME_STATE_RX_DATA: + mach->bytes_to_receive--; + mach->data[mach->datalen++] = b; + + if (mach->bytes_to_receive == 2u) { + /* There are CRC and STOP bytes to receive. */ + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_CRC; + } + break; + + case XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_CRC: + mach->bytes_to_receive--; + mach->data[mach->datalen++] = b; + + /* We will go until the end of the current frame. */ + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_STOP; + + if (MBUS_FRAME_SHORT_START == mach->data[0]) { + uint8_t checksum = _xmlmbus_mbus_checksum(&mach->data[1], mach->datalen - 1u - 1u); + mach->status.checksum_error = (checksum == b) ? 0 : 1; + } + else if (MBUS_FRAME_LONG_START == mach->data[0]) { + uint8_t checksum = _xmlmbus_mbus_checksum(&mach->data[4], mach->datalen - 4u - 1u); + mach->status.checksum_error = (checksum == b) ? 0 : 1; + } + else { + /* Unknown frame? */ + _xmlmbus_reset_state_machine(mach); + } + break; + + case XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_STOP: + mach->bytes_to_receive--; + mach->data[mach->datalen++] = b; + + /* Frame is definetely complete. */ + mach->status.rx_complete = 1u; + + /* And also stopped? */ + mach->status.stop_error = (MBUS_FRAME_STOP == b) ? 0 : 1; + + if (mach->bytes_to_receive == 0) { + mach->state = XMLMBUS_MBUS_RX_FRAME_STATE_WAIT_START_1; + } + else { + /* Still bytes to receive? */ + _xmlmbus_reset_state_machine(mach); + } + break; + } + + return (mach->status.rx_complete); +} + +void xmlmbus_mbus_frame_clear_error_mask(struct xmlmbus_mbus_frame_state_machine_data *mach) { + + _xmlmbus_clear_error_mask(mach); +} + +int xmlmbus_mbus_frame_is_length_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (_xmlmbus_is_length_error(mach)); +} + +int xmlmbus_mbus_frame_is_start2_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (_xmlmbus_is_start2_error(mach)); +} + +int xmlmbus_mbus_frame_is_checksum_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (_xmlmbus_is_checksum_error(mach)); +} + +int xmlmbus_mbus_frame_is_stop_error(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (_xmlmbus_is_stop_error(mach)); +} + +int xmlmbus_mbus_frame_is_good(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + unsigned error_mask = 0; + + error_mask |= _xmlmbus_is_length_error(mach) << 0; + error_mask |= _xmlmbus_is_start2_error(mach) << 1; + error_mask |= _xmlmbus_is_checksum_error(mach) << 2; + error_mask |= _xmlmbus_is_stop_error(mach) << 3; + + return ((error_mask == 0) ? 1 : 0); +} + +int xmlmbus_mbus_frame_is_rx_complete(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->status.rx_complete); +} + +uint8_t xmlmbus_mbus_checksum(const uint8_t *buf, unsigned buflen) { + + return (_xmlmbus_mbus_checksum(buf, buflen)); +} + +const uint8_t* xmlmbus_mbus_frame_get_data(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->data); +} + +unsigned xmlmbus_mbus_frame_get_datalen(const struct xmlmbus_mbus_frame_state_machine_data *mach) { + + return (mach->datalen); +} + diff --git a/ext/xmlmbus/src/xmlmbus_server.c b/ext/xmlmbus/src/xmlmbus_server.c new file mode 100644 index 0000000000..bed45083c9 --- /dev/null +++ b/ext/xmlmbus/src/xmlmbus_server.c @@ -0,0 +1,139 @@ +#include +#include + +uint8_t* xmlmbus_server_get_response_buffer(struct xmlmbus_server_ctx *ctx) { + + return (ctx->buffer.data); +} + +size_t xmlmbus_server_get_response_buffer_size(const struct xmlmbus_server_ctx *ctx) { + + return (sizeof(ctx->buffer.data)); +} + +size_t xmlmbus_server_get_response_buffer_used(const struct xmlmbus_server_ctx *ctx) { + + return (ctx->buffer.length); +} + +static int xmlmbus_server_process_short_frame(struct xmlmbus_server_ctx *ctx, uint8_t cfield) { + + if (ctx->ctrl_cmd_table == NULL || + ctx->ctrl_cmd_table_size == 0) { + + return XMLMBUS_SERVER_UNIMPLEMENTED_SHORT_FRAME_HANDLER; + } + + + int rc = XMLMBUS_SERVER_UNIMPLEMENTED_SHORT_FRAME_HANDLER; + + for (size_t i = 0; i < ctx->ctrl_cmd_table_size; i++) { + const struct ctrl_cmd *cmd = &ctx->ctrl_cmd_table[i]; + + if (cfield == cmd->cfield) { + if (cmd->func != NULL) { + if (0 == cmd->func(ctx, cmd->func_arg)) { + rc = XMLMBUS_SERVER_OK; + } + else { + rc = XMLMBUS_SERVER_ERROR_IN_SHORT_FRAME_HANDLER; + } + + /* Don't process any further here, because the control frame is over. */ + break; + } + } + } + + return rc; +} + +static int xmlmbus_server_process_long_frame(struct xmlmbus_server_ctx *ctx, uint8_t cfield, + const uint8_t *next_ci, const uint8_t * const last_ci) { + + if (ctx->ci_cmd_table == NULL || + ctx->ci_cmd_table_size == 0) { + + return XMLMBUS_SERVER_UNIMPLEMENTED_LONG_FRAME_HANDLER; + } + + int rc = XMLMBUS_SERVER_OK; + + while (rc == XMLMBUS_SERVER_OK && next_ci < last_ci) { + rc = XMLMBUS_SERVER_UNIMPLEMENTED_LONG_FRAME_HANDLER; + + for (size_t i = 0; i < ctx->ci_cmd_table_size; i++) { + const struct ci_cmd *cmd = &ctx->ci_cmd_table[i]; + + if (cfield == cmd->cfield && *next_ci == cmd->ci) { + if (cmd->func != NULL) { + if (0 == cmd->func(ctx, &next_ci, last_ci - next_ci, cmd->func_arg)) { + rc = XMLMBUS_SERVER_OK; + } + else { + rc = XMLMBUS_SERVER_ERROR_IN_LONG_FRAME_HANDLER; + } + + break; + } + } + } + } + + return rc; +} + +int xmlmbus_server_process_client_request(struct xmlmbus_server_ctx *ctx, const uint8_t *in, size_t inlen) { + + int rc; + unsigned cfield, address, length; + + if (ctx == NULL || in == NULL || inlen == 0) + return XMLMBUS_SERVER_ERROR; + + ctx->buffer.length = 0; + + switch (inlen) { + case MBUS_FRAME_SIZE_SINGLE_CHARACTER: + if (ctx->single_character_handler != NULL) + rc = ctx->single_character_handler(ctx); + else + rc = XMLMBUS_SERVER_UNIMPLEMENTED_SINGLE_CHARACTER_FRAME_HANDLER; + break; + + case MBUS_FRAME_SIZE_SHORT: + cfield = in[1]; + address = in[2]; + //length = MBUS_FRAME_SIZE_DATA_SHORT; + + if ((cfield & MBUS_CFIELD_REQUEST) == 0) + return XMLMBUS_SERVER_ERROR_WRONG_DIRECTION_IN_CFIELD; + + if (address == MBUS_ADDRESS_BROADCAST_ALL_REPLY || address == ctx->address) + rc = xmlmbus_server_process_short_frame(ctx, cfield); + else + rc = XMLMBUS_SERVER_NOT_FOR_ME; + break; + + default: + cfield = in[4]; + address = in[5]; + length = in[1]; + + if ((cfield & MBUS_CFIELD_REQUEST) == 0) + return XMLMBUS_SERVER_ERROR_WRONG_DIRECTION_IN_CFIELD; + + if (address == MBUS_ADDRESS_BROADCAST_ALL_REPLY || address == ctx->address) + rc = xmlmbus_server_process_long_frame(ctx, cfield, &in[6], &in[4 + length]); + else + rc = XMLMBUS_SERVER_NOT_FOR_ME; + break; + } + + if (rc == XMLMBUS_SERVER_OK) { + ctx->access_number++; + } + + return rc; +} + diff --git a/ext/xmlmbus/xmlmbus_chibios.mk b/ext/xmlmbus/xmlmbus_chibios.mk new file mode 100644 index 0000000000..53f1c53783 --- /dev/null +++ b/ext/xmlmbus/xmlmbus_chibios.mk @@ -0,0 +1,11 @@ +# Required platform files. +XMLMBUS = $(CHIBIOS_CONTRIB)/ext/xmlmbus + +XMLMBUSSRC = $(XMLMBUS)/src/xmlmbus_buffer.c \ + $(XMLMBUS)/src/xmlmbus_server.c + +XMLMBUSINC = $(XMLMBUS)/include + +# Shared variables +ALLCSRC += $(XMLMBUSSRC) +ALLINC += $(XMLMBUSINC) diff --git a/os/common/ext/TI/devices/cc13x0/inc/asmdefs.h b/os/common/ext/TI/devices/cc13x0/inc/asmdefs.h new file mode 100644 index 0000000000..6c3fa14414 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/asmdefs.h @@ -0,0 +1,151 @@ +/****************************************************************************** +* Filename: asmdefs.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Description: Macros to allow assembly code be portable among tool chains. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // __IAR_SYSTEMS_ICC__ + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(__GNUC__) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // __GNUC__ + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#if defined(__CC_ARM) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // __CC_ARM + + +#endif // __ASMDEF_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_adi.h b/os/common/ext/TI/devices/cc13x0/inc/hw_adi.h new file mode 100644 index 0000000000..17dfa2ba08 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_adi.h @@ -0,0 +1,1182 @@ +/****************************************************************************** +* Filename: hw_adi.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_H__ +#define __HW_ADI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the ADI master and +// accessing ADI slave registers via the ADI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a ADI Slave. +// +// The macros that that provide ADI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example ADI_O_SLAVECONF is a macro for a +// register offset and ADI_SLAVECONF_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; +// +// The "instruction offset" macros are used to pass an instruction to +// the ADI Master when accessing ADI slave registers. These macros are +// only used when accessing ADI Slave Registers. (Remember ADI +// Master Registers are accessed normally). +// +// The instructions supported when accessing an ADI Slave Register follow: +// - Direct Access to an ADI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a ADI Slave register. +// - Clear the specified bits in a ADI Slave register. +// - Mask write of 4 bits to the a ADI Slave register. +// - Mask write of 8 bits to the a ADI Slave register. +// - Mask write of 16 bits to the a ADI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are +// supported natively. If accessing wider bitfields, the read/write operation +// will be spread out over a number of transactions. This is hidden for the +// user, but can potentially be very timeconsuming. Especially of running +// on a slow clock. +// +// The generic format of using these macros for a read follows: +// // Read low 8-bits in ADI_SLAVE_OFF +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// Notes: In the above example: +// - ADI_MASTER_BASE is the base address of the ADI Master defined +// in the hw_memmap.h header file. +// - ADI_SLAVE_OFF is the ADI Slave offset defined in the +// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys +// module). +// - ADI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to an ADI Slave register +// ADI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; +// +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; +// +// // Write each byte at ADI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the ADI master instruction offsets. +// +//***************************************************************************** +#define ADI_O_DIR 0x00000000 // Offset for the direct access + // instruction +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 15:8 are + // mask. Bits 7:0 are data. Requires + // 'short' write. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 31:16 + // are mask. Bits 15:0 are data. + // Requires 'long' write. + +//***************************************************************************** +// +// The following are defines for the ADI register offsets. +// +//***************************************************************************** +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 + +//***************************************************************************** +// +// The following are defines pseudo-magic numbers that should go away. +// New code should not use these registers and old code should be ported +// to not use these. +// +//***************************************************************************** +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte + // offsets 0 to 3 +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte + // offsets 4 to 7 +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte + // offsets 8 to 11 +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte + // offsets 12 to 15 +#define ADI_O_SET03 0x00000010 // Set register for ADI byte + // offsets 0 to 3 +#define ADI_O_SET47 0x00000014 // Set register for ADI byte + // offsets 4 to 7 +#define ADI_O_SET811 0x00000018 // Set register for ADI byte + // offsets 8 to 11 +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte + // offsets 12 to 15 +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte + // offsets 0 to 3 +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte + // offsets 4 to 7 +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte + // offsets 8 to 11 +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte + // offsets 12 to 15 +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + // register +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI + // Registers at byte offsets 14 and + // 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR03 register. +// +//***************************************************************************** +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR47 register. +// +//***************************************************************************** +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR811 register. +// +//***************************************************************************** +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register + // 11 +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register + // 10 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR1215 register. +// +//***************************************************************************** +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register + // 15 +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register + // 14 +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register + // 13 +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register + // 12 +#define ADI_DIR1215_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET03 register. +// +//***************************************************************************** +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 3. Read returns 0. +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 2. Read returns 0. +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 1. Read returns 0. +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 0. Read returns 0. +#define ADI_SET03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET47 register. +// +//***************************************************************************** +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 7. Read returns 0. +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 6. Read returns 0. +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 5. Read returns 0. +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 4. Read returns 0. +#define ADI_SET47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET811 register. +// +//***************************************************************************** +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 11. Read returns 0. +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 10. Read returns 0. +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 9. Read returns 0. +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 8. Read returns 0. +#define ADI_SET811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET1215 register. +// +//***************************************************************************** +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 15. Read returns 0. +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 14. Read returns 0. +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 13. Read returns 0. +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 12. Read returns 0. +#define ADI_SET1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR03 register. +// +//***************************************************************************** +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 3 +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 2 +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 1 +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 0 +#define ADI_CLR03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR47 register. +// +//***************************************************************************** +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 7 +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 6 +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 5 +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 4 +#define ADI_CLR47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR811 register. +// +//***************************************************************************** +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 11 +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 10 +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 9 +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 8 +#define ADI_CLR811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR1215 register. +// +//***************************************************************************** +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 15 +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 14 +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 13 +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 12 +#define ADI_CLR1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B01 register. +// +//***************************************************************************** +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 1 +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 1, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 1 +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 1, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 0 +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 0, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 0 +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 0, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B01_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B23 register. +// +//***************************************************************************** +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 3 +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 3, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 3 +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 3, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 2 +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 2, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 2 +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 2, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B23_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B45 register. +// +//***************************************************************************** +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 5 +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 5, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 5 +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 5, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 4 +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 4, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 4 +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 4, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B45_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B67 register. +// +//***************************************************************************** +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 7 +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 7, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 7 +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 7, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 6 +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 6, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 6 +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 6, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B67_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B89 register. +// +//***************************************************************************** +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 9 +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 9, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 9 +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 9, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 8 +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 8, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 8 +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 8, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B89_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1011 register. +// +//***************************************************************************** +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 11 +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 11, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 11 +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 11, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 10 +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 10, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 10 +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 10, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1011_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1213 register. +// +//***************************************************************************** +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 13 +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 13, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 13 +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 13, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 12 +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 12, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 12 +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 12, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1213_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1415 register. +// +//***************************************************************************** +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 15 +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 15, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 15 +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 15, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 14 +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 14, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 14 +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 14, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1415_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B01 register. +// +//***************************************************************************** +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B01_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B23 register. +// +//***************************************************************************** +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B23_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B45 register. +// +//***************************************************************************** +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B45_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B67 register. +// +//***************************************************************************** +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B67_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B89 register. +// +//***************************************************************************** +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B89_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1011 register. +// +//***************************************************************************** +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1011_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1213 register. +// +//***************************************************************************** +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1213_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1415 register. +// +//***************************************************************************** +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1415_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B01 register. +// +//***************************************************************************** +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at + // offsets 0 and 1, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B01_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B23 register. +// +//***************************************************************************** +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at + // offsets 2 and 3, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B23_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B45 register. +// +//***************************************************************************** +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at + // offsets 4 and 5, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B45_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B67 register. +// +//***************************************************************************** +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at + // offsets 6 and 7, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B67_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B89 register. +// +//***************************************************************************** +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at + // offsets 8 and 9, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B89_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1011 register. +// +//***************************************************************************** +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at + // offsets 10 and 11, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1011_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1213 register. +// +//***************************************************************************** +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at + // offsets 12 and 13, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1213_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1415 register. +// +//***************************************************************************** +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at + // offsets 14 and 15, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1415_D_S 0 + +#endif // __HW_ADI_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_adi_2_refsys.h b/os/common/ext/TI/devices/cc13x0/inc/hw_adi_2_refsys.h new file mode 100644 index 0000000000..1e2bd85f6e --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_adi_2_refsys.h @@ -0,0 +1,362 @@ +/****************************************************************************** +* Filename: hw_adi_2_refsys_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_2_REFSYS_H__ +#define __HW_ADI_2_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_2_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [4:0] TRIM_IREF +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL0 +// +//***************************************************************************** +// Field: [7:4] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 + +// Field: [3:0] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL1 +// +//***************************************************************************** +// Field: [7:4] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 + +// Field: [3:0] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL2 +// +//***************************************************************************** +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL3 +// +//***************************************************************************** +// Field: [7:6] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 + +// Field: [5:3] ITRIM_DIGLDO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BIAS_120P Internal. Only to be used through TI provided API. +// BIAS_100P Internal. Only to be used through TI provided API. +// BIAS_80P Internal. Only to be used through TI provided API. +// BIAS_60P Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 + +// Field: [2:0] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL4 +// +//***************************************************************************** +// Field: [6:5] UDIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 + +// Field: [4:2] DIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 + +// Field: [1] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 + +// Field: [0] UDIG_LDO_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL5 +// +//***************************************************************************** +// Field: [3] IMON_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 + +// Field: [2:0] TESTSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDD_AON Internal. Only to be used through TI provided API. +// VREF_AMP Internal. Only to be used through TI provided API. +// ITEST Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL0 +// +//***************************************************************************** +// Field: [7] FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 + +// Field: [6:5] BIAS_RECHARGE_DLY +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// MIN_DLY_X8 Internal. Only to be used through TI provided API. +// MIN_DLY_X4 Internal. Only to be used through TI provided API. +// MIN_DLY_X2 Internal. Only to be used through TI provided API. +// MIN_DLY_X1 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 + +// Field: [4:3] TUNE_CAP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SHIFT_M108 Internal. Only to be used through TI provided API. +// SHIFT_M70 Internal. Only to be used through TI provided API. +// SHIFT_M35 Internal. Only to be used through TI provided API. +// SHIFT_0 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 + +// Field: [2:1] SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 + +// Field: [0] DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HPOSC_2520MHZ Internal. Only to be used through TI provided API. +// HPOSC_840MHZ Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL1 +// +//***************************************************************************** +// Field: [5] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 + +// Field: [4] PWRDET_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 + +// Field: [3:0] BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL2 +// +//***************************************************************************** +// Field: [7] BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 + +// Field: [6] TESTMUX_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 + +// Field: [5:4] ATEST_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 + +// Field: [3:0] CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 + + +#endif // __ADI_2_REFSYS__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_adi_3_refsys.h b/os/common/ext/TI/devices/cc13x0/inc/hw_adi_3_refsys.h new file mode 100644 index 0000000000..62fce9c3c7 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_adi_3_refsys.h @@ -0,0 +1,481 @@ +/****************************************************************************** +* Filename: hw_adi_3_refsys_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_3_REFSYS_H__ +#define __HW_ADI_3_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_3_REFSYS component +// +//***************************************************************************** +// Analog Test Control +#define ADI_3_REFSYS_O_SPARE0 0x00000001 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 + +// DCDC Control 0 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 + +// DCDC Control 1 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 + +// DCDC Control 2 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 + +// DCDC Control 3 +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_SPARE0 +// +//***************************************************************************** +// Field: [7:0] SPARE0 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior. +#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 +#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF +#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [7:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BMCOMPOUT Internal. Only to be used through TI provided API. +// VTEMP Internal. Only to be used through TI provided API. +// VREF0P8V Internal. Only to be used through TI provided API. +// VBGUNBUFF Internal. Only to be used through TI provided API. +// VBG Internal. Only to be used through TI provided API. +// IREF4U Internal. Only to be used through TI provided API. +// IVREF4U Internal. Only to be used through TI provided API. +// IPTAT2U Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL1 +// +//***************************************************************************** +// Field: [7:3] TRIM_VDDS_BOD +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// POS_27 Internal. Only to be used through TI provided API. +// POS_26 Internal. Only to be used through TI provided API. +// POS_25 Internal. Only to be used through TI provided API. +// POS_24 Internal. Only to be used through TI provided API. +// POS_31 Internal. Only to be used through TI provided API. +// POS_30 Internal. Only to be used through TI provided API. +// POS_29 Internal. Only to be used through TI provided API. +// POS_28 Internal. Only to be used through TI provided API. +// POS_19 Internal. Only to be used through TI provided API. +// POS_18 Internal. Only to be used through TI provided API. +// POS_17 Internal. Only to be used through TI provided API. +// POS_16 Internal. Only to be used through TI provided API. +// POS_23 Internal. Only to be used through TI provided API. +// POS_22 Internal. Only to be used through TI provided API. +// POS_21 Internal. Only to be used through TI provided API. +// POS_20 Internal. Only to be used through TI provided API. +// POS_11 Internal. Only to be used through TI provided API. +// POS_10 Internal. Only to be used through TI provided API. +// POS_9 Internal. Only to be used through TI provided API. +// POS_8 Internal. Only to be used through TI provided API. +// POS_15 Internal. Only to be used through TI provided API. +// POS_14 Internal. Only to be used through TI provided API. +// POS_13 Internal. Only to be used through TI provided API. +// POS_12 Internal. Only to be used through TI provided API. +// POS_3 Internal. Only to be used through TI provided API. +// POS_2 Internal. Only to be used through TI provided API. +// POS_1 Internal. Only to be used through TI provided API. +// POS_0 Internal. Only to be used through TI provided API. +// POS_7 Internal. Only to be used through TI provided API. +// POS_6 Internal. Only to be used through TI provided API. +// POS_5 Internal. Only to be used through TI provided API. +// POS_4 Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 + +// Field: [2] BATMON_COMP_TEST_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 + +// Field: [1:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// IPTAT1U Internal. Only to be used through TI provided API. +// BMCOMPIN Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL2 +// +//***************************************************************************** +// Field: [7:4] TRIM_VREF +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 + +// Field: [1:0] TRIM_TSENSE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL3 +// +//***************************************************************************** +// Field: [7] BOD_BG_TRIM_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 + +// Field: [6] VTEMP_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 + +// Field: [5:0] TRIM_VBG +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL0 +// +//***************************************************************************** +// Field: [7:5] GLDO_ISRC +// +// Set charge and re-charge current level. +// 2's complement encoding. +// +// 0x0: Default 11mA. +// 0x3: Max 15mA. +// 0x4: Max 5mA +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 + +// Field: [4:0] VDDR_TRIM +// +// Set the VDDR voltage. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x05: Typical voltage after trim voltage 1.71V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL1 +// +//***************************************************************************** +// Field: [7:6] IPTAT_TRIM +// +// Trim GLDO bias current. +// Proprietary encoding. +// +// 0x0: Default +// 0x1: Increase GLDO bias by 1.3x. +// 0x2: Increase GLDO bias by 1.6x. +// 0x3: Decrease GLDO bias by 0.7x. +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 + +// Field: [5] VDDR_OK_HYST +// +// Increase the hysteresis for when VDDR is considered ok. +// +// 0: Hysteresis = 60mV +// 1: Hysteresis = 70mV +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 + +// Field: [4:0] VDDR_TRIM_SLEEP +// +// Set the min VDDR voltage threshold during sleep mode. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x19: Typical voltage after trim voltage 1.52V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL2 +// +//***************************************************************************** +// Field: [6] TURNON_EA_SW +// +// Turn on erroramp switch +// +// 0: Erroramp Off (Default) +// 1: Erroramp On. Turns on GLDO error amp switch. +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 + +// Field: [5] TEST_VDDR +// +// Connect VDDR to ATEST bus +// +// 0: Not connected. +// 1: Connected +// +// Set TESTSEL = 0x0 first before setting this bit. +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 + +// Field: [4] BIAS_DIS +// +// Disable dummy bias current. +// +// 0: Dummy bias current on (Default) +// 1: Dummy bias current off +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 + +// Field: [3:0] TESTSEL +// +// Select signal for test bus, one hot. +// ENUMs: +// VDDROK VDDR_OK connected to test bus. +// IB1U 1uA bias current connected to test bus. +// PASSGATE Pass transistor gate voltage connected to test +// bus. +// ERRAMP_OUT Error amp output voltage connected to test bus. +// NC No signal connected to test bus. +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL4 +// +//***************************************************************************** +// Field: [7:6] DEADTIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 + +// Field: [5:3] LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 + +// Field: [2:0] HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL5 +// +//***************************************************************************** +// Field: [5] TESTN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 + +// Field: [4] TESTP +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 + +// Field: [3] DITHER_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 + +// Field: [2:0] IPEAK +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 + + +#endif // __ADI_3_REFSYS__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_adi_4_aux.h b/os/common/ext/TI/devices/cc13x0/inc/hw_adi_4_aux.h new file mode 100644 index 0000000000..2eabfc854b --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_adi_4_aux.h @@ -0,0 +1,490 @@ +/****************************************************************************** +* Filename: hw_adi_4_aux_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_4_AUX_H__ +#define __HW_ADI_4_AUX_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_4_AUX component +// +//***************************************************************************** +// Internal +#define ADI_4_AUX_O_MUX0 0x00000000 + +// Internal +#define ADI_4_AUX_O_MUX1 0x00000001 + +// Internal +#define ADI_4_AUX_O_MUX2 0x00000002 + +// Internal +#define ADI_4_AUX_O_MUX3 0x00000003 + +// Current Source +#define ADI_4_AUX_O_ISRC 0x00000004 + +// Comparator +#define ADI_4_AUX_O_COMP 0x00000005 + +// Internal +#define ADI_4_AUX_O_MUX4 0x00000007 + +// ADC Control 0 +#define ADI_4_AUX_O_ADC0 0x00000008 + +// ADC Control 1 +#define ADI_4_AUX_O_ADC1 0x00000009 + +// ADC Reference 0 +#define ADI_4_AUX_O_ADCREF0 0x0000000A + +// ADC Reference 1 +#define ADI_4_AUX_O_ADCREF1 0x0000000B + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX0 +// +//***************************************************************************** +// Field: [3:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ADCVREFP Internal. Only to be used through TI provided API. +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX1 +// +//***************************************************************************** +// Field: [7:0] COMPA_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX2 +// +//***************************************************************************** +// Field: [7:3] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// ATEST1 Internal. Only to be used through TI provided API. +// ATEST0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 + +// Field: [2:0] COMPB_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_COMPB_REF_W 3 +#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 +#define ADI_4_AUX_MUX2_COMPB_REF_S 0 +#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX3 +// +//***************************************************************************** +// Field: [7:0] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ISRC +// +//***************************************************************************** +// Field: [7:2] TRIM +// +// Adjust current from current source. +// +// Output currents may be combined to get desired total current. +// ENUMs: +// 11P75U 11.75 uA +// 4P5U 4.5 uA +// 2P0U 2.0 uA +// 1P0U 1.0 uA +// 0P5U 0.5 uA +// 0P25U 0.25 uA +// NC No current connected +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 + +// Field: [0] EN +// +// Current source enable +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_COMP +// +//***************************************************************************** +// Field: [7] COMPA_REF_RES_EN +// +// Enables 400kohm resistance from COMPA reference node to ground. Used with +// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 + +// Field: [6] COMPA_REF_CURR_EN +// +// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires +// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for +// cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 + +// Field: [5:3] COMPB_TRIM +// +// COMPB voltage reference trim temperature coded: +// ENUMs: +// DIV4 Divide reference by 4 +// DIV3 Divide reference by 3 +// DIV2 Divide reference by 2 +// DIV1 No reference division +#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 + +// Field: [2] COMPB_EN +// +// COMPB enable +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 + +// Field: [0] COMPA_EN +// +// COMPA enable +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX4 +// +//***************************************************************************** +// Field: [7:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC0 +// +//***************************************************************************** +// Field: [7] SMPL_MODE +// +// ADC Sampling mode: +// +// 0: Synchronous mode +// 1: Asynchronous mode +// +// The ADC does a sample-and-hold before conversion. In synchronous mode the +// sampling starts when the ADC clock detects a rising edge on the trigger +// signal. Jitter/uncertainty will be inferred in the detection if the trigger +// signal originates from a domain that is asynchronous to the ADC clock. +// SMPL_CYCLE_EXP determines the the duration of sampling. +// Conversion starts immediately after sampling ends. +// +// In asynchronous mode the sampling is continuous when enabled. Sampling ends +// and conversion starts immediately with the rising edge of the trigger +// signal. Sampling restarts when the conversion has finished. +// Asynchronous mode is useful when it is important to avoid jitter in the +// sampling instant of an externally driven signal +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 + +// Field: [6:3] SMPL_CYCLE_EXP +// +// Controls the sampling duration before conversion when the ADC is operated in +// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous +// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. +// ENUMs: +// 10P9_MS 65536x 6 MHz clock periods = 10.9ms +// 5P46_MS 32768x 6 MHz clock periods = 5.46ms +// 2P73_MS 16384x 6 MHz clock periods = 2.73ms +// 1P37_MS 8192x 6 MHz clock periods = 1.37ms +// 682_US 4096x 6 MHz clock periods = 682us +// 341_US 2048x 6 MHz clock periods = 341us +// 170_US 1024x 6 MHz clock periods = 170us +// 85P3_US 512x 6 MHz clock periods = 85.3us +// 42P6_US 256x 6 MHz clock periods = 42.6us +// 21P3_US 128x 6 MHz clock periods = 21.3us +// 10P6_US 64x 6 MHz clock periods = 10.6us +// 5P3_US 32x 6 MHz clock periods = 5.3us +// 2P7_US 16x 6 MHz clock periods = 2.7us +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 + +// Field: [1] RESET_N +// +// Reset ADC digital subchip, active low. ADC must be reset every time it is +// reconfigured. +// +// 0: Reset +// 1: Normal operation +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 + +// Field: [0] EN +// +// ADC Enable +// +// 0: Disable +// 1: Enable +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC1 +// +//***************************************************************************** +// Field: [0] SCALE_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF0 +// +//***************************************************************************** +// Field: [6] REF_ON_IDLE +// +// Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. +// +// Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 + +// Field: [5] IOMUX +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 + +// Field: [4] EXT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 + +// Field: [3] SRC +// +// ADC reference source: +// +// 0: Fixed reference = 4.3V +// 1: Relative reference = VDDS +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 + +// Field: [0] EN +// +// ADC reference module enable: +// +// 0: ADC reference module powered down +// 1: ADC reference module enabled +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF1 +// +//***************************************************************************** +// Field: [5:0] VTRIM +// +// Trim output voltage of ADC fixed reference (64 steps, 2's complement). +// Applies only for ADCREF0.SRC = 0. +// +// Examples: +// 0x00 - nominal voltage 1.43V +// 0x01 - nominal + 0.4% 1.435V +// 0x3F - nominal - 0.4% 1.425V +// 0x1F - maximum voltage 1.6V +// 0x20 - minimum voltage 1.3V +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 + + +#endif // __ADI_4_AUX__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aon_batmon.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_batmon.h new file mode 100644 index 0000000000..b6727114f5 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_batmon.h @@ -0,0 +1,340 @@ +/****************************************************************************** +* Filename: hw_aon_batmon_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_BATMON_H__ +#define __HW_AON_BATMON_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_BATMON component +// +//***************************************************************************** +// Internal +#define AON_BATMON_O_CTL 0x00000000 + +// Internal +#define AON_BATMON_O_MEASCFG 0x00000004 + +// Internal +#define AON_BATMON_O_TEMPP0 0x0000000C + +// Internal +#define AON_BATMON_O_TEMPP1 0x00000010 + +// Internal +#define AON_BATMON_O_TEMPP2 0x00000014 + +// Internal +#define AON_BATMON_O_BATMONP0 0x00000018 + +// Internal +#define AON_BATMON_O_BATMONP1 0x0000001C + +// Internal +#define AON_BATMON_O_IOSTRP0 0x00000020 + +// Internal +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 + +// Last Measured Battery Voltage +#define AON_BATMON_O_BAT 0x00000028 + +// Battery Update +#define AON_BATMON_O_BATUPD 0x0000002C + +// Temperature +#define AON_BATMON_O_TEMP 0x00000030 + +// Temperature Update +#define AON_BATMON_O_TEMPUPD 0x00000034 + +//***************************************************************************** +// +// Register: AON_BATMON_O_CTL +// +//***************************************************************************** +// Field: [1] CALC_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 + +// Field: [0] MEAS_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_MEASCFG +// +//***************************************************************************** +// Field: [1:0] PER +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 32CYC Internal. Only to be used through TI provided API. +// 16CYC Internal. Only to be used through TI provided API. +// 8CYC Internal. Only to be used through TI provided API. +// CONT Internal. Only to be used through TI provided API. +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP0 +// +//***************************************************************************** +// Field: [7:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP2 +// +//***************************************************************************** +// Field: [4:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP0 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP0_CFG_W 6 +#define AON_BATMON_BATMONP0_CFG_M 0x0000003F +#define AON_BATMON_BATMONP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_IOSTRP0 +// +//***************************************************************************** +// Field: [5:4] CFG2 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 + +// Field: [3:0] CFG1 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_FLASHPUMPP0 +// +//***************************************************************************** +// Field: [8] FALLB +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 + +// Field: [7:6] HIGHLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 + +// Field: [5] LOWLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 + +// Field: [4] OVR +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 + +// Field: [3:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New battery voltage is present. +// +// Write 1 to clear the status. +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMP +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature value. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New temperature is present. +// +// Write 1 to clear the status. +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 + + +#endif // __AON_BATMON__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aon_event.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_event.h new file mode 100644 index 0000000000..389cb696c2 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_event.h @@ -0,0 +1,1533 @@ +/****************************************************************************** +* Filename: hw_aon_event_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_EVENT_H__ +#define __HW_AON_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_EVENT component +// +//***************************************************************************** +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL 0x00000000 + +// Wake-up Selector For AUX +#define AON_EVENT_O_AUXWUSEL 0x00000004 + +// Event Selector For MCU Event Fabric +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 + +// RTC Capture Event Selector For AON_RTC +#define AON_EVENT_O_RTCSEL 0x0000000C + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL +// +//***************************************************************************** +// Field: [29:24] WU3_EV +// +// MCU Wakeup Source #3 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 + +// Field: [21:16] WU2_EV +// +// MCU Wakeup Source #2 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 + +// Field: [13:8] WU1_EV +// +// MCU Wakeup Source #1 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 + +// Field: [5:0] WU0_EV +// +// MCU Wakeup Source #0 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_AUXWUSEL +// +//***************************************************************************** +// Field: [21:16] WU2_EV +// +// AUX Wakeup Source #2 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 +#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 + +// Field: [13:8] WU1_EV +// +// AUX Wakeup Source #1 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 +#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 + +// Field: [5:0] WU0_EV +// +// AUX Wakeup Source #0 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 +#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_EVTOMCUSEL +// +//***************************************************************************** +// Field: [21:16] AON_PROG2_EV +// +// Event selector for AON_PROG2 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 + +// Field: [13:8] AON_PROG1_EV +// +// Event selector for AON_PROG1 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 + +// Field: [5:0] AON_PROG0_EV +// +// Event selector for AON_PROG0 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_RTCSEL +// +//***************************************************************************** +// Field: [5:0] RTC_CH1_CAPT_EV +// +// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer +// to AON_RTC:CH1CAPT +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 + + +#endif // __AON_EVENT__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aon_ioc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_ioc.h new file mode 100644 index 0000000000..4c6e404a70 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_ioc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: hw_aon_ioc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_IOC_H__ +#define __HW_AON_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_IOC component +// +//***************************************************************************** +// Internal +#define AON_IOC_O_IOSTRMIN 0x00000000 + +// Internal +#define AON_IOC_O_IOSTRMED 0x00000004 + +// Internal +#define AON_IOC_O_IOSTRMAX 0x00000008 + +// IO Latch Control +#define AON_IOC_O_IOCLATCH 0x0000000C + +// SCLK_LF External Output Control +#define AON_IOC_O_CLK32KCTL 0x00000010 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMIN +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMED +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMAX +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOCLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Controls latches between MCU IOC and AON_IOC. +// +// The latches are transparent by default. +// +// They must be closed prior to power off the domain(s) controlling the IOs in +// order to preserve IO values on external pins. +// ENUMs: +// TRANSP Latches are transparent, meaning the value of the +// IO is directly controlled by the GPIO or +// peripheral value +// STATIC Latches are static, meaning the current value on +// the IO pin is frozen by latches and kept even +// if GPIO module or a peripheral module is turned +// off +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AON_IOC_O_CLK32KCTL +// +//***************************************************************************** +// Field: [0] OE_N +// +// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. +// IOC:IOCFG0.PORT_ID) set to AON_CLK32K. +// 1: Output enable not active +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 + + +#endif // __AON_IOC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aon_rtc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_rtc.h new file mode 100644 index 0000000000..79dbbe9fcf --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_rtc.h @@ -0,0 +1,508 @@ +/****************************************************************************** +* Filename: hw_aon_rtc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_RTC_H__ +#define __HW_AON_RTC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_RTC component +// +//***************************************************************************** +// Control +#define AON_RTC_O_CTL 0x00000000 + +// Event Flags, RTC Status +#define AON_RTC_O_EVFLAGS 0x00000004 + +// Second Counter Value, Integer Part +#define AON_RTC_O_SEC 0x00000008 + +// Second Counter Value, Fractional Part +#define AON_RTC_O_SUBSEC 0x0000000C + +// Subseconds Increment +#define AON_RTC_O_SUBSECINC 0x00000010 + +// Channel Configuration +#define AON_RTC_O_CHCTL 0x00000014 + +// Channel 0 Compare Value +#define AON_RTC_O_CH0CMP 0x00000018 + +// Channel 1 Compare Value +#define AON_RTC_O_CH1CMP 0x0000001C + +// Channel 2 Compare Value +#define AON_RTC_O_CH2CMP 0x00000020 + +// Channel 2 Compare Value Auto-increment +#define AON_RTC_O_CH2CMPINC 0x00000024 + +// Channel 1 Capture Value +#define AON_RTC_O_CH1CAPT 0x00000028 + +// AON Synchronization +#define AON_RTC_O_SYNC 0x0000002C + +//***************************************************************************** +// +// Register: AON_RTC_O_CTL +// +//***************************************************************************** +// Field: [18:16] COMB_EV_MASK +// +// Eventmask selecting which delayed events that form the combined event. +// ENUMs: +// CH2 Use Channel 2 delayed event in combined event +// CH1 Use Channel 1 delayed event in combined event +// CH0 Use Channel 0 delayed event in combined event +// NONE No event is selected for combined event. +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 + +// Field: [11:8] EV_DELAY +// +// Number of SCLK_LF clock cycles waited before generating delayed events. +// (Common setting for all RTC cannels) the delayed event is delayed +// ENUMs: +// D144 Delay by 144 clock cycles +// D128 Delay by 128 clock cycles +// D112 Delay by 112 clock cycles +// D96 Delay by 96 clock cycles +// D80 Delay by 80 clock cycles +// D64 Delay by 64 clock cycles +// D48 Delay by 48 clock cycles +// D32 Delay by 32 clock cycles +// D16 Delay by 16 clock cycles +// D8 Delay by 8 clock cycles +// D4 Delay by 4 clock cycles +// D2 Delay by 2 clock cycles +// D1 Delay by 1 clock cycles +// D0 No delay on delayed event +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 + +// Field: [7] RESET +// +// RTC Counter reset. +// +// Writing 1 to this bit will reset the RTC counter. +// +// This bit is cleared when reset takes effect +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 + +// Field: [2] RTC_4KHZ_EN +// +// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 +// which is used by AUX timer. +// +// 0: RTC_4KHZ signal is forced to 0 +// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 + +// Field: [1] RTC_UPD_EN +// +// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is +// SCLK_LF divided by 2 +// +// 0: RTC_UPD signal is forced to 0 +// 1: RTC_UPD signal is toggling @16 kHz +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 + +// Field: [0] EN +// +// Enable RTC counter +// +// 0: Halted (frozen) +// 1: Running +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_EVFLAGS +// +//***************************************************************************** +// Field: [16] CH2 +// +// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or +// passes the CH2CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH2CMP provided that the channel is enabled and the new value matches any +// time between next RTC value and 1 second in the past +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +// +// AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it +// using AUX_WUC:WUEVCLR.AON_RTC_CH2. +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 + +// Field: [8] CH1 +// +// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: +// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP +// value. +// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH1CMP provided that the channel is enabled, in compare mode and the new +// value matches any time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 + +// Field: [0] CH0 +// +// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or +// passes the CH0CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH0CMP provided that the channels is enabled and the new value matches any +// time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in seconds. +// +// When reading this register the content of SUBSEC.VALUE is simultaneously +// latched. A consistent reading of the combined Real Time Clock can be +// obtained by first reading this register, then reading SUBSEC register. +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in fractions of a second +// (VALUE/2^32 seconds) at the time when SEC register was read. +// +// Examples : +// - 0x0000_0000 = 0.0 sec +// - 0x4000_0000 = 0.25 sec +// - 0x8000_0000 = 0.5 sec +// - 0xC000_0000 = 0.75 sec +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSECINC +// +//***************************************************************************** +// Field: [23:0] VALUEINC +// +// This value compensates for a SCLK_LF clock which has an offset from 32768 +// Hz. +// +// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF +// clock frequency in Hertz +// +// This value is added to SUBSEC.VALUE on every cycle, and carry of this is +// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with +// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a +// hidden 6-bit register that generates a carry into the above mentioned +// addition on overflow. +// The default value corresponds to incrementing by precisely 1/32768 of a +// second. +// +// NOTE: This register is read only. Modification of the register value must be +// done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and +// AUX_WUC:RTCSUBSECINCCTL +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CHCTL +// +//***************************************************************************** +// Field: [18] CH2_CONT_EN +// +// Set to enable continuous operation of Channel 2 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 + +// Field: [16] CH2_EN +// +// RTC Channel 2 Enable +// +// 0: Disable RTC Channel 2 +// 1: Enable RTC Channel 2 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 + +// Field: [9] CH1_CAPT_EN +// +// Set Channel 1 mode +// +// 0: Compare mode (default) +// 1: Capture mode +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 + +// Field: [8] CH1_EN +// +// RTC Channel 1 Enable +// +// 0: Disable RTC Channel 1 +// 1: Enable RTC Channel 1 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 + +// Field: [0] CH0_EN +// +// RTC Channel 0 Enable +// +// 0: Disable RTC Channel 0 +// 1: Enable RTC Channel 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH0CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 0 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 1 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 2 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMPINC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every +// channel 2 compare event. +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CAPT +// +//***************************************************************************** +// Field: [31:16] SEC +// +// Value of SEC.VALUE bits 15:0 at capture time. +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 + +// Field: [15:0] SUBSEC +// +// Value of SUBSEC.VALUE bits 31:16 at capture time. +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNC +// +//***************************************************************************** +// Field: [0] WBUSY +// +// This register will always return 0,- however it will not return the value +// until there are no outstanding write requests between MCU and AON +// +// Note: Writing to this register prior to reading will force a wait until next +// SCLK_LF edge. This is recommended for syncing read registers from AON when +// waking up from sleep +// Failure to do so may result in reading AON values from prior to going to +// sleep +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 + + +#endif // __AON_RTC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aon_sysctl.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_sysctl.h new file mode 100644 index 0000000000..329b7b2446 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_sysctl.h @@ -0,0 +1,348 @@ +/****************************************************************************** +* Filename: hw_aon_sysctl_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_SYSCTL_H__ +#define __HW_AON_SYSCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_SYSCTL component +// +//***************************************************************************** +// Power Management +#define AON_SYSCTL_O_PWRCTL 0x00000000 + +// Reset Management +#define AON_SYSCTL_O_RESETCTL 0x00000004 + +// Sleep Mode +#define AON_SYSCTL_O_SLEEPCTL 0x00000008 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_PWRCTL +// +//***************************************************************************** +// Field: [2] DCDC_ACTIVE +// +// Select to use DCDC regulator for VDDR in active mode +// +// 0: Use GLDO for regulation of VDDRin active mode. +// 1: Use DCDC for regulation of VDDRin active mode. +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 + +// Field: [1] EXT_REG_MODE +// +// Status of source for VDDRsupply: +// +// 0: DCDC/GLDO are generating VDDR +// 1: DCDC/GLDO are bypassed, external regulator supplies VDDR +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 + +// Field: [0] DCDC_EN +// +// Select to use DCDC regulator during recharge of VDDR +// +// 0: Use GLDO for recharge of VDDR +// 1: Use DCDC for recharge of VDDR +// +// Note: This bitfield should be set to the same as DCDC_ACTIVE +#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_RESETCTL +// +//***************************************************************************** +// Field: [31] SYSRESET +// +// Cold reset register. Writing 1 to this bitfield will reset the entire chip +// and cause boot code to run again. +// +// 0: No effect +// 1: Generate system reset. Appears as SYSRESET in RESET_SRC. +#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 + +// Field: [25] BOOT_DET_1_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 + +// Field: [24] BOOT_DET_0_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 + +// Field: [17] BOOT_DET_1_SET +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 + +// Field: [16] BOOT_DET_0_SET +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 + +// Field: [15] WU_FROM_SD +// +// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from +// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin +// being forced low) +// +// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup +// sources. +// +// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC +// 1: A wakeup has occurred from SHUTDOWN +// +// Note: This flag can not be cleared and will therefor remain valid untill +// poweroff/reset +#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 + +// Field: [14] GPIO_WU_FROM_SD +// +// A wakeup from SHUTDOWN on an IO event has occurred +// +// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup +// sources. +// +// 0: The wakeup did not occur from SHUTDOWN on an IO event +// 1: A wakeup from SHUTDOWN occurred from an IO event +// +// The case where WU_FROM_SD is asserted but this bitfield is not asserted will +// only occur in a debug session. The boot code will not proceed with wakeup +// from SHUTDOWN procedure until this bitfield is asserted as well. +// +// Note: This flag can not be cleared and will therefor remain valid untill +// poweroff/reset +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 + +// Field: [13] BOOT_DET_1 +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 + +// Field: [12] BOOT_DET_0 +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 + +// Field: [11] VDDS_LOSS_EN_OVR +// +// Override of VDDS_LOSS_EN +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 +// 1: Brown out detect of VDDS generates system reset (regardless of +// VDDS_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 + +// Field: [10] VDDR_LOSS_EN_OVR +// +// Override of VDDR_LOSS_EN +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 +// 1: Brown out detect of VDDR generates system reset (regardless of +// VDDR_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 + +// Field: [9] VDD_LOSS_EN_OVR +// +// Override of VDD_LOSS_EN +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 +// 1: Brown out detect of VDD generates system reset (regardless of +// VDD_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 + +// Field: [7] VDDS_LOSS_EN +// +// Controls reset generation in case VDDS is lost +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDS generates system reset +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 + +// Field: [6] VDDR_LOSS_EN +// +// Controls reset generation in case VDDR is lost +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDR generates system reset +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 + +// Field: [5] VDD_LOSS_EN +// +// Controls reset generation in case VDD is lost +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 +// 1: Brown out detect of VDD generates system reset +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 + +// Field: [4] CLK_LOSS_EN +// +// Controls reset generation in case SCLK_LF is lost. (provided that clock +// loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) +// +// Note: Clock loss reset generation must be disabled before SCLK_LF clock +// source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled +// untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do +// so may result in a spurious system reset. Clock loss reset generation can be +// disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN +// +// 0: Clock loss is ignored +// 1: Clock loss generates system reset +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 + +// Field: [3:1] RESET_SRC +// +// Shows the source of the last system reset: +// Occurrence of one of the reset sources may trigger several other reset +// sources as essential parts of the system are undergoing reset. This field +// will report the root cause of the reset (not the other resets that are +// consequence of the system reset). +// To support this feature the actual register is not captured before the reset +// source being released. If a new reset source is triggered, in a window of +// four 32 kHz periods after the previous has been released, this register +// may indicate Power on reset as source. +// ENUMs: +// WARMRESET Software reset via PRCM warm reset request +// SYSRESET Software reset via SYSRESET register +// CLK_LOSS Clock loss detect +// VDDR_LOSS Brown out detect on VDDR +// VDD_LOSS Brown out detect on VDD +// VDDS_LOSS Brown out detect on VDDS +// PIN_RESET Reset pin +// PWR_ON Power on reset +#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 +#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 +#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_SLEEPCTL +// +//***************************************************************************** +// Field: [0] IO_PAD_SLEEP_DIS +// +// Controls the I/O pad sleep mode. The boot code will set this bitfield +// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set +// ). +// +// 0: I/O pad sleep mode is enabled, ie all pads are latched and can not +// toggle. +// 1: I/O pad sleep mode is disabled +// +// Application software may want to reconfigure the state for all IO's before +// setting this bitfield upon waking up from a SHUTDOWN. +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 + + +#endif // __AON_SYSCTL__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aon_wuc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_wuc.h new file mode 100644 index 0000000000..8cd45e4284 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aon_wuc.h @@ -0,0 +1,674 @@ +/****************************************************************************** +* Filename: hw_aon_wuc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_WUC_H__ +#define __HW_AON_WUC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_WUC component +// +//***************************************************************************** +// MCU Clock Management +#define AON_WUC_O_MCUCLK 0x00000000 + +// AUX Clock Management +#define AON_WUC_O_AUXCLK 0x00000004 + +// MCU Configuration +#define AON_WUC_O_MCUCFG 0x00000008 + +// AUX Configuration +#define AON_WUC_O_AUXCFG 0x0000000C + +// AUX Control +#define AON_WUC_O_AUXCTL 0x00000010 + +// Power Status +#define AON_WUC_O_PWRSTAT 0x00000014 + +// Shutdown Control +#define AON_WUC_O_SHUTDOWN 0x00000018 + +// Control 0 +#define AON_WUC_O_CTL0 0x00000020 + +// Control 1 +#define AON_WUC_O_CTL1 0x00000024 + +// Recharge Controller Configuration +#define AON_WUC_O_RECHARGECFG 0x00000030 + +// Recharge Controller Status +#define AON_WUC_O_RECHARGESTAT 0x00000034 + +// Oscillator Configuration +#define AON_WUC_O_OSCCFG 0x00000038 + +// JTAG Configuration +#define AON_WUC_O_JTAGCFG 0x00000040 + +// JTAG USERCODE +#define AON_WUC_O_JTAGUSERCODE 0x00000044 + +//***************************************************************************** +// +// Register: AON_WUC_O_MCUCLK +// +//***************************************************************************** +// Field: [2] RCOSC_HF_CAL_DONE +// +// MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can +// not be used until this bit is set. +// +// 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. +// 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF +// is safe +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 + +// Field: [1:0] PWR_DWN_SRC +// +// Controls the clock source for the entire MCU domain while MCU is requesting +// powerdown. +// +// When MCU requests powerdown with SCLK_HF as source, then WUC will switch +// over to this clock source during powerdown, and automatically switch back to +// SCLK_HF when MCU is no longer requesting powerdown and system is back in +// active mode. +// ENUMs: +// SCLK_LF Use SCLK_LF in Powerdown +// NONE No clock in Powerdown +#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCLK +// +//***************************************************************************** +// Field: [12:11] PWR_DWN_SRC +// +// When AUX requests powerdown with SCLK_HF as source, then WUC will switch +// over to this clock source during powerdown, and automatically switch back to +// SCLK_HF when AUX system is back in active mode +// ENUMs: +// SCLK_LF Use SCLK_LF in Powerdown +// NONE No clock in Powerdown +#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 + +// Field: [10:8] SCLK_HF_DIV +// +// Select the AUX clock divider for SCLK_HF +// +// NB: It is not supported to change the AUX clock divider while SCLK_HF is +// active source for AUX +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 + +// Field: [2:0] SRC +// +// Selects the clock source for AUX: +// +// NB: Switching the clock source is guaranteed to be glitchless +// ENUMs: +// SCLK_LF LF Clock (SCLK_LF) +// SCLK_HF HF Clock (SCLK_HF) +#define AON_WUC_AUXCLK_SRC_W 3 +#define AON_WUC_AUXCLK_SRC_M 0x00000007 +#define AON_WUC_AUXCLK_SRC_S 0 +#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 +#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 + +//***************************************************************************** +// +// Register: AON_WUC_O_MCUCFG +// +//***************************************************************************** +// Field: [17] VIRT_OFF +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 +#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_S 17 + +// Field: [16] FIXED_WU_EN +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 + +// Field: [3:0] SRAM_RET_EN +// +// MCU SRAM is partitioned into 4 banks . This register controls which of the +// banks that has retention during MCU power off +// ENUMs: +// RET_FULL Retention on for all banks (SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2 and SRAM:BANK3) +// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 and +// SRAM:BANK2 +// RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 +// RET_LEVEL1 Retention on for SRAM:BANK0 +// RET_NONE Retention is disabled +#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 +#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCFG +// +//***************************************************************************** +// Field: [0] RAM_RET_EN +// +// This bit controls retention mode for the AUX_RAM:BANK0: +// +// 0: Retention is disabled +// 1: Retention is enabled +// +// NB: If retention is disabled, the AUX_RAM will be powered off when it would +// otherwise be put in retention mode +#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 +#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCTL +// +//***************************************************************************** +// Field: [31] RESET_REQ +// +// Reset request for AUX. Writing 1 to this register will assert reset to AUX. +// The reset will be held until the bit is cleared again. +// +// 0: AUX reset pin will be deasserted +// 1: AUX reset pin will be asserted +#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 +#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_S 31 + +// Field: [2] SCE_RUN_EN +// +// Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin +// when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. +// +// Setting this bit will assure that AUX_SCE execution starts as soon as AUX +// power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX +// power domain has been off) +// +// 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 +// 1: AUX_SCE execution is enabled. +#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 + +// Field: [1] SWEV +// +// Writing 1 sets the software event to the AUX domain, which can be read +// through AUX_WUC:WUEVFLAGS.AON_SW. +// +// This event is normally cleared by AUX_SCE through the +// AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this +// register. +// +// Reading 0 means that there is no outstanding software event for AUX. +// +// Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from +// AUX. +#define AON_WUC_AUXCTL_SWEV 0x00000002 +#define AON_WUC_AUXCTL_SWEV_BITN 1 +#define AON_WUC_AUXCTL_SWEV_M 0x00000002 +#define AON_WUC_AUXCTL_SWEV_S 1 + +// Field: [0] AUX_FORCE_ON +// +// Forces the AUX domain into active mode, overriding the requests from +// AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. +// Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will +// set the AUX domain into active mode. +// +// MCU must set this bit in order to access the AUX peripherals. +// The AUX domain status can be read from PWRSTAT.AUX_PD_ON +// +// 0: AUX is allowed to Power Off, Power Down or Disconnect. +// 1: AUX Power OFF, Power Down or Disconnect requests will be overruled +#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_PWRSTAT +// +//***************************************************************************** +// Field: [9] AUX_PWR_DWN +// +// Indicates the AUX powerdown state when AUX domain is powered up. +// +// 0: Active mode +// 1: AUX Powerdown request has been granted +#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 + +// Field: [6] JTAG_PD_ON +// +// Indicates JTAG power state: +// +// 0: JTAG is powered off +// 1: JTAG is powered on +#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 + +// Field: [5] AUX_PD_ON +// +// Indicates AUX power state: +// +// 0: AUX is not ready for use ( may be powered off or in power state +// transition ) +// 1: AUX is powered on, connected to bus and ready for use, +#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 + +// Field: [4] MCU_PD_ON +// +// Indicates MCU power state: +// +// 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not +// be reliable +// 1: MCU Power sequencing is finalized and all MCU_AONIF registers are +// reliable +#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 + +// Field: [2] AUX_BUS_CONNECTED +// +// Indicates that AUX Bus is connected: +// +// 0: AUX bus is not connected +// 1: AUX bus is connected ( idle_ack = 0 ) +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 + +// Field: [1] AUX_RESET_DONE +// +// Indicates Reset Done from AUX: +// +// 0: AUX is being reset +// 1: AUX reset is released +#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 + +//***************************************************************************** +// +// Register: AON_WUC_O_SHUTDOWN +// +//***************************************************************************** +// Field: [0] EN +// +// Writing a 1 to this bit forces a shutdown request to be registered and all +// I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. +// Writing 0 will cancel a registered shutdown request and open th I/O latches +// residing in the PAD ring. +// +// A registered shutdown request takes effect the next time power down +// conditions exists. At this time, the will not enter Powerdown mode, but +// instead it will turn off all internal powersupplies, effectively putting the +// device into Shutdown mode. +#define AON_WUC_SHUTDOWN_EN 0x00000001 +#define AON_WUC_SHUTDOWN_EN_BITN 0 +#define AON_WUC_SHUTDOWN_EN_M 0x00000001 +#define AON_WUC_SHUTDOWN_EN_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_CTL0 +// +//***************************************************************************** +// Field: [8] PWR_DWN_DIS +// +// Controls whether MCU and AUX requesting to be powered off will enable a +// transition to powerdown: +// +// 0: Enabled +// 1: Disabled +#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 +#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 + +// Field: [3] AUX_SRAM_ERASE +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 + +// Field: [2] MCU_SRAM_ERASE +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 + +//***************************************************************************** +// +// Register: AON_WUC_O_CTL1 +// +//***************************************************************************** +// Field: [1] MCU_RESET_SRC +// +// Indicates source of last MCU Voltage Domain warm reset request: +// +// 0: MCU SW reset +// 1: JTAG reset +// +// This bit can only be cleared by writing a 1 to it +#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 +#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 + +// Field: [0] MCU_WARM_RESET +// +// Indicates type of last MCU Voltage Domain reset: +// +// 0: Last MCU reset was not a warm reset +// 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated +// in MCU_RESET_SRC) +// +// This bit can only be cleared by writing a 1 to it +#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 +#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_RECHARGECFG +// +//***************************************************************************** +// Field: [31] ADAPTIVE_EN +// +// Enable adaptive recharge +// +// Note: Recharge can be turned completely of by setting MAX_PER_E=7 and +// MAX_PER_M=31 and this bitfield to 0 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 + +// Field: [23:20] C2 +// +// Gain factor for adaptive recharge algorithm +// +// period_new=period * ( 1+/-(2^-C1+2^-C2) ) +// Valid values for C2 is 2 to 10 +// +// Note: Rounding may cause adaptive recharge not to start for very small +// values of both Gain and Initial period. Criteria for algorithm to start is +// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 +#define AON_WUC_RECHARGECFG_C2_W 4 +#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 +#define AON_WUC_RECHARGECFG_C2_S 20 + +// Field: [19:16] C1 +// +// Gain factor for adaptive recharge algorithm +// +// period_new=period * ( 1+/-(2^-C1+2^-C2) ) +// Valid values for C1 is 1 to 10 +// +// Note: Rounding may cause adaptive recharge not to start for very small +// values of both Gain and Initial period. Criteria for algorithm to start is +// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 +#define AON_WUC_RECHARGECFG_C1_W 4 +#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 +#define AON_WUC_RECHARGECFG_C1_S 16 + +// Field: [15:11] MAX_PER_M +// +// This register defines the maximum period that the recharge algorithm can +// take, i.e. it defines the maximum number of cycles between 2 recharges. +// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit +// exponent: +// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E +// This field sets the mantissa of MAXCYCLES +#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 +#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 + +// Field: [10:8] MAX_PER_E +// +// This register defines the maximum period that the recharge algorithm can +// take, i.e. it defines the maximum number of cycles between 2 recharges. +// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit +// exponent: +// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E +// This field sets the exponent MAXCYCLES +#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 +#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 + +// Field: [7:3] PER_M +// +// Number of 32 KHz clocks between activation of recharge controller +// For recharge algorithm, PERIOD is the initial period when entering powerdown +// mode. The adaptive recharge algorithm will not change this register +// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 +// bit exponent: +// This field sets the Mantissa of the Period. +// PERIOD=(PER_M*16+15)*2^PER_E +#define AON_WUC_RECHARGECFG_PER_M_W 5 +#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_WUC_RECHARGECFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Number of 32 KHz clocks between activation of recharge controller +// For recharge algorithm, PERIOD is the initial period when entering powerdown +// mode. The adaptive recharge algorithm will not change this register +// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 +// bit exponent: +// This field sets the Exponent of the Period. +// PERIOD=(PER_M*16+15)*2^PER_E +#define AON_WUC_RECHARGECFG_PER_E_W 3 +#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 +#define AON_WUC_RECHARGECFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_RECHARGESTAT +// +//***************************************************************************** +// Field: [19:16] VDDR_SMPLS +// +// The last 4 VDDR samples, bit 0 being the newest. +// +// The register is being updated in every recharge period with a shift left, +// and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case +// VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be +// shifted in. +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 + +// Field: [15:0] MAX_USED_PER +// +// The maximum value of recharge period seen with VDDR>threshold. +// +// The VDDR voltage is compared against the threshold voltage at just before +// each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max +// ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track +// the recharge period where VDDR is decharged to the threshold value. We can +// therefore use the value as an indication of the leakage current during +// recharge. +// +// This bitfield is cleared to 0 when writing this register. +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_OSCCFG +// +//***************************************************************************** +// Field: [7:3] PER_M +// +// Number of 32 KHz clocks between oscillator amplitude calibrations. +// When this counter expires, an oscillator amplitude compensation is triggered +// immediately in Active mode. When this counter expires in Powerdown mode an +// internal flag is set such that the amplitude compensation is postponed until +// the next recharge occurs. +// +// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and +// 3 bit exponent +// PERIOD=(PER_M*16+15)*2^PER_E +// This field sets the mantissa +// Note: Oscillator amplitude calibration is turned of when both this bitfield +// and PER_E are set to 0 +#define AON_WUC_OSCCFG_PER_M_W 5 +#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 +#define AON_WUC_OSCCFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Number of 32 KHz clocks between oscillator amplitude calibrations. +// When this counter expires, an oscillator amplitude compensation is triggered +// immediately in Active mode. When this counter expires in Powerdown mode an +// internal flag is set such that the amplitude compensation is postponed until +// the next recharge occurs. +// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and +// 3 bit exponent +// PERIOD=(PER_M*16+15)*2^PER_E +// This field sets the exponent +// Note: Oscillator amplitude calibration is turned of when both PER_M and +// this bitfield are set to 0 +#define AON_WUC_OSCCFG_PER_E_W 3 +#define AON_WUC_OSCCFG_PER_E_M 0x00000007 +#define AON_WUC_OSCCFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_JTAGCFG +// +//***************************************************************************** +// Field: [8] JTAG_PD_FORCE_ON +// +// Controls JTAG PowerDomain power state: +// +// 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be +// powered off unless a debugger is attached) +// 1: JTAG Power Domain is forced on, independent of debug subsystem. +// +// NB: The reset value causes JTAG Power Domain to be powered on by default. +// Software must clear this bit to turn off the JTAG Power Domain +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 + +//***************************************************************************** +// +// Register: AON_WUC_O_JTAGUSERCODE +// +//***************************************************************************** +// Field: [31:0] USER_CODE +// +// 32-bit JTAG USERCODE register feeding main JTAG TAP +// NB: This field can be locked +#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 +#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 + + +#endif // __AON_WUC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_aiodio.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_aiodio.h new file mode 100644 index 0000000000..665d6f7dc5 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_aiodio.h @@ -0,0 +1,481 @@ +/****************************************************************************** +* Filename: hw_aux_aiodio_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_AIODIO_H__ +#define __HW_AUX_AIODIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_AIODIO component +// +//***************************************************************************** +// General Purpose Input Output Data Out +#define AUX_AIODIO_O_GPIODOUT 0x00000000 + +// Input Output Mode +#define AUX_AIODIO_O_IOMODE 0x00000004 + +// General Purpose Input Output Data In +#define AUX_AIODIO_O_GPIODIN 0x00000008 + +// General Purpose Input Output Data Out Set +#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C + +// General Purpose Input Output Data Out Clear +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 + +// General Purpose Input Output Data Out Toggle +#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 + +// General Purpose Input Output Digital Input Enable +#define AUX_AIODIO_O_GPIODIE 0x00000018 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUT +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODE +// +//***************************************************************************** +// Field: [15:14] IO7 +// +// Select mode for AUXIO[8i+7]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is driven low. +// +// When GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 7 is 0: +// AUXIO[8i+7] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 7 is 1: +// AUXIO[8i+7] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 7 drives +// AUXIO[8i+7]. +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 + +// Field: [13:12] IO6 +// +// Select mode for AUXIO[8i+6]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is driven low. +// +// When GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 6 is 0: +// AUXIO[8i+6] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 6 is 1: +// AUXIO[8i+6] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 6 drives +// AUXIO[8i+6]. +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 + +// Field: [11:10] IO5 +// +// Select mode for AUXIO[8i+5]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is driven low. +// +// When GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 5 is 0: +// AUXIO[8i+5] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 5 is 1: +// AUXIO[8i+5] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 5 drives +// AUXIO[8i+5]. +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 + +// Field: [9:8] IO4 +// +// Select mode for AUXIO[8i+4]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is driven low. +// +// When GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 4 is 0: +// AUXIO[8i+4] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 4 is 1: +// AUXIO[8i+4] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 4 drives +// AUXIO[8i+4]. +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 + +// Field: [7:6] IO3 +// +// Select mode for AUXIO[8i+3]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is driven low. +// +// When GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 3 is 0: +// AUXIO[8i+3] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 3 is 1: +// AUXIO[8i+3] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 3 drives +// AUXIO[8i+3]. +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 + +// Field: [5:4] IO2 +// +// Select mode for AUXIO[8i+2]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is driven low. +// +// When GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 2 is 0: +// AUXIO[8i+2] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 2 is 1: +// AUXIO[8i+2] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 2 drives +// AUXIO[8i+2]. +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 + +// Field: [3:2] IO1 +// +// Select mode for AUXIO[8i+1]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is driven low. +// +// When GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 1 is 0: +// AUXIO[8i+1] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 1 is 1: +// AUXIO[8i+1] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 1 drives +// AUXIO[8i+1]. +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 + +// Field: [1:0] IO0 +// +// Select mode for AUXIO[8i+0]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is driven low. +// +// When GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 0 is 0: +// AUXIO[8i+0] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 0 is 1: +// AUXIO[8i+0] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 0 drives +// AUXIO[8i+0]. +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIN +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit +// n is set. Otherwise, bit n value is old. +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTSET +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTCLR +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTTGL +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to enable digital input buffer for +// AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to disable digital input buffer +// for AUXIO[8i+n]. +// +// You must enable the digital input buffer for AUXIO[8i+n] to read the pin +// value in GPIODIN. +// You must disable the digital input buffer for analog input or pins that +// float to avoid current leakage. +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 + + +#endif // __AUX_AIODIO__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_anaif.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_anaif.h new file mode 100644 index 0000000000..096c192daa --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_anaif.h @@ -0,0 +1,305 @@ +/****************************************************************************** +* Filename: hw_aux_anaif_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_ANAIF_H__ +#define __HW_AUX_ANAIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_ANAIF component +// +//***************************************************************************** +// ADC Control +#define AUX_ANAIF_O_ADCCTL 0x00000010 + +// ADC FIFO Status +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 + +// ADC FIFO +#define AUX_ANAIF_O_ADCFIFO 0x00000018 + +// ADC Trigger +#define AUX_ANAIF_O_ADCTRIG 0x0000001C + +// Current Source Control +#define AUX_ANAIF_O_ISRCCTL 0x00000020 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCCTL +// +//***************************************************************************** +// Field: [13] START_POL +// +// Select active polarity for START_SRC event. +// ENUMs: +// FALL Set ADC trigger on falling edge of event source. +// RISE Set ADC trigger on rising edge of event source. +#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_S 13 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 + +// Field: [12:8] START_SRC +// +// Select ADC trigger event source from the asynchronous AUX event bus. +// +// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through +// ADCTRIG.START. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// NO_EVENT1 No event. +// NO_EVENT0 No event. +// RESERVED1 Reserved - Do not use. +// RESERVED0 Reserved - Do not use. +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_ANAIF_ADCCTL_START_SRC_W 5 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 + +// Field: [1:0] CMD +// +// ADC interface command. +// +// Non-enumerated values are not supported. The written value is returned when +// read. +// ENUMs: +// FLUSH Flush ADC FIFO. +// +// You must set CMD to EN or +// DIS after flush. +// +// System CPU must wait two +// clock cycles before it sets CMD to EN or DIS. +// EN Enable ADC interface. +// DIS Disable ADC interface. +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFOSTAT +// +//***************************************************************************** +// Field: [4] OVERFLOW +// +// FIFO overflow flag. +// +// 0: FIFO has not overflowed. +// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO write pointer is static. It is not +// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 + +// Field: [3] UNDERFLOW +// +// FIFO underflow flag. +// +// 0: FIFO has not underflowed. +// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO read pointer is static. Read returns the +// previous sample that was read. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 + +// Field: [2] FULL +// +// FIFO full flag. +// +// 0: FIFO is not full, there is less than 4 samples in the FIFO. +// 1: FIFO is full, there are 4 samples in the FIFO. +// +// When the flag is set, it is not possible to add more samples to the ADC +// FIFO. An attempt to add samples sets the OVERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 + +// Field: [1] ALMOST_FULL +// +// FIFO almost full flag. +// +// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL +// flag is also asserted in the latter case. +// 1: There are 3 samples in the FIFO, there is room for one more sample. +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 + +// Field: [0] EMPTY +// +// FIFO empty flag. +// +// 0: FIFO contains one or more samples. +// 1: FIFO is empty. +// +// When the flag is set, read returns the previous sample that was read and +// sets the UNDERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFO +// +//***************************************************************************** +// Field: [11:0] DATA +// +// FIFO data. +// +// Read: +// Get oldest ADC sample from FIFO. +// +// Write: +// Write dummy sample to FIFO. This is useful for code development when you do +// not have real ADC samples. +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCTRIG +// +//***************************************************************************** +// Field: [0] START +// +// Manual ADC trigger. +// +// 0: No effect. +// 1: Single ADC trigger. +// +// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to +// avoid conflict with event-driven ADC trigger. +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ISRCCTL +// +//***************************************************************************** +// Field: [0] RESET_N +// +// ISRC reset control. +// +// 0: ISRC drives 0 uA. +// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 + + +#endif // __AUX_ANAIF__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_evctl.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_evctl.h new file mode 100644 index 0000000000..30e8b4e66c --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_evctl.h @@ -0,0 +1,1852 @@ +/****************************************************************************** +* Filename: hw_aux_evctl_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_EVCTL_H__ +#define __HW_AUX_EVCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_EVCTL component +// +//***************************************************************************** +// Vector Configuration 0 +#define AUX_EVCTL_O_VECCFG0 0x00000000 + +// Vector Configuration 1 +#define AUX_EVCTL_O_VECCFG1 0x00000004 + +// Sensor Controller Engine Wait Event Selection +#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 + +// Events To AON Flags +#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C + +// Events To AON Polarity +#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 + +// Direct Memory Access Control +#define AUX_EVCTL_O_DMACTL 0x00000014 + +// Software Event Set +#define AUX_EVCTL_O_SWEVSET 0x00000018 + +// Event Status 0 +#define AUX_EVCTL_O_EVSTAT0 0x0000001C + +// Event Status 1 +#define AUX_EVCTL_O_EVSTAT1 0x00000020 + +// Event To MCU Polarity +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 + +// Events to MCU Flags +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 + +// Combined Event To MCU Mask +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C + +// Vector Flags +#define AUX_EVCTL_O_VECFLAGS 0x00000034 + +// Events To MCU Flags Clear +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 + +// Events To AON Clear +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C + +// Vector Flags Clear +#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECCFG0 +// +//***************************************************************************** +// Field: [14] VEC1_POL +// +// Vector 1 trigger event polarity. +// +// To manually trigger vector 1 execution: +// - AUX_SCE must sleep. +// - Set VEC1_EV to a known static value. +// - Toggle VEC1_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 1 execution. +// RISE Rising edge triggers vector 1 execution. +#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 + +// Field: [13] VEC1_EN +// +// Vector 1 trigger enable. +// +// When enabled, VEC1_EV event with VEC1_POL polarity triggers a jump to vector +// # 1 when AUX_SCE sleeps. +// +// Lower vectors (0) have priority. +// ENUMs: +// EN Enable vector 1 trigger. +// DIS Disable vector 1 trigger. +#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 + +// Field: [12:8] VEC1_EV +// +// Select vector 1 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 + +// Field: [6] VEC0_POL +// +// Vector 0 trigger event polarity. +// +// To manually trigger vector 0 execution: +// - AUX_SCE must sleep. +// - Set VEC0_EV to a known static value. +// - Toggle VEC0_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 0 execution. +// RISE Rising edge triggers vector 0 execution. +#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 + +// Field: [5] VEC0_EN +// +// Vector 0 trigger enable. +// +// When enabled, VEC0_EV event with VEC0_POL polarity triggers a jump to vector +// # 0 when AUX_SCE sleeps. +// ENUMs: +// EN Enable vector 0 trigger. +// DIS Disable vector 0 trigger. +#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 + +// Field: [4:0] VEC0_EV +// +// Select vector 0 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECCFG1 +// +//***************************************************************************** +// Field: [14] VEC3_POL +// +// Vector 3 trigger event polarity. +// +// To manually trigger vector 3 execution: +// - AUX_SCE must sleep. +// - Set VEC3_EV to a known static value. +// - Toggle VEC3_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 3 execution. +// RISE Rising edge triggers vector 3 execution. +#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 + +// Field: [13] VEC3_EN +// +// Vector 3 trigger enable. +// +// When enabled, VEC3_EV event with VEC3_POL polarity triggers a jump to vector +// # 3 when AUX_SCE sleeps. +// +// Lower vectors (0, 1, and 2) have priority. +// ENUMs: +// EN Enable vector 3 trigger. +// DIS Disable vector 3 trigger. +#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 + +// Field: [12:8] VEC3_EV +// +// Select vector 3 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 + +// Field: [6] VEC2_POL +// +// Vector 2 trigger event polarity. +// +// To manually trigger vector 2 execution: +// - AUX_SCE must sleep. +// - Set VEC2_EV to a known static value. +// - Toggle VEC2_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 2 execution. +// RISE Rising edge triggers vector 2 execution. +#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 + +// Field: [5] VEC2_EN +// +// Vector 2 trigger enable. +// +// When enabled, VEC2_EV event with VEC2_POL polarity triggers a jump to vector +// # 2 when AUX_SCE sleeps. +// +// Lower vectors (0 and 1) have priority. +// ENUMs: +// EN Enable vector 2 trigger. +// DIS Disable vector 2 trigger. +#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 + +// Field: [4:0] VEC2_EV +// +// Select vector 2 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVSEL +// +//***************************************************************************** +// Field: [4:0] WEV7_EV +// +// Select event source to connect to AUX_SCE:WUSTAT.EV_SIGNALS bit 7. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGS +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on +// EVSTAT0.TIMER1_EV. +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 + +// Field: [7] TIMER0_EV +// +// This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on +// EVSTAT0.TIMER0_EV. +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 + +// Field: [6] TDC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on +// EVSTAT0.TDC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 + +// Field: [5] ADC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on +// EVSTAT0.ADC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on +// EVSTAT0.AUX_COMPB. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on +// EVSTAT0.AUX_COMPA. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV2. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV1. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV0. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONPOL +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// Select the level of EVSTAT0.TIMER1_EV that sets EVTOAONFLAGS.TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 + +// Field: [7] TIMER0_EV +// +// Select the level of EVSTAT0.TIMER0_EV that sets EVTOAONFLAGS.TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 + +// Field: [6] TDC_DONE +// +// Select level of EVSTAT0.TDC_DONE that sets EVTOAONFLAGS.TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 + +// Field: [5] ADC_DONE +// +// Select the level of EVSTAT0.ADC_DONE that sets EVTOAONFLAGS.ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 + +// Field: [4] AUX_COMPB +// +// Select the edge of EVSTAT0.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. +// ENUMs: +// LOW Falling edge +// HIGH Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 + +// Field: [3] AUX_COMPA +// +// Select the edge of EVSTAT0.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. +// ENUMs: +// LOW Falling edge +// HIGH Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_DMACTL +// +//***************************************************************************** +// Field: [2] REQ_MODE +// +// UDMA0 Request mode +// ENUMs: +// SINGLE Single requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +// BURST Burst requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 + +// Field: [1] EN +// +// uDMA ADC interface enable. +// +// 0: Disable UDMA0 interface to ADC. +// 1: Enable UDMA0 interface to ADC. +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 + +// Field: [0] SEL +// +// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO +// data. +// ENUMs: +// FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC +// FIFO is almost full (3/4 full). +// FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there +// are samples in the ADC FIFO. +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SWEVSET +// +//***************************************************************************** +// Field: [2] SWEV2 +// +// Software event flag 2. +// +// 0: No effect. +// 1: Set software event flag 2. +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Software event flag 1. +// +// 0: No effect. +// 1: Set software event flag 1. +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Software event flag 0. +// +// 0: No effect. +// 1: Set software event flag 0. +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0 +// +//***************************************************************************** +// Field: [15] AUXIO2 +// +// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 + +// Field: [14] AUXIO1 +// +// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 + +// Field: [13] AUXIO0 +// +// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 + +// Field: [12] AON_PROG_WU +// +// AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR +// AON_EVENT:AUXWUSEL.WU0_EV +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 + +// Field: [11] AON_SW +// +// AON_WUC:AUXCTL.SWEV +#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 +#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 + +// Field: [10] OBSMUX1 +// +// Observation input 1 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL1. +#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 + +// Field: [9] OBSMUX0 +// +// Observation input 0 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by +// IOC:OBSAUXOUTPUT.SEL_MISC. +#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// AUX_ANAIF ADC conversion done event. +#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. +#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. +#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// AUX_TDC:STAT.DONE +#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Comparator B output +#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Comparator A output +#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 + +// Field: [0] AON_RTC_CH2 +// +// AON_RTC:EVFLAGS.CH2 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1 +// +//***************************************************************************** +// Field: [15] ADC_IRQ +// +// The logical function for this event is configurable. +// +// When DMACTL.EN = 1 : +// Event = UDMA0 Channel 7 done event OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// When DMACTL.EN = 0 : +// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// Bit 7 in UDMA0:DONEMASK must be 0. +#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 + +// Field: [14] MCU_EV +// +// Event from EVENT configured by EVENT:AUXSEL0. +#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 + +// Field: [13] ACLK_REF +// +// TDC reference clock. +// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by +// AUX_WUC:REFCLKCTL.REQ. +#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 + +// Field: [12] AUXIO15 +// +// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 + +// Field: [11] AUXIO14 +// +// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 + +// Field: [10] AUXIO13 +// +// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 + +// Field: [9] AUXIO12 +// +// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 + +// Field: [8] AUXIO11 +// +// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 + +// Field: [7] AUXIO10 +// +// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 + +// Field: [6] AUXIO9 +// +// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 + +// Field: [5] AUXIO8 +// +// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 + +// Field: [4] AUXIO7 +// +// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 + +// Field: [3] AUXIO6 +// +// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 + +// Field: [2] AUXIO5 +// +// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 + +// Field: [1] AUXIO4 +// +// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 + +// Field: [0] AUXIO3 +// +// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUPOL +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_IRQ. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 + +// Field: [9] OBSMUX0 +// +// Select the event source level that sets EVTOMCUFLAGS.OBSMUX0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 + +// Field: [7] ADC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 + +// Field: [5] TIMER1_EV +// +// Select the event source level that sets EVTOMCUFLAGS.TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 + +// Field: [4] TIMER0_EV +// +// Select the event source level that sets EVTOMCUFLAGS.TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 + +// Field: [3] TDC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 + +// Field: [2] AUX_COMPB +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPB. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 + +// Field: [1] AUX_COMPA +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPA. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 + +// Field: [0] AON_WU_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AON_WU_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGS +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on +// EVSTAT0.ADC_IRQ. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs +// on EVSTAT0.MCU_OBSMUX0. +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// This event flag is set when level selected by +// EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on +// EVSTAT0.ADC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE +// occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on +// EVSTAT0.TIMER1_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on +// EVSTAT0.TIMER0_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on +// EVSTAT0.TDC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on +// EVSTAT0.AUX_COMPB. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on +// EVSTAT0.AUX_COMPA. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on +// the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, +// AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_COMBEVTOMCUMASK +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// EVTOMCUFLAGS.ADC_IRQ contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// EVTOMCUFLAGS.ADC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// EVTOMCUFLAGS.TIMER1_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// EVTOMCUFLAGS.TIMER0_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// EVTOMCUFLAGS.TDC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. +// +// 0: Exclude +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// EVTOMCUFLAGS.AON_WU_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECFLAGS +// +//***************************************************************************** +// Field: [3] VEC3 +// +// Vector flag 3. +// +// The vector flag is set if the edge selected VECCFG1.VEC3_POL occurs on the +// event selected in VECCFG1.VEC3_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC3. +#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_S 3 + +// Field: [2] VEC2 +// +// Vector flag 2. +// +// The vector flag is set if the edge selected VECCFG1.VEC2_POL occurs on the +// event selected in VECCFG1.VEC2_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC2. +#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_S 2 + +// Field: [1] VEC1 +// +// Vector flag 1. +// +// The vector flag is set if the edge selected VECCFG0.VEC1_POL occurs on the +// event selected in VECCFG0.VEC1_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC1. +#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_S 1 + +// Field: [0] VEC0 +// +// Vector flag 0. +// +// The vector flag is set if the edge selected VECCFG0.VEC0_POL occurs on the +// event selected in VECCFG0.VEC0_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC0. +#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// Write 1 to clear EVTOAONFLAGS.TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 + +// Field: [7] TIMER0_EV +// +// Write 1 to clear EVTOAONFLAGS.TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 + +// Field: [6] TDC_DONE +// +// Write 1 to clear EVTOAONFLAGS.TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 + +// Field: [5] ADC_DONE +// +// Write 1 to clear EVTOAONFLAGS.ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// Write 1 to clear EVTOAONFLAGS.SWEV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Write 1 to clear EVTOAONFLAGS.SWEV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Write 1 to clear EVTOAONFLAGS.SWEV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECFLAGSCLR +// +//***************************************************************************** +// Field: [3] VEC3 +// +// Clear vector flag 3. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC3. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 + +// Field: [2] VEC2 +// +// Clear vector flag 2. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC2. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 + +// Field: [1] VEC1 +// +// Clear vector flag 1. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC1. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 + +// Field: [0] VEC0 +// +// Clear vector flag 0. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC0. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 + + +#endif // __AUX_EVCTL__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_sce.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_sce.h new file mode 100644 index 0000000000..99ea02ac3c --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_sce.h @@ -0,0 +1,381 @@ +/****************************************************************************** +* Filename: hw_aux_sce_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SCE_H__ +#define __HW_AUX_SCE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SCE component +// +//***************************************************************************** +// Internal +#define AUX_SCE_O_CTL 0x00000000 + +// Internal +#define AUX_SCE_O_FETCHSTAT 0x00000004 + +// Internal +#define AUX_SCE_O_CPUSTAT 0x00000008 + +// Internal +#define AUX_SCE_O_WUSTAT 0x0000000C + +// Internal +#define AUX_SCE_O_REG1_0 0x00000010 + +// Internal +#define AUX_SCE_O_REG3_2 0x00000014 + +// Internal +#define AUX_SCE_O_REG5_4 0x00000018 + +// Internal +#define AUX_SCE_O_REG7_6 0x0000001C + +// Internal +#define AUX_SCE_O_LOOPADDR 0x00000020 + +// Internal +#define AUX_SCE_O_LOOPCNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CTL +// +//***************************************************************************** +// Field: [31:24] FORCE_EV_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 + +// Field: [23:16] FORCE_EV_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 + +// Field: [11:8] RESET_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESET_VECTOR_W 4 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 + +// Field: [6] DBG_FREEZE_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 + +// Field: [5] FORCE_WU_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 + +// Field: [4] FORCE_WU_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 + +// Field: [3] RESTART +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 + +// Field: [2] SINGLE_STEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 + +// Field: [1] SUSPEND +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 + +// Field: [0] CLK_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_FETCHSTAT +// +//***************************************************************************** +// Field: [31:16] OPCODE +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 + +// Field: [15:0] PC +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CPUSTAT +// +//***************************************************************************** +// Field: [11] BUS_ERROR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 + +// Field: [10] SLEEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 + +// Field: [9] WEV +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 + +// Field: [8] SELF_STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 +#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 + +// Field: [3] V_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 + +// Field: [2] C_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 + +// Field: [1] N_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 + +// Field: [0] Z_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_WUSTAT +// +//***************************************************************************** +// Field: [17:16] EXC_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 + +// Field: [8] WU_SIGNAL +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 + +// Field: [7:0] EV_SIGNALS +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG1_0 +// +//***************************************************************************** +// Field: [31:16] REG1 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 + +// Field: [15:0] REG0 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG3_2 +// +//***************************************************************************** +// Field: [31:16] REG3 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 + +// Field: [15:0] REG2 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG5_4 +// +//***************************************************************************** +// Field: [31:16] REG5 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 + +// Field: [15:0] REG4 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG7_6 +// +//***************************************************************************** +// Field: [31:16] REG7 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 + +// Field: [15:0] REG6 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPADDR +// +//***************************************************************************** +// Field: [31:16] STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 + +// Field: [15:0] START +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPCNT +// +//***************************************************************************** +// Field: [7:0] ITER_LEFT +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 + + +#endif // __AUX_SCE__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_smph.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_smph.h new file mode 100644 index 0000000000..3ddcd9673c --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_smph.h @@ -0,0 +1,282 @@ +/****************************************************************************** +* Filename: hw_aux_smph_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SMPH_H__ +#define __HW_AUX_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SMPH component +// +//***************************************************************************** +// Semaphore 0 +#define AUX_SMPH_O_SMPH0 0x00000000 + +// Semaphore 1 +#define AUX_SMPH_O_SMPH1 0x00000004 + +// Semaphore 2 +#define AUX_SMPH_O_SMPH2 0x00000008 + +// Semaphore 3 +#define AUX_SMPH_O_SMPH3 0x0000000C + +// Semaphore 4 +#define AUX_SMPH_O_SMPH4 0x00000010 + +// Semaphore 5 +#define AUX_SMPH_O_SMPH5 0x00000014 + +// Semaphore 6 +#define AUX_SMPH_O_SMPH6 0x00000018 + +// Semaphore 7 +#define AUX_SMPH_O_SMPH7 0x0000001C + +// Auto Take +#define AUX_SMPH_O_AUTOTAKE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_AUTOTAKE +// +//***************************************************************************** +// Field: [2:0] SMPH_ID +// +// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until +// it is granted. +// +// When semaphore SMPH_ID is granted, event +// AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE becomes 1. +// +// The event becomes 0 when software releases the semaphore or writes a new +// value to SMPH_ID. +// +// To avoid corrupted semaphores: +// - Usage of this functionality must be restricted to one CPU core. +// - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 +// before it writes a new value to SMPH_ID. +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 + + +#endif // __AUX_SMPH__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_tdc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_tdc.h new file mode 100644 index 0000000000..cd27a04055 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_tdc.h @@ -0,0 +1,694 @@ +/****************************************************************************** +* Filename: hw_aux_tdc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TDC_H__ +#define __HW_AUX_TDC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TDC component +// +//***************************************************************************** +// Control +#define AUX_TDC_O_CTL 0x00000000 + +// Status +#define AUX_TDC_O_STAT 0x00000004 + +// Result +#define AUX_TDC_O_RESULT 0x00000008 + +// Saturation Configuration +#define AUX_TDC_O_SATCFG 0x0000000C + +// Trigger Source +#define AUX_TDC_O_TRIGSRC 0x00000010 + +// Trigger Counter +#define AUX_TDC_O_TRIGCNT 0x00000014 + +// Trigger Counter Load +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 + +// Trigger Counter Configuration +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C + +// Prescaler Control +#define AUX_TDC_O_PRECTL 0x00000020 + +// Prescaler Counter +#define AUX_TDC_O_PRECNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_TDC_O_CTL +// +//***************************************************************************** +// Field: [1:0] CMD +// +// TDC commands. +// ENUMs: +// ABORT Force TDC state machine back to IDLE state. +// +// Never write this command +// while AUX_TDC:STAT.STATE equals CLR_CNT or +// WAIT_CLR_CNT_DONE. +// RUN Asynchronous counter start. +// +// The counter starts to +// count when the start event is high. To achieve +// precise edge-to-edge measurements you must +// ensure that the start event is low for at least +// 420 ns after you write this command. +// RUN_SYNC_START Synchronous counter start. +// +// The counter looks for the +// opposite edge of the selected start event +// before it starts to count when the selected +// edge occurs. This guarantees an edge-triggered +// start and is recommended for frequency +// measurements. +// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. +// +// This is not needed as +// prerequisite for a measurement. Reliable clear +// is only guaranteed from IDLE state. +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_STAT +// +//***************************************************************************** +// Field: [7] SAT +// +// TDC measurement saturation flag. +// +// 0: Conversion has not saturated. +// 1: Conversion stopped due to saturation. +// +// This field is cleared when a new measurement is started or when CLR_RESULT +// is written to CTL.CMD. +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 + +// Field: [6] DONE +// +// TDC measurement complete flag. +// +// 0: TDC measurement has not yet completed. +// 1: TDC measurement has completed. +// +// This field clears when a new TDC measurement starts or when you write +// CLR_RESULT to CTL.CMD. +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 + +// Field: [5:0] STATE +// +// TDC state machine status. +// ENUMs: +// FORCE_STOP Current state is TDC_FORCESTOP. +// You wrote ABORT to +// CTL.CMD to abort the TDC measurement. +// START_FALL Current state is TDC_WAIT_STARTFALL. +// The fast-counter circuit +// waits for a falling edge on the start event. +// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. +// The state machine waits +// for fast-counter circuit to finish reset. +// POR Current state is TDC_STATE_POR. +// This is the reset state. +// GET_RESULT Current state is TDC_STATE_GETRESULTS. +// The state machine copies +// the counter value from the fast-counter +// circuit. +// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. +// The fast-counter circuit +// looks for the stop condition. It will ignore a +// number of stop events configured in +// TRIGCNTLOAD.CNT. +// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. +// The state machine waits +// for the fast-counter circuit to stop. +// CLR_CNT Current state is TDC_STATE_CLRCNT. The +// fast-counter circuit is reset. +// IDLE Current state is TDC_STATE_IDLE. +// This is the default state +// after reset and abortion. State will change +// when you write CTL.CMD to either RUN_SYNC_START +// or RUN. +// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +// WAIT_START Current state is TDC_STATE_WAIT_START. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_RESULT +// +//***************************************************************************** +// Field: [24:0] VALUE +// +// TDC conversion result. +// +// The result of the TDC conversion is given in number of clock edges of the +// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and +// falling edges are counted. +// +// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it +// takes a non-zero time to stop the measurement. Hence, the maximum value of +// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT +// to R24. +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_SATCFG +// +//***************************************************************************** +// Field: [3:0] LIMIT +// +// Saturation limit. +// +// The flag STAT.SAT is set when the TDC counter saturates. +// +// Values not enumerated are not supported +// ENUMs: +// R24 Result bit 24: TDC conversion saturates and stops +// when RESULT.VALUE[24] is set. +// R23 Result bit 23: TDC conversion saturates and stops +// when RESULT.VALUE[23] is set. +// R22 Result bit 22: TDC conversion saturates and stops +// when RESULT.VALUE[22] is set. +// R21 Result bit 21: TDC conversion saturates and stops +// when RESULT.VALUE[21] is set. +// R20 Result bit 20: TDC conversion saturates and stops +// when RESULT.VALUE[20] is set. +// R19 Result bit 19: TDC conversion saturates and stops +// when RESULT.VALUE[19] is set. +// R18 Result bit 18: TDC conversion saturates and stops +// when RESULT.VALUE[18] is set. +// R17 Result bit 17: TDC conversion saturates and stops +// when RESULT.VALUE[17] is set. +// R16 Result bit 16: TDC conversion saturates and stops +// when RESULT.VALUE[16] is set. +// R15 Result bit 15: TDC conversion saturates and stops +// when RESULT.VALUE[15] is set. +// R14 Result bit 14: TDC conversion saturates and stops +// when RESULT.VALUE[14] is set. +// R13 Result bit 13: TDC conversion saturates and stops +// when RESULT.VALUE[13] is set. +// R12 Result bit 12: TDC conversion saturates and stops +// when RESULT.VALUE[12] is set. +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGSRC +// +//***************************************************************************** +// Field: [13] STOP_POL +// +// Polarity of stop source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion stops when low level is detected. +// HIGH TDC conversion stops when high level is detected. +#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 13 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 + +// Field: [12:8] STOP_SRC +// +// Select stop source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 + +// Field: [5] START_POL +// +// Polarity of start source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion starts when low level is detected. +// HIGH TDC conversion starts when high level is detected. +#define AUX_TDC_TRIGSRC_START_POL 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_BITN 5 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_S 5 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 + +// Field: [4:0] START_SRC +// +// Select start source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_TRIGSRC_START_SRC_W 5 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// Read CNT to get the remaining number of stop events to ignore during a TDC +// measurement. +// +// Write CNT to update the remaining number of stop events to ignore during a +// TDC measurement. The TDC measurement ignores updates of CNT if there are no +// more stop events left to ignore. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the +// start of the measurement. +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTLOAD +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// To measure frequency of an event source: +// - Set start event equal to stop event. +// - Set CNT to number of periods to measure. Both 0 and 1 values measures a +// single event source period. +// +// To measure pulse width of an event source: +// - Set start event source equal to stop event source. +// - Select different polarity for start and stop event. +// - Set CNT to 0. +// +// To measure time from the start event to the Nth stop event when N > 1: +// - Select different start and stop event source. +// - Set CNT to (N-1). +// +// See the Technical Reference Manual for event timing requirements. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start +// of the measurement. +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTCFG +// +//***************************************************************************** +// Field: [0] EN +// +// Enable stop-counter. +// +// 0: Disable stop-counter. +// 1: Enable stop-counter. +// +// Change only while STAT.STATE is IDLE. +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECTL +// +//***************************************************************************** +// Field: [7] RESET_N +// +// Prescaler reset. +// +// 0: Reset prescaler. +// 1: Release reset of prescaler. +// +// AUX_TDC_PRE event becomes 0 when you reset the prescaler. +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 + +// Field: [6] RATIO +// +// Prescaler ratio. +// +// This controls how often the AUX_TDC_PRE event is generated by the prescaler. +// ENUMs: +// DIV64 Prescaler divides input by 64. +// +// AUX_TDC_PRE event has a +// rising edge for every 64 rising edges of the +// input. AUX_TDC_PRE event toggles on every 32nd +// rising edge of the input. +// DIV16 Prescaler divides input by 16. +// +// AUX_TDC_PRE event has a +// rising edge for every 16 rising edges of the +// input. AUX_TDC_PRE event toggles on every 8th +// rising edge of the input. +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 + +// Field: [4:0] SRC +// +// Prescaler event source. +// +// Select an event from the asynchronous AUX event bus to connect to the +// prescaler input. +// +// Configure only while RESET_N is 0. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_PRECTL_SRC_W 5 +#define AUX_TDC_PRECTL_SRC_M 0x0000001F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D +#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B +#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Prescaler counter value. +// +// Write a value to CNT to capture the value of the 16-bit prescaler counter +// into CNT. Read CNT to get the captured value. +// +// The read value gets 1 LSB uncertainty if the event source level rises when +// you release the reset. +// +// You must capture the prescaler counter value when the event source level is +// stable, either high or low: +// - Disable AUX I/O input buffer to clamp AUXIO event low. +// - Disable COMPA to clamp AUX_COMPA event low. +// The read value can in general get 1 LSB uncertainty when you gate the event +// source asynchronously. +// +// Please note the following: +// - The prescaler counter is reset to 2 by PRECTL.RESET_N. +// - The captured value is 2 when the number of rising edges on prescaler input +// is less than 3. Otherwise, captured value equals number of event pulses - 1. +#define AUX_TDC_PRECNT_CNT_W 16 +#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNT_CNT_S 0 + + +#endif // __AUX_TDC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_timer.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_timer.h new file mode 100644 index 0000000000..3ff0a493e4 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_timer.h @@ -0,0 +1,447 @@ +/****************************************************************************** +* Filename: hw_aux_timer_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER_H__ +#define __HW_AUX_TIMER_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER component +// +//***************************************************************************** +// Timer 0 Configuration +#define AUX_TIMER_O_T0CFG 0x00000000 + +// Timer 1 Configuration +#define AUX_TIMER_O_T1CFG 0x00000004 + +// Timer 0 Control +#define AUX_TIMER_O_T0CTL 0x00000008 + +// Timer 0 Target +#define AUX_TIMER_O_T0TARGET 0x0000000C + +// Timer 1 Target +#define AUX_TIMER_O_T1TARGET 0x00000010 + +// Timer 1 Control +#define AUX_TIMER_O_T1CTL 0x00000014 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0CFG +// +//***************************************************************************** +// Field: [13] TICK_SRC_POL +// +// Tick source polarity for Timer 0. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [12:8] TICK_SRC +// +// Select Timer 0 tick source from the synchronous event bus. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TIMER_T0CFG_TICK_SRC_W 5 +#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 +#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER_T0CFG_PRE_W 4 +#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T0CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 0 mode. +// +// Configure source for Timer 0 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use AUX clock as source for prescaler. +#define AUX_TIMER_T0CFG_MODE 0x00000002 +#define AUX_TIMER_T0CFG_MODE_BITN 1 +#define AUX_TIMER_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER_T0CFG_MODE_S 1 +#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 0 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 0 restarts when the +// counter value becomes equal to or greater than +// ( T0TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 0 stops and +// T0CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T0TARGET.VALUE. +#define AUX_TIMER_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_S 0 +#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1CFG +// +//***************************************************************************** +// Field: [13] TICK_SRC_POL +// +// Tick source polarity for Timer 1. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [12:8] TICK_SRC +// +// Select Timer 1 tick source from the synchronous event bus. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TIMER_T1CFG_TICK_SRC_W 5 +#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 +#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER_T1CFG_PRE_W 4 +#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T1CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 1 mode. +// +// Configure source for Timer 1 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use AUX clock as source for prescaler. +#define AUX_TIMER_T1CFG_MODE 0x00000002 +#define AUX_TIMER_T1CFG_MODE_BITN 1 +#define AUX_TIMER_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER_T1CFG_MODE_S 1 +#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 1 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 1 restarts when the +// counter value becomes equal to or greater than +// ( T1TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 1 stops and +// T1CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T1TARGET.VALUE. +#define AUX_TIMER_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_S 0 +#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 0 enable. +// +// 0: Disable Timer 0. +// 1: Enable Timer 0. +// +// The counter restarts from 0 when you enable Timer 0. +#define AUX_TIMER_T0CTL_EN 0x00000001 +#define AUX_TIMER_T0CTL_EN_BITN 0 +#define AUX_TIMER_T0CTL_EN_M 0x00000001 +#define AUX_TIMER_T0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 target value. +// +// Manual Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is +// equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 +// AUX clock period. +// +// Continuous Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is +// 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 0 counter value remains 0. +// AUX_TIMER0_EV goes high and remains high 1 AUX clock period after you enable +// the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER_T0TARGET_VALUE_W 16 +#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER_T0TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1TARGET +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// Timer 1 target value. +// +// Manual Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is +// equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 +// AUX clock period. +// +// Continuous Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is +// 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 1 counter value remains 0. +// AUX_TIMER1_EV goes high and remains high 1 AUX clock period after you enable +// the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER_T1TARGET_VALUE_W 8 +#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF +#define AUX_TIMER_T1TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 1 enable. +// +// 0: Disable Timer 1. +// 1: Enable Timer 1. +// +// The counter restarts from 0 when you enable Timer 1. +#define AUX_TIMER_T1CTL_EN 0x00000001 +#define AUX_TIMER_T1CTL_EN_BITN 0 +#define AUX_TIMER_T1CTL_EN_M 0x00000001 +#define AUX_TIMER_T1CTL_EN_S 0 + + +#endif // __AUX_TIMER__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_aux_wuc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_wuc.h new file mode 100644 index 0000000000..17b5a2e31b --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_aux_wuc.h @@ -0,0 +1,705 @@ +/****************************************************************************** +* Filename: hw_aux_wuc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_WUC_H__ +#define __HW_AUX_WUC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_WUC component +// +//***************************************************************************** +// Module Clock Enable +#define AUX_WUC_O_MODCLKEN0 0x00000000 + +// Power Off Request +#define AUX_WUC_O_PWROFFREQ 0x00000004 + +// Power Down Request +#define AUX_WUC_O_PWRDWNREQ 0x00000008 + +// Power Down Acknowledgment +#define AUX_WUC_O_PWRDWNACK 0x0000000C + +// Low Frequency Clock Request +#define AUX_WUC_O_CLKLFREQ 0x00000010 + +// Low Frequency Clock Acknowledgment +#define AUX_WUC_O_CLKLFACK 0x00000014 + +// Wake-up Event Flags +#define AUX_WUC_O_WUEVFLAGS 0x00000028 + +// Wake-up Event Clear +#define AUX_WUC_O_WUEVCLR 0x0000002C + +// ADC Clock Control +#define AUX_WUC_O_ADCCLKCTL 0x00000030 + +// TDC Clock Control +#define AUX_WUC_O_TDCCLKCTL 0x00000034 + +// Reference Clock Control +#define AUX_WUC_O_REFCLKCTL 0x00000038 + +// Real Time Counter Sub Second Increment 0 +#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C + +// Real Time Counter Sub Second Increment 1 +#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 + +// Real Time Counter Sub Second Increment Control +#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 + +// MCU Bus Control +#define AUX_WUC_O_MCUBUSCTL 0x00000048 + +// MCU Bus Status +#define AUX_WUC_O_MCUBUSSTAT 0x0000004C + +// AON Domain Control Status +#define AUX_WUC_O_AONCTLSTAT 0x00000050 + +// AUX Input Output Latch +#define AUX_WUC_O_AUXIOLATCH 0x00000054 + +// Module Clock Enable 1 +#define AUX_WUC_O_MODCLKEN1 0x0000005C + +//***************************************************************************** +// +// Register: AUX_WUC_O_MODCLKEN0 +// +//***************************************************************************** +// Field: [7] AUX_ADI4 +// +// Enables (1) or disables (0) clock for AUX_ADI4. +// ENUMs: +// EN System CPU has requested clock for AUX_ADI4 +// DIS System CPU has not requested clock for AUX_ADI4 +#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 + +// Field: [6] AUX_DDI0_OSC +// +// Enables (1) or disables (0) clock for AUX_DDI0_OSC. +// ENUMs: +// EN System CPU has requested clock for AUX_DDI0_OSC +// DIS System CPU has not requested clock for +// AUX_DDI0_OSC +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 + +// Field: [5] TDC +// +// Enables (1) or disables (0) clock for AUX_TDCIF. +// +// Note that the TDC counter and reference clock sources must be requested +// separately using TDCCLKCTL and REFCLKCTL, respectively. +// ENUMs: +// EN System CPU has requested clock for TDC +// DIS System CPU has not requested clock for TDC +#define AUX_WUC_MODCLKEN0_TDC 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_BITN 5 +#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_S 5 +#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 + +// Field: [4] ANAIF +// +// Enables (1) or disables (0) clock for AUX_ANAIF. +// +// Note that the ADC internal clock must be requested separately using +// ADCCLKCTL. +// ENUMs: +// EN System CPU has requested clock for ANAIF +// DIS System CPU has not requested clock for ANAIF +#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_S 4 +#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 + +// Field: [3] TIMER +// +// Enables (1) or disables (0) clock for AUX_TIMER. +// ENUMs: +// EN System CPU has requested clock for TIMER +// DIS System CPU has not requested clock for TIMER +#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_S 3 +#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 + +// Field: [2] AIODIO1 +// +// Enables (1) or disables (0) clock for AUX_AIODIO1. +// ENUMs: +// EN System CPU has requested clock for AIODIO1 +// DIS System CPU has not requested clock for AIODIO1 +#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 + +// Field: [1] AIODIO0 +// +// Enables (1) or disables (0) clock for AUX_AIODIO0. +// ENUMs: +// EN System CPU has requested clock for AIODIO0 +// DIS System CPU has not requested clock for AIODIO0 +#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 + +// Field: [0] SMPH +// +// Enables (1) or disables (0) clock for AUX_SMPH. +// ENUMs: +// EN System CPU has requested clock for SMPH +// DIS System CPU has not requested clock for SMPH +#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_S 0 +#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWROFFREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Power off request +// +// 0: No action +// 1: Request to power down AUX. Once set, this bit shall not be cleared. The +// bit will be reset again when AUX is powered up again. +// +// The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and +// MCUBUSSTAT.DISCONNECTED=1. +#define AUX_WUC_PWROFFREQ_REQ 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_BITN 0 +#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWRDWNREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Power down request +// +// 0: Request for system to be in active mode +// 1: Request for system to be in power down mode +// +// When REQ is 1 one shall assume that the system is in power down, and that +// current supply is limited. When setting REQ = 0, one shall assume that the +// system is in power down until PWRDWNACK.ACK = 0 +#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 +#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWRDWNACK +// +//***************************************************************************** +// Field: [0] ACK +// +// Power down acknowledgment. Indicates whether the power down request given by +// PWRDWNREQ.REQ is captured by the AON domain or not +// +// 0: AUX can assume that the system is in active mode +// 1: The request for power down is acknowledged and the AUX must act like the +// system is in power down mode and power supply is limited +// +// The system CPU cannot use this bit since the bus bridge between MCU domain +// and AUX domain is always disconnected when this bit is set. For AUX_SCE use +// only +#define AUX_WUC_PWRDWNACK_ACK 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_BITN 0 +#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_CLKLFREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Low frequency request +// +// 0: Request clock frequency to be controlled by AON_WUC:AUXCLK and the system +// state +// 1: Request low frequency clock SCLK_LF as the clock source for AUX +// +// This bit must not be modified unless CLKLFACK.ACK matches the current value +#define AUX_WUC_CLKLFREQ_REQ 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_BITN 0 +#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_CLKLFACK +// +//***************************************************************************** +// Field: [0] ACK +// +// Acknowledgment of CLKLFREQ.REQ +// +// 0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and +// the system state +// 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source +// for AUX +#define AUX_WUC_CLKLFACK_ACK 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_BITN 0 +#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_WUEVFLAGS +// +//***************************************************************************** +// Field: [2] AON_RTC_CH2 +// +// Indicates pending event from AON_RTC_CH2 compare. Note that this flag will +// be set whenever the AON_RTC_CH2 event happens, but that does not mean that +// this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for +// the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, +// AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 + +// Field: [1] AON_SW +// +// Indicates pending event triggered by system CPU writing a 1 to +// AON_WUC:AUXCTL.SWEV. +#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 +#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 + +// Field: [0] AON_PROG_WU +// +// Indicates pending event triggered by the sources selected in +// AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and +// AON_EVENT:AUXWUSEL.WU2_EV. +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_WUEVCLR +// +//***************************************************************************** +// Field: [2] AON_RTC_CH2 +// +// Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC +// channel 2 is also set as source for AON_PROG_WU this field can also clear +// WUEVFLAGS.AON_PROG_WU +// +// This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. +#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 + +// Field: [1] AON_SW +// +// Set to clear the WUEVFLAGS.AON_SW wake-up event. +// +// This bit must remain set until WUEVFLAGS.AON_SW returns to 0. +#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 +#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_S 1 + +// Field: [0] AON_PROG_WU +// +// Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO +// event is selected as wake-up event, is it possible to use this field to +// clear the source. Other sources cannot be cleared using this field. +// +// The IO pin needs to be assigned to AUX in the IOC and the input enable for +// the pin needs to be set in AIODIO0 or AIODIO1 for this clearing to take +// effect. +// +// This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. +#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_ADCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 +#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the ADC internal clock. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 +#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_TDCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 +#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the TDC counter clock source. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 +#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_REFCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_REFCLKCTL_ACK 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_BITN 1 +#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the TDC reference clock source. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_REFCLKCTL_REQ 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_BITN 0 +#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINC0 +// +//***************************************************************************** +// Field: [15:0] INC15_0 +// +// Bits 15:0 of the RTC sub-second increment value. +#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINC1 +// +//***************************************************************************** +// Field: [7:0] INC23_16 +// +// Bits 23:16 of the RTC sub-second increment value. +#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINCCTL +// +//***************************************************************************** +// Field: [1] UPD_ACK +// +// Acknowledgment of the UPD_REQ. +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 + +// Field: [0] UPD_REQ +// +// Signal that a new real time counter sub second increment value is available +// +// 0: New sub second increment is not available +// 1: New sub second increment is available +// +// This bit must not be modified unless UPD_ACK matches the current value. +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MCUBUSCTL +// +//***************************************************************************** +// Field: [0] DISCONNECT_REQ +// +// Requests the AUX domain bus to be disconnected from the MCU domain bus. The +// request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. +// +// The disconnection status can be monitored through MCUBUSSTAT. Note however +// that this register cannot be read by the system CPU while disconnected. +// +// It is recommended that this bit is set and remains set after initial +// power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to +// connect/disconnect the bus. +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MCUBUSSTAT +// +//***************************************************************************** +// Field: [1] DISCONNECTED +// +// Indicates whether the AUX domain and MCU domain buses are currently +// disconnected (1) or connected (0). +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 + +// Field: [0] DISCONNECT_ACK +// +// Acknowledges reception of the bus disconnection request, by matching the +// value of MCUBUSCTL.DISCONNECT_REQ. +// +// Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain +// bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_AONCTLSTAT +// +//***************************************************************************** +// Field: [1] AUX_FORCE_ON +// +// Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 + +// Field: [0] SCE_RUN_EN +// +// Status of AON_WUC:AUX_CTL.SCE_RUN_EN. +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_AUXIOLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching. +// +// At startup, set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and +// subsequently selecting AUX mode in the AON_IOC. +// +// When powering off the AUX domain (using PWROFFREQ.REQ), set EN = STATIC in +// advance preserve the current state (mode and output value) of the I/O pins. +// ENUMs: +// TRANSP Latches are transparent ( open ) +// STATIC Latches are static ( closed ) +#define AUX_WUC_AUXIOLATCH_EN 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_BITN 0 +#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_S 0 +#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MODCLKEN1 +// +//***************************************************************************** +// Field: [7] AUX_ADI4 +// +// Enables (1) or disables (0) clock for AUX_ADI4. +// ENUMs: +// EN AUX_SCE has requested clock for AUX_ADI4 +// DIS AUX_SCE has not requested clock for AUX_ADI4 +#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 + +// Field: [6] AUX_DDI0_OSC +// +// Enables (1) or disables (0) clock for AUX_DDI0_OSC. +// ENUMs: +// EN AUX_SCE has requested clock for AUX_DDI0_OSC +// DIS AUX_SCE has not requested clock for AUX_DDI0_OSC +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 + +// Field: [4] ANAIF +// +// Enables (1) or disables (0) clock for AUX_ANAIF. +// ENUMs: +// EN AUX_SCE has requested clock for ANAIF +// DIS AUX_SCE has not requested clock for ANAIF +#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_S 4 +#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 + +// Field: [3] TIMER +// +// Enables (1) or disables (0) clock for AUX_TIMER. +// ENUMs: +// EN AUX_SCE has requested clock for TIMER +// DIS AUX_SCE has not requested clock for TIMER +#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_S 3 +#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 + +// Field: [2] AIODIO1 +// +// Enables (1) or disables (0) clock for AUX_AIODIO1. +// ENUMs: +// EN AUX_SCE has requested clock for AIODIO1 +// DIS AUX_SCE has not requested clock for AIODIO1 +#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 + +// Field: [1] AIODIO0 +// +// Enables (1) or disables (0) clock for AUX_AIODIO0. +// ENUMs: +// EN AUX_SCE has requested clock for AIODIO0 +// DIS AUX_SCE has not requested clock for AIODIO0 +#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 + +// Field: [0] SMPH +// +// Enables (1) or disables (0) clock for AUX_SMPH. +// ENUMs: +// EN AUX_SCE has requested clock for SMPH +// DIS AUX_SCE has not requested clock for SMPH +#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_S 0 +#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 + + +#endif // __AUX_WUC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ccfg.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ccfg.h new file mode 100644 index 0000000000..e451726c55 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ccfg.h @@ -0,0 +1,1919 @@ +/****************************************************************************** +* Filename: hw_ccfg_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_H__ +#define __HW_CCFG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CCFG component +// +//***************************************************************************** +// Extern LF clock configuration +#define CCFG_O_EXT_LF_CLK 0x00000FA8 + +// Mode Configuration 1 +#define CCFG_O_MODE_CONF_1 0x00000FAC + +// CCFG Size and Disable Flags +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 + +// Mode Configuration 0 +#define CCFG_O_MODE_CONF 0x00000FB4 + +// Voltage Load 0 +#define CCFG_O_VOLT_LOAD_0 0x00000FB8 + +// Voltage Load 1 +#define CCFG_O_VOLT_LOAD_1 0x00000FBC + +// Real Time Clock Offset +#define CCFG_O_RTC_OFFSET 0x00000FC0 + +// Frequency Offset +#define CCFG_O_FREQ_OFFSET 0x00000FC4 + +// IEEE MAC Address 0 +#define CCFG_O_IEEE_MAC_0 0x00000FC8 + +// IEEE MAC Address 1 +#define CCFG_O_IEEE_MAC_1 0x00000FCC + +// IEEE BLE Address 0 +#define CCFG_O_IEEE_BLE_0 0x00000FD0 + +// IEEE BLE Address 1 +#define CCFG_O_IEEE_BLE_1 0x00000FD4 + +// Bootloader Configuration +#define CCFG_O_BL_CONFIG 0x00000FD8 + +// Erase Configuration +#define CCFG_O_ERASE_CONF 0x00000FDC + +// TI Options +#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 + +// Test Access Points Enable 0 +#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 + +// Test Access Points Enable 1 +#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 + +// Image Valid +#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC + +// Protect Sectors 0-31 +#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 + +// Protect Sectors 32-63 +#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 + +// Protect Sectors 64-95 +#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 + +// Protect Sectors 96-127 +#define CCFG_O_CCFG_PROT_127_96 0x00000FFC + +//***************************************************************************** +// +// Register: CCFG_O_EXT_LF_CLK +// +//***************************************************************************** +// Field: [31:24] DIO +// +// Unsigned integer, selecting the DIO to supply external 32kHz clock as +// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO +// will be marked as reserved by the pin driver (TI-RTOS environment) and hence +// not selectable for other usage. +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 + +// Field: [23:0] RTC_INCREMENT +// +// Unsigned integer, defining the input frequency of the external clock and is +// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: +// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: +// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF_1 +// +//***************************************************************************** +// Field: [23:20] ALT_DCDC_VMIN +// +// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is +// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// Voltage = (28 + ALT_DCDC_VMIN) / 16. +// 0: 1.75V +// 1: 1.8125V +// ... +// 14: 2.625V +// 15: 2.6875V +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 + +// Field: [19] ALT_DCDC_DITHER_EN +// +// Enable DC/DC dithering if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// 0: Dither disable +// 1: Dither enable +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 + +// Field: [18:16] ALT_DCDC_IPEAK +// +// Inductor peak current if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external +// inductor! +// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : +// 0: 31mA (min) +// ... +// 4: 47mA +// ... +// 7: 59mA (max) +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 + +// Field: [15:12] DELTA_IBIAS_INIT +// +// Signed delta value for IBIAS_INIT. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 + +// Field: [11:8] DELTA_IBIAS_OFFSET +// +// Signed delta value for IBIAS_OFFSET. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 + +// Field: [7:0] XOSC_MAX_START +// +// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. +// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_SIZE_AND_DIS_FLAGS +// +//***************************************************************************** +// Field: [31:16] SIZE_OF_CCFG +// +// Total size of CCFG in bytes. +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 + +// Field: [15:4] DISABLE_FLAGS +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 + +// Field: [3] DIS_TCXO +// +// Disable TCXO. +// 0: TCXO functionality enabled. +// 1: TCXO functionality disabled. +// Note: +// An external TCXO is required if DIS_TCXO = 0. +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 + +// Field: [2] DIS_GPRAM +// +// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). +// 0: GPRAM is enabled and hence CACHE disabled. +// 1: GPRAM is disabled and instead CACHE is enabled (default). +// Notes: +// - Disabling CACHE will reduce CPU execution speed (up to 60%). +// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if +// enabled. +// See: +// VIMS:CTL.MODE +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 + +// Field: [1] DIS_ALT_DCDC_SETTING +// +// Disable alternate DC/DC settings. +// 0: Enable alternate DC/DC settings. +// 1: Disable alternate DC/DC settings. +// See: +// MODE_CONF_1.ALT_DCDC_VMIN +// MODE_CONF_1.ALT_DCDC_DITHER_EN +// MODE_CONF_1.ALT_DCDC_IPEAK +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 + +// Field: [0] DIS_XOSC_OVR +// +// Disable XOSC override functionality. +// 0: Enable XOSC override functionality. +// 1: Disable XOSC override functionality. +// See: +// MODE_CONF_1.DELTA_IBIAS_INIT +// MODE_CONF_1.DELTA_IBIAS_OFFSET +// MODE_CONF_1.XOSC_MAX_START +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF +// +//***************************************************************************** +// Field: [31:28] VDDR_TRIM_SLEEP_DELTA +// +// Signed delta value to apply to the +// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. +// 0x8 (-8) : Delta = -7 +// ... +// 0xF (-1) : Delta = 0 +// 0x0 (0) : Delta = +1 +// ... +// 0x7 (7) : Delta = +8 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 + +// Field: [27] DCDC_RECHARGE +// +// DC/DC during recharge in powerdown. +// 0: Use the DC/DC during recharge in powerdown. +// 1: Do not use the DC/DC during recharge in powerdown (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 + +// Field: [26] DCDC_ACTIVE +// +// DC/DC in active mode. +// 0: Use the DC/DC during active mode. +// 1: Do not use the DC/DC during active mode (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 + +// Field: [25] VDDR_EXT_LOAD +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 + +// Field: [24] VDDS_BOD_LEVEL +// +// VDDS BOD level. +// 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on +// CC13x0). +// 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 + +// Field: [23:22] SCLK_LF_OPTION +// +// Select source for SCLK_LF. +// ENUMs: +// RCOSC_LF Low frequency RCOSC (default) +// XOSC_LF 32.768kHz low frequency XOSC +// EXTERNAL_LF External low frequency clock on DIO defined by +// EXT_LF_CLK.DIO. The RTC tick speed +// AON_RTC:SUBSECINC is updated to +// EXT_LF_CLK.RTC_INCREMENT (done in the +// trimDevice() xxWare boot function). External +// clock must always be running when the chip is +// in standby for VDDR recharge timing. +// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing +// by 768 in HW). The RTC tick speed +// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, +// corresponding to a 31.25kHz clock (done in the +// trimDevice() xxWare boot function). Standby +// power mode is not supported when using this +// clock source. +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 + +// Field: [21] VDDR_TRIM_SLEEP_TC +// +// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated +// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time +// standby mode is entered. This improves low-temperature RCOSC_LF frequency +// stability in standby mode. +// +// When temperature compensation is performed, the delta is calculates this +// way: +// Delta = max (delta, min(8, floor(62-temp)/8)) +// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current +// temperature in degrees C. +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 + +// Field: [20] RTC_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 + +// Field: [19:18] XOSC_FREQ +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +// ENUMs: +// 24M 24 MHz XOSC_HF +// 48M 48 MHz XOSC_HF +// HPOSC HPOSC +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 + +// Field: [17] XOSC_CAP_MOD +// +// Enable modification (delta) to XOSC cap-array. Value specified in +// XOSC_CAPARRAY_DELTA. +// 0: Apply cap-array delta +// 1: Do not apply cap-array delta (default) +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 + +// Field: [16] HF_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 + +// Field: [15:8] XOSC_CAPARRAY_DELTA +// +// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. +// Enabled by XOSC_CAP_MOD. +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 + +// Field: [7:0] VDDR_CAP +// +// Unsigned 8-bit integer, representing the minimum decoupling capacitance +// (worst case) on VDDR, in units of 100nF. This should take into account +// capacitor tolerance and voltage dependent capacitance variation. This bit +// affects the recharge period calculation when going into powerdown or +// standby. +// +// NOTE! If using the following functions this field must be configured (used +// by TI RTOS): +// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_0 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP45 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 + +// Field: [23:16] VDDR_EXT_TP25 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 + +// Field: [15:8] VDDR_EXT_TP5 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 + +// Field: [7:0] VDDR_EXT_TM15 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_1 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP125 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 + +// Field: [23:16] VDDR_EXT_TP105 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 + +// Field: [15:8] VDDR_EXT_TP85 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 + +// Field: [7:0] VDDR_EXT_TP65 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_RTC_OFFSET +// +//***************************************************************************** +// Field: [31:16] RTC_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 + +// Field: [15:8] RTC_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 + +// Field: [7:0] RTC_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HF_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 + +// Field: [15:8] HF_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 + +// Field: [7:0] HF_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_BL_CONFIG +// +//***************************************************************************** +// Field: [31:24] BOOTLOADER_ENABLE +// +// Bootloader enable. Boot loader can be accessed if +// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and +// conditions for boot loader backdoor are met). +// 0xC5: Boot loader is enabled. +// Any other value: Boot loader is disabled. +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 + +// Field: [16] BL_LEVEL +// +// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot +// loader backdoor is enabled by the BL_ENABLE field. +// 0: Active low. +// 1: Active high. +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 + +// Field: [15:8] BL_PIN_NUMBER +// +// DIO number that is level checked if the boot loader backdoor is enabled by +// the BL_ENABLE field. +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 + +// Field: [7:0] BL_ENABLE +// +// Enables the boot loader backdoor. +// 0xC5: Boot loader backdoor is enabled. +// Any other value: Boot loader backdoor is disabled. +// +// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader +// backdoor is enabled. +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_ERASE_CONF +// +//***************************************************************************** +// Field: [8] CHIP_ERASE_DIS_N +// +// Chip erase. +// This bit controls if a chip erase requested through the JTAG WUC TAP will be +// ignored in a following boot caused by a reset of the MCU VD. +// A successful chip erase operation will force the content of the flash main +// bank back to the state as it was when delivered by TI. +// 0: Disable. Any chip erase request detected during boot will be ignored. +// 1: Enable. Any chip erase request detected during boot will be performed by +// the boot FW. +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 + +// Field: [0] BANK_ERASE_DIS_N +// +// Bank erase. +// This bit controls if the ROM serial boot loader will accept a received Bank +// Erase command (COMMAND_BANK_ERASE). +// A successful Bank Erase operation will erase all main bank sectors not +// protected by write protect configuration bits in CCFG. +// 0: Disable the boot loader bank erase function. +// 1: Enable the boot loader bank erase function. +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TI_OPTIONS +// +//***************************************************************************** +// Field: [7:0] TI_FA_ENABLE +// +// TI Failure Analysis. +// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) +// option with the unlock code. +// All other values: Disable the functionality of unlocking the TI FA option +// with the unlock code. +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_0 +// +//***************************************************************************** +// Field: [23:16] CPU_DAP_ENABLE +// +// Enable CPU DAP. +// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM +// boot FW. +// Any other value: Main CPU DAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 + +// Field: [15:8] PRCM_TAP_ENABLE +// +// Enable PRCM TAP. +// 0xC5: PRCM TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PRCM TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 + +// Field: [7:0] TEST_TAP_ENABLE +// +// Enable Test TAP. +// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: TEST TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_1 +// +//***************************************************************************** +// Field: [23:16] PBIST2_TAP_ENABLE +// +// Enable PBIST2 TAP. +// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST2 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 + +// Field: [15:8] PBIST1_TAP_ENABLE +// +// Enable PBIST1 TAP. +// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST1 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 + +// Field: [7:0] WUC_TAP_ENABLE +// +// Enable WUC TAP +// 0xC5: WUC TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: WUC TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IMAGE_VALID_CONF +// +//***************************************************************************** +// Field: [31:0] IMAGE_VALID +// +// This field must have a value of 0x00000000 in order for enabling the boot +// sequence to transfer control to a flash image. +// A non-zero value forces the boot sequence to call the boot loader. +// +// For CC2640R2: +// This field must have the address value of the start of the flash vector +// table in order for enabling the boot sequence to transfer control to a flash +// image. +// Any illegal vector table start address value forces the boot sequence to +// call the boot loader. +// Note that if any other legal vector table start address value than 0x0 is +// selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_31_0 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_31 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 + +// Field: [30] WRT_PROT_SEC_30 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 + +// Field: [29] WRT_PROT_SEC_29 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 + +// Field: [28] WRT_PROT_SEC_28 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 + +// Field: [27] WRT_PROT_SEC_27 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 + +// Field: [26] WRT_PROT_SEC_26 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 + +// Field: [25] WRT_PROT_SEC_25 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 + +// Field: [24] WRT_PROT_SEC_24 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 + +// Field: [23] WRT_PROT_SEC_23 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 + +// Field: [22] WRT_PROT_SEC_22 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 + +// Field: [21] WRT_PROT_SEC_21 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 + +// Field: [20] WRT_PROT_SEC_20 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 + +// Field: [19] WRT_PROT_SEC_19 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 + +// Field: [18] WRT_PROT_SEC_18 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 + +// Field: [17] WRT_PROT_SEC_17 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 + +// Field: [16] WRT_PROT_SEC_16 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 + +// Field: [15] WRT_PROT_SEC_15 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 + +// Field: [14] WRT_PROT_SEC_14 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 + +// Field: [13] WRT_PROT_SEC_13 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 + +// Field: [12] WRT_PROT_SEC_12 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 + +// Field: [11] WRT_PROT_SEC_11 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 + +// Field: [10] WRT_PROT_SEC_10 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 + +// Field: [9] WRT_PROT_SEC_9 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 + +// Field: [8] WRT_PROT_SEC_8 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 + +// Field: [7] WRT_PROT_SEC_7 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 + +// Field: [6] WRT_PROT_SEC_6 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 + +// Field: [5] WRT_PROT_SEC_5 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 + +// Field: [4] WRT_PROT_SEC_4 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 + +// Field: [3] WRT_PROT_SEC_3 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 + +// Field: [2] WRT_PROT_SEC_2 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 + +// Field: [1] WRT_PROT_SEC_1 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 + +// Field: [0] WRT_PROT_SEC_0 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_63_32 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_63 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 + +// Field: [30] WRT_PROT_SEC_62 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 + +// Field: [29] WRT_PROT_SEC_61 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 + +// Field: [28] WRT_PROT_SEC_60 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 + +// Field: [27] WRT_PROT_SEC_59 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 + +// Field: [26] WRT_PROT_SEC_58 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 + +// Field: [25] WRT_PROT_SEC_57 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 + +// Field: [24] WRT_PROT_SEC_56 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 + +// Field: [23] WRT_PROT_SEC_55 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 + +// Field: [22] WRT_PROT_SEC_54 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 + +// Field: [21] WRT_PROT_SEC_53 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 + +// Field: [20] WRT_PROT_SEC_52 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 + +// Field: [19] WRT_PROT_SEC_51 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 + +// Field: [18] WRT_PROT_SEC_50 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 + +// Field: [17] WRT_PROT_SEC_49 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 + +// Field: [16] WRT_PROT_SEC_48 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 + +// Field: [15] WRT_PROT_SEC_47 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 + +// Field: [14] WRT_PROT_SEC_46 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 + +// Field: [13] WRT_PROT_SEC_45 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 + +// Field: [12] WRT_PROT_SEC_44 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 + +// Field: [11] WRT_PROT_SEC_43 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 + +// Field: [10] WRT_PROT_SEC_42 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 + +// Field: [9] WRT_PROT_SEC_41 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 + +// Field: [8] WRT_PROT_SEC_40 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 + +// Field: [7] WRT_PROT_SEC_39 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 + +// Field: [6] WRT_PROT_SEC_38 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 + +// Field: [5] WRT_PROT_SEC_37 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 + +// Field: [4] WRT_PROT_SEC_36 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 + +// Field: [3] WRT_PROT_SEC_35 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 + +// Field: [2] WRT_PROT_SEC_34 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 + +// Field: [1] WRT_PROT_SEC_33 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 + +// Field: [0] WRT_PROT_SEC_32 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_95_64 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_95 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 + +// Field: [30] WRT_PROT_SEC_94 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 + +// Field: [29] WRT_PROT_SEC_93 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 + +// Field: [28] WRT_PROT_SEC_92 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 + +// Field: [27] WRT_PROT_SEC_91 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 + +// Field: [26] WRT_PROT_SEC_90 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 + +// Field: [25] WRT_PROT_SEC_89 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 + +// Field: [24] WRT_PROT_SEC_88 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 + +// Field: [23] WRT_PROT_SEC_87 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 + +// Field: [22] WRT_PROT_SEC_86 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 + +// Field: [21] WRT_PROT_SEC_85 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 + +// Field: [20] WRT_PROT_SEC_84 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 + +// Field: [19] WRT_PROT_SEC_83 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 + +// Field: [18] WRT_PROT_SEC_82 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 + +// Field: [17] WRT_PROT_SEC_81 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 + +// Field: [16] WRT_PROT_SEC_80 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 + +// Field: [15] WRT_PROT_SEC_79 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 + +// Field: [14] WRT_PROT_SEC_78 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 + +// Field: [13] WRT_PROT_SEC_77 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 + +// Field: [12] WRT_PROT_SEC_76 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 + +// Field: [11] WRT_PROT_SEC_75 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 + +// Field: [10] WRT_PROT_SEC_74 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 + +// Field: [9] WRT_PROT_SEC_73 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 + +// Field: [8] WRT_PROT_SEC_72 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 + +// Field: [7] WRT_PROT_SEC_71 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 + +// Field: [6] WRT_PROT_SEC_70 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 + +// Field: [5] WRT_PROT_SEC_69 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 + +// Field: [4] WRT_PROT_SEC_68 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 + +// Field: [3] WRT_PROT_SEC_67 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 + +// Field: [2] WRT_PROT_SEC_66 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 + +// Field: [1] WRT_PROT_SEC_65 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 + +// Field: [0] WRT_PROT_SEC_64 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_127_96 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_127 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 + +// Field: [30] WRT_PROT_SEC_126 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 + +// Field: [29] WRT_PROT_SEC_125 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 + +// Field: [28] WRT_PROT_SEC_124 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 + +// Field: [27] WRT_PROT_SEC_123 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 + +// Field: [26] WRT_PROT_SEC_122 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 + +// Field: [25] WRT_PROT_SEC_121 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 + +// Field: [24] WRT_PROT_SEC_120 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 + +// Field: [23] WRT_PROT_SEC_119 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 + +// Field: [22] WRT_PROT_SEC_118 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 + +// Field: [21] WRT_PROT_SEC_117 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 + +// Field: [20] WRT_PROT_SEC_116 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 + +// Field: [19] WRT_PROT_SEC_115 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 + +// Field: [18] WRT_PROT_SEC_114 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 + +// Field: [17] WRT_PROT_SEC_113 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 + +// Field: [16] WRT_PROT_SEC_112 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 + +// Field: [15] WRT_PROT_SEC_111 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 + +// Field: [14] WRT_PROT_SEC_110 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 + +// Field: [13] WRT_PROT_SEC_109 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 + +// Field: [12] WRT_PROT_SEC_108 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 + +// Field: [11] WRT_PROT_SEC_107 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 + +// Field: [10] WRT_PROT_SEC_106 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 + +// Field: [9] WRT_PROT_SEC_105 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 + +// Field: [8] WRT_PROT_SEC_104 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 + +// Field: [7] WRT_PROT_SEC_103 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 + +// Field: [6] WRT_PROT_SEC_102 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 + +// Field: [5] WRT_PROT_SEC_101 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 + +// Field: [4] WRT_PROT_SEC_100 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 + +// Field: [3] WRT_PROT_SEC_99 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 + +// Field: [2] WRT_PROT_SEC_98 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 + +// Field: [1] WRT_PROT_SEC_97 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 + +// Field: [0] WRT_PROT_SEC_96 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 + + +#endif // __CCFG__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ccfg_simple_struct.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ccfg_simple_struct.h new file mode 100644 index 0000000000..cdce58f2bc --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ccfg_simple_struct.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* Filename: hw_ccfg_simple_struct_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ +#define __HW_CCFG_SIMPLE_STRUCT_H__ + +//***************************************************************************** +// +// Customer configuration (ccfg) typedef. +// The implementation of this struct is required by device ROM boot code +// and must be placed at the end of flash. Do not modify this struct! +// +//***************************************************************************** +typedef struct +{ // Mapped to address + uint32_t CCFG_EXT_LF_CLK ; // 0x50003FA8 + uint32_t CCFG_MODE_CONF_1 ; // 0x50003FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50003FB0 + uint32_t CCFG_MODE_CONF ; // 0x50003FB4 + uint32_t CCFG_VOLT_LOAD_0 ; // 0x50003FB8 + uint32_t CCFG_VOLT_LOAD_1 ; // 0x50003FBC + uint32_t CCFG_RTC_OFFSET ; // 0x50003FC0 + uint32_t CCFG_FREQ_OFFSET ; // 0x50003FC4 + uint32_t CCFG_IEEE_MAC_0 ; // 0x50003FC8 + uint32_t CCFG_IEEE_MAC_1 ; // 0x50003FCC + uint32_t CCFG_IEEE_BLE_0 ; // 0x50003FD0 + uint32_t CCFG_IEEE_BLE_1 ; // 0x50003FD4 + uint32_t CCFG_BL_CONFIG ; // 0x50003FD8 + uint32_t CCFG_ERASE_CONF ; // 0x50003FDC + uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50003FE0 + uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50003FE4 + uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50003FE8 + uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50003FEC + uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50003FF0 + uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50003FF4 + uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50003FF8 + uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50003FFC +} ccfg_t; + +//***************************************************************************** +// +// Define the extern ccfg structure (__ccfg) +// +//***************************************************************************** +extern const ccfg_t __ccfg; + + +#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_chip_def.h b/os/common/ext/TI/devices/cc13x0/inc/hw_chip_def.h new file mode 100644 index 0000000000..2c9c7e0b0f --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_chip_def.h @@ -0,0 +1,237 @@ +/****************************************************************************** +* Filename: hw_chip_def.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Description: Defines for device properties. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup config_api +//! @{ +// +//***************************************************************************** + +#ifndef __HW_CHIP_DEF_H__ +#define __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Define CC_CHIP_ID code used in the following macros defined at the bottom: +// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV +// +//***************************************************************************** +/* CC2620F128 */ +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) + #define CC_CHIP_ID 0x26200720 +#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) + #define CC_CHIP_ID 0x26200520 +#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) + #define CC_CHIP_ID 0x26200420 +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) + #define CC_CHIP_ID 0x26200020 +#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) + #define CC_CHIP_ID 0x26200722 +#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) + #define CC_CHIP_ID 0x26200522 +#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) + #define CC_CHIP_ID 0x26200422 +#elif defined(CC2620F128_R22) || defined(CC2620F128) + #define CC_CHIP_ID 0x26200022 +/* CC2630F128 */ +#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) + #define CC_CHIP_ID 0x26300720 +#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) + #define CC_CHIP_ID 0x26300520 +#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) + #define CC_CHIP_ID 0x26300420 +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) + #define CC_CHIP_ID 0x26300020 +#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) + #define CC_CHIP_ID 0x26300722 +#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) + #define CC_CHIP_ID 0x26300522 +#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) + #define CC_CHIP_ID 0x26300422 +#elif defined(CC2630F128_R22) || defined(CC2630F128) + #define CC_CHIP_ID 0x26300022 +/* CC2640F128 */ +#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) + #define CC_CHIP_ID 0x26400720 +#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) + #define CC_CHIP_ID 0x26400520 +#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) + #define CC_CHIP_ID 0x26400420 +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) + #define CC_CHIP_ID 0x26400020 +#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) + #define CC_CHIP_ID 0x26400722 +#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) + #define CC_CHIP_ID 0x26400522 +#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) + #define CC_CHIP_ID 0x26400422 +#elif defined(CC2640F128_R22) || defined(CC2640F128) + #define CC_CHIP_ID 0x26400022 +/* CC2650F128 */ +#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) + #define CC_CHIP_ID 0x26500720 +#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) + #define CC_CHIP_ID 0x26500520 +#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) + #define CC_CHIP_ID 0x26500420 +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) + #define CC_CHIP_ID 0x26500020 +#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) + #define CC_CHIP_ID 0x26500722 +#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) + #define CC_CHIP_ID 0x26500522 +#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) + #define CC_CHIP_ID 0x26500422 +#elif defined(CC2650F128_R22) || defined(CC2650F128) + #define CC_CHIP_ID 0x26500022 +/* CC2650L128 (OTP) */ +#elif defined(CC2650L128) + #define CC_CHIP_ID 0x26501710 +/* CC1310F128 */ +#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) + #define CC_CHIP_ID 0x13100720 +#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) + #define CC_CHIP_ID 0x13100520 +#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) + #define CC_CHIP_ID 0x13100420 +#elif defined(CC1310F128_R20) || defined(CC1310F128) + #define CC_CHIP_ID 0x13100020 +/* CC1350F128 */ +#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) + #define CC_CHIP_ID 0x13500720 +#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) + #define CC_CHIP_ID 0x13500520 +#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) + #define CC_CHIP_ID 0x13500420 +#elif defined(CC1350F128_R20) || defined(CC1350F128) + #define CC_CHIP_ID 0x13500020 +/* CC2640R2F */ +#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) + #define CC_CHIP_ID 0x26401710 +#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) + #define CC_CHIP_ID 0x26401510 +#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) + #define CC_CHIP_ID 0x26401410 +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) + #define CC_CHIP_ID 0x26401010 +/* CC2652R1F */ +#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) + #define CC_CHIP_ID 0x26523710 +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) + #define CC_CHIP_ID 0x26523010 +/* CC2644R1F */ +#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) + #define CC_CHIP_ID 0x26443710 +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) + #define CC_CHIP_ID 0x26443010 +/* CC2642R1F */ +#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) + #define CC_CHIP_ID 0x26423710 +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) + #define CC_CHIP_ID 0x26423010 +/* CC1354R1F */ +#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) + #define CC_CHIP_ID 0x13543710 +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) + #define CC_CHIP_ID 0x13543010 +/* CC1352R1F */ +#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) + #define CC_CHIP_ID 0x13523710 +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) + #define CC_CHIP_ID 0x13523010 +/* CC1312R1F */ +#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) + #define CC_CHIP_ID 0x13123710 +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) + #define CC_CHIP_ID 0x13123010 +#endif + +#define CC_GET_CHIP_FAMILY 0x13 +#define CC_GET_CHIP_OPTION 0x0 +#define CC_GET_CHIP_HWREV 0x20 + +#ifdef CC_CHIP_ID + /* Define chip package only if specified */ + #if (CC_CHIP_ID & 0x00000F00) != 0 + #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) + #endif + + /* Define chip device */ + #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) + + /* The chip family, option and package shall match the DriverLib release */ + #if (CC_GET_CHIP_FAMILY != ((CC_CHIP_ID & 0xFF000000) >> 24)) + #error "Specified chip family does not match DriverLib release" + #endif + #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) + #error "Specified chip option does not match DriverLib release" + #endif + #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) + #error "Specified chip hardware revision does not match DriverLib release" + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_dwt.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_dwt.h new file mode 100644 index 0000000000..322dfa4877 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_dwt.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: hw_cpu_dwt_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_DWT_H__ +#define __HW_CPU_DWT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_DWT component +// +//***************************************************************************** +// Control +#define CPU_DWT_O_CTRL 0x00000000 + +// Current PC Sampler Cycle Count +#define CPU_DWT_O_CYCCNT 0x00000004 + +// CPI Count +#define CPU_DWT_O_CPICNT 0x00000008 + +// Exception Overhead Count +#define CPU_DWT_O_EXCCNT 0x0000000C + +// Sleep Count +#define CPU_DWT_O_SLEEPCNT 0x00000010 + +// LSU Count +#define CPU_DWT_O_LSUCNT 0x00000014 + +// Fold Count +#define CPU_DWT_O_FOLDCNT 0x00000018 + +// Program Counter Sample +#define CPU_DWT_O_PCSR 0x0000001C + +// Comparator 0 +#define CPU_DWT_O_COMP0 0x00000020 + +// Mask 0 +#define CPU_DWT_O_MASK0 0x00000024 + +// Function 0 +#define CPU_DWT_O_FUNCTION0 0x00000028 + +// Comparator 1 +#define CPU_DWT_O_COMP1 0x00000030 + +// Mask 1 +#define CPU_DWT_O_MASK1 0x00000034 + +// Function 1 +#define CPU_DWT_O_FUNCTION1 0x00000038 + +// Comparator 2 +#define CPU_DWT_O_COMP2 0x00000040 + +// Mask 2 +#define CPU_DWT_O_MASK2 0x00000044 + +// Function 2 +#define CPU_DWT_O_FUNCTION2 0x00000048 + +// Comparator 3 +#define CPU_DWT_O_COMP3 0x00000050 + +// Mask 3 +#define CPU_DWT_O_MASK3 0x00000054 + +// Function 3 +#define CPU_DWT_O_FUNCTION3 0x00000058 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CTRL +// +//***************************************************************************** +// Field: [25] NOCYCCNT +// +// When set, CYCCNT is not supported. +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 + +// Field: [24] NOPRFCNT +// +// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 + +// Field: [22] CYCEVTENA +// +// Enables Cycle count event. Emits an event when the POSTCNT counter triggers +// it. See CYCTAP and POSTPRESET for details. This event is only emitted if +// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. +// +// 0: Cycle count events disabled +// 1: Cycle count events enabled +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 + +// Field: [21] FOLDEVTENA +// +// Enables Folded instruction count event. Emits an event when FOLDCNT +// overflows (every 256 cycles of folded instructions). A folded instruction is +// one that does not incur even one cycle to execute. For example, an IT +// instruction is folded away and so does not use up one cycle. +// +// 0: Folded instruction count events disabled. +// 1: Folded instruction count events enabled. +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 + +// Field: [20] LSUEVTENA +// +// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 +// cycles of LSU operation). LSU counts include all LSU costs after the initial +// cycle for the instruction. +// +// 0: LSU count events disabled. +// 1: LSU count events enabled. +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 + +// Field: [19] SLEEPEVTENA +// +// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 +// cycles that the processor is sleeping). +// +// 0: Sleep count events disabled. +// 1: Sleep count events enabled. +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 + +// Field: [18] EXCEVTENA +// +// Enables Interrupt overhead event. Emits an event when EXCCNT overflows +// (every 256 cycles of interrupt overhead). +// +// 0x0: Interrupt overhead event disabled. +// 0x1: Interrupt overhead event enabled. +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 + +// Field: [17] CPIEVTENA +// +// Enables CPI count event. Emits an event when CPICNT overflows (every 256 +// cycles of multi-cycle instructions). +// +// 0: CPI counter events disabled. +// 1: CPI counter events enabled. +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 + +// Field: [16] EXCTRCENA +// +// Enables Interrupt event tracing. +// +// 0: Interrupt event trace disabled. +// 1: Interrupt event trace enabled. +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 + +// Field: [12] PCSAMPLEENA +// +// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT +// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this +// bit overrides CYCEVTENA. +// +// 0: PC Sampling event disabled. +// 1: Sampling event enabled. +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 + +// Field: [11:10] SYNCTAP +// +// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA +// must also be enabled for this feature. +// Synchronization packets (if enabled) are generated on tap transitions (0 to1 +// or 1 to 0). +// ENUMs: +// BIT28 Tap at bit 28 of CYCCNT +// BIT26 Tap at bit 26 of CYCCNT +// BIT24 Tap at bit 24 of CYCCNT +// DIS Disabled. No synchronization packets +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 + +// Field: [9] CYCTAP +// +// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the +// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the +// POSTCNT, post-scalar counter. That counter then counts down. On a bit change +// when post-scalar is 0, it triggers an event for PC sampling or cycle count +// event (see details in CYCEVTENA). +// ENUMs: +// BIT10 Selects bit [10] to tap +// BIT6 Selects bit [6] to tap +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 + +// Field: [8:5] POSTCNT +// +// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 +// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it +// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the +// value from POSTPRESET. +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 + +// Field: [4:1] POSTPRESET +// +// Reload value for post-scalar counter POSTCNT. When 0, events are triggered +// on each tap change (a power of 2). If this field has a non-0 value, it forms +// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For +// example, a value 1 in this register means an event is formed every other tap +// change. +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 + +// Field: [0] CYCCNTENA +// +// Enable CYCCNT, allowing it to increment and generate synchronization and +// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CYCCNT +// +//***************************************************************************** +// Field: [31:0] CYCCNT +// +// Current PC Sampler Cycle Counter count value. When enabled, this counter +// counts the number of core cycles, except when the core is halted. The cycle +// counter is a free running counter, counting upwards (this counter will not +// advance in power modes where free-running clock to CPU stops). It wraps +// around to 0 on overflow. The debugger must initialize this to 0 when first +// enabling. +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CPICNT +// +//***************************************************************************** +// Field: [7:0] CPICNT +// +// Current CPI counter value. Increments on the additional cycles (the first +// cycle is not counted) required to execute all instructions except those +// recorded by LSUCNT. This counter also increments on all instruction fetch +// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter +// overflows. This counter initializes to 0 when it is enabled using +// CTRL.CPIEVTENA. +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_EXCCNT +// +//***************************************************************************** +// Field: [7:0] EXCCNT +// +// Current interrupt overhead counter value. Counts the total cycles spent in +// interrupt processing (for example entry stacking, return unstacking, +// pre-emption). An event is emitted on counter overflow (every 256 cycles). +// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_SLEEPCNT +// +//***************************************************************************** +// Field: [7:0] SLEEPCNT +// +// Sleep counter. Counts the number of cycles during which the processor is +// sleeping. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note +// that the sleep counter is clocked using CPU's free-running clock. In some +// power modes the free-running clock to CPU is gated to minimize power +// consumption. This means that the sleep counter will be invalid in these +// power modes. +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_LSUCNT +// +//***************************************************************************** +// Field: [7:0] LSUCNT +// +// LSU counter. This counts the total number of cycles that the processor is +// processing an LSU operation. The initial execution cost of the instruction +// is not counted. For example, an LDR that takes two cycles to complete +// increments this counter one cycle. Equivalently, an LDR that stalls for two +// cycles (i.e. takes four cycles to execute), increments this counter three +// times. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FOLDCNT +// +//***************************************************************************** +// Field: [7:0] FOLDCNT +// +// This counts the total number folded instructions. This counter initializes +// to 0 when it is enabled using CTRL.FOLDEVTENA. +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_PCSR +// +//***************************************************************************** +// Field: [31:0] EIASAMPLE +// +// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP0 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler +// Counter (CYCCNT). +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK0 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP0. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP0. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION0 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 + +// Field: [7] CYCMATCH +// +// This bit is only available in comparator 0. When set, COMP0 will compare +// against the cycle counter (CYCCNT). +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP1 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION1. +// Comparator 1 can also compare data values. So this register can contain +// reference values for data matching. +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK1 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP1. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP1. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION1 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 + +// Field: [19:16] DATAVADDR1 +// +// Identity of a second linked address comparator for data value matching when +// DATAVMATCH == 1 and LNK1ENA == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 + +// Field: [15:12] DATAVADDR0 +// +// Identity of a linked address comparator for data value matching when +// DATAVMATCH == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 + +// Field: [11:10] DATAVSIZE +// +// Defines the size of the data in the COMP1 register that is to be matched: +// +// 0x0: Byte +// 0x1: Halfword +// 0x2: Word +// 0x3: Unpredictable. +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 + +// Field: [9] LNK1ENA +// +// Read only bit-field only supported in comparator 1. +// +// 0: DATAVADDR1 not supported +// 1: DATAVADDR1 supported (enabled) +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 + +// Field: [8] DATAVMATCH +// +// Data match feature: +// +// 0: Perform address comparison +// 1: Perform data value compare. The comparators given by DATAVADDR0 and +// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting +// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and +// those comparators only provide the address match for the data comparison. +// +// This bit is only available in comparator 1. +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings: +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and +// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 +// and DATAVADDR1 can then only perform address comparator matches for +// comparator 1 data matches. +// Note 4: If the data matching functionality is not included during +// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or +// DATAVMATCH. This means that the data matching functionality is not available +// in the implementation. Test the availability of data matching by writing and +// reading DATAVMATCH. If it is not settable then data matching is unavailable. +// Note 5: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP2 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION2. +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK2 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP2. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP2. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION2 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP3 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION3. +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK3 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP3. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP3. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION3 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 + + +#endif // __CPU_DWT__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_fpb.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_fpb.h new file mode 100644 index 0000000000..73466f9cde --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_fpb.h @@ -0,0 +1,443 @@ +/****************************************************************************** +* Filename: hw_cpu_fpb_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_FPB_H__ +#define __HW_CPU_FPB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_FPB component +// +//***************************************************************************** +// Control +#define CPU_FPB_O_CTRL 0x00000000 + +// Remap +#define CPU_FPB_O_REMAP 0x00000004 + +// Comparator 0 +#define CPU_FPB_O_COMP0 0x00000008 + +// Comparator 1 +#define CPU_FPB_O_COMP1 0x0000000C + +// Comparator 2 +#define CPU_FPB_O_COMP2 0x00000010 + +// Comparator 3 +#define CPU_FPB_O_COMP3 0x00000014 + +// Comparator 4 +#define CPU_FPB_O_COMP4 0x00000018 + +// Comparator 5 +#define CPU_FPB_O_COMP5 0x0000001C + +// Comparator 6 +#define CPU_FPB_O_COMP6 0x00000020 + +// Comparator 7 +#define CPU_FPB_O_COMP7 0x00000024 + +//***************************************************************************** +// +// Register: CPU_FPB_O_CTRL +// +//***************************************************************************** +// Field: [13:12] NUM_CODE2 +// +// Number of full banks of code comparators, sixteen comparators per bank. +// Where less than sixteen code comparators are provided, the bank count is +// zero, and the number present indicated by NUM_CODE1. This read only field +// contains 3'b000 to indicate 0 banks for Cortex-M processor. +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 + +// Field: [11:8] NUM_LIT +// +// Number of literal slots field. +// +// 0x0: No literal slots +// 0x2: Two literal slots +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 + +// Field: [7:4] NUM_CODE1 +// +// Number of code slots field. +// +// 0x0: No code slots +// 0x2: Two code slots +// 0x6: Six code slots +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 + +// Field: [1] KEY +// +// Key field. In order to write to this register, this bit-field must be +// written to '1'. This bit always reads 0. +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 + +// Field: [0] ENABLE +// +// Flash patch unit enable bit +// +// 0x0: Flash patch unit disabled +// 0x1: Flash patch unit enabled +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_REMAP +// +//***************************************************************************** +// Field: [28:5] REMAP +// +// Remap base address field. +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP0 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 0 disabled +// 0x1: Compare and remap for comparator 0 enabled +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP1 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 1 disabled +// 0x1: Compare and remap for comparator 1 enabled +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP2 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 2 disabled +// 0x1: Compare and remap for comparator 2 enabled +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP3 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 3 disabled +// 0x1: Compare and remap for comparator 3 enabled +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP4 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 4 disabled +// 0x1: Compare and remap for comparator 4 enabled +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP5 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 5 disabled +// 0x1: Compare and remap for comparator 5 enabled +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP6 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 6 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 6 disabled +// 0x1: Compare and remap for comparator 6 enabled +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP7 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 7 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 7 disabled +// 0x1: Compare and remap for comparator 7 enabled +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 + + +#endif // __CPU_FPB__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_itm.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_itm.h new file mode 100644 index 0000000000..6fe1ab93cd --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_itm.h @@ -0,0 +1,1122 @@ +/****************************************************************************** +* Filename: hw_cpu_itm_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ITM_H__ +#define __HW_CPU_ITM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ITM component +// +//***************************************************************************** +// Stimulus Port 0 +#define CPU_ITM_O_STIM0 0x00000000 + +// Stimulus Port 1 +#define CPU_ITM_O_STIM1 0x00000004 + +// Stimulus Port 2 +#define CPU_ITM_O_STIM2 0x00000008 + +// Stimulus Port 3 +#define CPU_ITM_O_STIM3 0x0000000C + +// Stimulus Port 4 +#define CPU_ITM_O_STIM4 0x00000010 + +// Stimulus Port 5 +#define CPU_ITM_O_STIM5 0x00000014 + +// Stimulus Port 6 +#define CPU_ITM_O_STIM6 0x00000018 + +// Stimulus Port 7 +#define CPU_ITM_O_STIM7 0x0000001C + +// Stimulus Port 8 +#define CPU_ITM_O_STIM8 0x00000020 + +// Stimulus Port 9 +#define CPU_ITM_O_STIM9 0x00000024 + +// Stimulus Port 10 +#define CPU_ITM_O_STIM10 0x00000028 + +// Stimulus Port 11 +#define CPU_ITM_O_STIM11 0x0000002C + +// Stimulus Port 12 +#define CPU_ITM_O_STIM12 0x00000030 + +// Stimulus Port 13 +#define CPU_ITM_O_STIM13 0x00000034 + +// Stimulus Port 14 +#define CPU_ITM_O_STIM14 0x00000038 + +// Stimulus Port 15 +#define CPU_ITM_O_STIM15 0x0000003C + +// Stimulus Port 16 +#define CPU_ITM_O_STIM16 0x00000040 + +// Stimulus Port 17 +#define CPU_ITM_O_STIM17 0x00000044 + +// Stimulus Port 18 +#define CPU_ITM_O_STIM18 0x00000048 + +// Stimulus Port 19 +#define CPU_ITM_O_STIM19 0x0000004C + +// Stimulus Port 20 +#define CPU_ITM_O_STIM20 0x00000050 + +// Stimulus Port 21 +#define CPU_ITM_O_STIM21 0x00000054 + +// Stimulus Port 22 +#define CPU_ITM_O_STIM22 0x00000058 + +// Stimulus Port 23 +#define CPU_ITM_O_STIM23 0x0000005C + +// Stimulus Port 24 +#define CPU_ITM_O_STIM24 0x00000060 + +// Stimulus Port 25 +#define CPU_ITM_O_STIM25 0x00000064 + +// Stimulus Port 26 +#define CPU_ITM_O_STIM26 0x00000068 + +// Stimulus Port 27 +#define CPU_ITM_O_STIM27 0x0000006C + +// Stimulus Port 28 +#define CPU_ITM_O_STIM28 0x00000070 + +// Stimulus Port 29 +#define CPU_ITM_O_STIM29 0x00000074 + +// Stimulus Port 30 +#define CPU_ITM_O_STIM30 0x00000078 + +// Stimulus Port 31 +#define CPU_ITM_O_STIM31 0x0000007C + +// Trace Enable +#define CPU_ITM_O_TER 0x00000E00 + +// Trace Privilege +#define CPU_ITM_O_TPR 0x00000E40 + +// Trace Control +#define CPU_ITM_O_TCR 0x00000E80 + +// Lock Access +#define CPU_ITM_O_LAR 0x00000FB0 + +// Lock Status +#define CPU_ITM_O_LSR 0x00000FB4 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM0 +// +//***************************************************************************** +// Field: [31:0] STIM0 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM1 +// +//***************************************************************************** +// Field: [31:0] STIM1 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM2 +// +//***************************************************************************** +// Field: [31:0] STIM2 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM3 +// +//***************************************************************************** +// Field: [31:0] STIM3 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM4 +// +//***************************************************************************** +// Field: [31:0] STIM4 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM5 +// +//***************************************************************************** +// Field: [31:0] STIM5 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM6 +// +//***************************************************************************** +// Field: [31:0] STIM6 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM7 +// +//***************************************************************************** +// Field: [31:0] STIM7 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM8 +// +//***************************************************************************** +// Field: [31:0] STIM8 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM9 +// +//***************************************************************************** +// Field: [31:0] STIM9 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM10 +// +//***************************************************************************** +// Field: [31:0] STIM10 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM11 +// +//***************************************************************************** +// Field: [31:0] STIM11 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM12 +// +//***************************************************************************** +// Field: [31:0] STIM12 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM13 +// +//***************************************************************************** +// Field: [31:0] STIM13 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM14 +// +//***************************************************************************** +// Field: [31:0] STIM14 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM15 +// +//***************************************************************************** +// Field: [31:0] STIM15 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM16 +// +//***************************************************************************** +// Field: [31:0] STIM16 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM17 +// +//***************************************************************************** +// Field: [31:0] STIM17 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM18 +// +//***************************************************************************** +// Field: [31:0] STIM18 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM19 +// +//***************************************************************************** +// Field: [31:0] STIM19 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM20 +// +//***************************************************************************** +// Field: [31:0] STIM20 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM21 +// +//***************************************************************************** +// Field: [31:0] STIM21 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM22 +// +//***************************************************************************** +// Field: [31:0] STIM22 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM23 +// +//***************************************************************************** +// Field: [31:0] STIM23 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM24 +// +//***************************************************************************** +// Field: [31:0] STIM24 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM25 +// +//***************************************************************************** +// Field: [31:0] STIM25 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM26 +// +//***************************************************************************** +// Field: [31:0] STIM26 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM27 +// +//***************************************************************************** +// Field: [31:0] STIM27 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM28 +// +//***************************************************************************** +// Field: [31:0] STIM28 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM29 +// +//***************************************************************************** +// Field: [31:0] STIM29 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM30 +// +//***************************************************************************** +// Field: [31:0] STIM30 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM31 +// +//***************************************************************************** +// Field: [31:0] STIM31 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TER +// +//***************************************************************************** +// Field: [31] STIMENA31 +// +// Bit mask to enable tracing on ITM stimulus port 31. +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 + +// Field: [30] STIMENA30 +// +// Bit mask to enable tracing on ITM stimulus port 30. +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 + +// Field: [29] STIMENA29 +// +// Bit mask to enable tracing on ITM stimulus port 29. +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 + +// Field: [28] STIMENA28 +// +// Bit mask to enable tracing on ITM stimulus port 28. +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 + +// Field: [27] STIMENA27 +// +// Bit mask to enable tracing on ITM stimulus port 27. +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 + +// Field: [26] STIMENA26 +// +// Bit mask to enable tracing on ITM stimulus port 26. +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 + +// Field: [25] STIMENA25 +// +// Bit mask to enable tracing on ITM stimulus port 25. +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 + +// Field: [24] STIMENA24 +// +// Bit mask to enable tracing on ITM stimulus port 24. +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 + +// Field: [23] STIMENA23 +// +// Bit mask to enable tracing on ITM stimulus port 23. +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 + +// Field: [22] STIMENA22 +// +// Bit mask to enable tracing on ITM stimulus port 22. +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 + +// Field: [21] STIMENA21 +// +// Bit mask to enable tracing on ITM stimulus port 21. +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 + +// Field: [20] STIMENA20 +// +// Bit mask to enable tracing on ITM stimulus port 20. +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 + +// Field: [19] STIMENA19 +// +// Bit mask to enable tracing on ITM stimulus port 19. +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 + +// Field: [18] STIMENA18 +// +// Bit mask to enable tracing on ITM stimulus port 18. +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 + +// Field: [17] STIMENA17 +// +// Bit mask to enable tracing on ITM stimulus port 17. +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 + +// Field: [16] STIMENA16 +// +// Bit mask to enable tracing on ITM stimulus port 16. +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 + +// Field: [15] STIMENA15 +// +// Bit mask to enable tracing on ITM stimulus port 15. +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 + +// Field: [14] STIMENA14 +// +// Bit mask to enable tracing on ITM stimulus port 14. +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 + +// Field: [13] STIMENA13 +// +// Bit mask to enable tracing on ITM stimulus port 13. +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 + +// Field: [12] STIMENA12 +// +// Bit mask to enable tracing on ITM stimulus port 12. +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 + +// Field: [11] STIMENA11 +// +// Bit mask to enable tracing on ITM stimulus port 11. +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 + +// Field: [10] STIMENA10 +// +// Bit mask to enable tracing on ITM stimulus port 10. +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 + +// Field: [9] STIMENA9 +// +// Bit mask to enable tracing on ITM stimulus port 9. +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 + +// Field: [8] STIMENA8 +// +// Bit mask to enable tracing on ITM stimulus port 8. +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 + +// Field: [7] STIMENA7 +// +// Bit mask to enable tracing on ITM stimulus port 7. +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 + +// Field: [6] STIMENA6 +// +// Bit mask to enable tracing on ITM stimulus port 6. +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 + +// Field: [5] STIMENA5 +// +// Bit mask to enable tracing on ITM stimulus port 5. +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 + +// Field: [4] STIMENA4 +// +// Bit mask to enable tracing on ITM stimulus port 4. +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 + +// Field: [3] STIMENA3 +// +// Bit mask to enable tracing on ITM stimulus port 3. +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 + +// Field: [2] STIMENA2 +// +// Bit mask to enable tracing on ITM stimulus port 2. +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 + +// Field: [1] STIMENA1 +// +// Bit mask to enable tracing on ITM stimulus port 1. +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 + +// Field: [0] STIMENA0 +// +// Bit mask to enable tracing on ITM stimulus port 0. +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TPR +// +//***************************************************************************** +// Field: [3:0] PRIVMASK +// +// Bit mask to enable unprivileged (User) access to ITM stimulus ports: +// +// Bit [0] enables stimulus ports 0, 1, ..., and 7. +// Bit [1] enables stimulus ports 8, 9, ..., and 15. +// Bit [2] enables stimulus ports 16, 17, ..., and 23. +// Bit [3] enables stimulus ports 24, 25, ..., and 31. +// +// 0: User access allowed to stimulus ports +// 1: Privileged access only to stimulus ports +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TCR +// +//***************************************************************************** +// Field: [23] BUSY +// +// Set when ITM events present and being drained. +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 + +// Field: [22:16] ATBID +// +// Trace Bus ID for CoreSight system. Optional identifier for multi-source +// trace stream formatting. If multi-source trace is in use, this field must be +// written with a non-zero value. +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 + +// Field: [9:8] TSPRESCALE +// +// Timestamp prescaler +// ENUMs: +// DIV64 Divide by 64 +// DIV16 Divide by 16 +// DIV4 Divide by 4 +// NOPRESCALING No prescaling +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 + +// Field: [4] SWOENA +// +// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If +// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of +// the timestamp counter. +// +// 0x0: Mode disabled. Timestamp counter uses system clock from the core and +// counts continuously. +// 0x1: Timestamp counter uses lineout (data related) clock from TPIU +// interface. The timestamp counter is held in reset while the output line is +// idle. +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 + +// Field: [3] DWTENA +// +// Enables the DWT stimulus (hardware event packet emission to the TPIU from +// the DWT) +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 + +// Field: [2] SYNCENA +// +// Enables synchronization packet transmission for a synchronous TPIU. +// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization +// speed. +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 + +// Field: [1] TSENA +// +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when +// the timestamp counter overflows. Timestamps are emitted during idle times +// after a fixed number of two million cycles. This provides a time reference +// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps +// are triggered by activity on the internal trace bus only. In this case there +// is no regular timestamp output when the ITM is idle. +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 + +// Field: [0] ITMENA +// +// Enables ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LAR +// +//***************************************************************************** +// Field: [31:0] LOCK_ACCESS +// +// A privileged write of 0xC5ACCE55 enables more write access to Control +// Registers TER, TPR and TCR. An invalid write removes write access. +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LSR +// +//***************************************************************************** +// Field: [2] BYTEACC +// +// Reads 0 which means 8-bit lock access is not be implemented. +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 + +// Field: [1] ACCESS +// +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 + +// Field: [0] PRESENT +// +// Indicates that a lock mechanism exists for this component. +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 + + +#endif // __CPU_ITM__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_rom_table.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_rom_table.h new file mode 100644 index 0000000000..dc3a4e6857 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_rom_table.h @@ -0,0 +1,220 @@ +/****************************************************************************** +* Filename: hw_cpu_rom_table_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ROM_TABLE_H__ +#define __HW_CPU_ROM_TABLE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ROM_TABLE component +// +//***************************************************************************** +// System Control Space Component +#define CPU_ROM_TABLE_O_SCS 0x00000000 + +// Data Watchpoint and Trace Component +#define CPU_ROM_TABLE_O_DWT 0x00000004 + +// Flash Patch and Breakpoint Component +#define CPU_ROM_TABLE_O_FPB 0x00000008 + +// Instrumentation Trace Component +#define CPU_ROM_TABLE_O_ITM 0x0000000C + +// Trace Port Interface Component +#define CPU_ROM_TABLE_O_TPIU 0x00000010 + +// Enhanced Trace Component +#define CPU_ROM_TABLE_O_ETM 0x00000014 + +// End Marker +#define CPU_ROM_TABLE_O_END 0x00000018 + +// System Memory Map Access for DAP +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SCS +// +//***************************************************************************** +// Field: [31:0] SCS +// +// Points to the SCS at 0xE000E000. +// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_DWT +// +//***************************************************************************** +// Field: [31:1] DWT +// +// Points to the Data Watchpoint and Trace block at 0xE0001000. +// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 + +// Field: [0] DWT_PRESENT +// +// 0: DWT is not present +// 1: DWT is present. +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_FPB +// +//***************************************************************************** +// Field: [31:1] FPB +// +// Points to the Flash Patch and Breakpoint block at 0xE0002000. +// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 + +// Field: [0] FPB_PRESENT +// +// 0: FPB is not present +// 1: FPB is present. +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ITM +// +//***************************************************************************** +// Field: [31:1] ITM +// +// Points to the Instrumentation Trace block at 0xE0000000. +// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 + +// Field: [0] ITM_PRESENT +// +// 0: ITM is not present +// 1: ITM is present. +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_TPIU +// +//***************************************************************************** +// Field: [31:1] TPIU +// +// Points to the TPIU. TPIU is at 0xE0040000. +// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 + +// Field: [0] TPIU_PRESENT +// +// 0: TPIU is not present +// 1: TPIU is present. +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ETM +// +//***************************************************************************** +// Field: [31:1] ETM +// +// Points to the ETM. ETM is at 0xE0041000. +// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 + +// Field: [0] ETM_PRESENT +// +// 0: ETM is not present +// 1: ETM is present. +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_END +// +//***************************************************************************** +// Field: [31:0] END +// +// End of the ROM table +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS +// +//***************************************************************************** +// Field: [0] SYSTEM_ACCESS +// +// 1: The system memory map is accessible using the DAP +// 0: Only debug resources are accessible using the DAP +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 + + +#endif // __CPU_ROM_TABLE__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_scs.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_scs.h new file mode 100644 index 0000000000..723ce1a544 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_scs.h @@ -0,0 +1,3885 @@ +/****************************************************************************** +* Filename: hw_cpu_scs_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_SCS_H__ +#define __HW_CPU_SCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_SCS component +// +//***************************************************************************** +// Interrupt Control Type +#define CPU_SCS_O_ICTR 0x00000004 + +// Auxiliary Control +#define CPU_SCS_O_ACTLR 0x00000008 + +// SysTick Control and Status +#define CPU_SCS_O_STCSR 0x00000010 + +// SysTick Reload Value +#define CPU_SCS_O_STRVR 0x00000014 + +// SysTick Current Value +#define CPU_SCS_O_STCVR 0x00000018 + +// SysTick Calibration Value +#define CPU_SCS_O_STCR 0x0000001C + +// Irq 0 to 31 Set Enable +#define CPU_SCS_O_NVIC_ISER0 0x00000100 + +// Irq 32 to 63 Set Enable +#define CPU_SCS_O_NVIC_ISER1 0x00000104 + +// Irq 0 to 31 Clear Enable +#define CPU_SCS_O_NVIC_ICER0 0x00000180 + +// Irq 32 to 63 Clear Enable +#define CPU_SCS_O_NVIC_ICER1 0x00000184 + +// Irq 0 to 31 Set Pending +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 + +// Irq 32 to 63 Set Pending +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 + +// Irq 0 to 31 Clear Pending +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 + +// Irq 32 to 63 Clear Pending +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 + +// Irq 0 to 31 Active Bit +#define CPU_SCS_O_NVIC_IABR0 0x00000300 + +// Irq 32 to 63 Active Bit +#define CPU_SCS_O_NVIC_IABR1 0x00000304 + +// Irq 0 to 3 Priority +#define CPU_SCS_O_NVIC_IPR0 0x00000400 + +// Irq 4 to 7 Priority +#define CPU_SCS_O_NVIC_IPR1 0x00000404 + +// Irq 8 to 11 Priority +#define CPU_SCS_O_NVIC_IPR2 0x00000408 + +// Irq 12 to 15 Priority +#define CPU_SCS_O_NVIC_IPR3 0x0000040C + +// Irq 16 to 19 Priority +#define CPU_SCS_O_NVIC_IPR4 0x00000410 + +// Irq 20 to 23 Priority +#define CPU_SCS_O_NVIC_IPR5 0x00000414 + +// Irq 24 to 27 Priority +#define CPU_SCS_O_NVIC_IPR6 0x00000418 + +// Irq 28 to 31 Priority +#define CPU_SCS_O_NVIC_IPR7 0x0000041C + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR8 0x00000420 + +// CPUID Base +#define CPU_SCS_O_CPUID 0x00000D00 + +// Interrupt Control State +#define CPU_SCS_O_ICSR 0x00000D04 + +// Vector Table Offset +#define CPU_SCS_O_VTOR 0x00000D08 + +// Application Interrupt/Reset Control +#define CPU_SCS_O_AIRCR 0x00000D0C + +// System Control +#define CPU_SCS_O_SCR 0x00000D10 + +// Configuration Control +#define CPU_SCS_O_CCR 0x00000D14 + +// System Handlers 4-7 Priority +#define CPU_SCS_O_SHPR1 0x00000D18 + +// System Handlers 8-11 Priority +#define CPU_SCS_O_SHPR2 0x00000D1C + +// System Handlers 12-15 Priority +#define CPU_SCS_O_SHPR3 0x00000D20 + +// System Handler Control and State +#define CPU_SCS_O_SHCSR 0x00000D24 + +// Configurable Fault Status +#define CPU_SCS_O_CFSR 0x00000D28 + +// Hard Fault Status +#define CPU_SCS_O_HFSR 0x00000D2C + +// Debug Fault Status +#define CPU_SCS_O_DFSR 0x00000D30 + +// Mem Manage Fault Address +#define CPU_SCS_O_MMFAR 0x00000D34 + +// Bus Fault Address +#define CPU_SCS_O_BFAR 0x00000D38 + +// Auxiliary Fault Status +#define CPU_SCS_O_AFSR 0x00000D3C + +// Processor Feature 0 +#define CPU_SCS_O_ID_PFR0 0x00000D40 + +// Processor Feature 1 +#define CPU_SCS_O_ID_PFR1 0x00000D44 + +// Debug Feature 0 +#define CPU_SCS_O_ID_DFR0 0x00000D48 + +// Auxiliary Feature 0 +#define CPU_SCS_O_ID_AFR0 0x00000D4C + +// Memory Model Feature 0 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 + +// Memory Model Feature 1 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 + +// Memory Model Feature 2 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 + +// Memory Model Feature 3 +#define CPU_SCS_O_ID_MMFR3 0x00000D5C + +// ISA Feature 0 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 + +// ISA Feature 1 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 + +// ISA Feature 2 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 + +// ISA Feature 3 +#define CPU_SCS_O_ID_ISAR3 0x00000D6C + +// ISA Feature 4 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 + +// Coprocessor Access Control +#define CPU_SCS_O_CPACR 0x00000D88 + +// Debug Halting Control and Status +#define CPU_SCS_O_DHCSR 0x00000DF0 + +// Deubg Core Register Selector +#define CPU_SCS_O_DCRSR 0x00000DF4 + +// Debug Core Register Data +#define CPU_SCS_O_DCRDR 0x00000DF8 + +// Debug Exception and Monitor Control +#define CPU_SCS_O_DEMCR 0x00000DFC + +// Software Trigger Interrupt +#define CPU_SCS_O_STIR 0x00000F00 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICTR +// +//***************************************************************************** +// Field: [2:0] INTLINESNUM +// +// Total number of interrupt lines in groups of 32. +// +// 0: 0...32 +// 1: 33...64 +// 2: 65...96 +// 3: 97...128 +// 4: 129...160 +// 5: 161...192 +// 6: 193...224 +// 7: 225...256 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ACTLR +// +//***************************************************************************** +// Field: [2] DISFOLD +// +// Disables folding of IT instruction. +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 + +// Field: [1] DISDEFWBUF +// +// Disables write buffer use during default memory map accesses. This causes +// all bus faults to be precise bus faults but decreases the performance of the +// processor because the stores to memory have to complete before the next +// instruction can be executed. +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 + +// Field: [0] DISMCYCINT +// +// Disables interruption of multi-cycle instructions. This increases the +// interrupt latency of the processor becuase LDM/STM completes before +// interrupt stacking occurs. +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application of any part of the SysTick Control and Status Register. +// If read by the debugger using the DAP, this bit is cleared on read-only if +// the MasterType bit in the **AHB-AP** Control Register is set to 0. +// Otherwise, COUNTFLAG is not changed by the debugger read. +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 + +// Field: [2] CLKSOURCE +// +// Clock source: +// +// 0: External reference clock. +// 1: Core clock +// +// External clock is not available in this device. Writes to this field will be +// ignored. +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 + +// Field: [1] TICKINT +// +// 0: Counting down to zero does not pend the SysTick handler. Software can use +// COUNTFLAG to determine if the SysTick handler has ever counted to zero. +// 1: Counting down to zero pends the SysTick handler. +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 + +// Field: [0] ENABLE +// +// Enable SysTick counter +// +// 0: Counter disabled +// 1: Counter operates in a multi-shot way. That is, counter loads with the +// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it +// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on +// TICKINT. It then loads STRVR.RELOAD again, and begins counting. +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STRVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register STCVR.CURRENT when the +// counter reaches 0. +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Current value at the time the register is accessed. No read-modify-write +// protection is provided, so change with care. Writing to it with any value +// clears the register to 0. Clearing this register also clears +// STCSR.COUNTFLAG. +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCR +// +//***************************************************************************** +// Field: [31] NOREF +// +// Reads as one. Indicates that no separate reference clock is provided. +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 + +// Field: [30] SKEW +// +// Reads as one. The calibration value is not exactly 10ms because of clock +// frequency. This could affect its suitability as a software real time clock. +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. The value read is valid only when core clock is at +// 48MHz. +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER0 +// +//***************************************************************************** +// Field: [31] SETENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 + +// Field: [30] SETENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 + +// Field: [29] SETENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 + +// Field: [28] SETENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 + +// Field: [27] SETENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 + +// Field: [26] SETENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 + +// Field: [25] SETENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 + +// Field: [24] SETENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 + +// Field: [23] SETENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 + +// Field: [22] SETENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 + +// Field: [21] SETENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 + +// Field: [20] SETENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 + +// Field: [19] SETENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 + +// Field: [18] SETENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 + +// Field: [17] SETENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 + +// Field: [16] SETENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 + +// Field: [15] SETENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 + +// Field: [14] SETENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 + +// Field: [13] SETENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 + +// Field: [12] SETENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 + +// Field: [11] SETENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 + +// Field: [10] SETENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 + +// Field: [9] SETENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 + +// Field: [8] SETENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 + +// Field: [7] SETENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 + +// Field: [6] SETENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 + +// Field: [5] SETENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 + +// Field: [4] SETENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 + +// Field: [3] SETENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 + +// Field: [2] SETENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 + +// Field: [1] SETENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 + +// Field: [0] SETENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER1 +// +//***************************************************************************** +// Field: [1] SETENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 + +// Field: [0] SETENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER0 +// +//***************************************************************************** +// Field: [31] CLRENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 + +// Field: [30] CLRENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 + +// Field: [29] CLRENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 + +// Field: [28] CLRENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 + +// Field: [27] CLRENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 + +// Field: [26] CLRENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 + +// Field: [25] CLRENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 + +// Field: [24] CLRENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 + +// Field: [23] CLRENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 + +// Field: [22] CLRENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 + +// Field: [21] CLRENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 + +// Field: [20] CLRENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 + +// Field: [19] CLRENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 + +// Field: [18] CLRENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 + +// Field: [17] CLRENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 + +// Field: [16] CLRENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 + +// Field: [15] CLRENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 + +// Field: [14] CLRENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 + +// Field: [13] CLRENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 + +// Field: [12] CLRENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 + +// Field: [11] CLRENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 + +// Field: [10] CLRENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 + +// Field: [9] CLRENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 + +// Field: [8] CLRENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 + +// Field: [7] CLRENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 + +// Field: [6] CLRENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 + +// Field: [5] CLRENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 + +// Field: [4] CLRENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 + +// Field: [3] CLRENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 + +// Field: [2] CLRENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 + +// Field: [1] CLRENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 + +// Field: [0] CLRENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER1 +// +//***************************************************************************** +// Field: [1] CLRENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 + +// Field: [0] CLRENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR0 +// +//***************************************************************************** +// Field: [31] SETPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 + +// Field: [30] SETPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 + +// Field: [29] SETPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 + +// Field: [28] SETPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 + +// Field: [27] SETPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 + +// Field: [26] SETPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 + +// Field: [25] SETPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 + +// Field: [24] SETPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 + +// Field: [23] SETPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 + +// Field: [22] SETPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 + +// Field: [21] SETPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 + +// Field: [20] SETPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 + +// Field: [19] SETPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 + +// Field: [18] SETPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 + +// Field: [17] SETPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 + +// Field: [16] SETPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 + +// Field: [15] SETPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 + +// Field: [14] SETPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 + +// Field: [13] SETPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 + +// Field: [12] SETPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 + +// Field: [11] SETPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 + +// Field: [10] SETPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 + +// Field: [9] SETPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 + +// Field: [8] SETPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 + +// Field: [7] SETPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 + +// Field: [6] SETPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 + +// Field: [5] SETPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 + +// Field: [4] SETPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 + +// Field: [3] SETPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 + +// Field: [2] SETPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 + +// Field: [1] SETPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 + +// Field: [0] SETPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR1 +// +//***************************************************************************** +// Field: [1] SETPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 + +// Field: [0] SETPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR0 +// +//***************************************************************************** +// Field: [31] CLRPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 + +// Field: [30] CLRPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 + +// Field: [29] CLRPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 + +// Field: [28] CLRPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 + +// Field: [27] CLRPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 + +// Field: [26] CLRPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 + +// Field: [25] CLRPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 + +// Field: [24] CLRPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 + +// Field: [23] CLRPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 + +// Field: [22] CLRPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 + +// Field: [21] CLRPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 + +// Field: [20] CLRPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 + +// Field: [19] CLRPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 + +// Field: [18] CLRPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 + +// Field: [17] CLRPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 + +// Field: [16] CLRPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 + +// Field: [15] CLRPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 + +// Field: [14] CLRPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 + +// Field: [13] CLRPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 + +// Field: [12] CLRPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 + +// Field: [11] CLRPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 + +// Field: [10] CLRPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 + +// Field: [9] CLRPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 + +// Field: [8] CLRPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 + +// Field: [7] CLRPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 + +// Field: [6] CLRPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 + +// Field: [5] CLRPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 + +// Field: [4] CLRPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 + +// Field: [3] CLRPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 + +// Field: [2] CLRPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 + +// Field: [1] CLRPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 + +// Field: [0] CLRPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR1 +// +//***************************************************************************** +// Field: [1] CLRPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 + +// Field: [0] CLRPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR0 +// +//***************************************************************************** +// Field: [31] ACTIVE31 +// +// Reading 0 from this bit implies that interrupt line 31 is not active. +// Reading 1 from this bit implies that the interrupt line 31 is active (See +// EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 + +// Field: [30] ACTIVE30 +// +// Reading 0 from this bit implies that interrupt line 30 is not active. +// Reading 1 from this bit implies that the interrupt line 30 is active (See +// EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 + +// Field: [29] ACTIVE29 +// +// Reading 0 from this bit implies that interrupt line 29 is not active. +// Reading 1 from this bit implies that the interrupt line 29 is active (See +// EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 + +// Field: [28] ACTIVE28 +// +// Reading 0 from this bit implies that interrupt line 28 is not active. +// Reading 1 from this bit implies that the interrupt line 28 is active (See +// EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 + +// Field: [27] ACTIVE27 +// +// Reading 0 from this bit implies that interrupt line 27 is not active. +// Reading 1 from this bit implies that the interrupt line 27 is active (See +// EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 + +// Field: [26] ACTIVE26 +// +// Reading 0 from this bit implies that interrupt line 26 is not active. +// Reading 1 from this bit implies that the interrupt line 26 is active (See +// EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 + +// Field: [25] ACTIVE25 +// +// Reading 0 from this bit implies that interrupt line 25 is not active. +// Reading 1 from this bit implies that the interrupt line 25 is active (See +// EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 + +// Field: [24] ACTIVE24 +// +// Reading 0 from this bit implies that interrupt line 24 is not active. +// Reading 1 from this bit implies that the interrupt line 24 is active (See +// EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 + +// Field: [23] ACTIVE23 +// +// Reading 0 from this bit implies that interrupt line 23 is not active. +// Reading 1 from this bit implies that the interrupt line 23 is active (See +// EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 + +// Field: [22] ACTIVE22 +// +// Reading 0 from this bit implies that interrupt line 22 is not active. +// Reading 1 from this bit implies that the interrupt line 22 is active (See +// EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 + +// Field: [21] ACTIVE21 +// +// Reading 0 from this bit implies that interrupt line 21 is not active. +// Reading 1 from this bit implies that the interrupt line 21 is active (See +// EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 + +// Field: [20] ACTIVE20 +// +// Reading 0 from this bit implies that interrupt line 20 is not active. +// Reading 1 from this bit implies that the interrupt line 20 is active (See +// EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 + +// Field: [19] ACTIVE19 +// +// Reading 0 from this bit implies that interrupt line 19 is not active. +// Reading 1 from this bit implies that the interrupt line 19 is active (See +// EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 + +// Field: [18] ACTIVE18 +// +// Reading 0 from this bit implies that interrupt line 18 is not active. +// Reading 1 from this bit implies that the interrupt line 18 is active (See +// EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 + +// Field: [17] ACTIVE17 +// +// Reading 0 from this bit implies that interrupt line 17 is not active. +// Reading 1 from this bit implies that the interrupt line 17 is active (See +// EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 + +// Field: [16] ACTIVE16 +// +// Reading 0 from this bit implies that interrupt line 16 is not active. +// Reading 1 from this bit implies that the interrupt line 16 is active (See +// EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 + +// Field: [15] ACTIVE15 +// +// Reading 0 from this bit implies that interrupt line 15 is not active. +// Reading 1 from this bit implies that the interrupt line 15 is active (See +// EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 + +// Field: [14] ACTIVE14 +// +// Reading 0 from this bit implies that interrupt line 14 is not active. +// Reading 1 from this bit implies that the interrupt line 14 is active (See +// EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 + +// Field: [13] ACTIVE13 +// +// Reading 0 from this bit implies that interrupt line 13 is not active. +// Reading 1 from this bit implies that the interrupt line 13 is active (See +// EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 + +// Field: [12] ACTIVE12 +// +// Reading 0 from this bit implies that interrupt line 12 is not active. +// Reading 1 from this bit implies that the interrupt line 12 is active (See +// EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 + +// Field: [11] ACTIVE11 +// +// Reading 0 from this bit implies that interrupt line 11 is not active. +// Reading 1 from this bit implies that the interrupt line 11 is active (See +// EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 + +// Field: [10] ACTIVE10 +// +// Reading 0 from this bit implies that interrupt line 10 is not active. +// Reading 1 from this bit implies that the interrupt line 10 is active (See +// EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 + +// Field: [9] ACTIVE9 +// +// Reading 0 from this bit implies that interrupt line 9 is not active. Reading +// 1 from this bit implies that the interrupt line 9 is active (See +// EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 + +// Field: [8] ACTIVE8 +// +// Reading 0 from this bit implies that interrupt line 8 is not active. Reading +// 1 from this bit implies that the interrupt line 8 is active (See +// EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 + +// Field: [7] ACTIVE7 +// +// Reading 0 from this bit implies that interrupt line 7 is not active. Reading +// 1 from this bit implies that the interrupt line 7 is active (See +// EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 + +// Field: [6] ACTIVE6 +// +// Reading 0 from this bit implies that interrupt line 6 is not active. Reading +// 1 from this bit implies that the interrupt line 6 is active (See +// EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 + +// Field: [5] ACTIVE5 +// +// Reading 0 from this bit implies that interrupt line 5 is not active. Reading +// 1 from this bit implies that the interrupt line 5 is active (See +// EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 + +// Field: [4] ACTIVE4 +// +// Reading 0 from this bit implies that interrupt line 4 is not active. Reading +// 1 from this bit implies that the interrupt line 4 is active (See +// EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 + +// Field: [3] ACTIVE3 +// +// Reading 0 from this bit implies that interrupt line 3 is not active. Reading +// 1 from this bit implies that the interrupt line 3 is active (See +// EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 + +// Field: [2] ACTIVE2 +// +// Reading 0 from this bit implies that interrupt line 2 is not active. Reading +// 1 from this bit implies that the interrupt line 2 is active (See +// EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 + +// Field: [1] ACTIVE1 +// +// Reading 0 from this bit implies that interrupt line 1 is not active. Reading +// 1 from this bit implies that the interrupt line 1 is active (See +// EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 + +// Field: [0] ACTIVE0 +// +// Reading 0 from this bit implies that interrupt line 0 is not active. Reading +// 1 from this bit implies that the interrupt line 0 is active (See +// EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR1 +// +//***************************************************************************** +// Field: [1] ACTIVE33 +// +// Reading 0 from this bit implies that interrupt line 33 is not active. +// Reading 1 from this bit implies that the interrupt line 33 is active (See +// EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 + +// Field: [0] ACTIVE32 +// +// Reading 0 from this bit implies that interrupt line 32 is not active. +// Reading 1 from this bit implies that the interrupt line 32 is active (See +// EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR0 +// +//***************************************************************************** +// Field: [31:24] PRI_3 +// +// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 + +// Field: [23:16] PRI_2 +// +// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 + +// Field: [15:8] PRI_1 +// +// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 + +// Field: [7:0] PRI_0 +// +// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR1 +// +//***************************************************************************** +// Field: [31:24] PRI_7 +// +// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 + +// Field: [23:16] PRI_6 +// +// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 + +// Field: [23:16] PRI_10 +// +// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 + +// Field: [15:8] PRI_9 +// +// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 + +// Field: [7:0] PRI_8 +// +// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 + +// Field: [15:8] PRI_13 +// +// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 + +// Field: [7:0] PRI_12 +// +// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR4 +// +//***************************************************************************** +// Field: [31:24] PRI_19 +// +// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 + +// Field: [23:16] PRI_18 +// +// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 + +// Field: [15:8] PRI_17 +// +// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 + +// Field: [7:0] PRI_16 +// +// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR5 +// +//***************************************************************************** +// Field: [31:24] PRI_23 +// +// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 + +// Field: [23:16] PRI_22 +// +// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 + +// Field: [15:8] PRI_21 +// +// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 + +// Field: [7:0] PRI_20 +// +// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR6 +// +//***************************************************************************** +// Field: [31:24] PRI_27 +// +// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 + +// Field: [23:16] PRI_26 +// +// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 + +// Field: [15:8] PRI_25 +// +// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 + +// Field: [7:0] PRI_24 +// +// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR7 +// +//***************************************************************************** +// Field: [31:24] PRI_31 +// +// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 + +// Field: [23:16] PRI_30 +// +// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 + +// Field: [15:8] PRI_29 +// +// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 + +// Field: [7:0] PRI_28 +// +// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR8 +// +//***************************************************************************** +// Field: [15:8] PRI_33 +// +// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 + +// Field: [7:0] PRI_32 +// +// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code. +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 + +// Field: [23:20] VARIANT +// +// Implementation defined variant number. +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 + +// Field: [19:16] CONSTANT +// +// Reads as 0xF +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 + +// Field: [15:4] PARTNO +// +// Number of processor within family. +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 + +// Field: [3:0] REVISION +// +// Implementation defined revision number. +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Set pending NMI bit. Setting this bit pends and activates an NMI. Because +// NMI is the highest-priority interrupt, it takes effect as soon as it +// registers. +// +// 0: No action +// 1: Set pending NMI +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 + +// Field: [28] PENDSVSET +// +// Set pending pendSV bit. +// +// 0: No action +// 1: Set pending PendSV +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 + +// Field: [27] PENDSVCLR +// +// Clear pending pendSV bit +// +// 0: No action +// 1: Clear pending pendSV +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. +// +// 0: No action +// 1: Set pending SysTick +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// +// 0: No action +// 1: Clear pending SysTick +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 + +// Field: [23] ISRPREEMPT +// +// This field can only be used at debug time. It indicates that a pending +// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, +// the interrupt is serviced. +// +// 0: A pending exception is not serviced. +// 1: A pending exception is serviced on exit from the debug halt state +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 + +// Field: [22] ISRPENDING +// +// Interrupt pending flag. Excludes NMI and faults. +// +// 0x0: Interrupt not pending +// 0x1: Interrupt pending +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 + +// Field: [17:12] VECTPENDING +// +// Pending ISR number field. This field contains the interrupt number of the +// highest priority pending ISR. +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 + +// Field: [11] RETTOBASE +// +// Indicates whether there are preempted active exceptions: +// +// 0: There are preempted active exceptions to execute +// 1: There are no active exceptions, or the currently-executing exception is +// the only active exception. +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 + +// Field: [8:0] VECTACTIVE +// +// Active ISR number field. Reset clears this field. +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_VTOR +// +//***************************************************************************** +// Field: [29:7] TBLOFF +// +// Bits 29 down to 7 of the vector table base offset. +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. +// Otherwise the write value is ignored. Read always returns 0xFA05. +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 + +// Field: [15] ENDIANESS +// +// Data endianness bit +// ENUMs: +// BIG Big endian +// LITTLE Little endian +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 + +// Field: [10:8] PRIGROUP +// +// Interrupt priority grouping field. This field is a binary point position +// indicator for creating subpriorities for exceptions that share the same +// pre-emption level. It divides the PRI_n field in the Interrupt Priority +// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption +// level and a subpriority level. The binary point is a left-of value. This +// means that the PRIGROUP value represents a point starting at the left of the +// Least Significant Bit (LSB). The lowest value might not be 0 depending on +// the number of bits allocated for priorities, and implementation choices. +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 + +// Field: [2] SYSRESETREQ +// +// Requests a warm reset. Setting this bit does not prevent Halting Debug from +// running. +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for active NMI, fault, and interrupts. +// It is the responsibility of the application to reinitialize the stack. This +// bit is for returning to a known state during debug. The bit self-clears. +// IPSR is not cleared by this operation. So, if used by an application, it +// must only be used at the base level of activation, or within a system +// handler whose active bit can be set. +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 + +// Field: [0] VECTRESET +// +// System Reset bit. Resets the system, with the exception of debug components. +// This bit is reserved for debug use and can be written to 1 only when the +// core is halted. The bit self-clears. Writing this bit to 1 while core is not +// halted may result in unpredictable behavior. +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// Send Event on Pending bit: +// +// 0: Only enabled interrupts or events can wakeup the processor, disabled +// interrupts are excluded +// 1: Enabled events and all interrupts, including disabled interrupts, can +// wakeup the processor. +// +// When an event or interrupt enters pending state, the event signal wakes up +// the processor from WFE. If +// the processor is not waiting for an event, the event is registered and +// affects the next WFE. +// The processor also wakes up on execution of an SEV instruction. +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 + +// Field: [2] SLEEPDEEP +// +// Controls whether the processor uses sleep or deep sleep as its low power +// mode +// ENUMs: +// DEEPSLEEP Deep sleep +// SLEEP Sleep +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// +// 0: Do not sleep when returning to thread mode +// 1: Sleep on ISR exit +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Stack alignment bit. +// +// 0: Only 4-byte alignment is guaranteed for the SP used prior to the +// exception on exception entry. +// 1: On exception entry, the SP used prior to the exception is adjusted to be +// 8-byte aligned and the context to restore it is saved. The SP is restored on +// the associated exception return. +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 + +// Field: [8] BFHFNMIGN +// +// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by +// load and store instructions. This applies to the HardFault, NMI, and +// FAULTMASK escalated handlers: +// +// 0: Data BusFaults caused by load and store instructions cause a lock-up +// 1: Data BusFaults caused by load and store instructions are ignored. +// +// Set this bit to 1 only when the handler and its data are in absolutely safe +// memory. The normal use +// of this bit is to probe system devices and bridges to detect problems. +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 + +// Field: [4] DIV_0_TRP +// +// Enables faulting or halting when the processor executes an SDIV or UDIV +// instruction with a divisor of 0: +// +// 0: Do not trap divide by 0. In this mode, a divide by zero returns a +// quotient of 0. +// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is +// CFSR.DIVBYZERO. +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 + +// Field: [3] UNALIGN_TRP +// +// Enables unaligned access traps: +// +// 0: Do not trap unaligned halfword and word accesses +// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault +// Status Register bit is CFSR.UNALIGNED. +// +// If this bit is set to 1, an unaligned access generates a UsageFault. +// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of +// the value in UNALIGN_TRP. +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 + +// Field: [1] USERSETMPEND +// +// Enables unprivileged software access to STIR: +// +// 0: User code is not allowed to write to the Software Trigger Interrupt +// register (STIR). +// 1: User code can write the Software Trigger Interrupt register (STIR) to +// trigger (pend) a Main exception, which is associated with the Main stack +// pointer. +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 + +// Field: [0] NONBASETHREDENA +// +// Indicates how the processor enters Thread mode: +// +// 0: Processor can enter Thread mode only when no exception is active. +// 1: Processor can enter Thread mode from any level using the appropriate +// return value (EXC_RETURN). +// +// Exception returns occur when one of the following instructions loads a value +// of 0xFXXXXXXX into the PC while in Handler mode: +// - POP/LDM which includes loading the PC. +// - LDR with PC as a destination. +// - BX with any register. +// The value written to the PC is intercepted and is referred to as the +// EXC_RETURN value. +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR1 +// +//***************************************************************************** +// Field: [23:16] PRI_6 +// +// Priority of system handler 6. UsageFault +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of system handler 5: BusFault +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of system handler 4: MemManage +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of system handler 11. SVCall +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of system handler 15. SysTick exception +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of system handler 14. Pend SV +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 + +// Field: [7:0] PRI_12 +// +// Priority of system handler 12. Debug Monitor +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHCSR +// +//***************************************************************************** +// Field: [18] USGFAULTENA +// +// Usage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 + +// Field: [17] BUSFAULTENA +// +// Bus fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 + +// Field: [16] MEMFAULTENA +// +// MemManage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 + +// Field: [15] SVCALLPENDED +// +// SVCall pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 + +// Field: [14] BUSFAULTPENDED +// +// BusFault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [13] MEMFAULTPENDED +// +// MemManage exception pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [12] USGFAULTPENDED +// +// Usage fault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [11] SYSTICKACT +// +// SysTick active flag. +// +// 0x0: Not active +// 0x1: Active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 + +// Field: [10] PENDSVACT +// +// PendSV active +// +// 0x0: Not active +// 0x1: Active +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 + +// Field: [8] MONITORACT +// +// Debug monitor active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 + +// Field: [7] SVCALLACT +// +// SVCall active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 + +// Field: [3] USGFAULTACT +// +// UsageFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 + +// Field: [1] BUSFAULTACT +// +// BusFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 + +// Field: [0] MEMFAULTACT +// +// MemManage exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CFSR +// +//***************************************************************************** +// Field: [25] DIVBYZERO +// +// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is +// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this +// fault occurs The instruction is executed and the return PC points to it. If +// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 + +// Field: [24] UNALIGNED +// +// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an +// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD +// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 + +// Field: [19] NOCP +// +// Attempt to use a coprocessor instruction. The processor does not support +// coprocessor instructions. +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 + +// Field: [18] INVPC +// +// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid +// context, invalid value. The return PC points to the instruction that tried +// to set the PC. +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 + +// Field: [17] INVSTATE +// +// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX +// type instruction has changed state). This includes state change after entry +// to or return from exception, as well as from inter-working instructions. +// Return PC points to faulting instruction, with the invalid state. +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 + +// Field: [16] UNDEFINSTR +// +// This bit is set when the processor attempts to execute an undefined +// instruction. This is an instruction that the processor cannot decode. The +// return PC points to the undefined instruction. +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 + +// Field: [15] BFARVALID +// +// This bit is set if the Bus Fault Address Register (BFAR) contains a valid +// address. This is true after a bus fault where the address is known. Other +// faults can clear this bit, such as a Mem Manage fault occurring later. If a +// Bus fault occurs that is escalated to a Hard Fault because of priority, the +// Hard Fault handler must clear this bit. This prevents problems if returning +// to a stacked active Bus fault handler whose BFAR value has been overwritten. +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 + +// Field: [12] STKERR +// +// Stacking from exception has caused one or more bus faults. The SP is still +// adjusted and the values in the context area on the stack might be incorrect. +// BFAR is not written. +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 + +// Field: [11] UNSTKERR +// +// Unstack from exception return has caused one or more bus faults. This is +// chained to the handler, so that the original return stack is still present. +// SP is not adjusted from failing return and new save is not performed. BFAR +// is not written. +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 + +// Field: [10] IMPRECISERR +// +// Imprecise data bus error. It is a BusFault, but the Return PC is not related +// to the causing instruction. This is not a synchronous fault. So, if detected +// when the priority of the current activation is higher than the Bus Fault, it +// only pends. Bus fault activates when returning to a lower priority +// activation. If a precise fault occurs before returning to a lower priority +// exception, the handler detects both IMPRECISERR set and one of the precise +// fault status bits set at the same time. BFAR is not written. +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 + +// Field: [9] PRECISERR +// +// Precise data bus error return. +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 + +// Field: [8] IBUSERR +// +// Instruction bus error flag. This flag is set by a prefetch error. The fault +// stops on the instruction, so if the error occurs under a branch shadow, no +// fault occurs. BFAR is not written. +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 + +// Field: [7] MMARVALID +// +// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving +// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage +// fault occurs that is escalated to a Hard Fault because of priority, the Hard +// Fault handler must clear this bit. This prevents problems on return to a +// stacked active MemManage handler whose MMFAR value has been overwritten. +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 + +// Field: [4] MSTKERR +// +// Stacking from exception has caused one or more access violations. The SP is +// still adjusted and the values in the context area on the stack might be +// incorrect. MMFAR is not written. +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 + +// Field: [3] MUNSTKERR +// +// Unstack from exception return has caused one or more access violations. This +// is chained to the handler, so that the original return stack is still +// present. SP is not adjusted from failing return and new save is not +// performed. MMFAR is not written. +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 + +// Field: [1] DACCVIOL +// +// Data access violation flag. Attempting to load or store at a location that +// does not permit the operation sets this flag. The return PC points to the +// faulting instruction. This error loads MMFAR with the address of the +// attempted access. +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 + +// Field: [0] IACCVIOL +// +// Instruction access violation flag. Attempting to fetch an instruction from a +// location that does not permit execution sets this flag. This occurs on any +// access to an XN region, even when the MPU is disabled or not present. The +// return PC points to the faulting instruction. MMFAR is not written. +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_HFSR +// +//***************************************************************************** +// Field: [31] DEBUGEVT +// +// This bit is set if there is a fault related to debug. This is only possible +// when halting debug is not enabled. For monitor enabled debug, it only +// happens for BKPT when the current priority is higher than the monitor. When +// both halting and monitor debug are disabled, it only happens for debug +// events that are not ignored (minimally, BKPT). The Debug Fault Status +// Register is updated. +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 + +// Field: [30] FORCED +// +// Hard Fault activated because a Configurable Fault was received and cannot +// activate because of priority or because the Configurable Fault is disabled. +// The Hard Fault handler then has to read the other fault status registers to +// determine cause. +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 + +// Field: [1] VECTTBL +// +// This bit is set if there is a fault because of vector table read on +// exception processing (Bus Fault). This case is always a Hard Fault. The +// return PC points to the pre-empted instruction. +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag. The processor stops on next instruction +// boundary. +// +// 0x0: External debug request signal not asserted +// 0x1: External debug request signal asserted +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 + +// Field: [3] VCATCH +// +// Vector catch flag. When this flag is set, a flag in one of the local fault +// status registers is also set to indicate the type of fault. +// +// 0x0: No vector catch occurred +// 0x1: Vector catch occurred +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 + +// Field: [2] DWTTRAP +// +// Data Watchpoint and Trace (DWT) flag. The processor stops at the current +// instruction or at the next instruction. +// +// 0x0: No DWT match +// 0x1: DWT match +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 + +// Field: [1] BKPT +// +// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, +// and also by normal code. Return PC points to breakpoint containing +// instruction. +// +// 0x0: No BKPT instruction execution +// 0x1: BKPT instruction execution +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 + +// Field: [0] HALTED +// +// Halt request flag. The processor is halted on the next instruction. +// +// 0x0: No halt request +// 0x1: Halt requested by NVIC, including step +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MMFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Mem Manage fault address field. +// This field is the data address of a faulted load or store attempt. When an +// unaligned access faults, the address is the actual address that faulted. +// Because an access can be split into multiple parts, each aligned, this +// address can be any offset in the range of the requested size. Flags +// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination +// with CFSR.MMARVALIDindicate the cause of the fault. +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_BFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Bus fault address field. This field is the data address of a faulted load or +// store attempt. When an unaligned access faults, the address is the address +// requested by the instruction, even if that is not the address that faulted. +// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and +// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the +// fault. +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AFSR +// +//***************************************************************************** +// Field: [31:0] IMPDEF +// +// Implementation defined. The bits map directly onto the signal assignment to +// the auxiliary fault inputs. Tied to 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR0 +// +//***************************************************************************** +// Field: [7:4] STATE1 +// +// State1 (T-bit == 1) +// +// 0x0: N/A +// 0x1: N/A +// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit +// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit +// instructions can be added using the appropriate instruction attribute, but +// other 32-bit basic instructions cannot.) +// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 + +// Field: [3:0] STATE0 +// +// State0 (T-bit == 0) +// +// 0x0: No ARM encoding +// 0x1: N/A +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR1 +// +//***************************************************************************** +// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL +// +// Microcontroller programmer's model +// +// 0x0: Not supported +// 0x2: Two-stack support +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_DFR0 +// +//***************************************************************************** +// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL +// +// Microcontroller Debug Model - memory mapped +// +// 0x0: Not supported +// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_AFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR2 +// +//***************************************************************************** +// Field: [24] WAIT_FOR_INTERRUPT_STALLING +// +// wait for interrupt stalling +// +// 0x0: Not supported +// 0x1: Wait for interrupt supported +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_CPACR +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is being reset now (held in +// reset still). +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 + +// Field: [24] S_RETIRE_ST +// +// Indicates that an instruction has completed since last read. This is a +// sticky bit that clears on read. This determines if the core is stalled on a +// load/store or fetch. +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 + +// Field: [19] S_LOCKUP +// +// Reads as one if the core is running (not halted) and a lockup condition is +// present. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 + +// Field: [18] S_SLEEP +// +// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must +// use C_HALT to gain control or wait for interrupt to wake-up. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 + +// Field: [17] S_HALT +// +// The core is in debug state when this bit is set. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 + +// Field: [16] S_REGRDY +// +// Register Read/Write on the Debug Core Register Selector register is +// available. Last transfer is complete. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 + +// Field: [5] C_SNAPSTALL +// +// If the core is stalled on a load/store operation the stall ceases and the +// instruction is forced to complete. This enables Halting debug to gain +// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. +// The core reads S_RETIRE_ST as 0. This indicates that no instruction has +// advanced. This prevents misuse. The bus state is Unpredictable when this is +// used. S_RETIRE_ST can detect core stalls on load/store operations. +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 + +// Field: [3] C_MASKINTS +// +// Mask interrupts when stepping or running in halted debug. This masking does +// not affect NMI, fault exceptions and SVC caused by execution of the +// instructions. This bit must only be modified when the processor is halted +// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released +// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must +// be separate). Modifying C_MASKINTS while the system is running with halting +// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable +// behavior. +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 + +// Field: [2] C_STEP +// +// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. +// Must only be modified when the processor is halted (S_HALT == 1). +// Modifying C_STEP while the system is running with halting debug support +// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core Halts. For +// example Breakpoint. This bit clears on core reset. +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 + +// Field: [0] C_DEBUGEN +// +// Enables debug. This can only be written by AHB-AP and not by the core. It is +// ignored when written by the core, which cannot set or clear it. The core +// must write a 1 to it when writing C_HALT to halt itself. +// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when +// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will +// be unknown to software when C_DEBUGEN = 0. +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWNR +// +// 1: Write +// 0: Read +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 + +// Field: [4:0] REGSEL +// +// Register select +// +// 0x00: R0 +// 0x01: R1 +// 0x02: R2 +// 0x03: R3 +// 0x04: R4 +// 0x05: R5 +// 0x06: R6 +// 0x07: R7 +// 0x08: R8 +// 0x09: R9 +// 0x0A: R10 +// 0x0B: R11 +// 0x0C: R12 +// 0x0D: Current SP +// 0x0E: LR +// 0x0F: DebugReturnAddress +// 0x10: XPSR/flags, execution state information, and exception number +// 0x11: MSP (Main SP) +// 0x12: PSP (Process SP) +// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DCRDR +// +// This register holds data for reading and writing registers to and from the +// processor. This is the data value written to the register selected by DCRSR. +// When the processor receives a request from DCRSR, this register is read or +// written by the processor using a normal load-store unit operation. If core +// register transfers are not being performed, software-based debug monitors +// can use this register for communication in non-halting debug. This enables +// flags and bits to acknowledge state and indicate if commands have been +// accepted to, replied to, or accepted and replied to. +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DEMCR +// +//***************************************************************************** +// Field: [24] TRCENA +// +// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, +// ITM, ETM and TPIU. This enables control of power usage unless tracing is +// required. The application can enable this, for ITM use, or use by a +// debugger. +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 + +// Field: [19] MON_REQ +// +// This enables the monitor to identify how it wakes up. This bit clears on a +// Core Reset. +// +// 0x0: Woken up by debug exception. +// 0x1: Woken up by MON_PEND +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 + +// Field: [18] MON_STEP +// +// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. +// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped +// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, +// or BASEPRI. +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 + +// Field: [17] MON_PEND +// +// Pend the monitor to activate when priority permits. This can wake up the +// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for +// Monitor debug. This register does not reset on a system reset. It is only +// reset by a power-on reset. Software in the reset handler or later, or by the +// DAP must enable the debug monitor. +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 + +// Field: [16] MON_EN +// +// Enable the debug monitor. +// When enabled, the System handler priority register controls its priority +// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN +// overrides this bit. Vector catching is semi-synchronous. When a matching +// event is seen, a Halt is requested. Because the processor can only halt on +// an instruction boundary, it must wait until the next instruction boundary. +// As a result, it stops on the first instruction of the exception handler. +// However, two special cases exist when a vector catch has triggered: 1. If a +// fault is taken during vectoring, vector read or stack push error, the halt +// occurs on the corresponding fault handler, for the vector error or stack +// push. 2. If a late arriving interrupt comes in during vectoring, it is not +// taken. That is, an implementation that supports the late arrival +// optimization must suppress it in this case. +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 + +// Field: [10] VC_HARDERR +// +// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 + +// Field: [9] VC_INTERR +// +// Debug trap on a fault occurring during an exception entry or return +// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 + +// Field: [8] VC_BUSERR +// +// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 + +// Field: [7] VC_STATERR +// +// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 + +// Field: [6] VC_CHKERR +// +// Debug trap on Usage Fault enabled checking errors. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 + +// Field: [5] VC_NOCPERR +// +// Debug trap on a UsageFault access to a Coprocessor. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 + +// Field: [4] VC_MMERR +// +// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STIR +// +//***************************************************************************** +// Field: [8:0] INTID +// +// Interrupt ID field. Writing a value to this bit-field is the same as +// manually pending an interrupt by setting the corresponding interrupt bit in +// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 + + +#endif // __CPU_SCS__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_tiprop.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_tiprop.h new file mode 100644 index 0000000000..40d9c5c449 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_tiprop.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* Filename: hw_cpu_tiprop_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TIPROP_H__ +#define __HW_CPU_TIPROP_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TIPROP component +// +//***************************************************************************** +// Internal +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 + +// Internal +#define CPU_TIPROP_O_DYN_CG 0x00000FFC + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_TRACECLKMUX +// +//***************************************************************************** +// Field: [0] TRACECLK_N_SWV +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TRACECLK Internal. Only to be used through TI provided API. +// SWV Internal. Only to be used through TI provided API. +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_DYN_CG +// +//***************************************************************************** +// Field: [1:0] DYN_CG +// +// Internal. Only to be used through TI provided API. +#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 +#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 +#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 + + +#endif // __CPU_TIPROP__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_tpiu.h b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_tpiu.h new file mode 100644 index 0000000000..16b46cd186 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_cpu_tpiu.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: hw_cpu_tpiu_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TPIU_H__ +#define __HW_CPU_TPIU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TPIU component +// +//***************************************************************************** +// Supported Sync Port Sizes +#define CPU_TPIU_O_SSPSR 0x00000000 + +// Current Sync Port Size +#define CPU_TPIU_O_CSPSR 0x00000004 + +// Async Clock Prescaler +#define CPU_TPIU_O_ACPR 0x00000010 + +// Selected Pin Protocol +#define CPU_TPIU_O_SPPR 0x000000F0 + +// Formatter and Flush Status +#define CPU_TPIU_O_FFSR 0x00000300 + +// Formatter and Flush Control +#define CPU_TPIU_O_FFCR 0x00000304 + +// Formatter Synchronization Counter +#define CPU_TPIU_O_FSCR 0x00000308 + +// Claim Tag Mask +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 + +// Claim Tag Set +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 + +// Current Claim Tag +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 + +// Claim Tag Clear +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 + +// Device ID +#define CPU_TPIU_O_DEVID 0x00000FC8 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_ACPR +// +//***************************************************************************** +// Field: [12:0] PRESCALER +// +// Divisor for input trace clock is (PRESCALER + 1). +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SPPR +// +//***************************************************************************** +// Field: [1:0] PROTOCOL +// +// Trace output protocol +// ENUMs: +// SWO_NRZ SerialWire Output (NRZ) +// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset +// value. +// TRACEPORT TracePort mode +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFSR +// +//***************************************************************************** +// Field: [3] FTNONSTOP +// +// 0: Formatter can be stopped +// 1: Formatter cannot be stopped +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFCR +// +//***************************************************************************** +// Field: [8] TRIGIN +// +// Indicates that triggers are inserted when a trigger pin is asserted. +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 + +// Field: [1] ENFCONT +// +// Enable continuous formatting: +// +// 0: Continuous formatting disabled +// 1: Continuous formatting enabled +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FSCR +// +//***************************************************************************** +// Field: [31:0] FSCR +// +// The global synchronization trigger is generated by the Program Counter (PC) +// Sampler block. This means that there is no synchronization counter in the +// TPIU. +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMMASK +// +//***************************************************************************** +// Field: [31:0] CLAIMMASK +// +// This register forms one half of the Claim Tag value. When reading this +// register returns the number of bits that can be set (each bit is considered +// separately): +// +// 0: This claim tag bit is not implemented +// 1: This claim tag bit is not implemented +// +// The behavior when writing to this register is described in CLAIMSET. +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMSET +// +//***************************************************************************** +// Field: [31:0] CLAIMSET +// +// This register forms one half of the Claim Tag value. Writing to this +// location allows individual bits to be set (each bit is considered +// separately): +// +// 0: No effect +// 1: Set this bit in the claim tag +// +// The behavior when reading from this location is described in CLAIMMASK. +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMTAG +// +//***************************************************************************** +// Field: [31:0] CLAIMTAG +// +// This register forms one half of the Claim Tag value. Reading this register +// returns the current Claim Tag value. +// Reading CLAIMMASK determines how many bits from this register must be used. +// +// The behavior when writing to this register is described in CLAIMCLR. +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMCLR +// +//***************************************************************************** +// Field: [31:0] CLAIMCLR +// +// This register forms one half of the Claim Tag value. Writing to this +// location enables individual bits to be cleared (each bit is considered +// separately): +// +// 0: No effect +// 1: Clear this bit in the claim tag. +// +// The behavior when reading from this location is described in CLAIMTAG. +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_DEVID +// +//***************************************************************************** +// Field: [31:0] DEVID +// +// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no +// ETM present. +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 + + +#endif // __CPU_TPIU__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_crypto.h b/os/common/ext/TI/devices/cc13x0/inc/hw_crypto.h new file mode 100644 index 0000000000..3b076d67f4 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_crypto.h @@ -0,0 +1,1914 @@ +/****************************************************************************** +* Filename: hw_crypto_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CRYPTO_H__ +#define __HW_CRYPTO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CRYPTO component +// +//***************************************************************************** +// DMA Channel 0 Control +#define CRYPTO_O_DMACH0CTL 0x00000000 + +// DMA Channel 0 External Address +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 + +// DMA Channel 0 Length +#define CRYPTO_O_DMACH0LEN 0x0000000C + +// DMA Controller Status +#define CRYPTO_O_DMASTAT 0x00000018 + +// DMA Controller Software Reset +#define CRYPTO_O_DMASWRESET 0x0000001C + +// DMA Channel 1 Control +#define CRYPTO_O_DMACH1CTL 0x00000020 + +// DMA Channel 1 External Address +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 + +// DMA Channel 1 Length +#define CRYPTO_O_DMACH1LEN 0x0000002C + +// DMA Controller Master Configuration +#define CRYPTO_O_DMABUSCFG 0x00000078 + +// DMA Controller Port Error +#define CRYPTO_O_DMAPORTERR 0x0000007C + +// DMA Controller Version +#define CRYPTO_O_DMAHWVER 0x000000FC + +// Key Write Area +#define CRYPTO_O_KEYWRITEAREA 0x00000400 + +// Key Written Area Status +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 + +// Key Size +#define CRYPTO_O_KEYSIZE 0x00000408 + +// Key Read Area +#define CRYPTO_O_KEYREADAREA 0x0000040C + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY20 0x00000500 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY21 0x00000504 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY22 0x00000508 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY23 0x0000050C + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY30 0x00000510 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY31 0x00000514 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY32 0x00000518 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY33 0x0000051C + +// AES Initialization Vector +#define CRYPTO_O_AESIV0 0x00000540 + +// AES Initialization Vector +#define CRYPTO_O_AESIV1 0x00000544 + +// AES Initialization Vector +#define CRYPTO_O_AESIV2 0x00000548 + +// AES Initialization Vector +#define CRYPTO_O_AESIV3 0x0000054C + +// AES Input/Output Buffer Control +#define CRYPTO_O_AESCTL 0x00000550 + +// Crypto Data Length LSW +#define CRYPTO_O_AESDATALEN0 0x00000554 + +// Crypto Data Length MSW +#define CRYPTO_O_AESDATALEN1 0x00000558 + +// AES Authentication Length +#define CRYPTO_O_AESAUTHLEN 0x0000055C + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT0 0x00000560 + +// AES Data Input/Output 0 +#define CRYPTO_O_AESDATAIN0 0x00000560 + +// AES Data Input/Output 3 +#define CRYPTO_O_AESDATAOUT1 0x00000564 + +// AES Data Input/Output 1 +#define CRYPTO_O_AESDATAIN1 0x00000564 + +// AES Data Input/Output 2 +#define CRYPTO_O_AESDATAOUT2 0x00000568 + +// AES Data Input/Output 2 +#define CRYPTO_O_AESDATAIN2 0x00000568 + +// AES Data Input/Output 3 +#define CRYPTO_O_AESDATAOUT3 0x0000056C + +// Data Input/Output +#define CRYPTO_O_AESDATAIN3 0x0000056C + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT0 0x00000570 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT1 0x00000574 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT2 0x00000578 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT3 0x0000057C + +// Master Algorithm Select +#define CRYPTO_O_ALGSEL 0x00000700 + +// Master Protection Control +#define CRYPTO_O_DMAPROTCTL 0x00000704 + +// Software Reset +#define CRYPTO_O_SWRESET 0x00000740 + +// Control Interrupt Configuration +#define CRYPTO_O_IRQTYPE 0x00000780 + +// Interrupt Enable +#define CRYPTO_O_IRQEN 0x00000784 + +// Interrupt Clear +#define CRYPTO_O_IRQCLR 0x00000788 + +// Interrupt Set +#define CRYPTO_O_IRQSET 0x0000078C + +// Interrupt Status +#define CRYPTO_O_IRQSTAT 0x00000790 + +// CTRL Module Version +#define CRYPTO_O_HWVER 0x000007FC + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority: +// +// A channel with high priority will be served before a channel with low +// priority in cases with simultaneous access requests. If both channels have +// the same priority access of the channels to the external port is arbitrated +// using a Round Robin scheme. +// ENUMs: +// HIGH Priority high +// LOW Priority low +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 +#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 + +// Field: [0] EN +// +// DMA Channel 0 Control +// ENUMs: +// EN Channel enabled +// DIS Channel disabled +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 +#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// Holds the last updated external address after being sent to the master +// interface. +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0LEN +// +//***************************************************************************** +// Field: [15:0] LEN +// +// DMA transfer length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Writing a non-zero value to this register field starts the transfer if +// the channel is enabled by setting DMACH0CTL.EN. +#define CRYPTO_DMACH0LEN_LEN_W 16 +#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASTAT +// +//***************************************************************************** +// Field: [17] PORT_ERR +// +// Reflects possible transfer errors on the AHB port. +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 + +// Field: [1] CH1_ACTIVE +// +// This register field indicates if DMA channel 1 is active or not. +// 0: Not active +// 1: Active +#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 + +// Field: [0] CH0_ACTIVE +// +// This register field indicates if DMA channel 0 is active or not. +// 0: Not active +// 1: Active +#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Software reset enable +// +// 0: Disable +// 1: Enable (self-cleared to zero). +// +// Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE +// and DMASTAT.CH1_ACTIVE. +#define CRYPTO_DMASWRESET_RESET 0x00000001 +#define CRYPTO_DMASWRESET_RESET_BITN 0 +#define CRYPTO_DMASWRESET_RESET_M 0x00000001 +#define CRYPTO_DMASWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority: +// +// A channel with high priority will be served before a channel with low +// priority in cases with simultaneous access requests. If both channels have +// the same priority access of the channels to the external port is arbitrated +// using a Round Robin scheme. +// ENUMs: +// HIGH Priority high +// LOW Priority low +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 +#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 + +// Field: [0] EN +// +// Channel enable: +// +// Note: Disabling an active channel will interrupt the DMA operation. The +// ongoing block transfer will be completed, but no new transfers will be +// requested. +// ENUMs: +// EN Channel enabled +// DIS Channel disabled +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 +#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// Holds the last updated external address after being sent to the master +// interface. +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1LEN +// +//***************************************************************************** +// Field: [15:0] LEN +// +// DMA transfer length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Writing a non-zero value to this register field starts the transfer if +// the channel is enabled by setting DMACH1CTL.EN. +#define CRYPTO_DMACH1LEN_LEN_W 16 +#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMABUSCFG +// +//***************************************************************************** +// Field: [15:12] AHB_MST1_BURST_SIZE +// +// Maximum burst size that can be performed on the AHB bus +// ENUMs: +// 64_BYTE 64 bytes +// 32_BYTE 32 bytes +// 16_BYTE 16 bytes +// 8_BYTE 8 bytes +// 4_BYTE 4 bytes +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 + +// Field: [11] AHB_MST1_IDLE_EN +// +// Idle transfer insertion between consecutive burst transfers on AHB +// ENUMs: +// IDLE Idle transfer insertion enabled +// NO_IDLE Do not insert idle transfers. +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 + +// Field: [10] AHB_MST1_INCR_EN +// +// Burst length type of AHB transfer +// ENUMs: +// SPECIFIED Fixed length bursts or single transfers +// UNSPECIFIED Unspecified length burst transfers +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 + +// Field: [9] AHB_MST1_LOCK_EN +// +// Locked transform on AHB +// ENUMs: +// LOCKED Transfers are locked +// NOT_LOCKED Transfers are not locked +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 + +// Field: [8] AHB_MST1_BIGEND +// +// Endianess for the AHB master +// ENUMs: +// BIG_ENDIAN Big Endian +// LITTLE_ENDIAN Little Endian +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPORTERR +// +//***************************************************************************** +// Field: [12] AHB_ERR +// +// A 1 indicates that the Crypto peripheral has detected an AHB bus error +#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 +#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 + +// Field: [9] LAST_CH +// +// Indicates which channel was serviced last (channel 0 or channel 1) by the +// AHB master port. +#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 +#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_S 9 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAHWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level. +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// Bit-by-bit complement of the VER_NUM field bits. +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// Version number of the DMA Controller (209) +#define CRYPTO_DMAHWVER_VER_NUM_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF +#define CRYPTO_DMAHWVER_VER_NUM_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITEAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA7 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 + +// Field: [6] RAM_AREA6 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 + +// Field: [5] RAM_AREA5 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 + +// Field: [4] RAM_AREA4 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 + +// Field: [3] RAM_AREA3 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 + +// Field: [2] RAM_AREA2 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 + +// Field: [1] RAM_AREA1 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 + +// Field: [0] RAM_AREA0 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITTENAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA_WRITTEN7 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 + +// Field: [6] RAM_AREA_WRITTEN6 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 + +// Field: [5] RAM_AREA_WRITTEN5 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 + +// Field: [4] RAM_AREA_WRITTEN4 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 + +// Field: [3] RAM_AREA_WRITTEN3 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 + +// Field: [2] RAM_AREA_WRITTEN2 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 + +// Field: [1] RAM_AREA_WRITTEN1 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 + +// Field: [0] RAM_AREA_WRITTEN0 +// +// On read this bit returns the key area written status. +// +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYSIZE +// +//***************************************************************************** +// Field: [1:0] SIZE +// +// Key size +// +// When writing to this register, KEYWRITTENAREA will be reset. +// +// Note: For the Crypto peripheral this field is fixed to 128 bits. For +// software compatibility KEYWRITTENAREA will be reset when writing to this +// register. +// ENUMs: +// 256_BIT Not supported +// 192_BIT Not supported +// 128_BIT 128 bits +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYREADAREA +// +//***************************************************************************** +// Field: [31] BUSY +// +// Key store operation busy status flag (read only) +// +// 0: operation is completed. +// 1: operation is not completed and the key store is busy. +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 + +// Field: [3:0] RAM_AREA +// +// Selects the area of the key store RAM from where the key needs to be read +// that will be written to the AES engine. +// +// Only RAM areas that contain valid written keys can be selected. +// ENUMs: +// NO_RAM No RAM +// RAM_AREA7 RAM Area 7 +// RAM_AREA6 RAM Area 6 +// RAM_AREA5 RAM Area 5 +// RAM_AREA4 RAM Area 4 +// RAM_AREA3 RAM Area 3 +// RAM_AREA2 RAM Area 2 +// RAM_AREA1 RAM Area 1 +// RAM_AREA0 RAM Area 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY20 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY20_KEY2_W 32 +#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY21 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY21_KEY2_W 32 +#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY22 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY22_KEY2_W 32 +#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY23 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY23_KEY2_W 32 +#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY30 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY30_KEY3_W 32 +#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY31 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY31_KEY3_W 32 +#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY32 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY32_KEY3_W 32 +#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY33 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY33_KEY3_W 32 +#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV0 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV0_IV_W 32 +#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV1 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV1_IV_W 32 +#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV2 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV2_IV_W 32 +#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV3 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV3_IV_W 32 +#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESCTL +// +//***************************************************************************** +// Field: [31] CONTEXT_RDY +// +// If 1, this status bit indicates that the context data registers can be +// overwritten and the Host is permitted to write the next context. Writing a +// context means writing either a mode, the crypto length or +// AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers +#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 + +// Field: [30] SAVED_CONTEXT_RDY +// +// If read as 1, this status bit indicates that an AES authentication TAG +// and/or IV block(s) is/are available for the Host to retrieve. This bit is +// only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive +// with CONTEXT_RDY. +// +// Writing 1 clears the bit to zero, indicating the Crypto peripheral can start +// its next operation. This bit is also cleared when the 4th word of the output +// TAG and/or IV is read. +// +// Note: All other mode bit writes will be ignored when this mode bit is +// written with 1. +// +// Note: This bit is controlled automatically by the Crypto peripheral for TAG +// read DMA operations. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 + +// Field: [29] SAVE_CONTEXT +// +// IV must be read before the AES engine can start a new operation. +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 + +// Field: [24:22] CCM_M +// +// Defines M that indicates the length of the authentication field for CCM +// operations; the authentication field length equals two times the value of +// CCM_M plus one. +// Note: The Crypto peripheral always returns a 128-bit authentication field, +// of which the M least significant bytes are valid. All values are supported. +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 + +// Field: [21:19] CCM_L +// +// Defines L that indicates the width of the length field for CCM operations; +// the length field in bytes equals the value of CMM_L plus one. All values are +// supported. +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 + +// Field: [18] CCM +// +// AES-CCM mode enable. +// AES-CCM is a combined mode, using AES for both authentication and +// encryption. +// Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and +// AESDATALEN0.LEN_LSW after all other registers. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR; selecting other AES modes than CTR mode is invalid. +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 + +// Field: [15] CBC_MAC +// +// MAC mode enable. +// The DIR bit must be set to 1 for this mode. +// Selecting this mode requires writing the AESDATALEN1.LEN_MSW and +// AESDATALEN0.LEN_LSW registers after all other registers. +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 + +// Field: [8:7] CTR_WIDTH +// +// Specifies the counter width for AES-CTR mode +// ENUMs: +// 128_BIT 128 bits +// 96_BIT 96 bits +// 64_BIT 64 bits +// 32_BIT 32 bits +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 + +// Field: [6] CTR +// +// AES-CTR mode enable +// This bit must also be set for CCM, when encryption/decryption is required. +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 + +// Field: [5] CBC +// +// CBC mode enable +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 + +// Field: [4:3] KEY_SIZE +// +// This field specifies the key size. +// The key size is automatically configured when a new key is loaded via the +// key store module. +// 00 = N/A - reserved +// 01 = 128 bits +// 10 = N/A - reserved +// 11 = N/A - reserved +// For the Crypto peripheral this field is fixed to 128 bits. +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 + +// Field: [2] DIR +// +// Direction. +// 0 : Decrypt operation is performed. +// 1 : Encrypt operation is performed. +// +// This bit must be written with a 1 when CBC-MAC is selected. +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 + +// Field: [1] INPUT_RDY +// +// If read as 1, this status bit indicates that the 16-byte AES input buffer is +// empty. The Host is permitted to write the next block of data. +// +// Writing a 0 clears the bit to zero and indicates that the AES engine can use +// the provided input data block. +// +// Writing a 1 to this bit will be ignored. +// +// Note: For DMA operations, this bit is automatically controlled by the Crypto +// peripheral. +// After reset, this bit is 0. After writing a context (note 1), this bit will +// become 1. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 +#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_S 1 + +// Field: [0] OUTPUT_RDY +// +// If read as 1, this status bit indicates that an AES output block is +// available to be retrieved by the Host. +// +// Writing a 0 clears the bit to zero and indicates that output data is read by +// the Host. The AES engine can provide a next output data block. +// +// Writing a 1 to this bit will be ignored. +// +// Note: For DMA operations, this bit is automatically controlled by the Crypto +// peripheral. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN0 +// +//***************************************************************************** +// Field: [31:0] LEN_LSW +// +// Used to write the Length values to the Crypto peripheral. +// +// This register contains bits [31:0] of the combined data length. +#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 +#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN1 +// +//***************************************************************************** +// Field: [28:0] LEN_MSW +// +// Bits [60:32] of the combined data length. +// +// Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store +// the cryptographic data length in bytes for all modes. Once processing with +// this context is started, this length decrements to zero. Data lengths up to +// (2^61 - 1) bytes are allowed. +// For GCM, any value up to 2^36 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 - +// 2, resulting in a maximum number of bytes of 2^36 - 32. +// Writing to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN.LEN. +// All modes must have a length > 0. For the combined modes, it is allowed to +// have one of the lengths equal to zero. +// For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero +// to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the Crypto peripheral. For block cipher +// modes, the data length must be programmed in multiples of the block cipher +// size, 16 bytes. +#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 +#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESAUTHLEN +// +//***************************************************************************** +// Field: [31:0] LEN +// +// Authentication data length in bytes for combined mode, CCM only. +// Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once +// processing with this context is started, this length decrements to zero. +// Writing this register triggers the engine to start using this context for +// CCM. +#define CRYPTO_AESAUTHLEN_LEN_W 32 +#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[31:0] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN0_DATA_W 32 +#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[63:32] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[63:32] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN1_DATA_W 32 +#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[95:64] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[95:64] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN2_DATA_W 32 +#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[127:96] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[127:96] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN3_DATA_W 32 +#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT0 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT0_TAG_W 32 +#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT1 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT1_TAG_W 32 +#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT2 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT2_TAG_W 32 +#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT3 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT3_TAG_W 32 +#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_ALGSEL +// +//***************************************************************************** +// Field: [31] TAG +// +// If this bit is cleared to 0, the DMA operation involves only data. +// If this bit is set, the DMA operation includes a TAG (Authentication Result +// / Digest). +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 + +// Field: [1] AES +// +// If set to 1, the AES data is loaded via DMA +// Both Read and Write maximum transfer size to DMA engine is set to 16 bytes +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 + +// Field: [0] KEY_STORE +// +// If set to 1, selects the Key Store to be loaded via DMA. +// The maximum transfer size to DMA engine is set to 32 bytes (however +// transfers of 16, 24 and 32 bytes are allowed) +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPROTCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Select AHB transfer protection control for DMA transfers using the key store +// area as destination. +// 0 : transfers use 'USER' type access. +// 1 : transfers use 'PRIVILEGED' type access. +#define CRYPTO_DMAPROTCTL_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// If this bit is set to 1, the following modules are reset: +// - Master control internal state is reset. That includes interrupt, error +// status register and result available interrupt generation FSM. +// - Key store module state is reset. That includes clearing the Written Area +// flags; therefore the keys must be reloaded to the key store module. +// Writing 0 has no effect. +// The bit is self cleared after executing the reset. +#define CRYPTO_SWRESET_RESET 0x00000001 +#define CRYPTO_SWRESET_RESET_BITN 0 +#define CRYPTO_SWRESET_RESET_M 0x00000001 +#define CRYPTO_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQTYPE +// +//***************************************************************************** +// Field: [0] LEVEL +// +// If this bit is 0, the interrupt output is a pulse. +// If this bit is set to 1, the interrupt is a level interrupt that must be +// cleared by writing the interrupt clear register. +// This bit is applicable for both interrupt output signals. +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQEN +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQCLR +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSET +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. +// Writing 0 has no effect. +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. +// Writing 0 has no effect. +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSTAT +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// This bit is set when a DMA bus error is detected during a DMA operation. The +// value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR +// Note: This error is asserted if an error is detected on the AHB master +// interface during a DMA operation. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// This bit is set when a write error is detected during the DMA write +// operation to the key store memory. The value of this register is held until +// it is cleared via IRQCLR.KEY_ST_WR_ERR +// Note: This error is asserted if a DMA operation does not cover a full key +// area or more areas are written than expected. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// This bit will be set when a read error is detected during the read of a key +// from the key store, while copying it to the AES engine. The value of this +// register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. +// Note: This error is asserted if a key location is selected in the key store +// that is not available. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// This bit returns the status of DMA data in done interrupt. +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This bit is set high when the Crypto peripheral has a result available. +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level, starts at 0 at first delivery of this version. +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// These bits simply contain the complement of VER_NUM (0x87), used by a driver +// to ascertain that the Crypto peripheral register is indeed read. +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// The version number for the Crypto peripheral, this field contains the value +// 120 (decimal) or 0x78. +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 + + +#endif // __CRYPTO__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ddi.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ddi.h new file mode 100644 index 0000000000..85ce989f99 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ddi.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Filename: hw_ddi.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_H__ +#define __HW_DDI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the DDI master and +// accessing DDI Slave registers via the DDI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a DDI Slave. +// +// The macros that that provide DDI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example DDI_O_CFG is a macro for a +// register offset and DDI_CFG_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register DDI_O_CFG of the DDI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; +// +// +// The "instruction offset" macros are used to pass an instruction to +// the DDI Master when accessing DDI slave registers. These macros are +// only used when accessing DDI Slave Registers. (Remember DDI +// Master Registers are accessed normally). +// +// The instructions supported when accessing a DDI Slave Regsiter follow: +// - Direct Access to a DDI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a DDI Slave register. +// - Clear the specified bits in a DDI Slave register. +// - Mask write of 4 bits to the a DDI Slave register. +// - Mask write of 8 bits to the a DDI Slave register. +// - Mask write of 16 bits to the a DDI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a DDI Slave register. Only 8- and 16-bit reads are supported. +// +// The generic format of using this marcos for a read follows: +// // read low 16-bits in DDI_SLAVE_OFF +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); +// +// // read high 16-bits in DDI_SLAVE_OFF +// // add 2 for data[31:16] +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); + +// // read data[31:24] byte in DDI_SLAVE_OFF +// // add 3 for data[31:24] +// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); +// +// Notes: In the above example: +// - DDI_MASTER_BASE is the base address of the DDI Master defined +// in the hw_memmap.h header file. +// - DDI_SLAVE_OFF is the DDI Slave offset defined in the +// hw_.h header file (e.g. hw_osc_top.h for the oscsc +// oscillator modules. +// - DDI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to DDI Slave register +// DDI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; + +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; +// +// // Write each byte at DDI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register +// // a long write is needed (32-bits). +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; + +// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register +// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; +// +// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). +// // a short write is needed (16-bits). +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; +// +// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). +// // add 2 to get to byte 1. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; +// +// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). +// // add 6 to get to byte 3. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the DDI master instruction offsets. +// +//***************************************************************************** +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 15:8 are mask. Bits 7:0 are data. + // Requires 'short' write. +#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 31:16 are mask. Bits 15:0 are data. + // Requires 'long' write. + + + +#endif // __HW_DDI_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ddi_0_osc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ddi_0_osc.h new file mode 100644 index 0000000000..932b19680d --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ddi_0_osc.h @@ -0,0 +1,1071 @@ +/****************************************************************************** +* Filename: hw_ddi_0_osc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_0_OSC_H__ +#define __HW_DDI_0_OSC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DDI_0_OSC component +// +//***************************************************************************** +// Control 0 +#define DDI_0_OSC_O_CTL0 0x00000000 + +// Control 1 +#define DDI_0_OSC_O_CTL1 0x00000004 + +// RADC External Configuration +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 + +// Amplitude Compensation Control +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C + +// Amplitude Compensation Threshold 1 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 + +// Amplitude Compensation Threshold 2 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 + +// Analog Bypass Values 1 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 + +// Internal +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C + +// Analog Test Control +#define DDI_0_OSC_O_ATESTCTL 0x00000020 + +// ADC Doubler Nanoamp Control +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 + +// XOSCHF Control +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 + +// Low Frequency Oscillator Control +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C + +// RCOSCHF Control +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 + +// Status 0 +#define DDI_0_OSC_O_STAT0 0x00000034 + +// Status 1 +#define DDI_0_OSC_O_STAT1 0x00000038 + +// Status 2 +#define DDI_0_OSC_O_STAT2 0x0000003C + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL0 +// +//***************************************************************************** +// Field: [31] XTAL_IS_24M +// +// Set based on the accurate high frequency XTAL. +// ENUMs: +// 24M Internal. Only to be used through TI provided API. +// 48M Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 + +// Field: [29] BYPASS_XOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 + +// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 + +// Field: [27:26] DOUBLER_START_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 + +// Field: [25] DOUBLER_RESET_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 + +// Field: [22] FORCE_KICKSTART_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 + +// Field: [16] ALLOW_SCLK_HF_SWITCHING +// +// 0: Default - Switching of HF clock source is disabled . +// 1: Allows switching of sclk_hf source. +// +// Provided to prevent switching of the SCLK_HF source when running from flash +// (a long period during switching could corrupt flash). When sclk_hf +// switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is +// changed, but the switch will not occur until this bit is set. This bit +// should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING +// indicates the new HF clock is ready. When switching completes (also +// indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be +// disabled to prevent flash corruption. Switching should not be enabled when +// running from flash. +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 + +// Field: [14] HPOSC_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 + +// Field: [12] RCOSC_LF_TRIMMED +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 + +// Field: [11] XOSC_HF_POWER_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 + +// Field: [10] XOSC_LF_DIG_BYPASS +// +// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf +// clock. +// +// 0: Use 32kHz XOSC as xosc_lf clock source +// 1: Use digital input (from AON) as xosc_lf clock source. +// +// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf +// as the sclk_lf source. The muxing performed by this bit is not glitch free. +// The following procedure must be followed when changing this field to avoid +// glitches on sclk_lf. +// +// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock +// source. +// 2) Set or clear this bit to bypass or not bypass the xosc_lf. +// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. +// +// It is recommended that either the rcosc_hf or xosc_hf (whichever is +// currently active) be selected as the source in step 1 above. This provides a +// faster clock change. +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 + +// Field: [9] CLK_LOSS_EN +// +// Enable clock loss detection and hence the indicators to system controller. +// Checks both SCLK_HF and SCLK_LF clock loss indicators. +// +// 0: Disable +// 1: Enable +// +// Clock loss detection must be disabled when changing the sclk_lf source. +// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf +// source has completed. +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 + +// Field: [8:7] ACLK_TDC_SRC_SEL +// +// Source select for aclk_tdc. +// +// 00: RCOSC_HF (48MHz) +// 01: RCOSC_HF (24MHz) +// 10: XOSC_HF (24MHz) +// 11: Not used +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 + +// Field: [6:5] ACLK_REF_SRC_SEL +// +// Source select for aclk_ref +// +// 00: RCOSC_HF derived (31.25kHz) +// 01: XOSC_HF derived (31.25kHz) +// 10: RCOSC_LF (32kHz) +// 11: XOSC_LF (32.768kHz) +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 + +// Field: [3:2] SCLK_LF_SRC_SEL +// +// Source select for sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 + +// Field: [1] SCLK_MF_SRC_SEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// XCOSCHFDMF Medium frequency clock derived from high frequency +// XOSC. +// RCOSCHFDMF Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 + +// Field: [0] SCLK_HF_SRC_SEL +// +// Source select for sclk_hf. XOSC option is supported for test and debug only +// and should be used when the XOSC_HF is running. +// ENUMs: +// XOSC High frequency XOSC clk +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL1 +// +//***************************************************************************** +// Field: [22:18] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 + +// Field: [17] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 + +// Field: [1:0] XOSC_HF_FAST_START +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RADCEXTCFG +// +//***************************************************************************** +// Field: [31:22] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 + +// Field: [21:16] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 + +// Field: [15:12] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 + +// Field: [11:6] RADC_DAC_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 + +// Field: [5] RADC_MODE_IS_SAR +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPCTL +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 + +// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 250KHZ Internal. Only to be used through TI provided API. +// 500KHZ Internal. Only to be used through TI provided API. +// 1MHZ Internal. Only to be used through TI provided API. +// 2MHZ Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 + +// Field: [27] AMPCOMP_SW_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 + +// Field: [26] AMPCOMP_SW_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL1 +// +//***************************************************************************** +// Field: [19:16] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 + +// Field: [15:0] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ATESTCTL +// +//***************************************************************************** +// Field: [29] SCLK_LF_AUX_EN +// +// Enable 32 kHz clock to AUX_COMPB. +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL +// +//***************************************************************************** +// Field: [24] NANOAMP_BIAS_ENABLE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 + +// Field: [23] SPARE23 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 + +// Field: [5] ADC_SH_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 + +// Field: [4] ADC_SH_VBUF_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 + +// Field: [1:0] ADC_IREF_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_XOSCHFCTL +// +//***************************************************************************** +// Field: [9:8] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 + +// Field: [6] BYPASS +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 + +// Field: [4:2] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 + +// Field: [1:0] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_LFOSCCTL +// +//***************************************************************************** +// Field: [23:22] XOSCLF_REGULATOR_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 + +// Field: [21:18] XOSCLF_CMIRRWR_RATIO +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 + +// Field: [9:8] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 6P0MEG Internal. Only to be used through TI provided API. +// 6P5MEG Internal. Only to be used through TI provided API. +// 7P0MEG Internal. Only to be used through TI provided API. +// 7P5MEG Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 + +// Field: [7:0] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCHFCTL +// +//***************************************************************************** +// Field: [15:8] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT0 +// +//***************************************************************************** +// Field: [30:29] SCLK_LF_SRC +// +// Indicates source for the sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 + +// Field: [28] SCLK_HF_SRC +// +// Indicates source for the sclk_hf +// ENUMs: +// XOSC High frequency XOSC +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 + +// Field: [22] RCOSC_HF_EN +// +// RCOSC_HF_EN +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 + +// Field: [21] RCOSC_LF_EN +// +// RCOSC_LF_EN +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 + +// Field: [20] XOSC_LF_EN +// +// XOSC_LF_EN +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 + +// Field: [19] CLK_DCDC_RDY +// +// CLK_DCDC_RDY +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 + +// Field: [18] CLK_DCDC_RDY_ACK +// +// CLK_DCDC_RDY_ACK +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 + +// Field: [17] SCLK_HF_LOSS +// +// Indicates sclk_hf is lost +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 + +// Field: [16] SCLK_LF_LOSS +// +// Indicates sclk_lf is lost +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 + +// Field: [15] XOSC_HF_EN +// +// Indicates that XOSC_HF is enabled. +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 + +// Field: [13] XB_48M_CLK_EN +// +// Indicates that the 48MHz clock from the DOUBLER is enabled. +// +// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler +// bypass for the 48MHz crystal). +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 + +// Field: [11] XOSC_HF_LP_BUF_EN +// +// XOSC_HF_LP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 + +// Field: [10] XOSC_HF_HP_BUF_EN +// +// XOSC_HF_HP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 + +// Field: [8] ADC_THMET +// +// ADC_THMET +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 + +// Field: [7] ADC_DATA_READY +// +// indicates when adc_data is ready. +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 + +// Field: [6:1] ADC_DATA +// +// adc_data +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 + +// Field: [0] PENDINGSCLKHFSWITCHING +// +// Indicates when sclk_hf is ready to be switched +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT1 +// +//***************************************************************************** +// Field: [31:28] RAMPSTATE +// +// AMPCOMP FSM State +// ENUMs: +// FAST_START_SETTLE FAST_START_SETTLE +// FAST_START FAST_START +// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 +// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE +// IBIAS_INC IBIAS_INCREMENT +// LPM_UPDATE LPM_UPDATE +// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE +// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE +// IDAC_INCREMENT IDAC_INCREMENT +// HPM_UPDATE HPM_UPDATE +// HPM_RAMP3 HPM_RAMP3 +// HPM_RAMP2 HPM_RAMP2 +// HPM_RAMP1 HPM_RAMP1 +// INITIALIZATION INITIALIZATION +// RESET RESET +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 + +// Field: [27:22] HPM_UPDATE_AMP +// +// OSC amplitude during HPM_UPDATE state. +// When amplitude compensation of XOSC_HF is enabled in high performance mode, +// this value is the amplitude of the crystal oscillations measured by the +// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 +// would indicate that the amplitude of the crystal is approximately 480 mV. +// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 + +// Field: [21:16] LPM_UPDATE_AMP +// +// OSC amplitude during LPM_UPDATE state +// When amplitude compensation of XOSC_HF is enabled in low power mode, this +// value is the amplitude of the crystal oscillations measured by the on-chip +// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would +// indicate that the amplitude of the crystal is approximately 480 mV. To +// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 + +// Field: [15] FORCE_RCOSC_HF +// +// force_rcosc_hf +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 + +// Field: [14] SCLK_HF_EN +// +// SCLK_HF_EN +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 + +// Field: [13] SCLK_MF_EN +// +// SCLK_MF_EN +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 + +// Field: [12] ACLK_ADC_EN +// +// ACLK_ADC_EN +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 + +// Field: [11] ACLK_TDC_EN +// +// ACLK_TDC_EN +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 + +// Field: [10] ACLK_REF_EN +// +// ACLK_REF_EN +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 + +// Field: [9] CLK_CHP_EN +// +// CLK_CHP_EN +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 + +// Field: [8] CLK_DCDC_EN +// +// CLK_DCDC_EN +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 + +// Field: [7] SCLK_HF_GOOD +// +// SCLK_HF_GOOD +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 + +// Field: [6] SCLK_MF_GOOD +// +// SCLK_MF_GOOD +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 + +// Field: [5] SCLK_LF_GOOD +// +// SCLK_LF_GOOD +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 + +// Field: [4] ACLK_ADC_GOOD +// +// ACLK_ADC_GOOD +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 + +// Field: [3] ACLK_TDC_GOOD +// +// ACLK_TDC_GOOD +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 + +// Field: [2] ACLK_REF_GOOD +// +// ACLK_REF_GOOD +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 + +// Field: [1] CLK_CHP_GOOD +// +// CLK_CHP_GOOD +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 + +// Field: [0] CLK_DCDC_GOOD +// +// CLK_DCDC_GOOD +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT2 +// +//***************************************************************************** +// Field: [31:26] ADC_DCBIAS +// +// DC Bias read by RADC during SAR mode +// The value is an unsigned integer. It is used for debug only. +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 + +// Field: [25] HPM_RAMP1_THMET +// +// Indication of threshold is met for hpm_ramp1 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 + +// Field: [24] HPM_RAMP2_THMET +// +// Indication of threshold is met for hpm_ramp2 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 + +// Field: [23] HPM_RAMP3_THMET +// +// Indication of threshold is met for hpm_ramp3 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 + +// Field: [15:12] RAMPSTATE +// +// xosc_hf amplitude compensation FSM +// +// This is identical to STAT1.RAMPSTATE. See that description for encoding. +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 + +// Field: [3] AMPCOMP_REQ +// +// ampcomp_req +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 + +// Field: [2] XOSC_HF_AMPGOOD +// +// amplitude of xosc_hf is within the required threshold (set by DDI). Not used +// for anything just for debug/status +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 + +// Field: [1] XOSC_HF_FREQGOOD +// +// frequency of xosc_hf is good to use for the digital clocks +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 + +// Field: [0] XOSC_HF_RF_FREQGOOD +// +// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio +// operations. Used for SW to start synthesizer. +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 + + +#endif // __DDI_0_OSC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_device.h b/os/common/ext/TI/devices/cc13x0/inc/hw_device.h new file mode 100644 index 0000000000..b181336a03 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_device.h @@ -0,0 +1,168 @@ +/****************************************************************************** +* Filename: hw_device.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DEVICE_H__ +#define __HW_DEVICE_H__ + +#include "../inc/hw_chip_def.h" + +#ifdef CC_GET_CHIP_PACKAGE + +#if ( CC_GET_CHIP_PACKAGE == 0x7 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 7x7 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 0x3F +#define AON_EVENT_DIO1 17 +#define AON_EVENT_DIO2 16 +#define AON_EVENT_DIO3 15 +#define AON_EVENT_DIO4 14 +#define AON_EVENT_DIO5 13 +#define AON_EVENT_DIO6 12 +#define AON_EVENT_DIO7 11 +#define AON_EVENT_DIO8 10 +#define AON_EVENT_DIO9 9 +#define AON_EVENT_DIO10 8 +#define AON_EVENT_DIO11 7 +#define AON_EVENT_DIO12 6 +#define AON_EVENT_DIO13 5 +#define AON_EVENT_DIO14 4 +#define AON_EVENT_DIO15 3 +#define AON_EVENT_DIO16 2 +#define AON_EVENT_DIO17 1 +#define AON_EVENT_DIO18 31 +#define AON_EVENT_DIO19 30 +#define AON_EVENT_DIO20 29 +#define AON_EVENT_DIO21 28 +#define AON_EVENT_DIO22 27 +#define AON_EVENT_DIO23 26 +#define AON_EVENT_DIO24 25 +#define AON_EVENT_DIO25 24 +#define AON_EVENT_DIO26 23 +#define AON_EVENT_DIO27 22 +#define AON_EVENT_DIO28 21 +#define AON_EVENT_DIO29 20 +#define AON_EVENT_DIO30 19 +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) + +#if ( CC_GET_CHIP_PACKAGE == 0x5 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 5x5 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 15 +#define AON_EVENT_DIO1 14 +#define AON_EVENT_DIO2 13 +#define AON_EVENT_DIO3 12 +#define AON_EVENT_DIO4 11 +#define AON_EVENT_DIO5 2 +#define AON_EVENT_DIO6 1 +#define AON_EVENT_DIO7 26 +#define AON_EVENT_DIO8 25 +#define AON_EVENT_DIO9 23 +#define AON_EVENT_DIO10 24 +#define AON_EVENT_DIO11 22 +#define AON_EVENT_DIO12 21 +#define AON_EVENT_DIO13 20 +#define AON_EVENT_DIO14 19 +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) + +#if ( CC_GET_CHIP_PACKAGE == 0x4 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 4x4 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 13 +#define AON_EVENT_DIO1 12 +#define AON_EVENT_DIO2 11 +#define AON_EVENT_DIO3 2 +#define AON_EVENT_DIO4 1 +#define AON_EVENT_DIO5 26 +#define AON_EVENT_DIO6 25 +#define AON_EVENT_DIO7 24 +#define AON_EVENT_DIO8 23 +#define AON_EVENT_DIO9 22 +#define AON_EVENT_DIO10 0x3F +#define AON_EVENT_DIO11 0x3F +#define AON_EVENT_DIO12 0x3F +#define AON_EVENT_DIO13 0x3F +#define AON_EVENT_DIO14 0x3F +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) + +#endif // defined( CC_GET_CHIP_PACKAGE ) +#endif // __HW_DEVICE_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_event.h b/os/common/ext/TI/devices/cc13x0/inc/hw_event.h new file mode 100644 index 0000000000..d29e70799f --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_event.h @@ -0,0 +1,3301 @@ +/****************************************************************************** +* Filename: hw_event_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_EVENT_H__ +#define __HW_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVENT component +// +//***************************************************************************** +// Output Selection for CPU Interrupt 0 +#define EVENT_O_CPUIRQSEL0 0x00000000 + +// Output Selection for CPU Interrupt 1 +#define EVENT_O_CPUIRQSEL1 0x00000004 + +// Output Selection for CPU Interrupt 2 +#define EVENT_O_CPUIRQSEL2 0x00000008 + +// Output Selection for CPU Interrupt 3 +#define EVENT_O_CPUIRQSEL3 0x0000000C + +// Output Selection for CPU Interrupt 4 +#define EVENT_O_CPUIRQSEL4 0x00000010 + +// Output Selection for CPU Interrupt 5 +#define EVENT_O_CPUIRQSEL5 0x00000014 + +// Output Selection for CPU Interrupt 6 +#define EVENT_O_CPUIRQSEL6 0x00000018 + +// Output Selection for CPU Interrupt 7 +#define EVENT_O_CPUIRQSEL7 0x0000001C + +// Output Selection for CPU Interrupt 8 +#define EVENT_O_CPUIRQSEL8 0x00000020 + +// Output Selection for CPU Interrupt 9 +#define EVENT_O_CPUIRQSEL9 0x00000024 + +// Output Selection for CPU Interrupt 10 +#define EVENT_O_CPUIRQSEL10 0x00000028 + +// Output Selection for CPU Interrupt 11 +#define EVENT_O_CPUIRQSEL11 0x0000002C + +// Output Selection for CPU Interrupt 12 +#define EVENT_O_CPUIRQSEL12 0x00000030 + +// Output Selection for CPU Interrupt 13 +#define EVENT_O_CPUIRQSEL13 0x00000034 + +// Output Selection for CPU Interrupt 14 +#define EVENT_O_CPUIRQSEL14 0x00000038 + +// Output Selection for CPU Interrupt 15 +#define EVENT_O_CPUIRQSEL15 0x0000003C + +// Output Selection for CPU Interrupt 16 +#define EVENT_O_CPUIRQSEL16 0x00000040 + +// Output Selection for CPU Interrupt 17 +#define EVENT_O_CPUIRQSEL17 0x00000044 + +// Output Selection for CPU Interrupt 18 +#define EVENT_O_CPUIRQSEL18 0x00000048 + +// Output Selection for CPU Interrupt 19 +#define EVENT_O_CPUIRQSEL19 0x0000004C + +// Output Selection for CPU Interrupt 20 +#define EVENT_O_CPUIRQSEL20 0x00000050 + +// Output Selection for CPU Interrupt 21 +#define EVENT_O_CPUIRQSEL21 0x00000054 + +// Output Selection for CPU Interrupt 22 +#define EVENT_O_CPUIRQSEL22 0x00000058 + +// Output Selection for CPU Interrupt 23 +#define EVENT_O_CPUIRQSEL23 0x0000005C + +// Output Selection for CPU Interrupt 24 +#define EVENT_O_CPUIRQSEL24 0x00000060 + +// Output Selection for CPU Interrupt 25 +#define EVENT_O_CPUIRQSEL25 0x00000064 + +// Output Selection for CPU Interrupt 26 +#define EVENT_O_CPUIRQSEL26 0x00000068 + +// Output Selection for CPU Interrupt 27 +#define EVENT_O_CPUIRQSEL27 0x0000006C + +// Output Selection for CPU Interrupt 28 +#define EVENT_O_CPUIRQSEL28 0x00000070 + +// Output Selection for CPU Interrupt 29 +#define EVENT_O_CPUIRQSEL29 0x00000074 + +// Output Selection for CPU Interrupt 30 +#define EVENT_O_CPUIRQSEL30 0x00000078 + +// Output Selection for CPU Interrupt 31 +#define EVENT_O_CPUIRQSEL31 0x0000007C + +// Output Selection for CPU Interrupt 32 +#define EVENT_O_CPUIRQSEL32 0x00000080 + +// Output Selection for CPU Interrupt 33 +#define EVENT_O_CPUIRQSEL33 0x00000084 + +// Output Selection for RFC Event 0 +#define EVENT_O_RFCSEL0 0x00000100 + +// Output Selection for RFC Event 1 +#define EVENT_O_RFCSEL1 0x00000104 + +// Output Selection for RFC Event 2 +#define EVENT_O_RFCSEL2 0x00000108 + +// Output Selection for RFC Event 3 +#define EVENT_O_RFCSEL3 0x0000010C + +// Output Selection for RFC Event 4 +#define EVENT_O_RFCSEL4 0x00000110 + +// Output Selection for RFC Event 5 +#define EVENT_O_RFCSEL5 0x00000114 + +// Output Selection for RFC Event 6 +#define EVENT_O_RFCSEL6 0x00000118 + +// Output Selection for RFC Event 7 +#define EVENT_O_RFCSEL7 0x0000011C + +// Output Selection for RFC Event 8 +#define EVENT_O_RFCSEL8 0x00000120 + +// Output Selection for RFC Event 9 +#define EVENT_O_RFCSEL9 0x00000124 + +// Output Selection for GPT0 0 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 + +// Output Selection for GPT0 1 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 + +// Output Selection for GPT1 0 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 + +// Output Selection for GPT1 1 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 + +// Output Selection for GPT2 0 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 + +// Output Selection for GPT2 1 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 + +// Output Selection for DMA Channel 1 SREQ +#define EVENT_O_UDMACH1SSEL 0x00000508 + +// Output Selection for DMA Channel 1 REQ +#define EVENT_O_UDMACH1BSEL 0x0000050C + +// Output Selection for DMA Channel 2 SREQ +#define EVENT_O_UDMACH2SSEL 0x00000510 + +// Output Selection for DMA Channel 2 REQ +#define EVENT_O_UDMACH2BSEL 0x00000514 + +// Output Selection for DMA Channel 3 SREQ +#define EVENT_O_UDMACH3SSEL 0x00000518 + +// Output Selection for DMA Channel 3 REQ +#define EVENT_O_UDMACH3BSEL 0x0000051C + +// Output Selection for DMA Channel 4 SREQ +#define EVENT_O_UDMACH4SSEL 0x00000520 + +// Output Selection for DMA Channel 4 REQ +#define EVENT_O_UDMACH4BSEL 0x00000524 + +// Output Selection for DMA Channel 5 SREQ +#define EVENT_O_UDMACH5SSEL 0x00000528 + +// Output Selection for DMA Channel 5 REQ +#define EVENT_O_UDMACH5BSEL 0x0000052C + +// Output Selection for DMA Channel 6 SREQ +#define EVENT_O_UDMACH6SSEL 0x00000530 + +// Output Selection for DMA Channel 6 REQ +#define EVENT_O_UDMACH6BSEL 0x00000534 + +// Output Selection for DMA Channel 7 SREQ +#define EVENT_O_UDMACH7SSEL 0x00000538 + +// Output Selection for DMA Channel 7 REQ +#define EVENT_O_UDMACH7BSEL 0x0000053C + +// Output Selection for DMA Channel 8 SREQ +#define EVENT_O_UDMACH8SSEL 0x00000540 + +// Output Selection for DMA Channel 8 REQ +#define EVENT_O_UDMACH8BSEL 0x00000544 + +// Output Selection for DMA Channel 9 SREQ +#define EVENT_O_UDMACH9SSEL 0x00000548 + +// Output Selection for DMA Channel 9 REQ +#define EVENT_O_UDMACH9BSEL 0x0000054C + +// Output Selection for DMA Channel 10 SREQ +#define EVENT_O_UDMACH10SSEL 0x00000550 + +// Output Selection for DMA Channel 10 REQ +#define EVENT_O_UDMACH10BSEL 0x00000554 + +// Output Selection for DMA Channel 11 SREQ +#define EVENT_O_UDMACH11SSEL 0x00000558 + +// Output Selection for DMA Channel 11 REQ +#define EVENT_O_UDMACH11BSEL 0x0000055C + +// Output Selection for DMA Channel 12 SREQ +#define EVENT_O_UDMACH12SSEL 0x00000560 + +// Output Selection for DMA Channel 12 REQ +#define EVENT_O_UDMACH12BSEL 0x00000564 + +// Output Selection for DMA Channel 13 REQ +#define EVENT_O_UDMACH13BSEL 0x0000056C + +// Output Selection for DMA Channel 14 REQ +#define EVENT_O_UDMACH14BSEL 0x00000574 + +// Output Selection for DMA Channel 15 REQ +#define EVENT_O_UDMACH15BSEL 0x0000057C + +// Output Selection for DMA Channel 16 SREQ +#define EVENT_O_UDMACH16SSEL 0x00000580 + +// Output Selection for DMA Channel 16 REQ +#define EVENT_O_UDMACH16BSEL 0x00000584 + +// Output Selection for DMA Channel 17 SREQ +#define EVENT_O_UDMACH17SSEL 0x00000588 + +// Output Selection for DMA Channel 17 REQ +#define EVENT_O_UDMACH17BSEL 0x0000058C + +// Output Selection for DMA Channel 21 SREQ +#define EVENT_O_UDMACH21SSEL 0x000005A8 + +// Output Selection for DMA Channel 21 REQ +#define EVENT_O_UDMACH21BSEL 0x000005AC + +// Output Selection for DMA Channel 22 SREQ +#define EVENT_O_UDMACH22SSEL 0x000005B0 + +// Output Selection for DMA Channel 22 REQ +#define EVENT_O_UDMACH22BSEL 0x000005B4 + +// Output Selection for DMA Channel 23 SREQ +#define EVENT_O_UDMACH23SSEL 0x000005B8 + +// Output Selection for DMA Channel 23 REQ +#define EVENT_O_UDMACH23BSEL 0x000005BC + +// Output Selection for DMA Channel 24 SREQ +#define EVENT_O_UDMACH24SSEL 0x000005C0 + +// Output Selection for DMA Channel 24 REQ +#define EVENT_O_UDMACH24BSEL 0x000005C4 + +// Output Selection for GPT3 0 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 + +// Output Selection for GPT3 1 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 + +// Output Selection for AUX Subscriber 0 +#define EVENT_O_AUXSEL0 0x00000700 + +// Output Selection for NMI Subscriber 0 +#define EVENT_O_CM3NMISEL0 0x00000800 + +// Output Selection for I2S Subscriber 0 +#define EVENT_O_I2SSTMPSEL0 0x00000900 + +// Output Selection for FRZ Subscriber +#define EVENT_O_FRZSEL0 0x00000A00 + +// Set or Clear Software Events +#define EVENT_O_SWEV 0x00000F00 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2C_IRQ Interrupt event from I2C +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV0 AUX software event 0, triggered by +// AUX_EVCTL:SWEVSET.SWEV0, also available as +// AUX_EVENT0 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL10 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL11 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL12 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2S_IRQ Interrupt event from I2S +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL13 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL14 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL15 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL16 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL17 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL18 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL19 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL20 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL21 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL22 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL23 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL24 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL25 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL26 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL27 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL28 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL29 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL30 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// NONE Always inactive +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL31 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL32 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL33 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5SSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5BSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6SSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6BSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH13BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH14BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2C_IRQ Interrupt event from I2C +// I2S_IRQ Interrupt event from I2S +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH15BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_AUXSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// NONE Always inactive +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CM3NMISEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 + +//***************************************************************************** +// +// Register: EVENT_O_I2SSTMPSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// NONE Always inactive +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_FRZSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// NONE Always inactive +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_SWEV +// +//***************************************************************************** +// Field: [24] SWEV3 +// +// Writing "1" to this bit when the value is "0" triggers the Software 3 event. +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 + +// Field: [16] SWEV2 +// +// Writing "1" to this bit when the value is "0" triggers the Software 2 event. +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 + +// Field: [8] SWEV1 +// +// Writing "1" to this bit when the value is "0" triggers the Software 1 event. +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 + +// Field: [0] SWEV0 +// +// Writing "1" to this bit when the value is "0" triggers the Software 0 event. +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 + + +#endif // __EVENT__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_fcfg1.h b/os/common/ext/TI/devices/cc13x0/inc/hw_fcfg1.h new file mode 100644 index 0000000000..f92c371422 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_fcfg1.h @@ -0,0 +1,3028 @@ +/****************************************************************************** +* Filename: hw_fcfg1_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FCFG1_H__ +#define __HW_FCFG1_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FCFG1 component +// +//***************************************************************************** +// Misc configurations +#define FCFG1_O_MISC_CONF_1 0x000000A0 + +// Internal +#define FCFG1_O_MISC_CONF_2 0x000000A4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 + +// Shadow of EFUSE:DIE_ID_0 +#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 + +// Shadow of EFUSE:DIE_ID_1 +#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C + +// Shadow of EFUSE:DIE_ID_2 +#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 + +// Shadow of EFUSE:DIE_ID_3 +#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 + +// Internal +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 + +// Internal +#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C + +#define FCFG1_O_FLASH_NUMBER 0x00000164 + +#define FCFG1_O_FLASH_COORDINATE 0x0000016C + +// Internal +#define FCFG1_O_FLASH_E_P 0x00000170 + +// Internal +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +// Internal +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +// Internal +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +// Internal +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +// Internal +#define FCFG1_O_FLASH_PP 0x00000184 + +// Internal +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +// Internal +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +// Internal +#define FCFG1_O_FLASH_VHV 0x00000190 + +// Internal +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +// Internal +#define FCFG1_O_FLASH_V 0x00000198 + +// User Identification. +#define FCFG1_O_USER_ID 0x00000294 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +// Internal +#define FCFG1_O_ANA2_TRIM 0x000002B4 + +// Internal +#define FCFG1_O_LDO_TRIM 0x000002B8 + +// Internal +#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC + +// MAC BLE Address 0 +#define FCFG1_O_MAC_BLE_0 0x000002E8 + +// MAC BLE Address 1 +#define FCFG1_O_MAC_BLE_1 0x000002EC + +// MAC IEEE 802.15.4 Address 0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 + +// MAC IEEE 802.15.4 Address 1 +#define FCFG1_O_MAC_15_4_1 0x000002F4 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +// Miscellaneous Trim Parameters +#define FCFG1_O_MISC_TRIM 0x0000030C + +// Internal +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 + +// Internal +#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 + +// IcePick Device Identification +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 + +// Factory Configuration (FCFG1) Revision +#define FCFG1_O_FCFG1_REVISION 0x0000031C + +// Misc OTP Data +#define FCFG1_O_MISC_OTP_DATA 0x00000320 + +// IO Configuration +#define FCFG1_O_IOCONF 0x00000344 + +// Internal +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C + +// Internal +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 + +// Internal +#define FCFG1_O_CONFIG_SYNTH 0x00000358 + +// AUX_ADC Gain in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C + +// AUX_ADC Gain in Relative Reference Mode +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 + +// AUX_ADC Temperature Offsets in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 + +// Internal +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C + +// Internal +#define FCFG1_O_AMPCOMP_TH1 0x00000370 + +// Internal +#define FCFG1_O_AMPCOMP_TH2 0x00000374 + +// Internal +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 + +// Internal +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 + +// Internal +#define FCFG1_O_VOLT_TRIM 0x00000388 + +// OSC Configuration +#define FCFG1_O_OSC_CONF 0x0000038C + +// Internal +#define FCFG1_O_FREQ_OFFSET 0x00000390 + +// Internal +#define FCFG1_O_CAP_TRIM 0x00000394 + +// Internal +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 + +// Power Down Current Control 20C +#define FCFG1_O_PWD_CURR_20C 0x0000039C + +// Power Down Current Control 35C +#define FCFG1_O_PWD_CURR_35C 0x000003A0 + +// Power Down Current Control 50C +#define FCFG1_O_PWD_CURR_50C 0x000003A4 + +// Power Down Current Control 65C +#define FCFG1_O_PWD_CURR_65C 0x000003A8 + +// Power Down Current Control 80C +#define FCFG1_O_PWD_CURR_80C 0x000003AC + +// Power Down Current Control 95C +#define FCFG1_O_PWD_CURR_95C 0x000003B0 + +// Power Down Current Control 110C +#define FCFG1_O_PWD_CURR_110C 0x000003B4 + +// Power Down Current Control 125C +#define FCFG1_O_PWD_CURR_125C 0x000003B8 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_1 +// +//***************************************************************************** +// Field: [7:0] DEVICE_MINOR_REV +// +// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). +// Any test of this field by SW should be implemented as a 'greater or equal' +// comparison as signed integer. +// Value may change without warning. +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_2 +// +//***************************************************************************** +// Field: [7:0] HPOSC_COMP_P3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV5 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV6 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV10 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV12 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV15 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV30 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV5 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV10 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV15 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV30 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV5 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV6 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV10 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV12 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV15 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV30 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_0 +// +//***************************************************************************** +// Field: [31:0] ID_31_0 +// +// Shadow of the DIE_ID_0 register in eFuse row number 3 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_1 +// +//***************************************************************************** +// Field: [31:0] ID_63_32 +// +// Shadow of the DIE_ID_1 register in eFuse row number 4 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_2 +// +//***************************************************************************** +// Field: [31:0] ID_95_64 +// +// Shadow of the DIE_ID_2 register in eFuse row number 5 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_3 +// +//***************************************************************************** +// Field: [31:0] ID_127_96 +// +// Shadow of the DIE_ID_3 register in eFuse row number 6 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM +// +//***************************************************************************** +// Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ + 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ + 0x18000000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ + 27 + +// Field: [26:23] TRIMMAG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 + +// Field: [22:18] TRIMIREF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 + +// Field: [17:16] ITRIM_DIG_LDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 + +// Field: [15:12] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 + +// Field: [11:8] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 + +// Field: [7:0] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_ANA_TRIM +// +//***************************************************************************** +// Field: [26:25] BOD_BANDGAP_TRIM_CNF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 + +// Field: [24] VDDR_ENABLE_PG1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 + +// Field: [23] VDDR_OK_HYS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 + +// Field: [22:21] IPTAT_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 + +// Field: [20:16] VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 + +// Field: [15:11] TRIMBOD_INTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 + +// Field: [10:6] TRIMBOD_EXTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 + +// Field: [5:0] TRIMTEMP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_NUMBER +// +//***************************************************************************** +// Field: [31:0] LOT_NUMBER +// +// Number of the manufacturing lot that produced this unit. +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_COORDINATE +// +//***************************************************************************** +// Field: [31:16] XCOORDINATE +// +// X coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 + +// Field: [15:0] YCOORDINATE +// +// Y coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_E_P +// +//***************************************************************************** +// Field: [31:24] PSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +// Field: [23:16] ESU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +// Field: [15:8] PVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +// Field: [7:0] EVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_C_E_P_R +// +//***************************************************************************** +// Field: [31:24] RVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +// Field: [23:16] PV_ACCESS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +// Field: [15:12] A_EXEZ_SETUP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +// Field: [11:0] CVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_P_R_PV +// +//***************************************************************************** +// Field: [31:24] PH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +// Field: [23:16] RH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +// Field: [15:8] PVH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +// Field: [7:0] PVH2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_EH_SEQ +// +//***************************************************************************** +// Field: [31:24] EH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +// Field: [23:16] SEQ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 + +// Field: [15:12] VSTAT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +// Field: [11:0] SM_FREQUENCY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_E +// +//***************************************************************************** +// Field: [31:16] VHV_E_START +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +// Field: [15:0] VHV_E_STEP_HIGHT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PP +// +//***************************************************************************** +// Field: [31:24] PUMP_SU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 + +// Field: [15:0] MAX_PP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PROG_EP +// +//***************************************************************************** +// Field: [31:16] MAX_EP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +// Field: [15:0] PROGRAM_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_ERA_PW +// +//***************************************************************************** +// Field: [31:0] ERASE_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV +// +//***************************************************************************** +// Field: [27:24] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +// Field: [19:16] VHV_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +// Field: [11:8] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +// Field: [3:0] VHV_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_PV +// +//***************************************************************************** +// Field: [27:24] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +// Field: [19:16] VHV_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +// Field: [15:8] VCG2P5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +// Field: [7:0] VINH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_V +// +//***************************************************************************** +// Field: [31:24] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +// Field: [23:16] VWL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +// Field: [15:8] V_READ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +//***************************************************************************** +// +// Register: FCFG1_O_USER_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 + +// Field: [27:26] VER +// +// Version number. +// +// 0x0: Bits [25:12] of this register has the stated meaning. +// +// Any other setting indicate a different encoding of these bits. +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 + +// Field: [22:19] SEQUENCE +// +// Sequence. +// +// Used to differentiate between marketing/orderable product where other fields +// of USER_ID is the same (temp range, flash size, voltage range etc) +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 + +// Field: [18:16] PKG +// +// Package type. +// +// 0x0: 4x4mm QFN (RHB) package +// 0x1: 5x5mm QFN (RSM) package +// 0x2: 7x7mm QFN (RGZ) package +// 0x3: Wafer sale package (naked die) +// 0x4: 2.7x2.7mm WCSP (YFV) +// 0x5: 7x7mm QFN package with Wettable Flanks +// +// Other values are reserved for future use. +// Packages available for a specific device are shown in the device datasheet. +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 + +// Field: [15:12] PROTOCOL +// +// Protocols supported. +// +// 0x1: BLE +// 0x2: RF4CE +// 0x4: Zigbee/6lowpan +// 0x8: Proprietary +// +// More than one protocol can be supported on same device - values above are +// then combined. +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA3 +// +//***************************************************************************** +// Field: [31:23] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +// Field: [22] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +// Field: [21:18] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +// Field: [17:16] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +// Field: [15:8] FLASH_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 + +// Field: [7:0] WAIT_SYSCODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANA2_TRIM +// +//***************************************************************************** +// Field: [31] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 + +// Field: [30:26] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 + +// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 + +// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 + +// Field: [21:16] NANOAMP_RES_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 + +// Field: [11] DITHER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 + +// Field: [10:8] DCDC_IPEAK +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 + +// Field: [7:6] DEAD_TIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 + +// Field: [5:3] DCDC_LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 + +// Field: [2:0] DCDC_HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_LDO_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_SLEEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 + +// Field: [18:16] GLDO_CURSRC +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 + +// Field: [12:11] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 + +// Field: [10:8] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 + +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_BAT_RC_LDO_TRIM +// +//***************************************************************************** +// Field: [27:24] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 + +// Field: [19:16] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 + +// Field: [11:8] RCOSCHF_ITUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 + +// Field: [1:0] MEASUREPER +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA4 +// +//***************************************************************************** +// Field: [31] STANDBY_MODE_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +// Field: [30:29] STANDBY_PW_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +// Field: [28] DIS_STANDBY_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 + +// Field: [27] DIS_IDLE_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 + +// Field: [26:24] VIN_AT_X_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +// Field: [23] STANDBY_MODE_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +// Field: [22:21] STANDBY_PW_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +// Field: [20] DIS_STANDBY_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 + +// Field: [19] DIS_IDLE_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 + +// Field: [18:16] VIN_AT_X_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +// Field: [15] STANDBY_MODE_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +// Field: [14:13] STANDBY_PW_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +// Field: [12] DIS_STANDBY_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 + +// Field: [11] DIS_IDLE_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 + +// Field: [10:8] VIN_AT_X_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +// Field: [7] STANDBY_MODE_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +// Field: [6:5] STANDBY_PW_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +// Field: [4] DIS_STANDBY_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 + +// Field: [3] DIS_IDLE_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 + +// Field: [2:0] VIN_AT_X_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_TRIM +// +//***************************************************************************** +// Field: [7:0] TEMPVSLOPE +// +// Signed byte value representing the TEMP slope with battery voltage, in +// degrees C / V, with four fractional bits. +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_RCOSC_HF_TEMPCOMP +// +//***************************************************************************** +// Field: [31:24] FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 + +// Field: [23:16] CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 + +// Field: [15:8] CTRIMFRACT_QUAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 + +// Field: [7:0] CTRIMFRACT_SLOPE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_TRIM_CAL_REVISION +// +//***************************************************************************** +// Field: [31:16] FT1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 +#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 + +// Field: [15:0] MP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 +#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF +#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ICEPICK_DEVICE_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 + +// Field: [27:12] WAFER_ID +// +// Field used to identify silicon die. +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 + +// Field: [11:0] MANUFACTURER_ID +// +// Manufacturer code. +// +// 0x02F: Texas Instruments +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FCFG1_REVISION +// +//***************************************************************************** +// Field: [31:0] REV +// +// The revision number of the FCFG1 layout. This value will be read by +// application SW in order to determine which FCFG1 parameters that have valid +// values. This revision number must be incremented by 1 before any devices are +// to be produced if the FCFG1 layout has changed since the previous production +// of devices. +// Value migth change without warning. +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA +// +//***************************************************************************** +// Field: [31:28] RCOSC_HF_ITUNE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 + +// Field: [27:20] RCOSC_HF_CRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 + +// Field: [19:15] PER_M +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 + +// Field: [14:12] PER_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 + +// Field: [11:8] MIN_ALLOWED_RTRIM_DIV5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_W 4 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M 0x00000F00 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S 8 + +// Field: [7:0] TEST_PROGRAM_REV +// +// The revision of the test program used in the production process when FCFG1 +// was programmed. +// Value migth change without warning. +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_IOCONF +// +//***************************************************************************** +// Field: [6:0] GPIO_CNT +// +// Number of available DIOs. +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_IF_ADC +// +//***************************************************************************** +// Field: [31:28] FF2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 + +// Field: [27:24] FF3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 + +// Field: [23:20] INT3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 + +// Field: [19:16] FF1ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 + +// Field: [15:14] AAFCAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 + +// Field: [13:10] INT2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 + +// Field: [9:5] IFDIGLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 + +// Field: [4:0] IFANALDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_OSC_TOP +// +//***************************************************************************** +// Field: [29:26] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 + +// Field: [25:10] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 + +// Field: [9:2] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 + +// Field: [1:0] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization only on +// cc13x0. +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_ABS_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 +// +// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REL_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 +// +// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_OFFSET_INT +// +//***************************************************************************** +// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 +// +// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 + +// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 +// +// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT +// +//***************************************************************************** +// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ + 6 +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ + 0x0000003F +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ + 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_CTRL1 +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANABYPASS_VALUE2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S 18 + +// Field: [17] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_VOLT_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_HH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 + +// Field: [20:16] VDDR_TRIM_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 + +// Field: [12:8] VDDR_TRIM_SLEEP_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 + +// Field: [4:0] TRIMBOD_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_OSC_CONF +// +//***************************************************************************** +// Field: [29] ADC_SH_VBUF_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 + +// Field: [28] ADC_SH_MODE_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 + +// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM +// +// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 + +// Field: [26:25] XOSCLF_REGULATOR_TRIM +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 + +// Field: [24:21] XOSCLF_CMIRRWR_RATIO +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 + +// Field: [20:19] XOSC_HF_FAST_START +// +// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 + +// Field: [18] XOSC_OPTION +// +// 0: XOSC_HF unavailable (may not be bonded out) +// 1: XOSC_HF available (default) +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 + +// Field: [17] HPOSC_OPTION +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 + +// Field: [16] HPOSC_BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 + +// Field: [15:12] HPOSC_CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 + +// Field: [11:8] HPOSC_BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 + +// Field: [7] HPOSC_FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 + +// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 + +// Field: [2:1] HPOSC_SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 + +// Field: [0] HPOSC_DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HPOSC_COMP_P0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 + +// Field: [15:8] HPOSC_COMP_P1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 + +// Field: [7:0] HPOSC_COMP_P2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CAP_TRIM +// +//***************************************************************************** +// Field: [31:16] FLUX_CAP_0P28_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 + +// Field: [15:0] FLUX_CAP_0P4_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA_1 +// +//***************************************************************************** +// Field: [28:27] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 + +// Field: [26:24] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 + +// Field: [23:22] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 + +// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 + +// Field: [19:10] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 + +// Field: [9:4] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 + +// Field: [3:0] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_20C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_20C_BASELINE_W 8 +#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_20C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_35C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_35C_BASELINE_W 8 +#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_35C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_50C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_50C_BASELINE_W 8 +#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_50C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_65C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_65C_BASELINE_W 8 +#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_65C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_80C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_80C_BASELINE_W 8 +#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_80C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_95C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_95C_BASELINE_W 8 +#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_95C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_110C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_110C_BASELINE_W 8 +#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_110C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_125C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_125C_BASELINE_W 8 +#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_125C_BASELINE_S 0 + + +#endif // __FCFG1__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_flash.h b/os/common/ext/TI/devices/cc13x0/inc/hw_flash.h new file mode 100644 index 0000000000..a685a04b30 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_flash.h @@ -0,0 +1,3475 @@ +/****************************************************************************** +* Filename: hw_flash_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FLASH component +// +//***************************************************************************** +// FMC and Efuse Status +#define FLASH_O_STAT 0x0000001C + +// Internal +#define FLASH_O_CFG 0x00000024 + +// Internal +#define FLASH_O_SYSCODE_START 0x00000028 + +// Internal +#define FLASH_O_FLASH_SIZE 0x0000002C + +// Internal +#define FLASH_O_FWLOCK 0x0000003C + +// Internal +#define FLASH_O_FWFLAG 0x00000040 + +// Internal +#define FLASH_O_EFUSE 0x00001000 + +// Internal +#define FLASH_O_EFUSEADDR 0x00001004 + +// Internal +#define FLASH_O_DATAUPPER 0x00001008 + +// Internal +#define FLASH_O_DATALOWER 0x0000100C + +// Internal +#define FLASH_O_EFUSECFG 0x00001010 + +// Internal +#define FLASH_O_EFUSESTAT 0x00001014 + +// Internal +#define FLASH_O_ACC 0x00001018 + +// Internal +#define FLASH_O_BOUNDARY 0x0000101C + +// Internal +#define FLASH_O_EFUSEFLAG 0x00001020 + +// Internal +#define FLASH_O_EFUSEKEY 0x00001024 + +// Internal +#define FLASH_O_EFUSERELEASE 0x00001028 + +// Internal +#define FLASH_O_EFUSEPINS 0x0000102C + +// Internal +#define FLASH_O_EFUSECRA 0x00001030 + +// Internal +#define FLASH_O_EFUSEREAD 0x00001034 + +// Internal +#define FLASH_O_EFUSEPROGRAM 0x00001038 + +// Internal +#define FLASH_O_EFUSEERROR 0x0000103C + +// Internal +#define FLASH_O_SINGLEBIT 0x00001040 + +// Internal +#define FLASH_O_TWOBIT 0x00001044 + +// Internal +#define FLASH_O_SELFTESTCYC 0x00001048 + +// Internal +#define FLASH_O_SELFTESTSIGN 0x0000104C + +// Internal +#define FLASH_O_FRDCTL 0x00002000 + +// Internal +#define FLASH_O_FSPRD 0x00002004 + +// Internal +#define FLASH_O_FEDACCTL1 0x00002008 + +// Internal +#define FLASH_O_FEDACSTAT 0x0000201C + +// Internal +#define FLASH_O_FBPROT 0x00002030 + +// Internal +#define FLASH_O_FBSE 0x00002034 + +// Internal +#define FLASH_O_FBBUSY 0x00002038 + +// Internal +#define FLASH_O_FBAC 0x0000203C + +// Internal +#define FLASH_O_FBFALLBACK 0x00002040 + +// Internal +#define FLASH_O_FBPRDY 0x00002044 + +// Internal +#define FLASH_O_FPAC1 0x00002048 + +// Internal +#define FLASH_O_FPAC2 0x0000204C + +// Internal +#define FLASH_O_FMAC 0x00002050 + +// Internal +#define FLASH_O_FMSTAT 0x00002054 + +// Internal +#define FLASH_O_FLOCK 0x00002064 + +// Internal +#define FLASH_O_FVREADCT 0x00002080 + +// Internal +#define FLASH_O_FVHVCT1 0x00002084 + +// Internal +#define FLASH_O_FVHVCT2 0x00002088 + +// Internal +#define FLASH_O_FVHVCT3 0x0000208C + +// Internal +#define FLASH_O_FVNVCT 0x00002090 + +// Internal +#define FLASH_O_FVSLP 0x00002094 + +// Internal +#define FLASH_O_FVWLCT 0x00002098 + +// Internal +#define FLASH_O_FEFUSECTL 0x0000209C + +// Internal +#define FLASH_O_FEFUSESTAT 0x000020A0 + +// Internal +#define FLASH_O_FEFUSEDATA 0x000020A4 + +// Internal +#define FLASH_O_FSEQPMP 0x000020A8 + +// Internal +#define FLASH_O_FBSTROBES 0x00002100 + +// Internal +#define FLASH_O_FPSTROBES 0x00002104 + +// Internal +#define FLASH_O_FBMODE 0x00002108 + +// Internal +#define FLASH_O_FTCR 0x0000210C + +// Internal +#define FLASH_O_FADDR 0x00002110 + +// Internal +#define FLASH_O_FTCTL 0x0000211C + +// Internal +#define FLASH_O_FWPWRITE0 0x00002120 + +// Internal +#define FLASH_O_FWPWRITE1 0x00002124 + +// Internal +#define FLASH_O_FWPWRITE2 0x00002128 + +// Internal +#define FLASH_O_FWPWRITE3 0x0000212C + +// Internal +#define FLASH_O_FWPWRITE4 0x00002130 + +// Internal +#define FLASH_O_FWPWRITE5 0x00002134 + +// Internal +#define FLASH_O_FWPWRITE6 0x00002138 + +// Internal +#define FLASH_O_FWPWRITE7 0x0000213C + +// Internal +#define FLASH_O_FWPWRITE_ECC 0x00002140 + +// Internal +#define FLASH_O_FSWSTAT 0x00002144 + +// Internal +#define FLASH_O_FSM_GLBCTL 0x00002200 + +// Internal +#define FLASH_O_FSM_STATE 0x00002204 + +// Internal +#define FLASH_O_FSM_STAT 0x00002208 + +// Internal +#define FLASH_O_FSM_CMD 0x0000220C + +// Internal +#define FLASH_O_FSM_PE_OSU 0x00002210 + +// Internal +#define FLASH_O_FSM_VSTAT 0x00002214 + +// Internal +#define FLASH_O_FSM_PE_VSU 0x00002218 + +// Internal +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +// Internal +#define FLASH_O_FSM_EX_VAL 0x00002220 + +// Internal +#define FLASH_O_FSM_RD_H 0x00002224 + +// Internal +#define FLASH_O_FSM_P_OH 0x00002228 + +// Internal +#define FLASH_O_FSM_ERA_OH 0x0000222C + +// Internal +#define FLASH_O_FSM_SAV_PPUL 0x00002230 + +// Internal +#define FLASH_O_FSM_PE_VH 0x00002234 + +// Internal +#define FLASH_O_FSM_PRG_PW 0x00002240 + +// Internal +#define FLASH_O_FSM_ERA_PW 0x00002244 + +// Internal +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 + +// Internal +#define FLASH_O_FSM_TIMER 0x00002258 + +// Internal +#define FLASH_O_FSM_MODE 0x0000225C + +// Internal +#define FLASH_O_FSM_PGM 0x00002260 + +// Internal +#define FLASH_O_FSM_ERA 0x00002264 + +// Internal +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +// Internal +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +// Internal +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +// Internal +#define FLASH_O_FSM_PUL_CNTR 0x00002274 + +// Internal +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +// Internal +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +// Internal +#define FLASH_O_FSM_FLES 0x00002280 + +// Internal +#define FLASH_O_FSM_WR_ENA 0x00002288 + +// Internal +#define FLASH_O_FSM_ACC_PP 0x0000228C + +// Internal +#define FLASH_O_FSM_ACC_EP 0x00002290 + +// Internal +#define FLASH_O_FSM_ADDR 0x000022A0 + +// Internal +#define FLASH_O_FSM_SECTOR 0x000022A4 + +// Internal +#define FLASH_O_FMC_REV_ID 0x000022A8 + +// Internal +#define FLASH_O_FSM_ERR_ADDR 0x000022AC + +// Internal +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 + +// Internal +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +// Internal +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +// Internal +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +// Internal +#define FLASH_O_FSM_BSLE0 0x000022E0 + +// Internal +#define FLASH_O_FSM_BSLE1 0x000022E4 + +// Internal +#define FLASH_O_FSM_BSLP0 0x000022F0 + +// Internal +#define FLASH_O_FSM_BSLP1 0x000022F4 + +// Internal +#define FLASH_O_FCFG_BANK 0x00002400 + +// Internal +#define FLASH_O_FCFG_WRAPPER 0x00002404 + +// Internal +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 + +// Internal +#define FLASH_O_FCFG_B0_START 0x00002410 + +// Internal +#define FLASH_O_FCFG_B1_START 0x00002414 + +// Internal +#define FLASH_O_FCFG_B2_START 0x00002418 + +// Internal +#define FLASH_O_FCFG_B3_START 0x0000241C + +// Internal +#define FLASH_O_FCFG_B4_START 0x00002420 + +// Internal +#define FLASH_O_FCFG_B5_START 0x00002424 + +// Internal +#define FLASH_O_FCFG_B6_START 0x00002428 + +// Internal +#define FLASH_O_FCFG_B7_START 0x0000242C + +// Internal +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +//***************************************************************************** +// +// Register: FLASH_O_STAT +// +//***************************************************************************** +// Field: [15] EFUSE_BLANK +// +// Efuse scanning detected if fuse ROM is blank: +// 0 : Not blank +// 1 : Blank +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 + +// Field: [14] EFUSE_TIMEOUT +// +// Efuse scanning resulted in timeout error. +// 0 : No Timeout error +// 1 : Timeout Error +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 + +// Field: [13] EFUSE_CRC_ERROR +// +// Efuse scanning resulted in scan chain CRC error. +// 0 : No CRC error +// 1 : CRC Error +#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 +#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 + +// Field: [12:8] EFUSE_ERRCODE +// +// Same as EFUSEERROR.CODE +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 + +// Field: [2] SAMHOLD_DIS +// +// Status indicator of flash sample and hold sequencing logic. This bit will go +// to 1 some delay after CFG.DIS_IDLE is set to 1. +// 0: Not disabled +// 1: Sample and hold disabled and stable +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 + +// Field: [1] BUSY +// +// Fast version of the FMC FMSTAT.BUSY bit. +// This flag is valid immediately after the operation setting it (FMSTAT.BUSY +// is delayed some cycles) +// 0 : Not busy +// 1 : Busy +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 + +// Field: [0] POWER_MODE +// +// Power state of the flash sub-system. +// 0 : Active +// 1 : Low power +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_CFG +// +//***************************************************************************** +// Field: [8] STANDBY_MODE_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +// Field: [7:6] STANDBY_PW_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +// Field: [5] DIS_EFUSECLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 + +// Field: [4] DIS_READACCESS +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 + +// Field: [3] ENABLE_SWINTF +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 + +// Field: [1] DIS_STANDBY +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 + +// Field: [0] DIS_IDLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SYSCODE_START +// +//***************************************************************************** +// Field: [4:0] SYSCODE_START +// +// Internal. Only to be used through TI provided API. +#define FLASH_SYSCODE_START_SYSCODE_START_W 5 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLASH_SIZE +// +//***************************************************************************** +// Field: [7:0] SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWLOCK +// +//***************************************************************************** +// Field: [2:0] FWLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWFLAG +// +//***************************************************************************** +// Field: [2:0] FWFLAG +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSE +// +//***************************************************************************** +// Field: [28:24] INSTRUCTION +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 + +// Field: [15:0] DUMPWORD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEADDR +// +//***************************************************************************** +// Field: [15:11] BLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 + +// Field: [10:0] ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATAUPPER +// +//***************************************************************************** +// Field: [7:3] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 + +// Field: [2] P +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 + +// Field: [1] R +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 + +// Field: [0] EEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATALOWER +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECFG +// +//***************************************************************************** +// Field: [8] IDLEGATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 + +// Field: [4:3] SLAVEPOWER +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 + +// Field: [0] GATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSESTAT +// +//***************************************************************************** +// Field: [0] RESETDONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_ACC +// +//***************************************************************************** +// Field: [23:0] ACCUMULATOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_BOUNDARY +// +//***************************************************************************** +// Field: [23] DISROW0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 + +// Field: [22] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 + +// Field: [21] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 + +// Field: [20] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 + +// Field: [19] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 + +// Field: [18] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 + +// Field: [17:14] OUTPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 + +// Field: [11] EFC_FDI +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 + +// Field: [10] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 + +// Field: [9:8] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 + +// Field: [7:4] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 + +// Field: [3:0] INPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEFLAG +// +//***************************************************************************** +// Field: [0] KEY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEKEY +// +//***************************************************************************** +// Field: [31:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSERELEASE +// +//***************************************************************************** +// Field: [31:25] ODPYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 + +// Field: [24:21] ODPMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 + +// Field: [20:16] ODPDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 + +// Field: [15:9] EFUSEYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 + +// Field: [8:5] EFUSEMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 + +// Field: [4:0] EFUSEDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPINS +// +//***************************************************************************** +// Field: [15] EFC_SELF_TEST_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 + +// Field: [14] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 + +// Field: [11] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 + +// Field: [10] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 + +// Field: [9] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 + +// Field: [8] EFC_READY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 + +// Field: [7] EFC_FCLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 + +// Field: [6] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 + +// Field: [5:4] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 + +// Field: [3:0] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECRA +// +//***************************************************************************** +// Field: [5:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEREAD +// +//***************************************************************************** +// Field: [9:8] DATABIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 + +// Field: [7:4] READCLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 + +// Field: [3] DEBUG +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 + +// Field: [2] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 + +// Field: [1:0] MARGIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPROGRAM +// +//***************************************************************************** +// Field: [30] COMPAREDISABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 + +// Field: [29:14] CLOCKSTALL +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 + +// Field: [13] VPPTOVDD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 + +// Field: [12:9] ITERATIONS +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 + +// Field: [8:0] WRITECLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEERROR +// +//***************************************************************************** +// Field: [5] DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 + +// Field: [4:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SINGLEBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_TWOBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTCYC +// +//***************************************************************************** +// Field: [31:0] CYCLES +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTSIGN +// +//***************************************************************************** +// Field: [31:0] SIGNATURE +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FRDCTL +// +//***************************************************************************** +// Field: [11:8] RWAIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSPRD +// +//***************************************************************************** +// Field: [15:8] RMBSEM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 + +// Field: [1] RM1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 + +// Field: [0] RM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACCTL1 +// +//***************************************************************************** +// Field: [24] SUSP_IGNR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACSTAT +// +//***************************************************************************** +// Field: [25] RVF_INT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 + +// Field: [24] FSM_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FBPROT +// +//***************************************************************************** +// Field: [0] PROTL1DIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBSE +// +//***************************************************************************** +// Field: [15:0] BSE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBBUSY +// +//***************************************************************************** +// Field: [7:0] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBAC +// +//***************************************************************************** +// Field: [16] OTPPROTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 + +// Field: [15:8] BAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 + +// Field: [7:0] VREADS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBFALLBACK +// +//***************************************************************************** +// Field: [27:24] FSM_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 + +// Field: [19:16] REG_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 + +// Field: [15:14] BANKPWR7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 + +// Field: [13:12] BANKPWR6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 + +// Field: [11:10] BANKPWR5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 + +// Field: [9:8] BANKPWR4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 + +// Field: [7:6] BANKPWR3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 + +// Field: [5:4] BANKPWR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 + +// Field: [3:2] BANKPWR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 + +// Field: [1:0] BANKPWR0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBPRDY +// +//***************************************************************************** +// Field: [16] BANKBUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 + +// Field: [15] PUMPRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 + +// Field: [0] BANKRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC1 +// +//***************************************************************************** +// Field: [27:16] PSLEEPTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 + +// Field: [15:4] PUMPRESET_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 + +// Field: [1:0] PUMPPWR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC2 +// +//***************************************************************************** +// Field: [15:0] PAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMAC +// +//***************************************************************************** +// Field: [2:0] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMSTAT +// +//***************************************************************************** +// Field: [17] RVSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 + +// Field: [16] RDVER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 + +// Field: [15] RVF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 + +// Field: [14] ILA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 + +// Field: [13] DBF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 + +// Field: [12] PGV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 + +// Field: [11] PCV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 + +// Field: [10] EV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 + +// Field: [9] CV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 + +// Field: [8] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 + +// Field: [7] ERS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 + +// Field: [6] PGM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 + +// Field: [5] INVDAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 + +// Field: [4] CSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 + +// Field: [3] VOLSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 + +// Field: [2] ESUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 + +// Field: [1] PSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 + +// Field: [0] SLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLOCK +// +//***************************************************************************** +// Field: [15:0] ENCOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVREADCT +// +//***************************************************************************** +// Field: [3:0] VREADCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT1 +// +//***************************************************************************** +// Field: [23:20] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +// Field: [19:16] VHVCT_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +// Field: [7:4] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +// Field: [3:0] VHVCT_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT2 +// +//***************************************************************************** +// Field: [23:20] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +// Field: [19:16] VHVCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT3 +// +//***************************************************************************** +// Field: [19:16] WCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 + +// Field: [3:0] VHVCT_READ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVNVCT +// +//***************************************************************************** +// Field: [12:8] VCG2P5CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +// Field: [4:0] VIN_CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVSLP +// +//***************************************************************************** +// Field: [15:12] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FVWLCT +// +//***************************************************************************** +// Field: [4:0] VWLCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSECTL +// +//***************************************************************************** +// Field: [26:24] CHAIN_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 + +// Field: [17] WRITE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 + +// Field: [16] BP_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 + +// Field: [8] EF_CLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 + +// Field: [4] EF_TEST +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 + +// Field: [3:0] EFUSE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSESTAT +// +//***************************************************************************** +// Field: [0] SHIFT_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSEDATA +// +//***************************************************************************** +// Field: [31:0] FEFUSEDATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSEQPMP +// +//***************************************************************************** +// Field: [27:24] TRIM_3P4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 + +// Field: [21:20] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +// Field: [19:16] TRIM_0P8 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 + +// Field: [14:12] VIN_AT_X +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +// Field: [8] VIN_BY_PASS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FBSTROBES +// +//***************************************************************************** +// Field: [24] ECBIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 + +// Field: [18] RWAIT2_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 + +// Field: [17] RWAIT_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 + +// Field: [16] FLCLKEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 + +// Field: [8] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 + +// Field: [6] NOCOLRED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 + +// Field: [5] PRECOL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 + +// Field: [4] TI_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 + +// Field: [3] OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 + +// Field: [2] TEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 + +//***************************************************************************** +// +// Register: FLASH_O_FPSTROBES +// +//***************************************************************************** +// Field: [8] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 + +// Field: [1] V3PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 + +// Field: [0] V5PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBMODE +// +//***************************************************************************** +// Field: [2:0] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCR +// +//***************************************************************************** +// Field: [6:0] TCR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FADDR +// +//***************************************************************************** +// Field: [31:0] FADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCTL +// +//***************************************************************************** +// Field: [16] WDATA_BLK_CLR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 + +// Field: [1] TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE0 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE1 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE2 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE3 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE4 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE5 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE6 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE7 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE_ECC +// +//***************************************************************************** +// Field: [31:24] ECCBYTES07_00 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 + +// Field: [23:16] ECCBYTES15_08 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 + +// Field: [15:8] ECCBYTES23_16 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 + +// Field: [7:0] ECCBYTES31_24 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSWSTAT +// +//***************************************************************************** +// Field: [0] SAFELV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_GLBCTL +// +//***************************************************************************** +// Field: [0] CLKSEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STATE +// +//***************************************************************************** +// Field: [11] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 + +// Field: [10] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 + +// Field: [8] FSM_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 + +// Field: [7] TIOTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 + +// Field: [6] OTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STAT +// +//***************************************************************************** +// Field: [2] NON_OP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 + +// Field: [1] OVR_PUL_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 + +// Field: [0] INV_DAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMD +// +//***************************************************************************** +// Field: [5:0] FSMCMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_OSU +// +//***************************************************************************** +// Field: [15:8] PGM_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +// Field: [7:0] ERA_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_VSTAT +// +//***************************************************************************** +// Field: [15:12] VSTAT_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VSU +// +//***************************************************************************** +// Field: [15:8] PGM_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +// Field: [7:0] ERA_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMP_VSU +// +//***************************************************************************** +// Field: [15:12] ADD_EXZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EX_VAL +// +//***************************************************************************** +// Field: [15:8] REP_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +// Field: [7:0] EXE_VALD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_RD_H +// +//***************************************************************************** +// Field: [7:0] RD_H +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_P_OH +// +//***************************************************************************** +// Field: [15:8] PGM_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_OH +// +//***************************************************************************** +// Field: [15:0] ERA_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_PPUL +// +//***************************************************************************** +// Field: [11:0] SAV_P_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VH +// +//***************************************************************************** +// Field: [15:8] PGM_VH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PW +// +//***************************************************************************** +// Field: [15:0] PROG_PUL_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PW +// +//***************************************************************************** +// Field: [31:0] FSM_ERA_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_ERA_PUL +// +//***************************************************************************** +// Field: [11:0] SAV_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_TIMER +// +//***************************************************************************** +// Field: [31:0] FSM_TIMER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_MODE +// +//***************************************************************************** +// Field: [19:18] RDV_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 + +// Field: [17:16] PGM_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 + +// Field: [15:14] ERA_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 + +// Field: [13:12] SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 + +// Field: [11:9] SAV_PGM_CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 + +// Field: [8:6] SAV_ERA_MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 + +// Field: [5:3] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 + +// Field: [2:0] CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM +// +//***************************************************************************** +// Field: [25:23] PGM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 + +// Field: [22:0] PGM_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA +// +//***************************************************************************** +// Field: [25:23] ERA_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 + +// Field: [22:0] ERA_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PUL +// +//***************************************************************************** +// Field: [19:16] BEG_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +// Field: [11:0] MAX_PRG_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PUL +// +//***************************************************************************** +// Field: [19:16] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +// Field: [11:0] MAX_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STEP_SIZE +// +//***************************************************************************** +// Field: [24:16] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PUL_CNTR +// +//***************************************************************************** +// Field: [24:16] CUR_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 + +// Field: [11:0] PUL_CNTR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EC_STEP_HEIGHT +// +//***************************************************************************** +// Field: [3:0] EC_STEP_HEIGHT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ST_MACHINE +// +//***************************************************************************** +// Field: [23] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +// Field: [22] FSM_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 + +// Field: [21] ALL_BANKS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 + +// Field: [20] CMPV_ALLOWED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 + +// Field: [19] RANDOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 + +// Field: [18] RV_SEC_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 + +// Field: [17] RV_RES +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 + +// Field: [16] RV_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 + +// Field: [14] ONE_TIME_GOOD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 + +// Field: [11] DO_REDU_COL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 + +// Field: [10:7] DBG_SHORT_ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 + +// Field: [5] PGM_SEC_COF_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 + +// Field: [4] PREC_STOP_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 + +// Field: [3] DIS_TST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 + +// Field: [2] CMD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 + +// Field: [1] INV_DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 + +// Field: [0] OVERRIDE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_FLES +// +//***************************************************************************** +// Field: [11:8] BLK_TIOTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 + +// Field: [7:0] BLK_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_WR_ENA +// +//***************************************************************************** +// Field: [2:0] WR_ENA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_PP +// +//***************************************************************************** +// Field: [31:0] FSM_ACC_PP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_EP +// +//***************************************************************************** +// Field: [15:0] ACC_EP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ADDR +// +//***************************************************************************** +// Field: [30:28] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 + +// Field: [27:0] CUR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR +// +//***************************************************************************** +// Field: [31:16] SECT_ERASED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 + +// Field: [15:8] FSM_SECTOR_EXTENSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 + +// Field: [7:4] SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 + +// Field: [3:0] SEC_OUT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMC_REV_ID +// +//***************************************************************************** +// Field: [31:12] MOD_VERSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 + +// Field: [11:0] CONFIG_CRC +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERR_ADDR +// +//***************************************************************************** +// Field: [31:8] FSM_ERR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 + +// Field: [3:0] FSM_ERR_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM_MAXPUL +// +//***************************************************************************** +// Field: [11:0] FSM_PGM_MAXPUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EXECUTE +// +//***************************************************************************** +// Field: [19:16] SUSPEND_NOW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 + +// Field: [4:0] FSMEXECUTE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR1 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR2 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLP0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BANK +// +//***************************************************************************** +// Field: [31:20] EE_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 + +// Field: [19:16] EE_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 + +// Field: [15:4] MAIN_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 + +// Field: [3:0] MAIN_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_WRAPPER +// +//***************************************************************************** +// Field: [31:24] FAMILY_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 + +// Field: [20] MEM_MAP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 + +// Field: [19:16] CPU2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 + +// Field: [15:12] EE_IN_MAIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 + +// Field: [11] ROM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 + +// Field: [10] IFLUSH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 + +// Field: [9] SIL3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 + +// Field: [8] ECCA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 + +// Field: [7:6] AUTO_SUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 + +// Field: [5:4] UERR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 + +// Field: [3:0] CPU_TYPE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BNK_TYPE +// +//***************************************************************************** +// Field: [31:28] B7_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 + +// Field: [27:24] B6_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 + +// Field: [23:20] B5_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 + +// Field: [19:16] B4_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 + +// Field: [15:12] B3_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 + +// Field: [11:8] B2_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 + +// Field: [7:4] B1_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 + +// Field: [3:0] B0_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_START +// +//***************************************************************************** +// Field: [31:28] B0_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 + +// Field: [27:24] B0_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 + +// Field: [23:0] B0_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_START +// +//***************************************************************************** +// Field: [31:28] B1_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 + +// Field: [27:24] B1_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 + +// Field: [23:0] B1_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_START +// +//***************************************************************************** +// Field: [31:28] B2_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 + +// Field: [27:24] B2_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 + +// Field: [23:0] B2_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_START +// +//***************************************************************************** +// Field: [31:28] B3_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 + +// Field: [27:24] B3_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 + +// Field: [23:0] B3_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_START +// +//***************************************************************************** +// Field: [31:28] B4_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 + +// Field: [27:24] B4_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 + +// Field: [23:0] B4_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_START +// +//***************************************************************************** +// Field: [31:28] B5_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 + +// Field: [27:24] B5_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 + +// Field: [23:0] B5_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_START +// +//***************************************************************************** +// Field: [31:28] B6_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 + +// Field: [27:24] B6_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 + +// Field: [23:0] B6_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_START +// +//***************************************************************************** +// Field: [31:28] B7_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 + +// Field: [27:24] B7_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 + +// Field: [23:0] B7_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + + +#endif // __FLASH__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_gpio.h b/os/common/ext/TI/devices/cc13x0/inc/hw_gpio.h new file mode 100644 index 0000000000..9975f073bc --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_gpio.h @@ -0,0 +1,2247 @@ +/****************************************************************************** +* Filename: hw_gpio_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPIO component +// +//***************************************************************************** +// Data Out 0 to 3 +#define GPIO_O_DOUT3_0 0x00000000 + +// Data Out 4 to 7 +#define GPIO_O_DOUT7_4 0x00000004 + +// Data Out 8 to 11 +#define GPIO_O_DOUT11_8 0x00000008 + +// Data Out 12 to 15 +#define GPIO_O_DOUT15_12 0x0000000C + +// Data Out 16 to 19 +#define GPIO_O_DOUT19_16 0x00000010 + +// Data Out 20 to 23 +#define GPIO_O_DOUT23_20 0x00000014 + +// Data Out 24 to 27 +#define GPIO_O_DOUT27_24 0x00000018 + +// Data Out 28 to 31 +#define GPIO_O_DOUT31_28 0x0000001C + +// Data Output for DIO 0 to 31 +#define GPIO_O_DOUT31_0 0x00000080 + +// Data Out Set +#define GPIO_O_DOUTSET31_0 0x00000090 + +// Data Out Clear +#define GPIO_O_DOUTCLR31_0 0x000000A0 + +// Data Out Toggle +#define GPIO_O_DOUTTGL31_0 0x000000B0 + +// Data Input from DIO 0 to 31 +#define GPIO_O_DIN31_0 0x000000C0 + +// Data Output Enable for DIO 0 to 31 +#define GPIO_O_DOE31_0 0x000000D0 + +// Event Register for DIO 0 to 31 +#define GPIO_O_EVFLAGS31_0 0x000000E0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Sets the state of the pin that is configured as DIO#3, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 + +// Field: [16] DIO2 +// +// Sets the state of the pin that is configured as DIO#2, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 + +// Field: [8] DIO1 +// +// Sets the state of the pin that is configured as DIO#1, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 + +// Field: [0] DIO0 +// +// Sets the state of the pin that is configured as DIO#0, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Sets the state of the pin that is configured as DIO#7, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 + +// Field: [16] DIO6 +// +// Sets the state of the pin that is configured as DIO#6, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 + +// Field: [8] DIO5 +// +// Sets the state of the pin that is configured as DIO#5, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 + +// Field: [0] DIO4 +// +// Sets the state of the pin that is configured as DIO#4, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Sets the state of the pin that is configured as DIO#11, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 + +// Field: [16] DIO10 +// +// Sets the state of the pin that is configured as DIO#10, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 + +// Field: [8] DIO9 +// +// Sets the state of the pin that is configured as DIO#9, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 + +// Field: [0] DIO8 +// +// Sets the state of the pin that is configured as DIO#8, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Sets the state of the pin that is configured as DIO#15, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 + +// Field: [16] DIO14 +// +// Sets the state of the pin that is configured as DIO#14, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 + +// Field: [8] DIO13 +// +// Sets the state of the pin that is configured as DIO#13, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 + +// Field: [0] DIO12 +// +// Sets the state of the pin that is configured as DIO#12, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Sets the state of the pin that is configured as DIO#19, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 + +// Field: [16] DIO18 +// +// Sets the state of the pin that is configured as DIO#18, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 + +// Field: [8] DIO17 +// +// Sets the state of the pin that is configured as DIO#17, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 + +// Field: [0] DIO16 +// +// Sets the state of the pin that is configured as DIO#16, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Sets the state of the pin that is configured as DIO#23, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 + +// Field: [16] DIO22 +// +// Sets the state of the pin that is configured as DIO#22, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 + +// Field: [8] DIO21 +// +// Sets the state of the pin that is configured as DIO#21, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 + +// Field: [0] DIO20 +// +// Sets the state of the pin that is configured as DIO#20, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT27_24 +// +//***************************************************************************** +// Field: [24] DIO27 +// +// Sets the state of the pin that is configured as DIO#27, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 + +// Field: [16] DIO26 +// +// Sets the state of the pin that is configured as DIO#26, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 + +// Field: [8] DIO25 +// +// Sets the state of the pin that is configured as DIO#25, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 + +// Field: [0] DIO24 +// +// Sets the state of the pin that is configured as DIO#24, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_28 +// +//***************************************************************************** +// Field: [24] DIO31 +// +// Sets the state of the pin that is configured as DIO#31, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 + +// Field: [16] DIO30 +// +// Sets the state of the pin that is configured as DIO#30, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 + +// Field: [8] DIO29 +// +// Sets the state of the pin that is configured as DIO#29, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 + +// Field: [0] DIO28 +// +// Sets the state of the pin that is configured as DIO#28, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output for DIO 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output for DIO 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output for DIO 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output for DIO 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output for DIO 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output for DIO 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output for DIO 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output for DIO 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output for DIO 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output for DIO 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output for DIO 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output for DIO 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output for DIO 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output for DIO 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output for DIO 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output for DIO 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output for DIO 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output for DIO 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output for DIO 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output for DIO 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output for DIO 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output for DIO 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output for DIO 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output for DIO 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output for DIO 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output for DIO 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output for DIO 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output for DIO 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output for DIO 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output for DIO 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output for DIO 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output for DIO 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTSET31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Set bit 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Set bit 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Set bit 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Set bit 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Set bit 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Set bit 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Set bit 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Set bit 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Set bit 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Set bit 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Set bit 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Set bit 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Set bit 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Set bit 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Set bit 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Set bit 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Set bit 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Set bit 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Set bit 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Set bit 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Set bit 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Set bit 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Set bit 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Set bit 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Set bit 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Set bit 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Set bit 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Set bit 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Set bit 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Set bit 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Set bit 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Set bit 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTCLR31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Clears bit 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Clears bit 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Clears bit 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Clears bit 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Clears bit 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Clears bit 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Clears bit 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Clears bit 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Clears bit 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Clears bit 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Clears bit 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Clears bit 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Clears bit 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Clears bit 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Clears bit 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Clears bit 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Clears bit 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Clears bit 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Clears bit 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Clears bit 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Clears bit 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Clears bit 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Clears bit 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Clears bit 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Clears bit 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Clears bit 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Clears bit 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Clears bit 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Clears bit 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Clears bit 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Clears bit 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Clears bit 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Toggles bit 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Toggles bit 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Toggles bit 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Toggles bit 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Toggles bit 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Toggles bit 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Toggles bit 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Toggles bit 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Toggles bit 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Toggles bit 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Toggles bit 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Toggles bit 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Toggles bit 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Toggles bit 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Toggles bit 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Toggles bit 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Toggles bit 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Toggles bit 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Toggles bit 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Toggles bit 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Toggles bit 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Toggles bit 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Toggles bit 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Toggles bit 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Toggles bit 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Toggles bit 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Toggles bit 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Toggles bit 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Toggles bit 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Toggles bit 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Toggles bit 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Toggles bit 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DIN31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data input from DIO 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data input from DIO 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data input from DIO 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data input from DIO 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data input from DIO 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data input from DIO 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data input from DIO 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data input from DIO 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data input from DIO 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data input from DIO 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data input from DIO 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data input from DIO 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data input from DIO 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data input from DIO 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data input from DIO 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data input from DIO 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data input from DIO 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data input from DIO 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data input from DIO 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data input from DIO 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data input from DIO 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data input from DIO 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data input from DIO 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data input from DIO 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data input from DIO 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data input from DIO 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data input from DIO 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data input from DIO 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data input from DIO 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data input from DIO 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data input from DIO 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data input from DIO 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOE31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output enable for DIO 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output enable for DIO 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output enable for DIO 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output enable for DIO 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output enable for DIO 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output enable for DIO 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output enable for DIO 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output enable for DIO 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output enable for DIO 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output enable for DIO 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output enable for DIO 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output enable for DIO 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output enable for DIO 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output enable for DIO 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output enable for DIO 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output enable for DIO 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output enable for DIO 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output enable for DIO 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output enable for DIO 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output enable for DIO 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output enable for DIO 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output enable for DIO 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output enable for DIO 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output enable for DIO 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output enable for DIO 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output enable for DIO 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output enable for DIO 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output enable for DIO 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output enable for DIO 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output enable for DIO 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output enable for DIO 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output enable for DIO 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_EVFLAGS31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Event for DIO 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Event for DIO 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Event for DIO 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Event for DIO 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Event for DIO 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Event for DIO 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Event for DIO 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Event for DIO 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Event for DIO 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Event for DIO 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Event for DIO 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Event for DIO 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Event for DIO 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Event for DIO 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Event for DIO 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Event for DIO 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Event for DIO 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Event for DIO 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Event for DIO 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Event for DIO 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Event for DIO 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Event for DIO 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Event for DIO 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Event for DIO 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Event for DIO 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Event for DIO 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Event for DIO 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Event for DIO 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Event for DIO 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Event for DIO 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Event for DIO 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Event for DIO 0 +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 + + +#endif // __GPIO__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_gpt.h b/os/common/ext/TI/devices/cc13x0/inc/hw_gpt.h new file mode 100644 index 0000000000..49592d1c2e --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_gpt.h @@ -0,0 +1,1686 @@ +/****************************************************************************** +* Filename: hw_gpt_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPT_H__ +#define __HW_GPT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPT component +// +//***************************************************************************** +// Configuration +#define GPT_O_CFG 0x00000000 + +// Timer A Mode +#define GPT_O_TAMR 0x00000004 + +// Timer B Mode +#define GPT_O_TBMR 0x00000008 + +// Control +#define GPT_O_CTL 0x0000000C + +// Synch Register +#define GPT_O_SYNC 0x00000010 + +// Interrupt Mask +#define GPT_O_IMR 0x00000018 + +// Raw Interrupt Status +#define GPT_O_RIS 0x0000001C + +// Masked Interrupt Status +#define GPT_O_MIS 0x00000020 + +// Interrupt Clear +#define GPT_O_ICLR 0x00000024 + +// Timer A Interval Load Register +#define GPT_O_TAILR 0x00000028 + +// Timer B Interval Load Register +#define GPT_O_TBILR 0x0000002C + +// Timer A Match Register +#define GPT_O_TAMATCHR 0x00000030 + +// Timer B Match Register +#define GPT_O_TBMATCHR 0x00000034 + +// Timer A Pre-scale +#define GPT_O_TAPR 0x00000038 + +// Timer B Pre-scale +#define GPT_O_TBPR 0x0000003C + +// Timer A Pre-scale Match +#define GPT_O_TAPMR 0x00000040 + +// Timer B Pre-scale Match +#define GPT_O_TBPMR 0x00000044 + +// Timer A Register +#define GPT_O_TAR 0x00000048 + +// Timer B Register +#define GPT_O_TBR 0x0000004C + +// Timer A Value +#define GPT_O_TAV 0x00000050 + +// Timer B Value +#define GPT_O_TBV 0x00000054 + +// Timer A Pre-scale Snap-shot +#define GPT_O_TAPS 0x0000005C + +// Timer B Pre-scale Snap-shot +#define GPT_O_TBPS 0x00000060 + +// Timer A Pre-scale Value +#define GPT_O_TAPV 0x00000064 + +// Timer B Pre-scale Value +#define GPT_O_TBPV 0x00000068 + +// DMA Event +#define GPT_O_DMAEV 0x0000006C + +// Peripheral Version +#define GPT_O_VERSION 0x00000FB0 + +// Combined CCP Output +#define GPT_O_ANDCCP 0x00000FB4 + +//***************************************************************************** +// +// Register: GPT_O_CFG +// +//***************************************************************************** +// Field: [2:0] CFG +// +// GPT Configuration +// 0x2- 0x3 - Reserved +// 0x5- 0x7 - Reserved +// ENUMs: +// 16BIT_TIMER 16-bit timer configuration. +// Configure for two 16-bit +// timers. +// Also see TAMR.TAMR and +// TBMR.TBMR. +// 32BIT_TIMER 32-bit timer configuration +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_TAMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TACINTD +// +// One-Shot/Periodic Interrupt Disable +// ENUMs: +// DIS_TO_INTR Time-out interrupt are disabled +// EN_TO_INTR Time-out interrupt function as normal +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TAPLO +// +// GPTM Timer A PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TAILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TAILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 + +// Field: [10] TAMRSU +// +// Timer A Match Register Update mode +// +// This bit defines when the TAMATCHR and TAPR registers are updated. +// +// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and +// TAPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and +// TAPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TAMATCHR and TAPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next +// cycle. +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TAPWMIE +// +// GPTM Timer A PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TAEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 + +// Field: [8] TAILD +// +// GPT Timer A PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TAR register with the value in the +// TAILR register on the next timeout. If the +// prescaler is used, update the TAPS register +// with the value in the TAPR register on the next +// timeout. +// CYCLEUPDATE Update the TAR register with the value in the +// TAILR register on the next clock cycle. If the +// pre-scaler is used, update the TAPS register +// with the value in the TAPR register on the next +// clock cycle. +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TASNAPS +// +// GPT Timer A Snap-Shot Mode +// ENUMs: +// EN If Timer A is configured in the periodic mode, the +// actual free-running value of Timer A is loaded +// at the time-out event into the GPT Timer A +// (TAR) register. +// DIS Snap-shot mode is disabled. +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 + +// Field: [6] TAWOT +// +// GPT Timer A Wait-On-Trigger +// ENUMs: +// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does +// not begin counting until it receives a trigger +// from the timer in the previous position in the +// daisy chain. This bit must be clear for GPT +// Module 0, Timer A. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer A begins counting as soon as it is enabled. +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 + +// Field: [5] TAMIE +// +// GPT Timer A Match Interrupt Enable +// ENUMs: +// EN An interrupt is generated when the match value in +// TAMATCHR is reached in the one-shot and +// periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 + +// Field: [4] TACDIR +// +// GPT Timer A Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 + +// Field: [3] TAAMS +// +// GPT Timer A Alternate Mode +// +// Note: To enable PWM mode, you must also clear TACM and then configure TAMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 + +// Field: [2] TACM +// +// GPT Timer A Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 + +// Field: [1:0] TAMR +// +// GPT Timer A Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_TBMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TBCINTD +// +// One-Shot/Periodic Interrupt Mode +// ENUMs: +// DIS_TO_INTR Mask Time-Out Interrupt +// EN_TO_INTR Normal Time-Out Interrupt +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TBPLO +// +// GPTM Timer B PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TBILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TBILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 + +// Field: [10] TBMRSU +// +// Timer B Match Register Update mode +// +// This bit defines when the TBMATCHR and TBPR registers are updated +// +// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR +// and TBPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR +// and TBPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TBMATCHR and TBPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next +// cycle. +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TBPWMIE +// +// GPTM Timer B PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TBEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 + +// Field: [8] TBILD +// +// GPT Timer B PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TBR register with the value in the +// TBILR register on the next timeout. If the +// prescaler is used, update the TBPS register +// with the value in the TBPR register on the next +// timeout. +// CYCLEUPDATE Update the TBR register with the value in the +// TBILR register on the next clock cycle. If the +// pre-scaler is used, update the TBPS register +// with the value in the TBPR register on the next +// clock cycle. +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TBSNAPS +// +// GPT Timer B Snap-Shot Mode +// ENUMs: +// EN If Timer B is configured in the periodic mode +// DIS Snap-shot mode is disabled. +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 + +// Field: [6] TBWOT +// +// GPT Timer B Wait-On-Trigger +// ENUMs: +// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B +// does not begin counting until it receives a +// trigger from the timer in the previous position +// in the daisy chain. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer B begins counting as soon as it is enabled. +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 + +// Field: [5] TBMIE +// +// GPT Timer B Match Interrupt Enable. +// ENUMs: +// EN An interrupt is generated when the match value in +// the TBMATCHR register is reached in the +// one-shot and periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 + +// Field: [4] TBCDIR +// +// GPT Timer B Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 + +// Field: [3] TBAMS +// +// GPT Timer B Alternate Mode +// +// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 + +// Field: [2] TBCM +// +// GPT Timer B Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 + +// Field: [1:0] TBMR +// +// GPT Timer B Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_CTL +// +//***************************************************************************** +// Field: [14] TBPWML +// +// GPT Timer B PWM Output Level +// +// 0: Output is unaffected. +// 1: Output is inverted. +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 + +// Field: [11:10] TBEVENT +// +// GPT Timer B Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 + +// Field: [9] TBSTALL +// +// GPT Timer B Stall Enable +// ENUMs: +// EN Timer B freezes counting while the processor is +// halted by the debugger. +// DIS Timer B continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 + +// Field: [8] TBEN +// +// GPT Timer B Enable +// ENUMs: +// EN Timer B is enabled and begins counting or the +// capture logic is enabled based on CFG register. +// DIS Timer B is disabled. +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 + +// Field: [6] TAPWML +// +// GPT Timer A PWM Output Level +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 + +// Field: [3:2] TAEVENT +// +// GPT Timer A Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 + +// Field: [1] TASTALL +// +// GPT Timer A Stall Enable +// ENUMs: +// EN Timer A freezes counting while the processor is +// halted by the debugger. +// DIS Timer A continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 + +// Field: [0] TAEN +// +// GPT Timer A Enable +// ENUMs: +// EN Timer A is enabled and begins counting or the +// capture logic is enabled based on the CFG +// register. +// DIS Timer A is disabled. +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_SYNC +// +//***************************************************************************** +// Field: [7:6] SYNC3 +// +// Synchronize GPT Timer 3. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT3 is triggered +// TIMERB A timeout event for Timer B of GPT3 is triggered +// TIMERA A timeout event for Timer A of GPT3 is triggered +// NOSYNC No Sync. GPT3 is not affected. +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 + +// Field: [5:4] SYNC2 +// +// Synchronize GPT Timer 2. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT2 is triggered +// TIMERB A timeout event for Timer B of GPT2 is triggered +// TIMERA A timeout event for Timer A of GPT2 is triggered +// NOSYNC No Sync. GPT2 is not affected. +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 + +// Field: [3:2] SYNC1 +// +// Synchronize GPT Timer 1 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT1 is triggered +// TIMERB A timeout event for Timer B of GPT1 is triggered +// TIMERA A timeout event for Timer A of GPT1 is triggered +// NOSYNC No Sync. GPT1 is not affected. +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 + +// Field: [1:0] SYNC0 +// +// Synchronize GPT Timer 0 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT0 is triggered +// TIMERB A timeout event for Timer B of GPT0 is triggered +// TIMERA A timeout event for Timer A of GPT0 is triggered +// NOSYNC No Sync. GPT0 is not affected. +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_IMR +// +//***************************************************************************** +// Field: [13] DMABIM +// +// Enabling this bit will make the RIS.DMABRIS interrupt propagate to +// MIS.DMABMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 + +// Field: [11] TBMIM +// +// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 + +// Field: [10] CBEIM +// +// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 + +// Field: [9] CBMIM +// +// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 + +// Field: [8] TBTOIM +// +// Enabling this bit will make the RIS.TBTORIS interrupt propagate to +// MIS.TBTOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 + +// Field: [5] DMAAIM +// +// Enabling this bit will make the RIS.DMAARIS interrupt propagate to +// MIS.DMAAMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 + +// Field: [4] TAMIM +// +// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 + +// Field: [2] CAEIM +// +// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 + +// Field: [1] CAMIM +// +// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 + +// Field: [0] TATOIM +// +// Enabling this bit will make the RIS.TATORIS interrupt propagate to +// MIS.TATOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_RIS +// +//***************************************************************************** +// Field: [13] DMABRIS +// +// GPT Timer B DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 + +// Field: [11] TBMRIS +// +// GPT Timer B Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 + +// Field: [10] CBERIS +// +// GPT Timer B Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 + +// Field: [9] CBMRIS +// +// GPT Timer B Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer B has not occurred. +// 1: A capture mode match has occurred for Timer B. This interrupt +// asserts when the values in the TBR and TBPR +// match the values in the TBMATCHR and TBPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 + +// Field: [8] TBTORIS +// +// GPT Timer B Time-out Raw Interrupt +// +// 0: Timer B has not timed out +// 1: Timer B has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TBILR, +// depending on the count direction. +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 + +// Field: [5] DMAARIS +// +// GPT Timer A DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 + +// Field: [4] TAMRIS +// +// GPT Timer A Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 + +// Field: [2] CAERIS +// +// GPT Timer A Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 + +// Field: [1] CAMRIS +// +// GPT Timer A Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer A has not occurred. +// 1: A capture mode match has occurred for Timer A. This interrupt +// asserts when the values in the TAR and TAPR +// match the values in the TAMATCHR and TAPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 + +// Field: [0] TATORIS +// +// GPT Timer A Time-out Raw Interrupt +// +// 0: Timer A has not timed out +// 1: Timer A has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TAILR, +// depending on the count direction. +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_MIS +// +//***************************************************************************** +// Field: [13] DMABMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 + +// Field: [11] TBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 + +// Field: [10] CBEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 + +// Field: [9] CBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 + +// Field: [8] TBTOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 + +// Field: [5] DMAAMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 + +// Field: [4] TAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 + +// Field: [2] CAEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 + +// Field: [1] CAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 + +// Field: [0] TATOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ICLR +// +//***************************************************************************** +// Field: [13] DMABINT +// +// 0: Do nothing. +// 1: Clear RIS.DMABRIS and MIS.DMABMIS +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 + +// Field: [11] TBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBMRIS and MIS.TBMMIS +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 + +// Field: [10] CBECINT +// +// 0: Do nothing. +// 1: Clear RIS.CBERIS and MIS.CBEMIS +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 + +// Field: [9] CBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CBMRIS and MIS.CBMMIS +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 + +// Field: [8] TBTOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBTORIS and MIS.TBTOMIS +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 + +// Field: [5] DMAAINT +// +// 0: Do nothing. +// 1: Clear RIS.DMAARIS and MIS.DMAAMIS +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 + +// Field: [4] TAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TAMRIS and MIS.TAMMIS +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 + +// Field: [2] CAECINT +// +// 0: Do nothing. +// 1: Clear RIS.CAERIS and MIS.CAEMIS +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 + +// Field: [1] CAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CAMRIS and MIS.CAMMIS +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 + +// Field: [0] TATOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TATORIS and MIS.TATOMIS +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAILR +// +//***************************************************************************** +// Field: [31:0] TAILR +// +// GPT Timer A Interval Load Register +// +// Writing this field loads the counter for Timer A. A read returns the current +// value of TAILR. +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBILR +// +//***************************************************************************** +// Field: [31:0] TBILR +// +// GPT Timer B Interval Load Register +// +// Writing this field loads the counter for Timer B. A read returns the current +// value of TBILR. +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAMATCHR +// +//***************************************************************************** +// Field: [31:0] TAMATCHR +// +// GPT Timer A Match Register +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBMATCHR +// +//***************************************************************************** +// Field: [15:0] TBMATCHR +// +// GPT Timer B Match Register +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPR +// +//***************************************************************************** +// Field: [7:0] TAPSR +// +// Timer A Pre-scale. +// +// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPR +// +//***************************************************************************** +// Field: [7:0] TBPSR +// +// Timer B Pre-scale. +// +// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPMR +// +//***************************************************************************** +// Field: [7:0] TAPSMR +// +// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPMR +// +//***************************************************************************** +// Field: [7:0] TBPSMR +// +// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits +// 23 to 16. +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAR +// +//***************************************************************************** +// Field: [31:0] TAR +// +// GPT Timer A Register +// +// Based on the value in the register field TAMR.TAILD, this register is +// updated with the value from TAILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer A Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBR +// +//***************************************************************************** +// Field: [31:0] TBR +// +// GPT Timer B Register +// +// Based on the value in the register field TBMR.TBILD, this register is +// updated with the value from TBILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer B Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAV +// +//***************************************************************************** +// Field: [31:0] TAV +// +// GPT Timer A Register +// A read returns the current, free-running value of Timer A in all modes. +// When written, the value written into this register is loaded into the +// TAR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBV +// +//***************************************************************************** +// Field: [31:0] TBV +// +// GPT Timer B Register +// A read returns the current, free-running value of Timer B in all modes. +// When written, the value written into this register is loaded into the +// TBR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer A Pre-scaler +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer B Pre-scaler +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer A Pre-scaler Value +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer B Pre-scaler Value +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_DMAEV +// +//***************************************************************************** +// Field: [11] TBMDMAEN +// +// GPT Timer B Match DMA Trigger Enable +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 + +// Field: [10] CBEDMAEN +// +// GPT Timer B Capture Event DMA Trigger Enable +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 + +// Field: [9] CBMDMAEN +// +// GPT Timer B Capture Match DMA Trigger Enable +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 + +// Field: [8] TBTODMAEN +// +// GPT Timer B Time-Out DMA Trigger Enable +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 + +// Field: [4] TAMDMAEN +// +// GPT Timer A Match DMA Trigger Enable +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 + +// Field: [2] CAEDMAEN +// +// GPT Timer A Capture Event DMA Trigger Enable +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 + +// Field: [1] CAMDMAEN +// +// GPT Timer A Capture Match DMA Trigger Enable +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 + +// Field: [0] TATODMAEN +// +// GPT Timer A Time-Out DMA Trigger Enable +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 + +//***************************************************************************** +// +// Register: GPT_O_VERSION +// +//***************************************************************************** +// Field: [31:0] VERSION +// +// Timer Revision. +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ANDCCP +// +//***************************************************************************** +// Field: [0] CCP_AND_EN +// +// Enables AND operation of the CCP outputs for timers A and B. +// +// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM +// signals of the respective timers. +// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM +// signals and Timer B PWM ouput is Timer B PWM signal only. +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 + + +#endif // __GPT__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_i2c.h b/os/common/ext/TI/devices/cc13x0/inc/hw_i2c.h new file mode 100644 index 0000000000..926bd9673b --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_i2c.h @@ -0,0 +1,728 @@ +/****************************************************************************** +* Filename: hw_i2c_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2C component +// +//***************************************************************************** +// Slave Own Address +#define I2C_O_SOAR 0x00000000 + +// Slave Status +#define I2C_O_SSTAT 0x00000004 + +// Slave Control +#define I2C_O_SCTL 0x00000004 + +// Slave Data +#define I2C_O_SDR 0x00000008 + +// Slave Interrupt Mask +#define I2C_O_SIMR 0x0000000C + +// Slave Raw Interrupt Status +#define I2C_O_SRIS 0x00000010 + +// Slave Masked Interrupt Status +#define I2C_O_SMIS 0x00000014 + +// Slave Interrupt Clear +#define I2C_O_SICR 0x00000018 + +// Master Salve Address +#define I2C_O_MSA 0x00000800 + +// Master Status +#define I2C_O_MSTAT 0x00000804 + +// Master Control +#define I2C_O_MCTRL 0x00000804 + +// Master Data +#define I2C_O_MDR 0x00000808 + +// I2C Master Timer Period +#define I2C_O_MTPR 0x0000080C + +// Master Interrupt Mask +#define I2C_O_MIMR 0x00000810 + +// Master Raw Interrupt Status +#define I2C_O_MRIS 0x00000814 + +// Master Masked Interrupt Status +#define I2C_O_MMIS 0x00000818 + +// Master Interrupt Clear +#define I2C_O_MICR 0x0000081C + +// Master Configuration +#define I2C_O_MCR 0x00000820 + +//***************************************************************************** +// +// Register: I2C_O_SOAR +// +//***************************************************************************** +// Field: [6:0] OAR +// +// I2C slave own address +// This field specifies bits a6 through a0 of the slave address. +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SSTAT +// +//***************************************************************************** +// Field: [2] FBR +// +// First byte received +// +// 0: The first byte has not been received. +// 1: The first byte following the slave's own address has been received. +// +// This bit is only valid when the RREQ bit is set and is automatically cleared +// when data has been read from the SDR register. +// Note: This bit is not used for slave transmit operations. +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 + +// Field: [1] TREQ +// +// Transmit request +// +// 0: No outstanding transmit request. +// 1: The I2C controller has been addressed as a slave transmitter and is using +// clock stretching to delay the master until data has been written to the SDR +// register. +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 + +// Field: [0] RREQ +// +// Receive request +// +// 0: No outstanding receive data +// 1: The I2C controller has outstanding receive data from the I2C master and +// is using clock stretching to delay the master until data has been read from +// the SDR register. +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SCTL +// +//***************************************************************************** +// Field: [0] DA +// +// Device active +// +// 0: Disables the I2C slave operation +// 1: Enables the I2C slave operation +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data for transfer +// This field contains the data for transfer during a slave receive or transmit +// operation. When written the register data is used as transmit data. When +// read, this register returns the last data received. +// Data is stored until next update, either by a system write for transmit or +// by an external master for receive. +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SIMR +// +//***************************************************************************** +// Field: [2] STOPIM +// +// Stop condition interrupt mask +// +// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 + +// Field: [1] STARTIM +// +// Start condition interrupt mask +// +// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 + +// Field: [0] DATAIM +// +// Data interrupt mask +// +// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt +// controller. +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SRIS +// +//***************************************************************************** +// Field: [2] STOPRIS +// +// Stop condition raw interrupt status +// +// 0: No interrupt +// 1: A Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STOPIC. +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 + +// Field: [1] STARTRIS +// +// Start condition raw interrupt status +// +// 0: No interrupt +// 1: A Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STARTIC. +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 + +// Field: [0] DATARIS +// +// Data raw interrupt status +// +// 0: No interrupt +// 1: A data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SMIS +// +//***************************************************************************** +// Field: [2] STOPMIS +// +// Stop condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STOPIC. +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 + +// Field: [1] STARTMIS +// +// Start condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STARTIC. +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 + +// Field: [0] DATAMIS +// +// Data masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SICR +// +//***************************************************************************** +// Field: [2] STOPIC +// +// Stop condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 + +// Field: [1] STARTIC +// +// Start condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 + +// Field: [0] DATAIC +// +// Data interrupt clear +// +// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MSA +// +//***************************************************************************** +// Field: [7:1] SA +// +// I2C master slave address +// Defines which slave is addressed for the transaction in master mode +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 + +// Field: [0] RS +// +// Receive or Send +// This bit-field specifies if the next operation is a receive (high) or a +// transmit/send (low) from the addressed slave SA. +// ENUMs: +// RX Receive data from slave +// TX Transmit/send data to slave +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MSTAT +// +//***************************************************************************** +// Field: [6] BUSBSY +// +// Bus busy +// +// 0: The I2C bus is idle. +// 1: The I2C bus is busy. +// +// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 + +// Field: [5] IDLE +// +// I2C idle +// +// 0: The I2C controller is not idle. +// 1: The I2C controller is idle. +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 + +// Field: [4] ARBLST +// +// Arbitration lost +// +// 0: The I2C controller won arbitration. +// 1: The I2C controller lost arbitration. +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 + +// Field: [3] DATACK_N +// +// Data Was Not Acknowledge +// +// 0: The transmitted data was acknowledged. +// 1: The transmitted data was not acknowledged. +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 + +// Field: [2] ADRACK_N +// +// Address Was Not Acknowledge +// +// 0: The transmitted address was acknowledged. +// 1: The transmitted address was not acknowledged. +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 + +// Field: [1] ERR +// +// Error +// +// 0: No error was detected on the last operation. +// 1: An error occurred on the last operation. +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 + +// Field: [0] BUSY +// +// I2C busy +// +// 0: The controller is idle. +// 1: The controller is busy. +// +// When this bit-field is set, the other status bits are not valid. +// +// Note: The I2C controller requires four SYSBUS clock cycles to assert the +// BUSY status after I2C master operation has been initiated through MCTRL +// register. +// Hence after programming MCTRL register, application is requested to wait for +// four SYSBUS clock cycles before issuing a controller status inquiry through +// MSTAT register. +// Any prior inquiry would result in wrong status being reported. +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCTRL +// +//***************************************************************************** +// Field: [3] ACK +// +// Data acknowledge enable +// +// 0: The received data byte is not acknowledged automatically by the master. +// 1: The received data byte is acknowledged automatically by the master. +// +// This bit-field must be cleared when the I2C bus controller requires no +// further data to be transmitted from the slave transmitter. +// ENUMs: +// EN Enable acknowledge +// DIS Disable acknowledge +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 + +// Field: [2] STOP +// +// This bit-field determines if the cycle stops at the end of the data cycle or +// continues on to a repeated START condition. +// +// 0: The controller does not generate the Stop condition. +// 1: The controller generates the Stop condition. +// ENUMs: +// EN Enable STOP +// DIS Disable STOP +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 + +// Field: [1] START +// +// This bit-field generates the Start or Repeated Start condition. +// +// 0: The controller does not generate the Start condition. +// 1: The controller generates the Start condition. +// ENUMs: +// EN Enable START +// DIS Disable START +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 + +// Field: [0] RUN +// +// I2C master enable +// +// 0: The master is disabled. +// 1: The master is enabled to transmit or receive data. +// ENUMs: +// EN Enable Master +// DIS Disable Master +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// When Read: Last RX Data is returned +// When Written: Data is transferred during TX transaction +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MTPR +// +//***************************************************************************** +// Field: [7] TPR_7 +// +// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 + +// Field: [6:0] TPR +// +// SCL clock period +// This field specifies the period of the SCL clock. +// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD +// where: +// SCL_PRD is the SCL line period (I2C clock). +// TPR is the timer period register value (range of 1 to 127) +// SCL_LP is the SCL low period (fixed at 6). +// SCL_HP is the SCL high period (fixed at 4). +// CLK_PRD is the system clock period in ns. +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MIMR +// +//***************************************************************************** +// Field: [0] IM +// +// Interrupt mask +// +// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The master interrupt is sent to the interrupt controller when the +// MRIS.RIS is set. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MRIS +// +//***************************************************************************** +// Field: [0] RIS +// +// Raw interrupt status +// +// 0: No interrupt +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MMIS +// +//***************************************************************************** +// Field: [0] MIS +// +// Masked interrupt status +// +// 0: An interrupt has not occurred or is masked. +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MICR +// +//***************************************************************************** +// Field: [0] IC +// +// Interrupt clear +// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . +// +// Reading this register returns no meaningful data. +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCR +// +//***************************************************************************** +// Field: [5] SFE +// +// I2C slave function enable +// ENUMs: +// EN Slave mode is enabled. +// DIS Slave mode is disabled. +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 + +// Field: [4] MFE +// +// I2C master function enable +// ENUMs: +// EN Master mode is enabled. +// DIS Master mode is disabled. +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 + +// Field: [0] LPBK +// +// I2C loopback +// +// 0: Normal operation +// 1: Loopback operation (test mode) +// ENUMs: +// EN Enable Test Mode +// DIS Disable Test Mode +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 + + +#endif // __I2C__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_i2s.h b/os/common/ext/TI/devices/cc13x0/inc/hw_i2s.h new file mode 100644 index 0000000000..8c774b06ef --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_i2s.h @@ -0,0 +1,967 @@ +/****************************************************************************** +* Filename: hw_i2s_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2S_H__ +#define __HW_I2S_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2S component +// +//***************************************************************************** +// WCLK Source Selection +#define I2S_O_AIFWCLKSRC 0x00000000 + +// DMA Buffer Size Configuration +#define I2S_O_AIFDMACFG 0x00000004 + +// Pin Direction +#define I2S_O_AIFDIRCFG 0x00000008 + +// Serial Interface Format Configuration +#define I2S_O_AIFFMTCFG 0x0000000C + +// Word Selection Bit Mask for Pin 0 +#define I2S_O_AIFWMASK0 0x00000010 + +// Word Selection Bit Mask for Pin 1 +#define I2S_O_AIFWMASK1 0x00000014 + +// Audio Interface PWM Debug Value +#define I2S_O_AIFPWMVALUE 0x0000001C + +// DMA Input Buffer Next Pointer +#define I2S_O_AIFINPTRNEXT 0x00000020 + +// DMA Input Buffer Current Pointer +#define I2S_O_AIFINPTR 0x00000024 + +// DMA Output Buffer Next Pointer +#define I2S_O_AIFOUTPTRNEXT 0x00000028 + +// DMA Output Buffer Current Pointer +#define I2S_O_AIFOUTPTR 0x0000002C + +// Samplestamp Generator Control Register +#define I2S_O_STMPCTL 0x00000034 + +// Captured XOSC Counter Value, Capture Channel 0 +#define I2S_O_STMPXCNTCAPT0 0x00000038 + +// XOSC Period Value +#define I2S_O_STMPXPER 0x0000003C + +// Captured WCLK Counter Value, Capture Channel 0 +#define I2S_O_STMPWCNTCAPT0 0x00000040 + +// WCLK Counter Period Value +#define I2S_O_STMPWPER 0x00000044 + +// WCLK Counter Trigger Value for Input Pins +#define I2S_O_STMPINTRIG 0x00000048 + +// WCLK Counter Trigger Value for Output Pins +#define I2S_O_STMPOUTTRIG 0x0000004C + +// WCLK Counter Set Operation +#define I2S_O_STMPWSET 0x00000050 + +// WCLK Counter Add Operation +#define I2S_O_STMPWADD 0x00000054 + +// XOSC Minimum Period Value +#define I2S_O_STMPXPERMIN 0x00000058 + +// Current Value of WCNT +#define I2S_O_STMPWCNT 0x0000005C + +// Current Value of XCNT +#define I2S_O_STMPXCNT 0x00000060 + +// Internal +#define I2S_O_STMPXCNTCAPT1 0x00000064 + +// Internal +#define I2S_O_STMPWCNTCAPT1 0x00000068 + +// Interrupt Mask Register +#define I2S_O_IRQMASK 0x00000070 + +// Raw Interrupt Status Register +#define I2S_O_IRQFLAGS 0x00000074 + +// Interrupt Set Register +#define I2S_O_IRQSET 0x00000078 + +// Interrupt Clear Register +#define I2S_O_IRQCLR 0x0000007C + +//***************************************************************************** +// +// Register: I2S_O_AIFWCLKSRC +// +//***************************************************************************** +// Field: [2] WCLK_INV +// +// Inverts WCLK source (pad or internal) when set. +// +// 0: Not inverted +// 1: Inverted +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 + +// Field: [1:0] WCLK_SRC +// +// Selects WCLK source for AIF (should be the same as the BCLK source). The +// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC +// ENUMs: +// RESERVED Not supported. Will give same WCLK as 'NONE' +// ('00') +// INT Internal WCLK generator, from module PRCM +// EXT External WCLK generator, from pad +// NONE None ('0') +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFDMACFG +// +//***************************************************************************** +// Field: [7:0] END_FRAME_IDX +// +// Defines the length of the DMA buffer. Writing a non-zero value to this +// register field enables and initializes AIF. Note that before doing so, all +// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must +// have been loaded. +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFDIRCFG +// +//***************************************************************************** +// Field: [5:4] AD1 +// +// Configures the AD1 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 + +// Field: [1:0] AD0 +// +// Configures the AD0 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFFMTCFG +// +//***************************************************************************** +// Field: [15:8] DATA_DELAY +// +// The number of BCLK periods between a WCLK edge and MSB of the first word in +// a phase: +// +// 0x00: LJF and DSP format +// 0x01: I2S and DSP format +// 0x02: RJF format +// ... +// 0xFF: RJF format +// +// Note: When 0, MSB of the next word will be output in the idle period between +// LSB of the previous word and the start of the next word. Otherwise logical 0 +// will be output until the data delay has expired. +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 + +// Field: [7] MEM_LEN_24 +// +// The size of each word stored to or loaded from memory: +// ENUMs: +// 24BIT 24-bit (one 8 bit and one 16 bit locked access per +// sample) +// 16BIT 16-bit (one 16 bit access per sample) +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 + +// Field: [6] SMPL_EDGE +// +// On the serial audio interface, data (and wclk) is sampled and clocked out on +// opposite edges of BCLK. +// ENUMs: +// POS Data is sampled on the positive edge and clocked +// out on the negative edge. +// NEG Data is sampled on the negative edge and clocked +// out on the positive edge. +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 + +// Field: [5] DUAL_PHASE +// +// Selects dual- or single-phase format. +// +// 0: Single-phase: DSP format +// 1: Dual-phase: I2S, LJF and RJF formats +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 + +// Field: [4:0] WORD_LEN +// +// Number of bits per word (8-24): +// In single-phase format, this is the exact number of bits per word. +// In dual-phase format, this is the maximum number of bits per word. +// +// Values below 8 and above 24 give undefined behavior. Data written to memory +// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that +// differ from this alignment will either be truncated or zero padded. +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK0 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD0. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK1 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD1. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFPWMVALUE +// +//***************************************************************************** +// Field: [15:0] PULSE_WIDTH +// +// The value written to this register determines the width of the active high +// PWM pulse (pwm_debug), which starts together with MSB of the first output +// word in a DMA buffer: +// +// 0x0000: Constant low +// 0x0001: Width of the pulse (number of BCLK cycles, here 1). +// ... +// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). +// 0xFFFF: Constant high +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA input buffer. +// +// The read value equals the last written value until the currently used DMA +// input buffer is completed, and then becomes null when the last written value +// is transferred to the DMA controller to start on the next buffer. This event +// is signalized by IRQFLAGS.AIF_DMA_IN. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA input buffer pointer currently used by the DMA controller. +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA output buffer. +// +// The read value equals the last written value until the currently used DMA +// output buffer is completed, and then becomes null when the last written +// value is transferred to the DMA controller to start on the next buffer. This +// event is signalized by IRQFLAGS.AIF_DMA_OUT. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. At this time, the first two samples will +// be fetched from memory. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA output buffer pointer currently used by the DMA controller +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPCTL +// +//***************************************************************************** +// Field: [2] OUT_RDY +// +// Low until the output pins are ready to be started by the samplestamp +// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the +// bit goes back low. +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 + +// Field: [1] IN_RDY +// +// Low until the input pins are ready to be started by the samplestamp +// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit +// goes back low. +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 + +// Field: [0] STMP_EN +// +// Enables the samplestamp generator. The samplestamp generator must only be +// enabled after it has been properly configured. +// When cleared, all samplestamp generator counters and capture values are +// cleared. +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for +// channel 0). This number corresponds to the number of 24 MHz clock cycles +// since the last positive edge of the selected WCLK. +// The value is cleared when STMPCTL.STMP_EN = 0. +// Note: Due to buffering and synchronization, WCLK is delayed by a small +// number of BCLK periods and clk periods. +// Note: When calculating the fractional part of the sample stamp, STMPXPER may +// be less than this bit field. +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// The number of 24 MHz clock cycles in the previous WCLK period (that is - +// the next value of the XOSC counter at the positive WCLK edge, had it not +// been reset to 0). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel +// 0). This number corresponds to the number of positive WCLK edges since the +// samplestamp generator was enabled (not taking modification through +// STMPWADD/STMPWSET into account). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Used to define when STMPWCNT is to be reset so number of WCLK edges are +// found for the size of the sample buffer. This is thus a modulo value for the +// WCLK counter. This number must correspond to the size of the sample buffer +// used by the system (that is the index of the last sample plus 1). +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPINTRIG +// +//***************************************************************************** +// Field: [15:0] IN_START_WCNT +// +// Compare value used to start the incoming audio streams. +// This bit field shall equal the WCLK counter value during the WCLK period in +// which the first input word(s) are sampled and stored to memory (that is the +// sample at the start of the very first DMA input buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as inputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and at least 32 +// BCLK cycle ticks have happened. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPOUTTRIG +// +//***************************************************************************** +// Field: [15:0] OUT_START_WCNT +// +// Compare value used to start the outgoing audio streams. +// +// This bit field must equal the WCLK counter value during the WCLK period in +// which the first output word(s) read from memory are clocked out (that is the +// sample at the start of the very first DMA output buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as outputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK +// cycle ticks have happened. +// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register +// if necessary). +// Note: The memory read access is only performed when required, that is +// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWSET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// WCLK counter modification: Sets the running WCLK counter equal to the +// written value. +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWADD +// +//***************************************************************************** +// Field: [15:0] VALUE_INC +// +// WCLK counter modification: Adds the written value to the running WCLK +// counter. If a positive edge of WCLK occurs at the same time as the +// operation, this will be taken into account. +// To add a negative value, write "STMPWPER.VALUE - value". +// +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPERMIN +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Each time STMPXPER is updated, the value is also loaded into this register, +// provided that the value is smaller than the current value in this register. +// When written, the register is reset to 0xFFFF (65535), regardless of the +// value written. +// The minimum value can be used to detect extra WCLK pulses (this registers +// value will be significantly smaller than STMPXPER.VALUE). +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the WCLK counter +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the XOSC counter, latched when reading STMPWCNT. +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQMASK +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// IRQFLAGS.AIF_DMA_IN interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// IRQFLAGS.AIF_DMA_OUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// IRQFLAGS.WCLK_TIMEOUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// IRQFLAGS.BUS_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// IRQFLAGS.WCLK_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// IRQFLAGS.PTR_ERR interrupt mask. +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQFLAGS +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// Set when condition for this bit field event occurs (auto cleared when input +// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register +// for details. +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// Set when condition for this bit field event occurs (auto cleared when output +// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT +// register for details +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// Set when the sample stamp generator does not detect a positive WCLK edge for +// 65535 clk periods. This signalizes that the internal or external BCLK and +// WCLK generator source has been disabled. +// +// The bit is sticky and may only be cleared by software (by writing '1' to +// IRQCLR.WCLK_TIMEOUT). +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// Set when a DMA operation is not completed in time (that is audio output +// buffer underflow, or audio input buffer overflow). +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.BUS_ERR). +// +// Note that DMA initiated transactions to illegal addresses will not trigger +// an interrupt. The response to such transactions is undefined. +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// Set when: +// - An unexpected WCLK edge occurs during the data delay period of a phase. +// Note unexpected WCLK edges during the word and idle periods of the phase are +// not detected. +// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles +// apart. +// - In single-phase mode, when a WCLK pulse occurs before the last channel. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.WCLK_ERR). +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next +// block address in time. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.PTR_ERR). +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQSET +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Sets the interrupt of IRQFLAGS.BUS_ERR +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Sets the interrupt of IRQFLAGS.PTR_ERR +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQCLR +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 + + +#endif // __I2S__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ints.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ints.h new file mode 100644 index 0000000000..051969edba --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ints.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* Filename: hw_ints_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) + // Fault +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the + // System Timer in NVIC. +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE + // Generated events +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE + // Generated events +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command + // Acknowledgement Interrupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt + // event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event + +//***************************************************************************** +// +// The following are defines for number of interrupts and priority levels. +// +//***************************************************************************** +#define NUM_INTERRUPTS 50 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels + + +//***************************************************************************** +// +// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 +// +//***************************************************************************** + +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 + +#endif diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ioc.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ioc.h new file mode 100644 index 0000000000..07cf8d9f1e --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ioc.h @@ -0,0 +1,11951 @@ +/****************************************************************************** +* Filename: hw_ioc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_IOC_H__ +#define __HW_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// IOC component +// +//***************************************************************************** +// Configuration of DIO0 +#define IOC_O_IOCFG0 0x00000000 + +// Configuration of DIO1 +#define IOC_O_IOCFG1 0x00000004 + +// Configuration of DIO2 +#define IOC_O_IOCFG2 0x00000008 + +// Configuration of DIO3 +#define IOC_O_IOCFG3 0x0000000C + +// Configuration of DIO4 +#define IOC_O_IOCFG4 0x00000010 + +// Configuration of DIO5 +#define IOC_O_IOCFG5 0x00000014 + +// Configuration of DIO6 +#define IOC_O_IOCFG6 0x00000018 + +// Configuration of DIO7 +#define IOC_O_IOCFG7 0x0000001C + +// Configuration of DIO8 +#define IOC_O_IOCFG8 0x00000020 + +// Configuration of DIO9 +#define IOC_O_IOCFG9 0x00000024 + +// Configuration of DIO10 +#define IOC_O_IOCFG10 0x00000028 + +// Configuration of DIO11 +#define IOC_O_IOCFG11 0x0000002C + +// Configuration of DIO12 +#define IOC_O_IOCFG12 0x00000030 + +// Configuration of DIO13 +#define IOC_O_IOCFG13 0x00000034 + +// Configuration of DIO14 +#define IOC_O_IOCFG14 0x00000038 + +// Configuration of DIO15 +#define IOC_O_IOCFG15 0x0000003C + +// Configuration of DIO16 +#define IOC_O_IOCFG16 0x00000040 + +// Configuration of DIO17 +#define IOC_O_IOCFG17 0x00000044 + +// Configuration of DIO18 +#define IOC_O_IOCFG18 0x00000048 + +// Configuration of DIO19 +#define IOC_O_IOCFG19 0x0000004C + +// Configuration of DIO20 +#define IOC_O_IOCFG20 0x00000050 + +// Configuration of DIO21 +#define IOC_O_IOCFG21 0x00000054 + +// Configuration of DIO22 +#define IOC_O_IOCFG22 0x00000058 + +// Configuration of DIO23 +#define IOC_O_IOCFG23 0x0000005C + +// Configuration of DIO24 +#define IOC_O_IOCFG24 0x00000060 + +// Configuration of DIO25 +#define IOC_O_IOCFG25 0x00000064 + +// Configuration of DIO26 +#define IOC_O_IOCFG26 0x00000068 + +// Configuration of DIO27 +#define IOC_O_IOCFG27 0x0000006C + +// Configuration of DIO28 +#define IOC_O_IOCFG28 0x00000070 + +// Configuration of DIO29 +#define IOC_O_IOCFG29 0x00000074 + +// Configuration of DIO30 +#define IOC_O_IOCFG30 0x00000078 + +// Configuration of DIO31 +#define IOC_O_IOCFG31 0x0000007C + +//***************************************************************************** +// +// Register: IOC_O_IOCFG0 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input/output +// OPENSRC Open Source +// Normal input / outut +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO0 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG1 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO1 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG2 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO2 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG3 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO3 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG4 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO4 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG5 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO5 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG6 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO6 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG7 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO7 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG8 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO8 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG9 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO9 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG10 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO10 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG11 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO11 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG12 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO12 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG13 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO13 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG14 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO14 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG15 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO15 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG16 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO16 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG17 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO17 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG18 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO18 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG19 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO19 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG20 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO20 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG21 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO21 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG22 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO22 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG23 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO23 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG24 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO24 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG25 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO25 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG26 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO26 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG27 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO27 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG28 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO28 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG29 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO29 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG30 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO30 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG31 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO31 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 + + +#endif // __IOC__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_memmap.h b/os/common/ext/TI/devices/cc13x0/inc/hw_memmap.h new file mode 100644 index 0000000000..2873083d6b --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_memmap.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* Filename: hw_memmap_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the CPU_MMAP interface +// +//***************************************************************************** +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL +#define AON_WUC_BASE 0x40091000 // AON_WUC +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_WUC_BASE 0x400C6000 // AUX_WUC +#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 +#ifndef CCFG_BASE +#define CCFG_BASE 0x50003000 // CCFG +#endif +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base +#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define AUX_AIODIO0_NONBUF_BASE \ + 0x600C1000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO1_NONBUF_BASE \ + 0x600C2000 // AUX_AIODIO CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base +#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base +#define AUX_DDI0_OSC_NONBUF_BASE \ + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + +#endif // __HW_MEMMAP__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_nvic.h b/os/common/ext/TI/devices/cc13x0/inc/hw_nvic.h new file mode 100644 index 0000000000..cba36e3e4d --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_nvic.h @@ -0,0 +1,1026 @@ +/****************************************************************************** +* Filename: hw_nvic.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_prcm.h b/os/common/ext/TI/devices/cc13x0/inc/hw_prcm.h new file mode 100644 index 0000000000..f3a773f947 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_prcm.h @@ -0,0 +1,1636 @@ +/****************************************************************************** +* Filename: hw_prcm_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PRCM_H__ +#define __HW_PRCM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PRCM component +// +//***************************************************************************** +// Infrastructure Clock Division Factor For Run Mode +#define PRCM_O_INFRCLKDIVR 0x00000000 + +// Infrastructure Clock Division Factor For Sleep Mode +#define PRCM_O_INFRCLKDIVS 0x00000004 + +// Infrastructure Clock Division Factor For DeepSleep Mode +#define PRCM_O_INFRCLKDIVDS 0x00000008 + +// MCU Voltage Domain Control +#define PRCM_O_VDCTL 0x0000000C + +// Load PRCM Settings To CLKCTRL Power Domain +#define PRCM_O_CLKLOADCTL 0x00000028 + +// RFC Clock Gate +#define PRCM_O_RFCCLKG 0x0000002C + +// VIMS Clock Gate +#define PRCM_O_VIMSCLKG 0x00000030 + +// TRNG, CRYPTO And UDMA Clock Gate For Run Mode +#define PRCM_O_SECDMACLKGR 0x0000003C + +// TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode +#define PRCM_O_SECDMACLKGS 0x00000040 + +// TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode +#define PRCM_O_SECDMACLKGDS 0x00000044 + +// GPIO Clock Gate For Run Mode +#define PRCM_O_GPIOCLKGR 0x00000048 + +// GPIO Clock Gate For Sleep Mode +#define PRCM_O_GPIOCLKGS 0x0000004C + +// GPIO Clock Gate For Deep Sleep Mode +#define PRCM_O_GPIOCLKGDS 0x00000050 + +// GPT Clock Gate For Run Mode +#define PRCM_O_GPTCLKGR 0x00000054 + +// GPT Clock Gate For Sleep Mode +#define PRCM_O_GPTCLKGS 0x00000058 + +// GPT Clock Gate For Deep Sleep Mode +#define PRCM_O_GPTCLKGDS 0x0000005C + +// I2C Clock Gate For Run Mode +#define PRCM_O_I2CCLKGR 0x00000060 + +// I2C Clock Gate For Sleep Mode +#define PRCM_O_I2CCLKGS 0x00000064 + +// I2C Clock Gate For Deep Sleep Mode +#define PRCM_O_I2CCLKGDS 0x00000068 + +// UART Clock Gate For Run Mode +#define PRCM_O_UARTCLKGR 0x0000006C + +// UART Clock Gate For Sleep Mode +#define PRCM_O_UARTCLKGS 0x00000070 + +// UART Clock Gate For Deep Sleep Mode +#define PRCM_O_UARTCLKGDS 0x00000074 + +// SSI Clock Gate For Run Mode +#define PRCM_O_SSICLKGR 0x00000078 + +// SSI Clock Gate For Sleep Mode +#define PRCM_O_SSICLKGS 0x0000007C + +// SSI Clock Gate For Deep Sleep Mode +#define PRCM_O_SSICLKGDS 0x00000080 + +// I2S Clock Gate For Run Mode +#define PRCM_O_I2SCLKGR 0x00000084 + +// I2S Clock Gate For Sleep Mode +#define PRCM_O_I2SCLKGS 0x00000088 + +// I2S Clock Gate For Deep Sleep Mode +#define PRCM_O_I2SCLKGDS 0x0000008C + +// Internal +#define PRCM_O_CPUCLKDIV 0x000000B8 + +// I2S Clock Control +#define PRCM_O_I2SBCLKSEL 0x000000C8 + +// GPT Scalar +#define PRCM_O_GPTCLKDIV 0x000000CC + +// I2S Clock Control +#define PRCM_O_I2SCLKCTL 0x000000D0 + +// MCLK Division Ratio +#define PRCM_O_I2SMCLKDIV 0x000000D4 + +// BCLK Division Ratio +#define PRCM_O_I2SBCLKDIV 0x000000D8 + +// WCLK Division Ratio +#define PRCM_O_I2SWCLKDIV 0x000000DC + +// SW Initiated Resets +#define PRCM_O_SWRESET 0x0000010C + +// WARM Reset Control And Status +#define PRCM_O_WARMRESET 0x00000110 + +// Power Domain Control +#define PRCM_O_PDCTL0 0x0000012C + +// RFC Power Domain Control +#define PRCM_O_PDCTL0RFC 0x00000130 + +// SERIAL Power Domain Control +#define PRCM_O_PDCTL0SERIAL 0x00000134 + +// PERIPH Power Domain Control +#define PRCM_O_PDCTL0PERIPH 0x00000138 + +// Power Domain Status +#define PRCM_O_PDSTAT0 0x00000140 + +// RFC Power Domain Status +#define PRCM_O_PDSTAT0RFC 0x00000144 + +// SERIAL Power Domain Status +#define PRCM_O_PDSTAT0SERIAL 0x00000148 + +// PERIPH Power Domain Status +#define PRCM_O_PDSTAT0PERIPH 0x0000014C + +// Power Domain Control +#define PRCM_O_PDCTL1 0x0000017C + +// CPU Power Domain Direct Control +#define PRCM_O_PDCTL1CPU 0x00000184 + +// RFC Power Domain Direct Control +#define PRCM_O_PDCTL1RFC 0x00000188 + +// VIMS Mode Direct Control +#define PRCM_O_PDCTL1VIMS 0x0000018C + +// Power Manager Status +#define PRCM_O_PDSTAT1 0x00000194 + +// BUS Power Domain Direct Read Status +#define PRCM_O_PDSTAT1BUS 0x00000198 + +// RFC Power Domain Direct Read Status +#define PRCM_O_PDSTAT1RFC 0x0000019C + +// CPU Power Domain Direct Read Status +#define PRCM_O_PDSTAT1CPU 0x000001A0 + +// VIMS Mode Direct Read Status +#define PRCM_O_PDSTAT1VIMS 0x000001A4 + +// Control To RFC +#define PRCM_O_RFCBITS 0x000001CC + +// Selected RFC Mode +#define PRCM_O_RFCMODESEL 0x000001D0 + +// Allowed RFC Modes +#define PRCM_O_RFCMODEHWOPT 0x000001D4 + +// Power Profiler Register +#define PRCM_O_PWRPROFSTAT 0x000001E0 + +// Memory Retention Control +#define PRCM_O_RAMRETEN 0x00000224 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVR +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in run mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in sleep mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVDS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in seepsleep mode. Division ratio affects both infrastructure clock +// and perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_VDCTL +// +//***************************************************************************** +// Field: [2] MCU_VD +// +// Request WUC to power down the MCU voltage domain +// +// 0: No request +// 1: Assert request when possible. An asserted power down request will result +// in a boot of the MCU system when powered up again. +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = 0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 5. RFC do no request access to BUS +// 6. System CPU in deepsleep +#define PRCM_VDCTL_MCU_VD 0x00000004 +#define PRCM_VDCTL_MCU_VD_BITN 2 +#define PRCM_VDCTL_MCU_VD_M 0x00000004 +#define PRCM_VDCTL_MCU_VD_S 2 + +// Field: [0] ULDO +// +// Request WUC to switch to uLDO. +// +// 0: No request +// 1: Assert request when possible +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = 0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 5. RFC do no request access to BUS +// 6. System CPU in deepsleep +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CLKLOADCTL +// +//***************************************************************************** +// Field: [1] LOAD_DONE +// +// Status of LOAD. +// Will be cleared to 0 when any of the registers requiring a LOAD is written +// to, and be set to 1 when a LOAD is done. +// Note that writing no change to a register will result in the LOAD_DONE being +// cleared. +// +// 0 : One or more registers have been write accessed after last LOAD +// 1 : No registers are write accessed after last LOAD +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 + +// Field: [0] LOAD +// +// 0: No action +// 1: Load settings to CLKCTRL. Bit is HW cleared. +// +// Multiple changes to settings may be done before LOAD is written once so all +// changes takes place at the same time. LOAD can also be done after single +// setting updates. +// +// Registers that needs to be followed by LOAD before settings being applied +// are: +// - RFCCLKG +// - VIMSCLKG +// - SECDMACLKGR +// - SECDMACLKGS +// - SECDMACLKGDS +// - GPIOCLKGR +// - GPIOCLKGS +// - GPIOCLKGDS +// - GPTCLKGR +// - GPTCLKGS +// - GPTCLKGDS +// - GPTCLKDIV +// - I2CCLKGR +// - I2CCLKGS +// - I2CCLKGDS +// - SSICLKGR +// - SSICLKGS +// - SSICLKGDS +// - UARTCLKGR +// - UARTCLKGS +// - UARTCLKGDS +// - I2SCLKGR +// - I2SCLKGS +// - I2SCLKGDS +// - I2SBCLKSEL +// - I2SCLKCTL +// - I2SMCLKDIV +// - I2SBCLKDIV +// - I2SWCLKDIV +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCCLKG +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock if RFC power domain is on +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_VIMSCLKG +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 00: Disable clock +// 01: Disable clock when system CPU is in DeepSleep +// 11: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGR +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGDS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGR +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGDS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGR_CLK_EN 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_BITN 0 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGR +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CPUCLKDIV +// +//***************************************************************************** +// Field: [0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKSEL +// +//***************************************************************************** +// Field: [0] SRC +// +// BCLK source selector +// +// 0: Use external BCLK +// 1: Use internally generated clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Scalar used for GPTs. The division rate will be constant and ungated for Run +// / Sleep / DeepSleep mode. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// Other values are not supported. +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKCTL +// +//***************************************************************************** +// Field: [3] SMPL_ON_POSEDGE +// +// On the I2S serial interface, data and WCLK is sampled and clocked out on +// opposite edges of BCLK. +// +// 0 - data and WCLK are sampled on the negative edge and clocked out on the +// positive edge. +// 1 - data and WCLK are sampled on the positive edge and clocked out on the +// negative edge. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 + +// Field: [2:1] WCLK_PHASE +// +// Decides how the WCLK division ratio is calculated and used to generate +// different duty cycles (See I2SWCLKDIV.WDIV). +// +// 0: Single phase +// 1: Dual phase +// 2: User Defined +// 3: Reserved/Undefined +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 + +// Field: [0] EN +// +// +// 0: MCLK, BCLK and WCLK will be static low +// 1: Enables the generation of MCLK, BCLK and WCLK +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SMCLKDIV +// +//***************************************************************************** +// Field: [9:0] MDIV +// +// An unsigned factor of the division ratio used to generate MCLK [2-1024]: +// +// MCLK = MCUCLK/MDIV[Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If MDIV is odd the low phase of the clock is one MCUCLK period longer than +// the high phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKDIV +// +//***************************************************************************** +// Field: [9:0] BDIV +// +// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: +// +// BCLK = MCUCLK/BDIV[Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock +// is one MCUCLK period longer than the high phase. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the +// clock is one MCUCLK period longer than the low phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SWCLKDIV +// +//***************************************************************************** +// Field: [15:0] WDIV +// +// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. +// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. +// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] +// +// If I2SCLKCTL.WCLK_PHASE = 2, User defined. +// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] +// (unsigned, [1-255]) BCLK periods. +// +// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SWRESET +// +//***************************************************************************** +// Field: [2] MCU +// +// Internal. Only to be used through TI provided API. +#define PRCM_SWRESET_MCU 0x00000004 +#define PRCM_SWRESET_MCU_BITN 2 +#define PRCM_SWRESET_MCU_M 0x00000004 +#define PRCM_SWRESET_MCU_S 2 + +//***************************************************************************** +// +// Register: PRCM_O_WARMRESET +// +//***************************************************************************** +// Field: [2] WR_TO_PINRESET +// +// 0: No action +// 1: A warm system reset event triggered by the below listed sources will +// result in an emulated pin reset. +// +// Warm reset sources included: +// ICEPick sysreset +// System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ +// System CPU Lockup +// WDT timeout +// +// An active ICEPick block system reset will gate all sources except ICEPick +// sysreset +// +// SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the last +// reset resulting in a full power up sequence. WARMRESET in this register is +// set in the scenario that WR_TO_PINRESET=1 and one of the above listed +// sources is triggered. +#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 +#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 + +// Field: [1] LOCKUP_STAT +// +// +// 0: No registred event +// 1: A system CPU LOCKUP event has occured since last SW clear of the +// register. +// +// A read of this register clears both WDT_STAT and LOCKUP_STAT. +#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 +#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_S 1 + +// Field: [0] WDT_STAT +// +// +// 0: No registered event +// 1: A WDT event has occured since last SW clear of the register. +// +// A read of this register clears both WDT_STAT and LOCKUP_STAT. +#define PRCM_WARMRESET_WDT_STAT 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_BITN 0 +#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: PERIPH power domain is powered down +// 1: PERIPH power domain is powered up +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: SERIAL power domain is powered down +// 1: SERIAL power domain is powered up +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 +// 1: RFC power domain powered on +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.RFC_ON +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.SERIAL_ON +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.PERIPH_ON +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// RFC Power domain +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.RFC_ON +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.SERIAL_ON +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.PERIPH_ON +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1 +// +//***************************************************************************** +// Field: [3] VIMS_MODE +// +// +// 0: VIMS power domain is only powered when CPU power domain is powered. +// 1: VIMS power domain is powered whenever the BUS power domain is powered. +#define PRCM_PDCTL1_VIMS_MODE 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_BITN 3 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 +// 1: RFC power domain powered on +// +// Bit shall be used by RFC in autonomus mode but there is no HW restrictions +// fom system CPU to access the bit. +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: Causes a power down of the CPU power domain when system CPU indicates it +// is idle. +// 1: Initiates power-on of the CPU power domain. +// +// This bit is automatically set by a WIC power-on event. +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.CPU_ON +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.RFC_ON +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.VIMS_MODE +#define PRCM_PDCTL1VIMS_ON 0x00000001 +#define PRCM_PDCTL1VIMS_ON_BITN 0 +#define PRCM_PDCTL1VIMS_ON_M 0x00000001 +#define PRCM_PDCTL1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1 +// +//***************************************************************************** +// Field: [4] BUS_ON +// +// +// 0: BUS domain not accessible +// 1: BUS domain is currently accessible +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 + +// Field: [3] VIMS_MODE +// +// +// 0: VIMS domain not accessible +// 1: VIMS domain is currently accessible +#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 +#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC domain not accessible +// 1: RFC domain is currently accessible +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: CPU and BUS domain not accessible +// 1: CPU and BUS domains are both currently accessible +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1BUS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.BUS_ON +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.RFC_ON +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.CPU_ON +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.VIMS_MODE +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCBITS +// +//***************************************************************************** +// Field: [31:0] READ +// +// Control bits for RFC. The RF core CPE processor will automatically check +// this register when it boots, and it can be used to immediately instruct CPE +// to perform some tasks at its start-up. The supported functionality is +// ROM-defined and may vary. See the technical reference manual for more +// details. +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODESEL +// +//***************************************************************************** +// Field: [2:0] CURR +// +// Selects the set of commands that the RFC will accept. Only modes permitted +// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for +// details. +// ENUMs: +// MODE7 Select Mode 7 +// MODE6 Select Mode 6 +// MODE5 Select Mode 5 +// MODE4 Select Mode 4 +// MODE3 Select Mode 3 +// MODE2 Select Mode 2 +// MODE1 Select Mode 1 +// MODE0 Select Mode 0 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODEHWOPT +// +//***************************************************************************** +// Field: [7:0] AVAIL +// +// Permitted RFC modes. More than one mode can be permitted. +// ENUMs: +// MODE7 Mode 7 permitted +// MODE6 Mode 6 permitted +// MODE5 Mode 5 permitted +// MODE4 Mode 4 permitted +// MODE3 Mode 3 permitted +// MODE2 Mode 2 permitted +// MODE1 Mode 1 permitted +// MODE0 Mode 0 permitted +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_PWRPROFSTAT +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// SW can use these bits to timestamp the application. These bits are also +// available through the testtap and can thus be used by the emulator to +// profile in real time. +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RAMRETEN +// +//***************************************************************************** +// Field: [2] RFC +// +// +// 0: Retention for RFC SRAM disabled +// 1: Retention for RFC SRAM enabled +// +// Memories controlled: CPERAM MCERAM RFERAM +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 + +// Field: [1:0] VIMS +// +// +// 0: Memory retention disabled +// 1: Memory retention enabled +// +// Bit 0: VIMS_TRAM +// Bit 1: VIMS_CRAM +// +// Legal modes depend on settings in VIMS:CTL.MODE +// +// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to +// CACHE or SPLIT mode after waking up again +// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in +// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE +// or SPILT mode. +// 10: Illegal mode +// 11: No restrictions +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 + + +#endif // __PRCM__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_dbell.h b/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_dbell.h new file mode 100644 index 0000000000..85b846f6d4 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_dbell.h @@ -0,0 +1,1671 @@ +/****************************************************************************** +* Filename: hw_rfc_dbell_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_DBELL_H__ +#define __HW_RFC_DBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_DBELL component +// +//***************************************************************************** +// Doorbell Command Register +#define RFC_DBELL_O_CMDR 0x00000000 + +// Doorbell Command Status Register +#define RFC_DBELL_O_CMDSTA 0x00000004 + +// Interrupt Flags From RF Hardware Modules +#define RFC_DBELL_O_RFHWIFG 0x00000008 + +// Interrupt Enable For RF Hardware Modules +#define RFC_DBELL_O_RFHWIEN 0x0000000C + +// Interrupt Flags For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIFG 0x00000010 + +// Interrupt Enable For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIEN 0x00000014 + +// Interrupt Vector Selection For Command and Packet Engine Generated +// Interrupts +#define RFC_DBELL_O_RFCPEISL 0x00000018 + +// Doorbell Command Acknowledgement Interrupt Flag +#define RFC_DBELL_O_RFACKIFG 0x0000001C + +// RF Core General Purpose Output Control +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDR +// +//***************************************************************************** +// Field: [31:0] CMD +// +// Command register. Raises an interrupt to the Command and packet engine (CPE) +// upon write. +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDSTA +// +//***************************************************************************** +// Field: [31:0] STAT +// +// Status of the last command used +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIFG +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// RF engine command done interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Modem synchronization word detection interrupt flag. This interrupt will be +// raised by modem when the synchronization word is received. The CPE may +// decide to reject the packet based on its header (protocol specific). Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Modem command done interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Frequency synthesizer calibration accelerator interrupt flag. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIEN +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Interrupt enable for RFHWIFG.RATCH7. +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Interrupt enable for RFHWIFG.RATCH6. +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Interrupt enable for RFHWIFG.RATCH5. +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Interrupt enable for RFHWIFG.RATCH4. +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Interrupt enable for RFHWIFG.RATCH3. +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Interrupt enable for RFHWIFG.RATCH2. +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Interrupt enable for RFHWIFG.RATCH1. +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Interrupt enable for RFHWIFG.RATCH0. +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// Interrupt enable for RFHWIFG.RFESOFT2. +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// Interrupt enable for RFHWIFG.RFESOFT1. +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// Interrupt enable for RFHWIFG.RFESOFT0. +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// Interrupt enable for RFHWIFG.RFEDONE. +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Interrupt enable for RFHWIFG.TRCTK. +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Interrupt enable for RFHWIFG.MDMSOFT. +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Interrupt enable for RFHWIFG.MDMOUT. +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Interrupt enable for RFHWIFG.MDMIN. +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Interrupt enable for RFHWIFG.MDMDONE. +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Interrupt enable for RFHWIFG.FSCA. +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIFG +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt flag 31. The command and packet engine (CPE) has observed an +// unexpected error. A reset of the CPE is needed. This can be done by +// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt flag 30. The command and packet engine (CPE) boot is finished. +// Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt flag 29. As part of command and packet engine (CPE) boot process, +// it has opened access to RF Core modules and memories. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt flag 28. The phase-locked loop in frequency synthesizer has +// reported loss of lock. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt flag 26. Packet reception stopped before packet was done. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt flag 25. Specified number of bytes written to partial read Rx +// buffer. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt flag 23. Rx queue data entry changing state to finished. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: +// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame +// received that did not fit in the Rx queue. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, +// not to be ignored, then acknowledgement sent. Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, +// not to be ignored. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be +// ignored, no payload. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet +// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received +// with ignore flag set. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received +// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with +// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received +// with CRC OK. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 + +// Field: [13] IRQ13 +// +// Interrupt flag 13. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 + +// Field: [12] IRQ12 +// +// Interrupt flag 12. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt flag 11. BLE mode only: A buffer change is complete after +// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted +// LL control packet, and acknowledgement transmitted for that packet. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL +// control packet. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted +// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been +// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio +// operation command in a chain of commands has finished. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation +// command has finished. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt flag 1. The last radio operation command in a chain of commands +// has finished. (IEEE 802.15.4 mode: The last background level radio operation +// command in a chain of commands has finished.) Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A +// background level radio operation command has finished.) Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIEN +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt enable for RFCPEIFG.BOOT_DONE. +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt enable for RFCPEIFG.IRQ27. +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt enable for RFCPEIFG.RX_ABORTED. +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt enable for RFCPEIFG.RX_BUF_FULL. +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt enable for RFCPEIFG.RX_CTRL. +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt enable for RFCPEIFG.RX_EMPTY. +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt enable for RFCPEIFG.RX_IGNORED. +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt enable for RFCPEIFG.RX_NOK. +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt enable for RFCPEIFG.RX_OK. +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt enable for RFCPEIFG.IRQ15. +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt enable for RFCPEIFG.IRQ14. +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 + +// Field: [13] IRQ13 +// +// Interrupt enable for RFCPEIFG.IRQ13. +#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 + +// Field: [12] IRQ12 +// +// Interrupt enable for RFCPEIFG.IRQ12. +#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt enable for RFCPEIFG.TX_RETRANS. +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt enable for RFCPEIFG.TX_CTRL. +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt enable for RFCPEIFG.TX_ACK. +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt enable for RFCPEIFG.TX_DONE. +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEISL +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 + +// Field: [30] BOOT_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 + +// Field: [29] MODULES_UNLOCKED +// +// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 + +// Field: [28] SYNTH_NO_LOCK +// +// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 + +// Field: [27] IRQ27 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 + +// Field: [26] RX_ABORTED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [24] RX_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [23] RX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [22] RX_BUF_FULL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 + +// Field: [21] RX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 + +// Field: [20] RX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 + +// Field: [19] RX_EMPTY +// +// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 + +// Field: [18] RX_IGNORED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 + +// Field: [17] RX_NOK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 + +// Field: [16] RX_OK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 + +// Field: [15] IRQ15 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 + +// Field: [14] IRQ14 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 + +// Field: [13] IRQ13 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ13 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_S 13 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 + +// Field: [12] IRQ12 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ12 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_S 12 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 + +// Field: [11] TX_BUFFER_CHANGED +// +// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 + +// Field: [10] TX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [9] TX_RETRANS +// +// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 + +// Field: [7] TX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 + +// Field: [6] TX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 + +// Field: [5] TX_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 + +// Field: [4] TX_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE +// interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [2] FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [1] LAST_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 + +// Field: [0] COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFACKIFG +// +//***************************************************************************** +// Field: [0] ACKFLAG +// +// Interrupt flag for Command ACK +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_SYSGPOCTL +// +//***************************************************************************** +// Field: [15:12] GPOCTL3 +// +// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO +// line 3. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 + +// Field: [11:8] GPOCTL2 +// +// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO +// line 2. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 + +// Field: [7:4] GPOCTL1 +// +// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO +// line 1. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 + +// Field: [3:0] GPOCTL0 +// +// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO +// line 0. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 + + +#endif // __RFC_DBELL__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_pwr.h b/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_pwr.h new file mode 100644 index 0000000000..e5e98c2df3 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_pwr.h @@ -0,0 +1,153 @@ +/****************************************************************************** +* Filename: hw_rfc_pwr_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_PWR_H__ +#define __HW_RFC_PWR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_PWR component +// +//***************************************************************************** +// RF Core Power Management and Clock Enable +#define RFC_PWR_O_PWMCLKEN 0x00000000 + +//***************************************************************************** +// +// Register: RFC_PWR_O_PWMCLKEN +// +//***************************************************************************** +// Field: [10] RFCTRC +// +// Enable clock to the RF Core Tracer (RFCTRC) module. +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 + +// Field: [9] FSCA +// +// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) +// module. +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 + +// Field: [8] PHA +// +// Enable clock to the Packet Handling Accelerator (PHA) module. +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 + +// Field: [7] RAT +// +// Enable clock to the Radio Timer (RAT) module. +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 + +// Field: [6] RFERAM +// +// Enable clock to the RF Engine RAM module. +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 + +// Field: [5] RFE +// +// Enable clock to the RF Engine (RFE) module. +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 + +// Field: [4] MDMRAM +// +// Enable clock to the Modem RAM module. +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 + +// Field: [3] MDM +// +// Enable clock to the Modem (MDM) module. +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 + +// Field: [2] CPERAM +// +// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of +// RF Core initialization, set this bit together with CPE bit to enable CPE to +// boot. +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 + +// Field: [1] CPE +// +// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As +// part of RF Core initialization, set this bit together with CPERAM bit to +// enable CPE to boot. +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 + +// Field: [0] RFC +// +// Enable essential clocks for the RF Core interface. This includes the +// interconnect, the radio doorbell DBELL command interface, the power +// management (PWR) clock control module, and bus clock (sclk) for the CPE. To +// remove possibility of locking yourself out from the RF Core, this bit can +// not be cleared. If you need to disable all clocks to the RF Core, see the +// PRCM:RFCCLKG.CLK_EN register. +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 + + +#endif // __RFC_PWR__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_rat.h b/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_rat.h new file mode 100644 index 0000000000..38e253e30d --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_rfc_rat.h @@ -0,0 +1,190 @@ +/****************************************************************************** +* Filename: hw_rfc_rat_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_RAT_H__ +#define __HW_RFC_RAT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_RAT component +// +//***************************************************************************** +// Radio Timer Counter Value +#define RFC_RAT_O_RATCNT 0x00000004 + +// Timer Channel 0 Capture/Compare Register +#define RFC_RAT_O_RATCH0VAL 0x00000080 + +// Timer Channel 1 Capture/Compare Register +#define RFC_RAT_O_RATCH1VAL 0x00000084 + +// Timer Channel 2 Capture/Compare Register +#define RFC_RAT_O_RATCH2VAL 0x00000088 + +// Timer Channel 3 Capture/Compare Register +#define RFC_RAT_O_RATCH3VAL 0x0000008C + +// Timer Channel 4 Capture/Compare Register +#define RFC_RAT_O_RATCH4VAL 0x00000090 + +// Timer Channel 5 Capture/Compare Register +#define RFC_RAT_O_RATCH5VAL 0x00000094 + +// Timer Channel 6 Capture/Compare Register +#define RFC_RAT_O_RATCH6VAL 0x00000098 + +// Timer Channel 7 Capture/Compare Register +#define RFC_RAT_O_RATCH7VAL 0x0000009C + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCNT +// +//***************************************************************************** +// Field: [31:0] CNT +// +// Counter value. This is not writable while radio timer counter is enabled. +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH0VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH1VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH2VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH3VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH4VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH5VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH6VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH7VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 + + +#endif // __RFC_RAT__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_smph.h b/os/common/ext/TI/devices/cc13x0/inc/hw_smph.h new file mode 100644 index 0000000000..5ca6d64af9 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_smph.h @@ -0,0 +1,1455 @@ +/****************************************************************************** +* Filename: hw_smph_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SMPH_H__ +#define __HW_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SMPH component +// +//***************************************************************************** +// MCU SEMAPHORE 0 +#define SMPH_O_SMPH0 0x00000000 + +// MCU SEMAPHORE 1 +#define SMPH_O_SMPH1 0x00000004 + +// MCU SEMAPHORE 2 +#define SMPH_O_SMPH2 0x00000008 + +// MCU SEMAPHORE 3 +#define SMPH_O_SMPH3 0x0000000C + +// MCU SEMAPHORE 4 +#define SMPH_O_SMPH4 0x00000010 + +// MCU SEMAPHORE 5 +#define SMPH_O_SMPH5 0x00000014 + +// MCU SEMAPHORE 6 +#define SMPH_O_SMPH6 0x00000018 + +// MCU SEMAPHORE 7 +#define SMPH_O_SMPH7 0x0000001C + +// MCU SEMAPHORE 8 +#define SMPH_O_SMPH8 0x00000020 + +// MCU SEMAPHORE 9 +#define SMPH_O_SMPH9 0x00000024 + +// MCU SEMAPHORE 10 +#define SMPH_O_SMPH10 0x00000028 + +// MCU SEMAPHORE 11 +#define SMPH_O_SMPH11 0x0000002C + +// MCU SEMAPHORE 12 +#define SMPH_O_SMPH12 0x00000030 + +// MCU SEMAPHORE 13 +#define SMPH_O_SMPH13 0x00000034 + +// MCU SEMAPHORE 14 +#define SMPH_O_SMPH14 0x00000038 + +// MCU SEMAPHORE 15 +#define SMPH_O_SMPH15 0x0000003C + +// MCU SEMAPHORE 16 +#define SMPH_O_SMPH16 0x00000040 + +// MCU SEMAPHORE 17 +#define SMPH_O_SMPH17 0x00000044 + +// MCU SEMAPHORE 18 +#define SMPH_O_SMPH18 0x00000048 + +// MCU SEMAPHORE 19 +#define SMPH_O_SMPH19 0x0000004C + +// MCU SEMAPHORE 20 +#define SMPH_O_SMPH20 0x00000050 + +// MCU SEMAPHORE 21 +#define SMPH_O_SMPH21 0x00000054 + +// MCU SEMAPHORE 22 +#define SMPH_O_SMPH22 0x00000058 + +// MCU SEMAPHORE 23 +#define SMPH_O_SMPH23 0x0000005C + +// MCU SEMAPHORE 24 +#define SMPH_O_SMPH24 0x00000060 + +// MCU SEMAPHORE 25 +#define SMPH_O_SMPH25 0x00000064 + +// MCU SEMAPHORE 26 +#define SMPH_O_SMPH26 0x00000068 + +// MCU SEMAPHORE 27 +#define SMPH_O_SMPH27 0x0000006C + +// MCU SEMAPHORE 28 +#define SMPH_O_SMPH28 0x00000070 + +// MCU SEMAPHORE 29 +#define SMPH_O_SMPH29 0x00000074 + +// MCU SEMAPHORE 30 +#define SMPH_O_SMPH30 0x00000078 + +// MCU SEMAPHORE 31 +#define SMPH_O_SMPH31 0x0000007C + +// MCU SEMAPHORE 0 ALIAS +#define SMPH_O_PEEK0 0x00000800 + +// MCU SEMAPHORE 1 ALIAS +#define SMPH_O_PEEK1 0x00000804 + +// MCU SEMAPHORE 2 ALIAS +#define SMPH_O_PEEK2 0x00000808 + +// MCU SEMAPHORE 3 ALIAS +#define SMPH_O_PEEK3 0x0000080C + +// MCU SEMAPHORE 4 ALIAS +#define SMPH_O_PEEK4 0x00000810 + +// MCU SEMAPHORE 5 ALIAS +#define SMPH_O_PEEK5 0x00000814 + +// MCU SEMAPHORE 6 ALIAS +#define SMPH_O_PEEK6 0x00000818 + +// MCU SEMAPHORE 7 ALIAS +#define SMPH_O_PEEK7 0x0000081C + +// MCU SEMAPHORE 8 ALIAS +#define SMPH_O_PEEK8 0x00000820 + +// MCU SEMAPHORE 9 ALIAS +#define SMPH_O_PEEK9 0x00000824 + +// MCU SEMAPHORE 10 ALIAS +#define SMPH_O_PEEK10 0x00000828 + +// MCU SEMAPHORE 11 ALIAS +#define SMPH_O_PEEK11 0x0000082C + +// MCU SEMAPHORE 12 ALIAS +#define SMPH_O_PEEK12 0x00000830 + +// MCU SEMAPHORE 13 ALIAS +#define SMPH_O_PEEK13 0x00000834 + +// MCU SEMAPHORE 14 ALIAS +#define SMPH_O_PEEK14 0x00000838 + +// MCU SEMAPHORE 15 ALIAS +#define SMPH_O_PEEK15 0x0000083C + +// MCU SEMAPHORE 16 ALIAS +#define SMPH_O_PEEK16 0x00000840 + +// MCU SEMAPHORE 17 ALIAS +#define SMPH_O_PEEK17 0x00000844 + +// MCU SEMAPHORE 18 ALIAS +#define SMPH_O_PEEK18 0x00000848 + +// MCU SEMAPHORE 19 ALIAS +#define SMPH_O_PEEK19 0x0000084C + +// MCU SEMAPHORE 20 ALIAS +#define SMPH_O_PEEK20 0x00000850 + +// MCU SEMAPHORE 21 ALIAS +#define SMPH_O_PEEK21 0x00000854 + +// MCU SEMAPHORE 22 ALIAS +#define SMPH_O_PEEK22 0x00000858 + +// MCU SEMAPHORE 23 ALIAS +#define SMPH_O_PEEK23 0x0000085C + +// MCU SEMAPHORE 24 ALIAS +#define SMPH_O_PEEK24 0x00000860 + +// MCU SEMAPHORE 25 ALIAS +#define SMPH_O_PEEK25 0x00000864 + +// MCU SEMAPHORE 26 ALIAS +#define SMPH_O_PEEK26 0x00000868 + +// MCU SEMAPHORE 27 ALIAS +#define SMPH_O_PEEK27 0x0000086C + +// MCU SEMAPHORE 28 ALIAS +#define SMPH_O_PEEK28 0x00000870 + +// MCU SEMAPHORE 29 ALIAS +#define SMPH_O_PEEK29 0x00000874 + +// MCU SEMAPHORE 30 ALIAS +#define SMPH_O_PEEK30 0x00000878 + +// MCU SEMAPHORE 31 ALIAS +#define SMPH_O_PEEK31 0x0000087C + +//***************************************************************************** +// +// Register: SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 + + +#endif // __SMPH__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_ssi.h b/os/common/ext/TI/devices/cc13x0/inc/hw_ssi.h new file mode 100644 index 0000000000..299366c420 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_ssi.h @@ -0,0 +1,544 @@ +/****************************************************************************** +* Filename: hw_ssi_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SSI component +// +//***************************************************************************** +// Control 0 +#define SSI_O_CR0 0x00000000 + +// Control 1 +#define SSI_O_CR1 0x00000004 + +// Data +#define SSI_O_DR 0x00000008 + +// Status +#define SSI_O_SR 0x0000000C + +// Clock Prescale +#define SSI_O_CPSR 0x00000010 + +// Interrupt Mask Set and Clear +#define SSI_O_IMSC 0x00000014 + +// Raw Interrupt Status +#define SSI_O_RIS 0x00000018 + +// Masked Interrupt Status +#define SSI_O_MIS 0x0000001C + +// Interrupt Clear +#define SSI_O_ICR 0x00000020 + +// DMA Control +#define SSI_O_DMACR 0x00000024 + +//***************************************************************************** +// +// Register: SSI_O_CR0 +// +//***************************************************************************** +// Field: [15:8] SCR +// +// Serial clock rate: +// This is used to generate the transmit and receive bit rate of the SSI. The +// bit rate is +// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). +// SCR is a value from 0-255. +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 + +// Field: [7] SPH +// +// CLKOUT phase (Motorola SPI frame format only) +// This bit selects the clock edge that captures data and enables it to change +// state. It +// has the most impact on the first bit transmitted by either permitting or not +// permitting a clock transition before the first data capture edge. +// ENUMs: +// 2ND_CLK_EDGE Data is captured on the second clock edge +// transition. +// 1ST_CLK_EDGE Data is captured on the first clock edge +// transition. +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 + +// Field: [6] SPO +// +// CLKOUT polarity (Motorola SPI frame format only) +// ENUMs: +// HIGH SSI produces a steady state HIGH value on the +// CLKOUT pin when data is not being transferred. +// LOW SSI produces a steady state LOW value on the +// CLKOUT pin when data is +// not being transferred. +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 + +// Field: [5:4] FRF +// +// Frame format. +// The supported frame formats are Motorola SPI, TI synchronous serial and +// National Microwire. +// Value 0'b11 is reserved and shall not be used. +// ENUMs: +// NATIONAL_MICROWIRE National Microwire frame format +// TI_SYNC_SERIAL TI synchronous serial frame format +// MOTOROLA_SPI Motorola SPI frame format +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 + +// Field: [3:0] DSS +// +// Data Size Select. +// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. +// ENUMs: +// 16_BIT 16-bit data +// 15_BIT 15-bit data +// 14_BIT 14-bit data +// 13_BIT 13-bit data +// 12_BIT 12-bit data +// 11_BIT 11-bit data +// 10_BIT 10-bit data +// 9_BIT 9-bit data +// 8_BIT 8-bit data +// 7_BIT 7-bit data +// 6_BIT 6-bit data +// 5_BIT 5-bit data +// 4_BIT 4-bit data +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 + +//***************************************************************************** +// +// Register: SSI_O_CR1 +// +//***************************************************************************** +// Field: [3] SOD +// +// Slave-mode output disabled +// This bit is relevant only in the slave mode, MS=1. In multiple-slave +// systems, it is possible for an SSI master to broadcast a message to all +// slaves in the system while ensuring that only one slave drives data onto its +// serial output line. In such systems the RXD lines from multiple slaves could +// be tied together. To operate in such systems, this bitfield can be set if +// the SSI slave is not supposed to drive the TXD line: +// +// 0: SSI can drive the TXD output in slave mode. +// 1: SSI cannot drive the TXD output in slave mode. +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 + +// Field: [2] MS +// +// Master or slave mode select. This bit can be modified only when SSI is +// disabled, SSE=0. +// ENUMs: +// SLAVE Device configured as slave +// MASTER Device configured as master +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 + +// Field: [1] SSE +// +// Synchronous serial interface enable. +// ENUMs: +// SSI_ENABLED Operation enabled +// SSI_DISABLED Operation disabled +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 + +// Field: [0] LBM +// +// Loop back mode: +// +// 0: Normal serial port operation enabled. +// 1: Output of transmit serial shifter is connected to input of receive serial +// shifter internally. +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Transmit/receive data +// The values read from this field or written to this field must be +// right-justified when SSI is programmed for a data size that is less than 16 +// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit +// logic. The receive logic automatically right-justifies. +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: SSI_O_SR +// +//***************************************************************************** +// Field: [4] BSY +// +// Serial interface busy: +// +// 0: SSI is idle +// 1: SSI is currently transmitting and/or receiving a frame or the transmit +// FIFO is not empty. +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 + +// Field: [3] RFF +// +// Receive FIFO full: +// +// 0: Receive FIFO is not full. +// 1: Receive FIFO is full. +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 + +// Field: [2] RNE +// +// Receive FIFO not empty +// +// 0: Receive FIFO is empty. +// 1: Receive FIFO is not empty. +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 + +// Field: [1] TNF +// +// Transmit FIFO not full: +// +// 0: Transmit FIFO is full. +// 1: Transmit FIFO is not full. +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 + +// Field: [0] TFE +// +// Transmit FIFO empty: +// +// 0: Transmit FIFO is not empty. +// 1: Transmit FIFO is empty. +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 + +//***************************************************************************** +// +// Register: SSI_O_CPSR +// +//***************************************************************************** +// Field: [7:0] CPSDVSR +// +// Clock prescale divisor: +// This field specifies the division factor by which the input system clock to +// SSI must be internally divided before further use. +// The value programmed into this field must be an even non-zero number +// (2-254). The least significant bit of the programmed number is hard-coded to +// zero. If an odd number is written to this register, data read back from +// this register has the least significant bit as zero. +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// Register: SSI_O_IMSC +// +//***************************************************************************** +// Field: [3] TXIM +// +// Transmit FIFO interrupt mask: +// A read returns the current mask for transmit FIFO interrupt. On a write of +// 1, the mask for transmit FIFO interrupt is set which means the interrupt +// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which +// means MIS.TXMIS will not reflect the interrupt. +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 + +// Field: [2] RXIM +// +// Receive FIFO interrupt mask: +// A read returns the current mask for receive FIFO interrupt. On a write of 1, +// the mask for receive FIFO interrupt is set which means the interrupt state +// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means +// MIS.RXMIS will not reflect the interrupt. +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 + +// Field: [1] RTIM +// +// Receive timeout interrupt mask: +// A read returns the current mask for receive timeout interrupt. On a write of +// 1, the mask for receive timeout interrupt is set which means the interrupt +// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which +// means MIS.RTMIS will not reflect the interrupt. +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 + +// Field: [0] RORIM +// +// Receive overrun interrupt mask: +// A read returns the current mask for receive overrun interrupt. On a write of +// 1, the mask for receive overrun interrupt is set which means the interrupt +// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which +// means MIS.RORMIS will not reflect the interrupt. +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_RIS +// +//***************************************************************************** +// Field: [3] TXRIS +// +// Raw transmit FIFO interrupt status: +// The transmit interrupt is asserted when there are four or fewer valid +// entries in the transmit FIFO. The transmit interrupt is not qualified with +// the SSI enable signal. Therefore one of the following ways can be used: +// - data can be written to the transmit FIFO prior to enabling the SSI and +// the +// interrupts. +// - SSI and interrupts can be enabled so that data can be written to the +// transmit FIFO by an interrupt service routine. +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 + +// Field: [2] RXRIS +// +// Raw interrupt state of receive FIFO interrupt: +// The receive interrupt is asserted when there are four or more valid entries +// in the receive FIFO. +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 + +// Field: [1] RTRIS +// +// Raw interrupt state of receive timeout interrupt: +// The receive timeout interrupt is asserted when the receive FIFO is not empty +// and SSI has remained idle for a fixed 32 bit period. This mechanism can be +// used to notify the user that data is still present in the receive FIFO and +// requires servicing. This interrupt is deasserted if the receive FIFO becomes +// empty by subsequent reads, or if new data is received on RXD. +// It can also be cleared by writing to ICR.RTIC. +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 + +// Field: [0] RORRIS +// +// Raw interrupt state of receive overrun interrupt: +// The receive overrun interrupt is asserted when the FIFO is already full and +// an additional data frame is received, causing an overrun of the FIFO. Data +// is over-written in the +// receive shift register, but not the FIFO so the FIFO contents stay valid. +// It can also be cleared by writing to ICR.RORIC. +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_MIS +// +//***************************************************************************** +// Field: [3] TXMIS +// +// Masked interrupt state of transmit FIFO interrupt: +// This field returns the masked interrupt state of transmit FIFO interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 + +// Field: [2] RXMIS +// +// Masked interrupt state of receive FIFO interrupt: +// This field returns the masked interrupt state of receive FIFO interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 + +// Field: [1] RTMIS +// +// Masked interrupt state of receive timeout interrupt: +// This field returns the masked interrupt state of receive timeout interrupt +// which is the AND product of raw interrupt state RIS.RTRIS and the mask +// setting IMSC.RTIM. +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 + +// Field: [0] RORMIS +// +// Masked interrupt state of receive overrun interrupt: +// This field returns the masked interrupt state of receive overrun interrupt +// which is the AND product of raw interrupt state RIS.RORRIS and the mask +// setting IMSC.RORIM. +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_ICR +// +//***************************************************************************** +// Field: [1] RTIC +// +// Clear the receive timeout interrupt: +// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 +// has no effect. +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 + +// Field: [0] RORIC +// +// Clear the receive overrun interrupt: +// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). +// Writing 0 has no effect. +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DMACR +// +//***************************************************************************** +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 + + +#endif // __SSI__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_sysctl.h b/os/common/ext/TI/devices/cc13x0/inc/hw_sysctl.h new file mode 100644 index 0000000000..43f20fcf4d --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_sysctl.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Filename: hw_sysctl.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + + +//***************************************************************************** +// +// The following are initial defines for the MCU clock +// +//***************************************************************************** +#define GET_MCU_CLOCK 48000000 + + +#endif // __HW_SYSCTL_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_trng.h b/os/common/ext/TI/devices/cc13x0/inc/hw_trng.h new file mode 100644 index 0000000000..e6628bbe42 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_trng.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: hw_trng_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TRNG_H__ +#define __HW_TRNG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// TRNG component +// +//***************************************************************************** +// Random Number Lower Word Readout Value +#define TRNG_O_OUT0 0x00000000 + +// Random Number Upper Word Readout Value +#define TRNG_O_OUT1 0x00000004 + +// Interrupt Status +#define TRNG_O_IRQFLAGSTAT 0x00000008 + +// Interrupt Mask +#define TRNG_O_IRQFLAGMASK 0x0000000C + +// Interrupt Flag Clear +#define TRNG_O_IRQFLAGCLR 0x00000010 + +// Control +#define TRNG_O_CTL 0x00000014 + +// Configuration 0 +#define TRNG_O_CFG0 0x00000018 + +// Alarm Control +#define TRNG_O_ALARMCNT 0x0000001C + +// FRO Enable +#define TRNG_O_FROEN 0x00000020 + +// FRO De-tune Bit +#define TRNG_O_FRODETUNE 0x00000024 + +// Alarm Event +#define TRNG_O_ALARMMASK 0x00000028 + +// Alarm Shutdown +#define TRNG_O_ALARMSTOP 0x0000002C + +// LFSR Readout Value +#define TRNG_O_LFSR0 0x00000030 + +// LFSR Readout Value +#define TRNG_O_LFSR1 0x00000034 + +// LFSR Readout Value +#define TRNG_O_LFSR2 0x00000038 + +// TRNG Engine Options Information +#define TRNG_O_HWOPT 0x00000078 + +// HW Version 0 +#define TRNG_O_HWVER0 0x0000007C + +// Interrupt Status After Masking +#define TRNG_O_IRQSTATMASK 0x00001FD8 + +// HW Version 1 +#define TRNG_O_HWVER1 0x00001FE0 + +// Interrupt Set +#define TRNG_O_IRQSET 0x00001FEC + +// SW Reset Control +#define TRNG_O_SWRESET 0x00001FF0 + +// Interrupt Status +#define TRNG_O_IRQSTAT 0x00001FF8 + +//***************************************************************************** +// +// Register: TRNG_O_OUT0 +// +//***************************************************************************** +// Field: [31:0] VALUE_31_0 +// +// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_OUT1 +// +//***************************************************************************** +// Field: [31:0] VALUE_63_32 +// +// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGSTAT +// +//***************************************************************************** +// Field: [31] NEED_CLOCK +// +// 1: Indicates that the TRNG is busy generating entropy or is in one of its +// test modes - clocks may not be turned off and the power supply voltage must +// be kept stable. +// 0: TRNG is idle and can be shut down +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 + +// Field: [1] SHUTDOWN_OVF +// +// 1: The number of FROs shut down (i.e. the number of '1' bits in the +// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR +// +// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Data are available in OUT0 and OUT1. +// +// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to +// '0'. +// If a new number is already available in the internal register of the TRNG, +// the number is directly clocked into the result register. In this case the +// status bit is asserted again, after one clock cycle. +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this +// module. +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGCLR +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Clear IRQFLAGSTAT.RDY. +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_CTL +// +//***************************************************************************** +// Field: [31:16] STARTUP_CYCLES +// +// This field determines the number of samples (between 2^8 and 2^24) taken to +// gather entropy from the FROs during startup. If the written value of this +// field is zero, the number of samples is 2^24, otherwise the number of +// samples equals the written value times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while TRNG_EN is 0. If 1 an update will be +// ignored. +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 + +// Field: [10] TRNG_EN +// +// 0: Forces all TRNG logic back into the idle state immediately. +// 1: Starts TRNG, gathering entropy from the FROs for the number of samples +// determined by STARTUP_CYCLES. +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 + +// Field: [2] NO_LFSR_FB +// +// 1: Remove XNOR feedback from the main LFSR, converting it into a normal +// shift register for the XOR-ed outputs of the FROs (shifting data in on the +// LSB side). A '1' also forces the LFSR to sample continuously. +// +// This bit can only be set to '1' when TEST_MODE is also set to '1' and should +// not be used for other than test purposes +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 + +// Field: [1] TEST_MODE +// +// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter +// are automatically cleared before enabling access) and keeps +// IRQFLAGSTAT.NEED_CLOCK at '1'. +// +// This bit shall not be used unless you need to change the LFSR seed prior to +// creating a new random value. All other testing is done external to register +// control. +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 + +//***************************************************************************** +// +// Register: TRNG_O_CFG0 +// +//***************************************************************************** +// Field: [31:16] MAX_REFILL_CYCLES +// +// This field determines the maximum number of samples (between 2^8 and 2^24) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the written value of this field is zero, the number of +// samples is 2^24, otherwise the number of samples equals the written value +// times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while CTL.TRNG_EN is 0. +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 + +// Field: [11:8] SMPL_DIV +// +// This field directly controls the number of clock cycles between samples +// taken from the FROs. Default value 0 indicates that samples are taken every +// clock cycle, +// maximum value 0xF takes one sample every 16 clock cycles. +// This field must be set to a value such that the slowest FRO (even under +// worst-case +// conditions) has a cycle time less than twice the sample period. +// +// This field can only be modified while CTL.TRNG_EN is '0'. +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 + +// Field: [7:0] MIN_REFILL_CYCLES +// +// This field determines the minimum number of samples (between 2^6 and 2^14) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the value of this field is zero, the number of samples is +// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the +// minimum number of samples equals the written value times 64 (which can be up +// to 2^14). To ensure same entropy in all generated random numbers the value 0 +// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. +// The number of samples defined here cannot be higher than the number defined +// by the 'max_refill_cycles' field (i.e. that field takes precedence). No +// random value will be created if min refill > max refill. +// +// This field can only be modified while CTL.TRNG_EN = 0. +// +// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) +// 0x01: 1*2^6 samples +// 0x02: 2*2^6 samples +// ... +// 0xFF: 255*2^6 samples +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMCNT +// +//***************************************************************************** +// Field: [29:24] SHUTDOWN_CNT +// +// Read-only, indicates the number of '1' bits in ALARMSTOP register. +// The maximum value equals the number of FROs. +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 + +// Field: [20:16] SHUTDOWN_THR +// +// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The +// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 + +// Field: [7:0] ALARM_THR +// +// Alarm detection threshold for the repeating pattern detectors on each FRO. +// An FRO 'alarm event' is declared when a repeating pattern (of up to four +// samples length) is detected continuously for the number of samples defined +// by this field's value. Reset value 0xFF should keep the number of 'alarm +// events' to a manageable level. +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FROEN +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. +// Default state is all '1's to enable all FROs after power-up. Note that they +// are not actually started up before the CTL.TRNG_EN bit is set to '1'. +// +// Bits are automatically forced to '0' here (and cannot be written to '1') +// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FRODETUNE +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run +// approximately 5% faster. The value of one of these bits may only be changed +// while the corresponding FRO is turned off (by temporarily writing a '0' in +// the corresponding +// bit of the FROEN.FRO_MASK register). +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMMASK +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced an 'alarm event'. +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMSTOP +// +//***************************************************************************** +// Field: [23:0] FRO_FLAGS +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced more than one 'alarm event' in quick +// succession and has been turned off. A '1' in this field forces the +// corresponding bit in FROEN.FRO_MASK to '0'. +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR0 +// +//***************************************************************************** +// Field: [31:0] LFSR_31_0 +// +// Bits [31:0] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR1 +// +//***************************************************************************** +// Field: [31:0] LFSR_63_32 +// +// Bits [63:32] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR2 +// +//***************************************************************************** +// Field: [16:0] LFSR_80_64 +// +// Bits [80:64] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWOPT +// +//***************************************************************************** +// Field: [11:6] NR_OF_FROS +// +// Number of FROs implemented in this TRNG, value 24 (decimal). +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER0 +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// 4 bits binary encoding of the major hardware revision number. +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// 4 bits binary encoding of the minor hardware revision number. +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// 4 bits binary encoding of the hardware patch level, initial release will +// carry value zero. +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 + +// Field: [15:8] EIP_NUM_COMPL +// +// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 + +// Field: [7:0] EIP_NUM +// +// 8 bits binary encoding of the module number. This TRNG gives 0x4B. +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTATMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with +// IRQFLAGMASK.SHUTDOWN_OVF) +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// New random value available (result of IRQFLAGSTAT.RDY AND'ed with +// IRQFLAGMASK.RDY) +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER1 +// +//***************************************************************************** +// Field: [7:0] REV +// +// The revision number of this module is Rev 2.0. +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSET +// +//***************************************************************************** +//***************************************************************************** +// +// Register: TRNG_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 +// for reset to be completed. +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and +// IRQFLAGSTAT.RDY +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 + + +#endif // __TRNG__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_types.h b/os/common/ext/TI/devices/cc13x0/inc/hw_types.h new file mode 100644 index 0000000000..d04bcb2cd9 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_types.h @@ -0,0 +1,123 @@ +/****************************************************************************** +* Filename: hw_types.h +* Revised: $Date$ +* Revision: $Revision$ +* +* Description: Common types and macros. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +#include +#include +#include "../inc/hw_chip_def.h" + +//***************************************************************************** +// +// Common driverlib types +// +//***************************************************************************** +typedef void (* FPTR_VOID_VOID_T) (void); +typedef void (* FPTR_VOID_UINT8_T) (uint8_t); + +//***************************************************************************** +// +// This symbol forces simple driverlib functions to be inlined in the code +// instead of using function calls. +// +//***************************************************************************** +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +//***************************************************************************** +// +// C99 types only allows bitfield defintions on certain datatypes. +// +//***************************************************************************** +typedef unsigned int __UINT32; + +//***************************************************************************** +// +// Macros for direct hardware access. +// +// If using these macros the programmer should be aware of any limitations to +// the address accessed i.e. if it supports word and/or byte access. +// +//***************************************************************************** +// Word (32 bit) access to address x +// Read example : my32BitVar = HWREG(base_addr + offset) ; +// Write example : HWREG(base_addr + offset) = my32BitVar ; +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) + +// Half word (16 bit) access to address x +// Read example : my16BitVar = HWREGH(base_addr + offset) ; +// Write example : HWREGH(base_addr + offset) = my16BitVar ; +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) + +// Byte (8 bit) access to address x +// Read example : my8BitVar = HWREGB(base_addr + offset) ; +// Write example : HWREGB(base_addr + offset) = my8BitVar ; +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +//***************************************************************************** +// +// Macros for hardware access to bit-band supported addresses via the bit-band region. +// +// Macros calculate the corresponding address to access in the bit-band region +// based on the actual address of the memory/register and the bit number. +// +// Do NOT use these macros to access the bit-band region directly! +// +//***************************************************************************** +// Bit-band access to address x bit number b using word access (32 bit) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using half word access (16 bit) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using byte access (8 bit) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_uart.h b/os/common/ext/TI/devices/cc13x0/inc/hw_uart.h new file mode 100644 index 0000000000..3bd2269837 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_uart.h @@ -0,0 +1,1044 @@ +/****************************************************************************** +* Filename: hw_uart_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UART component +// +//***************************************************************************** +// Data +#define UART_O_DR 0x00000000 + +// Status +#define UART_O_RSR 0x00000004 + +// Error Clear +#define UART_O_ECR 0x00000004 + +// Flag +#define UART_O_FR 0x00000018 + +// Integer Baud-Rate Divisor +#define UART_O_IBRD 0x00000024 + +// Fractional Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 + +// Line Control +#define UART_O_LCRH 0x0000002C + +// Control +#define UART_O_CTL 0x00000030 + +// Interrupt FIFO Level Select +#define UART_O_IFLS 0x00000034 + +// Interrupt Mask Set/Clear +#define UART_O_IMSC 0x00000038 + +// Raw Interrupt Status +#define UART_O_RIS 0x0000003C + +// Masked Interrupt Status +#define UART_O_MIS 0x00000040 + +// Interrupt Clear +#define UART_O_ICR 0x00000044 + +// DMA Control +#define UART_O_DMACTL 0x00000048 + +//***************************************************************************** +// +// Register: UART_O_DR +// +//***************************************************************************** +// Field: [11] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 + +// Field: [10] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). When a +// break occurs, a 0 character is loaded into the FIFO. The next character is +// enabled after the receive data input (UARTRXD input pin) goes to a 1 +// (marking state), and the next valid start bit is received. +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 + +// Field: [9] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 + +// Field: [8] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 + +// Field: [7:0] DATA +// +// Data transmitted or received: +// On writes, the transmit data character is pushed into the FIFO. +// On reads, the oldest received data character since the last read is +// returned. +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: UART_O_RSR +// +//***************************************************************************** +// Field: [3] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 + +// Field: [2] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// When a break occurs, a 0 character is loaded into the FIFO. The next +// character is enabled after the receive data input (UARTRXD input pin) goes +// to a 1 (marking state), and the next valid start bit is received. +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 + +// Field: [1] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 + +// Field: [0] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_ECR +// +//***************************************************************************** +// Field: [3] OE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 + +// Field: [2] BE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 + +// Field: [1] PE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 + +// Field: [0] FE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_FR +// +//***************************************************************************** +// Field: [7] TXFE +// +// UART Transmit FIFO Empty: +// The meaning of this bit depends on the state of LCRH.FEN . +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. +// This bit does not indicate if there is data in the transmit shift register. +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 + +// Field: [6] RXFF +// +// UART Receive FIFO Full: +// The meaning of this bit depends on the state of LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is full. +// - If the FIFO is enabled, this bit is set when the receive FIFO is full. +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 + +// Field: [5] TXFF +// +// UART Transmit FIFO Full: +// Transmit FIFO full. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is full. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 + +// Field: [4] RXFE +// +// UART Receive FIFO Empty: +// Receive FIFO empty. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 + +// Field: [3] BUSY +// +// UART Busy: +// If this bit is set to 1, the UART is busy transmitting data. This bit +// remains set until the complete byte, including all the stop bits, has been +// sent from the shift register. +// This bit is set as soon as the transmit FIFO becomes non-empty, regardless +// of whether the UART is enabled or not. +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 + +// Field: [0] CTS +// +// Clear To Send: +// This bit is the complement of the active-low UART CTS input pin. +// That is, the bit is 1 when CTS input pin is LOW. +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 + +//***************************************************************************** +// +// Register: UART_O_IBRD +// +//***************************************************************************** +// Field: [15:0] DIVINT +// +// The integer baud rate divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, DIVINT=0 does not give a valid baud rate. +// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// Register: UART_O_FBRD +// +//***************************************************************************** +// Field: [5:0] DIVFRAC +// +// Fractional Baud-Rate Divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, IBRD.DIVINT=0 does not give a valid baud rate. +// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// Register: UART_O_LCRH +// +//***************************************************************************** +// Field: [7] SPS +// +// UART Stick Parity Select: +// +// 0: Stick parity is disabled +// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. +// the parity bit is transmitted and checked as 1 when EPS = 0). +// +// This bit has no effect when PEN disables parity checking and generation. +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 + +// Field: [6:5] WLEN +// +// UART Word Length: +// These bits indicate the number of data bits transmitted or received in a +// frame. +// ENUMs: +// 8 Word Length 8 bits +// 7 Word Length 7 bits +// 6 Word Length 6 bits +// 5 Word Length 5 bits +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 + +// Field: [4] FEN +// +// UART Enable FIFOs +// ENUMs: +// EN Transmit and receive FIFO buffers are enabled +// (FIFO mode) +// DIS FIFOs are disabled (character mode) that is, the +// FIFOs become 1-byte-deep holding registers. +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 + +// Field: [3] STP2 +// +// UART Two Stop Bits Select: +// If this bit is set to 1, two stop bits are transmitted at the end of the +// frame. The receive logic does not check for two stop bits being received. +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 + +// Field: [2] EPS +// +// UART Even Parity Select +// ENUMs: +// EVEN Even parity: The UART generates or checks for an +// even number of 1s in the data and parity bits. +// ODD Odd parity: The UART generates or checks for an +// odd number of 1s in the data and parity bits. +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 + +// Field: [1] PEN +// +// UART Parity Enable +// This bit controls generation and checking of parity bit. +// ENUMs: +// EN Parity checking and generation is enabled. +// DIS Parity is disabled and no parity bit is added to +// the data frame +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 + +// Field: [0] BRK +// +// UART Send Break +// If this bit is set to 1, a low-level is continually output on the UARTTXD +// output pin, after completing transmission of the current character. For the +// proper execution of the break command, the +// software must set this bit for at least two complete frames. For normal use, +// this bit must be cleared to 0. +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 + +//***************************************************************************** +// +// Register: UART_O_CTL +// +//***************************************************************************** +// Field: [15] CTSEN +// +// CTS hardware flow control enable +// ENUMs: +// EN CTS hardware flow control enabled +// DIS CTS hardware flow control disabled +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 + +// Field: [14] RTSEN +// +// RTS hardware flow control enable +// ENUMs: +// EN RTS hardware flow control enabled +// DIS RTS hardware flow control disabled +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 + +// Field: [11] RTS +// +// Request to Send +// This bit is the complement of the active-low UART RTS output. That is, when +// the bit is programmed to a 1 then RTS output on the pins is LOW. +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 + +// Field: [9] RXE +// +// UART Receive Enable +// If the UART is disabled in the middle of reception, it completes the current +// character before stopping. +// ENUMs: +// EN UART Receive enabled +// DIS UART Receive disabled +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 + +// Field: [8] TXE +// +// UART Transmit Enable +// If the UART is disabled in the middle of transmission, it completes the +// current character before stopping. +// ENUMs: +// EN UART Transmit enabled +// DIS UART Transmit disabled +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 + +// Field: [7] LBE +// +// UART Loop Back Enable: +// Enabling the loop-back mode connects the UARTTXD output from the UART to +// UARTRXD input of the UART. +// ENUMs: +// EN Loop Back enabled +// DIS Loop Back disabled +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 + +// Field: [0] UARTEN +// +// UART Enable +// ENUMs: +// EN UART enabled +// DIS UART disabled +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IFLS +// +//***************************************************************************** +// Field: [5:3] RXSEL +// +// Receive interrupt FIFO level select: +// This field sets the trigger points for the receive interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Receive FIFO becomes >= 7/8 full +// 6_8 Receive FIFO becomes >= 3/4 full +// 4_8 Receive FIFO becomes >= 1/2 full +// 2_8 Receive FIFO becomes >= 1/4 full +// 1_8 Receive FIFO becomes >= 1/8 full +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 + +// Field: [2:0] TXSEL +// +// Transmit interrupt FIFO level select: +// This field sets the trigger points for the transmit interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Transmit FIFO becomes <= 7/8 full +// 6_8 Transmit FIFO becomes <= 3/4 full +// 4_8 Transmit FIFO becomes <= 1/2 full +// 2_8 Transmit FIFO becomes <= 1/4 full +// 1_8 Transmit FIFO becomes <= 1/8 full +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IMSC +// +//***************************************************************************** +// Field: [10] OEIM +// +// Overrun error interrupt mask. A read returns the current mask for UART's +// overrun error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not +// reflect the interrupt. +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 + +// Field: [9] BEIM +// +// Break error interrupt mask. A read returns the current mask for UART's break +// error interrupt. On a write of 1, the mask of the overrun error interrupt is +// set which means the interrupt state will be reflected in MIS.BEMIS. A write +// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 + +// Field: [8] PEIM +// +// Parity error interrupt mask. A read returns the current mask for UART's +// parity error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not +// reflect the interrupt. +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 + +// Field: [7] FEIM +// +// Framing error interrupt mask. A read returns the current mask for UART's +// framing error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not +// reflect the interrupt. +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 + +// Field: [6] RTIM +// +// Receive timeout interrupt mask. A read returns the current mask for UART's +// receive timeout interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not +// reflect the interrupt. +// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the +// mask is set (RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 + +// Field: [5] TXIM +// +// Transmit interrupt mask. A read returns the current mask for UART's transmit +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 +// clears the mask which means MIS.TXMIS will not reflect the interrupt. +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 + +// Field: [4] RXIM +// +// Receive interrupt mask. A read returns the current mask for UART's receive +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 +// clears the mask which means MIS.RXMIS will not reflect the interrupt. +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 + +// Field: [1] CTSMIM +// +// Clear to Send (CTS) modem interrupt mask. A read returns the current mask +// for UART's clear to send interrupt. On a write of 1, the mask of the overrun +// error interrupt is set which means the interrupt state will be reflected in +// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not +// reflect the interrupt. +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 + +//***************************************************************************** +// +// Register: UART_O_RIS +// +//***************************************************************************** +// Field: [10] OERIS +// +// Overrun error interrupt status: +// This field returns the raw interrupt state of UART's overrun error +// interrupt. Overrun error occurs if data is received and the receive FIFO is +// full. +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 + +// Field: [9] BERIS +// +// Break error interrupt status: +// This field returns the raw interrupt state of UART's break error interrupt. +// Break error is set when a break condition is detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 + +// Field: [8] PERIS +// +// Parity error interrupt status: +// This field returns the raw interrupt state of UART's parity error interrupt. +// Parity error is set if the parity of the received data character does not +// match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 + +// Field: [7] FERIS +// +// Framing error interrupt status: +// This field returns the raw interrupt state of UART's framing error +// interrupt. Framing error is set if the received character does not have a +// valid stop bit (a valid stop bit is 1). +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 + +// Field: [6] RTRIS +// +// Receive timeout interrupt status: +// This field returns the raw interrupt state of UART's receive timeout +// interrupt. The receive timeout interrupt is asserted when the receive FIFO +// is not empty, and no more data is received during a 32-bit period. The +// receive timeout interrupt is cleared either when the FIFO becomes empty +// through reading all the data, or when a 1 is written to ICR.RTIC. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 + +// Field: [5] TXRIS +// +// Transmit interrupt status: +// This field returns the raw interrupt state of UART's transmit interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if +// the number of bytes in transmit FIFO is equal to or lower than the +// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by +// writing data to the transmit FIFO until it becomes greater than the trigger +// level, or by clearing the interrupt through ICR.TXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the transmit interrupt is asserted if there is no data present in +// the transmitters single location. It is cleared by performing a single write +// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 + +// Field: [4] RXRIS +// +// Receive interrupt status: +// This field returns the raw interrupt state of UART's receive interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if +// the receive FIFO reaches the programmed trigger +// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from +// the receive FIFO until it becomes less than the trigger level, or by +// clearing the interrupt through ICR.RXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the receive interrupt is asserted if data is received +// thereby filling the location. The receive interrupt is cleared by performing +// a single read of the receive FIFO, or by clearing the interrupt through +// ICR.RXIC. +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 + +// Field: [1] CTSRMIS +// +// Clear to Send (CTS) modem interrupt status: +// This field returns the raw interrupt state of UART's clear to send +// interrupt. +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_MIS +// +//***************************************************************************** +// Field: [10] OEMIS +// +// Overrun error masked interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.OERIS and the mask setting +// IMSC.OEIM. +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 + +// Field: [9] BEMIS +// +// Break error masked interrupt status: +// This field returns the masked interrupt state of the break error interrupt +// which is the AND product of raw interrupt state RIS.BERIS and the mask +// setting IMSC.BEIM. +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 + +// Field: [8] PEMIS +// +// Parity error masked interrupt status: +// This field returns the masked interrupt state of the parity error interrupt +// which is the AND product of raw interrupt state RIS.PERIS and the mask +// setting IMSC.PEIM. +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 + +// Field: [7] FEMIS +// +// Framing error masked interrupt status: Returns the masked interrupt state of +// the framing error interrupt which is the AND product of raw interrupt state +// RIS.FERIS and the mask setting IMSC.FEIM. +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 + +// Field: [6] RTMIS +// +// Receive timeout masked interrupt status: +// Returns the masked interrupt state of the receive timeout interrupt. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 + +// Field: [5] TXMIS +// +// Transmit masked interrupt status: +// This field returns the masked interrupt state of the transmit interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 + +// Field: [4] RXMIS +// +// Receive masked interrupt status: +// This field returns the masked interrupt state of the receive interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 + +// Field: [1] CTSMMIS +// +// Clear to Send (CTS) modem masked interrupt status: +// This field returns the masked interrupt state of the clear to send interrupt +// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask +// setting IMSC.CTSMIM. +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_ICR +// +//***************************************************************************** +// Field: [10] OEIC +// +// Overrun error interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). +// Writing 0 has no effect. +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 + +// Field: [9] BEIC +// +// Break error interrupt clear: +// Writing 1 to this field clears the break error interrupt (RIS.BERIS). +// Writing 0 has no effect. +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 + +// Field: [8] PEIC +// +// Parity error interrupt clear: +// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). +// Writing 0 has no effect. +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 + +// Field: [7] FEIC +// +// Framing error interrupt clear: +// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). +// Writing 0 has no effect. +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 + +// Field: [6] RTIC +// +// Receive timeout interrupt clear: +// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). +// Writing 0 has no effect. +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 + +// Field: [5] TXIC +// +// Transmit interrupt clear: +// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 +// has no effect. +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 + +// Field: [4] RXIC +// +// Receive interrupt clear: +// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 +// has no effect. +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 + +// Field: [1] CTSMIC +// +// Clear to Send (CTS) modem interrupt clear: +// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). +// Writing 0 has no effect. +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 + +//***************************************************************************** +// +// Register: UART_O_DMACTL +// +//***************************************************************************** +// Field: [2] DMAONERR +// +// DMA on error. If this bit is set to 1, the DMA receive request outputs (for +// single and burst requests) are disabled when the UART error interrupt is +// asserted (more specifically if any of the error interrupts RIS.PERIS, +// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 + +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 + + +#endif // __UART__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_udma.h b/os/common/ext/TI/devices/cc13x0/inc/hw_udma.h new file mode 100644 index 0000000000..6896cbcaf5 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_udma.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* Filename: hw_udma_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UDMA component +// +//***************************************************************************** +// Status +#define UDMA_O_STATUS 0x00000000 + +// Configuration +#define UDMA_O_CFG 0x00000004 + +// Channel Control Data Base Pointer +#define UDMA_O_CTRL 0x00000008 + +// Channel Alternate Control Data Base Pointer +#define UDMA_O_ALTCTRL 0x0000000C + +// Channel Wait On Request Status +#define UDMA_O_WAITONREQ 0x00000010 + +// Channel Software Request +#define UDMA_O_SOFTREQ 0x00000014 + +// Channel Set UseBurst +#define UDMA_O_SETBURST 0x00000018 + +// Channel Clear UseBurst +#define UDMA_O_CLEARBURST 0x0000001C + +// Channel Set Request Mask +#define UDMA_O_SETREQMASK 0x00000020 + +// Clear Channel Request Mask +#define UDMA_O_CLEARREQMASK 0x00000024 + +// Set Channel Enable +#define UDMA_O_SETCHANNELEN 0x00000028 + +// Clear Channel Enable +#define UDMA_O_CLEARCHANNELEN 0x0000002C + +// Channel Set Primary-Alternate +#define UDMA_O_SETCHNLPRIALT 0x00000030 + +// Channel Clear Primary-Alternate +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 + +// Set Channel Priority +#define UDMA_O_SETCHNLPRIORITY 0x00000038 + +// Clear Channel Priority +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C + +// Error Status and Clear +#define UDMA_O_ERROR 0x0000004C + +// Channel Request Done +#define UDMA_O_REQDONE 0x00000504 + +// Channel Request Done Mask +#define UDMA_O_DONEMASK 0x00000520 + +//***************************************************************************** +// +// Register: UDMA_O_STATUS +// +//***************************************************************************** +// Field: [31:28] TEST +// +// +// 0x0: Controller does not include the integration test logic +// 0x1: Controller includes the integration test logic +// 0x2: Undefined +// ... +// 0xF: Undefined +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 + +// Field: [20:16] TOTALCHANNELS +// +// Register value returns number of available uDMA channels minus one. For +// example a read out value of: +// +// 0x00: Show that the controller is configured to use 1 uDMA channel +// 0x01: Shows that the controller is configured to use 2 uDMA channels +// ... +// 0x1F: Shows that the controller is configured to use 32 uDMA channels +// (32-1=31=0x1F) +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 + +// Field: [7:4] STATE +// +// Current state of the control state machine. State can be one of the +// following: +// +// 0x0: Idle +// 0x1: Reading channel controller data +// 0x2: Reading source data end pointer +// 0x3: Reading destination data end pointer +// 0x4: Reading source data +// 0x5: Writing destination data +// 0x6: Waiting for uDMA request to clear +// 0x7: Writing channel controller data +// 0x8: Stalled +// 0x9: Done +// 0xA: Peripheral scatter-gather transition +// 0xB: Undefined +// ... +// 0xF: Undefined. +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 + +// Field: [0] MASTERENABLE +// +// Shows the enable status of the controller as configured by CFG.MASTERENABLE: +// +// 0: Controller is disabled +// 1: Controller is enabled +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CFG +// +//***************************************************************************** +// Field: [7:5] PRTOCTRL +// +// Sets the AHB-Lite bus protocol protection state by controlling the AHB +// signal HProt[3:1] as follows: +// +// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. +// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. +// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. +// +// When bit [n] = 1 then the corresponding HProt bit is high. +// When bit [n] = 0 then the corresponding HProt bit is low. +// +// This field controls HProt[3:1] signal for all transactions initiated by uDMA +// except two transactions below: +// - the read from the address indicated by source address pointer +// - the write to the address indicated by destination address pointer +// HProt[3:1] for these two exceptions can be controlled by dedicated fields in +// the channel configutation descriptor. +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 + +// Field: [0] MASTERENABLE +// +// Enables the controller: +// +// 0: Disables the controller +// 1: Enables the controller +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CTRL +// +//***************************************************************************** +// Field: [31:10] BASEPTR +// +// This register point to the base address for the primary data structures of +// each DMA channel. This is not stored in module, but in system memory, thus +// space must be allocated for this usage when DMA is in usage +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 + +//***************************************************************************** +// +// Register: UDMA_O_ALTCTRL +// +//***************************************************************************** +// Field: [31:0] BASEPTR +// +// This register shows the base address for the alternate data structures and +// is calculated by module, thus read only +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_WAITONREQ +// +//***************************************************************************** +// Field: [31:0] CHNLSTATUS +// +// Channel wait on request status: +// +// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, +// this channel may come out of active state even if request is still present. +// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it +// keeps channel Ch in active state until the requests are deasserted. This +// handshake is necessary for channels where the requester is in an +// asynchronous domain or can run at slower clock speed than uDMA +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SOFTREQ +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to generate a software uDMA request on the +// corresponding uDMA channel +// +// Bit [Ch] = 0: Does not create a uDMA request for channel Ch +// Bit [Ch] = 1: Creates a uDMA request for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented does not create a +// uDMA request for that channel +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the useburst status, or disables individual channels from generating +// single uDMA requests. The value R is the arbitration rate and stored in the +// controller data structure. +// +// Read as: +// +// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on +// channel C. The controller performs 2^R, or single, bus transfers. +// +// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. +// The controller only responds to burst transfer requests and performs 2^R +// transfers. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. +// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The +// controller performs 2^R transfers for burst requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable single transfer requests. +// +// Write as: +// +// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer +// requests. +// +// Bit [Ch] = 1: Enables single transfer requests on channel Ch. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the burst and single request mask status, or disables the +// corresponding channel from generating uDMA requests. +// +// Read as: +// Bit [Ch] = 0: External requests are enabled for channel Ch. +// Bit [Ch] = 1: External requests are disabled for channel Ch. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. +// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single +// request channel [C] input from generating uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable DMA request for the channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from +// generating requests. +// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the enable status of the channels, or enables the corresponding +// channels. +// +// Read as: +// Bit [Ch] = 0: Channel Ch is disabled. +// Bit [Ch] = 1: Channel Ch is enabled. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel +// Bit [Ch] = 1: Enables channel Ch +// +// Writing to a bit where a DMA channel is not implemented has no effect +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to disable the corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. +// Bit [Ch] = 1: Disables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel control data structure status, or selects the alternate +// data structure for the corresponding uDMA channel. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. +// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel +// Bit [Ch] = 1: Selects the alternate data structure for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clears the appropriate bit to select the primary data structure for the +// corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate +// data structure. +// Bit [Ch] = 1: Selects the primary data structure for channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel priority mask status, or sets the channel priority to +// high. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. +// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch +// to the default priority level. +// Bit [Ch] = 1: Channel Ch uses the high priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clear the appropriate bit to select the default priority level for the +// specified uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to +// the high priority level. +// Bit [Ch] = 1: Channel Ch uses the default priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_ERROR +// +//***************************************************************************** +// Field: [0] STATUS +// +// Returns the status of bus error flag in uDMA, or clears this bit +// +// Read as: +// +// 0: No bus error detected +// 1: Bus error detected +// +// Write as: +// +// 0: No effect, status of bus error flag is unchanged. +// 1: Clears the bus error flag. +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_REQDONE +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Reflects the uDMA done status for the given channel, channel [Ch]. It's a +// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. +// +// Read as: +// Bit [Ch] = 0: Request has not completed for channel Ch +// Bit [Ch] = 1: Request has completed for the channel Ch +// +// Writing a 1 to individual bits would clear the corresponding bit. +// +// Write as: +// Bit [Ch] = 0: No effect. +// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_DONEMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Controls the propagation of the uDMA done and active state to the assigned +// peripheral. Specifically used for software channels. +// +// Read as: +// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is blocked from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is not blocked from +// contributing to generation of combined uDMA done signal +// +// Write as: +// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the +// peripherals. +// Note that this disables uDMA done state for channel [Ch] from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the +// peripherals. +// Note that this enables uDMA done for channel [Ch] to contribute to +// generation of combined uDMA done signal. +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 + + +#endif // __UDMA__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_vims.h b/os/common/ext/TI/devices/cc13x0/inc/hw_vims.h new file mode 100644 index 0000000000..790d5752d1 --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_vims.h @@ -0,0 +1,206 @@ +/****************************************************************************** +* Filename: hw_vims_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_VIMS_H__ +#define __HW_VIMS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Status +#define VIMS_O_STAT 0x00000000 + +// Control +#define VIMS_O_CTL 0x00000004 + +//***************************************************************************** +// +// Register: VIMS_O_STAT +// +//***************************************************************************** +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer status +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 + +// Field: [3] MODE_CHANGING +// +// VIMS mode change status +// +// 0: VIMS is in the mode defined by MODE +// 1: VIMS is in the process of changing to the mode given in CTL.MODE +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 + +// Field: [2] INV +// +// This bit is set when invalidation of the cache memory is active / ongoing +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 + +// Field: [1:0] MODE +// +// Current VIMS mode +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 + +//***************************************************************************** +// +// Register: VIMS_O_CTL +// +//***************************************************************************** +// Field: [31] STATS_CLR +// +// Set this bit to clear statistic counters. +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 + +// Field: [30] STATS_EN +// +// Set this bit to enable statistic counters. +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 + +// Field: [29] DYN_CG_EN +// +// 0: The in-built clock gate functionality is bypassed. +// 1: The in-built clock gate functionality is enabled, automatically gating +// the clock when not needed. +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 + +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 + +// Field: [3] ARB_CFG +// +// Icode/Dcode and sysbus arbitation scheme +// +// 0: Static arbitration (icode/docde > sysbus) +// 1: Round-robin arbitration +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 + +// Field: [2] PREF_EN +// +// Tag prefetch control +// +// 0: Disabled +// 1: Enabled +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 + +// Field: [1:0] MODE +// +// VIMS mode request. +// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set +// to 1. +// Note: Transaction from CACHE mode to GPRAM mode should be done through OFF +// mode to minimize flash block delay. +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 + + +#endif // __VIMS__ diff --git a/os/common/ext/TI/devices/cc13x0/inc/hw_wdt.h b/os/common/ext/TI/devices/cc13x0/inc/hw_wdt.h new file mode 100644 index 0000000000..b71797d9ce --- /dev/null +++ b/os/common/ext/TI/devices/cc13x0/inc/hw_wdt.h @@ -0,0 +1,290 @@ +/****************************************************************************** +* Filename: hw_wdt_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// WDT component +// +//***************************************************************************** +// Configuration +#define WDT_O_LOAD 0x00000000 + +// Current Count Value +#define WDT_O_VALUE 0x00000004 + +// Control +#define WDT_O_CTL 0x00000008 + +// Interrupt Clear +#define WDT_O_ICR 0x0000000C + +// Raw Interrupt Status +#define WDT_O_RIS 0x00000010 + +// Masked Interrupt Status +#define WDT_O_MIS 0x00000014 + +// Test Mode +#define WDT_O_TEST 0x00000418 + +// Interrupt Cause Test Mode +#define WDT_O_INT_CAUS 0x0000041C + +// Lock +#define WDT_O_LOCK 0x00000C00 + +//***************************************************************************** +// +// Register: WDT_O_LOAD +// +//***************************************************************************** +// Field: [31:0] WDTLOAD +// +// This register is the 32-bit interval value used by the 32-bit counter. When +// this register is written, the value is immediately loaded and the counter is +// restarted to count down from the new value. If this register is loaded with +// 0x0000.0000, an interrupt is immediately generated. +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 + +//***************************************************************************** +// +// Register: WDT_O_VALUE +// +//***************************************************************************** +// Field: [31:0] WDTVALUE +// +// This register contains the current count value of the timer. +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 + +//***************************************************************************** +// +// Register: WDT_O_CTL +// +//***************************************************************************** +// Field: [2] INTTYPE +// +// WDT Interrupt Type +// +// 0: WDT interrupt is a standard interrupt. +// 1: WDT interrupt is a non-maskable interrupt. +// ENUMs: +// NONMASKABLE Non-maskable interrupt +// MASKABLE Maskable interrupt +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 + +// Field: [1] RESEN +// +// WDT Reset Enable. Defines the function of the WDT reset source (see +// PRCM:WARMRESET.WDT_STAT if enabled) +// +// 0: Disabled. +// 1: Enable the Watchdog reset output. +// ENUMs: +// EN Reset output Enabled +// DIS Reset output Disabled +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 + +// Field: [0] INTEN +// +// WDT Interrupt Enable +// +// 0: Interrupt event disabled. +// 1: Interrupt event enabled. Once set, this bit can only be cleared by a +// hardware reset. +// ENUMs: +// EN Interrupt Enabled +// DIS Interrupt Disabled +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_ICR +// +//***************************************************************************** +// Field: [31:0] WDTICR +// +// This register is the interrupt clear register. A write of any value to this +// register clears the WDT interrupt and reloads the 32-bit counter from the +// LOAD register. +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_RIS +// +//***************************************************************************** +// Field: [0] WDTRIS +// +// This register is the raw interrupt status register. WDT interrupt events can +// be monitored via this register if the controller interrupt is masked. +// +// Value Description +// +// 0: The WDT has not timed out +// 1: A WDT time-out event has occurred +// +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_MIS +// +//***************************************************************************** +// Field: [0] WDTMIS +// +// This register is the masked interrupt status register. The value of this +// register is the logical AND of the raw interrupt bit and the WDT interrupt +// enable bit CTL.INTEN. +// +// Value Description +// +// 0: The WDT has not timed out or is masked. +// 1: An unmasked WDT time-out event has occurred. +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_TEST +// +//***************************************************************************** +// Field: [8] STALL +// +// WDT Stall Enable +// +// 0: The WDT timer continues counting if the CPU is stopped with a debugger. +// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the +// CPU is restarted, the WDT resumes counting. +// ENUMs: +// EN Enable STALL +// DIS Disable STALL +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 + +// Field: [0] TEST_EN +// +// The test enable bit +// +// 0: Enable external reset +// 1: Disables the generation of an external reset. Instead bit 1 of the +// INT_CAUS register is set and an interrupt is generated +// ENUMs: +// EN Test mode Enabled +// DIS Test mode Disabled +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_INT_CAUS +// +//***************************************************************************** +// Field: [1] CAUSE_RESET +// +// Indicates that the cause of an interrupt was a reset generated but blocked +// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 + +// Field: [0] CAUSE_INTR +// +// Replica of RIS.WDTRIS +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_LOCK +// +//***************************************************************************** +// Field: [31:0] WDTLOCK +// +// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers +// for write access. A write of any other value reapplies the lock, preventing +// any register updates (NOTE: TEST.TEST_EN bit is not lockable). +// +// A read of this register returns the following values: +// +// 0x0000.0000: Unlocked +// 0x0000.0001: Locked +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 + + +#endif // __WDT__ diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F128.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F128.ld new file mode 100644 index 0000000000..5725f1615d --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F128.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xC3 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 128k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 16k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F32.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F32.ld new file mode 100644 index 0000000000..829ecd005b --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F32.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xC3 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 32k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 16k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F64.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F64.ld new file mode 100644 index 0000000000..ec10ebf00c --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/CC13X0F64.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xC3 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 64k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 16k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG14PXF128.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG14PXF128.ld new file mode 100644 index 0000000000..f6be5c0b63 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG14PXF128.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P23XF128 memory setup. + */ +MEMORY { + flash0 (rx) : org = 0x00000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (rwx) : org = 0x20000000, len = 16k + ram1 (rwx) : org = 0x00000000, len = 0 + ram2 (rwx) : org = 0x00000000, len = 0 + ram3 (rwx) : org = 0x00000000, len = 0 + ram4 (rwx) : org = 0x00000000, len = 0 + ram5 (rwx) : org = 0x00000000, len = 0 + ram6 (rwx) : org = 0x00000000, len = 0 + ram7 (rwx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG14PXF256.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG14PXF256.ld new file mode 100644 index 0000000000..335cf0abf2 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG14PXF256.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P23XF256 memory setup. + */ +MEMORY { + flash0 (rx) : org = 0x00000000, len = 256k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (rwx) : org = 0x20000000, len = 32k + ram1 (rwx) : org = 0x00000000, len = 0 + ram2 (rwx) : org = 0x00000000, len = 0 + ram3 (rwx) : org = 0x00000000, len = 0 + ram4 (rwx) : org = 0x00000000, len = 0 + ram5 (rwx) : org = 0x00000000, len = 0 + ram6 (rwx) : org = 0x00000000, len = 0 + ram7 (rwx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF128.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF128.ld new file mode 100644 index 0000000000..29f82ca34b --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF128.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG23XF128 memory setup. + */ +MEMORY { + flash0 (rx) : org = 0x08000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (rwx) : org = 0x20000000, len = 32k + ram1 (rwx) : org = 0x00000000, len = 0 + ram2 (rwx) : org = 0x00000000, len = 0 + ram3 (rwx) : org = 0x00000000, len = 0 + ram4 (rwx) : org = 0x00000000, len = 0 + ram5 (rwx) : org = 0x00000000, len = 0 + ram6 (rwx) : org = 0x00000000, len = 0 + ram7 (rwx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF256.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF256.ld new file mode 100644 index 0000000000..080b47e968 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF256.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG23XF256 memory setup. + */ +MEMORY { + flash0 (rx) : org = 0x08000000, len = 256k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (rwx) : org = 0x20000000, len = 32k + ram1 (rwx) : org = 0x00000000, len = 0 + ram2 (rwx) : org = 0x00000000, len = 0 + ram3 (rwx) : org = 0x00000000, len = 0 + ram4 (rwx) : org = 0x00000000, len = 0 + ram5 (rwx) : org = 0x00000000, len = 0 + ram6 (rwx) : org = 0x00000000, len = 0 + ram7 (rwx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF512.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF512.ld new file mode 100644 index 0000000000..7f00177746 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/EFR32FG23XF512.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG23XF512 memory setup. + */ +MEMORY { + flash0 (rx) : org = 0x08000000, len = 512k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (rwx) : org = 0x20000000, len = 64k + ram1 (rwx) : org = 0x00000000, len = 0 + ram2 (rwx) : org = 0x00000000, len = 0 + ram3 (rwx) : org = 0x00000000, len = 0 + ram4 (rwx) : org = 0x00000000, len = 0 + ram5 (rwx) : org = 0x00000000, len = 0 + ram6 (rwx) : org = 0x00000000, len = 0 + ram7 (rwx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_cc13x0fxx.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_cc13x0fxx.mk new file mode 100644 index 0000000000..6866a3fac6 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_cc13x0fxx.mk @@ -0,0 +1,22 @@ +# ChibiOS/RT - Copyright (c) 2023 Xael South +# startup_cc13x0fxx.mk - Makefile for TI CC13x0Fxx series uC. + + +# List of the ChibiOS generic CC13x0Fxx startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/CC13x0Fxx \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/TI/devices/cc13x0 + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg14p23x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg14p23x.mk new file mode 100644 index 0000000000..8678531999 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg14p23x.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic EFR32FG14P startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/SiliconLabs/EFR32FG14P/Source/system_efr32fg14p.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/EFR32FG14P \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/SiliconLabs/EFR32FG14P/Include + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk new file mode 100644 index 0000000000..7f4eeb215c --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk @@ -0,0 +1,19 @@ +# List of the ChibiOS generic EFR32FG23 startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-ml.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/EFR32FG23 \ + $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/Device/SiliconLabs/EFR32FG23/Include + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/devices/CC13x0Fxx/cmparams.h b/os/common/startup/ARMCMx/devices/CC13x0Fxx/cmparams.h new file mode 100644 index 0000000000..16a38b3d76 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/CC13x0Fxx/cmparams.h @@ -0,0 +1,137 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CC13x0Fxx/cmparams.h + * @brief ARM Cortex-M3 parameters for the CC13x0Fxx. + * + * @defgroup ARMCMx_CC13x0Fxx CC13x0Fxx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * CC13x0Fxx platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/* Defines required for correct CMSIS header functioning */ +#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 0U /*!< Does not provides MPU */ +#define __NVIC_PRIO_BITS 3U /*!< Uses 3 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 3 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the include file.*/ +#if !defined (CC1310F128RGZ_R20) && !defined (CC1310F128RGZ) && \ + !defined (CC1310F128RHB_R20) && !defined (CC1310F128RHB) && \ + !defined (CC1310F128RSM_R20) && !defined (CC1310F128RSM) && \ + !defined (CC1310F128_R20) && !defined (CC1310F128) && \ + !defined (CC1312R1FRGZ_R10) && !defined (CC1312R1FRGZ) && \ + !defined (CC1312R1F_R10) && !defined (CC1312R1F) +#include "board.h" +#endif + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 56 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** CC13x0 specific Interrupt Numbers ***********************************************************/ + EXTI_IRQn = 0, /*!< GPIO edge detect */ + I2C_IRQn = 1, /*!< I2C Event Interrup */ + RFCP1_IRQn = 2, /*!< RF Core and packet engine 1 */ + RTC_IRQn = 4, /*!< AON RTC */ + USART1_IRQn = 5, /*!< USART1 global Interrupt */ + USART2_IRQn = 6, /*!< USART2 global Interrupt */ + +} IRQn_Type; + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "core_cm3.h" + +/* Including the TivaWare peripheral headers.*/ +#include "inc/hw_chip_def.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_nvic.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_gpio.h" +#include "inc/hw_uart.h" +#include "inc/hw_i2c.h" +#include "inc/hw_wdt.h" +#include "inc/hw_ssi.h" +#include "inc/hw_udma.h" +#include "inc/hw_ddi_0_osc.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_HAS_FPU != __FPU_PRESENT +#error "CMSIS __FPU_PRESENT mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/EFR32FG14P/cmparams.h b/os/common/startup/ARMCMx/devices/EFR32FG14P/cmparams.h new file mode 100644 index 0000000000..2d589f64cf --- /dev/null +++ b/os/common/startup/ARMCMx/devices/EFR32FG14P/cmparams.h @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2023 Xael South + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file EFR32FG14P23x/cmparams.h + * @brief ARM Cortex-M4 parameters for the SiLabs EFR32FG14P23x. + * + * @defgroup ARMCMx_EFR32FG14P23x SiLabs EFR32FG14P23x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * SiLabs EFR32FG14P23x platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 40 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#if !defined(EFR32FG14P231F128GM48) && !defined(EFR32FG14P231F256GM32) && \ + !defined(EFR32FG14P231F256GM48) && !defined(EFR32FG14P231F256IM32) && \ + !defined(EFR32FG14P231F256IM48) && !defined(EFR32FG14P232F128GM32) && \ + !defined(EFR32FG14P232F128GM48) && !defined(EFR32FG14P232F256GM32) && \ + !defined(EFR32FG14P232F256GM48) && !defined(EFR32FG14P233F128GM48) && \ + !defined(EFR32FG14P233F256GM48) +#include "board.h" +#endif + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "em_device.h" + +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/EFR32FG23/cmparams.h b/os/common/startup/ARMCMx/devices/EFR32FG23/cmparams.h new file mode 100644 index 0000000000..0a8d0dd28d --- /dev/null +++ b/os/common/startup/ARMCMx/devices/EFR32FG23/cmparams.h @@ -0,0 +1,100 @@ +/* + ChibiOS/RT - Copyright (C) 2023 Xael South + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file EFR32FG14P23x/cmparams.h + * @brief ARM Cortex-M4 parameters for the SiLabs EFR32FG14P23x. + * + * @defgroup ARMCMx_EFR32FG14P23x SiLabs EFR32FG14P23x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * SiLabs EFR32FG14P23x platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 33U + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4U + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 80 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#if !defined(EFR32FG23A010F128GM40) && !defined(EFR32FG23A010F256GM40) && \ + !defined(EFR32FG23A010F256GM48) && !defined(EFR32FG23A010F512GM40) && \ + !defined(EFR32FG23A010F512GM48) && !defined(EFR32FG23A011F512GM40) && \ + !defined(EFR32FG23A020F128GM40) && !defined(EFR32FG23A020F256GM40) && \ + !defined(EFR32FG23A020F256GM48) && !defined(EFR32FG23A020F512GM40) && \ + !defined(EFR32FG23A020F512GM48) && !defined(EFR32FG23A021F512GM40) && \ + !defined(EFR32FG23B010F128GM40) && !defined(EFR32FG23B010F512GM48) && \ + !defined(EFR32FG23B010F512IM40) && !defined(EFR32FG23B010F512IM48) && \ + !defined(EFR32FG23B020F128GM40) && !defined(EFR32FG23B020F512IM40) && \ + !defined(EFR32FG23B020F512IM48) && !defined(EFR32FG23B021F512IM40) && \ + !defined(EFR32FG23B021F512IM48) +#include "board.h" +#endif + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "em_device.h" + +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#if CORTEX_NUM_VECTORS < EXT_IRQ_COUNT +#error "CORTEX_NUM_VECTORS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.c b/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.c new file mode 100644 index 0000000000..e656ea67a0 --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.c @@ -0,0 +1,74 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + .PAData = { + .ctrlr = PAL_EFR32_PORTA_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTA_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTA_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTA_DOUT_DEFAULT + }, + + .PBData = { + .ctrlr = PAL_EFR32_PORTB_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTB_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTB_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTB_DOUT_DEFAULT + }, + + .PCData = { + .ctrlr = PAL_EFR32_PORTC_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTC_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTC_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTC_DOUT_DEFAULT + }, + + .PDData = { + .ctrlr = PAL_EFR32_PORTD_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTD_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTD_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTD_DOUT_DEFAULT + }, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + efr32_escape_hatch(); + efr32_chip_init(); + efr32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.h b/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.h new file mode 100644 index 0000000000..41a1a9e18d --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.h @@ -0,0 +1,64 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Board identifier. + */ +#define BOARD_SILABS_EFR32FG23_BRD4001A_REVA01 +#define BOARD_NAME "SILABS_EFR32FG23_BRD4001A_REVA01" + +/* + * Board frequencies. + */ + +#if !defined(EFR32_LFXO_FREQ) +#define EFR32_LFXO_FREQ 32768UL +#define LFXO_RTC_GAIN_DEFAULT_VALUE 0x02UL /**< Manually estmated value which gave 32.768 kHz on CLKOUTn pin. */ +#define LFXO_RTC_CAPTUNE_DEFAULT_VALUE 0x1CUL /**< Manually estmated value which gave 32.768 kHz on CLKOUTn pin. */ +#endif + +#if !defined(EFR32_HFXO_FREQ) +#define EFR32_HFXO_FREQ 39000000UL +#endif + +#if !defined(EFR32_CLKIN0_FREQ) +#define EFR32_CLKIN0_FREQ 0UL +#endif + +#define ESCAPE_HATCH_PORT GPIO_PORTC +#define ESCAPE_HATCH_PIN 3 + +/* + * MCU type as defined in the Silicon Labs header. + */ +#if !defined(EFR32FG23A010F256GM48) +#define EFR32FG23A010F256GM48 1 +#endif + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.mk b/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.mk new file mode 100644 index 0000000000..ffa25fa562 --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SILABS_EFR32FG23_BRD4001A_REVA01 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.c b/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.c new file mode 100644 index 0000000000..90149a5eb1 --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.c @@ -0,0 +1,74 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + .PAData = { + .ctrlr = PAL_EFR32_PORTA_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTA_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTA_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTA_DOUT_DEFAULT + }, + + .PBData = { + .ctrlr = PAL_EFR32_PORTB_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTB_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTB_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTB_DOUT_DEFAULT + }, + + .PCData = { + .ctrlr = PAL_EFR32_PORTC_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTC_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTC_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTC_DOUT_DEFAULT + }, + + .PDData = { + .ctrlr = PAL_EFR32_PORTD_CTRL_DEFAULT, + .modelr = PAL_EFR32_PORTD_MODEL_DEFAULT, + .modehr = PAL_EFR32_PORTD_MODEH_DEFAULT, + .doutr = PAL_EFR32_PORTD_DOUT_DEFAULT + }, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + efr32_escape_hatch(); + efr32_chip_init(); + efr32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.h b/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.h new file mode 100644 index 0000000000..23113560d1 --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.h @@ -0,0 +1,106 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Board identifier. + */ +#define BOARD_SILABS_EFR32FG23_DK2600A +#define BOARD_NAME "BOARD_SILABS_EFR32FG23_DK2600A" + +/* + * Board frequencies. + */ + +#if defined(LFXO_FREQ) +#define EFR32_LFXO_FREQ LFXO_FREQ +#endif + +#if !defined(EFR32_LFXO_FREQ) +#define EFR32_LFXO_FREQ 32768UL +#endif + +#if defined(HFXO_FREQ) +#define EFR32_HFXO_FREQ HFXO_FREQ +#endif + +#if !defined(EFR32_HFXO_FREQ) +#define EFR32_HFXO_FREQ 39000000UL +#endif + +#if defined(CLKIN0_FREQ) +#define EFR32_CLKIN0_FREQ CLKIN0_FREQ +#endif + +#if !defined(EFR32_CLKIN0_FREQ) +#define EFR32_CLKIN0_FREQ 0UL +#endif + +#if defined(LFRCO_FREQ) +#define EFR32_LFRCO_FREQ LFRCO_FREQ +#endif + +#if !defined(EFR32_LFRCO_FREQ) +#define EFR32_LFRCO_FREQ 32768UL +#endif + +#if defined(FSRCO_FREQ) +#define EFR32_FSRCO_FREQ FSRCO_FREQ +#endif + +#if !defined(EFR32_FSRCO_FREQ) +#define EFR32_FSRCO_FREQ 20000000UL +#endif + +/* + * Board calibration values. + */ + +/** LFXO default gain value manually estmated by measuring 32.768 kHz on CLKOUTn pin. */ +#define LFXO_RTC_GAIN_DEFAULT_VALUE 0x02UL + +/** LFXO captune default value manually estmated by measuring 32.768 kHz on CLKOUTn pin. */ +#define LFXO_RTC_CAPTUNE_DEFAULT_VALUE 0x1CUL + + +/* + * Hatch port and pin to get into debugger on startup. + */ + +/** PA5 is BUTTON1 used for debug escape. */ +#define ESCAPE_HATCH_PORT GPIO_PORTA +#define ESCAPE_HATCH_PIN 5 + +/* + * MCU type as defined in the Silicon Labs header. + */ +#if !defined(EFR32FG23B010F512IM48) +#define EFR32FG23B010F512IM48 1 +#endif + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk b/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk new file mode 100644 index 0000000000..9a6b4a5716 --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SILABS_EFR32FG23_DK2600A + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/SILABS_EFR32FG23_DK2600A/readme.txt b/os/hal/boards/SILABS_EFR32FG23_DK2600A/readme.txt new file mode 100644 index 0000000000..69190ddffc --- /dev/null +++ b/os/hal/boards/SILABS_EFR32FG23_DK2600A/readme.txt @@ -0,0 +1,8 @@ +FG23-DK2600A with EFR32FG23B010F512IM48 is EFR32FG23 868-915 MHz +14 dBm Dev Kit +================================================================================ + +The EFR32FG23 development board is a compact, feature-packed development +platform. It provides the fastest path to develop and prototype sub-GHz +IoT products. The development platform includes support for the FG23’s +onboard segment LCD controller and other key features including LESENSE +and pulse counter. diff --git a/os/hal/boards/SILABS_SLWSTK6061B/board.c b/os/hal/boards/SILABS_SLWSTK6061B/board.c new file mode 100644 index 0000000000..381f3c07c9 --- /dev/null +++ b/os/hal/boards/SILABS_SLWSTK6061B/board.c @@ -0,0 +1,34 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + efr32_escape_hatch(); + efr32_chip_init(); + efr32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/SILABS_SLWSTK6061B/board.h b/os/hal/boards/SILABS_SLWSTK6061B/board.h new file mode 100644 index 0000000000..34d0acd20f --- /dev/null +++ b/os/hal/boards/SILABS_SLWSTK6061B/board.h @@ -0,0 +1,58 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Board identifier. + */ +#define BOARD_SILABS_SLWSTK6061B +#define BOARD_NAME "SLWSTK6061B EFR32FG 868 MHz 2.4 GHz and Sub-GHz Starter Kit" + +/* + * Board frequencies. + */ + +#if !defined(EFR32_LFXO_FREQ) +#define EFR32_LFXO_FREQ (32768UL) +#endif + +#if !defined(EFR32_HFXO_FREQ) +#define EFR32_HFXO_FREQ (38400000UL) +#endif + +#define GPIO_ESCAPE_HATCH_PORT gpioPortB +#define GPIO_ESCAPE_HATCH_PIN 0 + +/* + * MCU type as defined in the Silicon Labs header. + */ +#if !defined(EFR32FG14P233F256GM48) +#define EFR32FG14P233F256GM48 1 +#endif + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SILABS_SLWSTK6061B/board.mk b/os/hal/boards/SILABS_SLWSTK6061B/board.mk new file mode 100644 index 0000000000..14cabf789c --- /dev/null +++ b/os/hal/boards/SILABS_SLWSTK6061B/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SILABS_SLWSTK6061B/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SILABS_SLWSTK6061B + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.c b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.c new file mode 100644 index 0000000000..74e05f3a48 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.c @@ -0,0 +1,281 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; + uint32_t ascr; + uint32_t lockr; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, + VAL_GPIOA_LOCKR}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, + VAL_GPIOB_LOCKR}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, + VAL_GPIOC_LOCKR}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, + VAL_GPIOD_LOCKR}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, + VAL_GPIOE_LOCKR}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, + VAL_GPIOF_LOCKR}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, + VAL_GPIOG_LOCKR}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, + VAL_GPIOH_LOCKR}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, + VAL_GPIOI_LOCKR}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, + VAL_GPIOJ_LOCKR}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, + VAL_GPIOK_LOCKR} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->ASCR = config->ascr; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; + gpiop->LOCKR = config->lockr; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB2(STM32_GPIO_EN_MASK); + rccEnableAHB2(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.h b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.h new file mode 100644 index 0000000000..7bf9fd7cae --- /dev/null +++ b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.h @@ -0,0 +1,1527 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo64-L476RG board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO64_L476RG +#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32L476xx + +/* + * IO pins assignments. + */ +#define GPIOA_ARD_A0 0U +#define GPIOA_ACD12_IN5 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_ACD12_IN6 1U +#define GPIOA_MODEM_STAT 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_USART2_TX 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_USART2_RX 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ACD12_IN9 4U +#define GPIOA_MODEM_RST 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_LED_GREEN 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U +#define GPIOA_W5500_INT 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_ARD_A3 0U +#define GPIOB_ACD12_IN15 0U +#define GPIOB_W5500_RST 0U +#define GPIOB_PIN1 1U +#define GPIOB_USER_UART_CTS 2U +#define GPIOB_ARD_D3 3U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U +#define GPIOB_ARD_D10 6U +#define GPIOB_SPI1_CS 6U +#define GPIOB_W5500_NSS 6U +#define GPIOB_PIN7 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_LPUART1_RX 10U +#define GPIOB_LPUART1_TX 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ACD123_IN1 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ACD123_IN2 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_ARD_D9 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) +#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U) +#define LINE_MODEM_STAT PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U) +#define LINE_MODEM_RST PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_W5500_INT PAL_LINE(GPIOA, 10U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U) +#define LINE_W5500_RST PAL_LINE(GPIOB, 0U) +#define LINE_USER_UART_CTS PAL_LINE(GPIOB, 2U) +#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) +#define LINE_SPI1_CS PAL_LINE(GPIOB, 6U) +#define LINE_W5500_NSS PAL_LINE(GPIOB, 6U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) +#define LINE_LPUART1_RX PAL_LINE(GPIOB, 10U) +#define LINE_LPUART1_TX PAL_LINE(GPIOB, 11U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_ASCR_DISABLED(n) (0U << (n)) +#define PIN_ASCR_ENABLED(n) (1U << (n)) +#define PIN_LOCKR_DISABLED(n) (0U << (n)) +#define PIN_LOCKR_ENABLED(n) (1U << (n)) + +/* + * GPIOA setup: + * + * PA0 - ARD_A0 ACD12_IN5 (analog). + * PA1 - ARD_A1 ACD12_IN6 MODEM_STAT(input pulldown). + * PA2 - ARD_D1 USART2_TX (alternate 7). + * PA3 - ARD_D0 USART2_RX (alternate 7). + * PA4 - ARD_A2 ACD12_IN9 MODEM_RST(output pushpull maximum). + * PA5 - ARD_D13 LED_GREEN SPI1_SCK(alternate 5). + * PA6 - ARD_D12 SPI1_MISO (alternate 5). + * PA7 - ARD_D11 SPI1_MOSI (alternate 5). + * PA8 - ARD_D7 (analog). + * PA9 - ARD_D8 (analog). + * PA10 - ARD_D2 W5500_INT (input pullup). + * PA11 - PIN11 (analog). + * PA12 - PIN12 (analog). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (analog). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \ + PIN_MODE_OUTPUT(GPIOA_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D13) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D12) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D11) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D7) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D8) | \ + PIN_MODE_INPUT(GPIOA_ARD_D2) | \ + PIN_MODE_ANALOG(GPIOA_PIN11) | \ + PIN_MODE_ANALOG(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ANALOG(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ + PIN_OSPEED_HIGH(GPIOA_PIN11) | \ + PIN_OSPEED_HIGH(GPIOA_PIN12) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLDOWN(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A2) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_ARD_D7) | \ + PIN_ODR_HIGH(GPIOA_ARD_D8) | \ + PIN_ODR_HIGH(GPIOA_ARD_D2) | \ + PIN_ODR_HIGH(GPIOA_PIN11) | \ + PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 5U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 5U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) +#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \ + PIN_ASCR_DISABLED(GPIOA_PIN11) | \ + PIN_ASCR_DISABLED(GPIOA_PIN12) | \ + PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ + PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ + PIN_ASCR_DISABLED(GPIOA_PIN15)) +#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ + PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN15)) + +/* + * GPIOB setup: + * + * PB0 - ARD_A3 ACD12_IN15 W5500_RST(output pushpull maximum). + * PB1 - PIN1 (analog). + * PB2 - USER_UART_CTS (input pullup). + * PB3 - ARD_D3 SWO (alternate 0). + * PB4 - ARD_D5 (analog). + * PB5 - ARD_D4 (analog). + * PB6 - ARD_D10 SPI1_CS W5500_NSS (output pushpull maximum). + * PB7 - PIN7 (analog). + * PB8 - ARD_D15 (analog). + * PB9 - ARD_D14 (analog). + * PB10 - ARD_D6 LPUART1_RX (alternate 8). + * PB11 - LPUART1_TX (alternate 8). + * PB12 - PIN12 (analog). + * PB13 - PIN13 (analog). + * PB14 - PIN14 (analog). + * PB15 - PIN15 (analog). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ARD_A3) | \ + PIN_MODE_ANALOG(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_USER_UART_CTS) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D3) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D5) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D4) | \ + PIN_MODE_OUTPUT(GPIOB_ARD_D10) | \ + PIN_MODE_ANALOG(GPIOB_PIN7) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D15) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D14) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D6) | \ + PIN_MODE_ALTERNATE(GPIOB_LPUART1_TX) | \ + PIN_MODE_ANALOG(GPIOB_PIN12) | \ + PIN_MODE_ANALOG(GPIOB_PIN13) | \ + PIN_MODE_ANALOG(GPIOB_PIN14) | \ + PIN_MODE_ANALOG(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_USER_UART_CTS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LPUART1_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_USER_UART_CTS) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOB_LPUART1_TX) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_USER_UART_CTS) |\ + PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D10) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \ + PIN_PUPDR_FLOATING(GPIOB_LPUART1_TX) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_USER_UART_CTS) | \ + PIN_ODR_HIGH(GPIOB_ARD_D3) | \ + PIN_ODR_HIGH(GPIOB_ARD_D5) | \ + PIN_ODR_HIGH(GPIOB_ARD_D4) | \ + PIN_ODR_HIGH(GPIOB_ARD_D10) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_ARD_D15) | \ + PIN_ODR_HIGH(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ARD_D6) | \ + PIN_ODR_HIGH(GPIOB_LPUART1_TX) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_USER_UART_CTS, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D6, 8U) | \ + PIN_AFIO_AF(GPIOB_LPUART1_TX, 8U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) +#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_A3) | \ + PIN_ASCR_DISABLED(GPIOB_PIN1) | \ + PIN_ASCR_DISABLED(GPIOB_USER_UART_CTS) |\ + PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D10) | \ + PIN_ASCR_DISABLED(GPIOB_PIN7) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \ + PIN_ASCR_DISABLED(GPIOB_LPUART1_TX) | \ + PIN_ASCR_DISABLED(GPIOB_PIN12) | \ + PIN_ASCR_DISABLED(GPIOB_PIN13) | \ + PIN_ASCR_DISABLED(GPIOB_PIN14) | \ + PIN_ASCR_DISABLED(GPIOB_PIN15)) +#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOB_USER_UART_CTS) |\ + PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D10) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \ + PIN_LOCKR_DISABLED(GPIOB_LPUART1_TX) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN15)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A5 ACD123_IN1 (analog). + * PC1 - ARD_A4 ACD123_IN2 (analog). + * PC2 - PIN2 (analog). + * PC3 - PIN3 (analog). + * PC4 - PIN4 (analog). + * PC5 - PIN5 (analog). + * PC6 - PIN6 (analog). + * PC7 - ARD_D9 (analog). + * PC8 - PIN8 (analog). + * PC9 - PIN9 (analog). + * PC10 - PIN10 (analog). + * PC11 - PIN11 (analog). + * PC12 - PIN12 (analog). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A4) | \ + PIN_MODE_ANALOG(GPIOC_PIN2) | \ + PIN_MODE_ANALOG(GPIOC_PIN3) | \ + PIN_MODE_ANALOG(GPIOC_PIN4) | \ + PIN_MODE_ANALOG(GPIOC_PIN5) | \ + PIN_MODE_ANALOG(GPIOC_PIN6) | \ + PIN_MODE_ANALOG(GPIOC_ARD_D9) | \ + PIN_MODE_ANALOG(GPIOC_PIN8) | \ + PIN_MODE_ANALOG(GPIOC_PIN9) | \ + PIN_MODE_ANALOG(GPIOC_PIN10) | \ + PIN_MODE_ANALOG(GPIOC_PIN11) | \ + PIN_MODE_ANALOG(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \ + PIN_ODR_HIGH(GPIOC_ARD_A4) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_ARD_D9) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D9, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) +#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A5) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_A4) | \ + PIN_ASCR_DISABLED(GPIOC_PIN2) | \ + PIN_ASCR_DISABLED(GPIOC_PIN3) | \ + PIN_ASCR_DISABLED(GPIOC_PIN4) | \ + PIN_ASCR_DISABLED(GPIOC_PIN5) | \ + PIN_ASCR_DISABLED(GPIOC_PIN6) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_D9) | \ + PIN_ASCR_DISABLED(GPIOC_PIN8) | \ + PIN_ASCR_DISABLED(GPIOC_PIN9) | \ + PIN_ASCR_DISABLED(GPIOC_PIN10) | \ + PIN_ASCR_DISABLED(GPIOC_PIN11) | \ + PIN_ASCR_DISABLED(GPIOC_PIN12) | \ + PIN_ASCR_DISABLED(GPIOC_BUTTON) | \ + PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \ + PIN_ASCR_DISABLED(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_A4) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_D9) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \ + PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \ + PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (analog). + * PD1 - PIN1 (analog). + * PD2 - PIN2 (analog). + * PD3 - PIN3 (analog). + * PD4 - PIN4 (analog). + * PD5 - PIN5 (analog). + * PD6 - PIN6 (analog). + * PD7 - PIN7 (analog). + * PD8 - PIN8 (analog). + * PD9 - PIN9 (analog). + * PD10 - PIN10 (analog). + * PD11 - PIN11 (analog). + * PD12 - PIN12 (analog). + * PD13 - PIN13 (analog). + * PD14 - PIN14 (analog). + * PD15 - PIN15 (analog). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ + PIN_MODE_ANALOG(GPIOD_PIN1) | \ + PIN_MODE_ANALOG(GPIOD_PIN2) | \ + PIN_MODE_ANALOG(GPIOD_PIN3) | \ + PIN_MODE_ANALOG(GPIOD_PIN4) | \ + PIN_MODE_ANALOG(GPIOD_PIN5) | \ + PIN_MODE_ANALOG(GPIOD_PIN6) | \ + PIN_MODE_ANALOG(GPIOD_PIN7) | \ + PIN_MODE_ANALOG(GPIOD_PIN8) | \ + PIN_MODE_ANALOG(GPIOD_PIN9) | \ + PIN_MODE_ANALOG(GPIOD_PIN10) | \ + PIN_MODE_ANALOG(GPIOD_PIN11) | \ + PIN_MODE_ANALOG(GPIOD_PIN12) | \ + PIN_MODE_ANALOG(GPIOD_PIN13) | \ + PIN_MODE_ANALOG(GPIOD_PIN14) | \ + PIN_MODE_ANALOG(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) +#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ + PIN_ASCR_DISABLED(GPIOD_PIN1) | \ + PIN_ASCR_DISABLED(GPIOD_PIN2) | \ + PIN_ASCR_DISABLED(GPIOD_PIN3) | \ + PIN_ASCR_DISABLED(GPIOD_PIN4) | \ + PIN_ASCR_DISABLED(GPIOD_PIN5) | \ + PIN_ASCR_DISABLED(GPIOD_PIN6) | \ + PIN_ASCR_DISABLED(GPIOD_PIN7) | \ + PIN_ASCR_DISABLED(GPIOD_PIN8) | \ + PIN_ASCR_DISABLED(GPIOD_PIN9) | \ + PIN_ASCR_DISABLED(GPIOD_PIN10) | \ + PIN_ASCR_DISABLED(GPIOD_PIN11) | \ + PIN_ASCR_DISABLED(GPIOD_PIN12) | \ + PIN_ASCR_DISABLED(GPIOD_PIN13) | \ + PIN_ASCR_DISABLED(GPIOD_PIN14) | \ + PIN_ASCR_DISABLED(GPIOD_PIN15)) +#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN15)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (analog). + * PE1 - PIN1 (analog). + * PE2 - PIN2 (analog). + * PE3 - PIN3 (analog). + * PE4 - PIN4 (analog). + * PE5 - PIN5 (analog). + * PE6 - PIN6 (analog). + * PE7 - PIN7 (analog). + * PE8 - PIN8 (analog). + * PE9 - PIN9 (analog). + * PE10 - PIN10 (analog). + * PE11 - PIN11 (analog). + * PE12 - PIN12 (analog). + * PE13 - PIN13 (analog). + * PE14 - PIN14 (analog). + * PE15 - PIN15 (analog). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ + PIN_MODE_ANALOG(GPIOE_PIN1) | \ + PIN_MODE_ANALOG(GPIOE_PIN2) | \ + PIN_MODE_ANALOG(GPIOE_PIN3) | \ + PIN_MODE_ANALOG(GPIOE_PIN4) | \ + PIN_MODE_ANALOG(GPIOE_PIN5) | \ + PIN_MODE_ANALOG(GPIOE_PIN6) | \ + PIN_MODE_ANALOG(GPIOE_PIN7) | \ + PIN_MODE_ANALOG(GPIOE_PIN8) | \ + PIN_MODE_ANALOG(GPIOE_PIN9) | \ + PIN_MODE_ANALOG(GPIOE_PIN10) | \ + PIN_MODE_ANALOG(GPIOE_PIN11) | \ + PIN_MODE_ANALOG(GPIOE_PIN12) | \ + PIN_MODE_ANALOG(GPIOE_PIN13) | \ + PIN_MODE_ANALOG(GPIOE_PIN14) | \ + PIN_MODE_ANALOG(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) +#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ + PIN_ASCR_DISABLED(GPIOE_PIN1) | \ + PIN_ASCR_DISABLED(GPIOE_PIN2) | \ + PIN_ASCR_DISABLED(GPIOE_PIN3) | \ + PIN_ASCR_DISABLED(GPIOE_PIN4) | \ + PIN_ASCR_DISABLED(GPIOE_PIN5) | \ + PIN_ASCR_DISABLED(GPIOE_PIN6) | \ + PIN_ASCR_DISABLED(GPIOE_PIN7) | \ + PIN_ASCR_DISABLED(GPIOE_PIN8) | \ + PIN_ASCR_DISABLED(GPIOE_PIN9) | \ + PIN_ASCR_DISABLED(GPIOE_PIN10) | \ + PIN_ASCR_DISABLED(GPIOE_PIN11) | \ + PIN_ASCR_DISABLED(GPIOE_PIN12) | \ + PIN_ASCR_DISABLED(GPIOE_PIN13) | \ + PIN_ASCR_DISABLED(GPIOE_PIN14) | \ + PIN_ASCR_DISABLED(GPIOE_PIN15)) +#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN15)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (analog). + * PF1 - PIN1 (analog). + * PF2 - PIN2 (analog). + * PF3 - PIN3 (analog). + * PF4 - PIN4 (analog). + * PF5 - PIN5 (analog). + * PF6 - PIN6 (analog). + * PF7 - PIN7 (analog). + * PF8 - PIN8 (analog). + * PF9 - PIN9 (analog). + * PF10 - PIN10 (analog). + * PF11 - PIN11 (analog). + * PF12 - PIN12 (analog). + * PF13 - PIN13 (analog). + * PF14 - PIN14 (analog). + * PF15 - PIN15 (analog). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ + PIN_MODE_ANALOG(GPIOF_PIN1) | \ + PIN_MODE_ANALOG(GPIOF_PIN2) | \ + PIN_MODE_ANALOG(GPIOF_PIN3) | \ + PIN_MODE_ANALOG(GPIOF_PIN4) | \ + PIN_MODE_ANALOG(GPIOF_PIN5) | \ + PIN_MODE_ANALOG(GPIOF_PIN6) | \ + PIN_MODE_ANALOG(GPIOF_PIN7) | \ + PIN_MODE_ANALOG(GPIOF_PIN8) | \ + PIN_MODE_ANALOG(GPIOF_PIN9) | \ + PIN_MODE_ANALOG(GPIOF_PIN10) | \ + PIN_MODE_ANALOG(GPIOF_PIN11) | \ + PIN_MODE_ANALOG(GPIOF_PIN12) | \ + PIN_MODE_ANALOG(GPIOF_PIN13) | \ + PIN_MODE_ANALOG(GPIOF_PIN14) | \ + PIN_MODE_ANALOG(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) +#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ + PIN_ASCR_DISABLED(GPIOF_PIN1) | \ + PIN_ASCR_DISABLED(GPIOF_PIN2) | \ + PIN_ASCR_DISABLED(GPIOF_PIN3) | \ + PIN_ASCR_DISABLED(GPIOF_PIN4) | \ + PIN_ASCR_DISABLED(GPIOF_PIN5) | \ + PIN_ASCR_DISABLED(GPIOF_PIN6) | \ + PIN_ASCR_DISABLED(GPIOF_PIN7) | \ + PIN_ASCR_DISABLED(GPIOF_PIN8) | \ + PIN_ASCR_DISABLED(GPIOF_PIN9) | \ + PIN_ASCR_DISABLED(GPIOF_PIN10) | \ + PIN_ASCR_DISABLED(GPIOF_PIN11) | \ + PIN_ASCR_DISABLED(GPIOF_PIN12) | \ + PIN_ASCR_DISABLED(GPIOF_PIN13) | \ + PIN_ASCR_DISABLED(GPIOF_PIN14) | \ + PIN_ASCR_DISABLED(GPIOF_PIN15)) +#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN15)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (analog). + * PG1 - PIN1 (analog). + * PG2 - PIN2 (analog). + * PG3 - PIN3 (analog). + * PG4 - PIN4 (analog). + * PG5 - PIN5 (analog). + * PG6 - PIN6 (analog). + * PG7 - PIN7 (analog). + * PG8 - PIN8 (analog). + * PG9 - PIN9 (analog). + * PG10 - PIN10 (analog). + * PG11 - PIN11 (analog). + * PG12 - PIN12 (analog). + * PG13 - PIN13 (analog). + * PG14 - PIN14 (analog). + * PG15 - PIN15 (analog). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ + PIN_MODE_ANALOG(GPIOG_PIN1) | \ + PIN_MODE_ANALOG(GPIOG_PIN2) | \ + PIN_MODE_ANALOG(GPIOG_PIN3) | \ + PIN_MODE_ANALOG(GPIOG_PIN4) | \ + PIN_MODE_ANALOG(GPIOG_PIN5) | \ + PIN_MODE_ANALOG(GPIOG_PIN6) | \ + PIN_MODE_ANALOG(GPIOG_PIN7) | \ + PIN_MODE_ANALOG(GPIOG_PIN8) | \ + PIN_MODE_ANALOG(GPIOG_PIN9) | \ + PIN_MODE_ANALOG(GPIOG_PIN10) | \ + PIN_MODE_ANALOG(GPIOG_PIN11) | \ + PIN_MODE_ANALOG(GPIOG_PIN12) | \ + PIN_MODE_ANALOG(GPIOG_PIN13) | \ + PIN_MODE_ANALOG(GPIOG_PIN14) | \ + PIN_MODE_ANALOG(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) +#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ + PIN_ASCR_DISABLED(GPIOG_PIN1) | \ + PIN_ASCR_DISABLED(GPIOG_PIN2) | \ + PIN_ASCR_DISABLED(GPIOG_PIN3) | \ + PIN_ASCR_DISABLED(GPIOG_PIN4) | \ + PIN_ASCR_DISABLED(GPIOG_PIN5) | \ + PIN_ASCR_DISABLED(GPIOG_PIN6) | \ + PIN_ASCR_DISABLED(GPIOG_PIN7) | \ + PIN_ASCR_DISABLED(GPIOG_PIN8) | \ + PIN_ASCR_DISABLED(GPIOG_PIN9) | \ + PIN_ASCR_DISABLED(GPIOG_PIN10) | \ + PIN_ASCR_DISABLED(GPIOG_PIN11) | \ + PIN_ASCR_DISABLED(GPIOG_PIN12) | \ + PIN_ASCR_DISABLED(GPIOG_PIN13) | \ + PIN_ASCR_DISABLED(GPIOG_PIN14) | \ + PIN_ASCR_DISABLED(GPIOG_PIN15)) +#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN15)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (analog). + * PH3 - PIN3 (analog). + * PH4 - PIN4 (analog). + * PH5 - PIN5 (analog). + * PH6 - PIN6 (analog). + * PH7 - PIN7 (analog). + * PH8 - PIN8 (analog). + * PH9 - PIN9 (analog). + * PH10 - PIN10 (analog). + * PH11 - PIN11 (analog). + * PH12 - PIN12 (analog). + * PH13 - PIN13 (analog). + * PH14 - PIN14 (analog). + * PH15 - PIN15 (analog). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_ANALOG(GPIOH_PIN2) | \ + PIN_MODE_ANALOG(GPIOH_PIN3) | \ + PIN_MODE_ANALOG(GPIOH_PIN4) | \ + PIN_MODE_ANALOG(GPIOH_PIN5) | \ + PIN_MODE_ANALOG(GPIOH_PIN6) | \ + PIN_MODE_ANALOG(GPIOH_PIN7) | \ + PIN_MODE_ANALOG(GPIOH_PIN8) | \ + PIN_MODE_ANALOG(GPIOH_PIN9) | \ + PIN_MODE_ANALOG(GPIOH_PIN10) | \ + PIN_MODE_ANALOG(GPIOH_PIN11) | \ + PIN_MODE_ANALOG(GPIOH_PIN12) | \ + PIN_MODE_ANALOG(GPIOH_PIN13) | \ + PIN_MODE_ANALOG(GPIOH_PIN14) | \ + PIN_MODE_ANALOG(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) +#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \ + PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \ + PIN_ASCR_DISABLED(GPIOH_PIN2) | \ + PIN_ASCR_DISABLED(GPIOH_PIN3) | \ + PIN_ASCR_DISABLED(GPIOH_PIN4) | \ + PIN_ASCR_DISABLED(GPIOH_PIN5) | \ + PIN_ASCR_DISABLED(GPIOH_PIN6) | \ + PIN_ASCR_DISABLED(GPIOH_PIN7) | \ + PIN_ASCR_DISABLED(GPIOH_PIN8) | \ + PIN_ASCR_DISABLED(GPIOH_PIN9) | \ + PIN_ASCR_DISABLED(GPIOH_PIN10) | \ + PIN_ASCR_DISABLED(GPIOH_PIN11) | \ + PIN_ASCR_DISABLED(GPIOH_PIN12) | \ + PIN_ASCR_DISABLED(GPIOH_PIN13) | \ + PIN_ASCR_DISABLED(GPIOH_PIN14) | \ + PIN_ASCR_DISABLED(GPIOH_PIN15)) +#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \ + PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN15)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.mk b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.mk new file mode 100644 index 0000000000..15fd98c21b --- /dev/null +++ b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/cfg/board.chcfg new file mode 100644 index 0000000000..d19e7e1d81 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/cfg/board.chcfg @@ -0,0 +1,1320 @@ + + + + + resources/gencfg/processors/boards/stm32l4xx/templates + .. + 5.0.x + + STMicroelectronics STM32 Nucleo64-L476RG + ST_NUCLEO64_L476RG + + STM32L476xx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/cfg/board.fmpp b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/cfg/board.fmpp new file mode 100644 index 0000000000..381659b4c7 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../../ChibiOS/tools/ftl/processors/boards/stm32l4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../../ChibiOS/tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/genboard.sh b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/genboard.sh new file mode 100755 index 0000000000..ec5aa8ddc6 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO64_L476RG_MIKROE_CLICK/genboard.sh @@ -0,0 +1,5 @@ +#!/bin/sh + +fmpp -C cfg/board.fmpp + +sed -i 's/$(CHIBIOS)/$(CHIBIOS_CONTRIB)/g' board.mk diff --git a/os/hal/boards/TI_CC1310_LAUNCHPAD/board.c b/os/hal/boards/TI_CC1310_LAUNCHPAD/board.c new file mode 100644 index 0000000000..77b90cc760 --- /dev/null +++ b/os/hal/boards/TI_CC1310_LAUNCHPAD/board.c @@ -0,0 +1,47 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) +{ + ti_clock_init(); +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) +{ +} diff --git a/os/hal/boards/TI_CC1310_LAUNCHPAD/board.h b/os/hal/boards/TI_CC1310_LAUNCHPAD/board.h new file mode 100644 index 0000000000..6abccd9ebb --- /dev/null +++ b/os/hal/boards/TI_CC1310_LAUNCHPAD/board.h @@ -0,0 +1,131 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for Texas Instruments CC1310 Launchpad Board. + */ + +/* + * Board identifier. + */ +#define BOARD_TI_CC1310_LAUNCHPAD +#define BOARD_NAME "Texas Instruments CC1310 Launchpad" + +/* + * MCU type and revision as defined in the TI header. + */ +#define CC1310F128RGZ + +/* + * Board oscillators-related settings. + */ +/* + * Board oscillators-related settings. + */ +#define TI_XOSC_LF 32768 +#define TI_RCOSC_LF 32000 + +#define TI_XOSC_HF 24000000 +#define TI_RCOSC_HF 24000000 + +/* + * IO pins assignments. + */ +#define DIO1 +#define DIO2_RXD +#define DIO3_TXD +#define DIO4_SCL +#define DIO5_SDA +#define DIO6_RLED +#define DIO7_GLED +#define DIO8_MISO +#define DII9_MOSI +#define DIO10_SCLK +#define DIO11_CS +#define DIO12 +#define DIO13_BTN1 +#define DIO14_BTN2 +#define DIO15 +#define DIO16_TDO +#define DIO17_TDI +#define DIO18_RTS_SWO +#define DIO19_CTS +#define DIO20_FLASH_CS +#define DIO21 +#define DIO22 +#define DIO23_ANALOG +#define DIO24_ANALOG +#define DIO25_ANALOG +#define DIO26_ANALOG +#define DIO27_ANALOG +#define DIO28_ANALOG +#define DIO29_ANALOG +#define DIO30_ANALOG + +/* + * IO lines assignments. + */ +#define LINE_DIO1 PAL_LINE(GPIOA, 0U) +#define LINE_DIO2_RXD PAL_LINE(GPIOA, 1U) +#define LINE_DIO3_TXD PAL_LINE(GPIOA, 2U) + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + */ +#define PIN_DATA_LOW(n) (0U << (n)) +#define PIN_DATA_HIGH(n) (1U << (n)) + +#define PIN_DIR_IN(n) (0U << (n)) +#define PIN_DIR_OUT(n) (1U << (n)) + +#define PIN_AFSEL_GPIO(n) (0U << (n)) +#define PIN_AFSEL_ALTERNATE(n) (1U << (n)) + +#define PIN_ODR_DISABLE(n) (0U << (n)) +#define PIN_ODR_ENABLE(n) (1U << (n)) + +#define PIN_PxR_DISABLE(n) (0U << (n)) +#define PIN_PxR_ENABLE(n) (1U << (n)) + +#define PIN_DEN_DISABLE(n) (0U << (n)) +#define PIN_DEN_ENABLE(n) (1U << (n)) + +#define PIN_AMSEL_DISABLE(n) (0U << (n)) +#define PIN_AMSEL_ENABLE(n) (1U << (n)) + +#define PIN_DRxR_DISABLE(n) (0U << (n)) +#define PIN_DRxR_ENABLE(n) (1U << (n)) + +#define PIN_SLR_DISABLE(n) (0U << (n)) +#define PIN_SLR_ENABLE(n) (1U << (n)) + +#define PIN_PCTL_MODE(n, mode) (mode << ((n) * 4)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/os/hal/boards/TI_CC1310_LAUNCHPAD/board.mk b/os/hal/boards/TI_CC1310_LAUNCHPAD/board.mk new file mode 100644 index 0000000000..ebcda85342 --- /dev/null +++ b/os/hal/boards/TI_CC1310_LAUNCHPAD/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_CC1310_LAUNCHPAD/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_CC1310_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 63c1faec36..8f64d7e7f1 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -1,119 +1,122 @@ -include ${CHIBIOS}/os/hal/hal.mk - -ifeq ($(USE_SMART_BUILD),yes) - -# Configuration files directory -ifeq ($(CONFDIR),) - CONFDIR = . -endif - -HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) - -HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c -ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c -endif -ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c -endif -ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c -endif -ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c -endif -ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c -endif -ifneq ($(findstring HAL_USE_EICU TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c -endif -ifneq ($(findstring HAL_USE_CRC TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c -endif -ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c -endif -ifneq ($(findstring HAL_USE_USBH TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c -endif -ifneq ($(findstring HAL_USBH_USE_MSD TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c -endif -ifneq ($(findstring HAL_USBH_USE_FTDI TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_ftdi.c -endif -ifneq ($(findstring HAL_USBH_USE_AOA TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_aoa.c -endif -ifneq ($(findstring HAL_USBH_USE_HID TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_hid.c -endif -ifneq ($(findstring HAL_USBH_USE_UVC TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c -endif -ifneq ($(findstring HAL_USE_EEPROM TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c -ifneq ($(findstring EEPROM_USE_EE25XX TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c -endif -ifneq ($(findstring EEPROM_USE_EE24XX TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c -endif -endif -ifneq ($(findstring HAL_USE_TIMCAP TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c -endif -ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c -endif -ifneq ($(findstring HAL_USE_USB_HID TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c -endif -ifneq ($(findstring HAL_USE_USB_MSD TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c -endif -ifneq ($(findstring HAL_USE_COMP TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c -endif -ifneq ($(findstring HAL_USE_OPAMP TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c -endif -else -HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_aoa.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hid.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c -endif - -HALINC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/include - -# Shared variables -ALLCSRC += $(HALSRC_CONTRIB) -ALLINC += $(HALINC_CONTRIB) +include ${CHIBIOS}/os/hal/hal.mk + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c +ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c +endif +ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c +endif +ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c +endif +ifneq ($(findstring HAL_USE_BURAM,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_buram.c +endif +ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c +endif +ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c +endif +ifneq ($(findstring HAL_USE_EICU TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c +endif +ifneq ($(findstring HAL_USE_CRC TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c +endif +ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c +endif +ifneq ($(findstring HAL_USE_USBH TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c +endif +ifneq ($(findstring HAL_USBH_USE_MSD TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c +endif +ifneq ($(findstring HAL_USBH_USE_FTDI TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_ftdi.c +endif +ifneq ($(findstring HAL_USBH_USE_AOA TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_aoa.c +endif +ifneq ($(findstring HAL_USBH_USE_HID TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh_hid.c +endif +ifneq ($(findstring HAL_USBH_USE_UVC TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c +endif +ifneq ($(findstring HAL_USE_EEPROM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c +ifneq ($(findstring EEPROM_USE_EE25XX TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c +endif +ifneq ($(findstring EEPROM_USE_EE24XX TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c +endif +endif +ifneq ($(findstring HAL_USE_TIMCAP TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c +endif +ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c +endif +ifneq ($(findstring HAL_USE_USB_HID TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c +endif +ifneq ($(findstring HAL_USE_USB_MSD TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c +endif +ifneq ($(findstring HAL_USE_COMP TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c +endif +ifneq ($(findstring HAL_USE_OPAMP TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c +endif +else +HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_aoa.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hid.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_comp.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c +endif + +HALINC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/include + +# Shared variables +ALLCSRC += $(HALSRC_CONTRIB) +ALLINC += $(HALINC_CONTRIB) diff --git a/os/hal/include/hal_buram.h b/os/hal/include/hal_buram.h new file mode 100644 index 0000000000..d506bba108 --- /dev/null +++ b/os/hal/include/hal_buram.h @@ -0,0 +1,124 @@ +/* + ChibiOS/HAL - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_buram.h + * @brief BURAM Driver subsystem low level driver header. + * + * @addtogroup BURAM + * @{ + */ + +#ifndef HAL_BURAM_H_ +#define HAL_BURAM_H_ + +#if (HAL_USE_BURAM == TRUE) || defined(__DOXYGEN__) + +#include "bitmap.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#include "hal_buram_lld.h" + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + BURAM_UNINIT = 0, /**< Not initialized. */ + BURAM_STOP = 1, /**< Stopped. */ + BURAM_READY = 2, /**< Ready. */ +} buramstate_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +struct BURAMConfig { + + #if defined(buram_lld_config_ext_fields) + buram_lld_config_ext_fields + #endif +}; + +/** + * @brief Structure representing an BURAM driver. + */ +struct BURAMDriver { + /** + * @brief Driver state. + */ + buramstate_t state; + + /** + * @brief Backup RAM start address. + */ + uintptr_t start; + + /** + * @brief Backup RAM end address. + */ + uintptr_t end; + + /** + * @brief Map of allocated backup RAM. + */ + bitmap_t buram_map; + + #if defined(buram_lld_driver_fields) + buram_lld_driver_fields + #endif +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void buramInit(void); + void buramObjectInit(BURAMDriver *sdramp); + void buramStart(BURAMDriver *buramp, const BURAMConfig *cfgp); + void buramStop(BURAMDriver *buramp); + volatile void* buramAllocateAtI(BURAMDriver* buramp, uintptr_t address, size_t size); + volatile void* buramAllocateAt(BURAMDriver *buramp, uintptr_t address, size_t size); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_BURAM */ + +#endif /* HAL_BURAM_H_ */ + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG14P/efr32_registry.h b/os/hal/ports/SILABS/EFR32FG14P/efr32_registry.h new file mode 100644 index 0000000000..b9bfe03b8d --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG14P/efr32_registry.h @@ -0,0 +1,75 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EFR32FG14P/efr32_registry.h + * @brief EFR32FG14P capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef EFR32_REGISTRY_H +#define EFR32_REGISTRY_H + +/*===========================================================================*/ +/* Defined device check. */ +/*===========================================================================*/ + +#if !defined(EFR32FG14P231F128GM48) && !defined(EFR32FG14P231F256GM32) && \ + !defined(EFR32FG14P231F256GM48) && !defined(EFR32FG14P231F256IM32) && \ + !defined(EFR32FG14P231F256IM48) && !defined(EFR32FG14P232F128GM32) && \ + !defined(EFR32FG14P232F128GM48) && !defined(EFR32FG14P232F256GM32) && \ + !defined(EFR32FG14P232F256GM48) && !defined(EFR32FG14P233F128GM48) && \ + !defined(EFR32FG14P233F256GM48) +#error "No valid device defined." +#endif + +/** + * @brief Sub-family identifier. + */ +#if !defined(EFR32FG14P23X) || defined(__DOXYGEN__) +#define EFR32FG14P23X +#endif + + +/* LETIM attributes.*/ +#define EFR32_LETIM_MAX_CHANNELS 2 + +#define EFR32_HAS_LETIM1 TRUE +#define EFR32_LETIM1_IS_32BITS FALSE +#define EFR32_LETIM1_CHANNELS 2 + +#define EFR32_HAS_LETIM2 FALSE +#define EFR32_LETIM2_IS_32BITS FALSE +#define EFR32_LETIM2_CHANNELS 2 + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + + + +/** @} */ + +#endif /* EFR32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG14P/hal_lld.c b/os/hal/ports/SILABS/EFR32FG14P/hal_lld.c new file mode 100644 index 0000000000..23b0b1b762 --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG14P/hal_lld.c @@ -0,0 +1,152 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EFR32FG14P chip and errata initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ + +void efr32_chip_init(void) { + + CHIP_Init(); +} + +/** + * @brief EFR32FG14P clocks initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void efr32_clock_init(void) { + SystemCoreClockUpdate(); + +#if EFR32_LFXO_ENABLED + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); +#else + CMU_OscillatorEnable(cmuOsc_LFXO, false, false); +#endif + +#if EFR32_HFXO_ENABLED + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); +#else + CMU_OscillatorEnable(cmuOsc_HFXO, false, false); +#endif + +#if EFR32_LFRCO_ENABLED + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); +#else + CMU_OscillatorEnable(cmuOsc_LFRCO, false, false); +#endif + +#if EFR32_HFRCO_ENABLED + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); +#else + CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); +#endif + +#if defined(EFR32_RTCCSEL) +#if EFR32_RTCCSEL == EFR32_RTCCSEL_NOCLOCK + CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_Disabled); + +#elif EFR32_RTCCSEL == EFR32_RTCCSEL_LFXO + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); + +#elif EFR32_RTCCSEL == EFR32_RTCCSEL_LFRCO + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); + +#elif EFR32_RTCCSEL == EFR32_RTCCSEL_ULFRCO + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_ULFRCO); + +#else +#error "EFR32_RTCCSEL not specified" +#endif +#endif + +#if defined(EFR32_LETIM1SEL) +#if EFR32_LETIM1SEL == EFR32_LETIM1SEL_NOCLOCK + CMU_ClockSelectSet(cmuClock_LETIMER0, cmuSelect_Disabled); + +#elif EFR32_LETIM1SEL == EFR32_LETIM1SEL_LFXO + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + +#elif EFR32_LETIM1SEL == EFR32_LETIM1SEL_LFRCO + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO); + +#elif EFR32_LETIM1SEL == EFR32_LETIM1SEL_ULFRCO + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_ULFRCO); + +#else +#error "EFR32_LETIM1SEL not specified" +#endif +#endif +} + + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + /* NVIC initialization.*/ + nvicInit(); +} + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG14P/hal_lld.h b/os/hal/ports/SILABS/EFR32FG14P/hal_lld.h new file mode 100644 index 0000000000..66274c2917 --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG14P/hal_lld.h @@ -0,0 +1,108 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#include "efr32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "EFR32FG14P" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if defined(EFR32FG14P23X) && !defined(EFR32FG14P23X_MCUCONF) +#error "Using a wrong mcuconf.h file, EFR32FG14P23X_MCUCONF not defined" +#endif + +#define EFR32_HCLK EFR32_HFRCO_STARTUP_FREQ +#define EFR32_LFXOCLK EFR32_LFXO_FREQ +#define EFR32_LFRCOCLK EFR32_LFRCO_FREQ +#define EFR32_ULFRCOCLK EFR32_ULFRCO_FREQ + + +#define EFR32_RTCCSEL_NOCLOCK (0u << 0) +#define EFR32_RTCCSEL_LFXO (1u << 0) +#define EFR32_RTCCSEL_LFRCO (1u << 1) +#define EFR32_RTCCSEL_ULFRCO (1u << 2) + +#define EFR32_RTCC_IRQ_HANDLER VectorBC +#define EFR32_RTCC_IRQ_NUMBER RTCC_IRQn +#define EFR32_RTCCCLK EFR32_LFXOCLK + + +#define EFR32_LETIM1SEL_NOCLOCK (0u << 0) +#define EFR32_LETIM1SEL_LFXO (1u << 0) +#define EFR32_LETIM1SEL_LFRCO (1u << 1) +#define EFR32_LETIM1SEL_ULFRCO (1u << 2) + +#define EFR32_LETIM1_HANDLER VectorAC +#define EFR32_LETIM1_NUMBER LETIMER0_IRQn +#define EFR32_LETIM1CLK EFR32_LFXOCLK + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" + +#ifdef __cplusplus +extern "C" { +#endif + void efr32_chip_init(void); + void efr32_clock_init(void); + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG14P/platform.mk b/os/hal/ports/SILABS/EFR32FG14P/platform.mk new file mode 100644 index 0000000000..75f49ab526 --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG14P/platform.mk @@ -0,0 +1,36 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := \ + $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG14P/hal_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := \ + $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG14P \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG14P \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/common + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +#include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/common/SYSTICKv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/SILABS/EFR32FG23/efr32_registry.h b/os/hal/ports/SILABS/EFR32FG23/efr32_registry.h new file mode 100644 index 0000000000..9e2664a85b --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG23/efr32_registry.h @@ -0,0 +1,112 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EFR32FG23/efr32_registry.h + * @brief EFR32FG23 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef EFR32_REGISTRY_H +#define EFR32_REGISTRY_H + +/*===========================================================================*/ +/* Defined device check. */ +/*===========================================================================*/ + +#if !defined(EFR32FG23A010F128GM40) && !defined(EFR32FG23A010F256GM40) && \ + !defined(EFR32FG23A010F256GM48) && !defined(EFR32FG23A010F512GM40) && \ + !defined(EFR32FG23A010F512GM48) && !defined(EFR32FG23A011F512GM40) && \ + !defined(EFR32FG23A020F128GM40) && !defined(EFR32FG23A020F256GM40) && \ + !defined(EFR32FG23A020F256GM48) && !defined(EFR32FG23A020F512GM40) && \ + !defined(EFR32FG23A020F512GM48) && !defined(EFR32FG23A021F512GM40) && \ + !defined(EFR32FG23B010F128GM40) && !defined(EFR32FG23B010F512GM48) && \ + !defined(EFR32FG23B010F512IM40) && !defined(EFR32FG23B010F512IM48) && \ + !defined(EFR32FG23B020F128GM40) && !defined(EFR32FG23B020F512IM40) && \ + !defined(EFR32FG23B020F512IM48) && !defined(EFR32FG23B021F512IM40) && \ + !defined(EFR32FG23B021F512IM48) +#error "No valid device defined." +#endif + +/** + * @brief Sub-family identifier. + */ +#if !defined(EFR32FG23X) || defined(__DOXYGEN__) +#define EFR32FG23X +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#define EFR32_HAS_LETIM1 TRUE + +#define EFR32_HAS_GPIOA TRUE +#define EFR32_HAS_GPIOB TRUE +#define EFR32_HAS_GPIOC TRUE +#define EFR32_HAS_GPIOD TRUE + +#define EFR32_HAS_EUSART1 TRUE +#define EFR32_HAS_EUSART2 TRUE +#define EFR32_HAS_EUSART3 TRUE + +#define EFR32_HAS_USART1 TRUE + +/* + * RTC driver system settings. + */ +#define EFR32_HAS_RTC TRUE +#define EFR32_RTC_HAS_SUBSECONDS TRUE +#define EFR32_RTC_NUM_ALARMS 1 + +/* + * LETIM driver system settings. + */ +#define EFR32_LETIM1_IS_32BITS TRUE +#define EFR32_LETIM_MAX_CHANNELS 2 +#define EFR32_LETIM1_CHANNELS 2 + +/* + * EUSART driver system settings. + */ +#define EFR32_EUSART1_LOW_POWER_ENABLED TRUE +#define EFR32_EUSART2_LOW_POWER_ENABLED FALSE +#define EFR32_EUSART3_LOW_POWER_ENABLED FALSE + +/* + * DAC driver system settings. + */ +#define EFR32_HAS_DAC1_CH1 TRUE +#define EFR32_HAS_DAC1_CH2 TRUE + +/* + * DMA driver system settings. + */ +#define EFR32_HAS_DMA TRUE +#define EFR32_ADVANCED_DMA TRUE +#define EFR32_DMA_SUPPORTS_DMAMUX TRUE + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + +/** @} */ + +#endif /* EFR32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG23/hal_lld.c b/os/hal/ports/SILABS/EFR32FG23/hal_lld.c new file mode 100644 index 0000000000..565ac665c1 --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG23/hal_lld.c @@ -0,0 +1,414 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void efr32_calibrate_lfxo(void) { + + uint32_t gain_cal_value, captune_cal_value; + uint32_t gain, captune; + + efr32_get_lfxo_calibration_values(&gain_cal_value, &captune_cal_value); + + gain = (LFXO->CAL & _LFXO_CAL_GAIN_MASK) >> _LFXO_CAL_GAIN_SHIFT; + if (gain != gain_cal_value) { + while ((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) == LFXO_SYNCBUSY_CAL); + LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_GAIN_MASK) | + ((gain_cal_value << _LFXO_CAL_GAIN_SHIFT) & _LFXO_CAL_GAIN_MASK); + while ((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) != 0U); + } + + while (true) { + captune = (LFXO->CAL & _LFXO_CAL_CAPTUNE_MASK) >> _LFXO_CAL_CAPTUNE_SHIFT; + + if (captune > captune_cal_value) { + --captune; + } + else if (captune < captune_cal_value) { + ++captune; + } + else { + break; + } + + while ((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) == LFXO_SYNCBUSY_CAL); + LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_CAPTUNE_MASK) | + ((captune << _LFXO_CAL_CAPTUNE_SHIFT) & _LFXO_CAL_CAPTUNE_MASK); + while ((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) == LFXO_SYNCBUSY_CAL); + } +} + +__STATIC_INLINE void efr32_set_voltage_scaling(void) { + + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) | EFR32_EM23_VSCALE; + + EMU->CMD = (EMU->CMD & ~(_EMU_CMD_EM01VSCALE1_MASK | _EMU_CMD_EM01VSCALE2_MASK)) | EFR32_EM01_VSCALE; + while ((EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK) == EMU_STATUS_VSCALEBUSY); +} + +__STATIC_INLINE void efr32_enable_clock_sources(void) { + +#if EFR32_LFXO_ENABLED + /* Enable clock. */ + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; + + /* Disable LFXO. */ + LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; + LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; + while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) == LFXO_STATUS_ENS); + + uint32_t gain_cal_value, captune_cal_value; + efr32_get_lfxo_calibration_values(&gain_cal_value, &captune_cal_value); + + /* Configure LFXO as specified. */ + LFXO->CAL = (LFXO->CAL & ~(_LFXO_CAL_GAIN_MASK | _LFXO_CAL_CAPTUNE_MASK)) | + ((gain_cal_value << _LFXO_CAL_GAIN_SHIFT) & _LFXO_CAL_GAIN_MASK) | + ((captune_cal_value << _LFXO_CAL_CAPTUNE_SHIFT) & _LFXO_CAL_CAPTUNE_MASK); + + LFXO->CTRL_SET = LFXO_CTRL_FORCEEN; + + while ((LFXO->STATUS & (_LFXO_STATUS_RDY_MASK | _LFXO_STATUS_ENS_MASK)) != + (LFXO_STATUS_RDY | LFXO_STATUS_ENS)); +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_LFXO; +#endif + +#if EFR32_HFXO_ENABLED + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; + HFXO0->CTRL |= HFXO_CTRL_FORCEEN; +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; +#endif + +#if EFR32_LFRCO_ENABLED + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_LFRCO; +#endif + +#if EFR32_ULFRCO_ENABLED + CMU->CLKEN0_SET = CMU_CLKEN0_ULFRCO; +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_ULFRCO; +#endif + +#if EFR32_HFRCO_ENABLED + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + while ((HFRCO0->STATUS & _HFRCO_STATUS_RDY_MASK) != HFRCO_STATUS_RDY); +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; +#endif + +#if EFR32_HFRCOEM23_ENABLED + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; + HFRCOEM23->CTRL_SET = HFRCO_CTRL_FORCEEN; + while ((HFRCOEM23->STATUS & _HFRCO_STATUS_RDY_MASK) != HFRCO_STATUS_RDY); +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCOEM23; +#endif + +#if EFR32_FSRCO_ENABLED + CMU->CLKEN0_SET = CMU_CLKEN0_FSRCO; +#else + CMU->CLKEN0_CLR = CMU_CLKEN0_FSRCO; +#endif + +#if defined(EFR32_CMU_SYSCLKCTRL) + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_MASK) | EFR32_CMU_SYSCLKCTRL; +#endif +} + +__STATIC_INLINE void efr32_enable_em01grpaclk(void) { + +#if EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK +#if EFR32_FSRCO_ENABLED && (EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_FSRCO) + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | + CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; +#elif EFR32_HFRCODPLL_ENABLED && (EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFRCODPLL) + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | + CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; +#elif EFR32_HFXO_ENABLED && (EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFXO) + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | + CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; +#else +#error "No clock source selected for EFR32_EM01GRPACLK" +#endif +#else +#warning "EFR32_EM01GRPACLK can't be disabled" +#endif +} + +__STATIC_INLINE void efr32_enable_em01grpcclk(void) { + +#if EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK +#if EFR32_FSRCO_ENABLED && (EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_FSRCO) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | + CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; +#elif EFR32_HFRCODPLL_ENABLED && (EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFRCODPLL) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | + CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; +#elif EFR32_HFXO_ENABLED && (EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFXO) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | + CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; +#else +#error "No clock source selected for EFR32_EM01GRPCCLK" +#endif +#else +#warning "EFR32_EM01GRPCCLK can't be disabled" +#endif +} + +__STATIC_INLINE void efr32_enable_em23grpaclk(void) { + +#if EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK +#if EFR32_LFXO_ENABLED && (EFR32_EM23GRPACLKSEL == EFR32_EM23GRPACLKSEL_LFXO) + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | + CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; + +#elif EFR32_LFRCO_ENABLED && (EFR32_EM23GRPACLKSEL == EFR32_EM23GRPACLKSEL_LFRCO) + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | + CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; + +#elif EFR32_ULFRCO_ENABLED && (EFR32_EM23GRPACLKSEL == EFR32_EM23GRPACLKSEL_ULFRCO) + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | + CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; +#else +#error "No clock source selected for EFR32_EM23GRPACLK" +#endif +#else +#warning "EFR32_EM23GRPACLK can't be disabled" +#endif +} + +__STATIC_INLINE void efr32_enable_buram(void) { + + CMU->CLKEN0_SET = CMU_CLKEN0_BURAM; +} + +__STATIC_INLINE void efr32_enable_eusartclk(void) { + +#if EFR32_EUSART1SEL != EFR32_EUSART1SEL_NOCLOCK +#if EFR32_LFRCO_ENABLED && EFR32_EUSART1SEL == EFR32_EUSART1SEL_LFRCO + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK)\ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; +#elif EFR32_LFXO_ENABLED && EFR32_EUSART1SEL == EFR32_EUSART1SEL_LFXO + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK)\ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; +#elif EFR32_HFRCOEM23_ENABLED && EFR32_EUSART1SEL == EFR32_EUSART1SEL_HFRCOEM23 + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK)\ + | CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; +#elif EFR32_HFRCODPLL_ENABLED && EFR32_EUSART1SEL == EFR32_EUSART1SEL_EM01GRPCCLK + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK)\ + | CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; +#else +#error "No clock source selected for EFR32_EUSART1SEL" +#endif +#else + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK)\ + | CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; +#endif + +#if EFR32_EUSART23SEL != EFR32_EUSART23SEL_NOCLOCK +#if EFR32_HFRCOEM23_ENABLED && EFR32_EUSART23SEL == EFR32_EUSART23SEL_HFRCOEM23 + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK)\ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; +#elif EFR32_HFRCODPLL_ENABLED && EFR32_EUSART23SEL == EFR32_EUSART23SEL_HFRCODPLL + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK)\ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; +#elif EFR32_FSRCO_ENABLED && EFR32_EUSART23SEL == EFR32_EUSART23SEL_FSRCO + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK)\ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; +#elif EFR32_HFXO_ENABLED && EFR32_EUSART23SEL == EFR32_EUSART23SEL_HFXO + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK)\ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; +#else +#error "No clock source selected for EFR32_EUSART23SEL" +#endif +#else + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK)\ + | CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT; +#endif +} + +__STATIC_INLINE void efr32_enable_vdacclk(void) { + +#if EFR32_DAC1SEL != EFR32_DAC1SEL_NOCLOCK +#if EFR32_EM01GRPACLK_ENABLED && EFR32_DAC1SEL == EFR32_DAC1SEL_EM01GRPACLK + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK)\ + | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; +#elif EFR32_EM23GRPACLK_ENABLED && EFR32_DAC1SEL == EFR32_DAC1SEL_EM23GRPACLK + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK)\ + | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; +#elif EFR32_FSRCO_ENABLED && EFR32_DAC1SEL == EFR32_DAC1SEL_FSRCO + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK)\ + | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; +#elif EFR32_HFRCOEM23_ENABLED && EFR32_DAC1SEL == EFR32_DAC1SEL_HFRCOEM23 + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK)\ + | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; +#else +#error "No clock source selected for EFR32_DAC1SEL" +#endif +#else + CMU->CLKEN1 = (CMU->CLKEN1 & ~_CMU_CLKEN1_VDAC0_MASK)\ + | CMU_CLKEN1_VDAC0_DEFAULT; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EFR32FG23 chip and errata initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ + +void efr32_chip_init(void) { + +} + +CC_WEAK void efr32_get_lfxo_calibration_values(uint32_t *gain, uint32_t *captune) { + + osalDbgAssert(gain != NULL, "gain must be not NULL"); + osalDbgAssert(captune != NULL, "captune must be not NULL"); + + *gain = LFXO_RTC_GAIN_DEFAULT_VALUE; + *captune = LFXO_RTC_CAPTUNE_DEFAULT_VALUE; +} + +/** + * @brief EFR32FG23 clocks initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void efr32_clock_init(void) { + + efr32_enable_clock_sources(); + efr32_enable_em01grpaclk(); + efr32_enable_em01grpcclk(); + efr32_enable_em23grpaclk(); + efr32_enable_buram(); + efr32_enable_eusartclk(); + efr32_enable_vdacclk(); + + /* After all clocks were set, set also the voltage scaling. */ + efr32_set_voltage_scaling(); +} + +/** + * @brief efr32_escape_hatch() + * When developing or debugging code that enters EM2 or + * lower, it's a good idea to have an "escape hatch" type + * mechanism, e.g. a way to pause the device so that a debugger can + * connect in order to erase flash, among other things. + * + * Before proceeding with this example, make sure ESCAPE_HATCH_PAD is not + * grounded. If the ESCAPE_HATCH_PIN pin is low, execute the breakpoint instruction + * to stop the processor in EM0 and allow a debug connection to be made. + */ +void efr32_escape_hatch(void) { + +#if defined(ESCAPE_HATCH_ENABLE) && (ESCAPE_HATCH_ENABLE == TRUE) + const uint32_t port = ESCAPE_HATCH_PORT; + const uint32_t pin = ESCAPE_HATCH_PIN; + const bool gpio_clk_was_enabled = (CMU->CLKEN0 & CMU_CLKEN0_GPIO) != 0U; + unsigned int pin_state; + + CMU->CLKEN0_SET = CMU_CLKEN0_GPIO; + + GPIO->P_SET[port].DOUT = 1UL << pin; + if (pin < 8) { + GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4))) | + (GPIO_P_MODEL_MODE0_INPUTPULLFILTER << (pin * 4)); + } + else { + GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << (pin * 4))) | + (GPIO_P_MODEL_MODE0_INPUTPULLFILTER << (pin * 4)); + } + + pin_state = (GPIO->P[port].DIN >> pin) & 1; + + if (pin_state == 0) { /* Pi asserted, so break into debugger. */ + __BKPT(0); + } + else { /* Pin not asserted, so disable input. */ + if (pin < 8) { + GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4))) | + (GPIO_P_MODEL_MODE0_DISABLED << (pin * 4)); + } + else { + GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << (pin * 4))) | + (GPIO_P_MODEL_MODE0_DISABLED << (pin * 4)); + } + + if (!gpio_clk_was_enabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_GPIO; + } + } +#endif +} + + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* DMA subsystems initialization.*/ +#if defined(EFR32_DMA_REQUIRED) + dmaInit(); +#endif + + /* NVIC initialization.*/ + nvicInit(); +} + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG23/hal_lld.h b/os/hal/ports/SILABS/EFR32FG23/hal_lld.h new file mode 100644 index 0000000000..463240d19d --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG23/hal_lld.h @@ -0,0 +1,509 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#include "efr32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "EFR32FG23" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if defined(EFR32FG23X) && !defined(EFR32FG23X_MCUCONF) +#error "Using a wrong mcuconf.h file, EFR32FG23X_MCUCONF not defined" +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +#define HFRCODPLL_MAX_FREQ 80000000UL +#endif + +#define VSCALE_1V0_MAX_FREQ 40000000UL +#define VSCALE_1V1_MAX_FREQ HFRCODPLL_MAX_FREQ + +#define EFR32_LFXOCLK EFR32_LFXO_FREQ +#define EFR32_HFXOCLK EFR32_HFXO_FREQ +#define EFR32_CLKIN0CLK EFR32_CLKIN0_FREQ +#define EFR32_FSRCOCLK 20000000UL +#define EFR32_LFRCOCLK 32768UL +#define EFR32_ULFRCOCLK 1000UL +#define EFR32_HFRCODPLL_FREQ 19000000UL + +#define EFR32_EM01_VSCALESEL_1V0 (1U << 0) +#define EFR32_EM01_VSCALESEL_1V1 (1U << 1) + +#define EFR32_EM23_VSCALESEL_0V9 (0U << 0) +#define EFR32_EM23_VSCALESEL_1V0 (1U << 0) +#define EFR32_EM23_VSCALESEL_1V1 (1U << 1) + +#define EFR32_EM01_VSCALE_1V0 (1U << 10) /**< EM0/EM1 operation up to 40 MHz */ +#define EFR32_EM01_VSCALE_1V1 (1U << 11) /**< EM0/EM1 operation up to 80 MHz */ + +#define EFR32_EM23_VSCALE_0V9 (0U << 8) /**< EM2/EM3 operation up to 40 MHz, slow startup */ +#define EFR32_EM23_VSCALE_1V0 (1U << 8) /**< EM2/EM3 operation up to 40 MHz */ +#define EFR32_EM23_VSCALE_1V1 (2U << 8) /**< EM2/EM3 operation up to 80 MHz */ + +/** + * @name CMU_SYSCLKCTRL register bits definitions + * @{ + */ +#define EFR32_SYSCLKSEL_FSRCO (1U << 0) /**< SYSCLK source is FSRCO. */ +#define EFR32_SYSCLKSEL_HFRCODPLL (2U << 0) /**< SYSCLK source is HFRCODPLL */ +#define EFR32_SYSCLKSEL_HFXO (3U << 0) /**< SYSCLK source is HFCO. */ +#define EFR32_SYSCLKSEL_CLKIN0 (4U << 0) /**< SYSCLK source is CLKIN0. */ + +#define EFR32_PPRE_DIV1 (0U << 10) /**< PCLK is HCLK divided by 1 */ +#define EFR32_PPRE_DIV2 (1U << 10) /**< PCLK is HCLK divided by 2 */ + +#define EFR32_HPRE_DIV1 (0U << 12) /**< HCLK is SYSCLK divided by 1 */ +#define EFR32_HPRE_DIV2 (1U << 12) /**< HCLK is SYSCLK divided by 2 */ +#define EFR32_HPRE_DIV4 (3U << 12) /**< HCLK is SYSCLK divided by 4 */ +#define EFR32_HPRE_DIV8 (7U << 12) /**< HCLK is SYSCLK divided by 8 */ +#define EFR32_HPRE_DIV16 (15U << 12) /**< HCLK is SYSCLK divided by 16 */ + +#define EFR32_RHPRE_DIV1 (0U << 16) /**< Radio HCLK is HCLK divided by 1 */ +#define EFR32_RHPRE_DIV2 (1U << 16) /**< Radio HCLK is HCLK divided by 2 */ + +#define EFR32_HFRCOPRE_DIV1 (0U << 24) /**< HFRCO clock is divided by 1 */ +#define EFR32_HFRCOPRE_DIV2 (1U << 24) /**< HFRCO clock is divided by 2 */ +#define EFR32_HFRCOPRE_DIV4 (2U << 24) /**< HFRCO clock is divided by 4 */ + +/** + * @brief System clock source. + */ +#if (EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_FSRCO) || defined(__DOXYGEN__) +#define EFR32_SYSCLK EFR32_FSRCOCLK +#elif (EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_HFRCODPLL) +#define EFR32_SYSCLK EFR32_HFRCODPLLCLK +#elif (EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_HFXO) +#define EFR32_SYSCLK EFR32_HFXOCLK +#elif (EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_CLKIN0) +#define EFR32_SYSCLK EFR32_CLKIN0CLK +#else +#error "invalid EFR32_SYSCLKSEL value specified" +#endif + +/** + * @brief HCLK frequency. + */ +#if (EFR32_HPRE == EFR32_HPRE_DIV1) || defined(__DOXYGEN__) +#define EFR32_HCLK (EFR32_SYSCLK / 1) +#elif EFR32_HPRE == EFR32_HPRE_DIV2 +#define EFR32_HCLK (EFR32_SYSCLK / 2) +#elif EFR32_HPRE == EFR32_HPRE_DIV4 +#define EFR32_HCLK (EFR32_SYSCLK / 4) +#elif EFR32_HPRE == EFR32_HPRE_DIV8 +#define EFR32_HCLK (EFR32_SYSCLK / 8) +#elif EFR32_HPRE == EFR32_HPRE_DIV16 +#define EFR32_HCLK (EFR32_SYSCLK / 16) +#else +#error "invalid EFR32_HPRE value specified" +#endif + +/** + * @brief PCLK frequency. + */ +#if (EFR32_PPRE == EFR32_PPRE_DIV1) || defined(__DOXYGEN__) +#define EFR32_PCLK (EFR32_HCLK / 1) +#elif EFR32_PPRE == EFR32_PPRE_DIV2 +#define EFR32_PCLK (EFR32_HCLK / 2) +#else +#error "invalid EFR32_PPRE value specified" +#endif + +/** + * @brief RHCLK frequency. + */ +#if (EFR32_RHPRE == EFR32_RHPRE_DIV1) || defined(__DOXYGEN__) +#define EFR32_RHCLK (EFR32_SYSCLK / 1) +#elif EFR32_RHPRE == EFR32_RHPRE_DIV2 +#define EFR32_RHCLK (EFR32_SYSCLK / 2) +#else +#error "invalid EFR32_RHPRE value specified" +#endif + +/** + * @brief HFRCODPLL and HFRCOEM23 frequencies. + */ +#if (EFR32_HFRCOPRE == EFR32_HFRCOPRE_DIV1) || defined(__DOXYGEN__) +#define EFR32_HFRCODPLLCLK (EFR32_HFRCODPLL_FREQ / 1) +#define EFR32_HFRCOEM23CLK (EFR32_HFRCODPLL_FREQ / 1) +#elif EFR32_HFRCOPRE == EFR32_HFRCOEM23PRE_DIV2 +#define EFR32_HFRCODPLLCLK (EFR32_HFRCODPLL_FREQ / 1) +#define EFR32_HFRCOEM23CLK (EFR32_HFRCODPLL_FREQ / 2) +#elif EFR32_HFRCOPRE == EFR32_HFRCOEM23PRE_DIV4 +#define EFR32_HFRCODPLLCLK (EFR32_HFRCODPLL_FREQ / 1) +#define EFR32_HFRCOEM23CLK (EFR32_HFRCODPLLCLK / 4) +#else +#error "invalid EFR32_HFRCOEM23PRE value specified" +#endif + +#if EFR32_HFXO_ENABLED +#else +#if EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_HFXO +#error "HFXO is not enabled, required by EFR32_SYSCLKSEL" +#endif +#endif + +#if EFR32_FSRCO_ENABLED +#else +#if EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_FSRCO +#error "FSRCO is not enabled, required by EFR32_SYSCLKSEL" +#endif +#endif + +#if EFR32_CLKIN0CLK == 0U +#else +#if EFR32_SYSCLKSEL == EFR32_SYSCLKSEL_CLKIN0 +#error "CLKIN0 is not enabled, required by EFR32_SYSCLKSEL" +#endif +#endif + +#if EFR32_EM01VSCALE_SEL >= EFR32_EM23VSCALE_SEL +#if EFR32_EM01VSCALE_SEL == EFR32_EM01_VSCALESEL_1V0 +#define EFR32_EM01_VSCALE EFR32_EM01_VSCALE_1V0 +#elif EFR32_EM01VSCALE_SEL == EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM01_VSCALE EFR32_EM01_VSCALE_1V1 +#else +#error "EFR32_EM01VSCALE_SEL is not set" +#endif +#else +#error "EFR32_EM01VSCALE_SEL must be equal or greater than EFR32_EM23VSCALE_SEL" +#endif + +#if EFR32_EM23VSCALE_SEL == EFR32_EM23_VSCALESEL_0V9 +#define EFR32_EM23_VSCALE EFR32_EM23_VSCALE_0V9 +#elif EFR32_EM23VSCALE_SEL == EFR32_EM23_VSCALESEL_1V0 +#define EFR32_EM23_VSCALE EFR32_EM23_VSCALE_1V0 +#elif EFR32_EM23VSCALE_SEL == EFR32_EM23_VSCALESEL_1V1 +#define EFR32_EM23_VSCALE EFR32_EM23_VSCALE_1V1 +#else +#error "EFR32_EM23VSCALE_SEL is not set" +#endif + +#if (EFR32_HCLK > VSCALE_1V1_MAX_FREQ) +#error "EFR32_HCLK must be lower than VSCALE_1V1_MAX_FREQ" +#elif (EFR32_HCLK > VSCALE_1V0_MAX_FREQ) && (EFR32_EM01_VSCALE != EFR32_EM23_VSCALESEL_1V1) +#error "EFR32_EM01_VSCALE must be set to EFR32_EM23_VSCALESEL_1V1" +#endif + +#define EFR32_EM01GRPACLKSEL_NOCLOCK (1u << 0) +#define EFR32_EM01GRPACLKSEL_HFRCODPLL (1u << 1) +#define EFR32_EM01GRPACLKSEL_HFXO (1u << 2) +#define EFR32_EM01GRPACLKSEL_FSRCO (1u << 3) +#define EFR32_EM01GRPACLKSEL_HFRCOEM23 (1u << 4) +#define EFR32_EM01GRPACLKSEL_HFRCODPLLRT (1u << 5) +#define EFR32_EM01GRPACLKSEL_HFXORT (1u << 6) + +#define EFR32_EM01GRPCCLKSEL_NOCLOCK (1u << 0) +#define EFR32_EM01GRPCCLKSEL_HFRCODPLL (1u << 1) +#define EFR32_EM01GRPCCLKSEL_HFXO (1u << 2) +#define EFR32_EM01GRPCCLKSEL_FSRCO (1u << 3) +#define EFR32_EM01GRPCCLKSEL_HFRCOEM23 (1u << 4) +#define EFR32_EM01GRPCCLKSEL_HFRCODPLLRT (1u << 5) +#define EFR32_EM01GRPCCLKSEL_HFXORT (1u << 6) + +#define EFR32_EM23GRPACLKSEL_NOCLOCK (1u << 0) +#define EFR32_EM23GRPACLKSEL_LFXO (1u << 1) +#define EFR32_EM23GRPACLKSEL_LFRCO (1u << 2) +#define EFR32_EM23GRPACLKSEL_ULFRCO (1u << 3) + +#define EFR32_EM4GRPACLKSEL_NOCLOCK (1u << 0) +#define EFR32_EM4GRPACLKSEL_LFXO (1u << 1) +#define EFR32_EM4GRPACLKSEL_LFRCO (1u << 2) +#define EFR32_EM4GRPACLKSEL_ULFRCO (1u << 3) + +#define EFR32_EUSART1SEL_NOCLOCK (0u << 0) +#define EFR32_EUSART1SEL_EM01GRPCCLK (1u << 1) +#define EFR32_EUSART1SEL_HFRCOEM23 (1u << 2) +#define EFR32_EUSART1SEL_LFRCO (1u << 3) +#define EFR32_EUSART1SEL_LFXO (1u << 4) + +#define EFR32_EUSART23SEL_NOCLOCK (0u << 0) +#define EFR32_EUSART23SEL_HFRCODPLL (1u << 0) +#define EFR32_EUSART23SEL_HFRCOEM23 (1u << 1) +#define EFR32_EUSART23SEL_HFXO (1u << 2) +#define EFR32_EUSART23SEL_HFRCODPLLRT (1u << 3) +#define EFR32_EUSART23SEL_HFXORT (1u << 4) +#define EFR32_EUSART23SEL_FSRCO (1u << 5) + + +#if EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK EFR32_HCLK +#elif EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFXO +#define EFR32_EM01GRPACLK EFR32_HFXOCLK +#elif EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_FSRCO +#define EFR32_EM01GRPACLK EFR32_FSRCOCLK +#elif EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFRCOEM23 +#error "EFR32_EM01GRPACLKSEL_HFRCOEM23 is not implemented" +#elif EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFRCODPLLRT +#error "EFR32_EM01GRPACLKSEL_HFRCODPLLRT is not implemented" +#elif EFR32_EM01GRPACLKSEL == EFR32_EM01GRPACLKSEL_HFXORT +#error "EFR32_EM01GRPACLKSEL_HFXORT is not implemented" +#endif + + +#if EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK EFR32_HCLK +#elif EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFXO +#define EFR32_EM01GRPCCLK EFR32_HFXOCLK +#elif EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_FSRCO +#define EFR32_EM01GRPCCLK EFR32_FSRCOCLK +#elif EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFRCOEM23 +#error "EFR32_EM01GRPCCLKSEL_HFRCOEM23 is not implemented" +#elif EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFRCODPLLRT +#error "EFR32_EM01GRPCCLKSEL_HFRCODPLLRT is not implemented" +#elif EFR32_EM01GRPCCLKSEL == EFR32_EM01GRPCCLKSEL_HFXORT +#error "EFR32_EM01GRPCCLKSEL_HFXORT is not implemented" +#endif + + +#if EFR32_EM23GRPACLKSEL == EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK EFR32_LFXOCLK +#elif EFR32_EM23GRPACLKSEL == EFR32_EM23GRPACLKSEL_LFRCO +#define EFR32_EM23GRPACLK EFR32_LFRCOCLK +#elif EFR32_EM23GRPACLKSEL == EFR32_EM23GRPACLKSEL_ULFRCO +#define EFR32_EM23GRPACLK EFR32_ULFRCOCLK +#endif + + +#if EFR32_EM4GRPACLKSEL == EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK EFR32_LFXOCLK +#elif EFR32_EM4GRPACLKSEL == EFR32_EM4GRPACLKSEL_LFRCO +#define EFR32_EM4GRPACLK EFR32_LFRCOCLK +#elif EFR32_EM4GRPACLKSEL == EFR32_EM4GRPACLKSEL_ULFRCO +#define EFR32_EM4GRPACLK EFR32_ULFRCOCLK +#endif + +#define EFR32_LETIM1CLK EFR32_EM23GRPACLK + +#define EFR32_BURTCCLK EFR32_EM4GRPACLK + +#if EFR32_EUSART1SEL == EFR32_EUSART1SEL_EM01GRPCCLK +#define EFR32_EUSART1CLK EFR32_EM01GRPCCLK +#elif EFR32_EUSART1SEL == EFR32_EUSART1SEL_HFRCOEM23 +#define EFR32_EUSART1CLK EFR32_HFRCOEM23CLK +#elif EFR32_EUSART1SEL == EFR32_EUSART1SEL_LFRCO +#define EFR32_EUSART1CLK EFR32_LFRCOCLK +#elif EFR32_EUSART1SEL == EFR32_EUSART1SEL_LFXO +#define EFR32_EUSART1CLK EFR32_LFXOCLK +#endif + +#define EFR32_EUSART23CLK EFR32_EM01GRPCCLK + +#define EFR32_USART1CLK EFR32_PCLK + + +#define EFR32_DAC1SEL_NOCLOCK (0u << 0) +#define EFR32_DAC1SEL_EM01GRPACLK (1u << 1) +#define EFR32_DAC1SEL_EM23GRPACLK (1u << 2) +#define EFR32_DAC1SEL_FSRCO (1u << 3) +#define EFR32_DAC1SEL_HFRCOEM23 (1u << 4) + +#if EFR32_DAC1SEL == EFR32_DAC1SEL_EM01GRPACLK +#define EFR32_DAC1SELCLK EFR32_EM01GRPACLK +#elif EFR32_DAC1SEL == EFR32_DAC1SEL_EM23GRPACLK +#define EFR32_DAC1SELCLK EFR32_EM23GRPACLK +#elif EFR32_DAC1SEL == EFR32_DAC1SEL_FSRCO +#define EFR32_DAC1SELCLK EFR32_FSRCOCLK +#elif EFR32_DAC1SEL == EFR32_DAC1SEL_HFRCOEM23 +#define EFR32_DAC1SELCLK EFR32_HFRCOEM23CLK +#endif + + +/* Vector8C = Vector(40 + 4*LETIMER0_IRQn) */ +#define EFR32_LETIM1_HANDLER Vector8C +#define EFR32_LETIM1_NUMBER LETIMER0_IRQn + +/* Vector120 = Vector(40 + 4*PCNT0_IRQn) */ +#define EFR32_PCNT0_HANDLER Vector120 +#define EFR32_PCNT0_NUMBER PCNT0_IRQn + +/* Vector154 = Vector(40 + 4*LESENSE_IRQn) */ +#define EFR32_LESENSE_HANDLER Vector154 +#define EFR32_LESENSE_NUMBER LESENSE_IRQn + +/* VectorA8 = Vector(40 + 4*GPIO_ODD_IRQn) */ +#define EFR32_GPIO_ODD_HANDLER VectorA8 +#define EFR32_GPIO_ODD_NUMBER GPIO_ODD_IRQn + +/* VectorAC = Vector(40 + 4*GPIO_EVEN_IRQn) */ +#define EFR32_GPIO_EVEN_HANDLER VectorAC +#define EFR32_GPIO_EVEN_NUMBER GPIO_EVEN_IRQn + +/* Vector64 = Vector(40 + 4*USART0_RX_IRQn) */ +#define EFR32_USART1_RX_HANDLER Vector64 +#define EFR32_USART1_RX_NUMBER USART0_RX_IRQn + +/* Vector68 = Vector(40 + 4*USART0_TX_IRQn) */ +#define EFR32_USART1_TX_HANDLER Vector68 +#define EFR32_USART1_TX_NUMBER USART0_TX_IRQn + +/* Vector6C = Vector(40 + 4*EUSART0_RX_IRQn) */ +#define EFR32_EUSART1_RX_HANDLER Vector6C +#define EFR32_EUSART1_RX_NUMBER EUSART0_RX_IRQn + +/* Vector70 = Vector(40 + 4*EUSART0_TX_IRQn) */ +#define EFR32_EUSART1_TX_HANDLER Vector70 +#define EFR32_EUSART1_TX_NUMBER EUSART0_TX_IRQn + +/* Vector74 = Vector(40 + 4*EUSART1_RX_IRQn) */ +#define EFR32_EUSART2_RX_HANDLER Vector74 +#define EFR32_EUSART2_RX_NUMBER EUSART1_RX_IRQn + +/* Vector78 = Vector(40 + 4*EUSART1_TX_IRQn) */ +#define EFR32_EUSART2_TX_HANDLER Vector78 +#define EFR32_EUSART2_TX_NUMBER EUSART1_TX_IRQn + +/* Vector7C = Vector(40 + 4*EUSART2_RX_IRQn) */ +#define EFR32_EUSART3_RX_HANDLER Vector7C +#define EFR32_EUSART3_RX_NUMBER EUSART2_RX_IRQn + +/* Vector80 = Vector(40 + 4*EUSART2_TX_IRQn) */ +#define EFR32_EUSART3_TX_HANDLER Vector80 +#define EFR32_EUSART3_TX_NUMBER EUSART2_TX_IRQn + +/* Vector88 = Vector(40 + 4*BURTC_IRQn) */ +#define EFR32_BURTC_HANDLER Vector88 +#define EFR32_BURTC_NUMBER BURTC_IRQn + +/* Vector88 = Vector(40 + 4*LDMA_IRQn) */ +#define EFR32_LDMA_HANDLER Vector98 +#define EFR32_LDMA_NUMBER LDMA_IRQn + +/* Vector168 = Vector(40 + 4*RFECA0_IRQn) */ +#define EFR32_RFECA0_HANDLER Vector168 +#define EFR32_RFECA0_NUMBER RFECA0_IRQn + +/* Vector16C = Vector(40 + 4*RFECA1_IRQn) */ +#define EFR32_RFECA1_HANDLER Vector16C +#define EFR32_RFECA1_NUMBER RFECA1_IRQn + +/* Vector15C = Vector(40 + 4*SYSRTC_SEQ_IRQn) */ +#define EFR32_SYSRTC_SEQ_HANDLER Vector15C +#define EFR32_SYSRTC_SEQ_NUMBER SYSRTC_SEQ_IRQn + +/* VectorBC = Vector(40 + 4*AGC_IRQn) */ +#define EFR32_AGC_HANDLER VectorBC +#define EFR32_AGC_NUMBER AGC_IRQn + +/* VectorC0 = Vector(40 + 4*BUFC_IRQn) */ +#define EFR32_BUFC_HANDLER VectorC0 +#define EFR32_BUFC_NUMBER BUFC_IRQn + +/* VectorB8 = Vector(40 + 4*EMUDG_IRQn) */ +#define EFR32_EMUDG_HANDLER VectorB8 +#define EFR32_EMUDG_NUMBER EMUDG_IRQn + +/* VectorC8 = Vector(40 + 4*FRC_IRQn) */ +#define EFR32_FRC_HANDLER VectorC8 +#define EFR32_FRC_NUMBER FRC_IRQn + +/* VectorC4 = Vector(40 + 4*FRC_PRI_IRQn) */ +#define EFR32_FRC_PRI_HANDLER VectorC4 +#define EFR32_FRC_PRI_NUMBER FRC_PRI_IRQn + +/* VectorDC = Vector(40 + 4*HOSTMAILBOX_IRQn) */ +#define EFR32_HOSTMAILBOX_HANDLER VectorDC +#define EFR32_HOSTMAILBOX_NUMBER HOSTMAILBOX_IRQn + +/* VectorCC = Vector(40 + 4*MODEM_IRQn) */ +#define EFR32_MODEM_HANDLER VectorCC +#define EFR32_MODEM_NUMBER MODEM_IRQn + +/* VectorD0 = Vector(40 + 4*PROTIMER_IRQn) */ +#define EFR32_PROTIMER_HANDLER VectorD0 +#define EFR32_PROTIMER_NUMBER PROTIMER_IRQn + +/* VectorD4 = Vector(40 + 4*RAC_RSM_IRQn) */ +#define EFR32_RAC_RSM_HANDLER VectorD4 +#define EFR32_RAC_RSM_NUMBER RAC_RSM_IRQn + +/* VectorD8 = Vector(40 + 4*RAC_SEQ_IRQn) */ +#define EFR32_RAC_SEQ_HANDLER VectorD8 +#define EFR32_RAC_SEQ_NUMBER RAC_SEQ_IRQn + +/* VectorE0 = Vector(40 + 4*SYNTH_IRQn) */ +#define EFR32_SYNTH_HANDLER VectorE0 +#define EFR32_SYNTH_NUMBER SYNTH_IRQn + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "efr32_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif +void efr32_chip_init(void); + +void efr32_clock_init(void); + +/** + * @brief The user can overwrite the weak function in order to use his own values. + * + * @param gain LFXO gain value + * @param captune LFXO cap tuning value + */ +void efr32_get_lfxo_calibration_values(uint32_t *gain, uint32_t *captune); + +void efr32_escape_hatch(void); + +void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SILABS/EFR32FG23/platform.mk b/os/hal/ports/SILABS/EFR32FG23/platform.mk new file mode 100644 index 0000000000..2fde6be2c2 --- /dev/null +++ b/os/hal/ports/SILABS/EFR32FG23/platform.mk @@ -0,0 +1,42 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := \ + $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/hal_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := \ + $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23 \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/common + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +#include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/common/SYSTICKv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/driver.mk new file mode 100644 index 0000000000..e0c45e54ad --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.c + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.c new file mode 100644 index 0000000000..4f5e6e3173 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.c @@ -0,0 +1,211 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv3/hal_st_lld.c + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + #if EFR32_ST_USE_TIMER == 1 + #if (OSAL_ST_RESOLUTION == 32) && !EFR32_LETIM1_IS_32BITS + #error "LETIM1 is not a 32 bit timer" + #endif + + #if !EFR32_HAS_LETIM1 + #error "LETIM1 not present in the selected device" + #endif + + #if EFR32_LETIM1SEL != EFR32_LETIM1SEL_LFXO && \ + EFR32_LETIM1SEL != EFR32_LETIM1SEL_LFRCO && \ + EFR32_LETIM1SEL != EFR32_LETIM1SEL_ULFRCO + #error "EFR32_LETIM1SEL is neither EFR32_LETIM1SEL_LFXO nor EFR32_LETIM1SEL_LFRCO nor EFR32_LETIM1SEL_ULFRCO" + #endif + + #define ST_HANDLER EFR32_LETIM1_HANDLER + #define ST_NUMBER EFR32_LETIM1_NUMBER + #define ST_CLOCK_SRC EFR32_LETIM1CLK + #define ST_ENABLE_CLOCK() CMU->LFACLKEN0 |= CMU_LFACLKEN0_LETIMER0 + #define ST_SET_PRESCALER() CMU->LFAPRESC0 |= EFR32_ST_PRESC + #else + #error "EFR32_ST_USE_TIMER specifies an unsupported timer" + #endif + + #if (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 32768U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV32768 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 16386U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV16384 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 8192U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV8192 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 4096U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV4096 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 2048U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV2048 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 1024U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV1024 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 512U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV512 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 256U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV256 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 128U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV128 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 64U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV64 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 32U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV32 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 16U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV16 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 8U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV8 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 4U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV4 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 2U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV2 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 1U) + #define EFR32_ST_PRESC CMU_LFAPRESC0_LETIMER0_DIV1 + #else + #error "EFR32_ST_PRESC is not obtainable" + #endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + #error "OSAL_ST_MODE_PERIODIC is not supported by SYSTICKv3" +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + + +#if !defined(EFR32_SYSTICK_SUPPRESS_ISR) +/** + * @brief Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + st_lld_serve_interrupt(); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + osalDbgAssert((ST_CLOCK_SRC % OSAL_ST_FREQUENCY) == 0U, + "clock rounding error"); + osalDbgAssert(((ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1U) < 0x10000, + "clock prescaler overflow"); + + /* Enabling timer clock. */ + ST_ENABLE_CLOCK(); + + /* Set prescaler. */ + ST_SET_PRESCALER(); + + /* Enable timer. */ + EFR32_ST_TIM->EN_SET = LETIMER_EN_EN; + + /* Initializing the counter in free running mode. */ + EFR32_ST_TIM->IEN = 0; + EFR32_ST_TIM->IFC = _LETIMER_IFC_MASK; + EFR32_ST_TIM->CTRL = LETIMER_CTRL_REPMODE_FREE; + EFR32_ST_TIM->COMP0 = 0; + + /* Wait for command to complete. */ + while (EFR32_ST_TIM->SYNCBUSY & LETIMER_SYNCBUSY_CMD) { + } + + /* Start timer on continuous mode. */ + EFR32_ST_TIM->CNT = 0; + EFR32_ST_TIM->CMD = LETIMER_CMD_START; + +#if !defined(EFR32_SYSTICK_SUPPRESS_ISR) + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, EFR32_ST_IRQ_PRIORITY); +#endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + + /* IRQ enabled.*/ + nvicEnableVector(HANDLER_SYSTICK, EFR32_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + if ((EFR32_ST_TIM->IF & LETIMER_IF_COMP0) != 0U) { + EFR32_ST_TIM->IFC = LETIMER_IFC_COMP0; +#endif + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + } +#endif +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.h new file mode 100644 index 0000000000..bd65f9d2e9 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/hal_st_lld.h @@ -0,0 +1,210 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv3/hal_st_lld.h + * @brief ST Driver subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Counter registry initial value. + */ +#if (OSAL_ST_RESOLUTION == 32) + #define ST_INIT_VALUE 0x00FFFFFFUL +#else + #define ST_INIT_VALUE 0x0000FFFFUL +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief LETIM1x unit (by number) to be used for free running operations. + * @note You must select a 16 bits timer if a 16 bits @p systick_t type + * is required. + * @note Timer 1 supported. + */ +#if !defined(EFR32_ST_USE_TIMER) || defined(__DOXYGEN__) + #define EFR32_ST_USE_TIMER 1 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) +#if !defined(EFR32_HAS_LETIM1) + #define EFR32_HAS_LETIM1 FALSE +#endif + +#if !defined(EFR32_HAS_LETIM2) + #define EFR32_HAS_LETIM2 FALSE +#endif + +#if EFR32_ST_USE_TIMER == 1 + #if defined(EFR32_LETIM1_IS_USED) + #error "ST requires LETIM1 but the timer is already used" + #else + #define EFR32_LETIM1_IS_USED + #endif + + #define EFR32_ST_TIM LETIMER0 +#elif EFR32_ST_USE_TIMER == 2 + #if defined(EFR32_LETIM2_IS_USED) + #error "ST requires LETIM2 but the timer is already used" + #else + #define EFR32_LETIM2_IS_USED + #endif + + #define EFR32_ST_TIM LETIMER1 +#endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void st_lld_init(void); +void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + + return (systime_t)(ST_INIT_VALUE - EFR32_ST_TIM->CNT); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + + EFR32_ST_TIM->IEN = _LETIMER_IEN_RESETVALUE; + + #if (OSAL_ST_RESOLUTION == 32) + EFR32_ST_TIM->COMP0 = (uint32_t)ST_INIT_VALUE - (uint32_t)abstime; + #else + EFR32_ST_TIM->COMP0 = (uint16_t)ST_INIT_VALUE - (uint16_t)abstime; + #endif + + EFR32_ST_TIM->IEN = LETIMER_IEN_COMP0; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + + EFR32_ST_TIM->IEN = 0; +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + + st_lld_start_alarm(abstime); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)(ST_INIT_VALUE - EFR32_ST_TIM->COMP0); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return (EFR32_ST_TIM->IEN & LETIMER_IEN_COMP0) != 0U; +} + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/readme.txt b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/readme.txt new file mode 100644 index 0000000000..194c39eed7 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG14P/SYSTICKv3/readme.txt @@ -0,0 +1,37 @@ +How to use LETIMERx present on EFR32FG1X controllers as system tick. + +Also see under demos/SILABS. + +1) In your mcuconf.h make sure, that: + +#define EFR32_LETIM1SEL EFR32_LETIM1SEL_LFXO +#define EFR32_LETIM2SEL EFM32_LETIM2SEL_LFXO + +or + +#define EFM32_LETIM1SEL EFM32_LETIM1SEL_LFRCO +#define EFM32_LETIM2SEL EFM32_LETIM2SEL_LFRCO + + +2) In your chconf.h make sure, that: + +#define CH_CFG_ST_RESOLUTION 16 +#define CH_CFG_ST_TIMEDELTA 6 +#define CH_CFG_ST_FREQUENCY 1024 // If LFXO used as src clk +#define CH_CFG_ST_FREQUENCY 1024 // If LFRCO used as src clk +#define CH_CFG_ST_FREQUENCY 1000 // If ULFRCO used as src clk + + +You can't use osDelay() or other "sleeping" functions for periods +longer than: + LETIM_ARR_MAX + 1 65536 +----------------------------------- = ------------------- seconds. +LETIM_CLOCK / LETIM_CLOCK_PRESCALER CH_CFG_ST_FREQUENCY + +For instance, with CH_CFG_ST_FREQUENCY = 1024 the period is 64 seconds. + +Known good combinations of CH_CFG_ST_FREQUENCY/CH_CFG_ST_TIMEDELTA: +a) 1000/8 or 1024/8 +b) 2000/4 or 2048/4 +c) 4000/2 or 4096/2 +d) 8000/2 or 8192/2 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/driver.mk new file mode 100644 index 0000000000..a7450c4fe9 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/driver.mk @@ -0,0 +1,11 @@ +ifeq ($(USE_SMART_BUILD),yes) + +ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.c +endif + +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.c new file mode 100644 index 0000000000..b9bdecbe57 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.c @@ -0,0 +1,141 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_adc_lld.c + * @brief PLATFORM ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ADC1 driver identifier. + */ +#if (PLATFORM_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if PLATFORM_ADC_USE_ADC1 == TRUE + /* Driver initialization.*/ + adcObjectInit(&ADCD1); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + if (adcp->state == ADC_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_ADC_USE_ADC1 == TRUE + if (&ADCD1 == adcp) { + + } +#endif + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + if (adcp->state == ADC_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ +#if PLATFORM_ADC_USE_ADC1 == TRUE + if (&ADCD1 == adcp) { + + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + + (void)adcp; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + (void)adcp; +} + +#endif /* HAL_USE_ADC == TRUE */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.h new file mode 100644 index 0000000000..b27ffbc8c8 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/ADCv1/hal_adc_lld.h @@ -0,0 +1,133 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_adc_lld.h + * @brief PLATFORM ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef HAL_ADC_LLD_H +#define HAL_ADC_LLD_H + +#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Possible ADC errors mask bits. + * @{ + */ +#define ADC_ERR_DMAFAILURE 1U /**< DMA operations failure. */ +#define ADC_ERR_OVERFLOW 2U /**< ADC overflow condition. */ +#define ADC_ERR_AWD 4U /**< Watchdog triggered. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define PLATFORM_ADC_USE_ADC1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of an ADC error mask. + */ +typedef uint32_t adcerror_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the ADC driver structure. + */ +#define adc_lld_driver_fields \ + /* Dummy field, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_configuration_group_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (PLATFORM_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC == TRUE */ + +#endif /* HAL_ADC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/driver.mk new file mode 100644 index 0000000000..4f290f8d01 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_BURAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.c +endif + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.c new file mode 100644 index 0000000000..62dc3c4528 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.c @@ -0,0 +1,147 @@ +/* + ChibiOS/HAL - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_buram_lld.c + * @brief BURAM Driver subsystem low level driver source. + * + * @addtogroup BURAM + * @{ + */ +#include "hal.h" + +#if (HAL_USE_BURAM == TRUE) || defined(__DOXYGEN__) + +#include "hal_buram_lld.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Configures and activates the BURAM peripheral. + * + * @param[in] buramp pointer to the @p BURAMDriver object + * @param[in] cfgp pointer to the @p BURAMConfig object + * + * @notapi + */ +void buram_lld_start(BURAMDriver *buramp, const BURAMConfig *cfgp) { + + (void)cfgp; + + if (false) { + } + /* BURAM clock could have been enabled during the early init, + so just check if the clock is enabled yet. */ + #if BURAM_USE_BURAM1 + else if (buramp == &BURAMD1) { + if ((CMU->CLKEN0 & CMU_CLKEN0_BURAM) == 0U) { + CMU->CLKEN0_SET = CMU_CLKEN0_BURAM; + } + } + #endif + #if BURAM_USE_BURAM2 + else if (buramp == &BURAMD2) { + if ((CMU->CLKEN0 & CMU_CLKEN0_BURAM) == 0U) { + CMU->CLKEN0_SET = CMU_CLKEN0_BURAM; + } + } + #endif + #if BURAM_USE_BURAM3 + else if (buramp == &BURAMD3) { + if ((CMU->CLKEN0 & CMU_CLKEN0_BURAM) == 0U) { + CMU->CLKEN0_SET = CMU_CLKEN0_BURAM; + } + } + #endif + #if BURAM_USE_BURAM4 + else if (buramp == &BURAMD4) { + if ((CMU->CLKEN0 & CMU_CLKEN0_BURAM) == 0U) { + CMU->CLKEN0_SET = CMU_CLKEN0_BURAM; + } + } + #endif +} + +/** + * @brief Deactivates the BURAM peripheral. + * + * @param[in] buramp pointer to the @p BURAMDriver object + * + * @notapi + */ +void buram_lld_stop(BURAMDriver *buramp) { + + if (false) { + } + #if BURAM_USE_BURAM1 + if (buramp == &BURAMD1) { + #if !BURAM_USE_BURAM2 && !BURAM_USE_BURAM3 && !BURAM_USE_BURAM4 + CMU->CLKEN0_CLR = CMU_CLKEN0_BURAM; + #endif + } + #endif + #if BURAM_USE_BURAM2 + if (buramp == &BURAMD2) { + #if !BURAM_USE_BURAM1 && !BURAM_USE_BURAM3 && !BURAM_USE_BURAM4 + CMU->CLKEN0_CLR = CMU_CLKEN0_BURAM; + #endif + } + #endif + #if BURAM_USE_BURAM3 + if (buramp == &BURAMD3) { + #if !BURAM_USE_BURAM1 && !BURAM_USE_BURAM2 && !BURAM_USE_BURAM4 + CMU->CLKEN0_CLR = CMU_CLKEN0_BURAM; + #endif + } + #endif + #if BURAM_USE_BURAM4 + if (buramp == &BURAMD4) { + #if !BURAM_USE_BURAM1 && !BURAM_USE_BURAM2 && !BURAM_USE_BURAM3 + CMU->CLKEN0_CLR = CMU_CLKEN0_BURAM; + #endif + } + #endif +} + +#endif /* HAL_USE_BURAM */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.h new file mode 100644 index 0000000000..e3181ae1a8 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/BURAMv1/hal_buram_lld.h @@ -0,0 +1,116 @@ +/* + ChibiOS/HAL - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_buram_lld.h + * @brief BURAM Driver subsystem low level driver header. + * + * @addtogroup BURAM + * @{ + */ + +#ifndef HAL_BURAM_LLD_H_ +#define HAL_BURAM_LLD_H_ + + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define BURAM1_ADDRESS (BURAM_BASE + 0UL) +#define BURAM1_SIZE 32U + +#define BURAM2_ADDRESS (BURAM1_ADDRESS + BURAM1_SIZE) +#define BURAM2_SIZE 32U + +#define BURAM3_ADDRESS (BURAM2_ADDRESS + BURAM2_SIZE) +#define BURAM3_SIZE 32U + +#define BURAM4_ADDRESS (BURAM3_ADDRESS + BURAM3_SIZE) +#define BURAM4_SIZE 32U + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if BURAM1_SIZE % 32U != 0U +#error "BURAM1_SIZE has to be a multiple of 32!" +#endif + +#if BURAM2_SIZE % 32U != 0U +#error "BURAM2_SIZE has to be a multiple of 32!" +#endif + +#if BURAM3_SIZE % 32U != 0U +#error "BURAM3_SIZE has to be a multiple of 32!" +#endif + +#if BURAM4_SIZE % 32U != 0U +#error "BURAM4_SIZE has to be a multiple of 32!" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Type of a structure representing a BURAM driver. + */ +typedef struct BURAMDriver BURAMDriver; + +/** + * @brief Type of a structure representing a BURAM driver configuration. + */ +typedef struct BURAMConfig BURAMConfig; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ +#if BURAM_USE_BURAM1 && !defined(__DOXYGEN__) +extern BURAMDriver BURAMD1; +#endif + +#if BURAM_USE_BURAM2 && !defined(__DOXYGEN__) +extern BURAMDriver BURAMD2; +#endif + +#if BURAM_USE_BURAM3 && !defined(__DOXYGEN__) +extern BURAMDriver BURAMD3; +#endif + +#if BURAM_USE_BURAM4 && !defined(__DOXYGEN__) +extern BURAMDriver BURAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void buram_lld_start(BURAMDriver *sramp, const BURAMConfig *cfgp); + void buram_lld_stop(BURAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_BURAM_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/driver.mk new file mode 100644 index 0000000000..cff5aa79af --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/driver.mk @@ -0,0 +1,12 @@ +ifeq ($(USE_SMART_BUILD),yes) + +ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.c +endif + +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1 + diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.c new file mode 100644 index 0000000000..ed108ccac1 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.c @@ -0,0 +1,631 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_rtc_lld.c + * @brief EFR32 RTC subsystem low level driver source. + * + * @addtogroup RTC + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_RTC == TRUE) && (HAL_USE_BURAM == TRUE) || defined(__DOXYGEN__) + +#include "hal_buram.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * EFR32_RTCCLK_DIV is more or less arbitrary. The smaller the value + * the often overflow interrupt will occur. To avoid frequent occurance + * of interrupts set the value as high as possible. + */ + +#if EFR32_BURTCCLK == 1000U /* Clock source is ULFRCO. */ +#define EFR32_RTCCLK_DIV 1U +#define EFR32_BURTC_CFG_CNTPRESC BURTC_CFG_CNTPRESC_DIV1 +#elif EFR32_BURTCCLK == 32768U /* Clock source is LFXO or LFRCO. */ +#define EFR32_RTCCLK_DIV 1U +#define EFR32_BURTC_CFG_CNTPRESC BURTC_CFG_CNTPRESC_DIV1 +#else +#error "EFR32_RTCCLK_DIV is not obtainable" +#endif + +#define EFR32_RTCCLK (EFR32_BURTCCLK / EFR32_RTCCLK_DIV) + +#define EFR32_RTC_OVERFLOW_VALUE ((_BURTC_CNT_CNT_MASK >> _BURTC_CNT_CNT_SHIFT) + 1UL) + +#define EFR32_RTC_OVERFLOW_INTERVAL (EFR32_RTC_OVERFLOW_VALUE / EFR32_RTCCLK) + +#define EFR32_RTC_OVERFLOW_INTERVAL_REMAINDER \ + (EFR32_RTC_OVERFLOW_VALUE % EFR32_RTCCLK) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +#if (EFR32_RTC_USE_RTC1 == TRUE) && !defined(__DOXYGEN__) +RTCDriver RTCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const int rtc_day_offset_by_month[2][12] = { + [0] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }, + [1] = { 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335 } +}; + +static const int rtc_day_of_the_week[7] = { + RTC_DAY_SUNDAY, RTC_DAY_MONDAY, RTC_DAY_TUESDAY, RTC_DAY_WEDNESDAY, + RTC_DAY_THURSDAY, RTC_DAY_FRIDAY, RTC_DAY_SATURDAY +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) + +/** + * @brief Return day of week according by implementing Zeller's congruence. + * + * @param[in] year Year, e.g. 1969 + * @param[in] month Months 1..12. + * @param[in] day Day of the month 1..31 + * @return Day of week 0 .. 6, Sun .. Sat. + * + */ +__STATIC_INLINE int _rtc_lld_wday(int year, int month, int day) { + + int adjustment, mm, yy, wday; + + adjustment = (14 - month) / 12; + mm = month + 12 * adjustment - 2; + yy = year - adjustment; + + /* wday in range from 0 .. 6: Sun to Sat */ + wday = (day + (13 * mm - 1) / 5 + + yy + yy / 4 - yy / 100 + yy / 400) % 7; + + return wday; +} + +__STATIC_INLINE void _rtc_lld_to_timespec_slow(uint32_t tv_sec, uint32_t tv_msec, RTCDateTime* timespec, uint32_t dstflag) { + + int year = RTC_BASE_YEAR; + int day = tv_sec / 86400; + + /* Seconds left after all days are subtracted. */ + tv_sec = tv_sec % 86400; + + /* Calculate year in 4 years steps. */ + do { + int days_in_4years = isleap(year) ? (1 + 4 * 365) : (4 * 365); + + if (day < days_in_4years) + break; + + day -= days_in_4years; + year += 4; + } + while (true); + + /* Further calculate year in 1 years steps. */ + do { + int days_in_1year = isleap(year) ? (1 + 1 * 365) : (1 * 365); + + if (day < days_in_1year) + break; + + day -= days_in_1year; + year += 1; + } + while (true); + + /* Calculate month. */ + int month = 0; + const int *day_offset_by_month = isleap(year) ? + &rtc_day_offset_by_month[1][0] : + &rtc_day_offset_by_month[0][0]; + for (int end = 12; month != end;) { + int mid = (month + end) / 2; + + if (day_offset_by_month[mid] <= day) { + month = mid + 1; + } + else { + end = mid; + } + } + + day -= day_offset_by_month[month - 1]; + + day += 1; /* 0 .. 30 -> 1 .. 31 */; + + timespec->millisecond = tv_sec * 1000U + tv_msec; + timespec->dstflag = dstflag; + timespec->year = year - RTC_BASE_YEAR; + timespec->month = month; + timespec->day = day; + int dayofweek = _rtc_lld_wday(year, month, day); + /* wday 0 .. 6: Sun .. Sat -> 1 .. 7: Mon .. Sun */ + timespec->dayofweek = rtc_day_of_the_week[dayofweek]; +} + +__STATIC_INLINE void _rtc_lld_to_timespec_approx(uint32_t tv_sec, uint32_t tv_msec, RTCDateTime* timespec, uint32_t dstflag) { + + int day = tv_sec / 86400; + + /* Seconds left after subtracting of all days. */ + tv_sec -= day * 86400; + + /* Every fourth year from 1980 to 2096 is leap year, so we can use that + formula for the next 70 years. */ + int year = (day * 4) / (365 * 4 + 1); + + day -= year * 365 + (year + 3) / 4; + + year += RTC_BASE_YEAR; + + /* Calculate month. */ + const int *day_offset_by_month = isleap(year) ? + &rtc_day_offset_by_month[1][0] : + &rtc_day_offset_by_month[0][0]; + int month = 0; + for (int end = 12; month != end;) { + int mid = (month + end) / 2; + + if (day_offset_by_month[mid] <= day) { + month = mid + 1; + } + else { + end = mid; + } + } + + day -= day_offset_by_month[month - 1]; + + day += 1; /* 0 .. 30 -> 1 .. 31 */; + + timespec->millisecond = tv_sec * 1000U + tv_msec; + timespec->dstflag = dstflag; + timespec->year = year - RTC_BASE_YEAR; + timespec->month = month; + timespec->day = day; + int dayofweek = _rtc_lld_wday(year, month, day); + /* wday 0 .. 6: Sun .. Sat -> 1 .. 7: Mon .. Sun */ + timespec->dayofweek = rtc_day_of_the_week[dayofweek]; +} + +__STATIC_INLINE void _rtc_lld_to_timespec(uint32_t tv_sec, uint32_t tv_msec, RTCDateTime* timespec, uint32_t dstflag) { + + return _rtc_lld_to_timespec_approx(tv_sec, tv_msec, timespec, dstflag); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC common interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_BURTC_HANDLER) { + + uint32_t isr; + + OSAL_IRQ_PROLOGUE(); + + isr = BURTC->IF & _BURTC_IF_MASK; + BURTC->IF_CLR = isr; + + if ((isr & _BURTC_IF_OF_MASK) == BURTC_IF_OF) { + #if EFR32_RTC_USE_RTC1 == TRUE + /* Increment overflow counter in order of tracking time. */ + *(RTCD1.ovf_counter) += 1U; + + if (RTCD1.callback != NULL) { + RTCD1.callback(&RTCD1, RTC_EVENT_TS_OVF); + } + #endif + } + + if ((isr & _BURTC_IF_COMP_MASK) == BURTC_IF_COMP) { + /* Disable alarm. */ + BURTC->IEN_CLR = BURTC_IEN_COMP; + + #if EFR32_RTC_USE_RTC1 == TRUE + if (RTCD1.callback != NULL) { + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + } + #endif + } + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers. + * + * @notapi + */ +void rtc_lld_init(void) { + +#if EFR32_RTC_USE_RTC1 == TRUE + /* RTC object initialization. */ + rtcObjectInit(&RTCD1); + + /* Callback initially disabled. */ + RTCD1.callback = NULL; + + /* Get data from backup RAM which survives restart. */ + RTCD1.ovf_counter = buramAllocateAtI(&BURAMD1, 0, 4); + RTCD1.tv_sec = buramAllocateAtI(&BURAMD1, 4, 4); + RTCD1.tv_msec = buramAllocateAtI(&BURAMD1, 8, 4); + RTCD1.dstflag = buramAllocateAtI(&BURAMD1, 12, 4); +#endif + + /* Enable clock. */ + CMU->CLKEN0_SET = CMU_CLKEN0_BURTC; + + /* After reboot the BURTC must remain enabled. + Check this before changing its configuration. */ + if ((BURTC->EN & _BURTC_EN_MASK) == BURTC_EN_EN) { + + /* Disable BURTC if cfg prescaler is not set as wanted. */ + if ((BURTC->CFG & _BURTC_CFG_CNTPRESC_MASK) != EFR32_BURTC_CFG_CNTPRESC) { + BURTC->CMD_CLR = BURTC_CMD_STOP; + while ((BURTC->SYNCBUSY & _BURTC_SYNCBUSY_MASK) != 0U); + + BURTC->EN_CLR = BURTC_EN_EN; + while ((BURTC->EN & _BURTC_EN_DISABLING_MASK) == BURTC_EN_DISABLING); + } + } + + /* If calendar has not been initialized yet, then proceed with the + initial setup.*/ + if ((BURTC->EN & _BURTC_EN_MASK) != BURTC_EN_EN) { + + /* Note that the CFG register can only be written when BURTC + is disabled. */ + BURTC->CFG = (BURTC->CFG & ~_BURTC_CFG_CNTPRESC_MASK) | EFR32_BURTC_CFG_CNTPRESC; + + /* Enable BURTC. */ + BURTC->EN_SET = BURTC_EN_EN; + + /* Clear counter. */ + BURTC->CNT_CLR = _BURTC_CNT_CNT_MASK; + + #if EFR32_RTC_USE_RTC1 == TRUE + *(RTCD1.ovf_counter) = 0U; + *(RTCD1.tv_sec) = 0U; + *(RTCD1.tv_msec) = 0U; + *(RTCD1.dstflag) = 0U; + #endif + + /* Clear interrupt flags. */ + BURTC->IF_CLR = _BURTC_IF_MASK; + + /* Enable interrupts. */ + BURTC->IEN_CLR = _BURTC_IEN_MASK; + BURTC->IEN_SET = BURTC_IEN_OF; + } + else { + + /* Clear interrupt flags. */ + BURTC->IF_CLR = _BURTC_IF_MASK; + + /* If BURTC was enabled before, the interrupts ae still enabled + but inactive because BURTC is not started yet. */ + } + + /* Start BURTC. */ + BURTC->CMD_SET = BURTC_CMD_START; + while ((BURTC->SYNCBUSY & _BURTC_SYNCBUSY_MASK) != 0U); + + /* IRQ vectors permanently assigned to this driver.*/ + nvicEnableVector(EFR32_BURTC_NUMBER, EFR32_BURTC_PRIORITY); +} + +__STATIC_INLINE void rtc_lld_set_time_slow(RTCDriver* rtcp, const RTCDateTime* timespec) { + + syssts_t sts; + uint32_t tv_sec, tv_msec; + + /* Number of leap corrections to apply up to end of last year. */ + const int leap_days_to_rtc_base_year = (RTC_BASE_YEAR - 1) / 4 - + (RTC_BASE_YEAR - 1) / 100 + + (RTC_BASE_YEAR - 1) / 400; + + const int last_year = (RTC_BASE_YEAR - 1) + timespec->year; + + const int leap_days_to_last_year = last_year / 4 - + last_year / 100 + + last_year / 400 - + leap_days_to_rtc_base_year; + + const int month = timespec->month - 1; /* 1 .. 12 -> 0 .. 11 */ + + int day = timespec->day - 1; /* 1 .. 31 -> 0 .. 30 */ + + const int *day_offset_by_month = isleap(RTC_BASE_YEAR + timespec->year) ? + &rtc_day_offset_by_month[1][0] : + &rtc_day_offset_by_month[0][0]; + + day += timespec->year * 365 + leap_days_to_last_year + + day_offset_by_month[month]; + + tv_sec = day * 86400 + timespec->millisecond / 1000; + tv_msec = timespec->millisecond % 1000; + + /* Entering a reentrant critical zone. */ + sts = osalSysGetStatusAndLockX(); + + /* Clear all counters resetting the overflow counter as well. */ + BURTC->CNT_CLR = _BURTC_CNT_CNT_MASK; + + *(rtcp->ovf_counter) = 0U; + *(rtcp->tv_sec) = tv_sec; + *(rtcp->tv_msec) = tv_msec; + *(rtcp->dstflag) = timespec->dstflag; + + while ((BURTC->SYNCBUSY & _BURTC_SYNCBUSY_MASK) != 0U); + + if (rtcp->callback != NULL) { + rtcp->callback(rtcp, RTC_EVENT_TIME_SET); + } + +/* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +__STATIC_INLINE void rtc_lld_set_time_approx(RTCDriver *rtcp, const RTCDateTime *timespec) { + + syssts_t sts; + uint32_t tv_sec, tv_msec; + + int year = timespec->year; + + const int *day_offset_by_month = isleap(RTC_BASE_YEAR + year) ? + &rtc_day_offset_by_month[1][0] : + &rtc_day_offset_by_month[0][0]; + + int month = timespec->month - 1; /* 1 .. 12 -> 0 .. 11 */ + + int day = timespec->day - 1; /* 1 .. 31 -> 0 .. 30 */ + + day += year * 365 + (year + 3) / 4 + day_offset_by_month[month]; + + tv_sec = day * 86400 + timespec->millisecond / 1000; + tv_msec = timespec->millisecond % 1000; + + /* Entering a reentrant critical zone. */ + sts = osalSysGetStatusAndLockX(); + + /* Clear all counters resetting the overflow counter as well. */ + BURTC->CNT_CLR = _BURTC_CNT_CNT_MASK; + + *(rtcp->ovf_counter) = 0U; + *(rtcp->tv_sec) = tv_sec; + *(rtcp->tv_msec) = tv_msec; + *(rtcp->dstflag) = timespec->dstflag; + + while ((BURTC->SYNCBUSY & _BURTC_SYNCBUSY_MASK) != 0U); + + if (rtcp->callback != NULL) { + rtcp->callback(rtcp, RTC_EVENT_TIME_SET); + } + +/* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Set current time. + * @note Fractional part of second will be silently ignored. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { + + return rtc_lld_set_time_approx(rtcp, timespec); +} + +/** + * @brief Get current time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver* rtcp, RTCDateTime* timespec) { + + syssts_t sts; + uint32_t cnt; + uint32_t ovf_counter, tv_sec, tv_msec, dstflag; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Cache overflow counter. */ + ovf_counter = *(rtcp->ovf_counter); + tv_sec = *(rtcp->tv_sec); + tv_msec = *(rtcp->tv_msec); + dstflag = *(rtcp->dstflag); + + /* Read counter. */ + cnt = BURTC->CNT; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); + + tv_sec += (ovf_counter * EFR32_RTC_OVERFLOW_INTERVAL) + + (ovf_counter * EFR32_RTC_OVERFLOW_INTERVAL_REMAINDER) / EFR32_RTCCLK + + (cnt / EFR32_RTCCLK); + + tv_msec += (cnt % EFR32_RTCCLK * 1000U) / EFR32_RTCCLK; + + tv_sec += tv_msec / 1000U; + tv_msec = tv_msec % 1000U; + + _rtc_lld_to_timespec(tv_sec, tv_msec, timespec, dstflag); +} + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Set alarm time. + * @note Default value after BKP domain reset for both comparators is 0. + * @note Function does not performs any checks of alarm time validity. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure. + * @param[in] alarm alarm identifier. Can only be 0. + * @param[in] alarmspec pointer to a @p RTCAlarm structure. + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDriver* rtcp, + rtcalarm_t alarm, + const RTCAlarm* alarmspec) { + + (void)rtcp; + syssts_t sts; + uint32_t cnt; + + osalDbgAssert(alarm == 0, "unknown alarm"); + + if (alarm == 0) { + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + if (alarmspec != NULL) { + /* Enable alarm. */ + + cnt = BURTC->CNT; + + /* Can overflow but don't care. */ + cnt += (alarmspec->tv_sec * EFR32_RTCCLK) + + (alarmspec->tv_usec * EFR32_RTCCLK) / 1000000U; + + BURTC->COMP = cnt; + + /* Enable alarm. */ + BURTC->IEN_SET = BURTC_IEN_COMP; + } + else { + /* Disable alarm. */ + BURTC->IEN_CLR = BURTC_IEN_COMP; + } + + /* Clear alarm interrupt flag. */ + BURTC->IF_CLR = BURTC_IF_COMP; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); + } +} + +/** + * @brief Get alarm time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_get_alarm(RTCDriver* rtcp, + rtcalarm_t alarm, + RTCAlarm* alarmspec) { + + (void)rtcp; + syssts_t sts; + uint32_t cnt, comp; + + if (alarm == 0) { + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + comp = BURTC->COMP; + + cnt = BURTC->CNT; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); + + uint32_t diff_comp_cnt = comp - cnt; + + if (diff_comp_cnt > 0U) { + alarmspec->tv_sec = diff_comp_cnt / EFR32_RTCCLK; + alarmspec->tv_usec = (diff_comp_cnt % EFR32_RTCCLK * 1000000U) / EFR32_RTCCLK; + } + else { + alarmspec->tv_sec = 0; + alarmspec->tv_usec = 0; + } + } +} +#endif /* RTC_ALARMS > 0 */ + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver* rtcp, rtccb_t callback) { + + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtcp->callback = callback; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.h new file mode 100644 index 0000000000..09c52ffda4 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/BURTCv1/hal_rtc_lld.h @@ -0,0 +1,154 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_rtc_lld.h + * @brief EFR32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if (HAL_USE_RTC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + * @{ + */ +/** + * @brief Callback support int the driver. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief Number of alarms available. + */ +#define RTC_ALARMS EFR32_RTC_NUM_ALARMS + +/** + * @brief Presence of a local persistent storage. + */ +#define RTC_HAS_STORAGE FALSE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name EFR32 configuration options + * @{ + */ +/** + * @brief RTCD1 driver enable switch. + * @details If set to @p TRUE the support for RTC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_RTC_USE_RTC1) || defined(__DOXYGEN__) +#define EFR32_RTC_USE_RTC1 TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#if (RTC_SUPPORTS_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_TIME_SET = 0, /**< New time set. */ + RTC_EVENT_ALARM = 1, /**< Wakeup. */ + RTC_EVENT_TS_OVF = 2 /**< Time stamp overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver* rtcp, rtcevent_t evt); +#endif + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct { + uint32_t tv_sec; /**< Seconds. */ + uint32_t tv_usec; /**< Microseconds. */ +} RTCAlarm; +#endif + +/** + * @brief Implementation-specific @p RTCDriver fields. + */ +#define rtc_lld_driver_fields \ + volatile uint32_t *ovf_counter; /**< BURTC overflow counter. */ \ + volatile uint32_t *tv_sec; /**< Seconds since RTC_BASE_YEAR.. */ \ + volatile uint32_t *tv_msec; /**< .. and additional milliseconds. */ \ + volatile uint32_t *dstflag; /**< Keep DST flag. */ \ + rtccb_t callback /**< Callback function. */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (EFR32_RTC_USE_RTC1 == TRUE) && !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif +void rtc_lld_init(void); +void rtc_lld_set_time(RTCDriver* rtcp, const RTCDateTime* timespec); +void rtc_lld_get_time(RTCDriver* rtcp, RTCDateTime* timespec); +#if RTC_ALARMS > 0 +void rtc_lld_set_alarm(RTCDriver* rtcp, + rtcalarm_t alarm, + const RTCAlarm* alarmspec); +void rtc_lld_get_alarm(RTCDriver* rtcp, + rtcalarm_t alarm, + RTCAlarm* alarmspec); +#endif +#if RTC_SUPPORTS_CALLBACKS == TRUE +void rtc_lld_set_callback(RTCDriver* rtcp, rtccb_t callback); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC == TRUE */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/driver.mk new file mode 100644 index 0000000000..482a860357 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/driver.mk @@ -0,0 +1,11 @@ +ifeq ($(USE_SMART_BUILD),yes) + +ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.c +endif + +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.c new file mode 100644 index 0000000000..5b18b4d301 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.c @@ -0,0 +1,282 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_dac_lld.c + * @brief EFR32 DAC subsystem low level driver source. + * + * @addtogroup DAC + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define EFF32_DAC1_CLK_EN_MASK 0x03 +#define EFF32_DAC1_CLK_EN_SHIFT(ch) (1U << ((ch) + 0)) + +#define EFF32_DAC2_CLK_EN_MASK 0x0C +#define EFF32_DAC2_CLK_EN_SHIFT(ch) (1U << ((ch) + 2)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief DAC1 CH1 driver identifier.*/ +#if (EFR32_DAC_USE_DAC1_CH1 == TRUE) || defined(__DOXYGEN__) +DACDriver DACD1; +#endif + +/** @brief DAC1 CH2 driver identifier.*/ +#if (EFR32_DAC_USE_DAC1_CH2 == TRUE) || defined(__DOXYGEN__) +#if !EFR32_DAC_DUAL_MODE +DACDriver DACD2; +#else +#error "DAC1 CH2 not independently available in dual mode" +#endif +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/* + * @brief Global DAC-related data structures. + */ +static struct +{ + /** + * @brief Mask of the allocated streams. + */ + uint32_t clk_en_mask; + +} dac; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level DAC driver initialization. + * + * @notapi + */ +void dac_lld_init(void) +{ + +#if EFR32_DAC_USE_DAC1_CH1 == TRUE + dacObjectInit(&DACD1); +#endif + +#if EFR32_DAC_USE_DAC1_CH2 == TRUE + dacObjectInit(&DACD2); +#endif + + dac.clk_en_mask = 0U; +} + +/** + * @brief Configures and activates the DAC peripheral. + * + * @param[in] dacp pointer to the @p DACDriver object + * + * @notapi + */ +msg_t dac_lld_start(DACDriver *dacp) +{ + + /* If the driver is in DAC_STOP state then a full initialization is + required.*/ + if (dacp->state == DAC_STOP) + { + dacchannel_t channel = 0; + + /* Enable DAC clock. DMA channel allocation is deferred to conversion + start and only allocated if a group conversion is used.*/ + + if (false) + { + } + +#if EFR32_DAC_USE_DAC1_CH1 == TRUE + else if (&DACD1 == dacp) + { + /* Enable clock only if disabled. The clock can be shared with CH2. */ + if ((dac.clk_en_mask & EFF32_DAC1_CLK_EN_MASK) == 0U) + { + CMU->CLKEN1 = (CMU->CLKEN1 & ~_CMU_CLKEN1_VDAC0_MASK) |\ + CMU_CLKEN1_VDAC0; + } + + dac.clk_en_mask |= EFF32_DAC1_CLK_EN_SHIFT(channel); + } +#endif + +#if EFR32_DAC_USE_DAC1_CH2 == TRUE + else if (&DACD2 == dacp) + { + channel = 1; + + /* Enable clock only if disabled. The clock can be shared with CH1. */ + if ((dac.clk_en_mask & EFF32_DAC1_CLK_EN_MASK) == 0U) + { + CMU->CLKEN1 = (CMU->CLKEN1 & ~_CMU_CLKEN1_VDAC0_MASK) |\ + CMU_CLKEN1_VDAC0; + } + + dac.clk_en_mask |= EFF32_DAC1_CLK_EN_SHIFT(channel); + } +#endif + else + { + osalDbgAssert(false, "unknown DAC instance"); + return HAL_RET_NO_RESOURCE; + } + } + + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the DAC peripheral. + * + * @param[in] dacp pointer to the @p DACDriver object + * + * @notapi + */ +void dac_lld_stop(DACDriver *dacp) +{ + + /* If in ready state then disables the DAC clock.*/ + if (dacp->state == DAC_READY) + { + dacchannel_t channel = 0; + +#if EFR32_DAC_USE_DAC1_CH1 == TRUE + if (&DACD1 == dacp) + { + dac.clk_en_mask &= ~EFF32_DAC1_CLK_EN_SHIFT(channel); + + if ((dac.clk_en_mask & EFF32_DAC1_CLK_EN_MASK) == 0U) + { + CMU->CLKEN1 = (CMU->CLKEN1 & ~_CMU_CLKEN1_VDAC0_MASK) |\ + CMU_CLKEN1_VDAC0_DEFAULT; + } + + return; + } +#endif + +#if EFR32_DAC_USE_DAC1_CH2 == TRUE + if (&DACD2 == dacp) + { + channel = 1; + + dac.clk_en_mask &= ~EFF32_DAC1_CLK_EN_SHIFT(channel); + + if ((dac.clk_en_mask & EFF32_DAC1_CLK_EN_MASK) == 0U) + { + CMU->CLKEN1 = (CMU->CLKEN1 & ~_CMU_CLKEN1_VDAC0_MASK) |\ + CMU_CLKEN1_VDAC0_DEFAULT; + } + + return; + } +#endif + } +} + +/** + * @brief Outputs a value directly on a DAC channel. + * + * @param[in] dacp pointer to the @p DACDriver object + * @param[in] channel DAC channel number + * @param[in] sample value to be output + * + * @api + */ +msg_t dac_lld_put_channel(DACDriver *dacp, + dacchannel_t channel, + dacsample_t sample) +{ + + (void)dacp; + (void)channel; + (void)sample; + + return HAL_RET_SUCCESS; +} + +/** + * @brief Starts a DAC conversion. + * @details Starts an asynchronous conversion operation. + * @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the + * callback are wrong because two samples are packed in a single + * dacsample_t element. This will not be corrected, do not rely + * on those parameters. + * @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated + * as a single 16 bits sample and packed into a single dacsample_t + * element. The num_channels must be set to one in the group + * conversion configuration structure. + * + * @param[in] dacp pointer to the @p DACDriver object + * + * @notapi + */ +msg_t dac_lld_start_conversion(DACDriver *dacp) +{ + + (void)dacp; + + osalDbgAssert(false, "not implemented"); + + return HAL_RET_HW_FAILURE; +} + +/** + * @brief Stops an ongoing conversion. + * @details This function stops the currently ongoing conversion and returns + * the driver in the @p DAC_READY state. If there was no conversion + * being processed then the function does nothing. + * + * @param[in] dacp pointer to the @p DACDriver object + * + * @iclass + */ +void dac_lld_stop_conversion(DACDriver *dacp) +{ + + (void)dacp; + + osalDbgAssert(false, "not implemented"); +} + +#endif /* HAL_USE_DAC == TRUE */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.h new file mode 100644 index 0000000000..21c411f91d --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/DACv1/hal_dac_lld.h @@ -0,0 +1,177 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_dac_lld.h + * @brief EFR32 DAC subsystem low level driver header. + * + * @addtogroup DAC + * @{ + */ + +#ifndef HAL_DAC_LLD_H +#define HAL_DAC_LLD_H + +#if (HAL_USE_DAC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define DAC_LLD_ENHANCED_API + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Enables the DAC dual mode. + * @note In dual mode DAC second channels cannot be accessed individually. + */ +#if !defined(EFR32_DAC_DUAL_MODE) || defined(__DOXYGEN__) +#define EFR32_DAC_DUAL_MODE FALSE +#endif + +/** + * @brief DAC1 CH1 driver enable switch. + * @details If set to @p TRUE the support for DAC1 channel 1 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__) +#define EFR32_DAC_USE_DAC1_CH1 FALSE +#endif + +/** + * @brief DAC1 CH2 driver enable switch. + * @details If set to @p TRUE the support for DAC1 channel 2 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__) +#define EFR32_DAC_USE_DAC1_CH2 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if EFR32_DAC_USE_DAC1_CH1 && !EFR32_HAS_DAC1_CH1 +#error "DAC1 CH1 not present in the selected device" +#endif + +#if EFR32_DAC_USE_DAC1_CH2 && !EFR32_HAS_DAC1_CH2 +#error "DAC1 CH2 not present in the selected device" +#endif + +#if !defined(EFR32_DMA_REQUIRED) +#define EFR32_DMA_REQUIRED +#endif + +/** + * @brief Maximum number of DAC channels per unit. + */ +#if EFR32_DAC_DUAL_MODE == TRUE +#define DAC_MAX_CHANNELS 2 +#else +#define DAC_MAX_CHANNELS 1 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a DAC channel index. + */ +typedef uint32_t dacchannel_t; + +/** + * @brief Type representing a DAC sample. + */ +typedef uint16_t dacsample_t; + +/** + * @brief Possible DAC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */ +} dacerror_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the DAC driver structure. + */ +#define dac_lld_driver_fields \ + /* Dummy field, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the DAC configuration structure. + */ +#define dac_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the DAC group configuration structure. + */ +#define dac_lld_conversion_group_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if EFR32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__) +extern DACDriver DACD1; +#endif + +#if EFR32_DAC_USE_DAC1_CH2 && !EFR32_DAC_DUAL_MODE && !defined(__DOXYGEN__) +extern DACDriver DACD2; +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + void dac_lld_init(void); + msg_t dac_lld_start(DACDriver *dacp); + void dac_lld_stop(DACDriver *dacp); + msg_t dac_lld_put_channel(DACDriver *dacp, + dacchannel_t channel, + dacsample_t sample); + msg_t dac_lld_start_conversion(DACDriver *dacp); + void dac_lld_stop_conversion(DACDriver *dacp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_DAC == TRUE */ + +#endif /* HAL_DAC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/driver.mk new file mode 100644 index 0000000000..39d276bf8e --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.c + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.c b/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.c new file mode 100644 index 0000000000..8ff38de722 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.c @@ -0,0 +1,345 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DMAv1/efr32_dma.c + * @brief Enhanced DMA helper driver code. + * + * @addtogroup EFR32_DMA + * @details DMA sharing helper driver. In the EFR32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(EFR32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA streams in @p dma.allocated_mask. + */ +#define EFR32_DMA_STREAMS_MASK 0x000000FFU + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p EFR32_DMA_STREAM0, @p EFR32_DMA1_STREAM1 etc. + */ +const efr32_dma_stream_t _efr32_dma_streams[EFR32_DMA_STREAMS] = { + {&(LDMA->CH[0]), &(LDMAXBAR->CH[0].REQSEL), 0}, + {&(LDMA->CH[1]), &(LDMAXBAR->CH[1].REQSEL), 1}, + {&(LDMA->CH[2]), &(LDMAXBAR->CH[2].REQSEL), 2}, + {&(LDMA->CH[3]), &(LDMAXBAR->CH[3].REQSEL), 3}, + {&(LDMA->CH[4]), &(LDMAXBAR->CH[4].REQSEL), 4}, + {&(LDMA->CH[5]), &(LDMAXBAR->CH[5].REQSEL), 5}, + {&(LDMA->CH[6]), &(LDMAXBAR->CH[6].REQSEL), 6}, + {&(LDMA->CH[7]), &(LDMAXBAR->CH[7].REQSEL), 7}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Global DMA-related data structures. + */ +static struct { + /** + * @brief Mask of the allocated streams. + */ + uint32_t allocated_mask; + + /** + * @brief DMA IRQ redirectors. + */ + struct { + /** + * @brief DMA callback function. + */ + efr32_dmaisr_t func; + + /** + * @brief DMA callback parameter. + */ + void *param; + } streams[EFR32_DMA_STREAMS]; +} dma; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief LDMA shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_LDMA_HANDLER) { + unsigned i; + uint32_t flags; + uint32_t ch_err; + + OSAL_IRQ_PROLOGUE(); + + flags = LDMA->IF; + + if ((flags & EFR32_DMA_ISR_ERROR_MASK) != 0U) { + ch_err = (LDMA->STATUS & _LDMA_STATUS_CHERROR_MASK) >> _LDMA_STATUS_CHERROR_SHIFT; + } + else { + ch_err = EFR32_DMA_STREAMS; + } + + LDMA->IF_CLR = flags; + + for (i = 0U; i < EFR32_DMA_STREAMS; i++) { + if (dma.streams[i].func) { + uint32_t mask = EFR32_DMA_ISR_DONE_MASK(i); + + if (i == ch_err) { + mask |= EFR32_DMA_ISR_ERROR_MASK; + dma.streams[i].func(dma.streams[i].param, flags & mask); + } + else if ((flags & mask) != 0U) { + dma.streams[i].func(dma.streams[i].param, flags & mask); + } + } + } + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EFR32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + unsigned i; + + dma.allocated_mask = 0U; + for (i = 0U; i < EFR32_DMA_STREAMS; i++) { + dma.streams[i].func = NULL; + dma.streams[i].param = NULL; + } +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * + * @param[in] id numeric identifiers of a specific stream or: + * - @p EFR32_DMA_STREAM_ID_ANY for any stream. + * - @p EFR32_DMA_STREAM_ID_ANY_DMA1 for any stream + * on DMA1. + * - @p EFR32_DMA_STREAM_ID_ANY_DMA2 for any stream + * on DMA2. + * . + * @param[in] priority IRQ priority for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return Pointer to the allocated @p efr32_dma_stream_t + * structure. + * @retval NULL if a/the stream is not available. + * + * @iclass + */ +const efr32_dma_stream_t *dmaStreamAllocI(uint32_t id, + uint32_t priority, + efr32_dmaisr_t func, + void *param) { + uint32_t i, startid, endid; + + osalDbgCheckClassI(); + + if (id < EFR32_DMA_STREAMS) { + startid = id; + endid = id; + } +#if EFR32_DMA_SUPPORTS_DMAMUX == TRUE + else if (id == EFR32_DMA_STREAM_ID_ANY) { + startid = 0U; + endid = EFR32_DMA_STREAMS - 1U; + } +#endif + else { + osalDbgCheck(false); + return NULL; + } + + /* Enabling DMA clocks required by the current streams set. */ + if ((dma.allocated_mask & EFR32_DMA_STREAMS_MASK) == 0U) { + CMU->CLKEN0_SET = CMU_CLKEN0_LDMA | CMU_CLKEN0_LDMAXBAR; + + LDMA->EN_SET = LDMA_EN_EN; + + LDMA->CHDIS_SET = _LDMA_CHDIS_MASK; + + LDMA->IEN_CLR = _LDMA_IEN_MASK; + + LDMA->IF_CLR = _LDMA_IF_MASK; + + LDMA->IEN_SET = LDMA_IEN_ERROR; + + nvicClearPending(EFR32_LDMA_NUMBER); + + nvicEnableVector(EFR32_LDMA_NUMBER, priority); + } + + for (i = startid; i <= endid; i++) { + uint32_t mask = (1U << i); + + if ((dma.allocated_mask & mask) == 0U) { + const efr32_dma_stream_t *dmastp = EFR32_DMA_STREAM(i); + + /* Installs the DMA handler.*/ + dma.streams[i].func = func; + dma.streams[i].param = param; + dma.allocated_mask |= mask; + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + + return dmastp; + } + } + + return NULL; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * + * @param[in] id numeric identifiers of a specific stream or: + * - @p EFR32_DMA_STREAM_ID_ANY for any stream. + * - @p EFR32_DMA_STREAM_ID_ANY_DMA1 for any stream + * on DMA1. + * - @p EFR32_DMA_STREAM_ID_ANY_DMA2 for any stream + * on DMA2. + * . + * @param[in] priority IRQ priority for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return Pointer to the allocated @p efr32_dma_stream_t + * structure. + * @retval NULL if a/the stream is not available. + * + * @api + */ +const efr32_dma_stream_t *dmaStreamAlloc(uint32_t id, + uint32_t priority, + efr32_dmaisr_t func, + void *param) { + const efr32_dma_stream_t *dmastp; + + osalSysLock(); + dmastp = dmaStreamAllocI(id, priority, func, param); + osalSysUnlock(); + + return dmastp; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * + * @iclass + */ +void dmaStreamFreeI(const efr32_dma_stream_t *dmastp) { + + osalDbgCheck(dmastp != NULL); + + /* Check if the streams is not taken.*/ + osalDbgAssert((dma.allocated_mask & (1U << dmastp->selfindex)) != 0U, + "not allocated"); + + /* Marks the stream as not allocated.*/ + dma.allocated_mask &= ~(1U << dmastp->selfindex); + + if ((dma.allocated_mask & EFR32_DMA_STREAMS_MASK) == 0U) { + /* Disable interrupt that is not more requiered. */ + nvicDisableVector(EFR32_LDMA_NUMBER); + + nvicClearPending(EFR32_LDMA_NUMBER); + + LDMA->IEN_CLR = _LDMA_IEN_MASK; + + LDMA->IF_CLR = _LDMA_IF_MASK; + + LDMA->CHDIS_SET = _LDMA_CHDIS_MASK; + + /* Disable LDMA unit. */ + LDMA->EN_CLR = LDMA_EN_EN; + + /* Shutting down clocks that are no more required, if any.*/ + CMU->CLKEN0_CLR = CMU_CLKEN0_LDMA | CMU_CLKEN0_LDMAXBAR; + } +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * + * @api + */ +void dmaStreamFree(const efr32_dma_stream_t *dmastp) { + + osalSysLock(); + dmaStreamFreeI(dmastp); + osalSysUnlock(); +} + +#endif /* EFR32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.h b/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.h new file mode 100644 index 0000000000..01c6376280 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/DMAv1/efr32_dma.h @@ -0,0 +1,362 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DMAv1/efr32_dma.h + * @brief Enhanced-DMA helper driver header. + * + * @addtogroup EFR32_DMA + * @{ + */ + +#ifndef EFR32_DMA_H +#define EFR32_DMA_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @details This is the total number of streams among all the DMA units. + */ +#define EFR32_DMA_STREAMS 8U + + +/** + * @brief Error mask of the ISR bits. + */ +#define EFR32_DMA_ISR_ERROR_MASK 0x80000000U + +/** + * @brief Done mask of the ISR bits. + */ +#define EFR32_DMA_ISR_DONE_MASK(id) (1U << EFR32_DMA_STREAM(id)->selfindex) + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define EFR32_DMA_ISR_MASK(id) (EFR32_DMA_ISR_ERROR_MASK | EFR32_DMA_ISR_DONE_MASK(id)) + +/** + * @brief Checks if a DMA stream id is within the valid range. + * + * @param[in] id DMA stream id + * @retval The check result. + * @retval false invalid DMA stream. + * @retval true correct DMA stream. + */ +#define EFR32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ + ((id) <= EFR32_DMA_STREAMS)) + +/** + * @name Special stream identifiers + * @{ + */ +#define EFR32_DMA_STREAM_ID_ANY EFR32_DMA_STREAMS +/** @} */ + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a efr32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the efr32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define EFR32_DMA_STREAM(id) (&_efr32_dma_streams[id]) + +#define EFR32_DMA1_STREAM0 EFR32_DMA_STREAM(0) +#define EFR32_DMA1_STREAM1 EFR32_DMA_STREAM(1) +#define EFR32_DMA1_STREAM2 EFR32_DMA_STREAM(2) +#define EFR32_DMA1_STREAM3 EFR32_DMA_STREAM(3) +#define EFR32_DMA1_STREAM4 EFR32_DMA_STREAM(4) +#define EFR32_DMA1_STREAM5 EFR32_DMA_STREAM(5) +#define EFR32_DMA1_STREAM6 EFR32_DMA_STREAM(6) +#define EFR32_DMA1_STREAM7 EFR32_DMA_STREAM(7) +/** @} */ + +/** + * @name CTRL register constants + * @{ + */ +#define EFR32_DMA_CH_CTRL_DSTMODE_ABSOLUTE (0U << 31) +#define EFR32_DMA_CH_CTRL_DSTMODE_RELATIVE (1U << 31) + +#define EFR32_DMA_CH_CTRL_SRCMODE_ABSOLUTE (0U << 30) +#define EFR32_DMA_CH_CTRL_SRCMODE_RELATIVE (1U << 30) + +#define EFR32_DMA_CH_CTRL_DSTINC_ONE (0U << 28) +#define EFR32_DMA_CH_CTRL_DSTINC_TWO (1U << 28) +#define EFR32_DMA_CH_CTRL_DSTINC_FOUR (2U << 28) +#define EFR32_DMA_CH_CTRL_DSTINC_NONE (3U << 28) + +#define EFR32_DMA_CH_CTRL_SIZE_BYTE (0U << 26) +#define EFR32_DMA_CH_CTRL_SIZE_HALFWORD (1U << 26) +#define EFR32_DMA_CH_CTRL_SIZE_WORD (2U << 26) + +#define EFR32_DMA_CH_CTRL_SRCINC_ONE (0U << 24) +#define EFR32_DMA_CH_CTRL_SRCINC_TWO (1U << 24) +#define EFR32_DMA_CH_CTRL_SRCINC_FOUR (2U << 24) +#define EFR32_DMA_CH_CTRL_SRCINC_NONE (3U << 24) + +#define EFR32_DMA_CH_CTRL_IGNORESREQ (1U << 23) + +#define EFR32_DMA_CH_CTRL_DECLOOPCNT (1U << 22) + +#define EFR32_DMA_CH_CTRL_REQMODE_BLOCK (0U << 21) +#define EFR32_DMA_CH_CTRL_REQMODE_ALL (1U << 21) + +#define EFR32_DMA_CH_CTRL_DONEIEN (1U << 20) + +#define EFR32_DMA_CH_CTRL_BLOCKSIZE_ALL (15U << 16) + +#define EFR32_DMA_CH_CTRL_BYTESWAP (1U << 15) + +#define EFR32_DMA_CH_CTRL_XFERCNT(size) (((size) - 1) << 4) + +#define EFR32_DMA_CH_CTRL_STRUCTREQ (1U << 3) + +#define EFR32_DMA_CH_CTRL_STRUCTTYPE_TRANSFER (0U << 0) +#define EFR32_DMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (1U << 0) +#define EFR32_DMA_CH_CTRL_STRUCTTYPE_WRITE (2U << 0) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(EFR32_HAS_DMA) +#error "EFR32_HAS_DMA missing in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EFR32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags content of the ISR register, see EFR32_DMA_ISR_MASK + */ +typedef void (*efr32_dmaisr_t)(void* p, uint32_t flags); + +/** + * @brief EFR32 DMA stream descriptor structure. + */ +typedef struct { + LDMA_CH_TypeDef *stream; /**< @brief Associated DMA stream. */ + volatile uint32_t *reqsel; /**< @brief Assoc. REQSEL register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ +} efr32_dma_stream_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * @param[in] addr value to be written in the CHx_SRC register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->stream->SRC = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * @param[in] addr value to be written in the CHx_DST register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->stream->DST = (uint32_t)(addr); \ +} + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * @param[in] mode value to be written in the CTRL register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->stream->CTRL = mode; \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + dmaStreamClearInterrupt(dmastp); \ + LDMA->IEN_SET = (1U << (dmastp)->selfindex); \ + LDMA->CHEN_SET = (1U << (dmastp)->selfindex); \ + *(dmastp)->reqsel = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE; \ + LDMA->SWREQ_SET = (1U << (dmastp)->selfindex); \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream, waits for the disable + * operation to complete and then clears any pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + LDMA->CHDIS_SET = (1U << (dmastp)->selfindex); \ + LDMA->IEN_CLR = (1U << (dmastp)->selfindex); \ + dmaStreamClearInterrupt(dmastp); \ + (dmastp)->stream->CFG = _LDMA_CH_CFG_RESETVALUE; \ + (dmastp)->stream->LOOP = _LDMA_CH_LOOP_RESETVALUE; \ + (dmastp)->stream->LINK = _LDMA_CH_LINK_RESETVALUE; \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + LDMA->IF_CLR = (1U << (dmastp)->selfindex); \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + * @param[in] mode value to be written in the CTRL register, this value + * is implicitly ORed with: + * - @p EFR32_DMA_CH_CTRL_DSTMODE_ABSOLUTE + * - @p EFR32_DMA_CH_CTRL_SRCMODE_ABSOLUTE + * - @p EFR32_DMA_CH_CTRL_SIZE_BYTE + * - @p EFR32_DMA_CH_CTRL_DSTINC_ONE + * - @p EFR32_DMA_CH_CTRL_SRCINC_ONE + * - @p EFR32_DMA_CH_CTRL_REQMODE_ALL + * - @p EFR32_DMA_CH_CTRL_BLOCKSIZE_ALL + * - @p EFR32_DMA_CH_CTRL_XFERCNT(n) + * - @p EFR32_DMA_CH_CTRL_DONEIEN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetMode(dmastp, (mode) | \ + EFR32_DMA_CH_CTRL_DSTMODE_ABSOLUTE | \ + EFR32_DMA_CH_CTRL_SRCMODE_ABSOLUTE | \ + EFR32_DMA_CH_CTRL_SIZE_BYTE | \ + EFR32_DMA_CH_CTRL_DSTINC_ONE | \ + EFR32_DMA_CH_CTRL_SRCINC_ONE | \ + EFR32_DMA_CH_CTRL_REQMODE_ALL | \ + EFR32_DMA_CH_CTRL_BLOCKSIZE_ALL | \ + EFR32_DMA_CH_CTRL_XFERCNT(n) | \ + EFR32_DMA_CH_CTRL_DONEIEN); \ + dmaStreamEnable(dmastp); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamFree(). + * + * @param[in] dmastp pointer to a efr32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while((LDMA->CHBUSY & (1U << (dmastp)->selfindex)) == 1U) {} \ + dmaStreamClearInterrupt(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const efr32_dma_stream_t _efr32_dma_streams[EFR32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + const efr32_dma_stream_t *dmaStreamAllocI(uint32_t id, + uint32_t priority, + efr32_dmaisr_t func, + void *param); + const efr32_dma_stream_t *dmaStreamAlloc(uint32_t id, + uint32_t priority, + efr32_dmaisr_t func, + void *param); + void dmaStreamFreeI(const efr32_dma_stream_t *dmastp); + void dmaStreamFree(const efr32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* EFR32_DMA_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/driver.mk new file mode 100644 index 0000000000..3e13365a17 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/driver.mk @@ -0,0 +1,21 @@ +ifeq ($(USE_SMART_BUILD),yes) + +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.c +endif + +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_uart_lld.c +endif + +ifneq ($(findstring HAL_USE_SIO TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.c +endif + +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_uart_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.c new file mode 100644 index 0000000000..1639f799ee --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.c @@ -0,0 +1,126 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_serial_lld.c + * @brief PLATFORM serial subsystem low level driver source. + * + * @addtogroup SERIAL + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 serial driver identifier.*/ +#if (EFR32_SERIAL_USE_USART1 == TRUE) || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + .speed = SERIAL_DEFAULT_BITRATE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if EFR32_SERIAL_USE_USART1 == TRUE + sdObjectInit(&SD1, NULL, notify1); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) { + config = &default_config; + } + + if (sdp->state == SD_STOP) { +#if EFR32_SERIAL_USE_USART1 == TRUE + if (&SD1 == sdp) { + + } +#endif + } + /* Configures the peripheral.*/ + (void)config; /* Warning suppression, remove this.*/ +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { +#if EFR32_SERIAL_USE_USART1 == TRUE + if (&SD1 == sdp) { + + } +#endif + } +} + +#endif /* HAL_USE_SERIAL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.h new file mode 100644 index 0000000000..1f665c8898 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_serial_lld.h @@ -0,0 +1,119 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_serial_lld.h + * @brief PLATFORM serial subsystem low level driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define EFR32_SERIAL_USE_USART1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PLATFORM Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct hal_serial_config { + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields.*/ +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (EFR32_SERIAL_USE_USART1 == TRUE) && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL == TRUE */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.c new file mode 100644 index 0000000000..04acb04d49 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.c @@ -0,0 +1,1223 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_sio_lld.c + * @brief PLATFORM SIO subsystem low level driver source. + * + * @addtogroup SIO + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_SIO == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of RX-related errors in the EUSART ISR register. + */ +#define EUSART_IEN_RX_ERRORS (EUSART_IEN_RXOF /* RX overrun */ | \ + EUSART_IEN_FERR /* Frame error. */ | \ + EUSART_IEN_PERR) /* Parity error. */ + +#define EUSART_IF_RX_ERRORS (EUSART_IF_RXOF /* RX overrun */ | \ + EUSART_IF_FERR /* Frame error. */ | \ + EUSART_IF_PERR) /* Parity error. */ + +#define EUSART_IF_CFG_FORBIDDEN (EUSART_IF_TXFL | \ + EUSART_IF_TXC | \ + EUSART_IF_RXFL | \ + EUSART_IF_RX_ERRORS) +/** + * @brief Mask of RX-related errors in the UART ISR register. + */ +#define USART_IEN_RX_ERRORS (USART_IEN_RXOF /* RX overrun */ | \ + USART_IEN_FERR /* Frame error. */ | \ + USART_IEN_PERR) /* Parity error. */ + +#define USART_IF_RX_ERRORS (USART_IF_RXOF /* RX overrun */ | \ + USART_IF_FERR /* Frame error. */ | \ + USART_IF_PERR) /* Parity error. */ + +#define USART_IF_CFG_FORBIDDEN (USART_IF_TXBL | \ + USART_IF_TXC | \ + USART_IF_RXFULL | \ + USART_IF_RX_ERRORS) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SIO1 driver identifier. + */ +#if (EFR32_SIO_USE_EUSART1 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD1; +#endif + +/** + * @brief SIO2 driver identifier. + */ +#if (EFR32_SIO_USE_EUSART2 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD2; +#endif + +/** + * @brief SIO3 driver identifier. + */ +#if (EFR32_SIO_USE_EUSART3 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD3; +#endif + +/** + * @brief SIO4 driver identifier. + */ +#if (EFR32_SIO_USE_USART1 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE bool _sio_lld_is_usart(SIODriver* siop) { + + if (false) { + (void)siop; + } +#if (EFR32_SIO_USE_USART1 == TRUE) + else if (siop == &SIOD4) { + return true; + } +#endif + + return false; +} + +__STATIC_INLINE uint32_t _sio_lld_get_clkdiv(uint32_t clock, uint32_t ovs, uint32_t bitrate) { + + uint32_t clkdiv; + + /* Avoid oveflow by mutliply by 32 instead of 256. */ + clkdiv = (32U * clock) / (ovs * bitrate) - 32U; + clkdiv *= 8; + + return clkdiv; +} + +__STATIC_INLINE uint32_t _sio_lld_get_ovs(uint32_t val) { + + switch (val) { + case 0b000: + return 16; + case 0b001: + return 8; + case 0b010: + return 6; + case 0b011: + return 4; + case 0b100: + return 1; + default: + break; + } + + osalDbgAssert((false), "invalid oversampling value"); + + /* Return something that _could_ work in most cases. */ + return 4; +} + +__STATIC_INLINE void _sio_lld_reg_masked_write(volatile uint32_t* address, + uint32_t mask, + uint32_t value) { + + *address = (*address & ~mask) | (value & mask); +} + +__STATIC_INLINE void _sio_lld_start_eusart(SIODriver* siop) { + + EUSART_TypeDef* usart = siop->usart; + const SIOConfig* config = siop->config; + uint32_t ovs, clkdiv; + + osalDbgAssert((siop->clock / config->baud >= 3), "invalid baudrate"); + + ovs = _sio_lld_get_ovs((config->cfg0 & _EUSART_CFG0_OVS_MASK) >> _EUSART_CFG0_OVS_SHIFT); + clkdiv = _sio_lld_get_clkdiv(siop->clock, ovs, config->baud); + + osalDbgAssert((clkdiv <= _EUSART_CLKDIV_MASK), "invalid clkdiv"); + + _sio_lld_reg_masked_write(&(usart->CFG0), _EUSART_CFG0_MASK, config->cfg0); + + _sio_lld_reg_masked_write(&(usart->FRAMECFG), _EUSART_FRAMECFG_MASK, config->framecfg); + + /* Enable module before writing into CLKDIV register. */ + usart->EN_SET = EUSART_EN_EN; + + _sio_lld_reg_masked_write(&(usart->CLKDIV), _EUSART_CLKDIV_MASK, clkdiv); + + usart->IF_CLR = usart->IF; + + usart->CMD_SET = EUSART_CMD_RXEN | EUSART_CMD_TXEN | EUSART_CMD_CLEARTX; + while ((usart->SYNCBUSY & _EUSART_SYNCBUSY_MASK) != 0U); +} + +__STATIC_INLINE void _sio_lld_stop_eusart(SIODriver* siop) { + + EUSART_TypeDef* usart = siop->usart; + + usart->CMD_CLR = EUSART_CMD_RXEN | EUSART_CMD_TXEN | EUSART_CMD_CLEARTX; + while ((usart->SYNCBUSY & _EUSART_SYNCBUSY_MASK) != 0U); + + usart->IF_CLR = usart->IF; + + usart->EN_CLR = EUSART_EN_EN; + + /* Wait until EUSART is disabled. */ + while ((usart->EN & _EUSART_EN_DISABLING_MASK) == EUSART_EN_DISABLING); +} + +__STATIC_INLINE void _sio_lld_start_usart(SIODriver* siop) { + + USART_TypeDef* usart = siop->usart; + const SIOConfig* config = siop->config; + uint32_t ovs, clkdiv; + + osalDbgAssert((siop->clock / config->baud >= 3), "invalid baudrate"); + + ovs = _sio_lld_get_ovs((config->cfg0 & _USART_CTRL_OVS_MASK) >> _USART_CTRL_OVS_SHIFT); + clkdiv = _sio_lld_get_clkdiv(siop->clock, ovs, config->baud); + + osalDbgAssert((clkdiv <= _USART_CLKDIV_MASK), "invalid clkdiv"); + + _sio_lld_reg_masked_write(&(usart->CTRL), _USART_CTRL_MASK, config->cfg0); + + _sio_lld_reg_masked_write(&(usart->FRAME), _USART_FRAME_MASK, config->framecfg); + + /* Enable module before writing into CLKDIV register. */ + usart->EN_SET = USART_EN_EN; + + _sio_lld_reg_masked_write(&(usart->CLKDIV), _USART_CLKDIV_MASK, clkdiv); + + usart->IF_CLR = usart->IF; + + usart->CMD_SET = USART_CMD_RXEN | USART_CMD_TXEN | USART_CMD_CLEARTX; +} + +__STATIC_INLINE void _sio_lld_stop_usart(SIODriver* siop) { + + USART_TypeDef* usart = siop->usart; + + usart->CMD_CLR = USART_CMD_RXEN | USART_CMD_TXEN | USART_CMD_CLEARTX; + + usart->IF_CLR = usart->IF; + + usart->EN_CLR = USART_EN_EN; +} + +__STATIC_INLINE void usart_enable_rx_irq(SIODriver* siop) { + + if ((siop->enabled & SIO_EV_RXNOTEMPY) != 0U) { + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + usart->IEN_SET = USART_IEN_RXFULL; + } else { + USART_TypeDef* usart = siop->usart; + usart->IEN_SET = EUSART_IEN_RXFL; + } + } +} + +__STATIC_INLINE void usart_enable_rx_errors_irq(SIODriver* siop) { + + uint32_t ien = 0U; + + if (_sio_lld_is_usart(siop)) { + ien |= __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, SIO_EV_FRAMING_ERR_POS, _USART_IEN_FERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, _USART_IEN_PERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, SIO_EV_OVERRUN_ERR_POS, _USART_IEN_RXOF_SHIFT); + + /* The following 3 are grouped.*/ + if ((siop->enabled & (SIO_EV_FRAMING_ERR | + SIO_EV_PARITY_ERR | + SIO_EV_OVERRUN_ERR)) != 0U) { + USART_TypeDef* usart = siop->usart; + usart->IEN_SET = ien; + } + } else { + ien |= __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, SIO_EV_FRAMING_ERR_POS, _EUSART_IEN_FERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, _EUSART_IEN_PERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, SIO_EV_OVERRUN_ERR_POS, _EUSART_IEN_RXOF_SHIFT); + + /* The following 3 are grouped.*/ + if ((siop->enabled & (SIO_EV_FRAMING_ERR | + SIO_EV_PARITY_ERR | + SIO_EV_OVERRUN_ERR)) != 0U) { + EUSART_TypeDef* usart = siop->usart; + usart->IEN_SET = ien; + } + } +} + +__STATIC_INLINE void usart_enable_tx_irq(SIODriver* siop) { + + if ((siop->enabled & SIO_EV_TXNOTFULL) != 0U) { + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + usart->IEN_SET = USART_IEN_TXBL; + } else { + EUSART_TypeDef* usart = siop->usart; + usart->IEN_SET = EUSART_IEN_TXFL; + } + } +} + +__STATIC_INLINE void usart_enable_tx_end_irq(SIODriver* siop) { + + if ((siop->enabled & SIO_EV_TXDONE) != 0U) { + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + usart->IEN_SET = USART_IEN_TXC; + } else { + EUSART_TypeDef* usart = siop->usart; + usart->IEN_SET = EUSART_IEN_TXC; + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ +#if (EFR32_SIO_USE_EUSART1 == TRUE) || defined(__DOXYGEN__) +/** + * @brief EFR32_EUSART1_RX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_EUSART1_RX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EFR32_EUSART1_TX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_EUSART1_TX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if (EFR32_SIO_USE_EUSART2 == TRUE) || defined(__DOXYGEN__) +/** + * @brief EFR32_EUSART2_RX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_EUSART2_RX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EFR32_EUSART2_TX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_EUSART2_TX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if (EFR32_SIO_USE_EUSART3 == TRUE) || defined(__DOXYGEN__) +/** + * @brief EFR32_EUSART3_RX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_EUSART3_RX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EFR32_EUSART3_TX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_EUSART3_TX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if (EFR32_SIO_USE_USART1 == TRUE) || defined(__DOXYGEN__) +/** + * @brief EFR32_USART1_RX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_USART1_RX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EFR32_USART1_TX_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_USART1_TX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SIO driver initialization. + * + * @notapi + */ +void sio_lld_init(void) { + + /* Driver initialization.*/ +#if EFR32_SIO_USE_EUSART1 == TRUE + sioObjectInit(&SIOD1); + SIOD1.usart = EUSART0; + SIOD1.clock = EFR32_EUSART1CLK; +#endif + +#if EFR32_SIO_USE_EUSART2 == TRUE + sioObjectInit(&SIOD2); + SIOD2.usart = EUSART1; + SIOD2.clock = EFR32_EUSART23CLK; +#endif + +#if EFR32_SIO_USE_EUSART3 == TRUE + sioObjectInit(&SIOD3); + SIOD3.usart = EUSART2; + SIOD3.clock = EFR32_EUSART23CLK; +#endif + +#if EFR32_SIO_USE_USART1 == TRUE + sioObjectInit(&SIOD4); + SIOD4.usart = USART0; + SIOD4.clock = EFR32_USART1CLK; +#endif +} + +/** + * @brief Configures and activates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The operation status. + * + * @notapi + */ +msg_t sio_lld_start(SIODriver* siop) { + + osalDbgAssert((siop->config != NULL), "invalid config"); + + if (siop->state == SIO_STOP) { + /* Enables the peripheral.*/ + /* Configures the peripheral.*/ +#if EFR32_SIO_USE_EUSART1 == TRUE + if (&SIOD1 == siop) { + CMU->CLKEN1_SET = CMU_CLKEN1_EUSART0; + + _sio_lld_start_eusart(siop); + + nvicEnableVector(EFR32_EUSART1_RX_NUMBER, EFR32_EUSART1_RX_IRQ_PRIORITY); + nvicEnableVector(EFR32_EUSART1_TX_NUMBER, EFR32_EUSART1_TX_IRQ_PRIORITY); + } +#endif + +#if EFR32_SIO_USE_EUSART2 == TRUE + if (&SIOD2 == siop) { + CMU->CLKEN1_SET = CMU_CLKEN1_EUSART1; + + _sio_lld_start_eusart(siop); + + nvicEnableVector(EFR32_EUSART2_RX_NUMBER, EFR32_EUSART2_RX_IRQ_PRIORITY); + nvicEnableVector(EFR32_EUSART2_TX_NUMBER, EFR32_EUSART2_TX_IRQ_PRIORITY); + } +#endif + +#if EFR32_SIO_USE_EUSART3 == TRUE + if (&SIOD3 == siop) { + CMU->CLKEN1_SET = CMU_CLKEN1_EUSART2; + + _sio_lld_start_eusart(siop); + + nvicEnableVector(EFR32_EUSART3_RX_NUMBER, EFR32_EUSART3_RX_IRQ_PRIORITY); + nvicEnableVector(EFR32_EUSART3_TX_NUMBER, EFR32_EUSART3_TX_IRQ_PRIORITY); + } +#endif + +#if EFR32_SIO_USE_USART1 == TRUE + if (&SIOD4 == siop) { + CMU->CLKEN0_SET = CMU_CLKEN0_USART0; + + _sio_lld_start_usart(siop); + + nvicEnableVector(EFR32_USART1_RX_NUMBER, EFR32_USART1_RX_IRQ_PRIORITY); + nvicEnableVector(EFR32_USART1_TX_NUMBER, EFR32_USART1_TX_IRQ_PRIORITY); + } +#endif + } + + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +void sio_lld_stop(SIODriver* siop) { + + if (siop->state == SIO_READY) { + /* Resets the peripheral.*/ + /* Disables the peripheral.*/ +#if EFR32_SIO_USE_EUSART1 == TRUE + if (&SIOD1 == siop) { + _sio_lld_stop_eusart(siop); + CMU->CLKEN1_CLR = CMU_CLKEN1_EUSART0; + } +#endif + +#if EFR32_SIO_USE_EUSART2 == TRUE + if (&SIOD2 == siop) { + _sio_lld_stop_eusart(siop); + CMU->CLKEN1_CLR = CMU_CLKEN1_EUSART1; + } +#endif + +#if EFR32_SIO_USE_EUSART3 == TRUE + if (&SIOD3 == siop) { + _sio_lld_stop_eusart(siop); + CMU->CLKEN1_CLR = CMU_CLKEN1_EUSART2; + } +#endif + +#if EFR32_SIO_USE_USART1 == TRUE + if (&SIOD4 == siop) { + _sio_lld_stop_usart(siop); + CMU->CLKEN0_CLR = CMU_CLKEN0_USART0; + } +#endif + } +} + +/** + * @brief Enable flags change notification. + * + * @param[in] siop pointer to the @p SIODriver object + */ +void sio_lld_update_enable_flags(SIODriver* siop) { + + uint32_t ien; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + ien = usart->IF & ~(USART_IF_RX_ERRORS | + USART_IF_RXFULL | + USART_IF_TXBL | + USART_IF_TXC); + + ien |= __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, SIO_EV_FRAMING_ERR_POS, _USART_IEN_FERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, _USART_IEN_PERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, SIO_EV_OVERRUN_ERR_POS, _USART_IEN_RXOF_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_RXNOTEMPY, SIO_EV_RXNOTEMPY_POS, _USART_IEN_RXFULL_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_TXNOTFULL, SIO_EV_TXNOTFULL_POS, _USART_IEN_TXBL_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_TXDONE, SIO_EV_TXDONE_POS, _USART_IEN_TXC_SHIFT); + + /* Setting up the operation.*/ + usart->IEN = ien; + } else { + EUSART_TypeDef* usart = siop->usart; + ien = usart->IF & ~(EUSART_IF_RX_ERRORS | + EUSART_IF_RXFL | + EUSART_IF_TXFL | + EUSART_IF_TXC); + + ien |= __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, SIO_EV_FRAMING_ERR_POS, _EUSART_IEN_FERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, _EUSART_IEN_PERR_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, SIO_EV_OVERRUN_ERR_POS, _EUSART_IEN_RXOF_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_RXNOTEMPY, SIO_EV_RXNOTEMPY_POS, _EUSART_IEN_RXFL_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_TXNOTFULL, SIO_EV_TXNOTFULL_POS, _EUSART_IEN_TXFL_SHIFT); + ien |= __sio_reloc_field(siop->enabled, SIO_EV_TXDONE, SIO_EV_TXDONE_POS, _EUSART_IEN_TXC_SHIFT); + + /* Setting up the operation.*/ + usart->IEN = ien; + } +} + +/** + * @brief Get and clears SIO error event flags. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The pending event flags. + * + * @notapi + */ +sioevents_t sio_lld_get_and_clear_errors(SIODriver* siop) { + + uint32_t isr; + sioevents_t errors; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + + /* Getting all error ISR flags (and only those).*/ + isr = usart->IF & (USART_IF_RX_ERRORS); + + /* Clearing captured events.*/ + usart->IF_CLR = isr; + + /* Status flags cleared, now the error-related interrupts can be + enabled again.*/ + usart_enable_rx_errors_irq(siop); + + /* Translating the status flags in SIO events.*/ + errors = __sio_reloc_field(isr, _USART_IF_FERR_MASK, _USART_IF_FERR_SHIFT, SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_PERR_MASK, _USART_IF_PERR_SHIFT, SIO_EV_PARITY_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_RXOF_MASK, _USART_IF_RXOF_SHIFT, SIO_EV_OVERRUN_ERR_POS); + } else { + EUSART_TypeDef* usart = siop->usart; + + /* Getting all error ISR flags (and only those).*/ + isr = usart->IF & (EUSART_IF_RX_ERRORS); + + /* Clearing captured events.*/ + usart->IF_CLR = isr; + + /* Status flags cleared, now the error-related interrupts can be + enabled again.*/ + usart_enable_rx_errors_irq(siop); + + /* Translating the status flags in SIO events.*/ + errors = __sio_reloc_field(isr, _EUSART_IF_FERR_MASK, _EUSART_IF_FERR_SHIFT, SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_PERR_MASK, _EUSART_IF_PERR_SHIFT, SIO_EV_PARITY_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_RXOF_MASK, _EUSART_IF_RXOF_SHIFT, SIO_EV_OVERRUN_ERR_POS); + } + + return errors; +} + +/** + * @brief Get and clears SIO event flags. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The pending event flags. + * + * @notapi + */ +sioevents_t sio_lld_get_and_clear_events(SIODriver* siop) { + + uint32_t isr, status; + sioevents_t events; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + + /* Getting all ISR flags.*/ + isr = usart->IF & (USART_IF_RX_ERRORS | + USART_IF_RXFULL | + USART_IF_TXBL | + USART_IF_TXC); + + /* Clearing captured events.*/ + usart->IF_CLR = isr; + + /* Status flags cleared, now the RX-related interrupts can be + enabled again.*/ + usart_enable_rx_irq(siop); + usart_enable_rx_errors_irq(siop); + + /* Translating the status flags in SIO events.*/ + events = __sio_reloc_field(isr, _USART_IF_FERR_MASK, _USART_IF_FERR_SHIFT, SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_PERR_MASK, _USART_IF_PERR_SHIFT, SIO_EV_PARITY_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_RXOF_MASK, _USART_IF_RXOF_SHIFT, SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_RXFULL_MASK, _USART_IF_RXFULL_SHIFT, SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(isr, _USART_IF_TXBL_MASK, _USART_IF_TXBL_SHIFT, SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(isr, _USART_IF_TXC_MASK, _USART_IF_TXC_SHIFT, SIO_EV_TXDONE_POS); + } else { + EUSART_TypeDef* usart = siop->usart; + + /* Getting all ISR flags.*/ + isr = usart->IF & (EUSART_IF_RX_ERRORS | + EUSART_IF_RXFL | + EUSART_IF_TXFL | + EUSART_IF_TXC); + + status = usart->STATUS & EUSART_STATUS_RXIDLE; + + /* Clearing captured events.*/ + usart->IF_CLR = isr; + + /* Status flags cleared, now the RX-related interrupts can be + enabled again.*/ + usart_enable_rx_irq(siop); + usart_enable_rx_errors_irq(siop); + + /* Translating the status flags in SIO events.*/ + events = __sio_reloc_field(isr, _EUSART_IF_FERR_MASK, _EUSART_IF_FERR_SHIFT, SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_PERR_MASK, _EUSART_IF_PERR_SHIFT, SIO_EV_PARITY_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_RXOF_MASK, _EUSART_IF_RXOF_SHIFT, SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_RXFL_MASK, _EUSART_IF_RXFL_SHIFT, SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(isr, _EUSART_IF_TXFL_MASK, _EUSART_IF_TXFL_SHIFT, SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(isr, _EUSART_IF_TXC_MASK, _EUSART_IF_TXC_SHIFT, SIO_EV_TXDONE_POS) | + __sio_reloc_field(status, _EUSART_STATUS_RXIDLE_MASK, _EUSART_STATUS_RXIDLE_SHIFT, SIO_EV_RXIDLE_POS); + } + + return events; +} + +/** + * @brief Returns the pending SIO event flags. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The pending event flags. + * + * @notapi + */ +sioevents_t sio_lld_get_events(SIODriver* siop) { + + uint32_t isr, status; + sioevents_t events; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + + /* Getting all ISR flags.*/ + isr = usart->IF & (USART_IF_RX_ERRORS | + USART_IF_RXFULL | + USART_IF_TXBL | + USART_IF_TXC); + + /* Translating the status flags in SIO events.*/ + events = __sio_reloc_field(isr, _USART_IF_FERR_MASK, _USART_IF_FERR_SHIFT, SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_PERR_MASK, _USART_IF_PERR_SHIFT, SIO_EV_PARITY_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_RXOF_MASK, _USART_IF_RXOF_SHIFT, SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(isr, _USART_IF_RXFULL_MASK, _USART_IF_RXFULL_SHIFT, SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(isr, _USART_IF_TXBL_MASK, _USART_IF_TXBL_SHIFT, SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(isr, _USART_IF_TXC_MASK, _USART_IF_TXC_SHIFT, SIO_EV_TXDONE_POS); + } else { + EUSART_TypeDef* usart = siop->usart; + + /* Getting all ISR flags.*/ + isr = usart->IF & (EUSART_IF_RX_ERRORS | + EUSART_IF_RXFL | + EUSART_IF_TXFL | + EUSART_IF_TXC); + + status = usart->STATUS & EUSART_STATUS_RXIDLE; + + /* Translating the status flags in SIO events.*/ + events = __sio_reloc_field(isr, _EUSART_IF_FERR_MASK, _EUSART_IF_FERR_SHIFT, SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_PERR_MASK, _EUSART_IF_PERR_SHIFT, SIO_EV_PARITY_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_RXOF_MASK, _EUSART_IF_RXOF_SHIFT, SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(isr, _EUSART_IF_RXFL_MASK, _EUSART_IF_RXFL_SHIFT, SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(isr, _EUSART_IF_TXFL_MASK, _EUSART_IF_TXFL_SHIFT, SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(isr, _EUSART_IF_TXC_MASK, _EUSART_IF_TXC_SHIFT, SIO_EV_TXDONE_POS) | + __sio_reloc_field(status, _EUSART_STATUS_RXIDLE_MASK, _EUSART_STATUS_RXIDLE_SHIFT, SIO_EV_RXIDLE_POS); + } + + return events; +} + +bool _sio_lld_is_rx_empty(SIODriver* siop) { + + bool rv; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + rv = (usart->IF & USART_IF_RXDATAV) == 0U; + } else { + EUSART_TypeDef* usart = siop->usart; + rv = (usart->IF & EUSART_IF_RXFL) == 0U; + } + + return rv; +} + +bool _sio_lld_is_rx_idle(SIODriver* siop) { + + bool rv; + + if (_sio_lld_is_usart(siop)) { + /** FIXME: There is no idle status flag? */ + //USART_TypeDef* usart = siop->usart; + rv = true; + } else { + EUSART_TypeDef* usart = siop->usart; + rv = (usart->STATUS & EUSART_STATUS_RXIDLE) != 0U; + } + + return rv; +} + +bool _sio_lld_has_rx_errors(SIODriver* siop) { + + bool rv; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + rv = (usart->IF & (USART_IF_FERR | USART_IF_PERR | USART_IF_RXOF)) != 0U; + } else { + EUSART_TypeDef* usart = siop->usart; + rv = (usart->IF & (EUSART_IF_FERR | EUSART_IF_PERR | EUSART_IF_RXOF)) != 0U; + } + + return rv; +} + +bool _sio_lld_is_tx_full(SIODriver* siop) { + + bool rv; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + rv = (usart->IF & USART_IF_TXBL) == 0U; + } else { + EUSART_TypeDef* usart = siop->usart; + rv = (usart->IF & EUSART_IF_TXFL) == 0U; + } + + return rv; +} + +bool _sio_lld_is_tx_ongoing(SIODriver* siop) { + + bool rv; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + rv = (usart->IF & USART_IF_TXC) == 0U; + } else { + EUSART_TypeDef* usart = siop->usart; + rv = (usart->IF & EUSART_IF_TXC) == 0U; + } + + return rv; +} + +__STATIC_INLINE uint_fast16_t _sio_lld_read(SIODriver* siop) { + + uint_fast16_t data; + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + data = (uint8_t)usart->RXDATA; + } else { + EUSART_TypeDef* usart = siop->usart; + data = (uint8_t)usart->RXDATA; + } + + return data; +} + +__STATIC_INLINE void _sio_lld_write(SIODriver* siop, uint_fast16_t data) { + + if (_sio_lld_is_usart(siop)) { + USART_TypeDef* usart = siop->usart; + usart->TXDATA = (uint8_t)data; + } else { + EUSART_TypeDef* usart = siop->usart; + usart->TXDATA = (uint8_t)data; + } +} + +/** + * @brief Reads data from the RX FIFO. + * @details The function is not blocking, it writes frames until there + * is space available without waiting. + * + * @param[in] siop pointer to an @p SIODriver structure + * @param[in] buffer pointer to the buffer for read frames + * @param[in] n maximum number of frames to be read + * @return The number of frames copied from the buffer. + * @retval 0 if the TX FIFO is full. + */ +size_t sio_lld_read(SIODriver* siop, uint8_t* buffer, size_t n) { + + size_t rd; + + rd = 0U; + while (true) { + + /* If the RX FIFO has been emptied then the RX FIFO and IDLE interrupts + are enabled again.*/ + if (sio_lld_is_rx_empty(siop)) { + usart_enable_rx_irq(siop); + break; + } + + /* Buffer filled condition.*/ + if (rd >= n) { + break; + } + + *buffer++ = (uint8_t)_sio_lld_read(siop); + rd++; + } + + return rd; +} + +/** + * @brief Writes data into the TX FIFO. + * @details The function is not blocking, it writes frames until there + * is space available without waiting. + * + * @param[in] siop pointer to an @p SIODriver structure + * @param[in] buffer pointer to the buffer for read frames + * @param[in] n maximum number of frames to be written + * @return The number of frames copied from the buffer. + * @retval 0 if the TX FIFO is full. + */ +size_t sio_lld_write(SIODriver* siop, const uint8_t* buffer, size_t n) { + + size_t wr; + + wr = 0U; + while (true) { + + /* If the TX FIFO has been filled then the interrupt is enabled again.*/ + if (sio_lld_is_tx_full(siop)) { + usart_enable_tx_irq(siop); + break; + } + + /* Buffer emptied condition.*/ + if (wr >= n) { + break; + } + + _sio_lld_write(siop, *buffer); + buffer++; + wr++; + } + + /* The transmit complete interrupt is always re-enabled on write.*/ + usart_enable_tx_end_irq(siop); + + return wr; +} + +/** + * @brief Returns one frame from the RX FIFO. + * @note If the FIFO is empty then the returned value is MSG_TIMEOUT. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The frame from RX FIFO. + * + * @notapi + */ +msg_t sio_lld_get(SIODriver* siop) { + + msg_t msg; + + /* If the RX FIFO has been emptied then the interrupt is enabled again.*/ + if (sio_lld_is_rx_empty(siop)) { + usart_enable_rx_irq(siop); + msg = MSG_TIMEOUT; + } else { + msg = (msg_t)_sio_lld_read(siop); + } + + return msg; +} + +/** + * @brief Pushes one frame into the TX FIFO. + * @note If the FIFO is full then the behavior is unpredictable. + * + * @param[in] siop pointer to the @p SIODriver object + * @param[in] data frame to be written + * + * @notapi + */ +void sio_lld_put(SIODriver* siop, uint_fast16_t data) { + + _sio_lld_write(siop, data); + + /* If the TX FIFO has been filled then the interrupt is enabled again.*/ + if (sio_lld_is_tx_full(siop)) { + usart_enable_tx_irq(siop); + } + + /* The transmit complete interrupt is always re-enabled on write.*/ + usart_enable_tx_end_irq(siop); +} + +/** + * @brief Control operation on a serial port. + * + * @param[in] siop pointer to the @p SIODriver object + * @param[in] operation control operation code + * @param[in,out] arg operation argument + * + * @return The control operation status. + * @retval MSG_OK in case of success. + * @retval MSG_TIMEOUT in case of operation timeout. + * @retval MSG_RESET in case of operation reset. + * + * @notapi + */ +msg_t sio_lld_control(SIODriver* siop, unsigned int operation, void* arg) { + + (void)siop; + (void)operation; + (void)arg; + + return MSG_OK; +} + +/** + * @brief Serves an EUSART interrupt. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +__STATIC_INLINE void sio_lld_serve_interrupt_eusart(SIODriver* siop) { + + sioevents_t events; + + EUSART_TypeDef* u = siop->usart; + uint32_t ien = u->IEN; + uint32_t ifr = u->IF; + + osalDbgAssert(siop->state == SIO_READY, "invalid state"); + + /* Events to be processed.*/ + events = sio_lld_get_events(siop) & siop->enabled; + if (events != 0U) { + + /* Error events handled as a group.*/ + if ((events & SIO_EV_ALL_ERRORS) != 0U) { + + ifr &= ~(EUSART_IF_RXFL | EUSART_IF_RX_ERRORS); + + /* All RX-related interrupt sources disabled.*/ + ien &= ~(EUSART_IEN_RXFL | EUSART_IEN_RX_ERRORS); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_errors(siop); + } + /* If there are no errors then we check for the other RX events.*/ + else { + /* Idle RX event.*/ + if ((events & SIO_EV_RXIDLE) != 0U) { + + /* There is no interrupt source to disable.*/ + + /* Waiting thread woken, if any.*/ + __sio_wakeup_rxidle(siop); + } + + /* RX FIFO is non-empty.*/ + if ((events & SIO_EV_RXNOTEMPY) != 0U) { + + ifr &= ~(EUSART_IF_RXFL); + + /* Interrupt source disabled.*/ + ien &= ~(EUSART_IEN_RXFL); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_rx(siop); + } + } + + /* TX FIFO is non-full.*/ + if ((events & SIO_EV_TXNOTFULL) != 0U) { + + /* Interrupt source disabled.*/ + ien &= ~(EUSART_IEN_TXFL); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_tx(siop); + } + + /* Physical transmission end.*/ + if ((events & SIO_EV_TXDONE) != 0U) { + + ifr &= ~(EUSART_IF_TXC); + + /* Interrupt source disabled.*/ + ien &= ~(EUSART_IEN_TXC); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_txend(siop); + } + + /* Updating control registers, some sources could have been disabled.*/ + u->IEN = ien; + + u->IF = ifr; + + /* The callback is invoked.*/ + __sio_callback(siop); + } else { + osalDbgAssert(false, "spurious interrupt"); + } +} + +/** + * @brief Serves an USART interrupt. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +__STATIC_INLINE void sio_lld_serve_interrupt_usart(SIODriver* siop) { + + sioevents_t events; + + USART_TypeDef* u = siop->usart; + uint32_t ien = u->IEN; + uint32_t ifr = u->IF; + + osalDbgAssert(siop->state == SIO_READY, "invalid state"); + + /* Events to be processed.*/ + events = sio_lld_get_events(siop) & siop->enabled; + if (events != 0U) { + + /* Error events handled as a group.*/ + if ((events & SIO_EV_ALL_ERRORS) != 0U) { + + ifr &= ~(USART_IF_RXFULL | USART_IF_RX_ERRORS); + + /* All RX-related interrupt sources disabled.*/ + ien &= ~(USART_IEN_RXFULL | USART_IEN_RX_ERRORS); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_errors(siop); + } + /* If there are no errors then we check for the other RX events.*/ + else { + /* Idle RX event.*/ + if ((events & SIO_EV_RXIDLE) != 0U) { + + /* There is no interrupt source to disable.*/ + + /* Waiting thread woken, if any.*/ + __sio_wakeup_rxidle(siop); + } + + /* RX FIFO is non-empty.*/ + if ((events & SIO_EV_RXNOTEMPY) != 0U) { + + ifr &= ~(USART_IF_RXFULL); + + /* Interrupt source disabled.*/ + ien &= ~(USART_IEN_RXFULL); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_rx(siop); + } + } + + /* TX FIFO is non-full.*/ + if ((events & SIO_EV_TXNOTFULL) != 0U) { + + /* Interrupt source disabled.*/ + ien &= ~(USART_IEN_TXBL); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_tx(siop); + } + + /* Physical transmission end.*/ + if ((events & SIO_EV_TXDONE) != 0U) { + + ifr &= ~(USART_IF_TXC); + + /* Interrupt source disabled.*/ + ien &= ~(USART_IEN_TXC); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_txend(siop); + } + + /* Updating control registers, some sources could have been disabled.*/ + u->IEN = ien; + + u->IF = ifr; + + /* The callback is invoked.*/ + __sio_callback(siop); + } else { + osalDbgAssert(false, "spurious interrupt"); + } +} + +/** + * @brief Serves an EUSART or USART interrupt. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +void sio_lld_serve_interrupt(SIODriver* siop) { + + if (_sio_lld_is_usart(siop)) { + sio_lld_serve_interrupt_usart(siop); + } else { + sio_lld_serve_interrupt_eusart(siop); + } +} + +#endif /* HAL_USE_SIO == TRUE */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.h new file mode 100644 index 0000000000..467839daa5 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/EUSARTv1/hal_sio_lld.h @@ -0,0 +1,305 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_sio_lld.h + * @brief PLATFORM SIO subsystem low level driver header. + * + * @addtogroup SIO + * @{ + */ + +#ifndef HAL_SIO_LLD_H +#define HAL_SIO_LLD_H + +#if (HAL_USE_SIO == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define EFR32_SIO_LLD_USART_DATABITS_FOUR (1U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_FIVE (2U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_SIX (3U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_SEVEN (4U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_EIGHT (5U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_NINE (6U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_TEN (7U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_ELEVEN (8U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_TWELVE (9U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_THIRTEEN (10U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_FOURTEEN (11U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_FIFTEEN (12U << 0) +#define EFR32_SIO_LLD_USART_DATABITS_SIXTEEN (13U << 0) + +#define EFR32_SIO_LLD_USART_PARITY_NONE (0U << 10) +#define EFR32_SIO_LLD_USART_PARITY_EVEN (2U << 10) +#define EFR32_SIO_LLD_USART_PARITY_ODD (3U << 10) + +#define EFR32_SIO_LLD_USART_STOPBITS_HALF (0U << 12) +#define EFR32_SIO_LLD_USART_STOPBITS_ONE (1U << 12) +#define EFR32_SIO_LLD_USART_STOPBITS_ONEANDHALF (2U << 12) +#define EFR32_SIO_LLD_USART_STOPBITS_TWO (3U << 12) + +#define EFR32_SIO_LLD_USART_8N1 (EFR32_SIO_LLD_USART_STOPBITS_ONE |\ + EFR32_SIO_LLD_USART_PARITY_NONE |\ + EFR32_SIO_LLD_USART_DATABITS_EIGHT) + +#define EFR32_SIO_LLD_USART_8E1 (EFR32_SIO_LLD_USART_STOPBITS_ONE |\ + EFR32_SIO_LLD_USART_PARITY_EVEN |\ + EFR32_SIO_LLD_USART_DATABITS_EIGHT) + +#define EFR32_SIO_LLD_USART_8O1 (EFR32_SIO_LLD_USART_STOPBITS_ONE |\ + EFR32_SIO_LLD_USART_PARITY_ODD |\ + EFR32_SIO_LLD_USART_DATABITS_EIGHT) + +#define EFR32_SIO_LLD_EUSART_DATABITS_SEVEN (1U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_EIGHT (2U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_NINE (3U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_TEN (4U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_ELEVEN (5U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITT_TWELVE (6U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_THIRTEEN (7U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_FOURTEEN (8U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_FIFTEEN (9U << 0) +#define EFR32_SIO_LLD_EUSART_DATABITS_SIXTEEN (10U << 0) + +#define EFR32_SIO_LLD_EUSART_PARITY_NONE (0U << 10) +#define EFR32_SIO_LLD_EUSART_PARITY_EVEN (2U << 10) +#define EFR32_SIO_LLD_EUSART_PARITY_ODD (3U << 10) + +#define EFR32_SIO_LLD_EUSART_STOPBITS_HALF (0U << 12) +#define EFR32_SIO_LLD_EUSART_STOPBITS_ONE (1U << 12) +#define EFR32_SIO_LLD_EUSART_STOPBITS_ONEANDHALF (2U << 12) +#define EFR32_SIO_LLD_EUSART_STOPBITS_TWO (3U << 12) + +#define EFR32_SIO_LLD_EUSART_8N1 (EFR32_SIO_LLD_EUSART_STOPBITS_ONE |\ + EFR32_SIO_LLD_EUSART_PARITY_NONE |\ + EFR32_SIO_LLD_EUSART_DATABITS_EIGHT) + +#define EFR32_SIO_LLD_EUSART_8E1 (EFR32_SIO_LLD_EUSART_STOPBITS_ONE |\ + EFR32_SIO_LLD_EUSART_PARITY_EVEN |\ + EFR32_SIO_LLD_EUSART_DATABITS_EIGHT) + +#define EFR32_SIO_LLD_EUSART_8O1 (EFR32_SIO_LLD_EUSART_STOPBITS_ONE |\ + EFR32_SIO_LLD_EUSART_PARITY_ODD |\ + EFR32_SIO_LLD_EUSART_DATABITS_EIGHT) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief SIO driver enable switch. + * @details If set to @p TRUE the support for SIO1 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_SIO_USE_EUSART1) || defined(__DOXYGEN__) +#define EFR32_SIO_USE_EUSART1 FALSE +#endif + +/** + * @brief SIO driver enable switch. + * @details If set to @p TRUE the support for SIO2 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_SIO_USE_EUSART2) || defined(__DOXYGEN__) +#define EFR32_SIO_USE_EUSART2 FALSE +#endif + +/** + * @brief SIO driver enable switch. + * @details If set to @p TRUE the support for SIO3 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_SIO_USE_EUSART3) || defined(__DOXYGEN__) +#define EFR32_SIO_USE_EUSART3 FALSE +#endif +/** @} */ + +/** + * @brief SIO driver enable switch. + * @details If set to @p TRUE the support for SIO4 is included. + * @note The default is @p FALSE. + */ +#if !defined(EFR32_SIO_USE_USART1) || defined(__DOXYGEN__) +#define EFR32_SIO_USE_USART1 FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if EFR32_SIO_USE_EUSART1 && !EFR32_HAS_EUSART1 +#error "EUSART1 not present in the selected device" +#endif + +#if EFR32_SIO_USE_EUSART2 && !EFR32_HAS_EUSART2 +#error "EUSART2 not present in the selected device" +#endif + +#if EFR32_SIO_USE_EUSART3 && !EFR32_HAS_EUSART3 +#error "EUSART3 not present in the selected device" +#endif + +#if EFR32_SIO_USE_USART1 && !EFR32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the SIO driver structure. + */ +#define sio_lld_driver_fields \ + /* Pointer to the EUSARTx or USARTx registers block.*/ \ + void *usart; \ +/* Clock frequency for the associated USART/UART.*/ \ + uint32_t clock + +/** + * @brief Low level fields of the SIO configuration structure. + */ +#define sio_lld_config_fields \ + uint32_t baud; /**< Desired baud rate. */ \ + uint32_t cfg0; /**< EUSART_CFG _or_ USART_CTRL. */ \ + uint32_t framecfg /**< EUSART_FRAMECFG _or_ USART_FRAME. */ + +/** + * @brief Determines the state of the RX FIFO. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The RX FIFO state. + * @retval false if RX FIFO is not empty + * @retval true if RX FIFO is empty + * + * @notapi + */ +#define sio_lld_is_rx_empty(siop) _sio_lld_is_rx_empty(siop) + +/** + * @brief Determines the activity state of the receiver. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The RX activity state. + * @retval false if RX is in active state. + * @retval true if RX is in idle state. + * + * @notapi + */ +#define sio_lld_is_rx_idle(siop) _sio_lld_is_rx_idle(siop) + +/** + * @brief Determines if RX has pending error events to be read and cleared. + * @note Only error and protocol errors are handled, data events are not + * considered. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The RX error events. + * @retval false if RX has no pending events + * @retval true if RX has pending events + * + * @notapi + */ +#define sio_lld_has_rx_errors(siop) _sio_lld_has_rx_errors(siop) + +/** + * @brief Determines the state of the TX FIFO. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The TX FIFO state. + * @retval false if TX FIFO is not full + * @retval true if TX FIFO is full + * + * @notapi + */ +#define sio_lld_is_tx_full(siop) _sio_lld_is_tx_full(siop) + +/** + * @brief Determines the transmission state. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The TX FIFO state. + * @retval false if transmission is idle + * @retval true if transmission is ongoing + * + * @notapi + */ +#define sio_lld_is_tx_ongoing(siop) _sio_lld_is_tx_ongoing(siop) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (EFR32_SIO_USE_EUSART1 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD1; +#endif + +#if (EFR32_SIO_USE_EUSART2 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD2; +#endif + +#if (EFR32_SIO_USE_EUSART3 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD3; +#endif + +#if (EFR32_SIO_USE_USART1 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD4; +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif +void sio_lld_init(void); +msg_t sio_lld_start(SIODriver* siop); +void sio_lld_stop(SIODriver* siop); +void sio_lld_update_enable_flags(SIODriver* siop); +sioevents_t sio_lld_get_and_clear_errors(SIODriver* siop); +sioevents_t sio_lld_get_and_clear_events(SIODriver* siop); +sioevents_t sio_lld_get_events(SIODriver* siop); +size_t sio_lld_read(SIODriver* siop, uint8_t* buffer, size_t n); +size_t sio_lld_write(SIODriver* siop, const uint8_t* buffer, size_t n); +msg_t sio_lld_get(SIODriver* siop); +void sio_lld_put(SIODriver* siop, uint_fast16_t data); +msg_t sio_lld_control(SIODriver* siop, unsigned int operation, void* arg); +void sio_lld_serve_interrupt(SIODriver* siop); + +bool _sio_lld_is_rx_empty(SIODriver* siop); +bool _sio_lld_is_rx_idle(SIODriver* siop); +bool _sio_lld_has_rx_errors(SIODriver* siop); +bool _sio_lld_is_tx_full(SIODriver* siop); +bool _sio_lld_is_tx_ongoing(SIODriver* siop); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SIO == TRUE */ + +#endif /* HAL_SIO_LLD_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/driver.mk new file mode 100644 index 0000000000..f611bdb633 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/driver.mk @@ -0,0 +1,11 @@ +ifeq ($(USE_SMART_BUILD),yes) + +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.c +endif + +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.c new file mode 100644 index 0000000000..47ad62a86d --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.c @@ -0,0 +1,605 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pal_lld.c + * @brief PLATFORM PAL subsystem low level driver source. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Event records for the PAL_EVENTS_SIZE GPIO odd and even channels. + */ +palevent_t _pal_events[PAL_EVENTS_SIZE]; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void _pal_lld_reg_masked_write(volatile uint32_t* address, + uint32_t mask, + uint32_t value) { + + *address = (*address & ~mask) | (value & mask); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (PAL_USE_WAIT || PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +/** + * @brief EFR32_GPIO_ODD_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_GPIO_ODD_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + /* Get and clear pending GPIO interrupts. */ + uint32_t flags = GPIO->IF; + _pal_lld_reg_masked_write(&(GPIO->IF_CLR), 0xAAAUL, flags); + + for (uint32_t pad = 1U; pad < PAL_EVENTS_SIZE; pad += 2U) { + if ((flags & (1U << pad)) != 0U) { + _pal_isr_code(pad); + } + } + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EFR32_GPIO_ODD_HANDLER interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(EFR32_GPIO_EVEN_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + /* Get and clear pending GPIO interrupts. */ + uint32_t flags = GPIO->IF; + _pal_lld_reg_masked_write(&(GPIO->IF_CLR), 0x555UL, flags); + + for (uint32_t pad = 0U; pad < PAL_EVENTS_SIZE; pad += 2U) { + if ((flags & (1U << pad)) != 0U) { + _pal_isr_code(pad); + } + } + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief I/O ports configuration. + * + * @notapi + */ +void _pal_lld_init(const PALConfig* config) { + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + int i; + + for (i = 0; i < 16; i++) { + _pal_init_event(i); + } +#endif + + /* + * Enables the GPIO related clocks. + */ + CMU->CLKEN0_SET = CMU_CLKEN0_GPIO; + + /* + * Initial GPIO setup. + */ + GPIO_PORT(GPIOA)->CTRL = config->PAData.ctrlr; + GPIO_PORT(GPIOA)->MODEL = config->PAData.modelr; + GPIO_PORT(GPIOA)->MODEH = config->PAData.modehr; + GPIO_PORT(GPIOA)->DOUT = config->PAData.doutr; + + GPIO_PORT(GPIOB)->CTRL = config->PBData.ctrlr; + GPIO_PORT(GPIOB)->MODEL = config->PBData.modelr; + GPIO_PORT(GPIOB)->MODEH = config->PBData.modehr; + GPIO_PORT(GPIOB)->DOUT = config->PBData.doutr; + + GPIO_PORT(GPIOC)->CTRL = config->PCData.ctrlr; + GPIO_PORT(GPIOC)->MODEL = config->PCData.modelr; + GPIO_PORT(GPIOC)->MODEH = config->PCData.modehr; + GPIO_PORT(GPIOC)->DOUT = config->PCData.doutr; + + GPIO_PORT(GPIOD)->CTRL = config->PDData.ctrlr; + GPIO_PORT(GPIOD)->MODEL = config->PDData.modelr; + GPIO_PORT(GPIOD)->MODEH = config->PDData.modehr; + GPIO_PORT(GPIOD)->DOUT = config->PDData.doutr; + +#if (PAL_USE_WAIT || PAL_USE_CALLBACKS) || defined(__DOXYGEN__) + nvicEnableVector(EFR32_GPIO_ODD_NUMBER, EFR32_GPIO_ODD_IRQ_PRIORITY); + nvicEnableVector(EFR32_GPIO_EVEN_NUMBER, EFR32_GPIO_EVEN_IRQ_PRIORITY); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + uint32_t pad = 0; + + osalDbgCheck(mask <= PAL_WHOLE_PORT); + + while (mask) { + if ((mask & 1) != 0) { + _pal_lld_setpadmode(port, pad, mode); + _pal_lld_setalternatefunction(port, pad, mode); + } + + mask >>= 1; + pad++; + } +} + +void _pal_lld_setalternatefunction(ioportid_t port, + iopadid_t pad, + iomode_t mode) { + + uint32_t altfunc = (mode & PAL_EFR32_ALTERNATE_FUNCSEL_MASK); + + switch (altfunc) { + case PAL_EFR32_ALTERNATE_FUNCSEL_NONE: + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_RX_DIS: + GPIO->EUSARTROUTE[0].ROUTEEN &= ~GPIO_EUSART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_TX_DIS: + GPIO->EUSARTROUTE[0].ROUTEEN &= ~GPIO_EUSART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_RX: + GPIO->EUSARTROUTE[0].RXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_EUSART_RXROUTE_PORT_SHIFT) | + (pad << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[0].ROUTEEN |= GPIO_EUSART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_TX: + GPIO->EUSARTROUTE[0].TXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_EUSART_TXROUTE_PORT_SHIFT) | + (pad << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[0].ROUTEEN |= GPIO_EUSART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_RX_DIS: + GPIO->EUSARTROUTE[1].ROUTEEN &= ~GPIO_EUSART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_TX_DIS: + GPIO->EUSARTROUTE[1].ROUTEEN &= ~GPIO_EUSART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_RX: + GPIO->EUSARTROUTE[1].RXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_EUSART_RXROUTE_PORT_SHIFT) | + (pad << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[1].ROUTEEN |= GPIO_EUSART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_TX: + GPIO->EUSARTROUTE[1].TXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_EUSART_TXROUTE_PORT_SHIFT) | + (pad << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[1].ROUTEEN |= GPIO_EUSART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_RX_DIS: + GPIO->EUSARTROUTE[2].ROUTEEN &= ~GPIO_EUSART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_TX_DIS: + GPIO->EUSARTROUTE[2].ROUTEEN &= ~GPIO_EUSART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_RX: + GPIO->EUSARTROUTE[2].RXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_EUSART_RXROUTE_PORT_SHIFT) | + (pad << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[2].ROUTEEN |= GPIO_EUSART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_TX: + GPIO->EUSARTROUTE[2].TXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_EUSART_TXROUTE_PORT_SHIFT) | + (pad << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[2].ROUTEEN |= GPIO_EUSART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_USART0_RX_DIS: + GPIO->USARTROUTE[0].ROUTEEN &= ~GPIO_USART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_USART0_TX_DIS: + GPIO->USARTROUTE[0].ROUTEEN &= ~GPIO_USART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_USART0_RX: + GPIO->USARTROUTE[0].RXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_USART_RXROUTE_PORT_SHIFT) | + (pad << _GPIO_USART_RXROUTE_PIN_SHIFT); + GPIO->USARTROUTE[0].ROUTEEN |= GPIO_USART_ROUTEEN_RXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_USART0_TX: + GPIO->USARTROUTE[0].TXROUTE = (GPIO_PORT_INDEX(port) << _GPIO_USART_TXROUTE_PORT_SHIFT) | + (pad << _GPIO_USART_TXROUTE_PIN_SHIFT); + GPIO->USARTROUTE[0].ROUTEEN |= GPIO_USART_ROUTEEN_TXPEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_NOCLOCK: + GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_FSRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HFXO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HFRCODPLL: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HFRCOEM23: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_LFXO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_LFRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_ULFRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HCLK: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN; + GPIO->CMUROUTE.CLKOUT0ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_NOCLOCK: + GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_FSRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HFXO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HFRCODPLL: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HFRCOEM23: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_LFXO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_LFRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_ULFRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HCLK: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOC) || (GPIO_PORT_INDEX(port) == GPIOD)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT1PEN; + GPIO->CMUROUTE.CLKOUT1ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_NOCLOCK: + GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_FSRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HFXO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HFRCODPLL: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HFRCOEM23: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_LFXO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_LFRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_ULFRCO: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + case PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HCLK: + osalDbgCheck((GPIO_PORT_INDEX(port) == GPIOA) || (GPIO_PORT_INDEX(port) == GPIOB)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK) | CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK; + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT2PEN; + GPIO->CMUROUTE.CLKOUT2ROUTE = (GPIO_PORT_INDEX(port) << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) | + (pad << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + break; + + default: + osalDbgAssert(false, "unimplemented alternate function"); + break; + } +} + +void _pal_lld_setpadmode(ioportid_t port, + iopadid_t pad, + iomode_t mode) { + + uint32_t moder = (mode & PAL_EFR32_MODE_MASK) >> PAL_EFR32_MODE_SHIFT; + uint32_t doutr = (mode & PAL_EFR32_DOUT_MASK) >> PAL_EFR32_DOUT_SHIFT; + + if (pad < 8) { + _pal_lld_reg_masked_write(&(GPIO_PORT(port)->MODEL), 0xFu << ((pad - 0) * 4), moder << ((pad - 0) * 4)); + } else { + _pal_lld_reg_masked_write(&(GPIO_PORT(port)->MODEH), 0xFu << ((pad - 8) * 4), moder << ((pad - 8) * 4)); + } + + pal_lld_writepad(port, pad, (doutr != 0) ? PAL_HIGH : PAL_LOW); +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) { + + uint32_t int_no = pad; + uint32_t rising_edge, falling_edge; + + osalDbgCheck(pad < GPIO_PORT_SIZE(port)); + + switch (mode & PAL_EVENT_MODE_EDGES_MASK) { + default: + case PAL_EVENT_MODE_DISABLED: + rising_edge = 0U; + falling_edge = 0U; + break; + case PAL_EVENT_MODE_RISING_EDGE: + rising_edge = 1U; + falling_edge = 0U; + break; + case PAL_EVENT_MODE_FALLING_EDGE: + rising_edge = 0U; + falling_edge = 1U; + break; + case PAL_EVENT_MODE_BOTH_EDGES: + rising_edge = 1U; + falling_edge = 1U; + break; + } + + if (int_no < 8) { + /* The EXTIPSELL register controls pins 0-7. */ + _pal_lld_reg_masked_write(&GPIO->EXTIPSELL, 0b11UL << (4U * int_no), GPIO_PORT_INDEX(port) << (4U * int_no)); + /* The EXTIPINSELL register controls interrupt 0-7. */ + _pal_lld_reg_masked_write(&GPIO->EXTIPINSELL, 0b11UL << (4U * int_no), (uint32_t)((pad % 4) & 0b11UL) << (4U * int_no)); + } else { + uint32_t tmp = int_no - 8; + /* EXTIPSELH controls pins 8-15 of the interrupt configuration. */ + _pal_lld_reg_masked_write(&GPIO->EXTIPSELH, 0b11UL << (4U * tmp), GPIO_PORT_INDEX(port) << (4U * tmp)); + /* EXTIPINSELH controls interrupt 8-15 of the interrupt/pin number mapping. */ + _pal_lld_reg_masked_write(&GPIO->EXTIPINSELH, 0b11UL << (4U * tmp), (uint32_t)((pad % 4) & 0b11UL) << (4U * tmp)); + } + + /* Enable/disable the rising edge interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->EXTIRISE), (1U << int_no), (rising_edge << int_no)); + + /* Enable/disable the falling edge interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->EXTIFALL), (1U << int_no), (falling_edge << int_no)); + + /* Clear any pending interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->IF_CLR), (1U << int_no), (1U << int_no)); + + /* Finally enable/disable interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->IEN), (1U << int_no), (1U << int_no)); +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { + + (void)port; + + uint32_t int_no = pad; + + /* Disable the rising edge interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->EXTIRISE), (1U << int_no), (0U << int_no)); + + /* Disable the falling edge interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->EXTIFALL), (1U << int_no), (0U << int_no)); + + /* Finally disable interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->IEN), (1U << int_no), (0U << int_no)); + + /* Clear any pending interrupt. */ + _pal_lld_reg_masked_write(&(GPIO->IF_CLR), (1U << int_no), (1U << int_no)); +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ + +#endif /* HAL_USE_PAL == TRUE */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.h new file mode 100644 index 0000000000..be7a215836 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/GPIOv1/hal_pal_lld.h @@ -0,0 +1,770 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv1/hal_pal_lld.h + * @brief EFR32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/** + * @name EFR32-specific I/O mode flags + * @{ + */ +#define PAL_EFR32_CTRL_SLEWRATE_DEFAULT GPIO_P_CTRL_SLEWRATE_DEFAULT +#define PAL_EFR32_CTRL_DINDIS_DEFAULT GPIO_P_CTRL_DINDIS_DEFAULT +#define PAL_EFR32_CTRL_SLEWRATEALT_DEFAULT GPIO_P_CTRL_SLEWRATEALT_DEFAULT +#define PAL_EFR32_CTRL_DINDISALT_DEFAULT GPIO_P_CTRL_DINDISALT_DEFAULT + + +#define PAL_EFR32_PORTA_CTRL_DEFAULT (PAL_EFR32_CTRL_SLEWRATE_DEFAULT | \ + PAL_EFR32_CTRL_DINDIS_DEFAULT | \ + PAL_EFR32_CTRL_SLEWRATEALT_DEFAULT | \ + PAL_EFR32_CTRL_DINDISALT_DEFAULT) + +#define PAL_EFR32_PORTB_CTRL_DEFAULT (PAL_EFR32_CTRL_SLEWRATE_DEFAULT | \ + PAL_EFR32_CTRL_DINDIS_DEFAULT | \ + PAL_EFR32_CTRL_SLEWRATEALT_DEFAULT | \ + PAL_EFR32_CTRL_DINDISALT_DEFAULT) + +#define PAL_EFR32_PORTC_CTRL_DEFAULT (PAL_EFR32_CTRL_SLEWRATE_DEFAULT | \ + PAL_EFR32_CTRL_DINDIS_DEFAULT | \ + PAL_EFR32_CTRL_SLEWRATEALT_DEFAULT | \ + PAL_EFR32_CTRL_DINDISALT_DEFAULT) + +#define PAL_EFR32_PORTD_CTRL_DEFAULT (PAL_EFR32_CTRL_SLEWRATE_DEFAULT | \ + PAL_EFR32_CTRL_DINDIS_DEFAULT | \ + PAL_EFR32_CTRL_SLEWRATEALT_DEFAULT | \ + PAL_EFR32_CTRL_DINDISALT_DEFAULT) + + +#define PAL_EFR32_MODEL_DEFAULT GPIO_P_MODEL_MODE0_DEFAULT +#define PAL_EFR32_MODEL_DISABLED GPIO_P_MODEL_MODE0_DISABLED +#define PAL_EFR32_MODEL_INPUT GPIO_P_MODEL_MODE0_INPUT +#define PAL_EFR32_MODEL_INPUTPULL GPIO_P_MODEL_MODE0_INPUTPULL +#define PAL_EFR32_MODEL_INPUTPULLFILTER GPIO_P_MODEL_MODE0_INPUTPULLFILTER +#define PAL_EFR32_MODEL_PUSHPULL GPIO_P_MODEL_MODE0_PUSHPULL +#define PAL_EFR32_MODEL_PUSHPULLALT GPIO_P_MODEL_MODE0_PUSHPULLALT +#define PAL_EFR32_MODEL_WIREDOR GPIO_P_MODEL_MODE0_WIREDOR +#define PAL_EFR32_MODEL_WIREDORPULLDOWN GPIO_P_MODEL_MODE0_WIREDORPULLDOWN +#define PAL_EFR32_MODEL_WIREDAND GPIO_P_MODEL_MODE0_WIREDAND +#define PAL_EFR32_MODEL_WIREDANDFILTER GPIO_P_MODEL_MODE0_WIREDANDFILTER +#define PAL_EFR32_MODEL_WIREDANDPULLUP GPIO_P_MODEL_MODE0_WIREDANDPULLUP +#define PAL_EFR32_MODEL_WIREDANDPULLUPFILTER GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER +#define PAL_EFR32_MODEL_WIREDANDALT GPIO_P_MODEL_MODE0_WIREDANDALT +#define PAL_EFR32_MODEL_WIREDANDALTFILTER GPIO_P_MODEL_MODE0_WIREDANDALTFILTER +#define PAL_EFR32_MODEL_WIREDANDALTPULLUP GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP +#define PAL_EFR32_MODEL_WIREDANDALTPULLUPFILTER GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER + + +#define PAL_EFR32_PORTA_MODEL_DEFAULT ((PAL_EFR32_MODEL_DEFAULT << 0U) | \ + (PAL_EFR32_MODEL_DEFAULT << 4U) | \ + (PAL_EFR32_MODEL_DEFAULT << 8U) | \ + (PAL_EFR32_MODEL_DEFAULT << 12U) | \ + (PAL_EFR32_MODEL_DEFAULT << 16U) | \ + (PAL_EFR32_MODEL_DEFAULT << 20U) | \ + (PAL_EFR32_MODEL_DEFAULT << 24U) | \ + (PAL_EFR32_MODEL_DEFAULT << 28U)) + +#define PAL_EFR32_PORTB_MODEL_DEFAULT ((PAL_EFR32_MODEL_DEFAULT << 0U) | \ + (PAL_EFR32_MODEL_DEFAULT << 4U) | \ + (PAL_EFR32_MODEL_DEFAULT << 8U) | \ + (PAL_EFR32_MODEL_DEFAULT << 12U) | \ + (PAL_EFR32_MODEL_DEFAULT << 16U) | \ + (PAL_EFR32_MODEL_DEFAULT << 20U) | \ + (PAL_EFR32_MODEL_DEFAULT << 24U) | \ + (PAL_EFR32_MODEL_DEFAULT << 28U)) + +#define PAL_EFR32_PORTC_MODEL_DEFAULT ((PAL_EFR32_MODEL_DEFAULT << 0U) | \ + (PAL_EFR32_MODEL_DEFAULT << 4U) | \ + (PAL_EFR32_MODEL_DEFAULT << 8U) | \ + (PAL_EFR32_MODEL_DEFAULT << 12U) | \ + (PAL_EFR32_MODEL_DEFAULT << 16U) | \ + (PAL_EFR32_MODEL_DEFAULT << 20U) | \ + (PAL_EFR32_MODEL_DEFAULT << 24U) | \ + (PAL_EFR32_MODEL_DEFAULT << 28U)) + +#define PAL_EFR32_PORTD_MODEL_DEFAULT ((PAL_EFR32_MODEL_DEFAULT << 0U) | \ + (PAL_EFR32_MODEL_DEFAULT << 4U) | \ + (PAL_EFR32_MODEL_DEFAULT << 8U) | \ + (PAL_EFR32_MODEL_DEFAULT << 12U) | \ + (PAL_EFR32_MODEL_DEFAULT << 16U) | \ + (PAL_EFR32_MODEL_DEFAULT << 20U) | \ + (PAL_EFR32_MODEL_DEFAULT << 24U) | \ + (PAL_EFR32_MODEL_DEFAULT << 28U)) + + +#define PAL_EFR32_MODEH_DEFAULT GPIO_P_MODEH_MODE0_DEFAULT +#define PAL_EFR32_MODEH_DISABLED GPIO_P_MODEH_MODE0_DISABLED +#define PAL_EFR32_MODEH_INPUT GPIO_P_MODEH_MODE0_INPUT +#define PAL_EFR32_MODEH_INPUTPULL GPIO_P_MODEH_MODE0_INPUTPULL +#define PAL_EFR32_MODEH_INPUTPULLFILTER GPIO_P_MODEH_MODE0_INPUTPULLFILTER +#define PAL_EFR32_MODEH_PUSHPULL GPIO_P_MODEH_MODE0_PUSHPULL +#define PAL_EFR32_MODEH_PUSHPULLALT GPIO_P_MODEH_MODE0_PUSHPULLALT +#define PAL_EFR32_MODEH_WIREDOR GPIO_P_MODEH_MODE0_WIREDOR +#define PAL_EFR32_MODEH_WIREDORPULLDOWN GPIO_P_MODEH_MODE0_WIREDORPULLDOWN +#define PAL_EFR32_MODEH_WIREDAND GPIO_P_MODEH_MODE0_WIREDAND +#define PAL_EFR32_MODEH_WIREDANDFILTER GPIO_P_MODEH_MODE0_WIREDANDFILTER +#define PAL_EFR32_MODEH_WIREDANDPULLUP GPIO_P_MODEH_MODE0_WIREDANDPULLUP +#define PAL_EFR32_MODEH_WIREDANDPULLUPFILTER GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER +#define PAL_EFR32_MODEH_WIREDANDALT GPIO_P_MODEH_MODE0_WIREDANDALT +#define PAL_EFR32_MODEH_WIREDANDALTFILTER GPIO_P_MODEH_MODE0_WIREDANDALTFILTER +#define PAL_EFR32_MODEH_WIREDANDALTPULLUP GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP +#define PAL_EFR32_MODEH_WIREDANDALTPULLUPFILTER GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER + + +#define PAL_EFR32_PORTA_MODEH_DEFAULT ((PAL_EFR32_MODEH_DEFAULT << 0U) | \ + (PAL_EFR32_MODEH_DEFAULT << 4U) | \ + (PAL_EFR32_MODEH_DEFAULT << 8U) | \ + (PAL_EFR32_MODEH_DEFAULT << 12U) | \ + (PAL_EFR32_MODEH_DEFAULT << 16U) | \ + (PAL_EFR32_MODEH_DEFAULT << 20U) | \ + (PAL_EFR32_MODEH_DEFAULT << 24U) | \ + (PAL_EFR32_MODEH_DEFAULT << 28U)) + +#define PAL_EFR32_PORTB_MODEH_DEFAULT ((PAL_EFR32_MODEH_DEFAULT << 0U) | \ + (PAL_EFR32_MODEH_DEFAULT << 4U) | \ + (PAL_EFR32_MODEH_DEFAULT << 8U) | \ + (PAL_EFR32_MODEH_DEFAULT << 12U) | \ + (PAL_EFR32_MODEH_DEFAULT << 16U) | \ + (PAL_EFR32_MODEH_DEFAULT << 20U) | \ + (PAL_EFR32_MODEH_DEFAULT << 24U) | \ + (PAL_EFR32_MODEH_DEFAULT << 28U)) + +#define PAL_EFR32_PORTC_MODEH_DEFAULT ((PAL_EFR32_MODEH_DEFAULT << 0U) | \ + (PAL_EFR32_MODEH_DEFAULT << 4U) | \ + (PAL_EFR32_MODEH_DEFAULT << 8U) | \ + (PAL_EFR32_MODEH_DEFAULT << 12U) | \ + (PAL_EFR32_MODEH_DEFAULT << 16U) | \ + (PAL_EFR32_MODEH_DEFAULT << 20U) | \ + (PAL_EFR32_MODEH_DEFAULT << 24U) | \ + (PAL_EFR32_MODEH_DEFAULT << 28U)) + +#define PAL_EFR32_PORTD_MODEH_DEFAULT ((PAL_EFR32_MODEH_DEFAULT << 0U) | \ + (PAL_EFR32_MODEH_DEFAULT << 4U) | \ + (PAL_EFR32_MODEH_DEFAULT << 8U) | \ + (PAL_EFR32_MODEH_DEFAULT << 12U) | \ + (PAL_EFR32_MODEH_DEFAULT << 16U) | \ + (PAL_EFR32_MODEH_DEFAULT << 20U) | \ + (PAL_EFR32_MODEH_DEFAULT << 24U) | \ + (PAL_EFR32_MODEH_DEFAULT << 28U)) + + +#define PAL_EFR32_DINT_DEFAULT GPIO_P_DIN_DIN_DEFAULT +#define PAL_EFR32_PORTA_DIN_DEFAULT PAL_EFR32_DIN_DEFAULT +#define PAL_EFR32_PORTB_DIN_DEFAULT PAL_EFR32_DIN_DEFAULT +#define PAL_EFR32_PORTC_DIN_DEFAULT PAL_EFR32_DIN_DEFAULT +#define PAL_EFR32_PORTD_DIN_DEFAULT PAL_EFR32_DIN_DEFAULT + + +#define PAL_EFR32_DOUT_DEFAULT GPIO_P_DOUT_DOUT_DEFAULT +#define PAL_EFR32_PORTA_DOUT_DEFAULT PAL_EFR32_DOUT_DEFAULT +#define PAL_EFR32_PORTB_DOUT_DEFAULT PAL_EFR32_DOUT_DEFAULT +#define PAL_EFR32_PORTC_DOUT_DEFAULT PAL_EFR32_DOUT_DEFAULT +#define PAL_EFR32_PORTD_DOUT_DEFAULT PAL_EFR32_DOUT_DEFAULT + + +#define PAL_EFR32_MODE_SHIFT (0U) +#define PAL_EFR32_MODE_MASK (0xFU << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_DISABLED ( 0U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_INPUT ( 1U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_INPUTPULL ( 2U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_INPUTPULL_FILTER ( 3U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_PUSHPULL ( 4U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_PUSHPULL_ALT ( 5U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDOR ( 6U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDOR_PULLDOWN ( 7U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND ( 8U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_FILTER ( 9U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_PULLUP (10U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_PULLUP_FILTER (11U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_ALT (12U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_ALT_FILTER (13U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_ALT_PULLUP (14U << PAL_EFR32_MODE_SHIFT) +#define PAL_EFR32_MODE_WIREDAND_ALT_PULLUP_FILTER (15U << PAL_EFR32_MODE_SHIFT) + + +#define PAL_EFR32_DOUT_SHIFT (4U) +#define PAL_EFR32_DOUT_MASK (1U << PAL_EFR32_DOUT_SHIFT) +#define PAL_EFR32_DOUT_LOW (0U << PAL_EFR32_DOUT_SHIFT) +#define PAL_EFR32_DOUT_PULLDOWN (0U << PAL_EFR32_DOUT_SHIFT) +#define PAL_EFR32_DOUT_FLOATING (0U << PAL_EFR32_DOUT_SHIFT) +#define PAL_EFR32_DOUT_HIGH (1U << PAL_EFR32_DOUT_SHIFT) +#define PAL_EFR32_DOUT_PULLUP (1U << PAL_EFR32_DOUT_SHIFT) +#define PAL_EFR32_DOUT_FILTER (1U << PAL_EFR32_DOUT_SHIFT) + + +#define PAL_EFR32_ALTERNATE_FUNCSEL_SHIFT (5U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_MASK (0xFFU << PAL_EFR32_ALTERNATE_FUNCSEL_SHIFT) +#define PAL_EFR32_ALTERNATE_FUNCSEL(n) ( (n) << PAL_EFR32_ALTERNATE_FUNCSEL_SHIFT) +#define PAL_EFR32_ALTERNATE_FUNCSEL_NONE PAL_EFR32_ALTERNATE_FUNCSEL(0U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_RX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(1U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_TX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(2U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_RX PAL_EFR32_ALTERNATE_FUNCSEL(3U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART0_TX PAL_EFR32_ALTERNATE_FUNCSEL(4U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_RX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(5U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_TX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(6U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_RX PAL_EFR32_ALTERNATE_FUNCSEL(7U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART1_TX PAL_EFR32_ALTERNATE_FUNCSEL(8U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_RX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(9U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_TX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(10U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_RX PAL_EFR32_ALTERNATE_FUNCSEL(11U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_EUSART2_TX PAL_EFR32_ALTERNATE_FUNCSEL(12U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_USART0_RX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(13U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_USART0_TX_DIS PAL_EFR32_ALTERNATE_FUNCSEL(14U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_USART0_RX PAL_EFR32_ALTERNATE_FUNCSEL(15U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_USART0_TX PAL_EFR32_ALTERNATE_FUNCSEL(16U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_NOCLOCK PAL_EFR32_ALTERNATE_FUNCSEL(17U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_FSRCO PAL_EFR32_ALTERNATE_FUNCSEL(18U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HFXO PAL_EFR32_ALTERNATE_FUNCSEL(19U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HFRCODPLL PAL_EFR32_ALTERNATE_FUNCSEL(20U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HFRCOEM23 PAL_EFR32_ALTERNATE_FUNCSEL(21U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_LFXO PAL_EFR32_ALTERNATE_FUNCSEL(22U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_LFRCO PAL_EFR32_ALTERNATE_FUNCSEL(23U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_ULFRCO PAL_EFR32_ALTERNATE_FUNCSEL(24U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT0_HCLK PAL_EFR32_ALTERNATE_FUNCSEL(25U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_NOCLOCK PAL_EFR32_ALTERNATE_FUNCSEL(26U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_FSRCO PAL_EFR32_ALTERNATE_FUNCSEL(27U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HFXO PAL_EFR32_ALTERNATE_FUNCSEL(28U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HFRCODPLL PAL_EFR32_ALTERNATE_FUNCSEL(29U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HFRCOEM23 PAL_EFR32_ALTERNATE_FUNCSEL(30U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_LFXO PAL_EFR32_ALTERNATE_FUNCSEL(31U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_LFRCO PAL_EFR32_ALTERNATE_FUNCSEL(32U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_ULFRCO PAL_EFR32_ALTERNATE_FUNCSEL(33U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT1_HCLK PAL_EFR32_ALTERNATE_FUNCSEL(34U) + +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_NOCLOCK PAL_EFR32_ALTERNATE_FUNCSEL(35U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_FSRCO PAL_EFR32_ALTERNATE_FUNCSEL(36U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HFXO PAL_EFR32_ALTERNATE_FUNCSEL(37U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HFRCODPLL PAL_EFR32_ALTERNATE_FUNCSEL(38U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HFRCOEM23 PAL_EFR32_ALTERNATE_FUNCSEL(39U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_LFXO PAL_EFR32_ALTERNATE_FUNCSEL(40U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_LFRCO PAL_EFR32_ALTERNATE_FUNCSEL(41U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_ULFRCO PAL_EFR32_ALTERNATE_FUNCSEL(42U) +#define PAL_EFR32_ALTERNATE_FUNCSEL_CLKOUT2_HCLK PAL_EFR32_ALTERNATE_FUNCSEL(43U) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) PAL_EFR32_ALTERNATE_FUNCSEL_##n +/** @} */ + + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +#define PAL_MODE_RESET (PAL_EFR32_MODE_DISABLED | \ + PAL_EFR32_DOUT_FLOATING) + +#define PAL_MODE_UNCONNECTED (PAL_EFR32_MODE_DISABLED | \ + PAL_EFR32_DOUT_FLOATING) + +#define PAL_MODE_INPUT (PAL_EFR32_MODE_INPUT | \ + PAL_EFR32_DOUT_FLOATING) + +#define PAL_MODE_INPUT_PULLUP (PAL_EFR32_MODE_INPUTPULL | \ + PAL_EFR32_DOUT_PULLUP) + +#define PAL_MODE_INPUT_PULLDOWN (PAL_EFR32_MODE_INPUTPULL | \ + PAL_EFR32_DOUT_PULLDOWN) + +#define PAL_MODE_INPUT_ANALOG (PAL_EFR32_MODE_INPUT | \ + PAL_EFR32_DOUT_FLOATING) + +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_EFR32_MODE_PUSHPULL | \ + PAL_EFR32_DOUT_HIGH) + +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_EFR32_MODE_WIREDAND | \ + PAL_EFR32_DOUT_PULLUP) + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16U + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + uint32_t ctrlr; /**< port control */ + uint32_t modelr; /**< mode low */ + uint32_t modehr; /**< mode high */ + uint32_t doutr; /**< data out */ +} efr32_gpio_setup_t; + +/** + * @brief EFR32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +/** @brief Port A setup data.*/ + efr32_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + efr32_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + efr32_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + efr32_gpio_setup_t PDData; +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef uint32_t ioportid_t; + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the EFR32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if EFR32_HAS_GPIOA || defined(__DOXYGEN__) +#define GPIOA GPIO_PA_INDEX +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if EFR32_HAS_GPIOB || defined(__DOXYGEN__) +#define GPIOB GPIO_PB_INDEX +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if EFR32_HAS_GPIOC || defined(__DOXYGEN__) +#define GPIOC GPIO_PC_INDEX +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if EFR32_HAS_GPIOD || defined(__DOXYGEN__) +#define GPIOD GPIO_PD_INDEX +#define IOPORT4 GPIOD +#endif + +#define GPIO_PORT_INDEX(port) (port) + +#define GPIO_PORT(port) (&(GPIO->P[GPIO_PORT_INDEX(port)])) + +#define GPIO_PORT_SIZE(port) ((port == GPIOA) ? GPIO_PA_COUNT : \ + (port == GPIOB) ? GPIO_PB_COUNT : \ + (port == GPIOC) ? GPIO_PC_COUNT : \ + (port == GPIOD) ? GPIO_PD_COUNT : \ + 0) + +#define GPIO_PORT_MASK(port) ((port == GPIOA) ? (ioportmask_t)GPIO_PA_MASK : \ + (port == GPIOB) ? (ioportmask_t)GPIO_PB_MASK : \ + (port == GPIOC) ? (ioportmask_t)GPIO_PC_MASK : \ + (port == GPIOD) ? (ioportmask_t)GPIO_PD_MASK : \ + 0) + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((ioportmask_t)(GPIO_PORT(port)->DIN) & GPIO_PORT_MASK(port)) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((ioportmask_t)(GPIO_PORT(port)->DOUT) & GPIO_PORT_MASK(port)) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((GPIO_PORT(port)->DOUT = (ioportmask_t)(bits) & GPIO_PORT_MASK(port))) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((GPIO->P_SET[GPIO_PORT_INDEX(port)].DOUT = (ioportmask_t)(bits) & GPIO_PORT_MASK(port))) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((GPIO->P_CLR[GPIO_PORT_INDEX(port)].DOUT = (ioportmask_t)(bits) & GPIO_PORT_MASK(port))) + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @notapi + */ +#define pal_lld_toggleport(port, bits) ((GPIO->P_TGL[GPIO_PORT_INDEX(port)].DOUT = (ioportmask_t)(bits) & GPIO_PORT_MASK(port))) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) ((((GPIO_PORT(port)->DIN >> pad) & 1) == 1) ? \ + PAL_HIGH : PAL_LOW) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + do { \ + if ((bit) == PAL_HIGH) \ + GPIO->P_SET[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + else \ + GPIO->P_CLR[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + } while (false) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + do { \ + if (!!PAL_HIGH) \ + GPIO->P_SET[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + else \ + GPIO->P_CLR[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + } while (false) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + do { \ + if (!!PAL_HIGH) \ + GPIO->P_CLR[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + else \ + GPIO->P_SET[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + } while (false) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) \ + do { \ + GPIO->P_TGL[GPIO_PORT_INDEX(port)].DOUT = 1 << (pad); \ + } while (false) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) \ + _pal_lld_setpadmode(port, pad, mode); \ + _pal_lld_setalternatefunction(port, pad, mode) + +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[pad]; (void)(port) + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[PAL_PAD(line)] + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) +#define PAL_EVENTS_SIZE 16U +extern palevent_t _pal_events[PAL_EVENTS_SIZE]; +#endif +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif +void _pal_lld_init(const PALConfig* config); +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode); +void _pal_lld_setpadmode(ioportid_t port, iopadid_t pad, iomode_t mode); +void _pal_lld_setalternatefunction(ioportid_t port, iopadid_t pad, iomode_t mode); +void _pal_lld_enablepadevent(ioportid_t port, iopadid_t pad, ioeventmode_t mode); +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL == TRUE */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/driver.mk b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/driver.mk new file mode 100644 index 0000000000..088d865d84 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.c + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3 diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.c b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.c new file mode 100644 index 0000000000..0d0f042628 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.c @@ -0,0 +1,199 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv3/hal_st_lld.c + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + #if EFR32_ST_USE_TIMER == 1 + #if (OSAL_ST_RESOLUTION == 32) && !EFR32_LETIM1_IS_32BITS + #error "LETIM1 is not a 32 bit timer" + #endif + + #if !EFR32_HAS_LETIM1 + #error "LETIM1 not present in the selected device" + #endif + + #define ST_HANDLER EFR32_LETIM1_HANDLER + #define ST_NUMBER EFR32_LETIM1_NUMBER + #define ST_CLOCK_SRC EFR32_LETIM1CLK + #define ST_ENABLE_CLOCK() CMU->CLKEN0_SET = CMU_CLKEN0_LETIMER0 + #else + #error "EFR32_ST_USE_TIMER specifies an unsupported timer" + #endif + + #if (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 256U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV256 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 128U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV128 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 64U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV64 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 32U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV32 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 16U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV16 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 8U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV8 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 4U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV4 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 2U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV2 + #elif (ST_CLOCK_SRC/OSAL_ST_FREQUENCY == 1U) + #define EFR32_ST_PRESC LETIMER_CTRL_CNTPRESC_DIV1 + #else + #error "EFR32_ST_PRESC is not obtainable" + #endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + #error "OSAL_ST_MODE_PERIODIC is not supported by SYSTICKv3" +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + + +#if !defined(EFR32_SYSTICK_SUPPRESS_ISR) +/** + * @brief Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + st_lld_serve_interrupt(); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + osalDbgAssert((ST_CLOCK_SRC % OSAL_ST_FREQUENCY) == 0U, + "clock rounding error"); + osalDbgAssert(((ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1U) < 0x10000, + "clock prescaler overflow"); + + /* Enabling timer clock. */ + ST_ENABLE_CLOCK(); + + /* Enable timer. */ + EFR32_ST_TIM->EN_SET = LETIMER_EN_EN; + + /* Initializing the counter in free running mode. */ + EFR32_ST_TIM->IEN = 0; + EFR32_ST_TIM->IF_CLR = _LETIMER_IF_MASK; + EFR32_ST_TIM->CTRL = LETIMER_CTRL_REPMODE_FREE | EFR32_ST_PRESC; + EFR32_ST_TIM->COMP0 = 0; + +#if ST_LLD_NUM_ALARMS > 1 + EFR32_ST_TIM->COMP1 = 0; +#endif + + /* Wait for command to complete. */ + while (EFR32_ST_TIM->SYNCBUSY & (LETIMER_SYNCBUSY_START | LETIMER_SYNCBUSY_CNT)) { + } + + /* Start timer on continuous mode. */ + EFR32_ST_TIM->CNT = 0; + EFR32_ST_TIM->CMD = LETIMER_CMD_START; + +#if !defined(EFR32_SYSTICK_SUPPRESS_ISR) + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, EFR32_ST_IRQ_PRIORITY); +#endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + + /* IRQ enabled.*/ + nvicEnableVector(HANDLER_SYSTICK, EFR32_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + if ((EFR32_ST_TIM->IF & LETIMER_IF_COMP0) != 0U) { + EFR32_ST_TIM->IF_CLR = LETIMER_IF_COMP0; +#endif + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + } +#if ST_LLD_NUM_ALARMS > 1 + if ((EFR32_ST_TIM->IF & LETIMER_IF_COMP1) != 0U) { + EFR32_ST_TIM->IF_CLR = LETIMER_IF_COMP1; + if (st_callbacks[1] != NULL) { + st_callbacks[1](1U); + } + } +#endif +#endif +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.h b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.h new file mode 100644 index 0000000000..990af3a00a --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/hal_st_lld.h @@ -0,0 +1,291 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv3/hal_st_lld.h + * @brief ST Driver subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Counter registry initial value. + */ +#if (OSAL_ST_RESOLUTION == 32) + #define ST_INIT_VALUE 0x00FFFFFFUL +#else + #define ST_INIT_VALUE 0x0000FFFFUL +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief LETIM1x unit (by number) to be used for free running operations. + * @note You must select a 16 bits timer if a 16 bits @p systick_t type + * is required. + * @note Timer 1 supported. + */ +#if !defined(EFR32_ST_USE_TIMER) || defined(__DOXYGEN__) + #define EFR32_ST_USE_TIMER 1 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) +#if !defined(EFR32_HAS_LETIM1) + #define EFR32_HAS_LETIM1 FALSE +#endif + +#if EFR32_ST_USE_TIMER == 1 + #if defined(EFR32_LETIM1_IS_USED) + #error "ST requires LETIM1 but the timer is already used" + #else + #define EFR32_LETIM1_IS_USED + #endif + + #define EFR32_ST_TIM LETIMER0 +#endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/** + * @brief ST Alarms number. + */ +#define ST_LLD_NUM_ALARMS 2 + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void st_lld_init(void); +void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + + return ((systime_t)(ST_INIT_VALUE - EFR32_ST_TIM->CNT)); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + + EFR32_ST_TIM->IEN_CLR = LETIMER_IEN_COMP0; + + #if (OSAL_ST_RESOLUTION == 32) + EFR32_ST_TIM->COMP0 = (uint32_t)ST_INIT_VALUE - (uint32_t)abstime; + #else + EFR32_ST_TIM->COMP0 = (uint16_t)ST_INIT_VALUE - (uint16_t)abstime; + #endif + + EFR32_ST_TIM->IEN_SET = LETIMER_IEN_COMP0; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + + EFR32_ST_TIM->IEN_CLR = LETIMER_IEN_COMP0; +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + + st_lld_start_alarm(abstime); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return ((systime_t)(ST_INIT_VALUE - EFR32_ST_TIM->COMP0)); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return ((EFR32_ST_TIM->IEN & LETIMER_IEN_COMP0) != 0U); +} + +#if (ST_LLD_NUM_ALARMS > 1) || defined(__DOXYGEN__) + +/** + * @brief Starts an alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * @param[in] abstime the time to be set for the first alarm + * @param[in] alarm alarm channel number + * @notapi + */ +static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) { + + (void)alarm; + + EFR32_ST_TIM->IEN_CLR = LETIMER_IEN_COMP1; + + #if (OSAL_ST_RESOLUTION == 32) + EFR32_ST_TIM->COMP1 = (uint32_t)ST_INIT_VALUE - (uint32_t)abstime; + #else + EFR32_ST_TIM->COMP1 = (uint16_t)ST_INIT_VALUE - (uint16_t)abstime; + #endif + + EFR32_ST_TIM->IEN_SET = LETIMER_IEN_COMP1; +} + +/** + * @brief Stops an alarm interrupt. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * @param[in] alarm alarm channel number + * @notapi + */ +static inline void st_lld_stop_alarm_n(unsigned alarm) { + + (void)alarm; + EFR32_ST_TIM->IEN_CLR = LETIMER_IEN_COMP1; +} + +/** + * @brief Sets an alarm time. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * @param[in] alarm alarm channel number + * @param[in] abstime the time to be set for the next alarm + * @notapi + */ +static inline void st_lld_set_alarm_n(unsigned alarm, systime_t abstime) { + + (void)alarm; + st_lld_start_alarm_n(alarm, abstime); +} + +/** + * @brief Returns an alarm current time. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * @param[in] alarm alarm channel number + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm_n(unsigned alarm) { + + (void)alarm; + return ((systime_t)(ST_INIT_VALUE - EFR32_ST_TIM->COMP1)); +} + +/** + * @brief Determines if an alarm is active. + * @param[in] alarm alarm channel number + * + * @return The alarm status. + * + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * @notapi + */ +static inline bool st_lld_is_alarm_active_n(unsigned alarm) { + + (void)alarm; + return ((EFR32_ST_TIM->IEN & LETIMER_IEN_COMP1) != 0U); +} +#endif /* ST_LLD_NUM_ALARMS > 1 */ + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/readme.txt b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/readme.txt new file mode 100644 index 0000000000..194c39eed7 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/EFR32FG23/SYSTICKv3/readme.txt @@ -0,0 +1,37 @@ +How to use LETIMERx present on EFR32FG1X controllers as system tick. + +Also see under demos/SILABS. + +1) In your mcuconf.h make sure, that: + +#define EFR32_LETIM1SEL EFR32_LETIM1SEL_LFXO +#define EFR32_LETIM2SEL EFM32_LETIM2SEL_LFXO + +or + +#define EFM32_LETIM1SEL EFM32_LETIM1SEL_LFRCO +#define EFM32_LETIM2SEL EFM32_LETIM2SEL_LFRCO + + +2) In your chconf.h make sure, that: + +#define CH_CFG_ST_RESOLUTION 16 +#define CH_CFG_ST_TIMEDELTA 6 +#define CH_CFG_ST_FREQUENCY 1024 // If LFXO used as src clk +#define CH_CFG_ST_FREQUENCY 1024 // If LFRCO used as src clk +#define CH_CFG_ST_FREQUENCY 1000 // If ULFRCO used as src clk + + +You can't use osDelay() or other "sleeping" functions for periods +longer than: + LETIM_ARR_MAX + 1 65536 +----------------------------------- = ------------------- seconds. +LETIM_CLOCK / LETIM_CLOCK_PRESCALER CH_CFG_ST_FREQUENCY + +For instance, with CH_CFG_ST_FREQUENCY = 1024 the period is 64 seconds. + +Known good combinations of CH_CFG_ST_FREQUENCY/CH_CFG_ST_TIMEDELTA: +a) 1000/8 or 1024/8 +b) 2000/4 or 2048/4 +c) 4000/2 or 4096/2 +d) 8000/2 or 8192/2 diff --git a/os/hal/ports/SILABS/LLD/common/SYSTICKv1/driver.mk b/os/hal/ports/SILABS/LLD/common/SYSTICKv1/driver.mk new file mode 100644 index 0000000000..3c566ef5c8 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/common/SYSTICKv1/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.c + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/LLD/common/SYSTICKv1 diff --git a/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.c b/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.c new file mode 100644 index 0000000000..9319681198 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.c @@ -0,0 +1,118 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief PLATFORM ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING +#error "OSAL_ST_MODE_FREERUNNING is not supported by SYSTICKv1" +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC +#define SYSTICK_CK_MAX 0x00FFFFFFU +#define ST_HANDLER SysTick_Handler +#define SYSTICK_CK EFR32_HCLK +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > SYSTICK_CK_MAX +#error "the selected ST frequency is not obtainable because of timer counter limits" +#endif + +#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because of integer rounding" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + st_lld_serve_interrupt(); + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, EFR32_ST_IRQ_PRIORITY); +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.h b/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.h new file mode 100644 index 0000000000..dda8a966b3 --- /dev/null +++ b/os/hal/ports/SILABS/LLD/common/SYSTICKv1/hal_st_lld.h @@ -0,0 +1,76 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(EFR32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define EFR32_ST_IRQ_PRIORITY 4 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); + void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TI/CC13x0Fxx/hal_lld.c b/os/hal/ports/TI/CC13x0Fxx/hal_lld.c new file mode 100644 index 0000000000..074b4431de --- /dev/null +++ b/os/hal/ports/TI/CC13x0Fxx/hal_lld.c @@ -0,0 +1,74 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TI/CC13x0Fxx/hal_lld.c + * @brief CC13x0Fxx HAL Driver subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) +{ +} + +/** + * @brief CC13x0Fxx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p mcuconf.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void ti_clock_init(void) +{ +} + +/** + * @} + */ diff --git a/os/hal/ports/TI/CC13x0Fxx/hal_lld.h b/os/hal/ports/TI/CC13x0Fxx/hal_lld.h new file mode 100644 index 0000000000..753e09c7a9 --- /dev/null +++ b/os/hal/ports/TI/CC13x0Fxx/hal_lld.h @@ -0,0 +1,111 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TI/CC13x0Fxx/hal_lld.h + * @brief CC13x0Fxx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - TODO: add required macros + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H +#define HAL_LLD_H + +#include "ti_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ + +#define PLATFORM_NAME "CC13x0 Series" + +/** + * @} + */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(CC13x0_MCUCONF) +#error "Using a wrong mcuconf.h file, CC13x0_MCUCONF not defined" +#endif + +/* + * Oscillator-related checks. + */ +#define TI_MAX_FREQ_SYSCLK 48000000UL + +/* + * System Clock calculation + */ + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "ti_isr.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ti_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H */ + +/** + * @} + */ diff --git a/os/hal/ports/TI/CC13x0Fxx/platform.mk b/os/hal/ports/TI/CC13x0Fxx/platform.mk new file mode 100644 index 0000000000..0cb20b8f69 --- /dev/null +++ b/os/hal/ports/TI/CC13x0Fxx/platform.mk @@ -0,0 +1,30 @@ +# List of all the platform files. +PLATFORMSRC_CONTRIB = $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/TI/CC13x0Fxx/hal_lld.c + + +# Required include directories +PLATFORMINC_CONTRIB = $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/TI/CC13x0Fxx + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) +endif #ifeq ($(USE_SMART_BUILD), yes) + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/TI/LLD/SYSTICKv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/TI/CC13x0Fxx/ti_isr.h b/os/hal/ports/TI/CC13x0Fxx/ti_isr.h new file mode 100644 index 0000000000..1eb550ded3 --- /dev/null +++ b/os/hal/ports/TI/CC13x0Fxx/ti_isr.h @@ -0,0 +1,66 @@ +/* + Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CC13x0/ti_isr.h + * @brief CC13x0 ISR remapper driver header. + * + * @addtogroup CC13x0_ISR + * @{ + */ + +#ifndef _TI_ISR_H_ +#define _TI_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ + + +/** + * @} + */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _TI_ISR_H_ */ + +/** + * @} + */ diff --git a/os/hal/ports/TI/CC13x0Fxx/ti_registry.h b/os/hal/ports/TI/CC13x0Fxx/ti_registry.h new file mode 100644 index 0000000000..2dc7e8af66 --- /dev/null +++ b/os/hal/ports/TI/CC13x0Fxx/ti_registry.h @@ -0,0 +1,36 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CC13x0Fxx/ti_registry.h + * @brief CC13x0 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef TI_REGISTRY_H +#define TI_REGISTRY_H + + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + + +#endif /* TI_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/TI/LLD/SYSTICKv1/driver.mk b/os/hal/ports/TI/LLD/SYSTICKv1/driver.mk new file mode 100644 index 0000000000..e771af2567 --- /dev/null +++ b/os/hal/ports/TI/LLD/SYSTICKv1/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.c + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/TI/LLD/SYSTICKv1 diff --git a/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.c new file mode 100644 index 0000000000..4b4bfe9870 --- /dev/null +++ b/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.c @@ -0,0 +1,105 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief PLATFORM ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ +OSAL_IRQ_HANDLER(SysTick_Handler) { + + OSAL_IRQ_PROLOGUE(); + + st_lld_serve_interrupt(); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + uint32_t clockval; + + clockval = 48000000; + clockval /= OSAL_ST_FREQUENCY; + + /* period for systick */ + HWREG(NVIC_ST_RELOAD) = clockval - 1; + + /* Nullify current value */ + HWREG(NVIC_ST_CURRENT) = 0; + + /* Enable SysTick */ + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; + + /* Enable Systick interrupt */ + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.h new file mode 100644 index 0000000000..376a02f40e --- /dev/null +++ b/os/hal/ports/TI/LLD/SYSTICKv1/hal_st_lld.h @@ -0,0 +1,143 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); + void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + + uint32_t value = HWREG(NVIC_ST_CURRENT); + return (systime_t)value; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + + (void)abstime; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + + (void)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)0; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return false; +} + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/src/hal_buram.c b/os/hal/src/hal_buram.c new file mode 100644 index 0000000000..786fbd8204 --- /dev/null +++ b/os/hal/src/hal_buram.c @@ -0,0 +1,252 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in buramliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_buram.c + * @brief BURAM Driver code. + * + * @addtogroup BURAM + * @{ + */ + +#include "hal.h" +#include "hal_buram.h" + +#if HAL_USE_BURAM || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BURAM1_MAP_LEN (BURAM1_SIZE / (sizeof(bitmap_word_t) * 8)) + +#define BURAM2_MAP_LEN (BURAM2_SIZE / (sizeof(bitmap_word_t) * 8)) + +#define BURAM3_MAP_LEN (BURAM3_SIZE / (sizeof(bitmap_word_t) * 8)) + +#define BURAM4_MAP_LEN (BURAM4_SIZE / (sizeof(bitmap_word_t) * 8)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if BURAM_USE_BURAM1 +static bitmap_word_t buram1_map_array[BURAM1_MAP_LEN]; +#endif + +#if BURAM_USE_BURAM2 +static bitmap_word_t buram2_map_array[BURAM2_MAP_LEN]; +#endif + +#if BURAM_USE_BURAM3 +static bitmap_word_t buram3_map_array[BURAM3_MAP_LEN]; +#endif + +#if BURAM_USE_BURAM4 +static bitmap_word_t buram4_map_array[BURAM4_MAP_LEN]; +#endif + +/** + * @brief BURAM1 driver identifier. + */ +#if BURAM_USE_BURAM1 || defined(__DOXYGEN__) +BURAMDriver BURAMD1 = { + .state = BURAM_READY, + .start = BURAM1_ADDRESS, + .end = BURAM1_ADDRESS + BURAM1_SIZE, + .buram_map.array = buram1_map_array, + .buram_map.len = sizeof(buram1_map_array) / sizeof(buram1_map_array[0]), +}; +#endif + +/** + * @brief BURAM2 driver identifier. + */ +#if BURAM_USE_BURAM2 || defined(__DOXYGEN__) +BURAMDriver BURAMD2 = { + .state = BURAM_READY, + .start = BURAM2_ADDRESS, + .end = BURAM2_ADDRESS + BURAM2_SIZE, + .buram_map.array = buram2_map_array, + .buram_map.len = sizeof(buram2_map_array) / sizeof(buram2_map_array[0]), +}; +#endif + +/** + * @brief BURAM3 driver identifier. + */ +#if BURAM_USE_BURAM3 || defined(__DOXYGEN__) +BURAMDriver BURAMD3 = { + .state = BURAM_READY, + .start = BURAM3_ADDRESS, + .end = BURAM3_ADDRESS + BURAM3_SIZE, + .buram_map.array = buram3_map_array, + .buram_map.len = sizeof(buram3_map_array) / sizeof(buram3_map_array[0]), +}; +#endif + +/** + * @brief BURAM4 driver identifier. + */ +#if BURAM_USE_BURAM4 || defined(__DOXYGEN__) +BURAMDriver BURAMD4 = { + .state = BURAM_READY, + .start = BURAM4_ADDRESS, + .end = BURAM4_ADDRESS + BURAM4_SIZE, + .buram_map.array = buram4_map_array, + .buram_map.len = sizeof(buram4_map_array) / sizeof(buram4_map_array[0]), +}; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief BURAM Driver initialization. + * @note This function is not implicitly invoked by @p halInit(), there is + * the need to explicitly initialize the driver. + * + * @init + */ +void buramInit(void) { + + /* Using static RAM for BURAMDx guarantees adequate structure + initialisation right after reset. */ +} + +/** + * @brief Initializes the standard part of a @p BURAMDriver structure. + * + * @param[out] buramp pointer to the @p BURAMDriver object + * + * @init + */ +void buramObjectInit(BURAMDriver *buramp) { + + (void)buramp; + + /* Using static RAM for BURAMDx guarantees adequate structure + initialisation right after reset. */ +} + +/** + * @brief Configures and activates the BURAM peripheral. + * + * @param[in] buramp pointer to the @p BURAMDriver object + * @param[in] config pointer to the @p BURAMConfig object + * + * @api + */ +void buramStart(BURAMDriver *buramp, const BURAMConfig *config) { + + osalDbgCheck((buramp != NULL) && (config != NULL)); + + osalSysLock(); + osalDbgAssert((buramp->state == BURAM_STOP) || (buramp->state == BURAM_READY), + "invalid state"); + buram_lld_start(buramp, config); + buramp->state = BURAM_READY; + osalSysUnlock(); +} + +/** + * @brief Deactivates the BURAM peripheral. + * + * @param[in] buramp pointer to the @p BURAMDriver object + * + * @api + */ +void buramStop(BURAMDriver *buramp) { + + osalDbgCheck(buramp != NULL); + + osalSysLock(); + osalDbgAssert((buramp->state == BURAM_STOP) || (buramp->state == BURAM_READY), + "invalid state"); + buram_lld_stop(buramp); + buramp->state = BURAM_STOP; + osalSysUnlock(); +} + +/** + * @brief Allocates backup RAM. + * + * @param[in] buramp pointer to the @p BURAMDriver object + * @param[in] address address of memory to allocate. Starts at 0 + * @param[in] size size of memory to allocate + * + * @api + */ +volatile void* buramAllocateAtI(BURAMDriver* buramp, uintptr_t address, size_t size) { + + osalDbgCheck(buramp != NULL); + + osalDbgAssert((buramp->state == BURAM_READY), "invalid state"); + + if (buramp->start + address + size >= buramp->end) { + osalDbgAssert(false, "exceeded available amount of BURAM"); + return NULL; + } + + /* Check if all requested bytes can be allocated. */ + for (size_t bit = address; bit < address + size; bit++) { + bitmap_word_t bit_state = bitmapGet(&buramp->buram_map, bit); + if (bit_state != (bitmap_word_t)0) { /* Byte is allocated? */ + osalDbgAssert(false, "BURAM is already allocated"); + return NULL; /* Yes, it was. */ + } + } + + /* All requested bytes will be marked as allocated. */ + for (size_t bit = address; bit < address + size; bit++) { + bitmapSet(&buramp->buram_map, bit); + } + + return (volatile void*)(buramp->start + address); +} + +/** + * @brief Allocates backup RAM. + * + * @param[in] buramp pointer to the @p BURAMDriver object + * @param[in] address address of memory to allocate. Starts at 0 + * @param[in] size size of memory to allocate + * + * @api + */ +volatile void* buramAllocateAt(BURAMDriver *buramp, uintptr_t address, size_t size) { + + volatile void *addr; + + osalSysLock(); + addr = buramAllocateAtI(buramp, address, size); + osalSysUnlock(); + return addr; +} + +#endif /* HAL_USE_BURAM */ + +/** @} */ \ No newline at end of file diff --git a/os/various/anjay_bindings/anjay.mk b/os/various/anjay_bindings/anjay.mk new file mode 100644 index 0000000000..ceb1cd3996 --- /dev/null +++ b/os/various/anjay_bindings/anjay.mk @@ -0,0 +1,143 @@ +# ANJAY files. + +AVS_COMMONS = $(CHIBIOS_CONTRIB)/ext/avs_commons-5.4.1 +ANJAY = $(CHIBIOS_CONTRIB)/ext/Anjay-3.5.0 +ANJAY_COAP = $(ANJAY)/deps/avs_coap +ANJAY_BINDINGS=$(CHIBIOS_CONTRIB)/os/various/anjay_bindings + +ANJAYSRC = \ + $(ANJAY_BINDINGS)/compat/threading/avs_cmsis_os_condvar.c \ + $(ANJAY_BINDINGS)/compat/threading/avs_cmsis_os_init_once.c \ + $(ANJAY_BINDINGS)/compat/threading/avs_csmis_os_mutex.c \ + $(ANJAY_BINDINGS)/compat/stdlib/avs_memory_chibios.c \ + $(ANJAY_BINDINGS)/compat/stdlib/avs_time_chibios.c \ + $(ANJAY_BINDINGS)/compat/stdlib/avs_math_chibios.c \ + $(AVS_COMMONS)/src/algorithm/avs_base64.c \ + $(AVS_COMMONS)/src/buffer/avs_buffer.c \ + $(AVS_COMMONS)/src/crypto/generic/avs_generic_prng.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_aead.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_data_loader.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_global.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_hkdf.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_pki.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_private.c \ + $(AVS_COMMONS)/src/crypto/mbedtls/avs_mbedtls_prng.c \ + $(AVS_COMMONS)/src/crypto/avs_crypto_global.c \ + $(AVS_COMMONS)/src/crypto/avs_crypto_persistence.c \ + $(AVS_COMMONS)/src/crypto/avs_crypto_utils.c \ + $(AVS_COMMONS)/src/list/avs_list.c \ + $(AVS_COMMONS)/src/log/avs_log.c \ + $(AVS_COMMONS)/src/net/mbedtls/avs_mbedtls_persistence.c \ + $(AVS_COMMONS)/src/net/mbedtls/avs_mbedtls_socket.c \ + $(AVS_COMMONS)/src/net/tinydtls/avs_tinydtls.c \ + $(AVS_COMMONS)/src/net/avs_addrinfo.c \ + $(AVS_COMMONS)/src/net/avs_api.c \ + $(AVS_COMMONS)/src/net/avs_net_global.c \ + $(AVS_COMMONS)/src/persistence/avs_persistence.c \ + $(AVS_COMMONS)/src/rbtree/avs_rbtree.c \ + $(AVS_COMMONS)/src/sched/avs_sched.c \ + $(AVS_COMMONS)/src/sorted_set/avs_sorted_set.c \ + $(AVS_COMMONS)/src/stream/avs_stream.c \ + $(AVS_COMMONS)/src/stream/avs_stream_buffered.c \ + $(AVS_COMMONS)/src/stream/avs_stream_common.c \ + $(AVS_COMMONS)/src/stream/avs_stream_file.c \ + $(AVS_COMMONS)/src/stream/avs_stream_inbuf.c \ + $(AVS_COMMONS)/src/stream/avs_stream_membuf.c \ + $(AVS_COMMONS)/src/stream/avs_stream_simple_io.c \ + $(AVS_COMMONS)/src/stream/md5/avs_md5_common.c \ + $(AVS_COMMONS)/src/stream/md5/avs_md5_impl.c \ + $(AVS_COMMONS)/src/stream/net/avs_netbuf.c \ + $(AVS_COMMONS)/src/stream/net/avs_stream_net.c \ + $(AVS_COMMONS)/src/url/avs_url.c \ + $(AVS_COMMONS)/src/utils/avs_cleanup.c \ + $(AVS_COMMONS)/src/utils/avs_hexlify.c \ + $(AVS_COMMONS)/src/utils/avs_numbers.c \ + $(AVS_COMMONS)/src/utils/avs_shared_buffer.c \ + $(AVS_COMMONS)/src/utils/avs_strerror.c \ + $(AVS_COMMONS)/src/utils/avs_strings.c \ + $(AVS_COMMONS)/src/utils/avs_time.c \ + $(AVS_COMMONS)/src/utils/avs_token.c \ + $(AVS_COMMONS)/src/vector/avs_vector.c \ + $(ANJAY)/src/core/io/cbor/anjay_cbor_encoder_ll.c \ + $(ANJAY)/src/core/io/cbor/anjay_json_like_cbor_decoder.c \ + $(ANJAY)/src/core/io/json/anjay_json_decoder.c \ + $(ANJAY)/src/core/io/anjay_base64_out.c \ + $(ANJAY)/src/core/io/anjay_batch_builder.c \ + $(ANJAY)/src/core/io/anjay_cbor_in.c \ + $(ANJAY)/src/core/io/anjay_cbor_out.c \ + $(ANJAY)/src/core/io/anjay_common.c \ + $(ANJAY)/src/core/io/anjay_dynamic.c \ + $(ANJAY)/src/core/io/anjay_input_buf.c \ + $(ANJAY)/src/core/io/anjay_json_encoder.c \ + $(ANJAY)/src/core/io/anjay_json_like_decoder.c \ + $(ANJAY)/src/core/io/anjay_opaque.c \ + $(ANJAY)/src/core/io/anjay_output_buf.c \ + $(ANJAY)/src/core/io/anjay_senml_in.c \ + $(ANJAY)/src/core/io/anjay_senml_like_encoder.c \ + $(ANJAY)/src/core/io/anjay_senml_like_out.c \ + $(ANJAY)/src/core/io/anjay_text.c \ + $(ANJAY)/src/core/io/anjay_tlv_in.c \ + $(ANJAY)/src/core/io/anjay_tlv_out.c \ + $(ANJAY_COAP)/src/avs_coap_code_utils.c \ + $(ANJAY_COAP)/src/avs_coap_common_utils.c \ + $(ANJAY_COAP)/src/avs_coap_ctx.c \ + $(ANJAY_COAP)/src/async/avs_coap_async_client.c \ + $(ANJAY_COAP)/src/async/avs_coap_async_server.c \ + $(ANJAY_COAP)/src/async/avs_coap_exchange.c \ + $(ANJAY_COAP)/src/options/avs_coap_iterator.c \ + $(ANJAY_COAP)/src/options/avs_coap_option.c \ + $(ANJAY_COAP)/src/options/avs_coap_options.c \ + $(ANJAY_COAP)/src/streaming/avs_coap_streaming_client.c \ + $(ANJAY_COAP)/src/streaming/avs_coap_streaming_server.c \ + $(ANJAY_COAP)/src/tcp/avs_coap_tcp_ctx.c \ + $(ANJAY_COAP)/src/tcp/avs_coap_tcp_header.c \ + $(ANJAY_COAP)/src/tcp/avs_coap_tcp_msg.c \ + $(ANJAY_COAP)/src/tcp/avs_coap_tcp_pending_requests.c \ + $(ANJAY_COAP)/src/tcp/avs_coap_tcp_signaling.c \ + $(ANJAY_COAP)/src/tcp/avs_coap_tcp_utils.c \ + $(ANJAY_COAP)/src/udp/avs_coap_udp_ctx.c \ + $(ANJAY_COAP)/src/udp/avs_coap_udp_msg.c \ + $(ANJAY_COAP)/src/udp/avs_coap_udp_msg_cache.c \ + $(ANJAY_COAP)/src/udp/avs_coap_udp_tx_params.c \ + $(AVS_COMMONS)/src/net/compat/posix/avs_compat_addrinfo.c \ + $(AVS_COMMONS)/src/net/compat/posix/avs_inet_ntop.c + +ifeq ($(USE_LWIP),yes) +ANJAYSRC += \ + $(AVS_COMMONS)/src/net/compat/posix/avs_net_impl.c +else +ANJAYSRC += \ + $(ANJAY_BINDINGS)/compat/net/xcc_wiznet_sockets_net_impl.c +endif + +ANJAYINC = \ + $(ANJAY_BINDINGS) \ + $(ANJAY_BINDINGS)/compat/net \ + $(ANJAY_BINDINGS)/compat/threading \ + $(ANJAY_BINDINGS)/compat/stdlib \ + $(AVS_COMMONS)/include_public \ + $(AVS_COMMONS) \ + $(AVS_COMMONS)/src \ + $(AVS_COMMONS)/src/net \ + $(AVS_COMMONS)/src/net/compat/posix \ + $(AVS_COMMONS)/src/net/mbedtls \ + $(AVS_COMMONS)/src/crypto \ + $(AVS_COMMONS)/src/crypto/mbedtls \ + $(AVS_COMMONS)/src/stream \ + $(AVS_COMMONS)/src/stream/md5 \ + $(ANJAY)/include_public \ + $(ANJAY)/src/core/io/cbor \ + $(ANJAY)/src/core/io/json \ + $(ANJAY)/src/core/io \ + $(ANJAY)/src \ + $(ANJAY_COAP)/include_public \ + $(ANJAY_COAP)/src \ + $(ANJAY_COAP)/src/async \ + $(ANJAY_COAP)/src/options \ + $(ANJAY_COAP)/src/streaming \ + $(ANJAY_COAP)/src/tcp \ + $(ANJAY_COAP)/src/udp + +# Shared variables +ALLCSRC += $(ANJAYSRC) +ALLINC += $(ANJAYINC) diff --git a/os/various/anjay_bindings/avsystem/commons/xcc_wiznet_posix_compat.h b/os/various/anjay_bindings/avsystem/commons/xcc_wiznet_posix_compat.h new file mode 100644 index 0000000000..a814b5bd96 --- /dev/null +++ b/os/various/anjay_bindings/avsystem/commons/xcc_wiznet_posix_compat.h @@ -0,0 +1,23 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef XCC_WIZNET_POSIX_COMPAT_H +#define XCC_WIZNET_POSIX_COMPAT_H + +typedef struct xcc_net_socket_impl xcc_net_socket_impl_t; + +#endif /* XCC_WIZNET_POSIX_COMPAT_H */ + diff --git a/os/various/anjay_bindings/compat/net/xcc_wiznet_sockets.h b/os/various/anjay_bindings/compat/net/xcc_wiznet_sockets.h new file mode 100644 index 0000000000..d03ab027b2 --- /dev/null +++ b/os/various/anjay_bindings/compat/net/xcc_wiznet_sockets.h @@ -0,0 +1,41 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef XCC_WIZNET_SOCKETS_H +#define XCC_WIZNET_SOCKETS_H + +#include +#include + +#include +#include + +// Forward declarations of avs_net APIs that must be implemented +void _avs_net_cleanup_global_compat_state(void); + +avs_error_t _avs_net_create_tcp_socket(avs_net_socket_t **socket, + const void *socket_configuration); + +avs_error_t _avs_net_create_udp_socket(avs_net_socket_t **socket, + const void *socket_configuration); + +int xcc_net_socket_poll_single(xcc_net_socket_impl_t *socket, + int64_t timeout_ms, + short events, + short *revents); + +#endif /* XCC_WIZNET_SOCKETS_H */ + diff --git a/os/various/anjay_bindings/compat/net/xcc_wiznet_sockets_net_impl.c b/os/various/anjay_bindings/compat/net/xcc_wiznet_sockets_net_impl.c new file mode 100644 index 0000000000..48d29f37cf --- /dev/null +++ b/os/various/anjay_bindings/compat/net/xcc_wiznet_sockets_net_impl.c @@ -0,0 +1,633 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + The code below is initially based on + Anjay-freertos-client-23.09/Application/Src/compat/net/xcc_com_sockets_net_impl.c. + with following copyright information: + +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "xcc_wiznet_sockets.h" +#include "wiznet_chibios.h" + +#define REMOTE_HOST_BUF_SIZE sizeof("255.255.255.255") +#define REMOTE_PORT_BUF_SIZE AVS_UINT_STR_BUF_SIZE(uint16_t) + +struct xcc_net_socket_impl { + const avs_net_socket_v_table_t *operations; + xcc_net_socket_impl_t *self; + int address_family; + int forced_mtu; + int socktype; + int32_t fd; + char remote_host_str[REMOTE_HOST_BUF_SIZE]; + char remote_port_str[REMOTE_PORT_BUF_SIZE]; + IP_Address_t remote_host; + uint16_t remote_port; + avs_time_duration_t recv_timeout; + uint64_t bytes_sent; + uint64_t bytes_received; +}; + +static struct xcc_net_socket_impl wiznet_sock; + +avs_error_t _avs_net_initialize_global_compat_state(void) { + + return AVS_OK; +} + +void _avs_net_cleanup_global_compat_state(void) { } + +static avs_errno_t wizchip_sockets_err_to_avs_errno(int err) { + + switch (err) { + case WIZCHIP_SOCKETS_ERR_OK: + return AVS_NO_ERROR; + + case WIZCHIP_SOCKETS_ERR_DESCRIPTOR: + return AVS_EIO; + + case WIZCHIP_SOCKETS_ERR_PARAMETER: + return AVS_EINVAL; + + case WIZCHIP_SOCKETS_ERR_WOULDBLOCK: + return AVS_EAGAIN; + + case WIZCHIP_SOCKETS_ERR_NOMEMORY: + return AVS_ENOMEM; + + case WIZCHIP_SOCKETS_ERR_CLOSING: + return AVS_ENOTCONN; + + case WIZCHIP_SOCKETS_ERR_LOCKED: + return AVS_EADDRINUSE; + + case WIZCHIP_SOCKETS_ERR_TIMEOUT: + return AVS_ETIMEDOUT; + + case WIZCHIP_SOCKETS_ERR_INPROGRESS: + return AVS_EINPROGRESS; + + case WIZCHIP_SOCKETS_ERR_NONAME: + return AVS_EHOSTUNREACH; + + case WIZCHIP_SOCKETS_ERR_NONETWORK: + return AVS_EHOSTUNREACH; + + case WIZCHIP_SOCKETS_ERR_UNSUPPORTED: + return AVS_ENOTSUP; + + case WIZCHIP_SOCKETS_ERR_STATE: + return AVS_EINVAL; + + default: + return AVS_UNKNOWN_ERROR; + } +} + +static avs_error_t wizchip_sockets_err_to_avs_error(int err) { + + return avs_errno(wizchip_sockets_err_to_avs_errno(err)); +} + +static int prepare_stringified_host_port(xcc_net_socket_impl_t *sock, + IP_Address_t *addr, + uint16_t port) { + + if (snprintf(sock->remote_host_str, sizeof(sock->remote_host_str), "%u.%u.%u.%u", + (unsigned int)addr->ip[0], (unsigned int)addr->ip[1], + (unsigned int)addr->ip[2], (unsigned int)addr->ip[3]) < 0 + || snprintf(sock->remote_port_str, sizeof(sock->remote_port_str), + "%" PRIu16, port) + < 0) { + return -1; + } + + return 0; +} + +#define GETHOSTBYNAME_RETRIES 20 + +static avs_error_t +net_connect(avs_net_socket_t *sock_, const char *host, const char *port) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + dns_query_result_t dns_res; + + assert(sock->fd < 0); + + if (sscanf(port, "%" PRIu16, &sock->remote_port) != 1) { + return avs_errno(AVS_EINVAL); + } + + for (int i = GETHOSTBYNAME_RETRIES; i > 0; i--) { + dns_res = wizchipDNSQuery(&WIZCHIP0, 15, host, &sock->remote_host); + + if (dns_res == DNS_QUERY_SUCCESS) + break; + + //LOG(WARNING, "Failed to resolve hostname. Result: %d Retries left: %d", (int) res, i); + } + + if (dns_res != DNS_QUERY_SUCCESS) { + return avs_errno(AVS_ECONNREFUSED); + } + + if (prepare_stringified_host_port(sock, &sock->remote_host, sock->remote_port)) { + return avs_errno(AVS_UNKNOWN_ERROR); + } + + int res; + + res = wizchipSocket(sock->address_family, sock->socktype, 0); + + if (res < 0) { + return wizchip_sockets_err_to_avs_error(res); + } + + sock->fd = res; + + res = wizchipConnect(sock->fd, &sock->remote_host, sock->remote_port); + + if (sock->socktype != WIZCHIP_TYPE_DGRAM && res < 0) { + return wizchip_sockets_err_to_avs_error(res); + } + + return AVS_OK; +} + +static avs_error_t +net_send(avs_net_socket_t *sock_, const void *buffer, size_t buffer_length) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + int res; + + if (sock->socktype == WIZCHIP_TYPE_DGRAM) { + res = wizchipSendTo(sock->fd, buffer, buffer_length, 0, &sock->remote_host, sock->remote_port); + } else { + res = wizchipSend(sock->fd, buffer, buffer_length, 0); + } + + if (res < 0 || res != (int)buffer_length) { + return avs_errno(AVS_EIO); + } + + sock->bytes_sent += res; + + return AVS_OK; +} + +avs_error_t net_send_to(avs_net_socket_t *sock_, const void *buffer, size_t buffer_length, + const char *host, const char *port) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + IP_Address_t remote_host; + uint16_t remote_port; + dns_query_result_t dns_res; + + if (sscanf(port, "%" PRIu16, &remote_port) != 1) { + return avs_errno(AVS_EINVAL); + } + + for (int i = GETHOSTBYNAME_RETRIES; i > 0; i--) { + dns_res = wizchipDNSQuery(&WIZCHIP0, 15, host, &remote_host); + + if (dns_res == DNS_QUERY_SUCCESS) + break; + + //LOG(WARNING, "Failed to resolve hostname. Result: %d Retries left: %d", (int) res, i); + } + + if (dns_res != DNS_QUERY_SUCCESS) { + return avs_errno(AVS_ECONNREFUSED); + } + + int res; + + res = wizchipSendTo(sock->fd, buffer, buffer_length, 0, &remote_host, remote_port); + + if (res < 0 || res != (int)buffer_length) { + return avs_errno(AVS_EIO); + } + + sock->bytes_sent += res; + + return AVS_OK; +} + +static int32_t recv_with_timeout(xcc_net_socket_impl_t *sock, + void *buffer, + int32_t buffer_length, + int64_t timeout) { + + uint32_t timeout_opt; + int32_t res; + + if (timeout == 0) { + if (sock->socktype == WIZCHIP_TYPE_DGRAM) { + res = wizchipRecvFrom(sock->fd, buffer, buffer_length, WIZCHIP_FLAG_MSG_DONTWAIT, + &sock->remote_host, sock->remote_port); + } else { + res = wizchipRecv(sock->fd, buffer, buffer_length, WIZCHIP_FLAG_MSG_DONTWAIT); + } + + if (res == WIZCHIP_SOCKETS_ERR_GENERAL) { + // behavior unique to WIZCHIP_MSG_DONTWAIT + res = AVS_ETIMEDOUT; + } + + return res; + } + + if (timeout < 0) { + timeout_opt = TIME_INFINITE; + } else { + timeout_opt = (uint32_t)timeout; + + if (timeout_opt != timeout) { + // accidentally truncated + return WIZCHIP_SOCKETS_ERR_GENERAL; + } + } + + res = wizchipSetSockopt(sock->fd, WIZCHIP_SOL_SOCKET, WIZCHIP_SO_RCVTIMEO, + &timeout_opt, sizeof(timeout_opt)); + + if (res) { + return res; + } + + if (sock->socktype == WIZCHIP_TYPE_DGRAM) { + res = wizchipRecvFrom(sock->fd, buffer, buffer_length, WIZCHIP_FLAG_MSG_WAIT, + &sock->remote_host, sock->remote_port); + } else { + res = wizchipRecv(sock->fd, buffer, buffer_length, WIZCHIP_FLAG_MSG_WAIT); + } + + return res; +} + +static avs_error_t net_receive(avs_net_socket_t *sock_, size_t *out_bytes_received, + void *buffer, size_t buffer_length) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + // assume we don't need support for zero-length datagrams + if (buffer_length == 0) { + *out_bytes_received = 0; + return AVS_OK; + } + + int64_t timeout_ms; + + if (avs_time_duration_to_scalar(&timeout_ms, AVS_TIME_MS, + sock->recv_timeout)) { + // treat AVS_TIME_DURATION_INVALID as infinite timeout + timeout_ms = -1; + } else if (timeout_ms < 0) { + timeout_ms = 0; + } + + int32_t res; + + res = recv_with_timeout(sock, buffer, buffer_length, timeout_ms); + + if (res < 0) { + return wizchip_sockets_err_to_avs_error(res); + } + + *out_bytes_received = res; + sock->bytes_received += res; + + return AVS_OK; +} + +static avs_error_t net_receive_from(avs_net_socket_t *sock_, size_t *out_bytes_received, + void *buffer, size_t buffer_length, + char *host, size_t host_size, char *port, size_t port_size) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + IP_Address_t remote_host; + uint16_t remote_port; + dns_query_result_t dns_res; + + (void)host_size; + (void)port_size; + + // assume we don't need support for zero-length datagrams + if (buffer_length == 0) { + *out_bytes_received = 0; + return AVS_OK; + } + + if (sscanf(port, "%" PRIu16, &remote_port) != 1) { + return avs_errno(AVS_EINVAL); + } + + for (int i = GETHOSTBYNAME_RETRIES; i > 0; i--) { + dns_res = wizchipDNSQuery(&WIZCHIP0, 15, host, &remote_host); + + if (dns_res == DNS_QUERY_SUCCESS) + break; + + //LOG(WARNING, "Failed to resolve hostname. Result: %d Retries left: %d", (int) res, i); + } + + if (dns_res != DNS_QUERY_SUCCESS) { + return avs_errno(AVS_ECONNREFUSED); + } + + int res; + + res = wizchipRecvFrom(sock->fd, buffer, buffer_length, 0, &remote_host, remote_port); + + if (res < 0) { + return wizchip_sockets_err_to_avs_error(res); + } + + *out_bytes_received = res; + sock->bytes_received += res; + + return AVS_OK; +} + +static avs_error_t net_bind(avs_net_socket_t *sock_, const char *address, const char *port) { + + (void)sock_; + (void)address; + (void)port; + + /** TODO: Implement net_bind. */ + return AVS_OK; +} + +static avs_error_t net_accept(avs_net_socket_t *server_socket, avs_net_socket_t *new_socket) { + + (void)server_socket; + (void)new_socket; + + /** TODO: Implement net_accept. */ + return AVS_OK; +} + +static avs_error_t net_close(avs_net_socket_t *sock_) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + avs_error_t err = AVS_OK; + + if (sock->fd >= 0) { + err = wizchip_sockets_err_to_avs_error(wizchipClose(sock->fd)); + sock->fd = -1; + } + + return err; +} + +static avs_error_t net_shutdown(avs_net_socket_t *sock_) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + avs_error_t err = AVS_OK; + + if (sock->fd >= 0) { + err = wizchip_sockets_err_to_avs_error(wizchipShutdown(sock->fd)); + } + + return err; +} + +static avs_error_t net_cleanup(avs_net_socket_t **sock_ptr) { + + avs_error_t err = AVS_OK; + + if (sock_ptr && *sock_ptr) { + err = net_close(*sock_ptr); + *sock_ptr = NULL; + memset(&wiznet_sock, 0, sizeof(wiznet_sock)); + } + + return err; +} + +static const void *net_system_socket(avs_net_socket_t *sock_) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + return sock->fd < 0 ? NULL : &sock->self; +} + +static avs_error_t net_remote_host(avs_net_socket_t *sock_, + char *out_buffer, + size_t out_buffer_size) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + if (out_buffer_size < strlen(sock->remote_host_str) + 1) { + return avs_errno(AVS_UNKNOWN_ERROR); + } + + strcpy(out_buffer, sock->remote_host_str); + + return AVS_OK; +} + +static avs_error_t net_remote_hostname(avs_net_socket_t *sock_, + char *out_buffer, size_t out_buffer_size) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + if (out_buffer_size < strlen(sock->remote_host_str) + 1) { + return avs_errno(AVS_UNKNOWN_ERROR); + } + + strcpy(out_buffer, sock->remote_host_str); + + return AVS_OK; +} + +static avs_error_t net_remote_port(avs_net_socket_t *sock_, + char *out_buffer, + size_t out_buffer_size) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + if (out_buffer_size < strlen(sock->remote_port_str) + 1) { + return avs_errno(AVS_UNKNOWN_ERROR); + } + + strcpy(out_buffer, sock->remote_port_str); + + return AVS_OK; +} + +static avs_error_t net_get_opt(avs_net_socket_t *sock_, + avs_net_socket_opt_key_t option_key, + avs_net_socket_opt_value_t *out_option_value) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + switch (option_key) { + case AVS_NET_SOCKET_OPT_RECV_TIMEOUT: + out_option_value->recv_timeout = sock->recv_timeout; + return AVS_OK; + + case AVS_NET_SOCKET_OPT_STATE: + out_option_value->state = sock->fd < 0 ? AVS_NET_SOCKET_STATE_CLOSED + : AVS_NET_SOCKET_STATE_CONNECTED; + return AVS_OK; + + case AVS_NET_SOCKET_OPT_MTU: + out_option_value->mtu = sock->forced_mtu; + return AVS_OK; + + case AVS_NET_SOCKET_OPT_INNER_MTU: + // this option only controls send and sendto calls, so use only max TX size + out_option_value->mtu = WIZCHIP_MAX_SOCKET_TX_DATA_SIZE; + return AVS_OK; + + case AVS_NET_SOCKET_HAS_BUFFERED_DATA: + out_option_value->flag = false; + return AVS_OK; + + case AVS_NET_SOCKET_OPT_BYTES_SENT: + out_option_value->bytes_sent = sock->bytes_sent; + return AVS_OK; + + case AVS_NET_SOCKET_OPT_BYTES_RECEIVED: + out_option_value->bytes_received = sock->bytes_received; + return AVS_OK; + + default: + return avs_errno(AVS_ENOTSUP); + } +} + +static avs_error_t net_set_opt(avs_net_socket_t *sock_, + avs_net_socket_opt_key_t option_key, + avs_net_socket_opt_value_t option_value) { + + xcc_net_socket_impl_t *sock = (xcc_net_socket_impl_t *)sock_; + + switch (option_key) { + case AVS_NET_SOCKET_OPT_RECV_TIMEOUT: + sock->recv_timeout = option_value.recv_timeout; + return AVS_OK; + + case AVS_NET_SOCKET_OPT_MTU: + sock->forced_mtu = option_value.mtu; + return AVS_OK; + + default: + return avs_errno(AVS_ENOTSUP); + } +} + +static const avs_net_socket_v_table_t NET_SOCKET_VTABLE = { + .connect = net_connect, + .decorate = NULL, + .send = net_send, + .send_to = net_send_to, + .receive = net_receive, + .receive_from = net_receive_from, + .bind = net_bind, + .accept = net_accept, + .close = net_close, + .shutdown = net_shutdown, + .cleanup = net_cleanup, + .get_system_socket = net_system_socket, + .get_interface_name = NULL, + .get_remote_host = net_remote_host, + .get_remote_hostname = net_remote_hostname, + .get_remote_port = net_remote_port, + .get_local_host = NULL, + .get_local_port = NULL, + .get_opt = net_get_opt, + .set_opt = net_set_opt +}; + +static avs_error_t +net_create_socket(avs_net_socket_t **socket_ptr, + const avs_net_socket_configuration_t *configuration, + int32_t socktype) { + + assert(socket_ptr); + assert(!*socket_ptr); + (void)configuration; + + xcc_net_socket_impl_t *socket = (xcc_net_socket_impl_t *)memset(&wiznet_sock, 0, + sizeof(wiznet_sock)); + + if (!socket) { + return avs_errno(AVS_ENOMEM); + } + + socket->operations = &NET_SOCKET_VTABLE; + socket->self = socket; + socket->address_family = configuration->address_family; + socket->forced_mtu = configuration->forced_mtu; + socket->socktype = socktype; + socket->fd = -1; + socket->recv_timeout = avs_time_duration_from_scalar(30, AVS_TIME_S); + *socket_ptr = (avs_net_socket_t *)socket; + return AVS_OK; +} + +avs_error_t _avs_net_create_udp_socket(avs_net_socket_t **socket_ptr, + const void *configuration) { + + return net_create_socket( + socket_ptr, (const avs_net_socket_configuration_t *)configuration, + WIZCHIP_TYPE_DGRAM); +} + +avs_error_t _avs_net_create_tcp_socket(avs_net_socket_t **socket_ptr, + const void *configuration) { + + return net_create_socket( + socket_ptr, (const avs_net_socket_configuration_t *)configuration, + WIZCHIP_TYPE_STREAM); +} diff --git a/os/various/anjay_bindings/compat/stdlib/avs_math_chibios.c b/os/various/anjay_bindings/compat/stdlib/avs_math_chibios.c new file mode 100644 index 0000000000..1abfe0984b --- /dev/null +++ b/os/various/anjay_bindings/compat/stdlib/avs_math_chibios.c @@ -0,0 +1,222 @@ +/* +Copyright © 2005-2020 Rich Felker, et al. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +/* Portions of this file are extracted from musl-1.2.4: + * src/internal/libm.h + * src/math/fmod.c + * src/math/trunc.c + * src/math/round.c + */ + + +#include +#include +#include + + +#ifndef fp_force_evalf +#define fp_force_evalf fp_force_evalf +static inline void fp_force_evalf(float x) +{ + volatile float y; + y = x; +} +#endif + +#ifndef fp_force_eval +#define fp_force_eval fp_force_eval +static inline void fp_force_eval(double x) +{ + volatile double y; + y = x; +} +#endif + +#ifndef fp_force_evall +#define fp_force_evall fp_force_evall +static inline void fp_force_evall(long double x) +{ + volatile long double y; + y = x; +} +#endif + +#define FORCE_EVAL(x) do { \ + if (sizeof(x) == sizeof(float)) { \ + fp_force_evalf(x); \ + } else if (sizeof(x) == sizeof(double)) { \ + fp_force_eval(x); \ + } else { \ + fp_force_evall(x); \ + } \ +} while(0) + + +double fmod(double x, double y) { + union { + double f; + uint64_t i; + } ux = {x}, uy = {y}; + int ex = ux.i >> 52 & 0x7ff; + int ey = uy.i >> 52 & 0x7ff; + int sx = ux.i >> 63; + uint64_t i; + + /* in the followings uxi should be ux.i, but then gcc wrongly adds */ + /* float load/store to inner loops ruining performance and code size */ + uint64_t uxi = ux.i; + + if (uy.i << 1 == 0 || isnan(y) || ex == 0x7ff) + return (x * y) / (x * y); + + if (uxi << 1 <= uy.i << 1) { + if (uxi << 1 == uy.i << 1) + return 0 * x; + + return x; + } + + /* normalize x and y */ + if (!ex) { + for (i = uxi << 12; i >> 63 == 0; ex--, i <<= 1); + + uxi <<= -ex + 1; + } else { + uxi &= -1ULL >> 12; + uxi |= 1ULL << 52; + } + + if (!ey) { + for (i = uy.i << 12; i >> 63 == 0; ey--, i <<= 1); + + uy.i <<= -ey + 1; + } else { + uy.i &= -1ULL >> 12; + uy.i |= 1ULL << 52; + } + + /* x mod y */ + for (; ex > ey; ex--) { + i = uxi - uy.i; + + if (i >> 63 == 0) { + if (i == 0) + return 0 * x; + + uxi = i; + } + + uxi <<= 1; + } + + i = uxi - uy.i; + + if (i >> 63 == 0) { + if (i == 0) + return 0 * x; + + uxi = i; + } + + for (; uxi >> 52 == 0; uxi <<= 1, ex--); + + /* scale result */ + if (ex > 0) { + uxi -= 1ULL << 52; + uxi |= (uint64_t)ex << 52; + } else { + uxi >>= -ex + 1; + } + + uxi |= (uint64_t)sx << 63; + ux.i = uxi; + return ux.f; +} + + +double trunc(double x) { + union { + double f; + uint64_t i; + } u = {x}; + int e = (int)(u.i >> 52 & 0x7ff) - 0x3ff + 12; + uint64_t m; + + if (e >= 52 + 12) + return x; + + if (e < 12) + e = 1; + + m = -1ULL >> e; + + if ((u.i & m) == 0) + return x; + + FORCE_EVAL(x + 0x1p120f); + u.i &= ~m; + return u.f; +} + +#if FLT_EVAL_METHOD==0 || FLT_EVAL_METHOD==1 +#define EPS DBL_EPSILON +#elif FLT_EVAL_METHOD==2 +#define EPS LDBL_EPSILON +#endif +static const double_t toint = 1 / EPS; + + +double round(double x) { + union { + double f; + uint64_t i; + } u = {x}; + int e = u.i >> 52 & 0x7ff; + double_t y; + + if (e >= 0x3ff + 52) + return x; + + if (u.i >> 63) + x = -x; + + if (e < 0x3ff - 1) { + /* raise inexact if x!=0 */ + FORCE_EVAL(x + toint); + return 0 * u.f; + } + + y = x + toint - toint - x; + + if (y > 0.5) + y = y + x - 1; + else if (y <= -0.5) + y = y + x + 1; + else + y = y + x; + + if (u.i >> 63) + y = -y; + + return y; +} diff --git a/os/various/anjay_bindings/compat/stdlib/avs_memory_chibios.c b/os/various/anjay_bindings/compat/stdlib/avs_memory_chibios.c new file mode 100644 index 0000000000..38351a488d --- /dev/null +++ b/os/various/anjay_bindings/compat/stdlib/avs_memory_chibios.c @@ -0,0 +1,94 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#define AVS_UTILS_COMPAT_STDLIB_MEMORY_C +#include + +#if defined(AVS_COMMONS_WITH_AVS_UTILS) \ + && !defined(AVS_COMMONS_UTILS_WITH_STANDARD_ALLOCATOR) + +#include + +#include +#include + +VISIBILITY_SOURCE_BEGIN + +#ifndef AVS_HEAP_MAX_BUFFER_SIZE +#define AVS_HEAP_MAX_BUFFER_SIZE 16*1024u +#endif + +static memory_heap_t avs_heap; +static uint8_t avs_heap_buf[AVS_HEAP_MAX_BUFFER_SIZE]; + +void avs_heap_init(void) { + + chHeapObjectInit(&avs_heap, avs_heap_buf, sizeof(avs_heap_buf)); +} + +size_t avs_heap_get_free(void) { + size_t total_free; + size_t largest; + size_t fragments = chHeapStatus(&avs_heap, &total_free, &largest); + + (void)fragments; + (void)largest; + + return total_free; +} + +void *avs_malloc(size_t size) { + + return chHeapAlloc(&avs_heap, size); +} + +void avs_free(void *ptr) { + + if (ptr == NULL) + return; + + chHeapFree(ptr); +} + +void *avs_calloc(size_t nmemb, size_t size) { + + void *ptr; + + const size_t total = nmemb * size; + + ptr = chHeapAlloc(&avs_heap, total); + + if (!ptr) + return NULL; + + memset(ptr, 0, total); + return ptr; +} + +void *avs_realloc(void *ptr, size_t size) { + + void *p = avs_malloc(size); + + if (!p) + return NULL; + + memcpy(p, ptr, size); + chHeapFree(ptr); + return p; +} + +#endif // defined(AVS_COMMONS_WITH_AVS_UTILS) && +// !defined(AVS_COMMONS_UTILS_WITH_STANDARD_ALLOCATOR) diff --git a/os/various/anjay_bindings/compat/stdlib/avs_memory_chibios.h b/os/various/anjay_bindings/compat/stdlib/avs_memory_chibios.h new file mode 100644 index 0000000000..af4d71be40 --- /dev/null +++ b/os/various/anjay_bindings/compat/stdlib/avs_memory_chibios.h @@ -0,0 +1,24 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef AVS_MEMORY_CHIBIOS_H +#define AVS_MEMORY_CHIBIOS_H + +void avs_heap_init(void); + +size_t avs_heap_get_free(void); + +#endif /* AVS_MEMORY_CHIBIOS_H */ diff --git a/os/various/anjay_bindings/compat/stdlib/avs_time_chibios.c b/os/various/anjay_bindings/compat/stdlib/avs_time_chibios.c new file mode 100644 index 0000000000..15c2844049 --- /dev/null +++ b/os/various/anjay_bindings/compat/stdlib/avs_time_chibios.c @@ -0,0 +1,67 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/* + * The avs_time_real_now() function should return the current real time, + * i.e. the amount of time that passed since January 1st, 1970, midnight + * UTC (the Unix epoch). + */ +avs_time_real_t avs_time_real_now(void) { + + avs_time_real_t result; + + const systime_t now = chVTGetSystemTime(); + + /* Using TIME_I2S() is impossible because of rounding up to the next seconds. */ + result.since_real_epoch.seconds = (time_conv_t)now / (time_conv_t)CH_CFG_ST_FREQUENCY; + result.since_real_epoch.nanoseconds = (time_conv_t)now - (time_conv_t)( + result.since_real_epoch.seconds) * (time_conv_t)CH_CFG_ST_FREQUENCY; + result.since_real_epoch.nanoseconds = TIME_I2US(result.since_real_epoch.nanoseconds) * + (time_conv_t)1000; + + return result; +} + +/* + * The avs_time_monotonic_now() function should return the current monotonic time, + * i.e. the amount of time that passed since some epoch - it might be any point in time, + * but needs to be stable at least throughout the lifetime of the process - different + * epochs might be used for different launches of the application. + * + * System boot time is often used as an epoch for the monotonic clock. + * If the real-time clock is considered stable, and not reset while the application is + * running, it may be also used as the monotonic clock. +*/ +avs_time_monotonic_t avs_time_monotonic_now(void) { + + avs_time_monotonic_t result; + + const systime_t now = chVTGetSystemTime(); + + /* Using TIME_I2S() is impossible because of rounding up to the next seconds. */ + result.since_monotonic_epoch.seconds = (time_conv_t)now / (time_conv_t)CH_CFG_ST_FREQUENCY; + result.since_monotonic_epoch.nanoseconds = (time_conv_t)now - (time_conv_t)( + result.since_monotonic_epoch.seconds) * (time_conv_t)CH_CFG_ST_FREQUENCY; + result.since_monotonic_epoch.nanoseconds = TIME_I2US(result.since_monotonic_epoch.nanoseconds) * + (time_conv_t)1000; + + return result; +} diff --git a/os/various/anjay_bindings/compat/threading/avs_cmsis_os_condvar.c b/os/various/anjay_bindings/compat/threading/avs_cmsis_os_condvar.c new file mode 100644 index 0000000000..f0b0ce2672 --- /dev/null +++ b/os/various/anjay_bindings/compat/threading/avs_cmsis_os_condvar.c @@ -0,0 +1,147 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include + +#include "avs_cmsis_os_structs.h" + +#include + +// Code partially inspired by: +// https://github.com/yaahallo/nachos/blob/master/threads/Condition.java +// The Nachos project is the code examples for the Operating Systems course on +// the University of California, see: +// https://eng.ucmerced.edu/crf/engineering/cse-150-operating-systems/ +// Copyright (c) 1992-2001 The Regents of the University of California. +// All rights reserved. Used under BSD license +// (https://github.com/yaahallo/nachos/blob/master/README) + +int avs_condvar_create(avs_condvar_t **out_condvar) { + AVS_ASSERT(!*out_condvar, + "possible attempt to reinitialize a condition variable"); + + *out_condvar = (avs_condvar_t *) avs_calloc(1, sizeof(avs_condvar_t)); + + if (!*out_condvar) { + return -1; + } + + if (_avs_mutex_init(&(*out_condvar)->waiters_mutex)) { + avs_free(*out_condvar); + *out_condvar = NULL; + return -1; + } + + return 0; +} + +int avs_condvar_notify_all(avs_condvar_t *condvar) { + avs_mutex_lock(&condvar->waiters_mutex); + condvar_waiter_node_t *waiter = condvar->first_waiter; + + while (waiter) { + // wake up the waiter + atomic_flag_clear(&waiter->waiting); + + waiter = waiter->next; + } + + avs_mutex_unlock(&condvar->waiters_mutex); + return 0; +} + +static void insert_new_waiter(avs_condvar_t *condvar, + condvar_waiter_node_t *waiter) { + avs_mutex_lock(&condvar->waiters_mutex); + + // Initialize the waiting flag to true + atomic_flag_clear(&waiter->waiting); + bool value = atomic_flag_test_and_set(&waiter->waiting); + assert(!value); + (void) value; + + // Insert waiter as the first element on the list + waiter->next = condvar->first_waiter; + condvar->first_waiter = waiter; + + avs_mutex_unlock(&condvar->waiters_mutex); +} + +static void remove_waiter(avs_condvar_t *condvar, + condvar_waiter_node_t *waiter) { + avs_mutex_lock(&condvar->waiters_mutex); + + condvar_waiter_node_t **waiter_node_ptr = &condvar->first_waiter; + + while (*waiter_node_ptr && *waiter_node_ptr != waiter) { + waiter_node_ptr = &(*waiter_node_ptr)->next; + } + + AVS_ASSERT(*waiter_node_ptr == waiter, + "waiter node inexplicably disappeared from condition variable"); + + if (*waiter_node_ptr == waiter) { + // detach it + *waiter_node_ptr = (*waiter_node_ptr)->next; + } + + avs_mutex_unlock(&condvar->waiters_mutex); +} + +int avs_condvar_wait(avs_condvar_t *condvar, + avs_mutex_t *mutex, + avs_time_monotonic_t deadline) { + // Precondition: mutex is locked by the current thread + // although we can't check if it's the current thread that locked it :( + + bool use_deadline = avs_time_monotonic_valid(deadline); + bool flag_value; + condvar_waiter_node_t waiter; + insert_new_waiter(condvar, &waiter); + + avs_mutex_unlock(mutex); + + do { + flag_value = atomic_flag_test_and_set(&waiter.waiting); + } while (flag_value + && (!use_deadline + || avs_time_monotonic_before(avs_time_monotonic_now(), + deadline))); + + avs_mutex_lock(mutex); + + remove_waiter(condvar, &waiter); + + // flag_value == 0 -> it means it was cleared, so we've been woken up + // flag_value == 1 -> it mean we haven't, so timeout occurred + return flag_value ? AVS_CONDVAR_TIMEOUT : 0; +} + +void avs_condvar_cleanup(avs_condvar_t **condvar) { + if (!*condvar) { + return; + } + + AVS_ASSERT(!(*condvar)->first_waiter, + "attempted to cleanup a condition variable some thread is " + "waiting on"); + + _avs_mutex_destroy(&(*condvar)->waiters_mutex); + avs_free(*condvar); + *condvar = NULL; +} diff --git a/os/various/anjay_bindings/compat/threading/avs_cmsis_os_init_once.c b/os/various/anjay_bindings/compat/threading/avs_cmsis_os_init_once.c new file mode 100644 index 0000000000..cda8744651 --- /dev/null +++ b/os/various/anjay_bindings/compat/threading/avs_cmsis_os_init_once.c @@ -0,0 +1,64 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include +#include + +#include +#include + +AVS_STATIC_ASSERT(sizeof(avs_init_once_handle_t) >= sizeof(atomic_int), + avs_init_once_handle_too_small); +AVS_STATIC_ASSERT(AVS_ALIGNOF(avs_init_once_handle_t) + >= AVS_ALIGNOF(atomic_int), + avs_init_once_alignment_incompatible); + +enum init_state { INIT_NOT_STARTED, INIT_IN_PROGRESS, INIT_DONE }; + +int avs_init_once(volatile avs_init_once_handle_t *handle, + avs_init_once_func_t *func, + void *func_arg) { + volatile atomic_int *state = (volatile atomic_int *) handle; + + int expected; + + do { + expected = INIT_NOT_STARTED; + /* + * `*_weak` version may fail spuriously (return false when + * *state == expected); this does not matter to us, because we check + * it in a loop anyway, and according to cppreference it may have + * better performance than `*_strong` variant on some platforms. + */ + } while (!atomic_compare_exchange_weak(state, &expected, INIT_IN_PROGRESS) + && expected != INIT_DONE); + + int result = 0; + + if (expected != INIT_DONE) { + result = func(func_arg); + + if (result) { + atomic_store(state, INIT_NOT_STARTED); + } else { + atomic_store(state, INIT_DONE); + } + } + + return result; +} diff --git a/os/various/anjay_bindings/compat/threading/avs_cmsis_os_structs.h b/os/various/anjay_bindings/compat/threading/avs_cmsis_os_structs.h new file mode 100644 index 0000000000..d804744775 --- /dev/null +++ b/os/various/anjay_bindings/compat/threading/avs_cmsis_os_structs.h @@ -0,0 +1,48 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef AVS_CMSIS_OS_STRUCTS_H +#define AVS_CMSIS_OS_STRUCTS_H + +#include +#include + +#include + +#include "cmsis_os.h" + +struct avs_mutex { + osMutexDef_t def; + osMutexId id; +}; + +// we are not using AVS_LIST because we want to use stack allocation +typedef struct condvar_waiter_node_struct { + volatile atomic_flag waiting; + struct condvar_waiter_node_struct *next; +} condvar_waiter_node_t; + +struct avs_condvar { + // first_waiter and every condvar_waiter_node_t::next are only accessed when + // waiters_mutex is locked + avs_mutex_t waiters_mutex; + condvar_waiter_node_t *first_waiter; +}; + +int _avs_mutex_init(avs_mutex_t *mutex); +void _avs_mutex_destroy(avs_mutex_t *mutex); + +#endif // AVS_CMSIS_OS_STRUCTS_H diff --git a/os/various/anjay_bindings/compat/threading/avs_csmis_os_mutex.c b/os/various/anjay_bindings/compat/threading/avs_csmis_os_mutex.c new file mode 100644 index 0000000000..9f1b8b2036 --- /dev/null +++ b/os/various/anjay_bindings/compat/threading/avs_csmis_os_mutex.c @@ -0,0 +1,78 @@ +/* + * Copyright 2020-2023 AVSystem + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include + +#include "avs_cmsis_os_structs.h" + +int _avs_mutex_init(avs_mutex_t *mutex) { + + mutex->id = osMutexCreate(&mutex->def); + + if (!mutex->id) { + return -1; + } + + return 0; +} + +int avs_mutex_create(avs_mutex_t **out_mutex) { + AVS_ASSERT(!*out_mutex, "possible attempt to reinitialize a mutex"); + + *out_mutex = (avs_mutex_t *) avs_calloc(1, sizeof(avs_mutex_t)); + + if (!*out_mutex) { + return -1; + } + + if (_avs_mutex_init(*out_mutex)) { + avs_free(*out_mutex); + *out_mutex = NULL; + return -1; + } + + return 0; +} + +int avs_mutex_lock(avs_mutex_t *mutex) { + return osMutexWait(mutex->id, osWaitForever) == osOK ? 0 : -1; +} + +int avs_mutex_try_lock(avs_mutex_t *mutex) { + return osMutexWait(mutex->id, 0) ? 0 : 1; +} + +int avs_mutex_unlock(avs_mutex_t *mutex) { + return osMutexRelease(mutex->id) == osOK ? 0 : -1; +} + +void _avs_mutex_destroy(avs_mutex_t *mutex) { + osStatus ret = osMutexDelete(mutex->id); + (void) ret; + AVS_ASSERT(ret == osOK, "osMutexDelete failed"); +} + +void avs_mutex_cleanup(avs_mutex_t **mutex) { + if (!*mutex) { + return; + } + + _avs_mutex_destroy(*mutex); + avs_free(*mutex); + *mutex = NULL; +} diff --git a/os/various/anjay_bindings/readme.txt b/os/various/anjay_bindings/readme.txt new file mode 100644 index 0000000000..7cc5c02613 --- /dev/null +++ b/os/various/anjay_bindings/readme.txt @@ -0,0 +1,2 @@ +See ChibiOS-Contrib/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS +for how to use it. diff --git a/os/various/devices_lib/ethernet/hal_mac_lld.h b/os/various/devices_lib/ethernet/hal_mac_lld.h new file mode 100644 index 0000000000..9cd1736745 --- /dev/null +++ b/os/various/devices_lib/ethernet/hal_mac_lld.h @@ -0,0 +1,207 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPI_MACv1/hal_mac_lld.h + * @brief SPI low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef HAL_MAC_LLD_H +#define HAL_MAC_LLD_H + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY FALSE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief MAC driver enable switch. + * @details If set to @p TRUE the support for MAC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_MAC_USE_MAC1) || defined(__DOXYGEN__) + #define PLATFORM_MAC_USE_MAC1 TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_SPI == FALSE + #error "ETH driver requires HAL_USE_SPI" +#endif + +#if SPI_USE_WAIT == FALSE + #error "ETH driver requires SPI_USE_WAIT" +#endif + +#define ETH_USE_MUTUAL_EXCLUSION SPI_USE_MUTUAL_EXCLUSION + +#if HAL_USE_PAL == FALSE + #error "ETH driver requires HAL_USE_PAL" +#endif + +#define ETH_USE_CALLBACKS PAL_USE_CALLBACKS + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#define ETH_PHY_CONF_BY_HW (eth_phy_conf_t)0 +#define ETH_PHY_CONF_BY_SW (eth_phy_conf_t)1 + +#define ETH_PHY_DUPLEX_HALF (eth_phy_duplex_t)0 +#define ETH_PHY_DUPLEX_FULL (eth_phy_duplex_t)1 + +#define ETH_PHY_MODE_MANUAL (eth_phy_mode_t)0 +#define ETH_PHY_MODE_AUTO (eth_phy_mode_t)1 + +#define ETH_PHY_SPEED_10 (eth_phy_speed_t)0 +#define ETH_PHY_SPEED_100 (eth_phy_speed_t)1 +#define ETH_PHY_SPEED_1000 (eth_phy_speed_t)2 + +#define ETH_PHY_LINK_DOWN (eth_phy_link_state_t)0 +#define ETH_PHY_LINK_UP (eth_phy_link_state_t)1 +#define ETH_PHY_LINK_UNKNOWN (eth_phy_link_state_t)-1 + +typedef int32_t eth_phy_conf_t; + +typedef int32_t eth_phy_duplex_t; + +typedef int32_t eth_phy_mode_t; + +typedef int32_t eth_phy_speed_t; + +typedef int32_t eth_phy_link_state_t; + +typedef struct { + void *driver; /* SPIDriver */ + + const void *config; /* SPIConfig */ + + uint16_t reset_trc_delay_ms; + + uint16_t reset_tpl_delay_ms; + + ioline_t reset_line; + +#if ETH_USE_CALLBACKS == TRUE + ioline_t irq_line; +#endif +} ETHSPIConfig; + +typedef struct { + eth_phy_conf_t conf_by; + + eth_phy_mode_t mode; + + eth_phy_speed_t speed; + + eth_phy_duplex_t duplex; +} ETHPhyConfig; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the MAC driver structure. + */ +#define mac_lld_driver_fields \ + const ETHSPIConfig *spi_config; \ + const ETHPhyConfig *phy_config; \ + bool irq_unhandled + +/** + * @brief Low level fields of the MAC configuration structure. + */ +#define mac_lld_config_fields \ + /* MAC address.*/ \ + const uint8_t *mac_address + +/** + * @brief Low level fields of the MAC transmit descriptor structure. + */ +#define mac_lld_transmit_descriptor_fields \ + MACDriver *macp + +/** + * @brief Low level fields of the MAC receive descriptor structure. + */ +#define mac_lld_receive_descriptor_fields \ + MACDriver *macp + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (PLATFORM_MAC_USE_MAC1 == TRUE) && !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void mac_lld_init(void); +void mac_lld_start(MACDriver *macp); +void mac_lld_stop(MACDriver *macp); +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); +bool mac_lld_poll_link_status(MACDriver *macp); +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); +#if MAC_USE_ZERO_COPY == TRUE +uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); +const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* HAL_MAC_LLD_H */ + +/** @} */ diff --git a/os/various/devices_lib/ethernet/w5500_lld.c b/os/various/devices_lib/ethernet/w5500_lld.c new file mode 100644 index 0000000000..4ed734b69a --- /dev/null +++ b/os/various/devices_lib/ethernet/w5500_lld.c @@ -0,0 +1,822 @@ +/* + W5500 for ChibiOS/RT - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "hal_mac_lld.h" +#include "w5500_lld.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define W5500_MSB(n) (((n) >> 8) & 0xFF) +#define W5500_LSB(n) (((n) >> 0) & 0xFF) + +#define W5500_RX_FRAME_HEADER_SIZE 2 + +#define W5500_RWB_READ (0x00 << 2) //< Read Access Mode Bit +#define W5500_RWB_WRITE (0x01 << 2) //< Write Access Mode Bit + +#define W5500P_BSB_COMMON (block_select_t)(0x00 << 3) //< Select Common Register +#define W5500P_BSB_SOCKET (block_select_t)(0x01 << 3) //< Select Socket 0 Register +#define W5500P_BSB_TX_BUF (block_select_t)(0x02 << 3) //< Select TX buffer +#define W5500P_BSB_RX_BUF (block_select_t)(0x03 << 3) //< Select RX buffer + +#define W5500_IO_COMMON_BASE 0x0000 + +#define W5500_IO_MR (io_address_t)(W5500_IO_COMMON_BASE + 0x0000) +#define W5500_MR_RST (1 << 7) + +#define W5500_IO_SNCR (io_address_t)(W5500_IO_COMMON_BASE + 0x0001) + +#define W5500_IO_SHAR (io_address_t)(W5500_IO_COMMON_BASE + 0x0009) + +#define W5500_IO_SIMR (io_address_t)(W5500_IO_COMMON_BASE + 0x0018) +#define W5500_SIMR_S0_INT (1 << 0) + +#define W5500_IO_PHYCFGR (io_address_t)(W5500_IO_COMMON_BASE + 0x002E) +#define W5500_PHYCFGR_RST (1 << 7) +#define W5500_PHYCFGR_OPMD (1 << 6) +#define W5500_PHYCFGR_OPMDC_AUTONEGOTIATION (1 << 5) +#define W5500_PHYCFGR_OPMDC_SPEED_100 (1 << 4) +#define W5500_PHYCFGR_OPMDC_FULL_DUPLEX (1 << 3) +#define W5500_PHYCFGR_PWR_DOWN ((1 << 5) | (1 << 4) | (0 << 3)) +#define W5500_PHYCFGR_STATUS_DPX_FULL (1 << 2) +#define W5500_PHYCFGR_STATUS_SPD_100 (1 << 1) +#define W5500_PHYCFGR_STATUS_LNK_UP (1 << 0) + +#define W5500_IO_VERSIONR (io_address_t)(W5500_IO_COMMON_BASE + 0x0039) + + +#define W5500_IO_SOCKET_BASE 0x0000 +#define W5500_IO_SN_MR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0000) +#define W5500_SN_MR_PROTO_MASK 0x0F +#define W5500_SN_MR_PROTO_TCP (1 << 0) +#define W5500_SN_MR_PROTO_UDP (1 << 1) +#define W5500_SN_MR_PROTO_MACRAW (1 << 2) + +#define W5500_IO_SN_CR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0001) +#define W5500_SN_CR_OPEN (0x01) +#define W5500_SN_CR_CLOSE (0x10) +#define W5500_SN_CR_SEND (0x20) +#define W5500_SN_CR_RECV (0x40) + +#define W5500_IO_SN_IR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0002) +#define W5500_SN_IR_CON (1 << 0) +#define W5500_SN_IR_DISCON (1 << 1) +#define W5500_SN_IR_RECV (1 << 2) +#define W5500_SN_IR_TIMEOUT (1 << 3) +#define W5500_SN_IR_SEND_OK (1 << 4) +#define W5500_SN_IR_CLEAR_ALL (W5500_SN_IR_CON | W5500_SN_IR_DISCON | W5500_SN_IR_RECV | \ + W5500_SN_IR_TIMEOUT | W5500_SN_IR_SEND_OK) + +#define W5500_IO_SN_SR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0003) +#define W5500_SN_SR_SOCK_CLOSED (0x00) +#define W5500_SN_SR_SOCK_MACRAW (0x42) + +#define W5500_IO_SN_RXBUF_SIZE (io_address_t)(W5500_IO_SOCKET_BASE + 0x001E) +#define W5500_IO_SN_TXBUF_SIZE (io_address_t)(W5500_IO_SOCKET_BASE + 0x001F) +#define W5500_IO_SN_TX_FSR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0020) +#define W5500_IO_SN_TX_WR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0024) +#define W5500_IO_SN_RX_RSR (io_address_t)(W5500_IO_SOCKET_BASE + 0x0026) +#define W5500_IO_SN_RX_RD (io_address_t)(W5500_IO_SOCKET_BASE + 0x0028) + +#define W5500_IO_SN_IMR (io_address_t)(W5500_IO_SOCKET_BASE + 0x002C) +#define W5500_SN_IMR_CON (1 << 0) +#define W5500_SN_IMR_DISCON (1 << 1) +#define W5500_SN_IMR_RECV (1 << 2) +#define W5500_SN_IMR_TIMEOUT (1 << 3) +#define W5500_SN_IMR_SEND_OK (1 << 4) + + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +typedef uint16_t io_address_t; +typedef uint8_t block_select_t; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static uint8_t w5500_read8(SPIDriver *spi, io_address_t address, block_select_t block); +static void w5500_write8(SPIDriver *spi, io_address_t address, block_select_t block, uint8_t val); + +#if ETH_USE_CALLBACKS == TRUE +/** + * @brief Interrupt handler. + * + * @isr + */ +static void w5500_lld_isr(void *arg) { + + chSysLockFromISR(); + MACDriver *macp = arg; + macp->irq_unhandled = true; + chEvtBroadcastFlagsI(macGetEventSource(macp), MAC_FLAGS_RX); + chSysUnlockFromISR(); +} +#endif + + +static void w5500_lld_enable_isr(MACDriver *macp) { +#if ETH_USE_CALLBACKS == TRUE + chSysLock(); + + SPIDriver *spi = macp->spi_config->driver; + + palSetLineCallback(macp->spi_config->irq_line, w5500_lld_isr, macp); + palEnableLineEvent(macp->spi_config->irq_line, PAL_EVENT_MODE_FALLING_EDGE); + + /* Unmask RECV interrupt. */ + w5500_write8(spi, W5500_IO_SN_IMR, W5500P_BSB_SOCKET, W5500_SN_IMR_RECV); + + /* Clear all pending interrupts. */ + w5500_write8(spi, W5500_IO_SN_IR, W5500P_BSB_SOCKET, W5500_SN_IR_CLEAR_ALL); + + /* Enable RECV interrupt. */ + w5500_write8(spi, W5500_IO_SIMR, W5500P_BSB_COMMON, W5500_SIMR_S0_INT); + + chSysUnlock(); +#else + (void)macp; +#endif +} + + +static void w5500_lld_disable_isr(MACDriver *macp) { +#if ETH_USE_CALLBACKS == TRUE + chSysLock(); + + SPIDriver *spi = macp->spi_config->driver; + + /* Mask interrupts. */ + w5500_write8(spi, W5500_IO_SN_IMR, W5500P_BSB_SOCKET, 0); + + /* Clear all pending interrupts. */ + w5500_write8(spi, W5500_IO_SN_IR, W5500P_BSB_SOCKET, W5500_SN_IR_CLEAR_ALL); + + /* Disable interrupts. */ + w5500_write8(spi, W5500_IO_SIMR, W5500P_BSB_COMMON, 0); + + palDisableLineEvent(macp->spi_config->irq_line); + palSetLineCallback(macp->spi_config->irq_line, NULL, NULL); + + chSysUnlock(); +#else + (void)macp; +#endif +} + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void w5500_read(SPIDriver *spi, io_address_t address, block_select_t block, size_t buflen, + void *buf) { + + const uint8_t cmd[3] = { + W5500_MSB(address), + W5500_LSB(address), + block | W5500_RWB_READ + }; + +#if ETH_USE_MUTUAL_EXCLUSION == TRUE + spiAcquireBus(spi); +#endif + + spiSelect(spi); + spiSend(spi, sizeof(cmd), cmd); + spiReceive(spi, buflen, buf); + spiUnselect(spi); + +#if ETH_USE_MUTUAL_EXCLUSION == TRUE + spiReleaseBus(spi); +#endif +} + + +static void w5500_write(SPIDriver *spi, io_address_t address, block_select_t block, size_t buflen, + const void *buf) { + + const uint8_t cmd[3] = { + W5500_MSB(address), + W5500_LSB(address), + block | W5500_RWB_WRITE + }; + +#if ETH_USE_MUTUAL_EXCLUSION == TRUE + spiAcquireBus(spi); +#endif + + spiSelect(spi); + spiSend(spi, sizeof(cmd), cmd); + + if (buf && buflen > 0) { + spiSend(spi, buflen, buf); + } + + spiUnselect(spi); + +#if ETH_USE_MUTUAL_EXCLUSION == TRUE + spiReleaseBus(spi); +#endif +} + + +uint8_t w5500_read8(SPIDriver *spi, io_address_t address, block_select_t block) { + uint8_t ret; + + w5500_read(spi, address, block, sizeof(ret), &ret); + return ret; +} + + +static uint16_t w5500_read16(SPIDriver *spi, io_address_t address, block_select_t block) { + uint16_t prev, last; + + last = ((uint16_t)w5500_read8(spi, address + 0, block) << 8) | + ((uint16_t)w5500_read8(spi, address + 1, block) << 0); + + do { + prev = last; + last = ((uint16_t)w5500_read8(spi, address + 0, block) << 8) | + ((uint16_t)w5500_read8(spi, address + 1, block) << 0); + } while (prev != last); + + return last; +} + + +void w5500_write8(SPIDriver *spi, io_address_t address, block_select_t block, uint8_t val) { + w5500_write(spi, address, block, sizeof(val), &val); +} + + +static void w5500_write16(SPIDriver *spi, io_address_t address, block_select_t block, + uint16_t val) { + w5500_write8(spi, address + 0, block, W5500_MSB(val)); + w5500_write8(spi, address + 1, block, W5500_LSB(val)); +} + + +static void w5500_lld_hw_reset(const ETHSPIConfig *spicfg) { + palClearLine(spicfg->reset_line); + chThdSleepMilliseconds(spicfg->reset_trc_delay_ms); + + palSetLine(spicfg->reset_line); + chThdSleepMilliseconds(spicfg->reset_tpl_delay_ms); +} + + +#if 0 +static void w5500_lld_sw_reset(SPIDriver *spi) { + w5500_write8(spi, W5500_IO_MR, W5500P_BSB_COMMON, W5500_MR_RST); +} + + +static uint8_t w5500_lld_get_version(SPIDriver *spi) { + return w5500_read8(spi, W5500_IO_VERSIONR, W5500P_BSB_COMMON); +} + + +static bool w5500_lld_probe(MACDriver *macp) { + + uint8_t chip_version; + SPIDriver *spi = macp->spi_config->driver; + + chip_version = w5500_lld_get_version(spi); + + if (chip_version == W5500_CHIP_ID) + return true; + + return false; +} + + +static void w5500_lld_get_phy_mode(MACDriver *macp, ETHPhyConfig *chipcfg) { + SPIDriver *spi = macp->spi_config->driver; + + uint8_t phycfg = w5500_read8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON); + + if (phycfg & W5500_PHYCFGR_OPMD) { + chipcfg->conf_by = ETH_PHY_CONF_BY_SW; + } else { + chipcfg->conf_by = ETH_PHY_CONF_BY_HW; + } + + if (phycfg & W5500_PHYCFGR_OPMDC_FULL_DUPLEX) { + chipcfg->duplex = ETH_PHY_DUPLEX_FULL; + } else { + chipcfg->duplex = ETH_PHY_DUPLEX_HALF; + } + + if (phycfg & W5500_PHYCFGR_OPMDC_SPEED_100) { + chipcfg->speed = ETH_PHY_SPEED_100; + } else { + chipcfg->speed = ETH_PHY_SPEED_10; + } + + if (phycfg & W5500_PHYCFGR_OPMDC_AUTONEGOTIATION) { + chipcfg->mode = ETH_PHY_MODE_AUTO; + } else { + chipcfg->mode = ETH_PHY_MODE_MANUAL; + } +} +#endif + + +static void w5500_lld_clear_pending_irqs(SPIDriver *spi) { + + w5500_write8(spi, W5500_IO_SN_IR, W5500P_BSB_SOCKET, W5500_SN_IR_CLEAR_ALL); +} + + +static void w5500_lld_set_mac_address(SPIDriver *spi, const uint8_t mac[6] ) { + + w5500_write(spi, W5500_IO_SHAR, W5500P_BSB_COMMON, 6, mac); +} + + +static void w5500_lld_pwr_down(SPIDriver *spi) { + uint8_t phycfg; + + phycfg = w5500_read8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON); + phycfg |= W5500_PHYCFGR_PWR_DOWN; + w5500_write8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON, phycfg); +} + + +static void w5500_lld_set_tx_buffer_size(SPIDriver *spi, size_t buf_size_kb) { + w5500_write8(spi, W5500_IO_SN_TXBUF_SIZE, W5500P_BSB_SOCKET, buf_size_kb); +} + + +static void w5500_lld_set_rx_buffer_size(SPIDriver *spi, size_t buf_size_kb) { + + w5500_write8(spi, W5500_IO_SN_RXBUF_SIZE, W5500P_BSB_SOCKET, buf_size_kb); +} + + +static void w5500_lld_set_socket_mode_raw(SPIDriver *spi) { + uint8_t tmp = w5500_read8(spi, W5500_IO_SN_MR, W5500P_BSB_SOCKET); + + tmp &= ~W5500_SN_MR_PROTO_MASK; + tmp |= W5500_SN_MR_PROTO_MACRAW; + w5500_write8(spi, W5500_IO_SN_MR, W5500P_BSB_SOCKET, W5500_SN_MR_PROTO_MACRAW); +} + + +static void w5500_lld_open_socket(SPIDriver *spi) { + + w5500_write8(spi, W5500_IO_SN_CR, W5500P_BSB_SOCKET, W5500_SN_CR_OPEN); +} + + +static void w5500_lld_close_socket(SPIDriver *spi) { + + w5500_write8(spi, W5500_IO_SN_CR, W5500P_BSB_SOCKET, W5500_SN_CR_CLOSE); +} + + +static void w5500_lld_set_phy_mode(MACDriver *macp, const ETHPhyConfig *chipcfg) { + SPIDriver *spi = macp->spi_config->driver; + + uint8_t phycfg = w5500_read8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON); + + if (chipcfg == NULL) + chipcfg = macp->phy_config; + + if (chipcfg->conf_by == ETH_PHY_CONF_BY_SW) { + phycfg |= W5500_PHYCFGR_OPMD; + } else { + phycfg &= ~W5500_PHYCFGR_OPMD; + } + + if (chipcfg->duplex == ETH_PHY_DUPLEX_FULL) { + phycfg |= W5500_PHYCFGR_OPMDC_FULL_DUPLEX; + } else { + phycfg &= ~W5500_PHYCFGR_OPMDC_FULL_DUPLEX; + } + + if (chipcfg->speed == ETH_PHY_SPEED_100) { + phycfg |= W5500_PHYCFGR_OPMDC_SPEED_100; + } else { + phycfg &= ~W5500_PHYCFGR_OPMDC_SPEED_100; + } + + if (chipcfg->mode == ETH_PHY_MODE_AUTO) { + phycfg |= W5500_PHYCFGR_OPMDC_AUTONEGOTIATION; + } else { + phycfg &= ~W5500_PHYCFGR_OPMDC_AUTONEGOTIATION; + } + + /* Reset PHY by setting the RST bit to '0' after the user configures this bit as '1'. */ + phycfg &= ~W5500_PHYCFGR_RST; + w5500_write8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON, phycfg); + /* And enable again. */ + phycfg |= W5500_PHYCFGR_RST; + w5500_write8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON, phycfg); +} + + +static void w5500_lld_init(void) { + +} + + +static void w5500_lld_start(MACDriver *macp) { + SPIDriver *spi = macp->spi_config->driver; + + w5500_lld_hw_reset(macp->spi_config); + + w5500_lld_set_phy_mode(macp, NULL); + + w5500_lld_set_mac_address(spi, macp->config->mac_address); + + w5500_lld_set_tx_buffer_size(spi, 16); + + w5500_lld_set_rx_buffer_size(spi, 16); + + w5500_lld_set_socket_mode_raw(spi); + + w5500_lld_open_socket(spi); + + w5500_lld_enable_isr(macp); +} + + +static bool w5500_lld_poll_link_status(MACDriver *macp) { + SPIDriver *spi = macp->spi_config->driver; + + uint8_t phycfg = w5500_read8(spi, W5500_IO_PHYCFGR, W5500P_BSB_COMMON); + + if (phycfg & W5500_PHYCFGR_STATUS_LNK_UP) + return true; + + return false; +} + + +static void w5500_lld_stop(MACDriver *macp) { + SPIDriver *spi = macp->spi_config->driver; + + w5500_lld_disable_isr(macp); + + w5500_lld_close_socket(spi); + + w5500_lld_pwr_down(spi); +} + + +static size_t w5500_lld_get_free_bytes(SPIDriver *spi) { + + if (W5500_SN_SR_SOCK_MACRAW != w5500_read8(spi, W5500_IO_SN_SR, W5500P_BSB_SOCKET)) + return 0; + + return w5500_read16(spi, W5500_IO_SN_TX_FSR, W5500P_BSB_SOCKET); +} + + +static uint16_t w5500_lld_get_tx_ptr(SPIDriver *spi) { + return w5500_read16(spi, W5500_IO_SN_TX_WR, W5500P_BSB_SOCKET); +} + + +static size_t w5500_lld_write_transmit(MACTransmitDescriptor *tdp, const void *txbuf, size_t size) { + + SPIDriver *spi = tdp->macp->spi_config->driver; + uint16_t ptr; + + if (size > tdp->size) size = tdp->size; + + ptr = tdp->offset; + w5500_write(spi, ptr, W5500P_BSB_TX_BUF, size, txbuf); + + ptr = (size_t)ptr + size; + w5500_write16(spi, W5500_IO_SN_TX_WR, W5500P_BSB_SOCKET, ptr); + + tdp->offset = ptr; + tdp->size = tdp->size - size; + + return size; +} + + +static size_t w5500_lld_get_bytes_received(SPIDriver *spi) { + return w5500_read16(spi, W5500_IO_SN_RX_RSR, W5500P_BSB_SOCKET); +} + + +static uint16_t w5500_lld_get_rx_ptr(SPIDriver *spi) { + return w5500_read16(spi, W5500_IO_SN_RX_RD, W5500P_BSB_SOCKET); +} + + +static size_t w5500_lld_read_receive(MACReceiveDescriptor *rdp, void *rxbuf, size_t size) { + + SPIDriver *spi = rdp->macp->spi_config->driver; + uint16_t ptr = rdp->offset; + + if (size > rdp->size) size = rdp->size; + + w5500_read(spi, ptr, W5500P_BSB_RX_BUF, size, rxbuf); + ptr = (size_t)ptr + size; + w5500_write16(spi, W5500_IO_SN_RX_RD, W5500P_BSB_SOCKET, ptr); + w5500_write8(spi, W5500_IO_SN_CR, W5500P_BSB_SOCKET, W5500_SN_CR_RECV); + + rdp->offset = ptr; + rdp->size = rdp->size - size; + + return size; +} + + +static uint16_t w5500_lld_get_rx_frame_length(SPIDriver *spi) { + + if (W5500_SN_SR_SOCK_MACRAW != w5500_read8(spi, W5500_IO_SN_SR, W5500P_BSB_SOCKET)) + return 0; + + uint16_t bytes_received = w5500_lld_get_bytes_received(spi); + + if (bytes_received < W5500_RX_FRAME_HEADER_SIZE) { + /* Return 0 so that the caller know he must wait for accumulating of more data. */ + return 0; + } + + if (bytes_received > (W5500_RX_FRAME_HEADER_SIZE + W5500_ETH_MAX_FRAME_SIZE)) { + /* Skip all rx data. */ + uint16_t ptr = w5500_lld_get_rx_ptr(spi); + ptr = (size_t)ptr + bytes_received; + w5500_write16(spi, W5500_IO_SN_RX_RD, W5500P_BSB_SOCKET, ptr); + w5500_write8(spi, W5500_IO_SN_CR, W5500P_BSB_SOCKET, W5500_SN_CR_RECV); + return 0; + } + + bytes_received = bytes_received - W5500_RX_FRAME_HEADER_SIZE; + + return bytes_received; +} + + +static uint16_t w5500_lld_get_rx_ptr_skip_eth_header_size(SPIDriver *spi) { + + uint16_t ptr = w5500_lld_get_rx_ptr(spi); + + ptr = (size_t)ptr + W5500_RX_FRAME_HEADER_SIZE; + w5500_write16(spi, W5500_IO_SN_RX_RD, W5500P_BSB_SOCKET, ptr); + w5500_write8(spi, W5500_IO_SN_CR, W5500P_BSB_SOCKET, W5500_SN_CR_RECV); + + return ptr; +} + + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + +#if PLATFORM_MAC_USE_MAC1 == TRUE + macObjectInit(ÐD1); +#endif + w5500_lld_init(); +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + + if (macp->state == MAC_STOP) { + spiStart(macp->spi_config->driver, macp->spi_config->config); + w5500_lld_start(macp); + } +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + if (macp->state != MAC_STOP) { + w5500_lld_stop(macp); + spiStop(macp->spi_config->driver); + } +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + + SPIDriver *spi = macp->spi_config->driver; + + size_t bytes_free = w5500_lld_get_free_bytes(spi); + + if (bytes_free == 0) + return MSG_TIMEOUT; + + tdp->offset = w5500_lld_get_tx_ptr(spi); + tdp->size = bytes_free; + tdp->macp = macp; + + return MSG_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + SPIDriver *spi = tdp->macp->spi_config->driver; + + tdp->offset = 0; + tdp->size = 0; + tdp->macp = NULL; + + w5500_write8(spi, W5500_IO_SN_CR, W5500P_BSB_SOCKET, W5500_SN_CR_SEND); + + while (true) { + uint8_t event_mask = 0; + uint8_t status = w5500_read8(spi, W5500_IO_SN_IR, W5500P_BSB_SOCKET); + + if (status & W5500_SN_IR_TIMEOUT) { + event_mask |= W5500_SN_IR_TIMEOUT; + } + + if (status & W5500_SN_IR_SEND_OK) { + event_mask |= W5500_SN_IR_SEND_OK; + } + + if (event_mask) { + w5500_write8(spi, W5500_IO_SN_IR, W5500P_BSB_SOCKET, event_mask); + break; + } + } +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + + SPIDriver *spi = macp->spi_config->driver; + + size_t eth_frame_length = w5500_lld_get_rx_frame_length(spi); + + if (eth_frame_length == 0) { + /* IRQ flag is still pending and needs to be removed if something + went wrong. */ + if (macp->irq_unhandled) { + macp->irq_unhandled = false; + w5500_lld_clear_pending_irqs(spi); + } + + return MSG_TIMEOUT; + } + + rdp->offset = w5500_lld_get_rx_ptr_skip_eth_header_size(spi); + rdp->size = eth_frame_length; + rdp->macp = macp; + + return MSG_OK; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + + MACDriver *macp = rdp->macp; + SPIDriver *spi = macp->spi_config->driver; + + if (macp->irq_unhandled) { + macp->irq_unhandled = false; + w5500_lld_clear_pending_irqs(spi); + } + + rdp->offset = 0; + rdp->size = 0; + rdp->macp = NULL; +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool mac_lld_poll_link_status(MACDriver *macp) { + + return w5500_lld_poll_link_status(macp); +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + return w5500_lld_write_transmit(tdp, buf, size); +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + + return w5500_lld_read_receive(rdp, buf, size); +} diff --git a/os/various/devices_lib/ethernet/w5500_lld.h b/os/various/devices_lib/ethernet/w5500_lld.h new file mode 100644 index 0000000000..b27bea89b3 --- /dev/null +++ b/os/various/devices_lib/ethernet/w5500_lld.h @@ -0,0 +1,73 @@ +/* + W5500 for ChibiOS/RT - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file w5500_lld.h + * @brief W5500 Driver macros and structures. + * @addtogroup WIZNET + * @{ + */ + +#ifndef W5500_LLD_H +#define W5500_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief W5500 chip ID. + */ +#define W5500_CHIP_ID 0x04 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Size of ethernet frame without FCS: MTU + VLAN tag = 1500 + 4. + */ +#if !defined(W5500_ETH_MAX_FRAME_SIZE) +#define W5500_ETH_MAX_FRAME_SIZE 1504 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" +{ +#endif +#ifdef __cplusplus +} +#endif + +#endif /* W5500_LLD_H */ + +/** @} */ diff --git a/os/various/mbedtls_bindings/hwrng.inc b/os/various/mbedtls_bindings/hwrng.inc new file mode 100644 index 0000000000..13d29070c1 --- /dev/null +++ b/os/various/mbedtls_bindings/hwrng.inc @@ -0,0 +1,32 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "hal.h" + +int mbedtls_ctr_drbg_random(void *p_rng, unsigned char *output, size_t output_len) { + + (void)p_rng; + + bool err = trngGenerate(&TRNGD1, output_len, output); + + if (err) + return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED; + + return 0; +} diff --git a/os/various/mbedtls_bindings/mbedtls.mk b/os/various/mbedtls_bindings/mbedtls.mk new file mode 100644 index 0000000000..be898e2194 --- /dev/null +++ b/os/various/mbedtls_bindings/mbedtls.mk @@ -0,0 +1,112 @@ +MBEDTLS = $(CHIBIOS_CONTRIB)/ext/mbedtls-mbedtls-3.5.0 + +MBEDBINDSRC = \ + $(CHIBIOS_CONTRIB)/os/various/mbedtls_bindings/mbedtls_rng.c \ + $(CHIBIOS_CONTRIB)/os/various/mbedtls_bindings/mbedtls_timing.c \ + $(MBEDTLS)/library/aes.c \ + $(MBEDTLS)/library/aesce.c \ + $(MBEDTLS)/library/aesni.c \ + $(MBEDTLS)/library/aria.c \ + $(MBEDTLS)/library/asn1parse.c \ + $(MBEDTLS)/library/asn1write.c \ + $(MBEDTLS)/library/base64.c \ + $(MBEDTLS)/library/bignum.c \ + $(MBEDTLS)/library/bignum_core.c \ + $(MBEDTLS)/library/bignum_mod.c \ + $(MBEDTLS)/library/bignum_mod_raw.c \ + $(MBEDTLS)/library/camellia.c \ + $(MBEDTLS)/library/ccm.c \ + $(MBEDTLS)/library/chacha20.c \ + $(MBEDTLS)/library/chachapoly.c \ + $(MBEDTLS)/library/cipher.c \ + $(MBEDTLS)/library/cipher_wrap.c \ + $(MBEDTLS)/library/cmac.c \ + $(MBEDTLS)/library/constant_time.c \ + $(MBEDTLS)/library/debug.c \ + $(MBEDTLS)/library/des.c \ + $(MBEDTLS)/library/dhm.c \ + $(MBEDTLS)/library/ecdh.c \ + $(MBEDTLS)/library/ecdsa.c \ + $(MBEDTLS)/library/ecjpake.c \ + $(MBEDTLS)/library/ecp.c \ + $(MBEDTLS)/library/ecp_curves.c \ + $(MBEDTLS)/library/ecp_curves_new.c \ + $(MBEDTLS)/library/error.c \ + $(MBEDTLS)/library/gcm.c \ + $(MBEDTLS)/library/hkdf.c \ + $(MBEDTLS)/library/hmac_drbg.c \ + $(MBEDTLS)/library/lmots.c \ + $(MBEDTLS)/library/lms.c \ + $(MBEDTLS)/library/md.c \ + $(MBEDTLS)/library/md5.c \ + $(MBEDTLS)/library/memory_buffer_alloc.c \ + $(MBEDTLS)/library/mps_reader.c \ + $(MBEDTLS)/library/mps_trace.c \ + $(MBEDTLS)/library/nist_kw.c \ + $(MBEDTLS)/library/oid.c \ + $(MBEDTLS)/library/padlock.c \ + $(MBEDTLS)/library/pem.c \ + $(MBEDTLS)/library/pk.c \ + $(MBEDTLS)/library/pk_wrap.c \ + $(MBEDTLS)/library/pkcs12.c \ + $(MBEDTLS)/library/pkcs5.c \ + $(MBEDTLS)/library/pkcs7.c \ + $(MBEDTLS)/library/pkparse.c \ + $(MBEDTLS)/library/pkwrite.c \ + $(MBEDTLS)/library/platform.c \ + $(MBEDTLS)/library/platform_util.c \ + $(MBEDTLS)/library/poly1305.c \ + $(MBEDTLS)/library/psa_crypto.c \ + $(MBEDTLS)/library/psa_crypto_aead.c \ + $(MBEDTLS)/library/psa_crypto_cipher.c \ + $(MBEDTLS)/library/psa_crypto_client.c \ + $(MBEDTLS)/library/psa_crypto_driver_wrappers_no_static.c \ + $(MBEDTLS)/library/psa_crypto_ecp.c \ + $(MBEDTLS)/library/psa_crypto_ffdh.c \ + $(MBEDTLS)/library/psa_crypto_hash.c \ + $(MBEDTLS)/library/psa_crypto_mac.c \ + $(MBEDTLS)/library/psa_crypto_pake.c \ + $(MBEDTLS)/library/psa_crypto_rsa.c \ + $(MBEDTLS)/library/psa_crypto_se.c \ + $(MBEDTLS)/library/psa_crypto_slot_management.c \ + $(MBEDTLS)/library/psa_crypto_storage.c \ + $(MBEDTLS)/library/psa_its_file.c \ + $(MBEDTLS)/library/psa_util.c \ + $(MBEDTLS)/library/ripemd160.c \ + $(MBEDTLS)/library/rsa.c \ + $(MBEDTLS)/library/rsa_alt_helpers.c \ + $(MBEDTLS)/library/sha1.c \ + $(MBEDTLS)/library/sha256.c \ + $(MBEDTLS)/library/sha3.c \ + $(MBEDTLS)/library/sha512.c \ + $(MBEDTLS)/library/ssl_cache.c \ + $(MBEDTLS)/library/ssl_ciphersuites.c \ + $(MBEDTLS)/library/ssl_client.c \ + $(MBEDTLS)/library/ssl_cookie.c \ + $(MBEDTLS)/library/ssl_debug_helpers_generated.c \ + $(MBEDTLS)/library/ssl_msg.c \ + $(MBEDTLS)/library/ssl_ticket.c \ + $(MBEDTLS)/library/ssl_tls.c \ + $(MBEDTLS)/library/ssl_tls12_client.c \ + $(MBEDTLS)/library/ssl_tls12_server.c \ + $(MBEDTLS)/library/ssl_tls13_client.c \ + $(MBEDTLS)/library/ssl_tls13_generic.c \ + $(MBEDTLS)/library/ssl_tls13_keys.c \ + $(MBEDTLS)/library/ssl_tls13_server.c \ + $(MBEDTLS)/library/threading.c \ + $(MBEDTLS)/library/version.c \ + $(MBEDTLS)/library/x509.c \ + $(MBEDTLS)/library/x509_create.c \ + $(MBEDTLS)/library/x509_crl.c \ + $(MBEDTLS)/library/x509_crt.c \ + $(MBEDTLS)/library/x509_csr.c \ + $(MBEDTLS)/library/x509write.c \ + $(MBEDTLS)/library/x509write_crt.c \ + $(MBEDTLS)/library/x509write_csr.c + +MBEDBINDINC = \ + $(MBEDTLS)/include + +# Shared variables +ALLCSRC += $(MBEDBINDSRC) +ALLINC += $(MBEDBINDINC) diff --git a/os/various/mbedtls_bindings/mbedtls/psk_mbedtls_config.h b/os/various/mbedtls_bindings/mbedtls/psk_mbedtls_config.h new file mode 100644 index 0000000000..d34c44a816 --- /dev/null +++ b/os/various/mbedtls_bindings/mbedtls/psk_mbedtls_config.h @@ -0,0 +1,112 @@ +/** + * \file config-ccm-psk-dtls1_2.h + * + * \brief Small configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Minimal configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites + * + * Distinguishing features: + * - Optimized for small code size, low bandwidth (on an unreliable transport), + * and low RAM usage. + * - No asymmetric cryptography (no certificates, no Diffie-Hellman key + * exchange). + * - Fully modern and secure (provided the pre-shared keys are generated and + * stored securely). + * - Very low record overhead with CCM-8. + * - Includes several optional DTLS features typically used in IoT. + * + * See README.txt for usage instructions. + */ + +/* System support */ +//#define MBEDTLS_HAVE_TIME /* Optionally used in Hello messages */ +/* Other MBEDTLS_HAVE_XXX flags irrelevant for this configuration */ + +/* Mbed TLS modules */ +#define MBEDTLS_AES_C +#define MBEDTLS_CCM_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_MD_C +#define MBEDTLS_NET_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_SSL_TLS_C +#define MBEDTLS_TIMING_C + +/* TLS protocol feature support */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#define MBEDTLS_SSL_DTLS_CONNECTION_ID +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/* + * Use only CCM_8 ciphersuites, and + * save ROM and a few bytes of RAM by specifying our own ciphersuite list + */ +#define MBEDTLS_SSL_CIPHERSUITES \ + MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8, \ + MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8 + +/* + * Save RAM at the expense of interoperability: do this only if you control + * both ends of the connection! (See comments in "mbedtls/ssl.h".) + * The optimal size here depends on the typical size of records. + */ +#define MBEDTLS_SSL_IN_CONTENT_LEN 256 +#define MBEDTLS_SSL_OUT_CONTENT_LEN 256 + +/* Save RAM at the expense of ROM */ +#define MBEDTLS_AES_ROM_TABLES + +/* Save some RAM by adjusting to your exact needs */ +#define MBEDTLS_PSK_MAX_LEN 16 /* 128-bits keys are generally enough */ + +/* + * You should adjust this to the exact number of sources you're using: default + * is the "platform_entropy_poll" source, but you may want to add other ones + * Minimum is 2 for the entropy test suite. + */ +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 + +/* These defines are present so that the config modifying scripts can enable + * them during tests/scripts/test-ref-configs.pl */ +//#define MBEDTLS_USE_PSA_CRYPTO +//#define MBEDTLS_PSA_CRYPTO_C + +/* Error messages and TLS debugging traces + * (huge code size increase, needed for tests/ssl-opt.sh) */ +//#define MBEDTLS_DEBUG_C +//#define MBEDTLS_ERROR_C + +/* To prevent using the libc standard calloc() and free(). */ +//#define MBEDTLS_PLATFORM_C +//#define MBEDTLS_PLATFORM_MEMORY + +/* If your system does not have a libc equivalent, you will get compile errors as calloc() or free() cannot be found.* */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + diff --git a/os/various/mbedtls_bindings/mbedtls/readme.txt b/os/various/mbedtls_bindings/mbedtls/readme.txt new file mode 100644 index 0000000000..7a356dbde6 --- /dev/null +++ b/os/various/mbedtls_bindings/mbedtls/readme.txt @@ -0,0 +1,5 @@ +Use psk_mbedtls_config.h if you want use PSK for authentication. + +x509_mbedtls_config.h if you want use X509 certificates for authentication. + +See also ChibiOS-Contrib/demos/STM32/RT-STM32L476RG-NUCLEO64-W5500-LWIP-ANJAY-MBEDTLS. diff --git a/os/various/mbedtls_bindings/mbedtls/x509_mbedtls_config.h b/os/various/mbedtls_bindings/mbedtls/x509_mbedtls_config.h new file mode 100644 index 0000000000..0021f9ef01 --- /dev/null +++ b/os/various/mbedtls_bindings/mbedtls/x509_mbedtls_config.h @@ -0,0 +1,124 @@ +/** + * \file config-suite-b.h + * + * \brief Minimal configuration for TLS NSA Suite B Profile (RFC 6460) + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Minimal configuration for TLS NSA Suite B Profile (RFC 6460) + * + * Distinguishing features: + * - no RSA or classic DH, fully based on ECC + * - optimized for low RAM usage + * + * Possible improvements: + * - if 128-bit security is enough, disable secp384r1 and SHA-512 + * - use embedded certs in DER format and disable PEM_PARSE_C and BASE64_C + * + * See README.txt for usage instructions. + */ + +/* System support */ +//#define MBEDTLS_HAVE_ASM +//#define MBEDTLS_HAVE_TIME + +/* Mbed TLS feature support */ +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#define MBEDTLS_SSL_DTLS_CONNECTION_ID +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/* Mbed TLS modules */ +#define MBEDTLS_AES_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CTR_DRBG_C +#define MBEDTLS_ECDH_C +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ENTROPY_C +#define MBEDTLS_GCM_C +#define MBEDTLS_MD_C +#define MBEDTLS_NET_C +#define MBEDTLS_OID_C +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SHA384_C +#define MBEDTLS_SHA512_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_SSL_TLS_C +#define MBEDTLS_X509_CRT_PARSE_C +#define MBEDTLS_X509_USE_C + +/* For test certificates */ +#define MBEDTLS_BASE64_C +#define MBEDTLS_PEM_PARSE_C + +/* Save RAM at the expense of ROM */ +#define MBEDTLS_AES_ROM_TABLES + +/* Save RAM by adjusting to our exact needs */ +#define MBEDTLS_MPI_MAX_SIZE 48 // 384-bit EC curve = 48 bytes + +/* Save RAM at the expense of speed, see ecp.h */ +#define MBEDTLS_ECP_WINDOW_SIZE 2 +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 0 + +/* Significant speed benefit at the expense of some ROM */ +#define MBEDTLS_ECP_NIST_OPTIM + +/* + * You should adjust this to the exact number of sources you're using: default + * is the "mbedtls_platform_entropy_poll" source, but you may want to add other ones. + * Minimum is 2 for the entropy test suite. + */ +#define MBEDTLS_ENTROPY_MAX_SOURCES 2 + +/* Save ROM and a few bytes of RAM by specifying our own ciphersuite list */ +#define MBEDTLS_SSL_CIPHERSUITES \ + MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384, \ + MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + +/* + * Save RAM at the expense of interoperability: do this only if you control + * both ends of the connection! (See comments in "mbedtls/ssl.h".) + * The minimum size here depends on the certificate chain used as well as the + * typical size of records. + */ +#define MBEDTLS_SSL_IN_CONTENT_LEN 1024 +#define MBEDTLS_SSL_OUT_CONTENT_LEN 1024 + +/* These defines are present so that the config modifying scripts can enable + * them during tests/scripts/test-ref-configs.pl */ +//#define MBEDTLS_USE_PSA_CRYPTO +//#define MBEDTLS_PSA_CRYPTO_C + +/* Error messages and TLS debugging traces + * (huge code size increase, needed for tests/ssl-opt.sh) */ +//#define MBEDTLS_DEBUG_C +//#define MBEDTLS_ERROR_C diff --git a/os/various/mbedtls_bindings/mbedtls_rng.c b/os/various/mbedtls_bindings/mbedtls_rng.c new file mode 100644 index 0000000000..79da10b029 --- /dev/null +++ b/os/various/mbedtls_bindings/mbedtls_rng.c @@ -0,0 +1,63 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" + +#include "mbedtls/platform.h" +#include "mbedtls/entropy.h" +#include "mbedtls/ctr_drbg.h" + +void mbedtls_ctr_drbg_free(mbedtls_ctr_drbg_context *ctx) { + + (void)ctx; +} + +void mbedtls_ctr_drbg_init(mbedtls_ctr_drbg_context *ctx) { + + (void)ctx; +} + +void mbedtls_entropy_init(mbedtls_entropy_context *ctx) { + + (void)ctx; +} + +int mbedtls_entropy_func(void *data, unsigned char *output, size_t len) { + + return mbedtls_ctr_drbg_random(data, output, len); +} + +int mbedtls_ctr_drbg_seed(mbedtls_ctr_drbg_context *ctx, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len) { + + (void)ctx; + (void)f_entropy; + (void)p_entropy; + (void)custom; + (void)len; + + return 0; +} + +#if defined(HAL_USE_TRNG) && (HAL_USE_TRNG==TRUE) && \ + defined(STM32_TRNG_USE_RNG1) && (STM32_TRNG_USE_RNG1==TRUE) +#include "hwrng.inc" +#else +#include "swrng.inc" +#endif diff --git a/os/various/mbedtls_bindings/mbedtls_timing.c b/os/various/mbedtls_bindings/mbedtls_timing.c new file mode 100644 index 0000000000..5f1805b082 --- /dev/null +++ b/os/various/mbedtls_bindings/mbedtls_timing.c @@ -0,0 +1,88 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * mbedtls_timing_set_delay, mbedtls_timing_get_delay and + * mbedtls_timing_get_timer implementations based on mbedtls/library/timing.c + */ + +#include + +#include "mbedtls/timing.h" + +#include "ch.h" + + +unsigned long mbedtls_timing_hardclock(void) { + + return (unsigned long)chTimeI2MS(chVTGetSystemTime()); +} + +/* + * Set delays to watch + */ +void mbedtls_timing_set_delay(void *data, uint32_t int_ms, uint32_t fin_ms) { + mbedtls_timing_delay_context *ctx = (mbedtls_timing_delay_context *)data; + + ctx->MBEDTLS_PRIVATE(int_ms) = int_ms; + ctx->MBEDTLS_PRIVATE(fin_ms) = fin_ms; + + if (fin_ms != 0) + (void)mbedtls_timing_get_timer(&ctx->MBEDTLS_PRIVATE(timer), 1); +} + +/* + * Get number of delays expired + */ +int mbedtls_timing_get_delay(void *data) { + mbedtls_timing_delay_context *ctx = (mbedtls_timing_delay_context *)data; + unsigned long elapsed_ms; + + if (ctx->MBEDTLS_PRIVATE(fin_ms) == 0) + return -1; + + elapsed_ms = mbedtls_timing_get_timer(&ctx->MBEDTLS_PRIVATE(timer), 0); + + if (elapsed_ms >= ctx->MBEDTLS_PRIVATE(fin_ms)) + return 2; + + if (elapsed_ms >= ctx->MBEDTLS_PRIVATE(int_ms)) + return 1; + + return 0; +} + +unsigned long mbedtls_timing_get_timer(struct mbedtls_timing_hr_time *val, + int reset) { + +#ifndef MIN +#define MIN(x, y) ((x) < (y) ? (x) : (y)) +#endif + + systime_t start = 0; + + memcpy(&start, val, MIN(sizeof(start), sizeof(*val))); + + const systime_t end = chVTGetSystemTime(); + + if (reset) { + memset(val, 0, sizeof(*val)); + memcpy(val, &end, MIN(sizeof(*val), sizeof(end))); + return 0; + } + + return (unsigned long)chTimeI2MS(chTimeDiffX(start, end)); +} diff --git a/os/various/mbedtls_bindings/swrng.inc b/os/various/mbedtls_bindings/swrng.inc new file mode 100644 index 0000000000..2b4fa1708f --- /dev/null +++ b/os/various/mbedtls_bindings/swrng.inc @@ -0,0 +1,69 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +/* Python-generated as follows: for i in [randint(0, 255) for _ in range(256)]: print("%#02x" % i, end=", ") */ +static const uint8_t rnd[256] = { + 0xe4, 0xd9, 0x5b, 0xd1, 0x92, 0x23, 0x16, 0x55, 0x7e, 0x32, 0x67, 0xd9, 0x52, 0x97, 0x6b, 0xb4, + 0xb7, 0x44, 0xaa, 0x69, 0x85, 0x6b, 0xf6, 0x23, 0xcf, 0x2a, 0x91, 0x55, 0x57, 0x15, 0x6e, 0x29, + 0x62, 0x5f, 0x67, 0xa2, 0xe8, 0xa1, 0x76, 0x7e, 0x97, 0x0a, 0xf4, 0x12, 0x52, 0x82, 0x33, 0xe5, + 0x89, 0x76, 0xe7, 0xbc, 0xec, 0xd0, 0x93, 0xf0, 0x2e, 0x97, 0x39, 0x86, 0x42, 0x1a, 0x24, 0x9d, + + 0xe3, 0xb1, 0xbc, 0x84, 0x1e, 0x6b, 0x80, 0xaa, 0x45, 0x3a, 0x77, 0x82, 0xff, 0x93, 0xc1, 0x09, + 0x65, 0x77, 0xc0, 0xda, 0x6f, 0x52, 0x38, 0x1a, 0x1e, 0x0e, 0x18, 0xd9, 0x1c, 0x68, 0x35, 0x29, + 0xf2, 0x5f, 0x8c, 0x61, 0x0a, 0x9e, 0x9e, 0x18, 0x67, 0x1f, 0x82, 0x57, 0x5c, 0xe4, 0x8c, 0x98, + 0x01, 0x38, 0xc5, 0xea, 0x33, 0x76, 0xd3, 0x7b, 0x83, 0x1d, 0xe6, 0x5f, 0x5f, 0x53, 0xf9, 0x49, + + 0xa9, 0x2e, 0x9a, 0xff, 0xfc, 0x93, 0x01, 0x6c, 0xae, 0xe5, 0x40, 0xc2, 0xe3, 0xc3, 0x9e, 0xc2, + 0x03, 0xe9, 0xdd, 0x28, 0x3e, 0x26, 0xa6, 0x08, 0xf2, 0xf8, 0x3c, 0xcf, 0x1a, 0x1d, 0xfd, 0x6a, + 0x67, 0xfa, 0xa8, 0xd8, 0x78, 0x6b, 0xbb, 0x64, 0xe2, 0xbf, 0x9c, 0xcf, 0x84, 0x25, 0x29, 0xe0, + 0x62, 0x1d, 0x63, 0x5b, 0x1c, 0x2b, 0x65, 0xe6, 0x25, 0x4a, 0x72, 0x3a, 0x5c, 0x71, 0xcb, 0xf1, + + 0x06, 0x4f, 0xf7, 0xeb, 0xf3, 0xe6, 0x0c, 0x1e, 0x00, 0xd8, 0xd4, 0xa8, 0x0f, 0xce, 0xdc, 0xfe, + 0x81, 0x60, 0xe8, 0x2c, 0x4a, 0x10, 0x6a, 0x9a, 0x94, 0xd5, 0x59, 0xce, 0x29, 0x1e, 0x5a, 0xea, + 0xaa, 0xfd, 0x9f, 0xbb, 0x2f, 0x31, 0x05, 0xa4, 0x5f, 0x71, 0xa3, 0x61, 0x24, 0x37, 0x2d, 0x24, + 0xf0, 0x93, 0x52, 0x13, 0x5f, 0x18, 0xca, 0x94, 0x9f, 0x9f, 0x7c, 0xbe, 0x29, 0x3e, 0xfa, 0xdd +}; + +int mbedtls_ctr_drbg_random(void *p_rng, unsigned char *output, size_t output_len) { + + (void)p_rng; + + while (output_len > 0) { + const systime_t now = chVTGetSystemTime(); + + const uint8_t n[sizeof(now)] = { +#if (CH_CFG_ST_RESOLUTION > 32) + rnd[(now >> 56) & 0xFF], rnd[(now >> 48) & 0xFF], + rnd[(now >> 40) & 0xFF], rnd[(now >> 32) & 0xFF], + +#endif +#if (CH_CFG_ST_RESOLUTION > 16) + rnd[(now >> 24) & 0xFF], rnd[(now >> 16) & 0xFF], +#endif + rnd[(now >> 8) & 0xFF], rnd[(now >> 0) & 0xFF], + }; + + size_t i = sizeof(n)/sizeof(n[0]); + while (i > 0 && output_len > 0) { + output[--output_len] = n[--i]; + } + } + + return 0; +} diff --git a/os/various/wiznet-iolibrary-driver_bindings/wiznet.mk b/os/various/wiznet-iolibrary-driver_bindings/wiznet.mk new file mode 100644 index 0000000000..140dc54290 --- /dev/null +++ b/os/various/wiznet-iolibrary-driver_bindings/wiznet.mk @@ -0,0 +1,55 @@ +# WIZNET files. + +WIZNETSRC = \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS_CONTRIB)/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5100/w5100.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5100S/w5100s.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5200/w5200.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5300/w5300.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5500/w5500.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/wizchip_conf.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/socket.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/DHCP/dhcp.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/DNS/dns.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/FTPClient/ftpc.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/FTPServer/ftpd.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/httpServer/httpParser.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/httpServer/httpServer.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/httpServer/httpUtil.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTClient.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/mqtt_interface.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTConnectServer.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTConnectClient.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTFormat.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTPacket.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTSerializePublish.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTSubscribeClient.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTSubscribeServer.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTUnsubscribeClient.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src/MQTTUnsubscribeServer.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/SNTP/sntp.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/TFTP/netutil.c \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/TFTP/tftp.c + +WIZNETINC = \ + $(CHIBIOS_CONTRIB)/os/various/wiznet-iolibrary-driver_bindings \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5100 \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5100S \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5200 \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5300 \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet/W5500 \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Ethernet \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/DHCP \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/DNS \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/FTPClient \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/FTPServer \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/httpServer \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/MQTT/MQTTPacket/src \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/SNTP \ + $(CHIBIOS_CONTRIB)/ext/wiznet-iolibrary-driver/Internet/TFTP + +# Shared variables +ALLCSRC += $(WIZNETSRC) +ALLINC += $(WIZNETINC) diff --git a/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.c b/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.c new file mode 100644 index 0000000000..4752156e48 --- /dev/null +++ b/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.c @@ -0,0 +1,529 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +#include "wiznet_chibios.h" +#include "wizchip_conf.h" + +#include "socket.h" +#include "dhcp.h" +#include "dns.h" + +static SPIDriver *spip; + +static void wizchip_select(void) { + + spiSelect(spip); +} + + +static void wizchip_deselect(void) { + + spiUnselect(spip); +} + + +static uint8_t wizchip_read_byte(void) { + + uint8_t rb; + + spiReceive(spip, 1, &rb); + return rb; +} + + +static void wizchip_write_byte(uint8_t wb) { + + spiSend(spip, 1, &wb); +} + + +static void wizchip_read_buffer(uint8_t *pBuf, uint16_t len) { + + spiReceive(spip, len, pBuf); +} + + +static void wizchip_write_buffer(uint8_t *pBuf, uint16_t len) { + + spiSend(spip, len, pBuf); +} + + +static inline void __wizchipHWReset(const WIZCHIP_ETHSPIConfig *config) { + + palClearLine(config->reset_line); + chThdSleepMilliseconds(config->reset_trc_delay_ms); + + palSetLine(config->reset_line); + chThdSleepMilliseconds(config->reset_tpl_delay_ms); +} + + +#define ETH_SOCKET_BUFFER_SIZE_INITIALIZER WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB, \ + WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB + +static inline int __wizchipInitSocketBufferSize(void) { + + uint8_t sock_buf_size[2] [_WIZCHIP_SOCK_NUM_] = { + [0] = { ETH_SOCKET_BUFFER_SIZE_INITIALIZER }, + [1] = { ETH_SOCKET_BUFFER_SIZE_INITIALIZER }, + }; + + return ctlwizchip(CW_INIT_WIZCHIP, sock_buf_size); +} + + +static inline int __wizchipConfigurePHY(const WIZCHIP_ETHPhyConfig *phy_config) { + + wiz_PhyConf phyconf; + + phyconf.by = (phy_config->conf_by == ETH_PHY_CONF_BY_HW) ? PHY_CONFBY_HW : PHY_CONFBY_SW; + phyconf.mode = (phy_config->mode == ETH_PHY_MODE_MANUAL) ? PHY_MODE_MANUAL : PHY_MODE_AUTONEGO; + phyconf.speed = (phy_config->speed == ETH_PHY_SPEED_10) ? PHY_SPEED_10 : PHY_SPEED_100; + phyconf.duplex = (phy_config->duplex == ETH_PHY_DUPLEX_HALF) ? PHY_DUPLEX_HALF : PHY_DUPLEX_FULL; + + return ctlwizchip(CW_SET_PHYCONF, &phyconf); +} + + +void wizchipInit(void) { +} + + +/** + * @brief Configures and activates the SPI peripheral. + * @param[in] spip pointer to the @p WIZCHIPConfig + * object + * @param[in] cfgp pointer to the @p WIZCHIPConfig + * object + * @return The operation status. + * @api + */ +msg_t wizchipStart(WIZCHIP_MACDriver *wizp, const WIZCHIP_MACConfig *configp) { + + msg_t msg; + + osalDbgCheck((wizp != NULL) && (configp != NULL)); + + osalDbgCheck(wizp->spi_config != NULL); + osalDbgCheck(wizp->phy_config != NULL); + osalDbgCheck(wizp->net_config != NULL); + osalDbgCheck(configp->mac_address != NULL); + + wizp->config = configp; + + spip = wizp->spi_config->driver; + + reg_wizchip_cs_cbfunc(wizchip_select, wizchip_deselect); + reg_wizchip_spi_cbfunc(wizchip_read_byte, wizchip_write_byte); + reg_wizchip_spiburst_cbfunc(wizchip_read_buffer, wizchip_write_buffer); + + msg = spiStart(wizp->spi_config->driver, wizp->spi_config->config); + + return msg; +} + + +void wizchipStop(WIZCHIP_MACDriver *wizp) { + + spiStop(wizp->spi_config->driver); + + reg_wizchip_cs_cbfunc(NULL, NULL); + reg_wizchip_spi_cbfunc(NULL, NULL); + reg_wizchip_spiburst_cbfunc(NULL, NULL); + + spip = NULL; +} + + +msg_t wizchipReset(WIZCHIP_MACDriver *wizp) { + + int rc; + + osalDbgCheck(wizp != NULL); + osalDbgCheck(wizp->config != NULL); + + __wizchipHWReset(wizp->spi_config); + + rc = __wizchipInitSocketBufferSize(); + + if (rc != 0) + return HAL_RET_CONFIG_ERROR; + + rc = __wizchipConfigurePHY(wizp->phy_config); + + if (rc != 0) + return HAL_RET_CONFIG_ERROR; + + return HAL_RET_SUCCESS; +} + + +bool wizchipPhyLinkIsUp(WIZCHIP_MACDriver *wizp) { + + int rc; + int8_t phylink; + + (void)wizp; + + rc = ctlwizchip(CW_GET_PHYLINK, &phylink); + + if (rc != 0) + return false; + + return (phylink == PHY_LINK_ON); +} + + +char *wizchipGetId(WIZCHIP_MACDriver *wizp, char chipid[6] ) { + + int rc; + + (void)wizp; + + rc = ctlwizchip(CW_GET_ID, chipid); + + if (rc != 0) + strcpy(chipid, "?????"); + + return chipid; +} + + +static msg_t wizchipSetIPModeStatic(WIZCHIP_MACDriver *wizp) { + + int rc; + wiz_NetInfo netinfo; + + osalDbgCheck(wizp != NULL); + osalDbgCheck(wizp->config->mac_address != NULL); + osalDbgCheck(wizp->net_config != NULL); + + wizp->net_config->mode = WIZCHIP_NET_ADDRESS_STATIC; + + memcpy(netinfo.mac, wizp->config->mac_address, 6); + memcpy(netinfo.ip, wizp->net_config->ip.ip, 4); + memcpy(netinfo.sn, wizp->net_config->sn.sn, 4); + memcpy(netinfo.gw, wizp->net_config->gw.ip, 4); + memcpy(netinfo.dns, wizp->net_config->dns.ip, 4); + netinfo.dhcp = NETINFO_STATIC; + + rc = ctlnetwork(CN_SET_NETINFO, &netinfo); + + if (rc != 0) + return HAL_RET_CONFIG_ERROR; + + return HAL_RET_SUCCESS; +} + + +static msg_t wizchipSetIPModeDHCP(WIZCHIP_MACDriver *wizp) { + + int rc; + wiz_NetInfo netinfo; + + osalDbgCheck(wizp != NULL); + osalDbgCheck(wizp->config->mac_address != NULL); + + wizp->net_config->mode = WIZCHIP_NET_ADDRESS_DHCP; + + memcpy(netinfo.mac, wizp->config->mac_address, 6); + memset(netinfo.ip, 0, 4); + memset(netinfo.sn, 0, 4); + memset(netinfo.gw, 0, 4); + memset(netinfo.dns, 0, 4); + netinfo.dhcp = NETINFO_DHCP; + + rc = ctlnetwork(CN_SET_NETINFO, &netinfo); + + if (rc != 0) + return HAL_RET_CONFIG_ERROR; + + return HAL_RET_SUCCESS; +} + + +msg_t wizchipSetIPMode(WIZCHIP_MACDriver *wizp, ip_mode_t ip_mode) { + + osalDbgCheck(wizp != NULL); + + if (ip_mode == WIZCHIP_NET_ADDRESS_STATIC) + return wizchipSetIPModeStatic(wizp); + else if (ip_mode == WIZCHIP_NET_ADDRESS_DHCP) + return wizchipSetIPModeDHCP(wizp); + else + osalDbgCheck(true); + + return HAL_RET_CONFIG_ERROR; +} + + +ip_mode_t wizchipGetIPMode(WIZCHIP_MACDriver *wizp) { + + osalDbgCheck(wizp != NULL); + + return wizp->net_config->mode; +} + + +dhcp_query_result_t wizchipRefreshDHCPLease(WIZCHIP_MACDriver *wizp, uint32_t waittime_sec, + uint32_t *dhcp_lease_time) { + + dhcp_query_result_t res = DHCP_QUERY_TIMEOUT; + + osalDbgCheck(wizp != NULL); + osalDbgCheck(waittime_sec > 0); + + DHCP_init(WIZCHIP_DHCP_SOCKET, wizp->eth_frame_buffer); + + const systime_t start = chVTGetSystemTime(); + const systime_t end = chTimeAddX(start, TIME_S2I(waittime_sec)); + + while (chVTIsSystemTimeWithin(start, end)) { + uint8_t dhcp_status = DHCP_run(); + + if (dhcp_status == DHCP_IP_ASSIGN || + dhcp_status == DHCP_IP_CHANGED || + dhcp_status == DHCP_IP_LEASED) { + + getIPfromDHCP(wizp->net_config->ip.ip); + getSNfromDHCP(wizp->net_config->sn.sn); + getGWfromDHCP(wizp->net_config->gw.ip); + getDNSfromDHCP(wizp->net_config->dns.ip); + + if (dhcp_lease_time != NULL) + *dhcp_lease_time = getDHCPLeasetime(); + + res = DHCP_QUERY_SUCCESS; + break; + } + + chThdSleepMilliseconds(1000); + DHCP_time_handler(); /* 1 second tick. */ + } + + DHCP_stop(); + + return res; +} + + +static inline int wizchipIsDomainName(const char *host, IP_Address_t *ip_from_dns) { + + const size_t host_size = strlen(host); + int dot_count = 0; + uint8_t *ip = ip_from_dns->ip; + + *ip = 0; + + for (size_t i = 0; i < host_size && dot_count < 4; ++i) { + if ('0' <= host[i] && host[i] <= '9') { + *ip *= 10; + *ip += host[i] - '0'; + } else if (host[i] == '.') { + ip++; + *ip = 0; + dot_count++; + } else { + memset(ip_from_dns, 0, sizeof(*ip_from_dns)); + return 1; /* host is a domain name. */ + } + } + + return 0; /* host is an IP address, NOT a domain name. */ +} + + +dns_query_result_t wizchipDNSQuery(WIZCHIP_MACDriver *wizp, uint32_t waittime_sec, const char *host, + IP_Address_t *ip_from_dns) { + + dns_query_result_t res = DNS_QUERY_TIMEOUT; + + osalDbgCheck(wizp != NULL); + osalDbgCheck(waittime_sec > 0); + osalDbgCheck(host != NULL); + osalDbgCheck(ip_from_dns != NULL); + + if (!wizchipIsDomainName(host, ip_from_dns)) + return DNS_QUERY_SUCCESS; + + DNS_init(WIZCHIP_DNS_SOCKET, wizp->eth_frame_buffer); + + const systime_t start = chVTGetSystemTime(); + const systime_t end = chTimeAddX(start, TIME_S2I(waittime_sec)); + + while (chVTIsSystemTimeWithin(start, end)) { + int8_t dns_status = DNS_run(wizp->net_config->dns.ip, (uint8_t *)host, ip_from_dns->ip); + + if (dns_status == 1) { + res = DNS_QUERY_SUCCESS; + break; + } + + chThdSleepMilliseconds(1000); + DNS_time_handler(); /* 1 second tick. */ + } + + return res; +} + + +int wizchipSocket(int domain, int socket_type, int protocol) { + + int sock; + + (void)domain; + (void)protocol; + + switch (socket_type) { + case WIZCHIP_TYPE_MAC: + sock = socket(WIZCHIP_MAC_SOCKET, Sn_MR_MACRAW, WIZCHIP_ANY_PORT, 0); + break; + + case WIZCHIP_TYPE_RAW: + sock = socket(WIZCHIP_RAW_SOCKET, Sn_MR_UDP, WIZCHIP_ANY_PORT, 0); + break; + + case WIZCHIP_TYPE_DGRAM: + sock = socket(WIZCHIP_UDP_SOCKET, Sn_MR_UDP, WIZCHIP_ANY_PORT, 0); + break; + + case WIZCHIP_TYPE_STREAM: + sock = socket(WIZCHIP_TCP_SOCKET, Sn_MR_TCP, WIZCHIP_ANY_PORT, 0); + break; + + default: + sock = WIZCHIP_INVALID_SOCKET; + break; + } + + return sock; +} + + +int wizchipClose(int sock) { + + int err = close(sock); + + if (err != SOCK_OK) + return -1; + + return 0; +} + +int wizchipShutdown(int sock) { + + (void)sock; + + return 0; +} + + +int wizchipConnect(int sock, IP_Address_t *addr, uint16_t port) { + + int err = connect(sock, addr->ip, port); + + if (err != SOCK_OK) + return -1; + + return 0; +} + + +int wizchipDisconnect(int sock) { + + int err = disconnect(sock); + + if (err != SOCK_OK) + return -1; + + return 0; +} + +int wizchipSend(int sock, const void *buf, size_t len, int flag) { + + (void)flag; + + int tx_bytes = send(sock, (void *)buf, len); + + return tx_bytes; +} + +int wizchipRecv(int sock, void *buf, size_t len, int flag) { + + (void)flag; + + int rx_bytes = recv(sock, buf, len); + + return rx_bytes; +} + + +int wizchipSendTo(int sock, const void *buf, size_t len, int flag, + IP_Address_t *dest_addr, uint16_t dest_port) { + + (void)flag; + + int tx_bytes = sendto(sock, (void *)buf, len, dest_addr->ip, dest_port); + + return tx_bytes; +} + + +int wizchipRecvFrom(int sock, void *buf, size_t len, int flag, + IP_Address_t *dest_addr, uint16_t dest_port) { + + (void)flag; + + int rx_bytes = recvfrom(sock, buf, len, dest_addr->ip, &dest_port); + + return rx_bytes; +} + +int wizchipSetSockopt(int sock, int level, int optname, + const void *optval, size_t optlen) { + + (void)sock; + (void)level; + (void)optname; + (void)optval; + (void)optlen; + + return 0; +} + +int wizchipGetSockopt(int sock, int level, int optname, + const void *optval, size_t optlen) { + + (void)sock; + (void)level; + (void)optname; + (void)optval; + (void)optlen; + + return 0; +} diff --git a/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.h b/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.h new file mode 100644 index 0000000000..200a8b2ed4 --- /dev/null +++ b/os/various/wiznet-iolibrary-driver_bindings/wiznet_chibios.h @@ -0,0 +1,294 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file wiznet_chibios.h + * @brief WIZNET Driver macros and structures. + * @addtogroup WIZNET + * @{ + */ + +#ifndef HAL_WIZNET_H +#define HAL_WIZNET_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +enum { + WIZCHIP_INVALID_SOCKET = -1, + WIZCHIP_MAC_SOCKET = 0, + WIZCHIP_RAW_SOCKET, + WIZCHIP_UDP_SOCKET, + WIZCHIP_TCP_SOCKET, + WIZCHIP_DHCP_SOCKET, + WIZCHIP_DNS_SOCKET, + WIZCHIP_NTP_SOCKET, +}; + +typedef enum { + DHCP_QUERY_SUCCESS = 0, + DHCP_QUERY_ERROR, + DHCP_QUERY_TIMEOUT +} dhcp_query_result_t; + +typedef enum { + DNS_QUERY_SUCCESS = 0, + DNS_QUERY_ERROR, + DNS_QUERY_TIMEOUT +} dns_query_result_t; + +typedef enum { + + WIZCHIP_NET_ADDRESS_STATIC = 0, + WIZCHIP_NET_ADDRESS_DHCP, +} ip_mode_t; + +#define WIZCHIP_DOMAIN_UNIX 0 +#define WIZCHIP_DOMAIN_LOCAL 1 +#define WIZCHIP_DOMAIN_INET 2 + +#define WIZCHIP_TYPE_MAC 0 +#define WIZCHIP_TYPE_RAW 1 +#define WIZCHIP_TYPE_DGRAM 2 +#define WIZCHIP_TYPE_STREAM 3 + +#define WIZCHIP_FLAG_MSG_DONTWAIT (1<<0) +#define WIZCHIP_FLAG_MSG_WAIT (1<<1) + +#define WIZCHIP_SOL_SOCKET 0 + +#define WIZCHIP_SO_RCVTIMEO 0 + +enum { + WIZCHIP_SOCKETS_ERR_OK = 0, + WIZCHIP_SOCKETS_ERR_DESCRIPTOR, + WIZCHIP_SOCKETS_ERR_PARAMETER, + WIZCHIP_SOCKETS_ERR_WOULDBLOCK, + WIZCHIP_SOCKETS_ERR_NOMEMORY, + WIZCHIP_SOCKETS_ERR_CLOSING, + WIZCHIP_SOCKETS_ERR_LOCKED, + WIZCHIP_SOCKETS_ERR_TIMEOUT, + WIZCHIP_SOCKETS_ERR_INPROGRESS, + WIZCHIP_SOCKETS_ERR_NONAME, + WIZCHIP_SOCKETS_ERR_NONETWORK, + WIZCHIP_SOCKETS_ERR_UNSUPPORTED, + WIZCHIP_SOCKETS_ERR_STATE, + WIZCHIP_SOCKETS_ERR_GENERAL +}; + +#define WIZCHIP_ANY_PORT (uint16_t)0 + +#define ETH_PHY_CONF_BY_HW (eth_phy_conf_t)0 +#define ETH_PHY_CONF_BY_SW (eth_phy_conf_t)1 + +#define ETH_PHY_MODE_MANUAL (eth_phy_mode_t)0 +#define ETH_PHY_MODE_AUTO (eth_phy_mode_t)1 + +#define ETH_PHY_SPEED_10 (eth_phy_speed_t)0 +#define ETH_PHY_SPEED_100 (eth_phy_speed_t)1 + +#define ETH_PHY_DUPLEX_HALF (eth_phy_duplex_t)0 +#define ETH_PHY_DUPLEX_FULL (eth_phy_duplex_t)1 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#ifndef _WIZCHIP_ +#define _WIZCHIP_ W5500 /* Define _WIZCHIP_ as one of W5100, W5100S, W5200, W5300, W5500 (default). */ +#endif + +#ifndef ETH_FRAME_BUFFER_SIZE +#define ETH_FRAME_BUFFER_SIZE 2048u +#endif + +#ifndef WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB +#define WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB 2u +#endif + +#if HAL_USE_SPI == FALSE +#error "ETH driver requires HAL_USE_SPI" +#endif + +#if SPI_USE_WAIT == FALSE +#error "ETH driver requires SPI_USE_WAIT" +#endif + +#define ETH_USE_MUTUAL_EXCLUSION SPI_USE_MUTUAL_EXCLUSION + +#if HAL_USE_PAL == FALSE +#error "ETH driver requires HAL_USE_PAL" +#endif + +#define ETH_USE_CALLBACKS PAL_USE_CALLBACKS + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#define WIZCHIP_MAX_SOCKET_TX_DATA_SIZE (WIZCHIP_MAX_SOCKET_TX_DATA_SIZE_KB*1024u) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef struct { + uint8_t ip[4]; +} IP_Address_t; + +typedef struct { + uint8_t sn[4]; +} IP_Subnet_t; + +typedef int32_t eth_link_state_t; + +typedef int32_t eth_phy_conf_t; + +typedef int32_t eth_phy_mode_t; + +typedef int32_t eth_phy_speed_t; + +typedef int32_t eth_phy_duplex_t; + + +typedef struct { + SPIDriver *driver; + + const SPIConfig *config; + + ioline_t reset_line; + + uint16_t reset_trc_delay_ms; + + uint16_t reset_tpl_delay_ms; + +#if ETH_USE_CALLBACKS == TRUE + ioline_t irq_line; +#endif +} WIZCHIP_ETHSPIConfig; + +typedef struct { + eth_phy_conf_t conf_by; + + eth_phy_mode_t mode; + + eth_phy_speed_t speed; + + eth_phy_duplex_t duplex; + +} WIZCHIP_ETHPhyConfig; + +typedef struct { + IP_Address_t ip; + + IP_Subnet_t sn; + + IP_Address_t gw; + + IP_Address_t dns; + + ip_mode_t mode; + +} WIZCHIP_NetworkConfig; + +typedef struct { + const uint8_t *mac_address; +} WIZCHIP_MACConfig; + +typedef struct { + const WIZCHIP_MACConfig *config; + + const WIZCHIP_ETHSPIConfig *spi_config; + + const WIZCHIP_ETHPhyConfig *phy_config; + + WIZCHIP_NetworkConfig *net_config; + + uint8_t eth_frame_buffer[ETH_FRAME_BUFFER_SIZE]; +} WIZCHIP_MACDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern WIZCHIP_MACDriver WIZCHIP0; + +#ifdef __cplusplus +extern "C" +{ +#endif +void wizchipInit(void); + +msg_t wizchipStart(WIZCHIP_MACDriver *wizp, const WIZCHIP_MACConfig *configp); + +void wizchipStop(WIZCHIP_MACDriver *wizp); + +msg_t wizchipReset(WIZCHIP_MACDriver *wizp); + +bool wizchipPhyLinkIsUp(WIZCHIP_MACDriver *wizp); + +char *wizchipGetId(WIZCHIP_MACDriver *wizp, char chipid[6] ); + +msg_t wizchipSetIPMode(WIZCHIP_MACDriver *wizp, ip_mode_t ip_mode); + +ip_mode_t wizchipGetIPMode(WIZCHIP_MACDriver *wizp); + +dhcp_query_result_t +wizchipRefreshDHCPLease(WIZCHIP_MACDriver *wizp, uint32_t waittime_sec, + uint32_t *dhcp_lease_time); + +dns_query_result_t +wizchipDNSQuery(WIZCHIP_MACDriver *wizp, uint32_t waittime_sec, + const char *host, IP_Address_t *ip_from_dns); + +int wizchipSocket(int domain, int socket_type, int protocol); + +int wizchipClose(int sock); + +int wizchipShutdown(int sock); + +int wizchipConnect(int sock, IP_Address_t *addr, uint16_t port); + +int wizchipDisconnect(int sock); + +int wizchipSend(int sock, const void *buf, size_t len, int flag); + +int wizchipRecv(int sock, void *buf, size_t len, int flag); + +int wizchipSendTo(int sock, const void *buf, size_t len, int flag, + IP_Address_t *dest_addr, uint16_t dest_port); + +int wizchipRecvFrom(int sock, void *buf, size_t len, int flag, + IP_Address_t *dest_addr, uint16_t dest_port); + +int wizchipSetSockopt(int sock, int level, int optname, + const void *optval, size_t optlen); + +int wizchipGetSockopt(int sock, int level, int optname, + const void *optval, size_t optlen); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_WIZNET_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/Makefile b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/Makefile new file mode 100644 index 0000000000..79b2889870 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/Makefile @@ -0,0 +1,200 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS_CONTRIB)/os/various/bitmap.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) \ + $(CHIBIOS_CONTRIB)/os/various + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DEFR32FG23B010F512IM48=1 \ + -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/halconf.h new file mode 100644 index 0000000000..0ecdc33c4e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/halconf_community.h new file mode 100644 index 0000000000..3e7feb073f --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 TRUE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 TRUE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 TRUE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 TRUE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/mcuconf.h new file mode 100644 index 0000000000..48aa277ad9 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/cfg/mcuconf.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_EM01GRPCCLK + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 TRUE +#define EFR32_SIO_USE_EUSART2 TRUE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/main.c b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/main.c new file mode 100644 index 0000000000..c064c314ae --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/main.c @@ -0,0 +1,143 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "cmsis_os.h" +#include "hal.h" +#include "hal_buram.h" + +static void led_on(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static int time_is_set; +static int alarm_triggered; + +static const RTCAlarm alarmspec1 = { + .tv_sec = 2, + .tv_usec = 100, +}; + +static void rtc_callback(RTCDriver* rtcp, rtcevent_t evt) { + + switch (evt) { + case RTC_EVENT_TIME_SET: + time_is_set++; + break; + case RTC_EVENT_ALARM: + alarm_triggered++; + /* Retrigger alarm. */ + rtcSetAlarm(rtcp, 0, &alarmspec1); + break; + case RTC_EVENT_TS_OVF: + break; + } +} + +static void test_rtc(void) { + + rtcSetCallback(&RTCD1, rtc_callback); + + const RTCDateTime ts1 = { + .year = 44, + .month = 6, + .dstflag = 0, + .dayofweek = 7, + .day = 9, + .millisecond = (19 * 3600 + 4 * 60 + 30) * 1000 + 123 + }; + rtcSetTime(&RTCD1, &ts1); + + osDelay(1000); + osDelay(1000); + + RTCDateTime ts2 = { 0 }; + rtcGetTime(&RTCD1, &ts2); + + osalDbgAssert(time_is_set == 1, "no time set event"); + osalDbgAssert(ts1.year == ts2.year, "wrong year"); + osalDbgAssert(ts1.month == ts2.month, "wrong month"); + osalDbgAssert(ts1.dstflag == ts2.dstflag, "wrong dstflag"); + osalDbgAssert(ts1.dayofweek == ts2.dayofweek, "wrong dayofweek"); + osalDbgAssert(ts1.day == ts2.day, "wrong day"); + osalDbgAssert((ts1.millisecond + 2000 - ts2.millisecond) < 10, "wrong milliscond"); +} + +static void test_rtc_alarm(void) { + + rtcSetAlarm(&RTCD1, 0, &alarmspec1); + + RTCAlarm alarmspec2 = { 0 }; + rtcGetAlarm(&RTCD1, 0, &alarmspec2); + + osalDbgAssert(alarmspec1.tv_sec == alarmspec2.tv_sec, "wrong alarm second"); + osalDbgAssert((alarmspec1.tv_usec - alarmspec2.tv_usec) < 100, "wrong alarm microsecond"); + + osDelay(alarmspec1.tv_sec * 1000 + 1 + alarmspec1.tv_usec / 1000); + osalDbgAssert(alarm_triggered == 1, "no first alarm triggered"); + + osDelay(alarmspec1.tv_sec * 1000 + 1 + alarmspec1.tv_usec / 1000); + osalDbgAssert(alarm_triggered == 2, "no second alarm triggered"); +} + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; + (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + buramInit(); + BURAMConfig cfgp; + buramStart(&BURAMD1, &cfgp); + + led_off(); + test_rtc(); + test_rtc_alarm(); + led_on(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + osDelay(1000); + } +} \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/BURTC_BURAM/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/Makefile b/testhal/SILABS/EFR32FG23x0xx/DMA/Makefile new file mode 100644 index 0000000000..a64658f137 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/Makefile @@ -0,0 +1,201 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS_CONTRIB)/os/various/bitmap.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) \ + $(CHIBIOS_CONTRIB)/os/various + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DEFR32FG23B010F512IM48=1 \ + -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE \ + -DEFR32_DMA_REQUIRED + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/halconf.h new file mode 100644 index 0000000000..fb9cef69c4 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/halconf_community.h new file mode 100644 index 0000000000..04bffb1565 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 FALSE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 FALSE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 FALSE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/mcuconf.h new file mode 100644 index 0000000000..48aa277ad9 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/cfg/mcuconf.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_EM01GRPCCLK + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 TRUE +#define EFR32_SIO_USE_EUSART2 TRUE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/main.c b/testhal/SILABS/EFR32FG23x0xx/DMA/main.c new file mode 100644 index 0000000000..1938c51f6b --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/main.c @@ -0,0 +1,151 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "cmsis_os.h" +#include "hal.h" +#include "hal_buram.h" + +static void led_on(void) +{ + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) +{ + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static int dma_calback_triggered; + +static void dma_callback(void *ptr, uint32_t mask) +{ + + (void)ptr; + (void)mask; + + dma_calback_triggered++; +} + +static void test_dma_check_stream_allocation(void) +{ + + /* Check stream allocation. */ + const efr32_dma_stream_t *dmastp[EFR32_DMA_STREAMS + 1] = { + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + + dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, NULL, NULL), + }; + + for (unsigned i = 0; i < EFR32_DMA_STREAMS; i++) + { + osalDbgCheck(dmastp[i] != NULL); + } + + /* Can't allocate more channels. */ + osalDbgCheck(dmastp[EFR32_DMA_STREAMS] == NULL); + + for (unsigned i = 0; i < EFR32_DMA_STREAMS; i++) + { + dmaStreamFree(dmastp[i]); + } +} + +static void test_dma_check_data_transfer(void) +{ + + /* Check data transfer. */ + uint8_t dma_test_src[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 8, 7, 6, 5, 4, 3, 2, 1 }; + uint8_t dma_test_dst[32] = { 0 }; + + const efr32_dma_stream_t *dmastp1 = dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, dma_callback, &dma_test_dst[0]); + const efr32_dma_stream_t *dmastp2 = dmaStreamAlloc(EFR32_DMA_STREAM_ID_ANY, 4, dma_callback, &dma_test_dst[16]); + + dmaStartMemCopy(dmastp1, 0, &dma_test_src[0], &dma_test_dst[0], 8); + dmaStartMemCopy(dmastp2, 0, &dma_test_src[8], &dma_test_dst[16], 8); + + dmaWaitCompletion(dmastp1); + dmaWaitCompletion(dmastp2); + + dmaStreamFree(dmastp1); + dmaStreamFree(dmastp2); + + for (size_t i = 0; i < 8; i++) + { + osalDbgCheck(dma_test_src[i] == dma_test_dst[i]); + osalDbgCheck(dma_test_src[i + 8] == dma_test_dst[i + 16]); + } + + for (size_t i = 8; i < 16; i++) + { + osalDbgCheck(dma_test_dst[i] == 0); + osalDbgCheck(dma_test_dst[i + 16] == 0); + } + + /* Check number of callbacks. */ + osalDbgCheck(dma_calback_triggered == 2); +} + +/* + * Application entry point. + */ +int main(void) +{ + + int unused = 0; + (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + led_off(); + test_dma_check_stream_allocation(); + test_dma_check_data_transfer(); + led_on(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) + { + osDelay(1000); + } +} \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/DMA/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/DMA/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/DMA/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/Makefile b/testhal/SILABS/EFR32FG23x0xx/GPIO/Makefile new file mode 100644 index 0000000000..53d4a5f536 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE \ + -DEFR32FG23B010F512IM48=1 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/halconf.h new file mode 100644 index 0000000000..6dc050152d --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/halconf.h @@ -0,0 +1,553 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/halconf_community.h new file mode 100644 index 0000000000..04bffb1565 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 FALSE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 FALSE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 FALSE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/mcuconf.h new file mode 100644 index 0000000000..ce0f78facc --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/cfg/mcuconf.h @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED TRUE +#define EFR32_ULFRCO_ENABLED TRUE +#define EFR32_HFRCO_ENABLED TRUE +#define EFR32_FSRCO_ENABLED TRUE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED TRUE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_LFXO + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 FALSE +#define EFR32_SIO_USE_EUSART2 FALSE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 FALSE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/main.c b/testhal/SILABS/EFR32FG23x0xx/GPIO/main.c new file mode 100644 index 0000000000..0dfedbabd6 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/main.c @@ -0,0 +1,219 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "cmsis_os.h" +#include "hal.h" + +static void led_on(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static int gpio_callback_counter; + +static void gpio_callback(void* arg) { + + int *cnt = arg; + (void)cnt; + + *cnt = *cnt + 1; +} + +static void test_clock_clkout2(void) { + + /* Clock output 2 works only on ports A or B. */ + + /* FRSCO clock is on PA7: 20 MHz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_FSRCO)); + + /* HFXO clock is on PA7: 39 MHz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_HFXO)); + + /* HFRCODPLL clock is on PA7: 19 MHz. */ + palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_HFRCODPLL)); + + /* HFRCOEM23 clock is on PA7: 19 MHz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_HFRCOEM23)); + + /* LFXO clock is on PA7: 32768 Hz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_LFXO)); + + /* LFRCO clock is on PA7: 32768 Hz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_LFRCO)); + + /* ULFRCO clock is on PA7: 1000 Hz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_ULFRCO)); + + /* HCLK clock is present on PA7: 19 MHz. */ + //palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT2_HCLK)); + + /* TODO: The clock should be measured by timer. */ +} + +static void test_clock_clkout1(void) { + + /* Clock output 1 works only on ports C or D. */ + + + /* FRSCO clock is on PA7: 20 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_FSRCO)); + + /* HFXO clock is on PA7: 39 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_HFXO)); + + /* HFRCODPLL clock is on PA7: 19 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_HFRCODPLL)); + + /* HFRCOEM23 clock is on PA7: 19 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_HFRCOEM23)); + + /* LFXO clock is on PA7: 32768 Hz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_LFXO)); + + /* LFRCO clock is on PA7: 32768 Hz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_LFRCO)); + + /* ULFRCO clock is on PA7: 1000 Hz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_ULFRCO)); + + /* HCLK clock is present on PA7: 19 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT1_HCLK)); + + /* TODO: The clock should be measured by timer. */ +} + +static void test_clock_clkout0(void) { + + /* Clock output 0 works only on ports C or D. */ + + /* FRSCO clock is on PA7: 20 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_FSRCO)); + + /* HFXO clock is on PA7: 39 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_HFXO)); + + /* HFRCODPLL clock is on PA7: 19 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_HFRCODPLL)); + + /* HFRCOEM23 clock is on PA7: 19 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_HFRCOEM23)); + + /* LFXO clock is on PA7: 32768 Hz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_LFXO)); + + /* LFRCO clock is on PA7: 32768 Hz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_LFRCO)); + + /* ULFRCO clock is on PA7: 1000 Hz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_ULFRCO)); + + /* HCLK clock is present on PA7: 19 MHz. */ + //palSetPadMode(GPIOC, 7, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(CLKOUT0_HCLK)); + + /* TODO: The clock should be measured by timer. */ +} + +static void test_gpio(void) { + + uint32_t pin_states; + (void)pin_states; + + gpio_callback_counter = 0; + + /* PB1 = BUTTON0. */ + palSetPadMode(GPIOB, 1, PAL_MODE_INPUT); + palSetPadCallback(GPIOB, 1, gpio_callback, &gpio_callback_counter); + palEnablePadEvent(GPIOB, 1, PAL_EVENT_MODE_BOTH_EDGES); + + /* PA5 = BUTTON1. */ + palSetPadMode(GPIOA, 5, PAL_MODE_OUTPUT_PUSHPULL); + + /* PB1 must be connected to PA5 via jumper wire. */ + palWritePad(GPIOA, 5, PAL_HIGH); + pin_states = palReadPad(GPIOB, 1); + osalDbgCheck(pin_states == PAL_HIGH); + + palWritePad(GPIOA, 5, PAL_LOW); + pin_states = palReadPad(GPIOB, 1); + osalDbgCheck(pin_states == PAL_LOW); + + palSetPad(GPIOA, 5); + pin_states = palReadPad(GPIOB, 1); + osalDbgCheck(pin_states == PAL_HIGH); + + palClearPad(GPIOA, 5); + pin_states = palReadPad(GPIOB, 1); + osalDbgCheck(pin_states == PAL_LOW); + + palTogglePad(GPIOA, 5); + pin_states = palReadPad(GPIOB, 1); + osalDbgCheck(pin_states == PAL_HIGH); + + palTogglePad(GPIOA, 5); + pin_states = palReadPad(GPIOB, 1); + osalDbgCheck(pin_states == PAL_LOW); + + palDisablePadEvent(GPIOB, 1); + palSetPadMode(GPIOB, 1, PAL_MODE_RESET); + palSetPadMode(GPIOA, 5, PAL_MODE_RESET); + + osalDbgAssert(gpio_callback_counter == 6, "Bug ON"); +} + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + led_off(); + test_clock_clkout2(); + test_clock_clkout1(); + test_clock_clkout0(); + test_gpio(); + led_on(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + osDelay(1000); + } +} diff --git a/testhal/SILABS/EFR32FG23x0xx/GPIO/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/GPIO/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/GPIO/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/Makefile b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/Makefile new file mode 100644 index 0000000000..b64592d702 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/Makefile @@ -0,0 +1,229 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +include $(CHIBIOS_CONTRIB)/ext/xmlmbus/xmlmbus_chibios.mk +include emlib/emlib.mk +include raillib/raillib.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS_CONTRIB)/os/various/bitmap.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) \ + $(CHIBIOS_CONTRIB)/os/various + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DCORTEX_ENABLE_WFI_IDLE + +# MCU and board specific. +UDEFS += \ + -DEFR32FG23B010F512IM48=1 \ + -DESCAPE_HATCH_ENABLE=TRUE + +# emlib specific. +UDEFS += \ + -DSYSTEM_NO_STATIC_MEMORY \ + -DFSRCO_FREQ=20000000UL \ + -DHFXO_FREQ=39000000UL \ + -DFRCODPLL_STARTUP_FREQ=19000000UL \ + -DRCODPLL_MAX_FREQ=0000000UL \ + -DCLKIN0_FREQ=0UL \ + -DLFRCO_FREQ=32768UL \ + -DULFRCO_FREQ=1000UL \ + -DLFXO_FREQ=LFRCO_FREQ +# -DSL_TRUSTZONE_NONSECURE +# -DSL_TRUSTZONE_SECURE \ + +# RAIL lib specific. +UDEFS += \ + -D_SILICON_LABS_32B_SERIES_1_CONFIG=0 \ + -DSL_RAIL_UTIL_PROTOCOL_IEEE802154_GB868_ENABLE=0 \ + -DFEAT_RF_2G4=0 \ + -DFEAT_RF_SUBG=1 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/radio/rail_lib/common \ + $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/radio/rail_lib/chip/efr32/efr32xg2x + +# List the user directory to look for the libraries here +ULIBDIR = $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/radio/rail_lib/autogen/librail_release + +# List all user libraries here +ULIBS = -l:librail_efr32xg23_gcc_release.a + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/halconf.h new file mode 100644 index 0000000000..0ecdc33c4e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/halconf_community.h new file mode 100644 index 0000000000..e0350ac110 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 TRUE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 FALSE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 FALSE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/mcuconf.h new file mode 100644 index 0000000000..3116692344 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/cfg/mcuconf.h @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG23 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_HFRCO_ENABLED TRUE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED TRUE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFXO +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_EM01GRPCCLK + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 TRUE +#define EFR32_SIO_USE_EUSART2 TRUE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib.mk b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib.mk new file mode 100644 index 0000000000..409e60f557 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib.mk @@ -0,0 +1,59 @@ +# Required platform files. +GECKO_SDK = $(CHIBIOS_CONTRIB)/ext/gecko_sdk + +EMLIBSRC = \ + emlib/emlib_chibios.c \ + $(GECKO_SDK)/platform/emlib/src/em_acmp.c \ + $(GECKO_SDK)/platform/emlib/src/em_adc.c \ + $(GECKO_SDK)/platform/emlib/src/em_aes.c \ + $(GECKO_SDK)/platform/emlib/src/em_burtc.c \ + $(GECKO_SDK)/platform/emlib/src/em_can.c \ + $(GECKO_SDK)/platform/emlib/src/em_cmu.c \ + $(GECKO_SDK)/platform/emlib/src/em_cmu_fpga.c \ + $(GECKO_SDK)/platform/emlib/src/em_cryotimer.c \ + $(GECKO_SDK)/platform/emlib/src/em_crypto.c \ + $(GECKO_SDK)/platform/emlib/src/em_csen.c \ + $(GECKO_SDK)/platform/emlib/src/em_dac.c \ + $(GECKO_SDK)/platform/emlib/src/em_dbg.c \ + $(GECKO_SDK)/platform/emlib/src/em_dma.c \ + $(GECKO_SDK)/platform/emlib/src/em_ebi.c \ + $(GECKO_SDK)/platform/emlib/src/em_emu.c \ + $(GECKO_SDK)/platform/emlib/src/em_eusart.c \ + $(GECKO_SDK)/platform/emlib/src/em_gpcrc.c \ + $(GECKO_SDK)/platform/emlib/src/em_gpio.c \ + $(GECKO_SDK)/platform/emlib/src/em_i2c.c \ + $(GECKO_SDK)/platform/emlib/src/em_iadc.c \ + $(GECKO_SDK)/platform/emlib/src/em_idac.c \ + $(GECKO_SDK)/platform/emlib/src/em_lcd.c \ + $(GECKO_SDK)/platform/emlib/src/em_ldma.c \ + $(GECKO_SDK)/platform/emlib/src/em_lesense.c \ + $(GECKO_SDK)/platform/emlib/src/em_letimer.c \ + $(GECKO_SDK)/platform/emlib/src/em_leuart.c \ + $(GECKO_SDK)/platform/emlib/src/em_msc.c \ + $(GECKO_SDK)/platform/emlib/src/em_opamp.c \ + $(GECKO_SDK)/platform/emlib/src/em_pcnt.c \ + $(GECKO_SDK)/platform/emlib/src/em_pdm.c \ + $(GECKO_SDK)/platform/emlib/src/em_prs.c \ + $(GECKO_SDK)/platform/emlib/src/em_qspi.c \ + $(GECKO_SDK)/platform/emlib/src/em_rmu.c \ + $(GECKO_SDK)/platform/emlib/src/em_rtc.c \ + $(GECKO_SDK)/platform/emlib/src/em_rtcc.c \ + $(GECKO_SDK)/platform/emlib/src/em_se.c \ + $(GECKO_SDK)/platform/emlib/src/em_system.c \ + $(GECKO_SDK)/platform/emlib/src/em_timer.c \ + $(GECKO_SDK)/platform/emlib/src/em_usart.c \ + $(GECKO_SDK)/platform/emlib/src/em_vcmp.c \ + $(GECKO_SDK)/platform/emlib/src/em_vdac.c \ + $(GECKO_SDK)/platform/emlib/src/em_wdog.c + +#EMLIBSRC += $(GECKO_SDK)/platform/emlib/src/em_core.c +#EMLIBSRC += $(GECKO_SDK)/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c + +EMLIBINC = \ + emlib \ + $(GECKO_SDK)/platform/common/inc \ + $(GECKO_SDK)/platform/emlib/inc + +# Shared variables +ALLCSRC += $(EMLIBSRC) +ALLINC += $(EMLIBINC) diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib_chibios.c b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib_chibios.c new file mode 100644 index 0000000000..34431c6aa5 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib_chibios.c @@ -0,0 +1,32 @@ +#include "hal.h" +#include "em_core_generic.h" + +CORE_irqState_t CORE_EnterCritical(void) { + + return (chSysGetStatusAndLockX()); +} + +void CORE_ExitCritical(CORE_irqState_t irqState) { + + chSysRestoreStatusX(irqState); +} + +CORE_irqState_t CORE_EnterAtomic(void) { + + return (chSysGetStatusAndLockX()); +} + +void CORE_ExitAtomic(CORE_irqState_t irqState) { + + chSysRestoreStatusX(irqState); +} + +#if 0 +void _start(void) { + + extern int main(void); + main(); + NVIC_SystemReset(); +} +#endif + diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib_chibios.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib_chibios.h new file mode 100644 index 0000000000..013d94c8d9 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/emlib/emlib_chibios.h @@ -0,0 +1,22 @@ +#ifndef EMLIB_CHIBIOS_H +#define EMLIB_CHIBIOS_H + +#include "em_acmp.h" +#include "em_assert.h" +#include "em_cryotimer.h" +#include "em_chip.h" +#include "em_cmu.h" +#include "em_emu.h" +#include "em_eusart.h" +#include "em_gpio.h" +#include "em_letimer.h" +#include "em_lcd.h" +#include "em_pcnt.h" +#include "em_prs.h" +#include "em_lesense.h" +#include "em_system.h" +#include "em_syscfg.h" +#include "em_vdac.h" + +#endif /* EMLIB_CHIBIOS_H */ + diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/main.c b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/main.c new file mode 100644 index 0000000000..63728305cf --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/main.c @@ -0,0 +1,217 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "cmsis_os.h" +#include "hal.h" + +#include "rail.h" +#include "sli_rail_util_callbacks.h" // for internal-only callback signatures +#include "sl_rail_util_init.h" +#include "sl_rail_util_protocol.h" + +static void led_on(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static void led_toggle(void) { + + /* PB2 = LED */ + palTogglePad(GPIOB, 2); +} + +void st_callback(unsigned alarm) { + + stStopAlarmN(alarm); + stStartAlarmN(alarm, stGetCounter() + chTimeMS2I(3000)); +} + +extern const RAIL_ChannelConfig_t *channelConfigs[]; + +static RAIL_Handle_t railHandle; + +enum { + WMBUS_MODE_T1A = 0, + WMBUS_MODE_C1A = 1, + WMBUS_MODE_S1 = 2 +}; + +static void send_datagram(void) { + + static const uint8_t wmbus_datagram_1[] = { + 0x31, 0x44, 0x93, 0x44, 0x48, 0x32, 0x75, 0x26, 0x35, 0x08, // 0x6D, 0x95, + 0x7A, 0xA3, 0x00, 0x00, 0x20, 0x0B, 0x6E, 0x16, 0x00, 0x00, 0x4B, 0x6E, 0x21, 0x02, 0x00, 0x42, // 0x91, 0xDD, + 0x6C, 0xBF, 0x2A, 0xCB, 0x08, 0x6E, 0x16, 0x00, 0x00, 0xC2, 0x08, 0x6C, 0xDE, 0x29, 0x32, 0x6C, // 0x8C, 0xC4, + 0xFF, 0xFF, 0x04, 0x6D, 0x27, 0x0E, 0xD2, 0x2A, // 0x3D, 0x89 + }; + + CC_ALIGN_DATA(16)static uint8_t railFifo[1024]; + + static int config_nr = WMBUS_MODE_T1A; + const RAIL_ChannelConfig_t *channel_config = channelConfigs[config_nr]; + config_nr = (config_nr + 1) % 3; + (void)RAIL_ConfigChannels(railHandle, channel_config, + &sli_rail_util_on_channel_config_change); + + led_toggle(); + + #define RAIL_CHANNEL_0 0 + memcpy(railFifo, wmbus_datagram_1, sizeof(wmbus_datagram_1)); + RAIL_SetTxFifo(railHandle, railFifo, sizeof(wmbus_datagram_1), sizeof(railFifo)); + RAIL_StartTx(railHandle, RAIL_CHANNEL_0, RAIL_TX_OPTIONS_DEFAULT, NULL); +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_assert_failed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code) { + + (void)rail_handle; + (void)error_code; + osalDbgAssert(false, "rail_handle with error_code"); +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_rf_ready(RAIL_Handle_t rail_handle) { + + (void)rail_handle; +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) { + + (void)rail_handle; + (void)entry; +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events) { + + (void)rail_handle; + (void)events; +} + +void custom_RAIL_Init(void) { + + RAIL_Status_t status; + (void)status; + + RAIL_Config_t sl_rail_config = { + .eventsCallback = &sli_rail_util_on_event, + // Other fields are ignored nowadays + }; + railHandle = RAIL_Init(&sl_rail_config, &sli_rail_util_on_rf_ready); + + RAIL_DataConfig_t data_config = { + .txSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_SOURCE, + .rxSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_SOURCE, + .txMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_MODE, + .rxMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_MODE, + }; + status = RAIL_ConfigData(railHandle, &data_config); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + const RAIL_ChannelConfig_t *channel_config = channelConfigs[WMBUS_MODE_C1A]; + + (void)RAIL_ConfigChannels(railHandle, + channel_config, + &sli_rail_util_on_channel_config_change); + status = sl_rail_util_protocol_config(railHandle, + SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + status = RAIL_ConfigCal(railHandle, + 0U + | (SL_RAIL_UTIL_INIT_CALIBRATION_TEMPERATURE_NOTIFY_INST0_ENABLE + ? RAIL_CAL_TEMP : 0U) + | (SL_RAIL_UTIL_INIT_CALIBRATION_ONETIME_NOTIFY_INST0_ENABLE + ? RAIL_CAL_ONETIME : 0U)); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + status = RAIL_ConfigEvents(railHandle, RAIL_EVENTS_ALL, + SL_RAIL_UTIL_INIT_EVENT_INST0_MASK); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + RAIL_StateTransitions_t tx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_ERROR + }; + status = RAIL_SetTxTransitions(railHandle, + &tx_transitions); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + RAIL_StateTransitions_t rx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_ERROR + }; + status = RAIL_SetRxTransitions(railHandle, + &rx_transitions); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); +} + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; + (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + led_off(); + custom_RAIL_Init(); + stSetCallback(1, st_callback); + stStartAlarmN(1, stGetCounter() + chTimeMS2I(3000)); + led_on(); + + //RAIL_TxStreamStart(railHandle, RAIL_STREAM_PN9_STREAM); + //RAIL_TxStreamStart(railHandle, RAIL_STREAM_CARRIER_WAVE); + + systime_t prev = chVTGetSystemTime(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + send_datagram(); + prev = chThdSleepUntilWindowed(prev, chTimeAddX(prev, TIME_MS2I(3000))); + } +} + diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/radioconf_generation_log.json b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/radioconf_generation_log.json new file mode 100644 index 0000000000..c4f4bcfba1 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/radioconf_generation_log.json @@ -0,0 +1,706 @@ +[ + { + "channel_name": "wmbus_mode_t-m2o_mode_t", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "0000111101" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 330000 + }, + { + "name": "Desired Bitrate [bps]", + "value": 99999 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 100000.0 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868949980 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 214977 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 99999.99999999999 + }, + { + "name": "Actual Deviation [Hz]", + "value": 50372.22057580948 + }, + { + "name": "Target Modulation Index", + "value": 1.000010000100001 + }, + { + "name": "Actual Modulation Index", + "value": 1.0074444115161896 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 199999 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 199999 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 330000 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 9.285714285714288 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 5 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 169.820512974359 + } + ] + }, + { + "channel_name": "wmbus_mode_t-o2m_mode_t", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "000111011010010110" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 333487 + }, + { + "name": "Desired Bitrate [bps]", + "value": 32768 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 32767.999445637863 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868299990 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 216737 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 32765.836028152942 + }, + { + "name": "Actual Deviation [Hz]", + "value": 49925.92823691666 + }, + { + "name": "Target Modulation Index", + "value": 3.0517578125 + }, + { + "name": "Actual Modulation Index", + "value": 3.047236882419009 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 185714 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 28.33962264150943 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 2 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 416.0556363415578 + } + ] + }, + { + "channel_name": "wmbus_mode_c-m2o_mode_c", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "00001111010101010011001101" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 314896 + }, + { + "name": "Desired Bitrate [bps]", + "value": 100000 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 100000.0 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -12.446100897895253 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868949980 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 207439 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 100000.75120756615 + }, + { + "name": "Actual Deviation [Hz]", + "value": 44862.75895033032 + }, + { + "name": "Target Modulation Index", + "value": 0.9 + }, + { + "name": "Actual Modulation Index", + "value": 0.8972551790066063 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.TRECS_VITERBI" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 190000 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 110000 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 162500 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 7.0 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 700005.2584529631 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 7 + }, + { + "name": "Effective Syncword Length", + "value": 32 + }, + { + "name": "Effective Preamble Length", + "value": 32 + }, + { + "name": "Number of Bits Used from Preamble to Syncword [bits]", + "value": 6 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "TRECS syncword timeout [us]", + "value": 770.0 + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 179.22578646314105 + } + ] + }, + { + "channel_name": "wmbus_mode_c-o2m_mode_c", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "00001111010101010011001101" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 166896 + }, + { + "name": "Desired Bitrate [bps]", + "value": 50000 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 50000.0 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -14.178302025260141 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868949980 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 133424 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 49999.88262497506 + }, + { + "name": "Actual Deviation [Hz]", + "value": 24689.509154995903 + }, + { + "name": "Target Modulation Index", + "value": 1.0 + }, + { + "name": "Actual Modulation Index", + "value": 0.9875803661998361 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.TRECS_SLICER" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 100000 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 100000 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 100000 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 7.000000000000001 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 349999.1783748254 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 8 + }, + { + "name": "Effective Syncword Length", + "value": 32 + }, + { + "name": "Effective Preamble Length", + "value": 32 + }, + { + "name": "Number of Bits Used from Preamble to Syncword [bits]", + "value": 6 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "TRECS syncword timeout [us]", + "value": 1540.0 + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 357.7993666402244 + } + ] + }, + { + "channel_name": "wmbus_mode_s-m2o_mode_s", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "0101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "000111011010010110" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 333487 + }, + { + "name": "Desired Bitrate [bps]", + "value": 32768 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 32767.999445637863 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868299990 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 216737 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 32765.836028152942 + }, + { + "name": "Actual Deviation [Hz]", + "value": 49925.92823691666 + }, + { + "name": "Target Modulation Index", + "value": 3.0517578125 + }, + { + "name": "Actual Modulation Index", + "value": 3.047236882419009 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 185714 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 28.33962264150943 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 2 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 416.0556363415578 + } + ] + }, + { + "channel_name": "wmbus_mode_s-o2m_mode_s", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "0101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "000111011010010110" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 333487 + }, + { + "name": "Desired Bitrate [bps]", + "value": 32768 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 32767.999445637863 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868299990 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 216737 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 32765.836028152942 + }, + { + "name": "Actual Deviation [Hz]", + "value": 49925.92823691666 + }, + { + "name": "Target Modulation Index", + "value": 3.0517578125 + }, + { + "name": "Actual Modulation Index", + "value": 3.047236882419009 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 185714 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 28.33962264150943 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 2 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 416.0556363415578 + } + ] + } +] \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/rail_config.c b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/rail_config.c new file mode 100644 index 0000000000..39d7e1fb24 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/rail_config.c @@ -0,0 +1,1225 @@ +/***************************************************************************//** + * @brief RAIL Configuration + * @details + * WARNING: Auto-Generated Radio Config - DO NOT EDIT + * Radio Configurator Version: 2402.6.1 + * RAIL Adapter Version: 2.4.33 + * RAIL Compatibility: 2.x + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" +#include "rail_config.h" + +uint32_t RAILCb_CalcSymbolRate(RAIL_Handle_t railHandle) +{ + (void) railHandle; + return 0U; +} + +uint32_t RAILCb_CalcBitRate(RAIL_Handle_t railHandle) +{ + (void) railHandle; + return 0U; +} + +void RAILCb_ConfigFrameTypeLength(RAIL_Handle_t railHandle, + const RAIL_FrameType_t *frameType) +{ + (void) railHandle; + (void) frameType; +} + +uint32_t frameCodingTable[] = { + 2155905152, 2155905152, 58753152, 2147615104, + 125862016, 2147909760, 2147485056, 2155905028, + 192970880, 2148142976, 2155874688, 2155905032, + 2148404608, 2155905036, 2155905152, 2155905152, + 185470234, 320215324, 589703468, 624046388, +}; + +static const uint8_t irCalConfig[] = { + 20, 41, 2, 0, 0, 49, 17, 0, 0, 0, 1, 0, 2, 100, 0, 1, 1, 47, 0, 0, 7 +}; + +static const int32_t timingConfig_0[] = { + 23455, 23455, 5000, 0 +}; + +static const int32_t timingConfig_1[] = { + 23455, 23455, 15259, 0 +}; + +static const int32_t timingConfig_2[] = { + 64447, 64447, 5000, 0 +}; + +static const int32_t timingConfig_3[] = { + 48093, 48093, 20000, 0 +}; + +static const uint8_t hfxoRetimingConfigEntries[] = { + 1, 0, 0, 0, 0xc0, 0x17, 0x53, 0x02, 4, 12, 0, 0, 0xe0, 0x02, 0, 0, 0, 0, 0x3c, 0x03, 1, 2, 5, 4, 0x98, 0x03, 1, 2, 5, 5, 0xf4, 0x03, 1, 2, 6, 5 +}; + +static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr_0 = { +#if RAIL_SUPPORTS_OFDM_PA + { +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL } + } +#else // RAIL_SUPPORTS_OFDM_PA +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS +#endif // RAIL_SUPPORTS_OFDM_PA +}; + +static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr_1 = { +#if RAIL_SUPPORTS_OFDM_PA + { +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL } + } +#else // RAIL_SUPPORTS_OFDM_PA +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS +#endif // RAIL_SUPPORTS_OFDM_PA +}; + +static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr_2 = { +#if RAIL_SUPPORTS_OFDM_PA + { +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL } + } +#else // RAIL_SUPPORTS_OFDM_PA +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS +#endif // RAIL_SUPPORTS_OFDM_PA +}; + +static const uint32_t phyInfo_0[] = { + 17UL, + 0x00539782UL, // 83.59183673469387 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_0, + 0x00000000UL, + 8UL, + 0UL, + 100000UL, + 0x00F50101UL, + 0x071021DEUL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 99999UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +static const uint32_t phyInfo_1[] = { + 17UL, + 0x00492492UL, // 73.14285714285714 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_1, + 0x00000000UL, + 8UL, + 0UL, + 32767UL, + 0x00F50201UL, + 0x07102225UL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 32765UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +static const uint32_t phyInfo_2[] = { + 17UL, + 0x00400000UL, // 64.0 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_2, + 0x00000000UL, + 8UL, + 0UL, + 100000UL, + 0x00F40101UL, + 0x075020AEUL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 100000UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +static const uint32_t phyInfo_3[] = { + 17UL, + 0x00369D03UL, // 54.61333333333334 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_3, + 0x00000000UL, + 8UL, + 0UL, + 50000UL, + 0x00F20101UL, + 0x07101505UL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 49999UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +const uint32_t wmbus_mode_t_modemConfigBase[] = { + 0x0002400CUL, 0x000A8001UL, + /* 4010 */ 0x000040FFUL, + 0x00024020UL, 0x00000000UL, + /* 4024 */ 0x00000000UL, + 0x00034040UL, (uint32_t) &frameCodingTable, + /* 4044 */ 0x00004000UL, + /* 4048 */ 0x000007A4UL, + 0x0002405CUL, 0x00000000UL, + /* 4060 */ 0x00000000UL, + 0x000140A8UL, 0x00000007UL, + 0x000440BCUL, 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + 0x00044108UL, 0x00004C09UL, + /* 410C */ 0x00004C0FUL, + /* 4110 */ 0x00004D09UL, + /* 4114 */ 0x00004D0FUL, + 0x1001C020UL, 0x0007F800UL, + 0x3001C020UL, 0x002801FEUL, + 0x1001C024UL, 0x000000FFUL, + 0x3001C024UL, 0x00001300UL, + 0x0005C028UL, 0x03B380ECUL, + /* C02C */ 0x51407543UL, + /* C030 */ 0xF8000FA0UL, + /* C034 */ 0x00004030UL, + /* C038 */ 0x0007AAA8UL, + 0x0002C040UL, 0x00000000UL, + /* C044 */ 0x00000000UL, + 0x000FC068UL, 0x0002C688UL, + /* C06C */ 0x00000520UL, + /* C070 */ 0x000010BAUL, + /* C074 */ 0x003F0000UL, + /* C078 */ 0x00EE008DUL, + /* C07C */ 0x03AC01F6UL, + /* C080 */ 0x079604F5UL, + /* C084 */ 0x0D9C09DEUL, + /* C088 */ 0x179311C3UL, + /* C08C */ 0x26F51DFEUL, + /* C090 */ 0x3FFF32BDUL, + /* C094 */ 0x1BF815FEUL, + /* C098 */ 0x2DB423DCUL, + /* C09C */ 0x3FFF39D0UL, + /* C0A0 */ 0x00003FFFUL, + 0x0005C0A8UL, 0x15724BBDUL, + /* C0AC */ 0x0518A311UL, + /* C0B0 */ 0x76543210UL, + /* C0B4 */ 0x00000A98UL, + /* C0B8 */ 0x00000000UL, + 0x0004C0CCUL, 0x000000EEUL, + /* C0D0 */ 0x00000000UL, + /* C0D4 */ 0x000A0001UL, + /* C0D8 */ 0x00280001UL, + 0x01010008UL, 0x000007A6UL, + 0x01010018UL, 0x00000000UL, + 0x01010020UL, 0x0000A6BCUL, + 0x01124090UL, 0x00000000UL, + /* 4094 */ 0x00000000UL, + /* 4098 */ 0x00000000UL, + /* 409C */ 0x00000000UL, + /* 40A0 */ 0x00000000UL, + /* 40A4 */ 0x00000000UL, + /* 40A8 */ 0x00000000UL, + /* 40AC */ 0x00000000UL, + /* 40B0 */ 0x00000000UL, + /* 40B4 */ 0x00000000UL, + /* 40B8 */ 0x00000000UL, + /* 40BC */ 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + /* 40CC */ 0x00000000UL, + /* 40D0 */ 0x00000000UL, + /* 40D4 */ 0x00000000UL, + 0x110140E0UL, 0x000001F8UL, + 0x310140E0UL, 0x00000201UL, + 0x01024110UL, 0x00051E33UL, + /* 4114 */ 0x00000000UL, + 0x0108411CUL, 0x04000000UL, + /* 4120 */ 0x00000000UL, + /* 4124 */ 0x078304FFUL, + /* 4128 */ 0x3AC81388UL, + /* 412C */ 0x0C6606FFUL, + /* 4130 */ 0x078304FFUL, + /* 4134 */ 0x03FF1388UL, + /* 4138 */ 0xF00A20BCUL, + 0x0102414CUL, 0x00003B80UL, + /* 4150 */ 0x00000000UL, + 0x01024158UL, 0x00000000UL, + /* 415C */ 0x0000FDFFUL, + 0x01014164UL, 0x0000010CUL, + 0x010B416CUL, 0x40000000UL, + /* 4170 */ 0x00000000UL, + /* 4174 */ 0x00000000UL, + /* 4178 */ 0x00000000UL, + /* 417C */ 0x00000000UL, + /* 4180 */ 0x00000000UL, + /* 4184 */ 0x00000101UL, + /* 4188 */ 0x00000000UL, + /* 418C */ 0x00000000UL, + /* 4190 */ 0x00000000UL, + /* 4194 */ 0x00000000UL, + 0x010241A4UL, 0x00000000UL, + /* 41A8 */ 0x00000000UL, + 0x010841B0UL, 0x00000000UL, + /* 41B4 */ 0x00200000UL, + /* 41B8 */ 0x00000000UL, + /* 41BC */ 0x00000000UL, + /* 41C0 */ 0x003C0000UL, + /* 41C4 */ 0x0006AAAAUL, + /* 41C8 */ 0x00000000UL, + /* 41CC */ 0x00000000UL, + 0x010341D4UL, 0x000001D0UL, + /* 41D8 */ 0x00020000UL, + /* 41DC */ 0x00000000UL, + 0x010741E4UL, 0x1492F42DUL, + /* 41E8 */ 0x003858D3UL, + /* 41EC */ 0x007AFDBEUL, + /* 41F0 */ 0x0041732CUL, + /* 41F4 */ 0x0DD53E7FUL, + /* 41F8 */ 0x03283A26UL, + /* 41FC */ 0x302424E2UL, + 0x01064220UL, 0x00000000UL, + /* 4224 */ 0x8000FFFFUL, + /* 4228 */ 0x00000000UL, + /* 422C */ 0x40001860UL, + /* 4230 */ 0x00000000UL, + /* 4234 */ 0x00000000UL, + 0x0101423CUL, 0x00000000UL, + 0x01034244UL, 0x00000014UL, + /* 4248 */ 0x00000000UL, + /* 424C */ 0x04000008UL, + 0x01018010UL, 0x00000003UL, + 0x0103809CUL, 0x00000000UL, + /* 80A0 */ 0x0003B870UL, + /* 80A4 */ 0x0003B870UL, + 0x110180A8UL, 0x000001F6UL, + 0x310180A8UL, 0x01014201UL, + 0x110180ACUL, 0x000001F6UL, + 0x310180ACUL, 0x01014201UL, + 0x010280B0UL, 0x02000300UL, + /* 80B4 */ 0x02000300UL, + 0x02030098UL, 0x00000000UL, + /* 009C */ 0x04000C00UL, + /* 00A0 */ 0x0000044CUL, + 0x020200D8UL, 0xAA400005UL, + /* 00DC */ 0x00000188UL, + 0x120100ECUL, 0x00000FE0UL, + 0x320100ECUL, 0x5151200DUL, + 0x020100F0UL, 0x0000052BUL, + 0x02010100UL, 0x00000110UL, + 0x12010104UL, 0x00000000UL, + 0x32010104UL, 0x00000110UL, + 0x12010110UL, 0x000FFF00UL, + 0x32010110UL, 0x42000002UL, + 0x1201012CUL, 0x001FFC00UL, + 0x3201012CUL, 0x008000A9UL, + 0x02010140UL, 0x0000003FUL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510063UL, + 0x02020168UL, 0x00060010UL, + /* 016C */ 0x00062000UL, + 0x02010174UL, 0x0C100169UL, + 0x12010178UL, 0x001C0000UL, + 0x32010178UL, 0xCFE00440UL, + 0x12010180UL, 0x00000779UL, + 0x32010180UL, 0x00000006UL, + 0x02020188UL, 0x00000090UL, + /* 018C */ 0x00000000UL, + 0x120101ACUL, 0x000001F8UL, + 0x320101ACUL, 0x00010204UL, + 0x020101B0UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t wmbus_mode_c_modemConfigBase[] = { + 0x0002400CUL, 0x000A8001UL, + /* 4010 */ 0x000040FFUL, + 0x00024020UL, 0x00000000UL, + /* 4024 */ 0x00000000UL, + 0x00074030UL, 0x00000000UL, + /* 4034 */ 0x00000000UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000000UL, + /* 4040 */ 0x00000000UL, + /* 4044 */ 0x00004000UL, + /* 4048 */ 0x000007A4UL, + 0x00014050UL, 0x00000000UL, + 0x0002405CUL, 0x00000000UL, + /* 4060 */ 0x00000000UL, + 0x000140A8UL, 0x00000007UL, + 0x000440BCUL, 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + 0x00044108UL, 0x00004C09UL, + /* 410C */ 0x00004C0FUL, + /* 4110 */ 0x00004D09UL, + /* 4114 */ 0x00004D0FUL, + 0x1001C020UL, 0x0007F800UL, + 0x3001C020UL, 0x002801FEUL, + 0x1001C024UL, 0x000000FFUL, + 0x3001C024UL, 0x00001300UL, + 0x0008C028UL, 0x03B380ECUL, + /* C02C */ 0x51407543UL, + /* C030 */ 0xF8000FA0UL, + /* C034 */ 0x00004030UL, + /* C038 */ 0x0007AAA8UL, + /* C03C */ 0x00000000UL, + /* C040 */ 0x00000000UL, + /* C044 */ 0x00000000UL, + 0x000DC070UL, 0x000010BAUL, + /* C074 */ 0x003F0000UL, + /* C078 */ 0x00EE008DUL, + /* C07C */ 0x03AC01F6UL, + /* C080 */ 0x079604F5UL, + /* C084 */ 0x0D9C09DEUL, + /* C088 */ 0x179311C3UL, + /* C08C */ 0x26F51DFEUL, + /* C090 */ 0x3FFF32BDUL, + /* C094 */ 0x1BF815FEUL, + /* C098 */ 0x2DB423DCUL, + /* C09C */ 0x3FFF39D0UL, + /* C0A0 */ 0x00003FFFUL, + 0x0005C0A8UL, 0x15724BBDUL, + /* C0AC */ 0x0518A311UL, + /* C0B0 */ 0x76543210UL, + /* C0B4 */ 0x00000A98UL, + /* C0B8 */ 0x00000000UL, + 0x0003C0D0UL, 0x00000000UL, + /* C0D4 */ 0x000A0001UL, + /* C0D8 */ 0x00280001UL, + 0x01010008UL, 0x000007A6UL, + 0x01010018UL, 0x00000000UL, + 0x01010020UL, 0x0000A6BCUL, + 0x01044058UL, 0x00000000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + 0x010F409CUL, 0x00000000UL, + /* 40A0 */ 0x00000000UL, + /* 40A4 */ 0x00000000UL, + /* 40A8 */ 0x00000000UL, + /* 40AC */ 0x00000000UL, + /* 40B0 */ 0x00000000UL, + /* 40B4 */ 0x00000000UL, + /* 40B8 */ 0x00000000UL, + /* 40BC */ 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + /* 40CC */ 0x00000000UL, + /* 40D0 */ 0x00000000UL, + /* 40D4 */ 0x00000000UL, + 0x110140E0UL, 0x000001F8UL, + 0x310140E0UL, 0x00000201UL, + 0x01024110UL, 0x00051E33UL, + /* 4114 */ 0x00000000UL, + 0x01074120UL, 0x00000000UL, + /* 4124 */ 0x078304FFUL, + /* 4128 */ 0x3AC81388UL, + /* 412C */ 0x0C6606FFUL, + /* 4130 */ 0x078304FFUL, + /* 4134 */ 0x03FF1388UL, + /* 4138 */ 0xF00A20BCUL, + 0x0102414CUL, 0x00403B89UL, + /* 4150 */ 0x800003C0UL, + 0x01024158UL, 0x00000000UL, + /* 415C */ 0x0000FDFFUL, + 0x01014164UL, 0x0000010CUL, + 0x010B416CUL, 0x40000000UL, + /* 4170 */ 0x00000000UL, + /* 4174 */ 0x00000000UL, + /* 4178 */ 0x00000000UL, + /* 417C */ 0x00000000UL, + /* 4180 */ 0x00000000UL, + /* 4184 */ 0x00000101UL, + /* 4188 */ 0x00000000UL, + /* 418C */ 0x00000000UL, + /* 4190 */ 0x00000000UL, + /* 4194 */ 0x00000000UL, + 0x010241A4UL, 0x00000000UL, + /* 41A8 */ 0x00000000UL, + 0x010941B0UL, 0x00000000UL, + /* 41B4 */ 0xC03F9658UL, + /* 41B8 */ 0x00000000UL, + /* 41BC */ 0x00000000UL, + /* 41C0 */ 0x003C0000UL, + /* 41C4 */ 0x0006AAAAUL, + /* 41C8 */ 0x00000000UL, + /* 41CC */ 0x00000000UL, + /* 41D0 */ 0x55555555UL, + 0x010241D8UL, 0x00C60007UL, + /* 41DC */ 0x00000000UL, + 0x010741E4UL, 0x11E107F9UL, + /* 41E8 */ 0x0005E9CCUL, + /* 41EC */ 0x006C8E32UL, + /* 41F0 */ 0x004EB132UL, + /* 41F4 */ 0x0E1C0182UL, + /* 41F8 */ 0x0265F774UL, + /* 41FC */ 0x3350259BUL, + 0x0107421CUL, 0x80000000UL, + /* 4220 */ 0x00000000UL, + /* 4224 */ 0x0000004DUL, + /* 4228 */ 0x00000000UL, + /* 422C */ 0x40001860UL, + /* 4230 */ 0x00000000UL, + /* 4234 */ 0x00000000UL, + 0x0101423CUL, 0x00000000UL, + 0x01024244UL, 0x00000014UL, + /* 4248 */ 0x00000000UL, + 0x010F4330UL, 0x00000000UL, + /* 4334 */ 0x00000000UL, + /* 4338 */ 0x00000000UL, + /* 433C */ 0x00000000UL, + /* 4340 */ 0x00000000UL, + /* 4344 */ 0x00000000UL, + /* 4348 */ 0x00000000UL, + /* 434C */ 0x00000000UL, + /* 4350 */ 0x00000000UL, + /* 4354 */ 0x00000000UL, + /* 4358 */ 0x00000000UL, + /* 435C */ 0x38000000UL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x00000000UL, + /* 4368 */ 0x58FF0000UL, + 0x01018010UL, 0x00000003UL, + 0x0103809CUL, 0x00000000UL, + /* 80A0 */ 0x0003B870UL, + /* 80A4 */ 0x0003B870UL, + 0x110180A8UL, 0x000001F6UL, + 0x310180A8UL, 0x01014201UL, + 0x110180ACUL, 0x000001F6UL, + 0x310180ACUL, 0x01014201UL, + 0x010280B0UL, 0x02000300UL, + /* 80B4 */ 0x02000300UL, + 0x02030098UL, 0x00000000UL, + /* 009C */ 0x04000C00UL, + /* 00A0 */ 0x0000044CUL, + 0x020200D8UL, 0xAA400005UL, + /* 00DC */ 0x00000188UL, + 0x120100ECUL, 0x00000FE0UL, + 0x320100ECUL, 0x5151200DUL, + 0x020100F0UL, 0x0000052BUL, + 0x02010100UL, 0x00000110UL, + 0x12010104UL, 0x00000000UL, + 0x32010104UL, 0x00000110UL, + 0x12010110UL, 0x000FFF00UL, + 0x32010110UL, 0x42000002UL, + 0x1201012CUL, 0x001FFC00UL, + 0x3201012CUL, 0x008000A9UL, + 0x02010140UL, 0x0000003FUL, + 0x02020168UL, 0x00060010UL, + /* 016C */ 0x00062000UL, + 0x02010174UL, 0x0C100169UL, + 0x12010178UL, 0x001C0000UL, + 0x32010178UL, 0xCFE00440UL, + 0x12010180UL, 0x00000779UL, + 0x32010180UL, 0x00000006UL, + 0x02020188UL, 0x00000090UL, + /* 018C */ 0x00000000UL, + 0x120101ACUL, 0x000001F8UL, + 0x320101ACUL, 0x00010204UL, + 0x020101B0UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t wmbus_mode_s_modemConfigBase[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_1, + 0x0002400CUL, 0x000A8001UL, + /* 4010 */ 0x000040FFUL, + 0x00024020UL, 0x00000000UL, + /* 4024 */ 0x00000000UL, + 0x00074030UL, 0x00000000UL, + /* 4034 */ 0x00000000UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000000UL, + /* 4040 */ 0x00000000UL, + /* 4044 */ 0x00004000UL, + /* 4048 */ 0x000007A4UL, + 0x00014050UL, 0x000008FFUL, + 0x0002405CUL, 0x00000000UL, + /* 4060 */ 0x00000000UL, + 0x000140A8UL, 0x00000007UL, + 0x000440BCUL, 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + 0x00044108UL, 0x00004C09UL, + /* 410C */ 0x00004C0FUL, + /* 4110 */ 0x00004D09UL, + /* 4114 */ 0x00004D0FUL, + 0x1001C020UL, 0x0007F800UL, + 0x3001C020UL, 0x002801FEUL, + 0x1001C024UL, 0x000000FFUL, + 0x3001C024UL, 0x00001300UL, + 0x0008C028UL, 0x03B380ECUL, + /* C02C */ 0x51407543UL, + /* C030 */ 0xF8000FA0UL, + /* C034 */ 0x00004030UL, + /* C038 */ 0x0007AAA8UL, + /* C03C */ 0x01090E35UL, + /* C040 */ 0x00000000UL, + /* C044 */ 0x00000000UL, + 0x0014C054UL, 0x00302187UL, + /* C058 */ 0xE654005AUL, + /* C05C */ 0x0000010EUL, + /* C060 */ 0x514D4432UL, + /* C064 */ 0x00000054UL, + /* C068 */ 0x0002C688UL, + /* C06C */ 0x00000520UL, + /* C070 */ 0x000010BAUL, + /* C074 */ 0x003F0000UL, + /* C078 */ 0x00EE008DUL, + /* C07C */ 0x03AC01F6UL, + /* C080 */ 0x079604F5UL, + /* C084 */ 0x0D9C09DEUL, + /* C088 */ 0x179311C3UL, + /* C08C */ 0x26F51DFEUL, + /* C090 */ 0x3FFF32BDUL, + /* C094 */ 0x1BF815FEUL, + /* C098 */ 0x2DB423DCUL, + /* C09C */ 0x3FFF39D0UL, + /* C0A0 */ 0x00003FFFUL, + 0x0005C0A8UL, 0x15724BBDUL, + /* C0AC */ 0x0518A311UL, + /* C0B0 */ 0x76543210UL, + /* C0B4 */ 0x00000A98UL, + /* C0B8 */ 0x00000000UL, + 0x0004C0CCUL, 0x000000EEUL, + /* C0D0 */ 0x00000000UL, + /* C0D4 */ 0x000A0001UL, + /* C0D8 */ 0x00280001UL, + 0x01010008UL, 0x000007A6UL, + 0x01010018UL, 0x00000000UL, + 0x01010020UL, 0x0000A6BCUL, + 0x01264040UL, 0x11D00000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000012UL, + /* 4050 */ 0x0081C011UL, + /* 4054 */ 0x20000000UL, + /* 4058 */ 0x000AD000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + /* 4068 */ 0x00C270BEUL, + /* 406C */ 0x00000041UL, + /* 4070 */ 0x00000030UL, + /* 4074 */ 0x00320011UL, + /* 4078 */ 0x00025A47UL, + /* 407C */ 0x0003FFFFUL, + /* 4080 */ 0x00001412UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x00080392UL, + /* 408C */ 0x62000000UL, + /* 4090 */ 0x00000000UL, + /* 4094 */ 0x00000000UL, + /* 4098 */ 0x00000000UL, + /* 409C */ 0x00000000UL, + /* 40A0 */ 0x00000000UL, + /* 40A4 */ 0x00000000UL, + /* 40A8 */ 0x00000000UL, + /* 40AC */ 0x00000000UL, + /* 40B0 */ 0x00000000UL, + /* 40B4 */ 0x00000000UL, + /* 40B8 */ 0x00000000UL, + /* 40BC */ 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + /* 40CC */ 0x00000000UL, + /* 40D0 */ 0x00000000UL, + /* 40D4 */ 0x00000000UL, + 0x110140E0UL, 0x000001F8UL, + 0x310140E0UL, 0x00000201UL, + 0x01024110UL, 0x00051E33UL, + /* 4114 */ 0x00000000UL, + 0x010E411CUL, 0x04000000UL, + /* 4120 */ 0x00000000UL, + /* 4124 */ 0x078304FFUL, + /* 4128 */ 0x3AC81388UL, + /* 412C */ 0x0C6606FFUL, + /* 4130 */ 0x078304FFUL, + /* 4134 */ 0x03FF1388UL, + /* 4138 */ 0xF00A20BCUL, + /* 413C */ 0x00508894UL, + /* 4140 */ 0x00A14284UL, + /* 4144 */ 0x123556B7UL, + /* 4148 */ 0x500000A1UL, + /* 414C */ 0x00003B80UL, + /* 4150 */ 0x00000000UL, + 0x01024158UL, 0x00000000UL, + /* 415C */ 0x0000FDFFUL, + 0x01014164UL, 0x0000010CUL, + 0x010B416CUL, 0x40000000UL, + /* 4170 */ 0x00000000UL, + /* 4174 */ 0x00000000UL, + /* 4178 */ 0x00000000UL, + /* 417C */ 0x00000000UL, + /* 4180 */ 0x00000000UL, + /* 4184 */ 0x00000101UL, + /* 4188 */ 0x00000000UL, + /* 418C */ 0x00000000UL, + /* 4190 */ 0x00000000UL, + /* 4194 */ 0x00000000UL, + 0x010241A4UL, 0x00000000UL, + /* 41A8 */ 0x00000000UL, + 0x010C41B0UL, 0x00000000UL, + /* 41B4 */ 0x00200000UL, + /* 41B8 */ 0x00000000UL, + /* 41BC */ 0x00000000UL, + /* 41C0 */ 0x003C0000UL, + /* 41C4 */ 0x0006AAAAUL, + /* 41C8 */ 0x00000000UL, + /* 41CC */ 0x00000000UL, + /* 41D0 */ 0xAAAAAAABUL, + /* 41D4 */ 0x000001D0UL, + /* 41D8 */ 0x00020000UL, + /* 41DC */ 0x00000000UL, + 0x011541E4UL, 0x1492F42DUL, + /* 41E8 */ 0x003858D3UL, + /* 41EC */ 0x007AFDBEUL, + /* 41F0 */ 0x0041732CUL, + /* 41F4 */ 0x0DD53E7FUL, + /* 41F8 */ 0x03283A26UL, + /* 41FC */ 0x302424E2UL, + /* 4200 */ 0x0C81901EUL, + /* 4204 */ 0x0006490CUL, + /* 4208 */ 0x006DDFA8UL, + /* 420C */ 0x00B10BC0UL, + /* 4210 */ 0x00A53D18UL, + /* 4214 */ 0x05020AE8UL, + /* 4218 */ 0x1DD71B27UL, + /* 421C */ 0x80000000UL, + /* 4220 */ 0x00000000UL, + /* 4224 */ 0x8000FFFFUL, + /* 4228 */ 0x00000000UL, + /* 422C */ 0x40001860UL, + /* 4230 */ 0x00000000UL, + /* 4234 */ 0x00000000UL, + 0x0101423CUL, 0x00000000UL, + 0x01034244UL, 0x00000014UL, + /* 4248 */ 0x00000000UL, + /* 424C */ 0x04000008UL, + 0x010F4330UL, 0x09C2422BUL, + /* 4334 */ 0x80E38121UL, + /* 4338 */ 0xF6C0C081UL, + /* 433C */ 0x00A40C06UL, + /* 4340 */ 0x00000000UL, + /* 4344 */ 0xD2600023UL, + /* 4348 */ 0x4000C350UL, + /* 434C */ 0x80000002UL, + /* 4350 */ 0x00000020UL, + /* 4354 */ 0x00000478UL, + /* 4358 */ 0xDA834504UL, + /* 435C */ 0x9518840FUL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x00210000UL, + /* 4368 */ 0x9AC85555UL, + 0x01018010UL, 0x00000003UL, + 0x01028038UL, 0x00102225UL, + /* 803C */ 0x00000003UL, + 0x0103809CUL, 0x00000000UL, + /* 80A0 */ 0x0003B870UL, + /* 80A4 */ 0x0003B870UL, + 0x110180A8UL, 0x000001F6UL, + 0x310180A8UL, 0x01014201UL, + 0x110180ACUL, 0x000001F6UL, + 0x310180ACUL, 0x01014201UL, + 0x010280B0UL, 0x02000300UL, + /* 80B4 */ 0x02000300UL, + 0x02030098UL, 0x00000000UL, + /* 009C */ 0x04000C00UL, + /* 00A0 */ 0x0000044CUL, + 0x020200D8UL, 0xAA400005UL, + /* 00DC */ 0x00000188UL, + 0x120100ECUL, 0x00000FE0UL, + 0x320100ECUL, 0x5151200DUL, + 0x020100F0UL, 0x0000052BUL, + 0x02010100UL, 0x00000110UL, + 0x12010104UL, 0x00000000UL, + 0x32010104UL, 0x00000110UL, + 0x12010110UL, 0x000FFF00UL, + 0x32010110UL, 0x42000002UL, + 0x1201012CUL, 0x001FFC00UL, + 0x3201012CUL, 0x008000A9UL, + 0x02010140UL, 0x0000003FUL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510063UL, + 0x02020168UL, 0x00060010UL, + /* 016C */ 0x00062000UL, + 0x02010174UL, 0x0C100169UL, + 0x12010178UL, 0x001C0000UL, + 0x32010178UL, 0xCFE00440UL, + 0x12010180UL, 0x00000779UL, + 0x32010180UL, 0x00000006UL, + 0x02020188UL, 0x00000090UL, + /* 018C */ 0x00000000UL, + 0x120101ACUL, 0x000001F8UL, + 0x320101ACUL, 0x00010204UL, + 0x020101B0UL, 0x00000000UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t m2o_mode_t_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_0, + 0x00044030UL, 0x00000300UL, + /* 4034 */ 0x00000020UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000007UL, + 0x00014050UL, 0x00800900UL, + 0x0001C03CUL, 0x0109040EUL, + 0x0005C054UL, 0x00302187UL, + /* C058 */ 0xE655005BUL, + /* C05C */ 0x00000111UL, + /* C060 */ 0x524D4432UL, + /* C064 */ 0x00000055UL, + 0x01144040UL, 0xF0F00000UL, + /* 4044 */ 0xC1F00000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000000UL, + /* 4050 */ 0x0081C009UL, + /* 4054 */ 0x20000000UL, + /* 4058 */ 0x00000000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + /* 4068 */ 0x000400C3UL, + /* 406C */ 0x00000041UL, + /* 4070 */ 0x00000030UL, + /* 4074 */ 0x00130012UL, + /* 4078 */ 0x000002F0UL, + /* 407C */ 0x00000000UL, + /* 4080 */ 0x00002410UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x003B0395UL, + /* 408C */ 0x60000000UL, + 0x0104413CUL, 0x00508778UL, + /* 4140 */ 0x001D4084UL, + /* 4144 */ 0x123556B7UL, + /* 4148 */ 0x5000001DUL, + 0x010141D0UL, 0x55555555UL, + 0x01084200UL, 0x1492F42DUL, + /* 4204 */ 0x003858D3UL, + /* 4208 */ 0x007AFDBEUL, + /* 420C */ 0x0041732CUL, + /* 4210 */ 0x0DD53E7FUL, + /* 4214 */ 0x03283A26UL, + /* 4218 */ 0x302424E2UL, + /* 421C */ 0x00000000UL, + 0x010F4330UL, 0x0146E46AUL, + /* 4334 */ 0x304A56EBUL, + /* 4338 */ 0x16C0C081UL, + /* 433C */ 0x00A00C07UL, + /* 4340 */ 0x40000000UL, + /* 4344 */ 0xD2240012UL, + /* 4348 */ 0x40004000UL, + /* 434C */ 0x80000002UL, + /* 4350 */ 0x00000020UL, + /* 4354 */ 0x00000478UL, + /* 4358 */ 0xDAA34004UL, + /* 435C */ 0x9520740EUL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x001E0000UL, + /* 4368 */ 0x9A9B5555UL, + 0x01028038UL, 0x001021DEUL, + /* 803C */ 0x00000003UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t o2m_mode_t_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_1, + 0x00044030UL, 0x00000000UL, + /* 4034 */ 0x00000000UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000000UL, + 0x00014050UL, 0x000008FFUL, + 0x0001C03CUL, 0x01090E35UL, + 0x0005C054UL, 0x00302187UL, + /* C058 */ 0xE654005AUL, + /* C05C */ 0x0000010EUL, + /* C060 */ 0x514D4432UL, + /* C064 */ 0x00000054UL, + 0x01144040UL, 0x11D00000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000012UL, + /* 4050 */ 0x0081C011UL, + /* 4054 */ 0x20000000UL, + /* 4058 */ 0x000AD000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + /* 4068 */ 0x00C270BEUL, + /* 406C */ 0x00000041UL, + /* 4070 */ 0x00000030UL, + /* 4074 */ 0x00130011UL, + /* 4078 */ 0x00025A47UL, + /* 407C */ 0x0003FFFFUL, + /* 4080 */ 0x00001412UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x00080392UL, + /* 408C */ 0x62000000UL, + 0x0104413CUL, 0x00508894UL, + /* 4140 */ 0x00A14284UL, + /* 4144 */ 0x123556B7UL, + /* 4148 */ 0x500000A1UL, + 0x010141D0UL, 0xAAAAAAABUL, + 0x01084200UL, 0x0C81901EUL, + /* 4204 */ 0x0006490CUL, + /* 4208 */ 0x006DDFA8UL, + /* 420C */ 0x00B10BC0UL, + /* 4210 */ 0x00A53D18UL, + /* 4214 */ 0x05020AE8UL, + /* 4218 */ 0x1DD71B27UL, + /* 421C */ 0x80000000UL, + 0x010F4330UL, 0x09C2422BUL, + /* 4334 */ 0x80E38121UL, + /* 4338 */ 0xF6C0C081UL, + /* 433C */ 0x00A40C06UL, + /* 4340 */ 0x00000000UL, + /* 4344 */ 0xD2600023UL, + /* 4348 */ 0x4000C350UL, + /* 434C */ 0x80000002UL, + /* 4350 */ 0x00000020UL, + /* 4354 */ 0x00000478UL, + /* 4358 */ 0xDA834504UL, + /* 435C */ 0x9518840FUL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x00210000UL, + /* 4368 */ 0x9AC85555UL, + 0x01028038UL, 0x00102225UL, + /* 803C */ 0x00000003UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t m2o_mode_c_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_2, + 0x0007C054UL, 0x00302187UL, + /* C058 */ 0xE657005EUL, + /* C05C */ 0x0000011AUL, + /* C060 */ 0x55504734UL, + /* C064 */ 0x00000057UL, + /* C068 */ 0x0002C688UL, + /* C06C */ 0x000004A0UL, + 0x0001C0CCUL, 0x000000EEUL, + 0x01064040UL, 0x70100000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000000UL, + /* 4050 */ 0x0082C019UL, + /* 4054 */ 0x00000000UL, + 0x010D4068UL, 0x00FC2FFDUL, + /* 406C */ 0x00000C41UL, + /* 4070 */ 0x0000002AUL, + /* 4074 */ 0x00130012UL, + /* 4078 */ 0x02CCAAF0UL, + /* 407C */ 0x02F0AAF0UL, + /* 4080 */ 0x00000E4DUL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x00080393UL, + /* 408C */ 0x62040000UL, + /* 4090 */ 0x00000000UL, + /* 4094 */ 0x00000000UL, + /* 4098 */ 0x00000000UL, + 0x0101411CUL, 0x8CA49000UL, + 0x0104413CUL, 0x0050AE4BUL, + /* 4140 */ 0x40AA64E5UL, + /* 4144 */ 0x543D54CDUL, + /* 4148 */ 0x43F91EB0UL, + 0x010141D4UL, 0x806E01E6UL, + 0x01074200UL, 0x0C81901EUL, + /* 4204 */ 0x0006490CUL, + /* 4208 */ 0x006DDFA8UL, + /* 420C */ 0x00B10BC0UL, + /* 4210 */ 0x00A53D18UL, + /* 4214 */ 0x05020AE8UL, + /* 4218 */ 0x1DD71B27UL, + 0x0101424CUL, 0x04060008UL, + 0x01028038UL, 0x001020AEUL, + /* 803C */ 0x00000003UL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510063UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t o2m_mode_c_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_3, + 0x0007C054UL, 0x00302187UL, + /* C058 */ 0xE6880092UL, + /* C05C */ 0x000001B6UL, + /* C060 */ 0x837C6E50UL, + /* C064 */ 0x00000088UL, + /* C068 */ 0x0002C688UL, + /* C06C */ 0x000004C0UL, + 0x0001C0CCUL, 0x000001FEUL, + 0x01064040UL, 0x30B00000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x04000000UL, + /* 4050 */ 0x0082C019UL, + /* 4054 */ 0x20005000UL, + 0x010D4068UL, 0x00FE60BDUL, + /* 406C */ 0x00000C41UL, + /* 4070 */ 0x00000070UL, + /* 4074 */ 0x00130012UL, + /* 4078 */ 0x02CCAAF0UL, + /* 407C */ 0x02F0AAF0UL, + /* 4080 */ 0x00000E35UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x002B037FUL, + /* 408C */ 0x62040000UL, + /* 4090 */ 0x00000000UL, + /* 4094 */ 0x22140A04UL, + /* 4098 */ 0x4F4A4132UL, + 0x0101411CUL, 0x8CF3D000UL, + 0x0104413CUL, 0x00505414UL, + /* 4140 */ 0x409A48B7UL, + /* 4144 */ 0x543D54CDUL, + /* 4148 */ 0x43F9FF9BUL, + 0x010141D4UL, 0x805780E6UL, + 0x01074200UL, 0x0A00ABFFUL, + /* 4204 */ 0x000FF15CUL, + /* 4208 */ 0x000241D3UL, + /* 420C */ 0x00B1ED95UL, + /* 4210 */ 0x0FD87B19UL, + /* 4214 */ 0x04B90812UL, + /* 4218 */ 0x1F6D1BEAUL, + 0x0101424CUL, 0x14060008UL, + 0x01028038UL, 0x00101505UL, + /* 803C */ 0x00000003UL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510062UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const RAIL_ChannelConfigEntry_t wmbus_mode_t_channels[] = { + { + .phyConfigDeltaAdd = m2o_mode_t_modemConfig, + .baseFrequency = 868950000, + .channelSpacing = 0, + .physicalChannelOffset = 0, + .channelNumberStart = 0, + .channelNumberEnd = 0, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_0, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, + { + .phyConfigDeltaAdd = o2m_mode_t_modemConfig, + .baseFrequency = 868300000, + .channelSpacing = 0, + .physicalChannelOffset = 1, + .channelNumberStart = 1, + .channelNumberEnd = 1, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_0, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, +}; + +const RAIL_ChannelConfigEntry_t wmbus_mode_c_channels[] = { + { + .phyConfigDeltaAdd = m2o_mode_c_modemConfig, + .baseFrequency = 868950000, + .channelSpacing = 0, + .physicalChannelOffset = 0, + .channelNumberStart = 0, + .channelNumberEnd = 0, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, + { + .phyConfigDeltaAdd = o2m_mode_c_modemConfig, + .baseFrequency = 868950000, + .channelSpacing = 0, + .physicalChannelOffset = 1, + .channelNumberStart = 1, + .channelNumberEnd = 1, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, +}; + +const RAIL_ChannelConfigEntry_t wmbus_mode_s_channels[] = { + { + .phyConfigDeltaAdd = NULL, + .baseFrequency = 868300000, + .channelSpacing = 0, + .physicalChannelOffset = 0, + .channelNumberStart = 0, + .channelNumberEnd = 0, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_2, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, + { + .phyConfigDeltaAdd = NULL, + .baseFrequency = 868300000, + .channelSpacing = 0, + .physicalChannelOffset = 1, + .channelNumberStart = 1, + .channelNumberEnd = 1, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_2, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, +}; + +const RAIL_ChannelConfig_t wmbus_mode_t_channelConfig = { + .phyConfigBase = wmbus_mode_t_modemConfigBase, + .phyConfigDeltaSubtract = NULL, + .configs = wmbus_mode_t_channels, + .length = 2U, + .signature = 0UL, + .xtalFrequencyHz = 39000000UL, +}; + +const RAIL_ChannelConfig_t wmbus_mode_c_channelConfig = { + .phyConfigBase = wmbus_mode_c_modemConfigBase, + .phyConfigDeltaSubtract = NULL, + .configs = wmbus_mode_c_channels, + .length = 2U, + .signature = 0UL, + .xtalFrequencyHz = 39000000UL, +}; + +const RAIL_ChannelConfig_t wmbus_mode_s_channelConfig = { + .phyConfigBase = wmbus_mode_s_modemConfigBase, + .phyConfigDeltaSubtract = NULL, + .configs = wmbus_mode_s_channels, + .length = 2U, + .signature = 0UL, + .xtalFrequencyHz = 39000000UL, +}; + +const RAIL_ChannelConfig_t *channelConfigs[] = { + &wmbus_mode_t_channelConfig, + &wmbus_mode_c_channelConfig, + &wmbus_mode_s_channelConfig, + NULL +}; + +uint32_t wmbusAccelerationBuffer[471]; diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/rail_config.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/rail_config.h new file mode 100644 index 0000000000..23a343ae04 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/rail_config.h @@ -0,0 +1,50 @@ +/***************************************************************************//** + * @brief RAIL Configuration + * @details + * WARNING: Auto-Generated Radio Config Header - DO NOT EDIT + * Radio Configurator Version: 2402.6.1 + * RAIL Adapter Version: 2.4.33 + * RAIL Compatibility: 2.x + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_CONFIG_H__ +#define __RAIL_CONFIG_H__ + +#include +#include "rail_types.h" + +#define WMBUS_ACCELERATION_BUFFER wmbusAccelerationBuffer +extern uint32_t wmbusAccelerationBuffer[]; + +#define RADIO_CONFIG_XTAL_FREQUENCY 39000000UL + +#define RAIL0_M2O_MODE_T_PHY_WMBUS_MODET_M2O_100K_FRAMEA +#define RAIL0_M2O_MODE_T_PROFILE_MBUS +extern const RAIL_ChannelConfig_t *channelConfigs[]; + +#endif // __RAIL_CONFIG_H__ diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_component_catalog.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_component_catalog.h new file mode 100644 index 0000000000..31242e89cc --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_component_catalog.h @@ -0,0 +1,51 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +//#define SL_CATALOG_APP_ASSERT_PRESENT +//#define SL_CATALOG_APP_LOG_PRESENT +//#define SL_CATALOG_CLI_PRESENT +//#define SL_CATALOG_CLOCK_MANAGER_PRESENT +//#define SL_CATALOG_DEVICE_INIT_PRESENT +//#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT +//#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT +//#define SL_CATALOG_EMLIB_CORE_PRESENT +//#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +//#define SL_CATALOG_HFXO_MANAGER_PRESENT +//#define SL_CATALOG_INTERRUPT_MANAGER_PRESENT +//#define SL_CATALOG_IOSTREAM_PRESENT +//#define SL_CATALOG_IOSTREAM_EUSART_PRESENT +//#define SL_CATALOG_RETARGET_STDIO_PRESENT +//#define SL_CATALOG_IOSTREAM_UART_COMMON_PRESENT +//#define SL_CATALOG_MEMORY_MANAGER_PRESENT +//#define SL_CATALOG_MPU_PRESENT +//#define SL_CATALOG_POWER_MANAGER_PRESENT +//#define SL_CATALOG_PRINTF_PRESENT +//#define SL_CATALOG_RADIO_CONFIG_WMBUS_METER_PRESENT +//#define SL_CATALOG_RAIL_LIB_PRESENT +//#define SL_CATALOG_RAIL_UTIL_INIT_PRESENT +//#define SL_CATALOG_RAIL_UTIL_PTI_PRESENT +//#define SL_CATALOG_SE_MANAGER_PRESENT +//#define SL_CATALOG_SEGMENT_LCD_DRIVER_PRESENT +//#define SL_CATALOG_BTN0_PRESENT +//#define SL_CATALOG_SIMPLE_BUTTON_PRESENT +//#define SL_CATALOG_SIMPLE_BUTTON_BTN0_PRESENT +//#define SL_CATALOG_BTN1_PRESENT +//#define SL_CATALOG_SIMPLE_BUTTON_BTN1_PRESENT +//#define SL_CATALOG_LED0_PRESENT +//#define SL_CATALOG_SIMPLE_LED_PRESENT +//#define SL_CATALOG_SIMPLE_LED_LED0_PRESENT +//#define SL_CATALOG_SIMPLE_RAIL_ASSISTANCE_PRESENT +//#define SL_CATALOG_FLEX_RAIL_CONFIG_PRESENT +//#define SL_CATALOG_FLEX_RAIL_SLEEP_PRESENT +//#define SL_CATALOG_SL_SIMPLE_RAIL_STUB_PRESENT +//#define SL_CATALOG_WMBUS_PACKET_ASSEMBLER_PRESENT +//#define SL_CATALOG_SL_WMBUS_SENSOR_CLI_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_CORE_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_PULSE_COUNTER_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_THERMO_METER_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_VIRTUAL_WATER_METER_PRESENT +//#define SL_CATALOG_WMBUS_SUPPORT_PRESENT +//#define SL_CATALOG_SLEEPTIMER_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_callbacks.c b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_callbacks.c new file mode 100644 index 0000000000..b09033d462 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_callbacks.c @@ -0,0 +1,118 @@ + /***************************************************************************//** + * @file sl_rail_util_callbacks.c + * @brief RAIL Callbacks + * WARNING: Auto-Generated Radio Callbacks - DO NOT EDIT + * Any application code placed within this file will be discarged + * upon project regeneration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "rail.h" +#include "sl_component_catalog.h" +#ifdef SL_CATALOG_APP_ASSERT_PRESENT +#include "app_assert.h" +#define APP_ASSERT(expr, ...) app_assert(expr,__VA_ARGS__) +#else + #define APP_ASSERT(expr, string ,rail_handle, error_code) \ + do { \ + if (!(expr)) { \ + while (1) ; \ + } \ + } while (0) +#endif +#include "sl_rail_util_callbacks_config.h" +#include "pa_conversions_efr32.h" + +// Provide weak function called by callback RAILCb_AssertFailed. +__WEAK +void sl_rail_util_on_assert_failed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code) +{ + (void) rail_handle; + (void) error_code; + APP_ASSERT(false, + "rail_handle: 0x%X, error_code: %d", + rail_handle, + error_code); +} + +#if SL_RAIL_UTIL_CALLBACKS_ASSERT_FAILED_OVERRIDE +// Note: RAILCb_AssertFailed is called directly by the RAIL library when +// needed, so maintain this exact function signature. +void RAILCb_AssertFailed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code) +{ + sl_rail_util_on_assert_failed(rail_handle, error_code); +} +#endif + +// Provide weak function called by callback sli_rail_util_on_rf_ready. +__WEAK +void sl_rail_util_on_rf_ready(RAIL_Handle_t rail_handle) +{ + (void) rail_handle; +} + +// Internal-only callback set up through call to RAIL_Init(). +void sli_rail_util_on_rf_ready(RAIL_Handle_t rail_handle) +{ + sl_rail_util_on_rf_ready(rail_handle); +} + +// Provide weak function called by callback +// sli_rail_util_on_channel_config_change. +__WEAK +void sl_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) +{ + (void) rail_handle; + (void) entry; +} + +// Internal-only callback set up through call to RAIL_ConfigChannels(). +void sli_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) +{ + sl_rail_util_pa_on_channel_config_change(rail_handle, entry); + sl_rail_util_on_channel_config_change(rail_handle, entry); +} + +// Provide weak function called by callback sli_rail_util_on_event. +__WEAK +void sl_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events) +{ + (void) rail_handle; + (void) events; +} + +// Internal-only callback set up through call to RAIL_Init(). +void sli_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events) +{ + sl_rail_util_on_event(rail_handle, events); +} diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_init.c b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_init.c new file mode 100644 index 0000000000..04d44e97d5 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_init.c @@ -0,0 +1,255 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "rail.h" +#include "rail_ble.h" // for RAIL_BLE_State_t +#include "sli_rail_util_callbacks.h" // for internal-only callback signatures +#include "sl_rail_util_init.h" +#include "sl_rail_util_protocol.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_TIMING_TEST_PRESENT) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT +// Needed for measuring RAIL_Init() time as a part of +// detailed timing characterization. +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_timer.h" +#else +#include "sl_hal_timer.h" +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager.h" +#else +#include "em_cmu.h" +#endif //defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#endif //defined(SL_CATALOG_TIMING_TEST_PRESENT) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT + +#ifdef SL_CATALOG_APP_ASSERT_PRESENT +#include "app_assert.h" +#define APP_ASSERT(expr, ...) app_assert(expr,__VA_ARGS__) +#else +#define APP_ASSERT(expr, ...) \ + do { \ + if (!(expr)) { \ + while (1) ; \ + } \ + } while (0) +#endif + +#if 0U \ + || SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE \ + || 0U + #include "rail_config.h" +#endif + +// Instance: inst0 +static RAIL_Handle_t sl_rail_handle_inst0 = RAIL_EFR32_HANDLE; + +#if defined(SL_CATALOG_TIMING_TEST_PRESENT) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT +uint32_t sli_timing_start_tick = 0U; +uint32_t sli_timing_end_tick = 0U; +static TIMER_TypeDef *timer = TIMER0; +static void setupTimingTestTimer(void) +{ +// Clock TIMER0 using the HF clock +#ifndef SL_CATALOG_CLOCK_MANAGER_PRESENT + CMU_CLOCK_SELECT_SET(TIMER0, HFXO); + CMU_ClockEnable(cmuClock_TIMER0, true); + // Use default configuration, prescaled by 8. + TIMER_Init_TypeDef timerCfg = TIMER_INIT_DEFAULT; + timerCfg.prescale = timerPrescale8; + // Enable TIMER0 to upcount + TIMER_Init(timer, &timerCfg); +#else + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_TIMER0); + sl_hal_timer_config_t timerCfg = SL_HAL_TIMER_CONFIG_DEFAULT; + // Use default configuration, prescaled by 8. + timerCfg.prescaler = TIMER_CFG_PRESC_DIV8; + // Enable TIMER0 to upcount + sl_hal_timer_init(timer, &timerCfg); +#endif //SL_CATALOG_CLOCK_MANAGER_PRESENT +} +#endif + +static void sl_rail_util_init_inst0(void) +{ +#if SL_RAIL_UTIL_INIT_INST0_ENABLE + RAIL_Status_t status; + RAIL_Config_t sl_rail_config = { + .eventsCallback = &sli_rail_util_on_event, + // Other fields are ignored nowadays + }; + (void) status; // Suppress compiler warning if status ends up unused +#ifdef SL_CATALOG_TIMING_TEST_PRESENT + setupTimingTestTimer(); + sli_timing_start_tick = timer->CNT; +#endif // SL_CATALOG_TIMING_TEST_PRESENT + sl_rail_handle_inst0 = RAIL_Init(&sl_rail_config, +#if SL_RAIL_UTIL_INIT_INIT_COMPLETE_CALLBACK_INST0_ENABLE + &sli_rail_util_on_rf_ready +#else + NULL +#endif // SL_RAIL_UTIL_INIT_INIT_COMPLETE_CALLBACK_INST0_ENABLE + ); +#ifdef SL_CATALOG_TIMING_TEST_PRESENT + sli_timing_end_tick = timer->CNT; +#endif // SL_CATALOG_TIMING_TEST_PRESENT + APP_ASSERT((NULL != sl_rail_handle_inst0), + "RAIL_Init failed, return value: NULL"); + +#if SL_RAIL_UTIL_INIT_DATA_FORMATS_INST0_ENABLE + RAIL_DataConfig_t data_config = { + .txSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_SOURCE, + .rxSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_SOURCE, + .txMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_MODE, + .rxMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_MODE, + }; + status = RAIL_ConfigData(sl_rail_handle_inst0, &data_config); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_ConfigData failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_DATA_FORMATS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_PROTOCOLS_INST0_ENABLE + const RAIL_ChannelConfig_t *channel_config = NULL; + if (SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT + == SL_RAIL_UTIL_PROTOCOL_PROPRIETARY) { +#if SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE + channel_config = channelConfigs[SL_RAIL_UTIL_INIT_PROTOCOL_PROPRIETARY_INST0_INDEX]; +#else // !SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE + APP_ASSERT(false, + "SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE must be true when (SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT == SL_RAIL_UTIL_PROTOCOL_PROPRIETARY)"); +#endif // SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE + } + (void) RAIL_ConfigChannels(sl_rail_handle_inst0, + channel_config, + &sli_rail_util_on_channel_config_change); + status = sl_rail_util_protocol_config(sl_rail_handle_inst0, + SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "sl_rail_util_protocol_config failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_PROTOCOLS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_CALIBRATIONS_INST0_ENABLE + status = RAIL_ConfigCal(sl_rail_handle_inst0, + 0U + | (SL_RAIL_UTIL_INIT_CALIBRATION_TEMPERATURE_NOTIFY_INST0_ENABLE + ? RAIL_CAL_TEMP : 0U) + | (SL_RAIL_UTIL_INIT_CALIBRATION_ONETIME_NOTIFY_INST0_ENABLE + ? RAIL_CAL_ONETIME : 0U)); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_ConfigCal failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_CALIBRATIONS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_EVENTS_INST0_ENABLE + status = RAIL_ConfigEvents(sl_rail_handle_inst0, + RAIL_EVENTS_ALL, + SL_RAIL_UTIL_INIT_EVENT_INST0_MASK); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_ConfigEvents failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_EVENTS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_TRANSITIONS_INST0_ENABLE + RAIL_StateTransitions_t tx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_ERROR + }; + RAIL_StateTransitions_t rx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_ERROR + }; + status = RAIL_SetTxTransitions(sl_rail_handle_inst0, + &tx_transitions); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_SetTxTransitions failed, return value: %d", + status); + status = RAIL_SetRxTransitions(sl_rail_handle_inst0, + &rx_transitions); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_SetRxTransitions failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_TRANSITIONS_INST0_ENABLE +#else // !SL_RAIL_UTIL_INIT_INST0_ENABLE + // Eliminate compiler warnings. + (void) sl_rail_handle_inst0; +#endif // SL_RAIL_UTIL_INIT_INST0_ENABLE +} + +RAIL_Handle_t sl_rail_util_get_handle(sl_rail_util_handle_type_t handle) +{ + RAIL_Handle_t *sl_rail_handle_array[] = { + &sl_rail_handle_inst0, + }; + return *sl_rail_handle_array[handle]; +} + +#define INIT_INSTANCES (0 + 1) + +#if (INIT_INSTANCES > 1) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT + #error "sl_rail_util_init.c: If you are going to use more than one rail_util_init instance, you must use the Multiprotocol RAIL library." +#elif (INIT_INSTANCES > 4) + static uint64_t extraStateBuffers[INIT_INSTANCES - 4][RAIL_STATE_BUFFER_BYTES / sizeof(uint64_t)]; + static RAIL_StateBufferEntry_t extraProtos[INIT_INSTANCES - 4]; +#else + // RAIL provides enough built-in state buffers for all the instances +#endif + +void sl_rail_util_init(void) +{ +#if (INIT_INSTANCES > 2) + RAIL_Status_t status; + status = RAIL_AddStateBuffer3(RAIL_EFR32_HANDLE); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_AddStateBuffer3 failed, return value: %d", + status); +#if (INIT_INSTANCES > 3) + status = RAIL_AddStateBuffer4(RAIL_EFR32_HANDLE); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_AddStateBuffer4 failed, return value: %d", + status); +#endif +#if (INIT_INSTANCES > 4) + for (int i = 0; i < (INIT_INSTANCES - 4); i++) { + extraProtos[i].bufferBytes = sizeof(extraStateBuffers[0]); + extraProtos[i].buffer = extraStateBuffers[i]; + status = RAIL_AddStateBuffer(RAIL_EFR32_HANDLE, &extraProtos[i]); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_AddStateBuffer(%d) failed, return value: %d", + (INIT_INSTANCES + i), status); + } +#endif +#endif + sl_rail_util_init_inst0(); +} diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_init.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_init.h new file mode 100644 index 0000000000..61d99db352 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/autogen/sl_rail_util_init.h @@ -0,0 +1,222 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_INIT_H +#define SL_RAIL_UTIL_INIT_H + +#include "rail.h" +#include "sl_rail_util_init_inst0_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum sl_rail_util_handle_type{ + SL_RAIL_UTIL_HANDLE_INST0, +} sl_rail_util_handle_type_t; + +/** + * Initialize the RAIL Init Utility. + * + * @note: This function should be called during application initialization. + */ +void sl_rail_util_init(void); + +/** + * Get the RAIL handle created during initialization. + * @param[in] handle The enum name of the desired RAIL handle. + * + * @return A valid RAIL handle. If the RAIL handle hasn't been set up, the + * invalid value of \ref RAIL_EFR32_HANDLE will be returned. + */ +RAIL_Handle_t sl_rail_util_get_handle(sl_rail_util_handle_type_t handle); + +/** + * A callback available to the application, called on RAIL asserts. + * + * @param[in] rail_handle The RAIL handle associated with the assert. + * @param[in] error_code The assertion error code. + */ +void sl_rail_util_on_assert_failed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code); + +/** + * A callback available to the application, called on RAIL init completion. + * + * @param[in] rail_handle The RAIL handle associated with the RAIL init + * completion notification. + */ +void sl_rail_util_on_rf_ready(RAIL_Handle_t rail_handle); + +/** + * A callback available to the application, called on a channel configuration + * change. + * + * @param[in] rail_handle The RAIL handle associated with the channel config + * change notification. + * @param[in] entry The channel configuration being changed to. + */ +void sl_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry); + +/** + * A callback available to the application, called on registered RAIL events. + * + * @param[in] rail_handle The RAIL handle associated with the RAIL event + * notification. + * @param[in] events The RAIL events having occurred. + */ +void sl_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events); + +/** + * An event mask, available to the application, specifying the radio events + * setup within the init code. + * + * @note: Because the value of this define is evaluated based on values in the + * \ref RAIL_Events_t enum, this define will only have a valid value during + * run-time. + */ +#define SL_RAIL_UTIL_INIT_EVENT_INST0_MASK (RAIL_EVENTS_NONE \ + | (SL_RAIL_UTIL_INIT_EVENT_RSSI_AVERAGE_DONE_INST0_ENABLE \ + ? RAIL_EVENT_RSSI_AVERAGE_DONE : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_ACK_TIMEOUT_INST0_ENABLE \ + ? RAIL_EVENT_RX_ACK_TIMEOUT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_ALMOST_FULL_INST0_ENABLE \ + ? RAIL_EVENT_RX_FIFO_ALMOST_FULL : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_RECEIVED_INST0_ENABLE \ + ? RAIL_EVENT_RX_PACKET_RECEIVED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_LOST_INST0_ENABLE \ + ? RAIL_EVENT_RX_PREAMBLE_LOST : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_PREAMBLE_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SYNC1_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_SYNC1_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SYNC2_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_SYNC2_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FRAME_ERROR_INST0_ENABLE \ + ? RAIL_EVENT_RX_FRAME_ERROR : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_FULL_INST0_ENABLE \ + ? RAIL_EVENT_RX_FIFO_FULL : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_OVERFLOW_INST0_ENABLE \ + ? RAIL_EVENT_RX_FIFO_OVERFLOW : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_ADDRESS_FILTERED_INST0_ENABLE \ + ? RAIL_EVENT_RX_ADDRESS_FILTERED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TIMEOUT_INST0_ENABLE \ + ? RAIL_EVENT_RX_TIMEOUT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TX_SCHEDULED_RX_TX_STARTED_INST0_ENABLE \ + ? RAIL_EVENT_SCHEDULED_RX_STARTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_END_INST0_ENABLE \ + ? RAIL_EVENT_RX_SCHEDULED_RX_END : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_MISSED_INST0_ENABLE \ + ? RAIL_EVENT_RX_SCHEDULED_RX_MISSED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_ABORTED_INST0_ENABLE \ + ? RAIL_EVENT_RX_PACKET_ABORTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FILTER_PASSED_INST0_ENABLE \ + ? RAIL_EVENT_RX_FILTER_PASSED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_LOST_INST0_ENABLE \ + ? RAIL_EVENT_RX_TIMING_LOST : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_TIMING_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_CHANNEL_HOPPING_COMPLETE_INST0_ENABLE \ + ? RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_DUTY_CYCLE_RX_END_INST0_ENABLE \ + ? RAIL_EVENT_RX_DUTY_CYCLE_RX_END : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_IEEE802154_DATA_REQUEST_COMMAND_INST0_ENABLE \ + ? RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_ZWAVE_BEAM_INST0_ENABLE \ + ? RAIL_EVENT_ZWAVE_BEAM : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_INST0_ENABLE \ + ? RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_FIFO_ALMOST_EMPTY_INST0_ENABLE \ + ? RAIL_EVENT_TX_FIFO_ALMOST_EMPTY : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_PACKET_SENT_INST0_ENABLE \ + ? RAIL_EVENT_TX_PACKET_SENT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_PACKET_SENT_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_PACKET_SENT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_ABORTED_INST0_ENABLE \ + ? RAIL_EVENT_TX_ABORTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_ABORTED_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_ABORTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_INST0_ENABLE \ + ? RAIL_EVENT_TX_BLOCKED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_BLOCKED_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_BLOCKED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_UNDERFLOW_INST0_ENABLE \ + ? RAIL_EVENT_TX_UNDERFLOW : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_UNDERFLOW_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_UNDERFLOW : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_CLEAR_INST0_ENABLE \ + ? RAIL_EVENT_TX_CHANNEL_CLEAR : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_BUSY_INST0_ENABLE \ + ? RAIL_EVENT_TX_CHANNEL_BUSY : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_CCA_RETRY_INST0_ENABLE \ + ? RAIL_EVENT_TX_CCA_RETRY : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_START_CCA_INST0_ENABLE \ + ? RAIL_EVENT_TX_START_CCA : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_STARTED_INST0_ENABLE \ + ? RAIL_EVENT_TX_STARTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_SCHEDULED_TX_MISSED_INST0_ENABLE \ + ? RAIL_EVENT_TX_SCHEDULED_TX_MISSED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_CONFIG_UNSCHEDULED_INST0_ENABLE \ + ? RAIL_EVENT_CONFIG_UNSCHEDULED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_CONFIG_SCHEDULED_INST0_ENABLE \ + ? RAIL_EVENT_CONFIG_SCHEDULED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_SCHEDULER_STATUS_INST0_ENABLE \ + ? RAIL_EVENT_SCHEDULER_STATUS : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_CAL_NEEDED_INST0_ENABLE \ + ? RAIL_EVENT_CAL_NEEDED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_DETECT_RSSI_THRESHOLD_INST0_ENABLE \ + ? RAIL_EVENT_DETECT_RSSI_THRESHOLD : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_THERMISTOR_DONE_INST0_ENABLE \ + ? RAIL_EVENT_THERMISTOR_DONE : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_TOO_HOT_INST0_ENABLE \ + ? RAIL_EVENT_TX_BLOCKED_TOO_HOT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_TOO_HOT_INST0_ENABLE \ + ? RAIL_EVENT_TEMPERATURE_TOO_HOT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_COOL_DOWN_INST0_ENABLE \ + ? RAIL_EVENT_TEMPERATURE_COOL_DOWN : RAIL_EVENTS_NONE)) + +/** + * An inverted event mask, available to the application, specifying the radio + * events setup within the init code. + * + * @note: Because the value of this define is evaluated based on values in the + * \ref RAIL_Events_t enum, this define will only have a valid value during + * run-time. + */ +#define SL_RAIL_UTIL_INIT_EVENT_INST0_INVERSE_MASK \ + (~SL_RAIL_UTIL_INIT_EVENT_INST0_MASK) + +#ifdef __cplusplus +} +#endif + +#endif // SL_RAIL_UTIL_INIT_H diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/rail/profile_wmbus.restriction b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/rail/profile_wmbus.restriction new file mode 100644 index 0000000000..8700aedf2c --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/rail/profile_wmbus.restriction @@ -0,0 +1,10 @@ +[ + { + "name": "selectLimit", + "arguments": { + "id": "ProfilSelector", + "enabled": ["Mbus"], + "selected": "Mbus" + } + } +] diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/rail/radio_settings.radioconf b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/rail/radio_settings.radioconf new file mode 100644 index 0000000000..5ac528ec53 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/rail/radio_settings.radioconf @@ -0,0 +1,112 @@ + + + + + + + 0 + 0 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeT_M2O_100k_frameA"} + 0 + + + + + 1 + 1 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeT_M2O_100k_frameA"} + 868300000 + 0 + + + mbus_frame_format + 1 + + + mbus_mode + 8 + + + mbus_symbol_encoding + 1 + + + + + {"selectedPhy":"PHY_wMbus_ModeT_M2O_100k_frameA"} + + + + + + 0 + 0 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeC_M2O_100k_frameA"} + 0 + + + + + 1 + 1 + 1 + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeC_M2O_100k_frameA"} + 0 + + + mbus_mode + 1 + + + mbus_postamble_length + 0 + + + + + {"selectedPhy":"PHY_wMbus_ModeC_M2O_100k_frameA"} + + + + + + 0 + 0 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeS_32p768k_frameA"} + 0 + + + preamble_length + 100 + + + + + 1 + 1 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeS_32p768k_frameA"} + 0 + + + preamble_length + 100 + + + + + {"selectedPhy":"PHY_wMbus_ModeS_32p768k_frameA"} + + + + \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_init_inst0_config.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_init_inst0_config.h new file mode 100644 index 0000000000..efb8574312 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_init_inst0_config.h @@ -0,0 +1,342 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_INIT_INST0_CONFIG_H +#define SL_RAIL_UTIL_INIT_INST0_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// RAIL Init Configuration +// Initialize RAIL +// Default: 1 +#define SL_RAIL_UTIL_INIT_INST0_ENABLE 1 + +// Project Configuration +// Enable Radio Configurator Support (include rail_config.c/h generated by Radio Config) +// Default: 0 +#define SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE 1 +// Enable RAIL Init Complete Callback +// Default: 0 +#define SL_RAIL_UTIL_INIT_INIT_COMPLETE_CALLBACK_INST0_ENABLE 1 +// + +// Protocol Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_PROTOCOLS_INST0_ENABLE 1 +// Radio Configuration +// Default Radio Configuration +// Proprietary (use rail_config.c/h) +// IEEE 802.15.4 GB868 915MHz +// IEEE 802.15.4 GB868 863MHz +// Z-Wave Australia +// Z-Wave China +// Z-Wave Europe +// Z-Wave Hong Kong +// Z-Wave India +// Z-Wave Israel +// Z-Wave Japan +// Z-Wave Korea +// Z-Wave Malaysia +// Z-Wave Russia +// Z-Wave United States +// Z-Wave United States, Long Range 1 +// Z-Wave United States, Long Range 2 +// Z-Wave United States, Long Range End Device +// Z-Wave European Union, Long Range 1 +// Z-Wave European Union, Long Range 2 +// Z-Wave European Union, Long Range End Device +// Default: SL_RAIL_UTIL_PROTOCOL_ZWAVE_EU +#define SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT SL_RAIL_UTIL_PROTOCOL_PROPRIETARY +// Proprietary Radio Config Index (if Proprietary radio config selected, use index X of channelConfigs[X]) +// <0-255:1> +// Default: 0 +#define SL_RAIL_UTIL_INIT_PROTOCOL_PROPRIETARY_INST0_INDEX 0 +// +// + +// Calibration Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_CALIBRATIONS_INST0_ENABLE 1 +// Calibration Notifications +// Enable Temperature Calibration Notifications (RAIL_EVENT_CAL_NEEDED radio event issued when temperature calibrations needed, for example VCO calibration) +// Default: 0 +#define SL_RAIL_UTIL_INIT_CALIBRATION_TEMPERATURE_NOTIFY_INST0_ENABLE 1 +// Enable One-time Calibration Notifications (RAIL_EVENT_CAL_NEEDED radio event issued when one-time calibrations needed, for example IR calibration) +// Default: 0 +#define SL_RAIL_UTIL_INIT_CALIBRATION_ONETIME_NOTIFY_INST0_ENABLE 1 +// +// + +// Auto Transition Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_TRANSITIONS_INST0_ENABLE 1 +// TX Transitions +// Transition on TX Success +// RX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_SUCCESS RAIL_RF_STATE_IDLE +// Transition on TX Error +// RX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_ERROR RAIL_RF_STATE_IDLE +// +// RX Transitions +// Transition on RX Success +// RX +// TX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_SUCCESS RAIL_RF_STATE_IDLE +// Transition on RX Error +// RX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_ERROR RAIL_RF_STATE_IDLE +// +// + +// Data Format Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_DATA_FORMATS_INST0_ENABLE 1 +// TX Data +// Source of TX Data +// Use frame hardware to packetize data +// Default: TX_PACKET_DATA +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_SOURCE TX_PACKET_DATA +// Method of Providing TX Data +// Packet Mode +// FIFO Mode +// Default: PACKET_MODE +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_MODE PACKET_MODE +// +// RX Data +// Source of RX Data +// Use frame hardware to packetize data +// Get 8-bit output from demodulator +// Get lowest 16 bits of I/Q data provided to demodulator +// Get highest 16 bits of I/Q data provided to demodulator +// Default: RX_PACKET_DATA +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_SOURCE RX_PACKET_DATA +// Method of Retrieving RX Data +// Packet Mode +// FIFO Mode +// Default: PACKET_MODE +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_MODE PACKET_MODE +// +// + +// Radio Event Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENTS_INST0_ENABLE 1 +// RX Radio Events +// RX Timing Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_DETECT_INST0_ENABLE 0 +// RX Timing Lost +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_LOST_INST0_ENABLE 0 +// RX Preamble Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_DETECT_INST0_ENABLE 0 +// RX Preamble Lost +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_LOST_INST0_ENABLE 1 +// RX Sync1 Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SYNC1_DETECT_INST0_ENABLE 0 +// RX Sync2 Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SYNC2_DETECT_INST0_ENABLE 0 +// RX Filter Passed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FILTER_PASSED_INST0_ENABLE 0 +// RX Address Filtered +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_ADDRESS_FILTERED_INST0_ENABLE 1 +// RX Packet Received +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_RECEIVED_INST0_ENABLE 1 +// RX Frame Error +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FRAME_ERROR_INST0_ENABLE 1 +// RX Packet Aborted +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_ABORTED_INST0_ENABLE 1 +// RX Timeout +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TIMEOUT_INST0_ENABLE 0 +// RX Channel Hopping Complete +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_CHANNEL_HOPPING_COMPLETE_INST0_ENABLE 0 +// RX Duty Cycle RX End +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_DUTY_CYCLE_RX_END_INST0_ENABLE 0 +// +// TX Radio Events +// TX Packet Sent +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_PACKET_SENT_INST0_ENABLE 1 +// TX Aborted +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_ABORTED_INST0_ENABLE 1 +// TX Blocked +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_INST0_ENABLE 1 +// TX Started +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_STARTED_INST0_ENABLE 1 +// +// RSSI Radio Events +// RSSI Average Done +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RSSI_AVERAGE_DONE_INST0_ENABLE 0 +// +// FIFO Radio Events +// RX FIFO, Almost Full +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_ALMOST_FULL_INST0_ENABLE 0 +// RX FIFO, Full +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_FULL_INST0_ENABLE 0 +// RX FIFO, Overflow +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_OVERFLOW_INST0_ENABLE 1 +// TX FIFO, Almost Empty +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_FIFO_ALMOST_EMPTY_INST0_ENABLE 0 +// TX FIFO, Underflow +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_UNDERFLOW_INST0_ENABLE 1 +// +// CCA Radio Events +// TX CCA, Channel Clear +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_CLEAR_INST0_ENABLE 0 +// TX CCA, Channel Busy +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_BUSY_INST0_ENABLE 1 +// TX CCA, Retry +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_CCA_RETRY_INST0_ENABLE 0 +// TX CCA, Started +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_START_CCA_INST0_ENABLE 0 +// +// Scheduled Radio Events +// Scheduled RX/TX Started +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TX_SCHEDULED_RX_TX_STARTED_INST0_ENABLE 1 +// Scheduled RX End +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_END_INST0_ENABLE 1 +// Scheduled RX Missed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_MISSED_INST0_ENABLE 1 +// Scheduled TX Missed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_SCHEDULED_TX_MISSED_INST0_ENABLE 1 +// +// ACK Radio Events +// RX ACK, Timeout +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_ACK_TIMEOUT_INST0_ENABLE 0 +// TX ACK, Packet Sent +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_PACKET_SENT_INST0_ENABLE 0 +// TX ACK, Aborted +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_ABORTED_INST0_ENABLE 0 +// TX ACK, Blocked +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_BLOCKED_INST0_ENABLE 0 +// TX ACK, FIFO Underflow +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_UNDERFLOW_INST0_ENABLE 0 +// +// Protocol Radio Events +// IEEE 802.15.4 Data Request Command +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_IEEE802154_DATA_REQUEST_COMMAND_INST0_ENABLE 0 +// Z-Wave Beam +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_ZWAVE_BEAM_INST0_ENABLE 0 +// Z-Wave LR ACK Request Command +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_INST0_ENABLE 0 +// +// Dynamic Multiprotocol (DMP) Radio Events +// Config Unscheduled +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_CONFIG_UNSCHEDULED_INST0_ENABLE 1 +// Config Scheduled +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_CONFIG_SCHEDULED_INST0_ENABLE 1 +// Scheduler Status +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_SCHEDULER_STATUS_INST0_ENABLE 1 +// +// Calibration Radio Events +// Calibration Needed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_CAL_NEEDED_INST0_ENABLE 1 +// +// RSSI Radio Events +// RSSI detect threshold +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_DETECT_RSSI_THRESHOLD_INST0_ENABLE 0 +// +// Thermistor Events +// End of thermistor measurement +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_THERMISTOR_DONE_INST0_ENABLE 0 +// +// Temperature Events +// Transmit blocked because of temperature limitation +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_TOO_HOT_INST0_ENABLE 0 +// Temperature is too hot for Tx operation +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_TOO_HOT_INST0_ENABLE 0 +// Temperature has cooled enough for Tx operation +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_COOL_DOWN_INST0_ENABLE 0 +// +// + +// +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_INIT_INST0_CONFIG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_pa_config.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..527858fc5c --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_pa_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" +#ifdef RAIL_INTERNAL_BUILD +#include "sl_rail_util_pa_config_internal.h" +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#ifndef SL_RAIL_UTIL_PA_SELECTION_2P4GHZ +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_NONE +#endif +// Sub-1 GHz PA Selection +// Enable +// Disable +// Default: RAIL_TX_POWER_MODE_SUBGIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_SUBGIG_HIGHEST +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_protocol_config.h b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_protocol_config.h new file mode 100644 index 0000000000..00541a1bdd --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/config/sl_rail_util_protocol_config.h @@ -0,0 +1,130 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PROTOCOL_CONFIG_H +#define SL_RAIL_UTIL_PROTOCOL_CONFIG_H + +#include "sl_rail_util_protocol_types.h" +#ifdef RAIL_INTERNAL_BUILD +#include "sl_rail_util_protocol_config_internal.h" +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Z-Wave Settings +// Z-Wave: Configuration Options +// Enable/Disable Z-Wave +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_ENABLE 0 +// Enable Promiscuous Mode +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_PROMISCUOUS_MODE_ENABLE 1 +// Accept Beam Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_DETECT_BEAM_FRAME_ENABLE 1 +// Filter Packets Based on Node ID +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_NODE_ID_FILTERING_ENABLE 0 +// Enable Promiscuous Beam Mode +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_PROMISCUOUS_BEAM_MODE_ENABLE 0 +// + +// Z-Wave: Transition Times +// Transition time (microseconds) from idle to RX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_IDLE_TO_RX_US 100 +// Transition time (microseconds) from TX to RX +// <0-65535:1> +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_TX_TO_RX_US 0 +// Transition time (microseconds) from idle to TX +// <0-65535:1> +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_IDLE_TO_TX_US 0 +// Transition time (microseconds) from RX to TX +// <0-65535:1> +// Default: 1000 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_TO_TX_US 1000 +// + +// Z-Wave: RX Search Timeouts +// Enable RX Search timeout after Idle +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from idle +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_US 65535 +// +// Enable RX Search timeout after TX +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from TX +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_US 65535 +// +// + +// Z-Wave: Auto ACK Configuration +// Enable Auto ACKs +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_ENABLE 0 +// RX ACK timeout duration (microseconds) +// <1-9600:1> +// Default: 9600 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_TIMEOUT_US 9600 +// Radio state transition after attempting to receive ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_RX_TRANSITION_STATE RAIL_RF_STATE_RX +// Radio state transition after transmitting ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_TX_TRANSITION_STATE RAIL_RF_STATE_RX +// +// +// + +// Sidewalk Settings +// Sidewalk: Configuration Options +// Enable/Disable Sidewalk +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_SIDEWALK_ENABLE 0 +// +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PROTOCOL_CONFIG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/raillib.mk b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/raillib.mk new file mode 100644 index 0000000000..c41e2258e2 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/raillib.mk @@ -0,0 +1,35 @@ +# Required platform files. +GECKO_SDK = $(CHIBIOS_CONTRIB)/ext/gecko_sdk + +# Below are RAIL lib binding for ChibiOS. +RAILLIBSRC = \ + raillib/raillib_chibios.c + +# Below are imports from Radio Configurator +RAILLIBSRC += raillib/autogen/rail_config.c +RAILLIBSRC += raillib/autogen/sl_rail_util_callbacks.c +#RAILLIBSRC += raillib/autogen/sl_rail_util_init.c + +# Below are imports from Gecko SDK +RAILLIBSRC += $(GECKO_SDK)/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c +RAILLIBSRC += $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_protocol/sl_rail_util_protocol.c + +RAILLIBINC = \ + raillib/autogen \ + raillib/config + +RAILLIBINC += \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/pa-conversions \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_callbacks \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_callbacks/config \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_protocol \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_protocol/config \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/ble \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/ieee802154 \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/sidewalk \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/wmbus \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/zwave + +# Shared variables +ALLCSRC += $(RAILLIBSRC) +ALLINC += $(RAILLIBINC) diff --git a/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/raillib_chibios.c b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/raillib_chibios.c new file mode 100644 index 0000000000..d8c251310c --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/RAILLIB/raillib/raillib_chibios.c @@ -0,0 +1,253 @@ +#include "hal.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +uint32_t sli_tz_syscfg_read_chiprev_register(void) { + + return (SYSCFG->CHIPREV); +} +#endif + +/* SystemNNNGet are declared as weak function as they can be overwritten + by linking with system_efr32fg23.c. */ +CC_WEAK uint32_t SystemHFXOClockGet(void) { + + return EFR32_HFXO_FREQ; +} + +CC_WEAK uint32_t SystemSYSCLKGet(void) { + + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (EFR32_HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: + ret = HFXO_FREQ; + break; +#endif + +#if (EFR32_CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = EFR32_FSRCO_FREQ; + break; + + default: + osalDbgAssert(false, "Unknown clock source."); + break; + } + + return ret; +} + +CC_WEAK uint32_t SystemHFRCODPLLClockGet(void) { + + uint32_t ret = 0UL; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +} + +OSAL_IRQ_HANDLER(EFR32_RFECA0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RFECA0_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_RFECA1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RFECA1_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_SYSRTC_SEQ_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + SYSRTC_SEQ_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_AGC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + AGC_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_BUFC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + BUFC_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_EMUDG_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + EMUDG_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_FRC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + FRC_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_FRC_PRI_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + FRC_PRI_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_HOSTMAILBOX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + HOSTMAILBOX_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_MODEM_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + MODEM_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_PROTIMER_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + PROTIMER_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_RAC_RSM_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RAC_RSM_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_RAC_SEQ_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RAC_SEQ_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_SYNTH_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + SYNTH_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/Makefile b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/Makefile new file mode 100644 index 0000000000..b64592d702 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/Makefile @@ -0,0 +1,229 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +include $(CHIBIOS_CONTRIB)/ext/xmlmbus/xmlmbus_chibios.mk +include emlib/emlib.mk +include raillib/raillib.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS_CONTRIB)/os/various/bitmap.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) \ + $(CHIBIOS_CONTRIB)/os/various + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DCORTEX_ENABLE_WFI_IDLE + +# MCU and board specific. +UDEFS += \ + -DEFR32FG23B010F512IM48=1 \ + -DESCAPE_HATCH_ENABLE=TRUE + +# emlib specific. +UDEFS += \ + -DSYSTEM_NO_STATIC_MEMORY \ + -DFSRCO_FREQ=20000000UL \ + -DHFXO_FREQ=39000000UL \ + -DFRCODPLL_STARTUP_FREQ=19000000UL \ + -DRCODPLL_MAX_FREQ=0000000UL \ + -DCLKIN0_FREQ=0UL \ + -DLFRCO_FREQ=32768UL \ + -DULFRCO_FREQ=1000UL \ + -DLFXO_FREQ=LFRCO_FREQ +# -DSL_TRUSTZONE_NONSECURE +# -DSL_TRUSTZONE_SECURE \ + +# RAIL lib specific. +UDEFS += \ + -D_SILICON_LABS_32B_SERIES_1_CONFIG=0 \ + -DSL_RAIL_UTIL_PROTOCOL_IEEE802154_GB868_ENABLE=0 \ + -DFEAT_RF_2G4=0 \ + -DFEAT_RF_SUBG=1 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/radio/rail_lib/common \ + $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/radio/rail_lib/chip/efr32/efr32xg2x + +# List the user directory to look for the libraries here +ULIBDIR = $(CHIBIOS_CONTRIB)/ext/gecko_sdk/platform/radio/rail_lib/autogen/librail_release + +# List all user libraries here +ULIBS = -l:librail_efr32xg23_gcc_release.a + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/halconf.h new file mode 100644 index 0000000000..0ecdc33c4e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/halconf_community.h new file mode 100644 index 0000000000..e0350ac110 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 TRUE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 FALSE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 FALSE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/mcuconf.h new file mode 100644 index 0000000000..3116692344 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/cfg/mcuconf.h @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG23 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_HFRCO_ENABLED TRUE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED TRUE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFXO +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_EM01GRPCCLK + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 TRUE +#define EFR32_SIO_USE_EUSART2 TRUE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib.mk b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib.mk new file mode 100644 index 0000000000..409e60f557 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib.mk @@ -0,0 +1,59 @@ +# Required platform files. +GECKO_SDK = $(CHIBIOS_CONTRIB)/ext/gecko_sdk + +EMLIBSRC = \ + emlib/emlib_chibios.c \ + $(GECKO_SDK)/platform/emlib/src/em_acmp.c \ + $(GECKO_SDK)/platform/emlib/src/em_adc.c \ + $(GECKO_SDK)/platform/emlib/src/em_aes.c \ + $(GECKO_SDK)/platform/emlib/src/em_burtc.c \ + $(GECKO_SDK)/platform/emlib/src/em_can.c \ + $(GECKO_SDK)/platform/emlib/src/em_cmu.c \ + $(GECKO_SDK)/platform/emlib/src/em_cmu_fpga.c \ + $(GECKO_SDK)/platform/emlib/src/em_cryotimer.c \ + $(GECKO_SDK)/platform/emlib/src/em_crypto.c \ + $(GECKO_SDK)/platform/emlib/src/em_csen.c \ + $(GECKO_SDK)/platform/emlib/src/em_dac.c \ + $(GECKO_SDK)/platform/emlib/src/em_dbg.c \ + $(GECKO_SDK)/platform/emlib/src/em_dma.c \ + $(GECKO_SDK)/platform/emlib/src/em_ebi.c \ + $(GECKO_SDK)/platform/emlib/src/em_emu.c \ + $(GECKO_SDK)/platform/emlib/src/em_eusart.c \ + $(GECKO_SDK)/platform/emlib/src/em_gpcrc.c \ + $(GECKO_SDK)/platform/emlib/src/em_gpio.c \ + $(GECKO_SDK)/platform/emlib/src/em_i2c.c \ + $(GECKO_SDK)/platform/emlib/src/em_iadc.c \ + $(GECKO_SDK)/platform/emlib/src/em_idac.c \ + $(GECKO_SDK)/platform/emlib/src/em_lcd.c \ + $(GECKO_SDK)/platform/emlib/src/em_ldma.c \ + $(GECKO_SDK)/platform/emlib/src/em_lesense.c \ + $(GECKO_SDK)/platform/emlib/src/em_letimer.c \ + $(GECKO_SDK)/platform/emlib/src/em_leuart.c \ + $(GECKO_SDK)/platform/emlib/src/em_msc.c \ + $(GECKO_SDK)/platform/emlib/src/em_opamp.c \ + $(GECKO_SDK)/platform/emlib/src/em_pcnt.c \ + $(GECKO_SDK)/platform/emlib/src/em_pdm.c \ + $(GECKO_SDK)/platform/emlib/src/em_prs.c \ + $(GECKO_SDK)/platform/emlib/src/em_qspi.c \ + $(GECKO_SDK)/platform/emlib/src/em_rmu.c \ + $(GECKO_SDK)/platform/emlib/src/em_rtc.c \ + $(GECKO_SDK)/platform/emlib/src/em_rtcc.c \ + $(GECKO_SDK)/platform/emlib/src/em_se.c \ + $(GECKO_SDK)/platform/emlib/src/em_system.c \ + $(GECKO_SDK)/platform/emlib/src/em_timer.c \ + $(GECKO_SDK)/platform/emlib/src/em_usart.c \ + $(GECKO_SDK)/platform/emlib/src/em_vcmp.c \ + $(GECKO_SDK)/platform/emlib/src/em_vdac.c \ + $(GECKO_SDK)/platform/emlib/src/em_wdog.c + +#EMLIBSRC += $(GECKO_SDK)/platform/emlib/src/em_core.c +#EMLIBSRC += $(GECKO_SDK)/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c + +EMLIBINC = \ + emlib \ + $(GECKO_SDK)/platform/common/inc \ + $(GECKO_SDK)/platform/emlib/inc + +# Shared variables +ALLCSRC += $(EMLIBSRC) +ALLINC += $(EMLIBINC) diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib_chibios.c b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib_chibios.c new file mode 100644 index 0000000000..34431c6aa5 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib_chibios.c @@ -0,0 +1,32 @@ +#include "hal.h" +#include "em_core_generic.h" + +CORE_irqState_t CORE_EnterCritical(void) { + + return (chSysGetStatusAndLockX()); +} + +void CORE_ExitCritical(CORE_irqState_t irqState) { + + chSysRestoreStatusX(irqState); +} + +CORE_irqState_t CORE_EnterAtomic(void) { + + return (chSysGetStatusAndLockX()); +} + +void CORE_ExitAtomic(CORE_irqState_t irqState) { + + chSysRestoreStatusX(irqState); +} + +#if 0 +void _start(void) { + + extern int main(void); + main(); + NVIC_SystemReset(); +} +#endif + diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib_chibios.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib_chibios.h new file mode 100644 index 0000000000..013d94c8d9 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/emlib/emlib_chibios.h @@ -0,0 +1,22 @@ +#ifndef EMLIB_CHIBIOS_H +#define EMLIB_CHIBIOS_H + +#include "em_acmp.h" +#include "em_assert.h" +#include "em_cryotimer.h" +#include "em_chip.h" +#include "em_cmu.h" +#include "em_emu.h" +#include "em_eusart.h" +#include "em_gpio.h" +#include "em_letimer.h" +#include "em_lcd.h" +#include "em_pcnt.h" +#include "em_prs.h" +#include "em_lesense.h" +#include "em_system.h" +#include "em_syscfg.h" +#include "em_vdac.h" + +#endif /* EMLIB_CHIBIOS_H */ + diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/main.c b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/main.c new file mode 100644 index 0000000000..63728305cf --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/main.c @@ -0,0 +1,217 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "cmsis_os.h" +#include "hal.h" + +#include "rail.h" +#include "sli_rail_util_callbacks.h" // for internal-only callback signatures +#include "sl_rail_util_init.h" +#include "sl_rail_util_protocol.h" + +static void led_on(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static void led_toggle(void) { + + /* PB2 = LED */ + palTogglePad(GPIOB, 2); +} + +void st_callback(unsigned alarm) { + + stStopAlarmN(alarm); + stStartAlarmN(alarm, stGetCounter() + chTimeMS2I(3000)); +} + +extern const RAIL_ChannelConfig_t *channelConfigs[]; + +static RAIL_Handle_t railHandle; + +enum { + WMBUS_MODE_T1A = 0, + WMBUS_MODE_C1A = 1, + WMBUS_MODE_S1 = 2 +}; + +static void send_datagram(void) { + + static const uint8_t wmbus_datagram_1[] = { + 0x31, 0x44, 0x93, 0x44, 0x48, 0x32, 0x75, 0x26, 0x35, 0x08, // 0x6D, 0x95, + 0x7A, 0xA3, 0x00, 0x00, 0x20, 0x0B, 0x6E, 0x16, 0x00, 0x00, 0x4B, 0x6E, 0x21, 0x02, 0x00, 0x42, // 0x91, 0xDD, + 0x6C, 0xBF, 0x2A, 0xCB, 0x08, 0x6E, 0x16, 0x00, 0x00, 0xC2, 0x08, 0x6C, 0xDE, 0x29, 0x32, 0x6C, // 0x8C, 0xC4, + 0xFF, 0xFF, 0x04, 0x6D, 0x27, 0x0E, 0xD2, 0x2A, // 0x3D, 0x89 + }; + + CC_ALIGN_DATA(16)static uint8_t railFifo[1024]; + + static int config_nr = WMBUS_MODE_T1A; + const RAIL_ChannelConfig_t *channel_config = channelConfigs[config_nr]; + config_nr = (config_nr + 1) % 3; + (void)RAIL_ConfigChannels(railHandle, channel_config, + &sli_rail_util_on_channel_config_change); + + led_toggle(); + + #define RAIL_CHANNEL_0 0 + memcpy(railFifo, wmbus_datagram_1, sizeof(wmbus_datagram_1)); + RAIL_SetTxFifo(railHandle, railFifo, sizeof(wmbus_datagram_1), sizeof(railFifo)); + RAIL_StartTx(railHandle, RAIL_CHANNEL_0, RAIL_TX_OPTIONS_DEFAULT, NULL); +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_assert_failed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code) { + + (void)rail_handle; + (void)error_code; + osalDbgAssert(false, "rail_handle with error_code"); +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_rf_ready(RAIL_Handle_t rail_handle) { + + (void)rail_handle; +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) { + + (void)rail_handle; + (void)entry; +} + +/* Overload weak function from sl_rail_util_callbacks.c. */ +void sl_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events) { + + (void)rail_handle; + (void)events; +} + +void custom_RAIL_Init(void) { + + RAIL_Status_t status; + (void)status; + + RAIL_Config_t sl_rail_config = { + .eventsCallback = &sli_rail_util_on_event, + // Other fields are ignored nowadays + }; + railHandle = RAIL_Init(&sl_rail_config, &sli_rail_util_on_rf_ready); + + RAIL_DataConfig_t data_config = { + .txSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_SOURCE, + .rxSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_SOURCE, + .txMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_MODE, + .rxMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_MODE, + }; + status = RAIL_ConfigData(railHandle, &data_config); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + const RAIL_ChannelConfig_t *channel_config = channelConfigs[WMBUS_MODE_C1A]; + + (void)RAIL_ConfigChannels(railHandle, + channel_config, + &sli_rail_util_on_channel_config_change); + status = sl_rail_util_protocol_config(railHandle, + SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + status = RAIL_ConfigCal(railHandle, + 0U + | (SL_RAIL_UTIL_INIT_CALIBRATION_TEMPERATURE_NOTIFY_INST0_ENABLE + ? RAIL_CAL_TEMP : 0U) + | (SL_RAIL_UTIL_INIT_CALIBRATION_ONETIME_NOTIFY_INST0_ENABLE + ? RAIL_CAL_ONETIME : 0U)); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + status = RAIL_ConfigEvents(railHandle, RAIL_EVENTS_ALL, + SL_RAIL_UTIL_INIT_EVENT_INST0_MASK); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + RAIL_StateTransitions_t tx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_ERROR + }; + status = RAIL_SetTxTransitions(railHandle, + &tx_transitions); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); + + RAIL_StateTransitions_t rx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_ERROR + }; + status = RAIL_SetRxTransitions(railHandle, + &rx_transitions); + osalDbgCheck(status == RAIL_STATUS_NO_ERROR); +} + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; + (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + led_off(); + custom_RAIL_Init(); + stSetCallback(1, st_callback); + stStartAlarmN(1, stGetCounter() + chTimeMS2I(3000)); + led_on(); + + //RAIL_TxStreamStart(railHandle, RAIL_STREAM_PN9_STREAM); + //RAIL_TxStreamStart(railHandle, RAIL_STREAM_CARRIER_WAVE); + + systime_t prev = chVTGetSystemTime(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + send_datagram(); + prev = chThdSleepUntilWindowed(prev, chTimeAddX(prev, TIME_MS2I(3000))); + } +} + diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/radioconf_generation_log.json b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/radioconf_generation_log.json new file mode 100644 index 0000000000..c4f4bcfba1 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/radioconf_generation_log.json @@ -0,0 +1,706 @@ +[ + { + "channel_name": "wmbus_mode_t-m2o_mode_t", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "0000111101" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 330000 + }, + { + "name": "Desired Bitrate [bps]", + "value": 99999 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 100000.0 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868949980 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 214977 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 99999.99999999999 + }, + { + "name": "Actual Deviation [Hz]", + "value": 50372.22057580948 + }, + { + "name": "Target Modulation Index", + "value": 1.000010000100001 + }, + { + "name": "Actual Modulation Index", + "value": 1.0074444115161896 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 199999 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 199999 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 330000 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 9.285714285714288 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 5 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 169.820512974359 + } + ] + }, + { + "channel_name": "wmbus_mode_t-o2m_mode_t", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "000111011010010110" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 333487 + }, + { + "name": "Desired Bitrate [bps]", + "value": 32768 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 32767.999445637863 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868299990 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 216737 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 32765.836028152942 + }, + { + "name": "Actual Deviation [Hz]", + "value": 49925.92823691666 + }, + { + "name": "Target Modulation Index", + "value": 3.0517578125 + }, + { + "name": "Actual Modulation Index", + "value": 3.047236882419009 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 185714 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 28.33962264150943 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 2 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 416.0556363415578 + } + ] + }, + { + "channel_name": "wmbus_mode_c-m2o_mode_c", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "00001111010101010011001101" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 314896 + }, + { + "name": "Desired Bitrate [bps]", + "value": 100000 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 100000.0 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -12.446100897895253 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868949980 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 207439 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 100000.75120756615 + }, + { + "name": "Actual Deviation [Hz]", + "value": 44862.75895033032 + }, + { + "name": "Target Modulation Index", + "value": 0.9 + }, + { + "name": "Actual Modulation Index", + "value": 0.8972551790066063 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.TRECS_VITERBI" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 190000 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 110000 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 162500 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 7.0 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 700005.2584529631 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 7 + }, + { + "name": "Effective Syncword Length", + "value": 32 + }, + { + "name": "Effective Preamble Length", + "value": 32 + }, + { + "name": "Number of Bits Used from Preamble to Syncword [bits]", + "value": 6 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "TRECS syncword timeout [us]", + "value": 770.0 + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 179.22578646314105 + } + ] + }, + { + "channel_name": "wmbus_mode_c-o2m_mode_c", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "01010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "00001111010101010011001101" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 166896 + }, + { + "name": "Desired Bitrate [bps]", + "value": 50000 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 50000.0 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -14.178302025260141 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868949980 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 133424 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 49999.88262497506 + }, + { + "name": "Actual Deviation [Hz]", + "value": 24689.509154995903 + }, + { + "name": "Target Modulation Index", + "value": 1.0 + }, + { + "name": "Actual Modulation Index", + "value": 0.9875803661998361 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.TRECS_SLICER" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 100000 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 100000 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 100000 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 7.000000000000001 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 349999.1783748254 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 8 + }, + { + "name": "Effective Syncword Length", + "value": 32 + }, + { + "name": "Effective Preamble Length", + "value": 32 + }, + { + "name": "Number of Bits Used from Preamble to Syncword [bits]", + "value": 6 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "TRECS syncword timeout [us]", + "value": 1540.0 + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 357.7993666402244 + } + ] + }, + { + "channel_name": "wmbus_mode_s-m2o_mode_s", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "0101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "000111011010010110" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 333487 + }, + { + "name": "Desired Bitrate [bps]", + "value": 32768 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 32767.999445637863 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868299990 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 216737 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 32765.836028152942 + }, + { + "name": "Actual Deviation [Hz]", + "value": 49925.92823691666 + }, + { + "name": "Target Modulation Index", + "value": 3.0517578125 + }, + { + "name": "Actual Modulation Index", + "value": 3.047236882419009 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 185714 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 28.33962264150943 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 2 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 416.0556363415578 + } + ] + }, + { + "channel_name": "wmbus_mode_s-o2m_mode_s", + "result_code": "0", + "error_message": "", + "logs": [], + "cfg_logs": [ + { + "name": "Preamble Binary Pattern", + "value": "0101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101" + }, + { + "name": "Syncword Binary Pattern", + "value": "000111011010010110" + }, + { + "name": "Pre Signal Lock RX Bandwidth [Hz]", + "value": 333487 + }, + { + "name": "Desired Bitrate [bps]", + "value": 32768 + }, + { + "name": "Actual TX Baudrate [baud]", + "value": 32767.999445637863 + }, + { + "name": "Calculated RSSI Offset [dB]", + "value": -11.781244155064684 + }, + { + "name": "Actual Carrier Frequency [Hz]", + "value": 868299990 + }, + { + "name": "Actual Intermediate Frequency [Hz]", + "value": 216737 + }, + { + "name": "Synthesizer Resolution [Hz]", + "value": 24.7955322265625 + }, + { + "name": "Actual RX Baudrate [baud]", + "value": 32765.836028152942 + }, + { + "name": "Actual Deviation [Hz]", + "value": 49925.92823691666 + }, + { + "name": "Target Modulation Index", + "value": 3.0517578125 + }, + { + "name": "Actual Modulation Index", + "value": 3.047236882419009 + }, + { + "name": "Selected Demodulator", + "value": "DemodSelectEnum.BCR" + }, + { + "name": "Carson Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "Theoretical Required Demodulator Bandwidth [Hz]", + "value": 132768 + }, + { + "name": "RX Crystal Accuracy [ppm]", + "value": 60 + }, + { + "name": "TX Crystal Accuracy [ppm]", + "value": 25 + }, + { + "name": "Post Signal Lock RX Bandwidth [Hz]", + "value": 185714 + }, + { + "name": "RSSI Measurement Period", + "value": 3 + }, + { + "name": "Actual Demodulator Oversampling Rate", + "value": 28.33962264150943 + }, + { + "name": "Raw Data Sampling Rate [sps]", + "value": 928571.4285714285 + }, + { + "name": "Signal Propagation Delay [symbol]", + "value": 2 + }, + { + "name": "Injection Side", + "value": "LoInjectionSideEnum.HIGH_SIDE" + }, + { + "name": "RSSI Update Period [symbol]", + "value": 8 + }, + { + "name": "RSSI Access Time After RX Start [us]", + "value": 416.0556363415578 + } + ] + } +] \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/rail_config.c b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/rail_config.c new file mode 100644 index 0000000000..39d7e1fb24 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/rail_config.c @@ -0,0 +1,1225 @@ +/***************************************************************************//** + * @brief RAIL Configuration + * @details + * WARNING: Auto-Generated Radio Config - DO NOT EDIT + * Radio Configurator Version: 2402.6.1 + * RAIL Adapter Version: 2.4.33 + * RAIL Compatibility: 2.x + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" +#include "rail_config.h" + +uint32_t RAILCb_CalcSymbolRate(RAIL_Handle_t railHandle) +{ + (void) railHandle; + return 0U; +} + +uint32_t RAILCb_CalcBitRate(RAIL_Handle_t railHandle) +{ + (void) railHandle; + return 0U; +} + +void RAILCb_ConfigFrameTypeLength(RAIL_Handle_t railHandle, + const RAIL_FrameType_t *frameType) +{ + (void) railHandle; + (void) frameType; +} + +uint32_t frameCodingTable[] = { + 2155905152, 2155905152, 58753152, 2147615104, + 125862016, 2147909760, 2147485056, 2155905028, + 192970880, 2148142976, 2155874688, 2155905032, + 2148404608, 2155905036, 2155905152, 2155905152, + 185470234, 320215324, 589703468, 624046388, +}; + +static const uint8_t irCalConfig[] = { + 20, 41, 2, 0, 0, 49, 17, 0, 0, 0, 1, 0, 2, 100, 0, 1, 1, 47, 0, 0, 7 +}; + +static const int32_t timingConfig_0[] = { + 23455, 23455, 5000, 0 +}; + +static const int32_t timingConfig_1[] = { + 23455, 23455, 15259, 0 +}; + +static const int32_t timingConfig_2[] = { + 64447, 64447, 5000, 0 +}; + +static const int32_t timingConfig_3[] = { + 48093, 48093, 20000, 0 +}; + +static const uint8_t hfxoRetimingConfigEntries[] = { + 1, 0, 0, 0, 0xc0, 0x17, 0x53, 0x02, 4, 12, 0, 0, 0xe0, 0x02, 0, 0, 0, 0, 0x3c, 0x03, 1, 2, 5, 4, 0x98, 0x03, 1, 2, 5, 5, 0xf4, 0x03, 1, 2, 6, 5 +}; + +static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr_0 = { +#if RAIL_SUPPORTS_OFDM_PA + { +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL } + } +#else // RAIL_SUPPORTS_OFDM_PA +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS +#endif // RAIL_SUPPORTS_OFDM_PA +}; + +static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr_1 = { +#if RAIL_SUPPORTS_OFDM_PA + { +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL } + } +#else // RAIL_SUPPORTS_OFDM_PA +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS +#endif // RAIL_SUPPORTS_OFDM_PA +}; + +static RAIL_ChannelConfigEntryAttr_t channelConfigEntryAttr_2 = { +#if RAIL_SUPPORTS_OFDM_PA + { +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL } + } +#else // RAIL_SUPPORTS_OFDM_PA +#ifdef RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + { 0xFFFFFFFFUL, 0xFFFFFFFFUL, }, +#else + { 0xFFFFFFFFUL }, +#endif // RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS +#endif // RAIL_SUPPORTS_OFDM_PA +}; + +static const uint32_t phyInfo_0[] = { + 17UL, + 0x00539782UL, // 83.59183673469387 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_0, + 0x00000000UL, + 8UL, + 0UL, + 100000UL, + 0x00F50101UL, + 0x071021DEUL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 99999UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +static const uint32_t phyInfo_1[] = { + 17UL, + 0x00492492UL, // 73.14285714285714 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_1, + 0x00000000UL, + 8UL, + 0UL, + 32767UL, + 0x00F50201UL, + 0x07102225UL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 32765UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +static const uint32_t phyInfo_2[] = { + 17UL, + 0x00400000UL, // 64.0 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_2, + 0x00000000UL, + 8UL, + 0UL, + 100000UL, + 0x00F40101UL, + 0x075020AEUL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 100000UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +static const uint32_t phyInfo_3[] = { + 17UL, + 0x00369D03UL, // 54.61333333333334 + (uint32_t) NULL, + (uint32_t) irCalConfig, + (uint32_t) timingConfig_3, + 0x00000000UL, + 8UL, + 0UL, + 50000UL, + 0x00F20101UL, + 0x07101505UL, + (uint32_t) NULL, + (uint32_t) hfxoRetimingConfigEntries, + (uint32_t) NULL, + 0UL, + 0UL, + 49999UL, + (uint32_t) NULL, + (uint32_t) NULL, + (uint32_t) NULL, +}; + +const uint32_t wmbus_mode_t_modemConfigBase[] = { + 0x0002400CUL, 0x000A8001UL, + /* 4010 */ 0x000040FFUL, + 0x00024020UL, 0x00000000UL, + /* 4024 */ 0x00000000UL, + 0x00034040UL, (uint32_t) &frameCodingTable, + /* 4044 */ 0x00004000UL, + /* 4048 */ 0x000007A4UL, + 0x0002405CUL, 0x00000000UL, + /* 4060 */ 0x00000000UL, + 0x000140A8UL, 0x00000007UL, + 0x000440BCUL, 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + 0x00044108UL, 0x00004C09UL, + /* 410C */ 0x00004C0FUL, + /* 4110 */ 0x00004D09UL, + /* 4114 */ 0x00004D0FUL, + 0x1001C020UL, 0x0007F800UL, + 0x3001C020UL, 0x002801FEUL, + 0x1001C024UL, 0x000000FFUL, + 0x3001C024UL, 0x00001300UL, + 0x0005C028UL, 0x03B380ECUL, + /* C02C */ 0x51407543UL, + /* C030 */ 0xF8000FA0UL, + /* C034 */ 0x00004030UL, + /* C038 */ 0x0007AAA8UL, + 0x0002C040UL, 0x00000000UL, + /* C044 */ 0x00000000UL, + 0x000FC068UL, 0x0002C688UL, + /* C06C */ 0x00000520UL, + /* C070 */ 0x000010BAUL, + /* C074 */ 0x003F0000UL, + /* C078 */ 0x00EE008DUL, + /* C07C */ 0x03AC01F6UL, + /* C080 */ 0x079604F5UL, + /* C084 */ 0x0D9C09DEUL, + /* C088 */ 0x179311C3UL, + /* C08C */ 0x26F51DFEUL, + /* C090 */ 0x3FFF32BDUL, + /* C094 */ 0x1BF815FEUL, + /* C098 */ 0x2DB423DCUL, + /* C09C */ 0x3FFF39D0UL, + /* C0A0 */ 0x00003FFFUL, + 0x0005C0A8UL, 0x15724BBDUL, + /* C0AC */ 0x0518A311UL, + /* C0B0 */ 0x76543210UL, + /* C0B4 */ 0x00000A98UL, + /* C0B8 */ 0x00000000UL, + 0x0004C0CCUL, 0x000000EEUL, + /* C0D0 */ 0x00000000UL, + /* C0D4 */ 0x000A0001UL, + /* C0D8 */ 0x00280001UL, + 0x01010008UL, 0x000007A6UL, + 0x01010018UL, 0x00000000UL, + 0x01010020UL, 0x0000A6BCUL, + 0x01124090UL, 0x00000000UL, + /* 4094 */ 0x00000000UL, + /* 4098 */ 0x00000000UL, + /* 409C */ 0x00000000UL, + /* 40A0 */ 0x00000000UL, + /* 40A4 */ 0x00000000UL, + /* 40A8 */ 0x00000000UL, + /* 40AC */ 0x00000000UL, + /* 40B0 */ 0x00000000UL, + /* 40B4 */ 0x00000000UL, + /* 40B8 */ 0x00000000UL, + /* 40BC */ 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + /* 40CC */ 0x00000000UL, + /* 40D0 */ 0x00000000UL, + /* 40D4 */ 0x00000000UL, + 0x110140E0UL, 0x000001F8UL, + 0x310140E0UL, 0x00000201UL, + 0x01024110UL, 0x00051E33UL, + /* 4114 */ 0x00000000UL, + 0x0108411CUL, 0x04000000UL, + /* 4120 */ 0x00000000UL, + /* 4124 */ 0x078304FFUL, + /* 4128 */ 0x3AC81388UL, + /* 412C */ 0x0C6606FFUL, + /* 4130 */ 0x078304FFUL, + /* 4134 */ 0x03FF1388UL, + /* 4138 */ 0xF00A20BCUL, + 0x0102414CUL, 0x00003B80UL, + /* 4150 */ 0x00000000UL, + 0x01024158UL, 0x00000000UL, + /* 415C */ 0x0000FDFFUL, + 0x01014164UL, 0x0000010CUL, + 0x010B416CUL, 0x40000000UL, + /* 4170 */ 0x00000000UL, + /* 4174 */ 0x00000000UL, + /* 4178 */ 0x00000000UL, + /* 417C */ 0x00000000UL, + /* 4180 */ 0x00000000UL, + /* 4184 */ 0x00000101UL, + /* 4188 */ 0x00000000UL, + /* 418C */ 0x00000000UL, + /* 4190 */ 0x00000000UL, + /* 4194 */ 0x00000000UL, + 0x010241A4UL, 0x00000000UL, + /* 41A8 */ 0x00000000UL, + 0x010841B0UL, 0x00000000UL, + /* 41B4 */ 0x00200000UL, + /* 41B8 */ 0x00000000UL, + /* 41BC */ 0x00000000UL, + /* 41C0 */ 0x003C0000UL, + /* 41C4 */ 0x0006AAAAUL, + /* 41C8 */ 0x00000000UL, + /* 41CC */ 0x00000000UL, + 0x010341D4UL, 0x000001D0UL, + /* 41D8 */ 0x00020000UL, + /* 41DC */ 0x00000000UL, + 0x010741E4UL, 0x1492F42DUL, + /* 41E8 */ 0x003858D3UL, + /* 41EC */ 0x007AFDBEUL, + /* 41F0 */ 0x0041732CUL, + /* 41F4 */ 0x0DD53E7FUL, + /* 41F8 */ 0x03283A26UL, + /* 41FC */ 0x302424E2UL, + 0x01064220UL, 0x00000000UL, + /* 4224 */ 0x8000FFFFUL, + /* 4228 */ 0x00000000UL, + /* 422C */ 0x40001860UL, + /* 4230 */ 0x00000000UL, + /* 4234 */ 0x00000000UL, + 0x0101423CUL, 0x00000000UL, + 0x01034244UL, 0x00000014UL, + /* 4248 */ 0x00000000UL, + /* 424C */ 0x04000008UL, + 0x01018010UL, 0x00000003UL, + 0x0103809CUL, 0x00000000UL, + /* 80A0 */ 0x0003B870UL, + /* 80A4 */ 0x0003B870UL, + 0x110180A8UL, 0x000001F6UL, + 0x310180A8UL, 0x01014201UL, + 0x110180ACUL, 0x000001F6UL, + 0x310180ACUL, 0x01014201UL, + 0x010280B0UL, 0x02000300UL, + /* 80B4 */ 0x02000300UL, + 0x02030098UL, 0x00000000UL, + /* 009C */ 0x04000C00UL, + /* 00A0 */ 0x0000044CUL, + 0x020200D8UL, 0xAA400005UL, + /* 00DC */ 0x00000188UL, + 0x120100ECUL, 0x00000FE0UL, + 0x320100ECUL, 0x5151200DUL, + 0x020100F0UL, 0x0000052BUL, + 0x02010100UL, 0x00000110UL, + 0x12010104UL, 0x00000000UL, + 0x32010104UL, 0x00000110UL, + 0x12010110UL, 0x000FFF00UL, + 0x32010110UL, 0x42000002UL, + 0x1201012CUL, 0x001FFC00UL, + 0x3201012CUL, 0x008000A9UL, + 0x02010140UL, 0x0000003FUL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510063UL, + 0x02020168UL, 0x00060010UL, + /* 016C */ 0x00062000UL, + 0x02010174UL, 0x0C100169UL, + 0x12010178UL, 0x001C0000UL, + 0x32010178UL, 0xCFE00440UL, + 0x12010180UL, 0x00000779UL, + 0x32010180UL, 0x00000006UL, + 0x02020188UL, 0x00000090UL, + /* 018C */ 0x00000000UL, + 0x120101ACUL, 0x000001F8UL, + 0x320101ACUL, 0x00010204UL, + 0x020101B0UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t wmbus_mode_c_modemConfigBase[] = { + 0x0002400CUL, 0x000A8001UL, + /* 4010 */ 0x000040FFUL, + 0x00024020UL, 0x00000000UL, + /* 4024 */ 0x00000000UL, + 0x00074030UL, 0x00000000UL, + /* 4034 */ 0x00000000UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000000UL, + /* 4040 */ 0x00000000UL, + /* 4044 */ 0x00004000UL, + /* 4048 */ 0x000007A4UL, + 0x00014050UL, 0x00000000UL, + 0x0002405CUL, 0x00000000UL, + /* 4060 */ 0x00000000UL, + 0x000140A8UL, 0x00000007UL, + 0x000440BCUL, 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + 0x00044108UL, 0x00004C09UL, + /* 410C */ 0x00004C0FUL, + /* 4110 */ 0x00004D09UL, + /* 4114 */ 0x00004D0FUL, + 0x1001C020UL, 0x0007F800UL, + 0x3001C020UL, 0x002801FEUL, + 0x1001C024UL, 0x000000FFUL, + 0x3001C024UL, 0x00001300UL, + 0x0008C028UL, 0x03B380ECUL, + /* C02C */ 0x51407543UL, + /* C030 */ 0xF8000FA0UL, + /* C034 */ 0x00004030UL, + /* C038 */ 0x0007AAA8UL, + /* C03C */ 0x00000000UL, + /* C040 */ 0x00000000UL, + /* C044 */ 0x00000000UL, + 0x000DC070UL, 0x000010BAUL, + /* C074 */ 0x003F0000UL, + /* C078 */ 0x00EE008DUL, + /* C07C */ 0x03AC01F6UL, + /* C080 */ 0x079604F5UL, + /* C084 */ 0x0D9C09DEUL, + /* C088 */ 0x179311C3UL, + /* C08C */ 0x26F51DFEUL, + /* C090 */ 0x3FFF32BDUL, + /* C094 */ 0x1BF815FEUL, + /* C098 */ 0x2DB423DCUL, + /* C09C */ 0x3FFF39D0UL, + /* C0A0 */ 0x00003FFFUL, + 0x0005C0A8UL, 0x15724BBDUL, + /* C0AC */ 0x0518A311UL, + /* C0B0 */ 0x76543210UL, + /* C0B4 */ 0x00000A98UL, + /* C0B8 */ 0x00000000UL, + 0x0003C0D0UL, 0x00000000UL, + /* C0D4 */ 0x000A0001UL, + /* C0D8 */ 0x00280001UL, + 0x01010008UL, 0x000007A6UL, + 0x01010018UL, 0x00000000UL, + 0x01010020UL, 0x0000A6BCUL, + 0x01044058UL, 0x00000000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + 0x010F409CUL, 0x00000000UL, + /* 40A0 */ 0x00000000UL, + /* 40A4 */ 0x00000000UL, + /* 40A8 */ 0x00000000UL, + /* 40AC */ 0x00000000UL, + /* 40B0 */ 0x00000000UL, + /* 40B4 */ 0x00000000UL, + /* 40B8 */ 0x00000000UL, + /* 40BC */ 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + /* 40CC */ 0x00000000UL, + /* 40D0 */ 0x00000000UL, + /* 40D4 */ 0x00000000UL, + 0x110140E0UL, 0x000001F8UL, + 0x310140E0UL, 0x00000201UL, + 0x01024110UL, 0x00051E33UL, + /* 4114 */ 0x00000000UL, + 0x01074120UL, 0x00000000UL, + /* 4124 */ 0x078304FFUL, + /* 4128 */ 0x3AC81388UL, + /* 412C */ 0x0C6606FFUL, + /* 4130 */ 0x078304FFUL, + /* 4134 */ 0x03FF1388UL, + /* 4138 */ 0xF00A20BCUL, + 0x0102414CUL, 0x00403B89UL, + /* 4150 */ 0x800003C0UL, + 0x01024158UL, 0x00000000UL, + /* 415C */ 0x0000FDFFUL, + 0x01014164UL, 0x0000010CUL, + 0x010B416CUL, 0x40000000UL, + /* 4170 */ 0x00000000UL, + /* 4174 */ 0x00000000UL, + /* 4178 */ 0x00000000UL, + /* 417C */ 0x00000000UL, + /* 4180 */ 0x00000000UL, + /* 4184 */ 0x00000101UL, + /* 4188 */ 0x00000000UL, + /* 418C */ 0x00000000UL, + /* 4190 */ 0x00000000UL, + /* 4194 */ 0x00000000UL, + 0x010241A4UL, 0x00000000UL, + /* 41A8 */ 0x00000000UL, + 0x010941B0UL, 0x00000000UL, + /* 41B4 */ 0xC03F9658UL, + /* 41B8 */ 0x00000000UL, + /* 41BC */ 0x00000000UL, + /* 41C0 */ 0x003C0000UL, + /* 41C4 */ 0x0006AAAAUL, + /* 41C8 */ 0x00000000UL, + /* 41CC */ 0x00000000UL, + /* 41D0 */ 0x55555555UL, + 0x010241D8UL, 0x00C60007UL, + /* 41DC */ 0x00000000UL, + 0x010741E4UL, 0x11E107F9UL, + /* 41E8 */ 0x0005E9CCUL, + /* 41EC */ 0x006C8E32UL, + /* 41F0 */ 0x004EB132UL, + /* 41F4 */ 0x0E1C0182UL, + /* 41F8 */ 0x0265F774UL, + /* 41FC */ 0x3350259BUL, + 0x0107421CUL, 0x80000000UL, + /* 4220 */ 0x00000000UL, + /* 4224 */ 0x0000004DUL, + /* 4228 */ 0x00000000UL, + /* 422C */ 0x40001860UL, + /* 4230 */ 0x00000000UL, + /* 4234 */ 0x00000000UL, + 0x0101423CUL, 0x00000000UL, + 0x01024244UL, 0x00000014UL, + /* 4248 */ 0x00000000UL, + 0x010F4330UL, 0x00000000UL, + /* 4334 */ 0x00000000UL, + /* 4338 */ 0x00000000UL, + /* 433C */ 0x00000000UL, + /* 4340 */ 0x00000000UL, + /* 4344 */ 0x00000000UL, + /* 4348 */ 0x00000000UL, + /* 434C */ 0x00000000UL, + /* 4350 */ 0x00000000UL, + /* 4354 */ 0x00000000UL, + /* 4358 */ 0x00000000UL, + /* 435C */ 0x38000000UL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x00000000UL, + /* 4368 */ 0x58FF0000UL, + 0x01018010UL, 0x00000003UL, + 0x0103809CUL, 0x00000000UL, + /* 80A0 */ 0x0003B870UL, + /* 80A4 */ 0x0003B870UL, + 0x110180A8UL, 0x000001F6UL, + 0x310180A8UL, 0x01014201UL, + 0x110180ACUL, 0x000001F6UL, + 0x310180ACUL, 0x01014201UL, + 0x010280B0UL, 0x02000300UL, + /* 80B4 */ 0x02000300UL, + 0x02030098UL, 0x00000000UL, + /* 009C */ 0x04000C00UL, + /* 00A0 */ 0x0000044CUL, + 0x020200D8UL, 0xAA400005UL, + /* 00DC */ 0x00000188UL, + 0x120100ECUL, 0x00000FE0UL, + 0x320100ECUL, 0x5151200DUL, + 0x020100F0UL, 0x0000052BUL, + 0x02010100UL, 0x00000110UL, + 0x12010104UL, 0x00000000UL, + 0x32010104UL, 0x00000110UL, + 0x12010110UL, 0x000FFF00UL, + 0x32010110UL, 0x42000002UL, + 0x1201012CUL, 0x001FFC00UL, + 0x3201012CUL, 0x008000A9UL, + 0x02010140UL, 0x0000003FUL, + 0x02020168UL, 0x00060010UL, + /* 016C */ 0x00062000UL, + 0x02010174UL, 0x0C100169UL, + 0x12010178UL, 0x001C0000UL, + 0x32010178UL, 0xCFE00440UL, + 0x12010180UL, 0x00000779UL, + 0x32010180UL, 0x00000006UL, + 0x02020188UL, 0x00000090UL, + /* 018C */ 0x00000000UL, + 0x120101ACUL, 0x000001F8UL, + 0x320101ACUL, 0x00010204UL, + 0x020101B0UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t wmbus_mode_s_modemConfigBase[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_1, + 0x0002400CUL, 0x000A8001UL, + /* 4010 */ 0x000040FFUL, + 0x00024020UL, 0x00000000UL, + /* 4024 */ 0x00000000UL, + 0x00074030UL, 0x00000000UL, + /* 4034 */ 0x00000000UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000000UL, + /* 4040 */ 0x00000000UL, + /* 4044 */ 0x00004000UL, + /* 4048 */ 0x000007A4UL, + 0x00014050UL, 0x000008FFUL, + 0x0002405CUL, 0x00000000UL, + /* 4060 */ 0x00000000UL, + 0x000140A8UL, 0x00000007UL, + 0x000440BCUL, 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + 0x00044108UL, 0x00004C09UL, + /* 410C */ 0x00004C0FUL, + /* 4110 */ 0x00004D09UL, + /* 4114 */ 0x00004D0FUL, + 0x1001C020UL, 0x0007F800UL, + 0x3001C020UL, 0x002801FEUL, + 0x1001C024UL, 0x000000FFUL, + 0x3001C024UL, 0x00001300UL, + 0x0008C028UL, 0x03B380ECUL, + /* C02C */ 0x51407543UL, + /* C030 */ 0xF8000FA0UL, + /* C034 */ 0x00004030UL, + /* C038 */ 0x0007AAA8UL, + /* C03C */ 0x01090E35UL, + /* C040 */ 0x00000000UL, + /* C044 */ 0x00000000UL, + 0x0014C054UL, 0x00302187UL, + /* C058 */ 0xE654005AUL, + /* C05C */ 0x0000010EUL, + /* C060 */ 0x514D4432UL, + /* C064 */ 0x00000054UL, + /* C068 */ 0x0002C688UL, + /* C06C */ 0x00000520UL, + /* C070 */ 0x000010BAUL, + /* C074 */ 0x003F0000UL, + /* C078 */ 0x00EE008DUL, + /* C07C */ 0x03AC01F6UL, + /* C080 */ 0x079604F5UL, + /* C084 */ 0x0D9C09DEUL, + /* C088 */ 0x179311C3UL, + /* C08C */ 0x26F51DFEUL, + /* C090 */ 0x3FFF32BDUL, + /* C094 */ 0x1BF815FEUL, + /* C098 */ 0x2DB423DCUL, + /* C09C */ 0x3FFF39D0UL, + /* C0A0 */ 0x00003FFFUL, + 0x0005C0A8UL, 0x15724BBDUL, + /* C0AC */ 0x0518A311UL, + /* C0B0 */ 0x76543210UL, + /* C0B4 */ 0x00000A98UL, + /* C0B8 */ 0x00000000UL, + 0x0004C0CCUL, 0x000000EEUL, + /* C0D0 */ 0x00000000UL, + /* C0D4 */ 0x000A0001UL, + /* C0D8 */ 0x00280001UL, + 0x01010008UL, 0x000007A6UL, + 0x01010018UL, 0x00000000UL, + 0x01010020UL, 0x0000A6BCUL, + 0x01264040UL, 0x11D00000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000012UL, + /* 4050 */ 0x0081C011UL, + /* 4054 */ 0x20000000UL, + /* 4058 */ 0x000AD000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + /* 4068 */ 0x00C270BEUL, + /* 406C */ 0x00000041UL, + /* 4070 */ 0x00000030UL, + /* 4074 */ 0x00320011UL, + /* 4078 */ 0x00025A47UL, + /* 407C */ 0x0003FFFFUL, + /* 4080 */ 0x00001412UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x00080392UL, + /* 408C */ 0x62000000UL, + /* 4090 */ 0x00000000UL, + /* 4094 */ 0x00000000UL, + /* 4098 */ 0x00000000UL, + /* 409C */ 0x00000000UL, + /* 40A0 */ 0x00000000UL, + /* 40A4 */ 0x00000000UL, + /* 40A8 */ 0x00000000UL, + /* 40AC */ 0x00000000UL, + /* 40B0 */ 0x00000000UL, + /* 40B4 */ 0x00000000UL, + /* 40B8 */ 0x00000000UL, + /* 40BC */ 0x00000000UL, + /* 40C0 */ 0x00000000UL, + /* 40C4 */ 0x00000000UL, + /* 40C8 */ 0x00000000UL, + /* 40CC */ 0x00000000UL, + /* 40D0 */ 0x00000000UL, + /* 40D4 */ 0x00000000UL, + 0x110140E0UL, 0x000001F8UL, + 0x310140E0UL, 0x00000201UL, + 0x01024110UL, 0x00051E33UL, + /* 4114 */ 0x00000000UL, + 0x010E411CUL, 0x04000000UL, + /* 4120 */ 0x00000000UL, + /* 4124 */ 0x078304FFUL, + /* 4128 */ 0x3AC81388UL, + /* 412C */ 0x0C6606FFUL, + /* 4130 */ 0x078304FFUL, + /* 4134 */ 0x03FF1388UL, + /* 4138 */ 0xF00A20BCUL, + /* 413C */ 0x00508894UL, + /* 4140 */ 0x00A14284UL, + /* 4144 */ 0x123556B7UL, + /* 4148 */ 0x500000A1UL, + /* 414C */ 0x00003B80UL, + /* 4150 */ 0x00000000UL, + 0x01024158UL, 0x00000000UL, + /* 415C */ 0x0000FDFFUL, + 0x01014164UL, 0x0000010CUL, + 0x010B416CUL, 0x40000000UL, + /* 4170 */ 0x00000000UL, + /* 4174 */ 0x00000000UL, + /* 4178 */ 0x00000000UL, + /* 417C */ 0x00000000UL, + /* 4180 */ 0x00000000UL, + /* 4184 */ 0x00000101UL, + /* 4188 */ 0x00000000UL, + /* 418C */ 0x00000000UL, + /* 4190 */ 0x00000000UL, + /* 4194 */ 0x00000000UL, + 0x010241A4UL, 0x00000000UL, + /* 41A8 */ 0x00000000UL, + 0x010C41B0UL, 0x00000000UL, + /* 41B4 */ 0x00200000UL, + /* 41B8 */ 0x00000000UL, + /* 41BC */ 0x00000000UL, + /* 41C0 */ 0x003C0000UL, + /* 41C4 */ 0x0006AAAAUL, + /* 41C8 */ 0x00000000UL, + /* 41CC */ 0x00000000UL, + /* 41D0 */ 0xAAAAAAABUL, + /* 41D4 */ 0x000001D0UL, + /* 41D8 */ 0x00020000UL, + /* 41DC */ 0x00000000UL, + 0x011541E4UL, 0x1492F42DUL, + /* 41E8 */ 0x003858D3UL, + /* 41EC */ 0x007AFDBEUL, + /* 41F0 */ 0x0041732CUL, + /* 41F4 */ 0x0DD53E7FUL, + /* 41F8 */ 0x03283A26UL, + /* 41FC */ 0x302424E2UL, + /* 4200 */ 0x0C81901EUL, + /* 4204 */ 0x0006490CUL, + /* 4208 */ 0x006DDFA8UL, + /* 420C */ 0x00B10BC0UL, + /* 4210 */ 0x00A53D18UL, + /* 4214 */ 0x05020AE8UL, + /* 4218 */ 0x1DD71B27UL, + /* 421C */ 0x80000000UL, + /* 4220 */ 0x00000000UL, + /* 4224 */ 0x8000FFFFUL, + /* 4228 */ 0x00000000UL, + /* 422C */ 0x40001860UL, + /* 4230 */ 0x00000000UL, + /* 4234 */ 0x00000000UL, + 0x0101423CUL, 0x00000000UL, + 0x01034244UL, 0x00000014UL, + /* 4248 */ 0x00000000UL, + /* 424C */ 0x04000008UL, + 0x010F4330UL, 0x09C2422BUL, + /* 4334 */ 0x80E38121UL, + /* 4338 */ 0xF6C0C081UL, + /* 433C */ 0x00A40C06UL, + /* 4340 */ 0x00000000UL, + /* 4344 */ 0xD2600023UL, + /* 4348 */ 0x4000C350UL, + /* 434C */ 0x80000002UL, + /* 4350 */ 0x00000020UL, + /* 4354 */ 0x00000478UL, + /* 4358 */ 0xDA834504UL, + /* 435C */ 0x9518840FUL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x00210000UL, + /* 4368 */ 0x9AC85555UL, + 0x01018010UL, 0x00000003UL, + 0x01028038UL, 0x00102225UL, + /* 803C */ 0x00000003UL, + 0x0103809CUL, 0x00000000UL, + /* 80A0 */ 0x0003B870UL, + /* 80A4 */ 0x0003B870UL, + 0x110180A8UL, 0x000001F6UL, + 0x310180A8UL, 0x01014201UL, + 0x110180ACUL, 0x000001F6UL, + 0x310180ACUL, 0x01014201UL, + 0x010280B0UL, 0x02000300UL, + /* 80B4 */ 0x02000300UL, + 0x02030098UL, 0x00000000UL, + /* 009C */ 0x04000C00UL, + /* 00A0 */ 0x0000044CUL, + 0x020200D8UL, 0xAA400005UL, + /* 00DC */ 0x00000188UL, + 0x120100ECUL, 0x00000FE0UL, + 0x320100ECUL, 0x5151200DUL, + 0x020100F0UL, 0x0000052BUL, + 0x02010100UL, 0x00000110UL, + 0x12010104UL, 0x00000000UL, + 0x32010104UL, 0x00000110UL, + 0x12010110UL, 0x000FFF00UL, + 0x32010110UL, 0x42000002UL, + 0x1201012CUL, 0x001FFC00UL, + 0x3201012CUL, 0x008000A9UL, + 0x02010140UL, 0x0000003FUL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510063UL, + 0x02020168UL, 0x00060010UL, + /* 016C */ 0x00062000UL, + 0x02010174UL, 0x0C100169UL, + 0x12010178UL, 0x001C0000UL, + 0x32010178UL, 0xCFE00440UL, + 0x12010180UL, 0x00000779UL, + 0x32010180UL, 0x00000006UL, + 0x02020188UL, 0x00000090UL, + /* 018C */ 0x00000000UL, + 0x120101ACUL, 0x000001F8UL, + 0x320101ACUL, 0x00010204UL, + 0x020101B0UL, 0x00000000UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t m2o_mode_t_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_0, + 0x00044030UL, 0x00000300UL, + /* 4034 */ 0x00000020UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000007UL, + 0x00014050UL, 0x00800900UL, + 0x0001C03CUL, 0x0109040EUL, + 0x0005C054UL, 0x00302187UL, + /* C058 */ 0xE655005BUL, + /* C05C */ 0x00000111UL, + /* C060 */ 0x524D4432UL, + /* C064 */ 0x00000055UL, + 0x01144040UL, 0xF0F00000UL, + /* 4044 */ 0xC1F00000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000000UL, + /* 4050 */ 0x0081C009UL, + /* 4054 */ 0x20000000UL, + /* 4058 */ 0x00000000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + /* 4068 */ 0x000400C3UL, + /* 406C */ 0x00000041UL, + /* 4070 */ 0x00000030UL, + /* 4074 */ 0x00130012UL, + /* 4078 */ 0x000002F0UL, + /* 407C */ 0x00000000UL, + /* 4080 */ 0x00002410UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x003B0395UL, + /* 408C */ 0x60000000UL, + 0x0104413CUL, 0x00508778UL, + /* 4140 */ 0x001D4084UL, + /* 4144 */ 0x123556B7UL, + /* 4148 */ 0x5000001DUL, + 0x010141D0UL, 0x55555555UL, + 0x01084200UL, 0x1492F42DUL, + /* 4204 */ 0x003858D3UL, + /* 4208 */ 0x007AFDBEUL, + /* 420C */ 0x0041732CUL, + /* 4210 */ 0x0DD53E7FUL, + /* 4214 */ 0x03283A26UL, + /* 4218 */ 0x302424E2UL, + /* 421C */ 0x00000000UL, + 0x010F4330UL, 0x0146E46AUL, + /* 4334 */ 0x304A56EBUL, + /* 4338 */ 0x16C0C081UL, + /* 433C */ 0x00A00C07UL, + /* 4340 */ 0x40000000UL, + /* 4344 */ 0xD2240012UL, + /* 4348 */ 0x40004000UL, + /* 434C */ 0x80000002UL, + /* 4350 */ 0x00000020UL, + /* 4354 */ 0x00000478UL, + /* 4358 */ 0xDAA34004UL, + /* 435C */ 0x9520740EUL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x001E0000UL, + /* 4368 */ 0x9A9B5555UL, + 0x01028038UL, 0x001021DEUL, + /* 803C */ 0x00000003UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t o2m_mode_t_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_1, + 0x00044030UL, 0x00000000UL, + /* 4034 */ 0x00000000UL, + /* 4038 */ 0x00000000UL, + /* 403C */ 0x00000000UL, + 0x00014050UL, 0x000008FFUL, + 0x0001C03CUL, 0x01090E35UL, + 0x0005C054UL, 0x00302187UL, + /* C058 */ 0xE654005AUL, + /* C05C */ 0x0000010EUL, + /* C060 */ 0x514D4432UL, + /* C064 */ 0x00000054UL, + 0x01144040UL, 0x11D00000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000012UL, + /* 4050 */ 0x0081C011UL, + /* 4054 */ 0x20000000UL, + /* 4058 */ 0x000AD000UL, + /* 405C */ 0x03000000UL, + /* 4060 */ 0x20000000UL, + /* 4064 */ 0x00000000UL, + /* 4068 */ 0x00C270BEUL, + /* 406C */ 0x00000041UL, + /* 4070 */ 0x00000030UL, + /* 4074 */ 0x00130011UL, + /* 4078 */ 0x00025A47UL, + /* 407C */ 0x0003FFFFUL, + /* 4080 */ 0x00001412UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x00080392UL, + /* 408C */ 0x62000000UL, + 0x0104413CUL, 0x00508894UL, + /* 4140 */ 0x00A14284UL, + /* 4144 */ 0x123556B7UL, + /* 4148 */ 0x500000A1UL, + 0x010141D0UL, 0xAAAAAAABUL, + 0x01084200UL, 0x0C81901EUL, + /* 4204 */ 0x0006490CUL, + /* 4208 */ 0x006DDFA8UL, + /* 420C */ 0x00B10BC0UL, + /* 4210 */ 0x00A53D18UL, + /* 4214 */ 0x05020AE8UL, + /* 4218 */ 0x1DD71B27UL, + /* 421C */ 0x80000000UL, + 0x010F4330UL, 0x09C2422BUL, + /* 4334 */ 0x80E38121UL, + /* 4338 */ 0xF6C0C081UL, + /* 433C */ 0x00A40C06UL, + /* 4340 */ 0x00000000UL, + /* 4344 */ 0xD2600023UL, + /* 4348 */ 0x4000C350UL, + /* 434C */ 0x80000002UL, + /* 4350 */ 0x00000020UL, + /* 4354 */ 0x00000478UL, + /* 4358 */ 0xDA834504UL, + /* 435C */ 0x9518840FUL, + /* 4360 */ 0x00000000UL, + /* 4364 */ 0x00210000UL, + /* 4368 */ 0x9AC85555UL, + 0x01028038UL, 0x00102225UL, + /* 803C */ 0x00000003UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t m2o_mode_c_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_2, + 0x0007C054UL, 0x00302187UL, + /* C058 */ 0xE657005EUL, + /* C05C */ 0x0000011AUL, + /* C060 */ 0x55504734UL, + /* C064 */ 0x00000057UL, + /* C068 */ 0x0002C688UL, + /* C06C */ 0x000004A0UL, + 0x0001C0CCUL, 0x000000EEUL, + 0x01064040UL, 0x70100000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x00000000UL, + /* 4050 */ 0x0082C019UL, + /* 4054 */ 0x00000000UL, + 0x010D4068UL, 0x00FC2FFDUL, + /* 406C */ 0x00000C41UL, + /* 4070 */ 0x0000002AUL, + /* 4074 */ 0x00130012UL, + /* 4078 */ 0x02CCAAF0UL, + /* 407C */ 0x02F0AAF0UL, + /* 4080 */ 0x00000E4DUL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x00080393UL, + /* 408C */ 0x62040000UL, + /* 4090 */ 0x00000000UL, + /* 4094 */ 0x00000000UL, + /* 4098 */ 0x00000000UL, + 0x0101411CUL, 0x8CA49000UL, + 0x0104413CUL, 0x0050AE4BUL, + /* 4140 */ 0x40AA64E5UL, + /* 4144 */ 0x543D54CDUL, + /* 4148 */ 0x43F91EB0UL, + 0x010141D4UL, 0x806E01E6UL, + 0x01074200UL, 0x0C81901EUL, + /* 4204 */ 0x0006490CUL, + /* 4208 */ 0x006DDFA8UL, + /* 420C */ 0x00B10BC0UL, + /* 4210 */ 0x00A53D18UL, + /* 4214 */ 0x05020AE8UL, + /* 4218 */ 0x1DD71B27UL, + 0x0101424CUL, 0x04060008UL, + 0x01028038UL, 0x001020AEUL, + /* 803C */ 0x00000003UL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510063UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const uint32_t o2m_mode_c_modemConfig[] = { + 0x03014FFCUL, (uint32_t) &phyInfo_3, + 0x0007C054UL, 0x00302187UL, + /* C058 */ 0xE6880092UL, + /* C05C */ 0x000001B6UL, + /* C060 */ 0x837C6E50UL, + /* C064 */ 0x00000088UL, + /* C068 */ 0x0002C688UL, + /* C06C */ 0x000004C0UL, + 0x0001C0CCUL, 0x000001FEUL, + 0x01064040UL, 0x30B00000UL, + /* 4044 */ 0x00000000UL, + /* 4048 */ 0x00000010UL, + /* 404C */ 0x04000000UL, + /* 4050 */ 0x0082C019UL, + /* 4054 */ 0x20005000UL, + 0x010D4068UL, 0x00FE60BDUL, + /* 406C */ 0x00000C41UL, + /* 4070 */ 0x00000070UL, + /* 4074 */ 0x00130012UL, + /* 4078 */ 0x02CCAAF0UL, + /* 407C */ 0x02F0AAF0UL, + /* 4080 */ 0x00000E35UL, + /* 4084 */ 0x00000000UL, + /* 4088 */ 0x002B037FUL, + /* 408C */ 0x62040000UL, + /* 4090 */ 0x00000000UL, + /* 4094 */ 0x22140A04UL, + /* 4098 */ 0x4F4A4132UL, + 0x0101411CUL, 0x8CF3D000UL, + 0x0104413CUL, 0x00505414UL, + /* 4140 */ 0x409A48B7UL, + /* 4144 */ 0x543D54CDUL, + /* 4148 */ 0x43F9FF9BUL, + 0x010141D4UL, 0x805780E6UL, + 0x01074200UL, 0x0A00ABFFUL, + /* 4204 */ 0x000FF15CUL, + /* 4208 */ 0x000241D3UL, + /* 420C */ 0x00B1ED95UL, + /* 4210 */ 0x0FD87B19UL, + /* 4214 */ 0x04B90812UL, + /* 4218 */ 0x1F6D1BEAUL, + 0x0101424CUL, 0x14060008UL, + 0x01028038UL, 0x00101505UL, + /* 803C */ 0x00000003UL, + 0x12010150UL, 0x0000C000UL, + 0x32010150UL, 0x00510062UL, + 0x03014FF8UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + +const RAIL_ChannelConfigEntry_t wmbus_mode_t_channels[] = { + { + .phyConfigDeltaAdd = m2o_mode_t_modemConfig, + .baseFrequency = 868950000, + .channelSpacing = 0, + .physicalChannelOffset = 0, + .channelNumberStart = 0, + .channelNumberEnd = 0, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_0, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, + { + .phyConfigDeltaAdd = o2m_mode_t_modemConfig, + .baseFrequency = 868300000, + .channelSpacing = 0, + .physicalChannelOffset = 1, + .channelNumberStart = 1, + .channelNumberEnd = 1, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_0, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, +}; + +const RAIL_ChannelConfigEntry_t wmbus_mode_c_channels[] = { + { + .phyConfigDeltaAdd = m2o_mode_c_modemConfig, + .baseFrequency = 868950000, + .channelSpacing = 0, + .physicalChannelOffset = 0, + .channelNumberStart = 0, + .channelNumberEnd = 0, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, + { + .phyConfigDeltaAdd = o2m_mode_c_modemConfig, + .baseFrequency = 868950000, + .channelSpacing = 0, + .physicalChannelOffset = 1, + .channelNumberStart = 1, + .channelNumberEnd = 1, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, +}; + +const RAIL_ChannelConfigEntry_t wmbus_mode_s_channels[] = { + { + .phyConfigDeltaAdd = NULL, + .baseFrequency = 868300000, + .channelSpacing = 0, + .physicalChannelOffset = 0, + .channelNumberStart = 0, + .channelNumberEnd = 0, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_2, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, + { + .phyConfigDeltaAdd = NULL, + .baseFrequency = 868300000, + .channelSpacing = 0, + .physicalChannelOffset = 1, + .channelNumberStart = 1, + .channelNumberEnd = 1, + .maxPower = RAIL_TX_POWER_MAX, + .attr = &channelConfigEntryAttr_2, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + .alternatePhy = NULL, + }, +}; + +const RAIL_ChannelConfig_t wmbus_mode_t_channelConfig = { + .phyConfigBase = wmbus_mode_t_modemConfigBase, + .phyConfigDeltaSubtract = NULL, + .configs = wmbus_mode_t_channels, + .length = 2U, + .signature = 0UL, + .xtalFrequencyHz = 39000000UL, +}; + +const RAIL_ChannelConfig_t wmbus_mode_c_channelConfig = { + .phyConfigBase = wmbus_mode_c_modemConfigBase, + .phyConfigDeltaSubtract = NULL, + .configs = wmbus_mode_c_channels, + .length = 2U, + .signature = 0UL, + .xtalFrequencyHz = 39000000UL, +}; + +const RAIL_ChannelConfig_t wmbus_mode_s_channelConfig = { + .phyConfigBase = wmbus_mode_s_modemConfigBase, + .phyConfigDeltaSubtract = NULL, + .configs = wmbus_mode_s_channels, + .length = 2U, + .signature = 0UL, + .xtalFrequencyHz = 39000000UL, +}; + +const RAIL_ChannelConfig_t *channelConfigs[] = { + &wmbus_mode_t_channelConfig, + &wmbus_mode_c_channelConfig, + &wmbus_mode_s_channelConfig, + NULL +}; + +uint32_t wmbusAccelerationBuffer[471]; diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/rail_config.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/rail_config.h new file mode 100644 index 0000000000..23a343ae04 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/rail_config.h @@ -0,0 +1,50 @@ +/***************************************************************************//** + * @brief RAIL Configuration + * @details + * WARNING: Auto-Generated Radio Config Header - DO NOT EDIT + * Radio Configurator Version: 2402.6.1 + * RAIL Adapter Version: 2.4.33 + * RAIL Compatibility: 2.x + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_CONFIG_H__ +#define __RAIL_CONFIG_H__ + +#include +#include "rail_types.h" + +#define WMBUS_ACCELERATION_BUFFER wmbusAccelerationBuffer +extern uint32_t wmbusAccelerationBuffer[]; + +#define RADIO_CONFIG_XTAL_FREQUENCY 39000000UL + +#define RAIL0_M2O_MODE_T_PHY_WMBUS_MODET_M2O_100K_FRAMEA +#define RAIL0_M2O_MODE_T_PROFILE_MBUS +extern const RAIL_ChannelConfig_t *channelConfigs[]; + +#endif // __RAIL_CONFIG_H__ diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_component_catalog.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_component_catalog.h new file mode 100644 index 0000000000..31242e89cc --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_component_catalog.h @@ -0,0 +1,51 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +//#define SL_CATALOG_APP_ASSERT_PRESENT +//#define SL_CATALOG_APP_LOG_PRESENT +//#define SL_CATALOG_CLI_PRESENT +//#define SL_CATALOG_CLOCK_MANAGER_PRESENT +//#define SL_CATALOG_DEVICE_INIT_PRESENT +//#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT +//#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT +//#define SL_CATALOG_EMLIB_CORE_PRESENT +//#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +//#define SL_CATALOG_HFXO_MANAGER_PRESENT +//#define SL_CATALOG_INTERRUPT_MANAGER_PRESENT +//#define SL_CATALOG_IOSTREAM_PRESENT +//#define SL_CATALOG_IOSTREAM_EUSART_PRESENT +//#define SL_CATALOG_RETARGET_STDIO_PRESENT +//#define SL_CATALOG_IOSTREAM_UART_COMMON_PRESENT +//#define SL_CATALOG_MEMORY_MANAGER_PRESENT +//#define SL_CATALOG_MPU_PRESENT +//#define SL_CATALOG_POWER_MANAGER_PRESENT +//#define SL_CATALOG_PRINTF_PRESENT +//#define SL_CATALOG_RADIO_CONFIG_WMBUS_METER_PRESENT +//#define SL_CATALOG_RAIL_LIB_PRESENT +//#define SL_CATALOG_RAIL_UTIL_INIT_PRESENT +//#define SL_CATALOG_RAIL_UTIL_PTI_PRESENT +//#define SL_CATALOG_SE_MANAGER_PRESENT +//#define SL_CATALOG_SEGMENT_LCD_DRIVER_PRESENT +//#define SL_CATALOG_BTN0_PRESENT +//#define SL_CATALOG_SIMPLE_BUTTON_PRESENT +//#define SL_CATALOG_SIMPLE_BUTTON_BTN0_PRESENT +//#define SL_CATALOG_BTN1_PRESENT +//#define SL_CATALOG_SIMPLE_BUTTON_BTN1_PRESENT +//#define SL_CATALOG_LED0_PRESENT +//#define SL_CATALOG_SIMPLE_LED_PRESENT +//#define SL_CATALOG_SIMPLE_LED_LED0_PRESENT +//#define SL_CATALOG_SIMPLE_RAIL_ASSISTANCE_PRESENT +//#define SL_CATALOG_FLEX_RAIL_CONFIG_PRESENT +//#define SL_CATALOG_FLEX_RAIL_SLEEP_PRESENT +//#define SL_CATALOG_SL_SIMPLE_RAIL_STUB_PRESENT +//#define SL_CATALOG_WMBUS_PACKET_ASSEMBLER_PRESENT +//#define SL_CATALOG_SL_WMBUS_SENSOR_CLI_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_CORE_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_PULSE_COUNTER_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_THERMO_METER_PRESENT +//#define SL_CATALOG_WMBUS_SENSOR_VIRTUAL_WATER_METER_PRESENT +//#define SL_CATALOG_WMBUS_SUPPORT_PRESENT +//#define SL_CATALOG_SLEEPTIMER_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_callbacks.c b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_callbacks.c new file mode 100644 index 0000000000..b09033d462 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_callbacks.c @@ -0,0 +1,118 @@ + /***************************************************************************//** + * @file sl_rail_util_callbacks.c + * @brief RAIL Callbacks + * WARNING: Auto-Generated Radio Callbacks - DO NOT EDIT + * Any application code placed within this file will be discarged + * upon project regeneration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "rail.h" +#include "sl_component_catalog.h" +#ifdef SL_CATALOG_APP_ASSERT_PRESENT +#include "app_assert.h" +#define APP_ASSERT(expr, ...) app_assert(expr,__VA_ARGS__) +#else + #define APP_ASSERT(expr, string ,rail_handle, error_code) \ + do { \ + if (!(expr)) { \ + while (1) ; \ + } \ + } while (0) +#endif +#include "sl_rail_util_callbacks_config.h" +#include "pa_conversions_efr32.h" + +// Provide weak function called by callback RAILCb_AssertFailed. +__WEAK +void sl_rail_util_on_assert_failed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code) +{ + (void) rail_handle; + (void) error_code; + APP_ASSERT(false, + "rail_handle: 0x%X, error_code: %d", + rail_handle, + error_code); +} + +#if SL_RAIL_UTIL_CALLBACKS_ASSERT_FAILED_OVERRIDE +// Note: RAILCb_AssertFailed is called directly by the RAIL library when +// needed, so maintain this exact function signature. +void RAILCb_AssertFailed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code) +{ + sl_rail_util_on_assert_failed(rail_handle, error_code); +} +#endif + +// Provide weak function called by callback sli_rail_util_on_rf_ready. +__WEAK +void sl_rail_util_on_rf_ready(RAIL_Handle_t rail_handle) +{ + (void) rail_handle; +} + +// Internal-only callback set up through call to RAIL_Init(). +void sli_rail_util_on_rf_ready(RAIL_Handle_t rail_handle) +{ + sl_rail_util_on_rf_ready(rail_handle); +} + +// Provide weak function called by callback +// sli_rail_util_on_channel_config_change. +__WEAK +void sl_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) +{ + (void) rail_handle; + (void) entry; +} + +// Internal-only callback set up through call to RAIL_ConfigChannels(). +void sli_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) +{ + sl_rail_util_pa_on_channel_config_change(rail_handle, entry); + sl_rail_util_on_channel_config_change(rail_handle, entry); +} + +// Provide weak function called by callback sli_rail_util_on_event. +__WEAK +void sl_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events) +{ + (void) rail_handle; + (void) events; +} + +// Internal-only callback set up through call to RAIL_Init(). +void sli_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events) +{ + sl_rail_util_on_event(rail_handle, events); +} diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_init.c b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_init.c new file mode 100644 index 0000000000..04d44e97d5 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_init.c @@ -0,0 +1,255 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "rail.h" +#include "rail_ble.h" // for RAIL_BLE_State_t +#include "sli_rail_util_callbacks.h" // for internal-only callback signatures +#include "sl_rail_util_init.h" +#include "sl_rail_util_protocol.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_TIMING_TEST_PRESENT) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT +// Needed for measuring RAIL_Init() time as a part of +// detailed timing characterization. +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_timer.h" +#else +#include "sl_hal_timer.h" +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager.h" +#else +#include "em_cmu.h" +#endif //defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#endif //defined(SL_CATALOG_TIMING_TEST_PRESENT) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT + +#ifdef SL_CATALOG_APP_ASSERT_PRESENT +#include "app_assert.h" +#define APP_ASSERT(expr, ...) app_assert(expr,__VA_ARGS__) +#else +#define APP_ASSERT(expr, ...) \ + do { \ + if (!(expr)) { \ + while (1) ; \ + } \ + } while (0) +#endif + +#if 0U \ + || SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE \ + || 0U + #include "rail_config.h" +#endif + +// Instance: inst0 +static RAIL_Handle_t sl_rail_handle_inst0 = RAIL_EFR32_HANDLE; + +#if defined(SL_CATALOG_TIMING_TEST_PRESENT) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT +uint32_t sli_timing_start_tick = 0U; +uint32_t sli_timing_end_tick = 0U; +static TIMER_TypeDef *timer = TIMER0; +static void setupTimingTestTimer(void) +{ +// Clock TIMER0 using the HF clock +#ifndef SL_CATALOG_CLOCK_MANAGER_PRESENT + CMU_CLOCK_SELECT_SET(TIMER0, HFXO); + CMU_ClockEnable(cmuClock_TIMER0, true); + // Use default configuration, prescaled by 8. + TIMER_Init_TypeDef timerCfg = TIMER_INIT_DEFAULT; + timerCfg.prescale = timerPrescale8; + // Enable TIMER0 to upcount + TIMER_Init(timer, &timerCfg); +#else + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_TIMER0); + sl_hal_timer_config_t timerCfg = SL_HAL_TIMER_CONFIG_DEFAULT; + // Use default configuration, prescaled by 8. + timerCfg.prescaler = TIMER_CFG_PRESC_DIV8; + // Enable TIMER0 to upcount + sl_hal_timer_init(timer, &timerCfg); +#endif //SL_CATALOG_CLOCK_MANAGER_PRESENT +} +#endif + +static void sl_rail_util_init_inst0(void) +{ +#if SL_RAIL_UTIL_INIT_INST0_ENABLE + RAIL_Status_t status; + RAIL_Config_t sl_rail_config = { + .eventsCallback = &sli_rail_util_on_event, + // Other fields are ignored nowadays + }; + (void) status; // Suppress compiler warning if status ends up unused +#ifdef SL_CATALOG_TIMING_TEST_PRESENT + setupTimingTestTimer(); + sli_timing_start_tick = timer->CNT; +#endif // SL_CATALOG_TIMING_TEST_PRESENT + sl_rail_handle_inst0 = RAIL_Init(&sl_rail_config, +#if SL_RAIL_UTIL_INIT_INIT_COMPLETE_CALLBACK_INST0_ENABLE + &sli_rail_util_on_rf_ready +#else + NULL +#endif // SL_RAIL_UTIL_INIT_INIT_COMPLETE_CALLBACK_INST0_ENABLE + ); +#ifdef SL_CATALOG_TIMING_TEST_PRESENT + sli_timing_end_tick = timer->CNT; +#endif // SL_CATALOG_TIMING_TEST_PRESENT + APP_ASSERT((NULL != sl_rail_handle_inst0), + "RAIL_Init failed, return value: NULL"); + +#if SL_RAIL_UTIL_INIT_DATA_FORMATS_INST0_ENABLE + RAIL_DataConfig_t data_config = { + .txSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_SOURCE, + .rxSource = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_SOURCE, + .txMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_MODE, + .rxMethod = SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_MODE, + }; + status = RAIL_ConfigData(sl_rail_handle_inst0, &data_config); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_ConfigData failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_DATA_FORMATS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_PROTOCOLS_INST0_ENABLE + const RAIL_ChannelConfig_t *channel_config = NULL; + if (SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT + == SL_RAIL_UTIL_PROTOCOL_PROPRIETARY) { +#if SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE + channel_config = channelConfigs[SL_RAIL_UTIL_INIT_PROTOCOL_PROPRIETARY_INST0_INDEX]; +#else // !SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE + APP_ASSERT(false, + "SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE must be true when (SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT == SL_RAIL_UTIL_PROTOCOL_PROPRIETARY)"); +#endif // SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE + } + (void) RAIL_ConfigChannels(sl_rail_handle_inst0, + channel_config, + &sli_rail_util_on_channel_config_change); + status = sl_rail_util_protocol_config(sl_rail_handle_inst0, + SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "sl_rail_util_protocol_config failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_PROTOCOLS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_CALIBRATIONS_INST0_ENABLE + status = RAIL_ConfigCal(sl_rail_handle_inst0, + 0U + | (SL_RAIL_UTIL_INIT_CALIBRATION_TEMPERATURE_NOTIFY_INST0_ENABLE + ? RAIL_CAL_TEMP : 0U) + | (SL_RAIL_UTIL_INIT_CALIBRATION_ONETIME_NOTIFY_INST0_ENABLE + ? RAIL_CAL_ONETIME : 0U)); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_ConfigCal failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_CALIBRATIONS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_EVENTS_INST0_ENABLE + status = RAIL_ConfigEvents(sl_rail_handle_inst0, + RAIL_EVENTS_ALL, + SL_RAIL_UTIL_INIT_EVENT_INST0_MASK); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_ConfigEvents failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_EVENTS_INST0_ENABLE + +#if SL_RAIL_UTIL_INIT_TRANSITIONS_INST0_ENABLE + RAIL_StateTransitions_t tx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_ERROR + }; + RAIL_StateTransitions_t rx_transitions = { + .success = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_SUCCESS, + .error = SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_ERROR + }; + status = RAIL_SetTxTransitions(sl_rail_handle_inst0, + &tx_transitions); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_SetTxTransitions failed, return value: %d", + status); + status = RAIL_SetRxTransitions(sl_rail_handle_inst0, + &rx_transitions); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_SetRxTransitions failed, return value: %d", + status); +#endif // SL_RAIL_UTIL_INIT_TRANSITIONS_INST0_ENABLE +#else // !SL_RAIL_UTIL_INIT_INST0_ENABLE + // Eliminate compiler warnings. + (void) sl_rail_handle_inst0; +#endif // SL_RAIL_UTIL_INIT_INST0_ENABLE +} + +RAIL_Handle_t sl_rail_util_get_handle(sl_rail_util_handle_type_t handle) +{ + RAIL_Handle_t *sl_rail_handle_array[] = { + &sl_rail_handle_inst0, + }; + return *sl_rail_handle_array[handle]; +} + +#define INIT_INSTANCES (0 + 1) + +#if (INIT_INSTANCES > 1) && !SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT + #error "sl_rail_util_init.c: If you are going to use more than one rail_util_init instance, you must use the Multiprotocol RAIL library." +#elif (INIT_INSTANCES > 4) + static uint64_t extraStateBuffers[INIT_INSTANCES - 4][RAIL_STATE_BUFFER_BYTES / sizeof(uint64_t)]; + static RAIL_StateBufferEntry_t extraProtos[INIT_INSTANCES - 4]; +#else + // RAIL provides enough built-in state buffers for all the instances +#endif + +void sl_rail_util_init(void) +{ +#if (INIT_INSTANCES > 2) + RAIL_Status_t status; + status = RAIL_AddStateBuffer3(RAIL_EFR32_HANDLE); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_AddStateBuffer3 failed, return value: %d", + status); +#if (INIT_INSTANCES > 3) + status = RAIL_AddStateBuffer4(RAIL_EFR32_HANDLE); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_AddStateBuffer4 failed, return value: %d", + status); +#endif +#if (INIT_INSTANCES > 4) + for (int i = 0; i < (INIT_INSTANCES - 4); i++) { + extraProtos[i].bufferBytes = sizeof(extraStateBuffers[0]); + extraProtos[i].buffer = extraStateBuffers[i]; + status = RAIL_AddStateBuffer(RAIL_EFR32_HANDLE, &extraProtos[i]); + APP_ASSERT((RAIL_STATUS_NO_ERROR == status), + "RAIL_AddStateBuffer(%d) failed, return value: %d", + (INIT_INSTANCES + i), status); + } +#endif +#endif + sl_rail_util_init_inst0(); +} diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_init.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_init.h new file mode 100644 index 0000000000..61d99db352 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/autogen/sl_rail_util_init.h @@ -0,0 +1,222 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_INIT_H +#define SL_RAIL_UTIL_INIT_H + +#include "rail.h" +#include "sl_rail_util_init_inst0_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum sl_rail_util_handle_type{ + SL_RAIL_UTIL_HANDLE_INST0, +} sl_rail_util_handle_type_t; + +/** + * Initialize the RAIL Init Utility. + * + * @note: This function should be called during application initialization. + */ +void sl_rail_util_init(void); + +/** + * Get the RAIL handle created during initialization. + * @param[in] handle The enum name of the desired RAIL handle. + * + * @return A valid RAIL handle. If the RAIL handle hasn't been set up, the + * invalid value of \ref RAIL_EFR32_HANDLE will be returned. + */ +RAIL_Handle_t sl_rail_util_get_handle(sl_rail_util_handle_type_t handle); + +/** + * A callback available to the application, called on RAIL asserts. + * + * @param[in] rail_handle The RAIL handle associated with the assert. + * @param[in] error_code The assertion error code. + */ +void sl_rail_util_on_assert_failed(RAIL_Handle_t rail_handle, + RAIL_AssertErrorCodes_t error_code); + +/** + * A callback available to the application, called on RAIL init completion. + * + * @param[in] rail_handle The RAIL handle associated with the RAIL init + * completion notification. + */ +void sl_rail_util_on_rf_ready(RAIL_Handle_t rail_handle); + +/** + * A callback available to the application, called on a channel configuration + * change. + * + * @param[in] rail_handle The RAIL handle associated with the channel config + * change notification. + * @param[in] entry The channel configuration being changed to. + */ +void sl_rail_util_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry); + +/** + * A callback available to the application, called on registered RAIL events. + * + * @param[in] rail_handle The RAIL handle associated with the RAIL event + * notification. + * @param[in] events The RAIL events having occurred. + */ +void sl_rail_util_on_event(RAIL_Handle_t rail_handle, + RAIL_Events_t events); + +/** + * An event mask, available to the application, specifying the radio events + * setup within the init code. + * + * @note: Because the value of this define is evaluated based on values in the + * \ref RAIL_Events_t enum, this define will only have a valid value during + * run-time. + */ +#define SL_RAIL_UTIL_INIT_EVENT_INST0_MASK (RAIL_EVENTS_NONE \ + | (SL_RAIL_UTIL_INIT_EVENT_RSSI_AVERAGE_DONE_INST0_ENABLE \ + ? RAIL_EVENT_RSSI_AVERAGE_DONE : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_ACK_TIMEOUT_INST0_ENABLE \ + ? RAIL_EVENT_RX_ACK_TIMEOUT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_ALMOST_FULL_INST0_ENABLE \ + ? RAIL_EVENT_RX_FIFO_ALMOST_FULL : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_RECEIVED_INST0_ENABLE \ + ? RAIL_EVENT_RX_PACKET_RECEIVED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_LOST_INST0_ENABLE \ + ? RAIL_EVENT_RX_PREAMBLE_LOST : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_PREAMBLE_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SYNC1_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_SYNC1_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SYNC2_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_SYNC2_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FRAME_ERROR_INST0_ENABLE \ + ? RAIL_EVENT_RX_FRAME_ERROR : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_FULL_INST0_ENABLE \ + ? RAIL_EVENT_RX_FIFO_FULL : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_OVERFLOW_INST0_ENABLE \ + ? RAIL_EVENT_RX_FIFO_OVERFLOW : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_ADDRESS_FILTERED_INST0_ENABLE \ + ? RAIL_EVENT_RX_ADDRESS_FILTERED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TIMEOUT_INST0_ENABLE \ + ? RAIL_EVENT_RX_TIMEOUT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TX_SCHEDULED_RX_TX_STARTED_INST0_ENABLE \ + ? RAIL_EVENT_SCHEDULED_RX_STARTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_END_INST0_ENABLE \ + ? RAIL_EVENT_RX_SCHEDULED_RX_END : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_MISSED_INST0_ENABLE \ + ? RAIL_EVENT_RX_SCHEDULED_RX_MISSED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_ABORTED_INST0_ENABLE \ + ? RAIL_EVENT_RX_PACKET_ABORTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_FILTER_PASSED_INST0_ENABLE \ + ? RAIL_EVENT_RX_FILTER_PASSED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_LOST_INST0_ENABLE \ + ? RAIL_EVENT_RX_TIMING_LOST : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_DETECT_INST0_ENABLE \ + ? RAIL_EVENT_RX_TIMING_DETECT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_CHANNEL_HOPPING_COMPLETE_INST0_ENABLE \ + ? RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_RX_DUTY_CYCLE_RX_END_INST0_ENABLE \ + ? RAIL_EVENT_RX_DUTY_CYCLE_RX_END : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_IEEE802154_DATA_REQUEST_COMMAND_INST0_ENABLE \ + ? RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_ZWAVE_BEAM_INST0_ENABLE \ + ? RAIL_EVENT_ZWAVE_BEAM : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_INST0_ENABLE \ + ? RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_FIFO_ALMOST_EMPTY_INST0_ENABLE \ + ? RAIL_EVENT_TX_FIFO_ALMOST_EMPTY : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_PACKET_SENT_INST0_ENABLE \ + ? RAIL_EVENT_TX_PACKET_SENT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_PACKET_SENT_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_PACKET_SENT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_ABORTED_INST0_ENABLE \ + ? RAIL_EVENT_TX_ABORTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_ABORTED_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_ABORTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_INST0_ENABLE \ + ? RAIL_EVENT_TX_BLOCKED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_BLOCKED_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_BLOCKED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_UNDERFLOW_INST0_ENABLE \ + ? RAIL_EVENT_TX_UNDERFLOW : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TXACK_UNDERFLOW_INST0_ENABLE \ + ? RAIL_EVENT_TXACK_UNDERFLOW : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_CLEAR_INST0_ENABLE \ + ? RAIL_EVENT_TX_CHANNEL_CLEAR : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_BUSY_INST0_ENABLE \ + ? RAIL_EVENT_TX_CHANNEL_BUSY : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_CCA_RETRY_INST0_ENABLE \ + ? RAIL_EVENT_TX_CCA_RETRY : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_START_CCA_INST0_ENABLE \ + ? RAIL_EVENT_TX_START_CCA : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_STARTED_INST0_ENABLE \ + ? RAIL_EVENT_TX_STARTED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_SCHEDULED_TX_MISSED_INST0_ENABLE \ + ? RAIL_EVENT_TX_SCHEDULED_TX_MISSED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_CONFIG_UNSCHEDULED_INST0_ENABLE \ + ? RAIL_EVENT_CONFIG_UNSCHEDULED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_CONFIG_SCHEDULED_INST0_ENABLE \ + ? RAIL_EVENT_CONFIG_SCHEDULED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_SCHEDULER_STATUS_INST0_ENABLE \ + ? RAIL_EVENT_SCHEDULER_STATUS : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_CAL_NEEDED_INST0_ENABLE \ + ? RAIL_EVENT_CAL_NEEDED : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_DETECT_RSSI_THRESHOLD_INST0_ENABLE \ + ? RAIL_EVENT_DETECT_RSSI_THRESHOLD : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_THERMISTOR_DONE_INST0_ENABLE \ + ? RAIL_EVENT_THERMISTOR_DONE : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_TOO_HOT_INST0_ENABLE \ + ? RAIL_EVENT_TX_BLOCKED_TOO_HOT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_TOO_HOT_INST0_ENABLE \ + ? RAIL_EVENT_TEMPERATURE_TOO_HOT : RAIL_EVENTS_NONE) \ + | (SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_COOL_DOWN_INST0_ENABLE \ + ? RAIL_EVENT_TEMPERATURE_COOL_DOWN : RAIL_EVENTS_NONE)) + +/** + * An inverted event mask, available to the application, specifying the radio + * events setup within the init code. + * + * @note: Because the value of this define is evaluated based on values in the + * \ref RAIL_Events_t enum, this define will only have a valid value during + * run-time. + */ +#define SL_RAIL_UTIL_INIT_EVENT_INST0_INVERSE_MASK \ + (~SL_RAIL_UTIL_INIT_EVENT_INST0_MASK) + +#ifdef __cplusplus +} +#endif + +#endif // SL_RAIL_UTIL_INIT_H diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/rail/profile_wmbus.restriction b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/rail/profile_wmbus.restriction new file mode 100644 index 0000000000..8700aedf2c --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/rail/profile_wmbus.restriction @@ -0,0 +1,10 @@ +[ + { + "name": "selectLimit", + "arguments": { + "id": "ProfilSelector", + "enabled": ["Mbus"], + "selected": "Mbus" + } + } +] diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/rail/radio_settings.radioconf b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/rail/radio_settings.radioconf new file mode 100644 index 0000000000..5ac528ec53 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/rail/radio_settings.radioconf @@ -0,0 +1,112 @@ + + + + + + + 0 + 0 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeT_M2O_100k_frameA"} + 0 + + + + + 1 + 1 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeT_M2O_100k_frameA"} + 868300000 + 0 + + + mbus_frame_format + 1 + + + mbus_mode + 8 + + + mbus_symbol_encoding + 1 + + + + + {"selectedPhy":"PHY_wMbus_ModeT_M2O_100k_frameA"} + + + + + + 0 + 0 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeC_M2O_100k_frameA"} + 0 + + + + + 1 + 1 + 1 + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeC_M2O_100k_frameA"} + 0 + + + mbus_mode + 1 + + + mbus_postamble_length + 0 + + + + + {"selectedPhy":"PHY_wMbus_ModeC_M2O_100k_frameA"} + + + + + + 0 + 0 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeS_32p768k_frameA"} + 0 + + + preamble_length + 100 + + + + + 1 + 1 + SAME_AS_FIRST_CHANNEL + RAIL_TX_POWER_MAX + {"selectedPhy":"PHY_wMbus_ModeS_32p768k_frameA"} + 0 + + + preamble_length + 100 + + + + + {"selectedPhy":"PHY_wMbus_ModeS_32p768k_frameA"} + + + + \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_init_inst0_config.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_init_inst0_config.h new file mode 100644 index 0000000000..efb8574312 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_init_inst0_config.h @@ -0,0 +1,342 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_INIT_INST0_CONFIG_H +#define SL_RAIL_UTIL_INIT_INST0_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// RAIL Init Configuration +// Initialize RAIL +// Default: 1 +#define SL_RAIL_UTIL_INIT_INST0_ENABLE 1 + +// Project Configuration +// Enable Radio Configurator Support (include rail_config.c/h generated by Radio Config) +// Default: 0 +#define SL_RAIL_UTIL_INIT_RADIO_CONFIG_SUPPORT_INST0_ENABLE 1 +// Enable RAIL Init Complete Callback +// Default: 0 +#define SL_RAIL_UTIL_INIT_INIT_COMPLETE_CALLBACK_INST0_ENABLE 1 +// + +// Protocol Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_PROTOCOLS_INST0_ENABLE 1 +// Radio Configuration +// Default Radio Configuration +// Proprietary (use rail_config.c/h) +// IEEE 802.15.4 GB868 915MHz +// IEEE 802.15.4 GB868 863MHz +// Z-Wave Australia +// Z-Wave China +// Z-Wave Europe +// Z-Wave Hong Kong +// Z-Wave India +// Z-Wave Israel +// Z-Wave Japan +// Z-Wave Korea +// Z-Wave Malaysia +// Z-Wave Russia +// Z-Wave United States +// Z-Wave United States, Long Range 1 +// Z-Wave United States, Long Range 2 +// Z-Wave United States, Long Range End Device +// Z-Wave European Union, Long Range 1 +// Z-Wave European Union, Long Range 2 +// Z-Wave European Union, Long Range End Device +// Default: SL_RAIL_UTIL_PROTOCOL_ZWAVE_EU +#define SL_RAIL_UTIL_INIT_PROTOCOL_INST0_DEFAULT SL_RAIL_UTIL_PROTOCOL_PROPRIETARY +// Proprietary Radio Config Index (if Proprietary radio config selected, use index X of channelConfigs[X]) +// <0-255:1> +// Default: 0 +#define SL_RAIL_UTIL_INIT_PROTOCOL_PROPRIETARY_INST0_INDEX 0 +// +// + +// Calibration Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_CALIBRATIONS_INST0_ENABLE 1 +// Calibration Notifications +// Enable Temperature Calibration Notifications (RAIL_EVENT_CAL_NEEDED radio event issued when temperature calibrations needed, for example VCO calibration) +// Default: 0 +#define SL_RAIL_UTIL_INIT_CALIBRATION_TEMPERATURE_NOTIFY_INST0_ENABLE 1 +// Enable One-time Calibration Notifications (RAIL_EVENT_CAL_NEEDED radio event issued when one-time calibrations needed, for example IR calibration) +// Default: 0 +#define SL_RAIL_UTIL_INIT_CALIBRATION_ONETIME_NOTIFY_INST0_ENABLE 1 +// +// + +// Auto Transition Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_TRANSITIONS_INST0_ENABLE 1 +// TX Transitions +// Transition on TX Success +// RX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_SUCCESS RAIL_RF_STATE_IDLE +// Transition on TX Error +// RX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_TX_ERROR RAIL_RF_STATE_IDLE +// +// RX Transitions +// Transition on RX Success +// RX +// TX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_SUCCESS RAIL_RF_STATE_IDLE +// Transition on RX Error +// RX +// Idle +// Default: RAIL_RF_STATE_IDLE +#define SL_RAIL_UTIL_INIT_TRANSITION_INST0_RX_ERROR RAIL_RF_STATE_IDLE +// +// + +// Data Format Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_DATA_FORMATS_INST0_ENABLE 1 +// TX Data +// Source of TX Data +// Use frame hardware to packetize data +// Default: TX_PACKET_DATA +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_SOURCE TX_PACKET_DATA +// Method of Providing TX Data +// Packet Mode +// FIFO Mode +// Default: PACKET_MODE +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_TX_MODE PACKET_MODE +// +// RX Data +// Source of RX Data +// Use frame hardware to packetize data +// Get 8-bit output from demodulator +// Get lowest 16 bits of I/Q data provided to demodulator +// Get highest 16 bits of I/Q data provided to demodulator +// Default: RX_PACKET_DATA +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_SOURCE RX_PACKET_DATA +// Method of Retrieving RX Data +// Packet Mode +// FIFO Mode +// Default: PACKET_MODE +#define SL_RAIL_UTIL_INIT_DATA_FORMAT_INST0_RX_MODE PACKET_MODE +// +// + +// Radio Event Configuration +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENTS_INST0_ENABLE 1 +// RX Radio Events +// RX Timing Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_DETECT_INST0_ENABLE 0 +// RX Timing Lost +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TIMING_LOST_INST0_ENABLE 0 +// RX Preamble Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_DETECT_INST0_ENABLE 0 +// RX Preamble Lost +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PREAMBLE_LOST_INST0_ENABLE 1 +// RX Sync1 Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SYNC1_DETECT_INST0_ENABLE 0 +// RX Sync2 Detect +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SYNC2_DETECT_INST0_ENABLE 0 +// RX Filter Passed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FILTER_PASSED_INST0_ENABLE 0 +// RX Address Filtered +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_ADDRESS_FILTERED_INST0_ENABLE 1 +// RX Packet Received +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_RECEIVED_INST0_ENABLE 1 +// RX Frame Error +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FRAME_ERROR_INST0_ENABLE 1 +// RX Packet Aborted +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_PACKET_ABORTED_INST0_ENABLE 1 +// RX Timeout +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TIMEOUT_INST0_ENABLE 0 +// RX Channel Hopping Complete +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_CHANNEL_HOPPING_COMPLETE_INST0_ENABLE 0 +// RX Duty Cycle RX End +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_DUTY_CYCLE_RX_END_INST0_ENABLE 0 +// +// TX Radio Events +// TX Packet Sent +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_PACKET_SENT_INST0_ENABLE 1 +// TX Aborted +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_ABORTED_INST0_ENABLE 1 +// TX Blocked +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_INST0_ENABLE 1 +// TX Started +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_STARTED_INST0_ENABLE 1 +// +// RSSI Radio Events +// RSSI Average Done +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RSSI_AVERAGE_DONE_INST0_ENABLE 0 +// +// FIFO Radio Events +// RX FIFO, Almost Full +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_ALMOST_FULL_INST0_ENABLE 0 +// RX FIFO, Full +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_FULL_INST0_ENABLE 0 +// RX FIFO, Overflow +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_FIFO_OVERFLOW_INST0_ENABLE 1 +// TX FIFO, Almost Empty +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_FIFO_ALMOST_EMPTY_INST0_ENABLE 0 +// TX FIFO, Underflow +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_UNDERFLOW_INST0_ENABLE 1 +// +// CCA Radio Events +// TX CCA, Channel Clear +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_CLEAR_INST0_ENABLE 0 +// TX CCA, Channel Busy +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_CHANNEL_BUSY_INST0_ENABLE 1 +// TX CCA, Retry +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_CCA_RETRY_INST0_ENABLE 0 +// TX CCA, Started +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_START_CCA_INST0_ENABLE 0 +// +// Scheduled Radio Events +// Scheduled RX/TX Started +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_TX_SCHEDULED_RX_TX_STARTED_INST0_ENABLE 1 +// Scheduled RX End +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_END_INST0_ENABLE 1 +// Scheduled RX Missed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_SCHEDULED_RX_MISSED_INST0_ENABLE 1 +// Scheduled TX Missed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_SCHEDULED_TX_MISSED_INST0_ENABLE 1 +// +// ACK Radio Events +// RX ACK, Timeout +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_RX_ACK_TIMEOUT_INST0_ENABLE 0 +// TX ACK, Packet Sent +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_PACKET_SENT_INST0_ENABLE 0 +// TX ACK, Aborted +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_ABORTED_INST0_ENABLE 0 +// TX ACK, Blocked +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_BLOCKED_INST0_ENABLE 0 +// TX ACK, FIFO Underflow +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TXACK_UNDERFLOW_INST0_ENABLE 0 +// +// Protocol Radio Events +// IEEE 802.15.4 Data Request Command +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_IEEE802154_DATA_REQUEST_COMMAND_INST0_ENABLE 0 +// Z-Wave Beam +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_ZWAVE_BEAM_INST0_ENABLE 0 +// Z-Wave LR ACK Request Command +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_INST0_ENABLE 0 +// +// Dynamic Multiprotocol (DMP) Radio Events +// Config Unscheduled +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_CONFIG_UNSCHEDULED_INST0_ENABLE 1 +// Config Scheduled +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_CONFIG_SCHEDULED_INST0_ENABLE 1 +// Scheduler Status +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_SCHEDULER_STATUS_INST0_ENABLE 1 +// +// Calibration Radio Events +// Calibration Needed +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_CAL_NEEDED_INST0_ENABLE 1 +// +// RSSI Radio Events +// RSSI detect threshold +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_DETECT_RSSI_THRESHOLD_INST0_ENABLE 0 +// +// Thermistor Events +// End of thermistor measurement +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_THERMISTOR_DONE_INST0_ENABLE 0 +// +// Temperature Events +// Transmit blocked because of temperature limitation +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TX_BLOCKED_TOO_HOT_INST0_ENABLE 0 +// Temperature is too hot for Tx operation +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_TOO_HOT_INST0_ENABLE 0 +// Temperature has cooled enough for Tx operation +// Default: 0 +#define SL_RAIL_UTIL_INIT_EVENT_TEMPERATURE_COOL_DOWN_INST0_ENABLE 0 +// +// + +// +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_INIT_INST0_CONFIG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_pa_config.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..527858fc5c --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_pa_config.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" +#ifdef RAIL_INTERNAL_BUILD +#include "sl_rail_util_pa_config_internal.h" +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#ifndef SL_RAIL_UTIL_PA_SELECTION_2P4GHZ +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_NONE +#endif +// Sub-1 GHz PA Selection +// Enable +// Disable +// Default: RAIL_TX_POWER_MODE_SUBGIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_SUBGIG_HIGHEST +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_protocol_config.h b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_protocol_config.h new file mode 100644 index 0000000000..00541a1bdd --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/config/sl_rail_util_protocol_config.h @@ -0,0 +1,130 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PROTOCOL_CONFIG_H +#define SL_RAIL_UTIL_PROTOCOL_CONFIG_H + +#include "sl_rail_util_protocol_types.h" +#ifdef RAIL_INTERNAL_BUILD +#include "sl_rail_util_protocol_config_internal.h" +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Z-Wave Settings +// Z-Wave: Configuration Options +// Enable/Disable Z-Wave +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_ENABLE 0 +// Enable Promiscuous Mode +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_PROMISCUOUS_MODE_ENABLE 1 +// Accept Beam Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_DETECT_BEAM_FRAME_ENABLE 1 +// Filter Packets Based on Node ID +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_NODE_ID_FILTERING_ENABLE 0 +// Enable Promiscuous Beam Mode +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_PROMISCUOUS_BEAM_MODE_ENABLE 0 +// + +// Z-Wave: Transition Times +// Transition time (microseconds) from idle to RX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_IDLE_TO_RX_US 100 +// Transition time (microseconds) from TX to RX +// <0-65535:1> +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_TX_TO_RX_US 0 +// Transition time (microseconds) from idle to TX +// <0-65535:1> +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_IDLE_TO_TX_US 0 +// Transition time (microseconds) from RX to TX +// <0-65535:1> +// Default: 1000 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_TO_TX_US 1000 +// + +// Z-Wave: RX Search Timeouts +// Enable RX Search timeout after Idle +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from idle +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_US 65535 +// +// Enable RX Search timeout after TX +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from TX +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_US 65535 +// +// + +// Z-Wave: Auto ACK Configuration +// Enable Auto ACKs +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_ENABLE 0 +// RX ACK timeout duration (microseconds) +// <1-9600:1> +// Default: 9600 +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_TIMEOUT_US 9600 +// Radio state transition after attempting to receive ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_RX_TRANSITION_STATE RAIL_RF_STATE_RX +// Radio state transition after transmitting ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_ZWAVE_AUTO_ACK_TX_TRANSITION_STATE RAIL_RF_STATE_RX +// +// +// + +// Sidewalk Settings +// Sidewalk: Configuration Options +// Enable/Disable Sidewalk +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_SIDEWALK_ENABLE 0 +// +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PROTOCOL_CONFIG_H diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/raillib.mk b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/raillib.mk new file mode 100644 index 0000000000..c41e2258e2 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/raillib.mk @@ -0,0 +1,35 @@ +# Required platform files. +GECKO_SDK = $(CHIBIOS_CONTRIB)/ext/gecko_sdk + +# Below are RAIL lib binding for ChibiOS. +RAILLIBSRC = \ + raillib/raillib_chibios.c + +# Below are imports from Radio Configurator +RAILLIBSRC += raillib/autogen/rail_config.c +RAILLIBSRC += raillib/autogen/sl_rail_util_callbacks.c +#RAILLIBSRC += raillib/autogen/sl_rail_util_init.c + +# Below are imports from Gecko SDK +RAILLIBSRC += $(GECKO_SDK)/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c +RAILLIBSRC += $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_protocol/sl_rail_util_protocol.c + +RAILLIBINC = \ + raillib/autogen \ + raillib/config + +RAILLIBINC += \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/pa-conversions \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_callbacks \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_callbacks/config \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_protocol \ + $(GECKO_SDK)/platform/radio/rail_lib/plugin/rail_util_protocol/config \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/ble \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/ieee802154 \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/sidewalk \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/wmbus \ + $(GECKO_SDK)/platform/radio/rail_lib/protocol/zwave + +# Shared variables +ALLCSRC += $(RAILLIBSRC) +ALLINC += $(RAILLIBINC) diff --git a/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/raillib_chibios.c b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/raillib_chibios.c new file mode 100644 index 0000000000..d8c251310c --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/TEMPLATE/raillib/raillib_chibios.c @@ -0,0 +1,253 @@ +#include "hal.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +uint32_t sli_tz_syscfg_read_chiprev_register(void) { + + return (SYSCFG->CHIPREV); +} +#endif + +/* SystemNNNGet are declared as weak function as they can be overwritten + by linking with system_efr32fg23.c. */ +CC_WEAK uint32_t SystemHFXOClockGet(void) { + + return EFR32_HFXO_FREQ; +} + +CC_WEAK uint32_t SystemSYSCLKGet(void) { + + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (EFR32_HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: + ret = HFXO_FREQ; + break; +#endif + +#if (EFR32_CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = EFR32_FSRCO_FREQ; + break; + + default: + osalDbgAssert(false, "Unknown clock source."); + break; + } + + return ret; +} + +CC_WEAK uint32_t SystemHFRCODPLLClockGet(void) { + + uint32_t ret = 0UL; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +} + +OSAL_IRQ_HANDLER(EFR32_RFECA0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RFECA0_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_RFECA1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RFECA1_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_SYSRTC_SEQ_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + SYSRTC_SEQ_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_AGC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + AGC_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_BUFC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + BUFC_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_EMUDG_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + EMUDG_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_FRC_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + FRC_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_FRC_PRI_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + FRC_PRI_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_HOSTMAILBOX_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + HOSTMAILBOX_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_MODEM_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + MODEM_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_PROTIMER_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + PROTIMER_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_RAC_RSM_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RAC_RSM_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_RAC_SEQ_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + RAC_SEQ_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(EFR32_SYNTH_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + SYNTH_IRQHandler(); + + OSAL_IRQ_EPILOGUE(); +} + diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/Makefile b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/Makefile new file mode 100644 index 0000000000..0ee370bd4f --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/Makefile @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DEFR32FG23B010F512IM48=1 \ + -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/halconf.h new file mode 100644 index 0000000000..fb9cef69c4 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/halconf_community.h new file mode 100644 index 0000000000..04bffb1565 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 FALSE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 FALSE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 FALSE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/mcuconf.h new file mode 100644 index 0000000000..1a70745bfb --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/cfg/mcuconf.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_LFXO + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 TRUE +#define EFR32_SIO_USE_EUSART2 TRUE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/main.c b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/main.c new file mode 100644 index 0000000000..a0eff652da --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/main.c @@ -0,0 +1,176 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "cmsis_os.h" +#include "hal.h" + +static void led_on(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static void test_GetX_PutX(SIODriver *siop, uint16_t data) { + + msg_t msg; + + osDelay(10); + sioPutX(siop, data); + osDelay(10); + msg = sioGetX(siop); + osalDbgCheck(data == msg); +} + +static void test_sioAsyncRead_sioAsyncWrite(SIODriver *siop, const uint8_t *tx_buffer, size_t n) { + + uint8_t rx_buffer[16]; + size_t rx_bytes = 0; + size_t tx_bytes = 0; + + osalDbgCheck(n <= sizeof(rx_buffer)); + + osDelay(10); + + while (tx_bytes < n) { + tx_bytes += sioAsyncWrite(siop, &tx_buffer[tx_bytes], n - tx_bytes); + + while (rx_bytes < tx_bytes) { + rx_bytes += sioAsyncRead(siop, &rx_buffer[rx_bytes], n - rx_bytes); + } + } + + osalDbgCheck(tx_bytes == n); + osalDbgCheck(rx_bytes == n); +} + +static void test_synchronized_api(SIODriver *siop, const uint8_t *tx_buffer, size_t n) { + +#if (SIO_USE_SYNCHRONIZATION == TRUE) || defined(__DOXYGEN__) + msg_t msg; + uint8_t rx_buffer[16]; + size_t rx_bytes = 0; + size_t tx_bytes = 0; + + osalDbgCheck(n <= sizeof(rx_buffer)); + + osDelay(10); + + while (tx_bytes < n) { + tx_bytes += sioAsyncWrite(siop, &tx_buffer[tx_bytes], n - tx_bytes); + msg = sioSynchronizeTXEnd(siop, TIME_INFINITE); + osalDbgCheck(msg == MSG_OK); + + while (rx_bytes < tx_bytes) { + msg = sioSynchronizeRX(siop, TIME_INFINITE); + osalDbgCheck(msg == MSG_OK); + rx_bytes += sioAsyncRead(siop, &rx_buffer[rx_bytes], n - rx_bytes); + } + } + + osalDbgCheck(tx_bytes == n); + osalDbgCheck(rx_bytes == n); +#endif +} + +static void test_vcom_eusart_slow(void) { + + SIODriver *siop = NULL; + const SIOConfig sio_config = { + .baud = 2400U, /* Baudrate (2400 max. for LF operation) */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (4U << 5), /* Disable oversampling (for LF operation) */ + .framecfg = EFR32_SIO_LLD_EUSART_8E1, + }; + + #if EFR32_SIO_USE_EUSART1 == TRUE + palSetPadMode(GPIOA, 9, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART0_TX)); + palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART0_RX)); + + siop = &SIOD1; + sioStart(siop, &sio_config); + test_synchronized_api(siop, (const uint8_t*)"\r\nEUSART1", 9); + test_GetX_PutX(siop, '1'); + test_sioAsyncRead_sioAsyncWrite(siop, (const uint8_t*)"EUSART1", 7); + osDelay(10); + sioStop(siop); + + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(EUSART0_TX_DIS)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(EUSART0_RX_DIS)); + #endif + + #if EFR32_SIO_USE_EUSART2 == TRUE + palSetPadMode(GPIOA, 9, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART1_TX)); + palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART1_RX)); + + siop = &SIOD2; + sioStart(siop, &sio_config); + test_synchronized_api(siop, (const uint8_t*)"\r\nEUSART2", 9); + test_GetX_PutX(siop, '2'); + test_sioAsyncRead_sioAsyncWrite(siop, (const uint8_t*)"EUSART2", 7); + osDelay(10); + sioStop(siop); + + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(EUSART1_TX_DIS)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(EUSART1_RX_DIS)); + #endif + + #if EFR32_SIO_USE_EUSART3 == TRUE + osalDbgAssert(true, "Untestable since EUSART3 is only available on Port C and D which are not present on the board header."); + #endif +} + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; + (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + led_off(); + test_vcom_eusart_slow(); + led_on(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + osDelay(1000); + } +} diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO-SLOW/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/Makefile b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/Makefile new file mode 100644 index 0000000000..0ee370bd4f --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/Makefile @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m33 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_efr32fg23x.mk +# HAL-OSAL files (optional). +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SILABS/EFR32FG23/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SILABS_EFR32FG23_DK2600A/board.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk +#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML-TZ/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +#include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/common/abstractions/cmsis_os/cmsis_os.mk + +# Define linker script file here +LDSCRIPT = $(STARTUPLD_CONTRIB)/EFR32FG23XF512.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wcast-align=strict + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DEFR32FG23B010F512IM48=1 \ + -DCORTEX_ENABLE_WFI_IDLE \ + -DESCAPE_HATCH_ENABLE=TRUE + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +include post-build.mk + +# +# Custom rules +############################################################################## diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/chconf.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/chconf.h new file mode 100644 index 0000000000..668bfae72e --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/chconf.h @@ -0,0 +1,840 @@ +/* + ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 4096 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/halconf.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/halconf.h new file mode 100644 index 0000000000..fb9cef69c4 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/halconf_community.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/halconf_community.h new file mode 100644 index 0000000000..04bffb1565 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/halconf_community.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + +/** + * @brief Enables the BURAM subsystem. + */ +#if !defined(HAL_USE_BURAM) || defined(__DOXYGEN__) +#define HAL_USE_BURAM FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* BURAM driver related settings. */ +/*===========================================================================*/ + +#if !defined(BURAM_USE_BURAM1) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM1 FALSE +#endif + +#if !defined(BURAM_USE_BURAM2) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM2 FALSE +#endif + +#if !defined(BURAM_USE_BURAM3) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM3 FALSE +#endif + +#if !defined(BURAM_USE_BURAM4) || defined(__DOXYGEN__) +#define BURAM_USE_BURAM4 FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/mcuconf.h b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/mcuconf.h new file mode 100644 index 0000000000..48aa277ad9 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/cfg/mcuconf.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2023 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * EFR32FG14P drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define EFR32FG23X_MCUCONF + +/* + * HAL driver system settings. + */ + +/* + * Power settings. + */ +#define EFR32_EM01VSCALE_SEL EFR32_EM01_VSCALESEL_1V1 +#define EFR32_EM23VSCALE_SEL EFR32_EM23_VSCALESEL_1V1 + +/* + * Clock settings. + */ +#define EFR32_CMU_SYSCLKCTRL (EFR32_SYSCLKSEL | EFR32_PPRE | EFR32_HPRE | EFR32_RHPRE) +#define EFR32_LFXO_ENABLED TRUE +#define EFR32_LFRCO_ENABLED FALSE +#define EFR32_ULFRCO_ENABLED FALSE +#define EFR32_FSRCO_ENABLED FALSE +#define EFR32_HFRCODPLL_ENABLED TRUE +#define EFR32_HFRCOEM23_ENABLED TRUE +#define EFR32_HFXO_ENABLED FALSE +#define EFR32_SYSCLKSEL EFR32_SYSCLKSEL_HFRCODPLL +#define EFR32_PPRE EFR32_PPRE_DIV1 +#define EFR32_HPRE EFR32_HPRE_DIV1 +#define EFR32_RHPRE EFR32_RHPRE_DIV1 +#define EFR32_HFRCOPRE EFR32_HFRCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define EFR32_EM01GRPACLKSEL EFR32_EM01GRPACLKSEL_HFRCODPLL +#define EFR32_EM01GRPACLK_ENABLED (EFR32_EM01GRPACLKSEL != EFR32_EM01GRPACLKSEL_NOCLOCK) + +#define EFR32_EM01GRPCCLKSEL EFR32_EM01GRPCCLKSEL_HFRCODPLL +#define EFR32_EM01GRPCCLK_ENABLED (EFR32_EM01GRPCCLKSEL != EFR32_EM01GRPCCLKSEL_NOCLOCK) + +#define EFR32_EM23GRPACLKSEL EFR32_EM23GRPACLKSEL_LFXO +#define EFR32_EM23GRPACLK_ENABLED (EFR32_EM23GRPACLKSEL != EFR32_EM23GRPACLKSEL_NOCLOCK) + +#define EFR32_EM4GRPACLKSEL EFR32_EM4GRPACLKSEL_LFXO +#define EFR32_EM4GRPACLK_ENABLED (EFR32_EM4GRPACLKSEL != EFR32_EM4GRPACLKSEL_NOCLOCK) + +#define EFR32_EUSART1SEL EFR32_EUSART1SEL_EM01GRPCCLK + +#define EFR32_EUSART23SEL EFR32_EUSART23SEL_HFRCODPLL + +#define EFR32_DAC1SEL EFR32_DAC1SEL_HFRCOEM23 + +/* + * ST driver system settings. + */ +#define EFR32_ST_IRQ_PRIORITY 4 +#define EFR32_ST_USE_TIMER 1 + +/* + * GPIO driver system settings. + */ +#define EFR32_GPIO_ODD_IRQ_PRIORITY 4 +#define EFR32_GPIO_EVEN_IRQ_PRIORITY 4 + +/* + * SIO driver system settings. + */ +#define EFR32_SIO_USE_EUSART1 TRUE +#define EFR32_SIO_USE_EUSART2 TRUE +#define EFR32_SIO_USE_EUSART3 FALSE +#define EFR32_SIO_USE_USART1 TRUE +#define EFR32_EUSART1_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART1_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART2_TX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_RX_IRQ_PRIORITY 4 +#define EFR32_EUSART3_TX_IRQ_PRIORITY 4 +#define EFR32_USART1_RX_IRQ_PRIORITY 4 +#define EFR32_USART1_TX_IRQ_PRIORITY 4 + +/* + * RTC driver system settings. + */ +#define EFR32_BURTC_PRIORITY 4 + +/* + * DAC driver system settings. + */ +#define EFR32_DAC_DUAL_MODE FALSE +#define EFR32_DAC_USE_DAC1_CH1 TRUE +#define EFR32_DAC_USE_DAC1_CH2 TRUE +#define EFR32_DAC_DAC1_IRQ_PRIORITY 4 +#define EFR32_DAC_DAC1_CH1_DMA_STREAM EFR32_DMA_STREAM_ID_ANY +#define EFR32_DAC_DAC1_CH2_DMA_STREAM EFR32_DMA_STREAM_ID_ANY + +#endif /* MCUCONF_H */ diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/main.c b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/main.c new file mode 100644 index 0000000000..f9a43b0d07 --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/main.c @@ -0,0 +1,204 @@ +/* + ChibiOS - Copyright (C) 2024 Xael South + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include "cmsis_os.h" +#include "hal.h" + +static void led_on(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(GPIOB, 2); +} + +static void led_off(void) { + + /* PB2 = LED */ + palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(GPIOB, 2); +} + +static void test_GetX_PutX(SIODriver *siop, uint16_t data) { + + msg_t msg; + + osDelay(10); + sioPutX(siop, data); + osDelay(10); + msg = sioGetX(siop); + osalDbgCheck(data == msg); +} + +static void test_sioAsyncRead_sioAsyncWrite(SIODriver *siop, const uint8_t *tx_buffer, size_t n) { + + uint8_t rx_buffer[16]; + size_t rx_bytes = 0; + size_t tx_bytes = 0; + + osalDbgCheck(n <= sizeof(rx_buffer)); + + osDelay(10); + + while (tx_bytes < n) { + tx_bytes += sioAsyncWrite(siop, &tx_buffer[tx_bytes], n - tx_bytes); + + while (rx_bytes < tx_bytes) { + rx_bytes += sioAsyncRead(siop, &rx_buffer[rx_bytes], n - rx_bytes); + } + } + + osalDbgCheck(tx_bytes == n); + osalDbgCheck(rx_bytes == n); +} + +static void test_synchronized_api(SIODriver *siop, const uint8_t *tx_buffer, size_t n) { + +#if (SIO_USE_SYNCHRONIZATION == TRUE) || defined(__DOXYGEN__) + msg_t msg; + uint8_t rx_buffer[16]; + size_t rx_bytes = 0; + size_t tx_bytes = 0; + + osalDbgCheck(n <= sizeof(rx_buffer)); + + osDelay(10); + + while (tx_bytes < n) { + tx_bytes += sioAsyncWrite(siop, &tx_buffer[tx_bytes], n - tx_bytes); + msg = sioSynchronizeTXEnd(siop, TIME_INFINITE); + osalDbgCheck(msg == MSG_OK); + + while (rx_bytes < tx_bytes) { + msg = sioSynchronizeRX(siop, TIME_INFINITE); + osalDbgCheck(msg == MSG_OK); + rx_bytes += sioAsyncRead(siop, &rx_buffer[rx_bytes], n - rx_bytes); + } + } + + osalDbgCheck(tx_bytes == n); + osalDbgCheck(rx_bytes == n); +#endif +} + +static void test_vcom_eusart(void) { + + SIODriver *siop = NULL; + const SIOConfig sio_config = { + .baud = 115200U, /* Baudrate */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (0U << 5), /* 16x oversampling (for HF operation) */ + .framecfg = EFR32_SIO_LLD_EUSART_8N1 + }; + + #if EFR32_SIO_USE_EUSART1 == TRUE + palSetPadMode(GPIOA, 9, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART0_TX)); + palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART0_RX)); + + siop = &SIOD1; + sioStart(siop, &sio_config); + test_synchronized_api(siop, (const uint8_t*)"\r\nEUSART1", 9); + test_GetX_PutX(siop, '1'); + test_sioAsyncRead_sioAsyncWrite(siop, (const uint8_t*)"EUSART1", 7); + osDelay(10); + sioStop(siop); + + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(EUSART0_TX_DIS)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(EUSART0_RX_DIS)); + #endif + + #if EFR32_SIO_USE_EUSART2 == TRUE + palSetPadMode(GPIOA, 9, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(EUSART1_TX)); + palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(EUSART1_RX)); + + siop = &SIOD2; + sioStart(siop, &sio_config); + test_synchronized_api(siop, (const uint8_t*)"\r\nEUSART2", 9); + test_GetX_PutX(siop, '2'); + test_sioAsyncRead_sioAsyncWrite(siop, (const uint8_t*)"EUSART2", 7); + osDelay(10); + sioStop(siop); + + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(EUSART1_TX_DIS)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(EUSART1_RX_DIS)); + #endif + + #if EFR32_SIO_USE_EUSART3 == TRUE + osalDbgAssert(true, "Untestable since EUSART3 is only available on Port C and D which are not present on the board header."); + #endif +} + +static void test_vcom_usart(void) { + + SIODriver *siop = NULL; + const SIOConfig sio_config = { + .baud = 115200U, /* Baudrate */ + .cfg0 = (0U << 0) | /* ASYNC operation */ + (0U << 5), /* 16x oversampling (for HF operation) */ + .framecfg = EFR32_SIO_LLD_USART_8N1 + }; + + #if EFR32_SIO_USE_USART1 == TRUE + palSetPadMode(GPIOA, 9, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(USART0_TX)); + palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLUP | PAL_MODE_ALTERNATE(USART0_RX)); + + siop = &SIOD4; + sioStart(siop, &sio_config); + test_synchronized_api(siop, (const uint8_t*)"\r\nUSART1", 8); + test_GetX_PutX(siop, '4'); + test_sioAsyncRead_sioAsyncWrite(siop, (const uint8_t*)"USART1", 6); + osDelay(10); + sioStop(siop); + + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(USART0_TX_DIS)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(USART0_RX_DIS)); + #endif +} + +/* + * Application entry point. + */ +int main(void) { + + int unused = 0; + (void)unused; + + /* HAL initialization, this also initializes the configured device drivers + and performs the board-specific initializations.*/ + halInit(); + + /* The kernel is initialized but not started yet, this means that + main() is executing with absolute priority but interrupts are + already enabled.*/ + osKernelInitialize(); + + /* Kernel started, the main() thread has priority osPriorityNormal + by default.*/ + osKernelStart(); + + led_off(); + test_vcom_usart(); + test_vcom_eusart(); + led_on(); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + osDelay(1000); + } +} \ No newline at end of file diff --git a/testhal/SILABS/EFR32FG23x0xx/UART-SIO/post-build.mk b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/post-build.mk new file mode 100644 index 0000000000..474874abff --- /dev/null +++ b/testhal/SILABS/EFR32FG23x0xx/UART-SIO/post-build.mk @@ -0,0 +1,22 @@ +POST_MAKE_ALL_RULE_HOOK: print-all-sections + +print-all-sections: $(BUILDDIR)/$(PROJECT).elf + $(SZ) -A -t $< + +JLINK ?= JLinkExe +JLINK_GDB_SERVER ?= JLinkGDBServerCLExe + +JLINK_SPEED ?= 4000 +DEVICE_PART = EFR32FG23BXXXF512 + +#JLINK_ARGS ?= USB 12345678 +#JLINK_GDB_SERVER_ARGS ?= -select 12345678 +JLINK_ARGS ?= +JLINK_GDB_SERVER_ARGS ?= +JLINK_SCRIPT := $(shell mktemp) +program: $(BUILDDIR)/$(PROJECT).hex + @echo 'Erase\nLoadFile $<\nReset\nExit\n' >$(JLINK_SCRIPT) + $(JLINK) -NoGui 1 -AutoConnect 1 -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -CommandFile $(JLINK_SCRIPT) + +start_gdb: $(BUILDDIR)/$(PROJECT).hex + $(JLINK_GDB_SERVER) -Device $(DEVICE_PART) -Speed $(JLINK_SPEED) -If SWD $(JLINK_ARGS) -localhostonly