diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 657faa10c5..5ecc6d7424 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -65,3 +65,7 @@ jobs: - name: build SAMD21 run: | $CHC_PATH/tools/chbuild.sh $CHC_PATH/testhal/SAMD21A + - name: build AT32 + run: | + $CHC_PATH/tools/chbuild.sh $CHC_PATH/testhal/AT32 + $CHC_PATH/tools/chbuild.sh $CHC_PATH/demos/AT32 diff --git a/demos/AT32/.keep b/demos/AT32/.keep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h new file mode 100644 index 0000000000..61a3258568 --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file at32f415.h + * @author Artery Technology & HorrorTroll & Zhaqian + * @brief AT32F415 header file + * + ****************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f415 + * @{ + */ + +#ifndef __AT32F415_H +#define __AT32F415_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#if defined (__CC_ARM) + #pragma anon_unions +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief AT32 Family + */ +#if !defined (AT32F415) +#define AT32F415 +#endif /* AT32F415 */ + +/* Uncomment the line below according to the target AT32 device used in your + application + */ + +#if !defined(AT32F415KB) && !defined(AT32F415KC) && !defined(AT32F415CB) && \ + !defined(AT32F415CC) && !defined(AT32F415RB) && !defined(AT32F415RC) + /* #define AT32F415KB */ /*!< AT32F415K8 and AT32F415KB */ + /* #define AT32F415KC */ /*!< AT32F415KC */ + /* #define AT32F415CB */ /*!< AT32F415C8 and AT32F415CB */ + /* #define AT32F415CC */ /*!< AT32F415CC */ + /* #define AT32F415RB */ /*!< AT32F415R8 and AT32F415RB */ + /* #define AT32F415RC */ /*!< AT32F415RC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#ifndef USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #ifdef _RTE_ + #include "RTE_Components.h" + #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK + #define USE_STDPERIPH_DRIVER + #endif + #endif +#endif /* USE_STDPERIPH_DRIVER */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(AT32F415KB) + #include "at32f415kx.h" +#elif defined(AT32F415KC) + #include "at32f415kx.h" +#elif defined(AT32F415CB) + #include "at32f415cx.h" +#elif defined(AT32F415CC) + #include "at32f415cx.h" +#elif defined(AT32F415RB) + #include "at32f415rx.h" +#elif defined(AT32F415RC) + #include "at32f415rx.h" +#else + #error "Please select first the target AT32F415 device used in your application (in at32f415.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ + +typedef int32_t INT32; +typedef int16_t INT16; +typedef int8_t INT8; +typedef uint32_t UINT32; +typedef uint16_t UINT16; +typedef uint8_t UINT8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< read only */ +typedef const int16_t sc16; /*!< read only */ +typedef const int8_t sc8; /*!< read only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< read only */ +typedef __I int16_t vsc16; /*!< read only */ +typedef __I int8_t vsc8; /*!< read only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< read only */ +typedef const uint16_t uc16; /*!< read only */ +typedef const uint8_t uc8; /*!< read only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< read only */ +typedef __I uint16_t vuc16; /*!< read only */ +typedef __I uint8_t vuc8; /*!< read only */ + +/** + * @brief flag status + */ +typedef enum {RESET = 0, SET = !RESET} flag_status; + +/** + * @brief confirm state + */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} confirm_state; + +/** + * @brief error status + */ +typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ + +#define REG8(addr) *(volatile uint8_t *)(addr) +#define REG16(addr) *(volatile uint16_t *)(addr) +#define REG32(addr) *(volatile uint32_t *)(addr) + +#define MAKE_VALUE(reg_offset, bit_num) (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F)) + +#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16))) +#define PERIPH_REG_BIT(value) (0x1U << (value & 0x1F)) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F415_H */ + +/** + * @} + */ + +/** + * @} + */ + +/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h new file mode 100644 index 0000000000..a1609cf0dd --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -0,0 +1,10497 @@ +/** + ****************************************************************************** + * @file at32f415cx.h + * @author Artery Technology & HorrorTroll & Zhaqian + * @version v2.1.1 + * @date 26-October-2023 + * @brief AT32F415Cx header file. + * + ****************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f415cx + * @{ + */ + +#ifndef __AT32F415Cx_H +#define __AT32F415Cx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief CMSIS Device version number V2.1.1 + */ +#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ +#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ + |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ + |(__AT32F415_LIBRARY_VERSION_MINOR << 8 )\ + |(__AT32F415_LIBRARY_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< AT32 devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< AT32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< AT32 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief AT32F415Cx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector Interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** AT32 specific Interrupt Numbers **********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ + PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ + ERTC_IRQn = 3, /*!< ERTC Interrupt linked to EXINT22 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + CRM_IRQn = 5, /*!< CRM global Interrupt */ + EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ + EXINT1_IRQn = 7, /*!< EXINT Line 1 Interrupt */ + EXINT2_IRQn = 8, /*!< EXINT Line 2 Interrupt */ + EXINT3_IRQn = 9, /*!< EXINT Line 3 Interrupt */ + EXINT4_IRQn = 10, /*!< EXINT Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SE_IRQn = 22, /*!< CAN1 SE Interrupt */ + EXINT9_5_IRQn = 23, /*!< EXINT Line[9:5] Interrupts */ + TMR1_BRK_TMR9_IRQn = 24, /*!< TMR1 Break Interrupt and TMR9 global Interrupt */ + TMR1_OVF_TMR10_IRQn = 25, /*!< TMR1 Overflow Interrupt and TMR10 global Interrupt */ + TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< TMR1 Trigger and Hall Interrupt and TMR11 global IRQ */ + TMR1_CH_IRQn = 27, /*!< TMR1 Channel Interrupt */ + TMR2_GLOBAL_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_GLOBAL_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_GLOBAL_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EVT_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ERR_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EVT_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ERR_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXINT15_10_IRQn = 40, /*!< EXINT Line[15:10] Interrupts */ + ERTCAlarm_IRQn = 41, /*!< ERTC Alarm Interrupt linked to EXINT17 */ + OTGFS_WKUP_IRQn = 42, /*!< OTGFS Wake Up Interrupt linked to EXINT18 */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_GLOBAL_IRQn = 50, /*!< TMR5 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + OTGFS_IRQn = 67, /*!< OTGFS global Interrupt */ + CMP1_IRQn = 70, /*!< CMP1 Interrupt linked to EXINT19 */ + CMP2_IRQn = 71, /*!< CMP2 Interrupt linked to EXINT20 */ + DMA2_Channel6_7_IRQn = 75, /*!< DMA2 Channel 6 and Channel 7 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" +#include "system_at32f415.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CTRL2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SPT1; /*!< ADC sampling time register 1, Address offset: 0x0C */ + __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x10 */ + __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x14 */ + __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x18 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3 Address offset: 0x1C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4 Address offset: 0x20 */ + __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x24 */ + __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x28 */ + __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x2C */ + __IO uint32_t OSQ2; /*!< ADC ordinary sequence register 2, Address offset: 0x30 */ + __IO uint32_t OSQ3; /*!< ADC ordinary sequence register 3, Address offset: 0x34 */ + __IO uint32_t PSQ; /*!< ADC preempted sequence register, Address offset: 0x38 */ + __IO uint32_t PDT1; /*!< ADC preempted data register 1, Address offset: 0x3C */ + __IO uint32_t PDT2; /*!< ADC preempted data register 2, Address offset: 0x40 */ + __IO uint32_t PDT3; /*!< ADC preempted data register 3, Address offset: 0x44 */ + __IO uint32_t PDT4; /*!< ADC preempted data register 4, Address offset: 0x48 */ + __IO uint32_t ODT; /*!< ADC ordinary data register, Address offset: 0x4C */ +} ADC_TypeDef; + +/** + * @brief Controller Area Network TX Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMC; + __IO uint32_t TMDTL; + __IO uint32_t TMDTH; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFO Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t RFI; + __IO uint32_t RFC; + __IO uint32_t RFDTL; + __IO uint32_t RFDTH; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network Filter Registers + */ + +typedef struct +{ + __IO uint32_t FFB1; + __IO uint32_t FFB2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; /*!< CAN master control register, Address offset: 0x000 */ + __IO uint32_t MSTS; /*!< CAN master status register, Address offset: 0x004 */ + __IO uint32_t TSTS; /*!< CAN transmit status register, Address offset: 0x008 */ + __IO uint32_t RF0; /*!< CAN receive FIFO 0 register, Address offset: 0x00C */ + __IO uint32_t RF1; /*!< CAN receive FIFO 1 register, Address offset: 0x010 */ + __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ + __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ + __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FF */ + __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ + __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ + __IO uint32_t FBWCFG; /*!< CAN filter bit width configuration register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x210 */ + __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ + __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ +} CAN_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CTRLSTS1; /*!< CMP control and status register 1, Address offset: 0x00 */ + __IO uint32_t CTRLSTS2; /*!< CMP control and status register 2, Address offset: 0x04 */ +} CMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DT; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t CDT; /*!< CRC Common data register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ +} CRC_TypeDef; + +/** + * @brief Clock and Reset Manage + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< CRM Clock control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< CRM Clock configuration register, Address offset: 0x04 */ + __IO uint32_t CLKINT; /*!< CRM Clock interrupt register, Address offset: 0x08 */ + __IO uint32_t APB2RST; /*!< CRM APB2 peripheral reset register, Address offset: 0x0C */ + __IO uint32_t APB1RST; /*!< CRM APB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHBEN; /*!< CRM APB peripheral clock enable register, Address offset: 0x14 */ + __IO uint32_t APB2EN; /*!< CRM APB2 peripheral clock enable register, Address offset: 0x18 */ + __IO uint32_t APB1EN; /*!< CRM APB1 peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t BPDC; /*!< CRM Battery powered domain control register, Address offset: 0x20 */ + __IO uint32_t CTRLSTS; /*!< CRM Control/status register, Address offset: 0x24 */ + __IO uint32_t AHBRST; /*!< CRM APB peripheral reset register, Address offset: 0x28 */ + __IO uint32_t PLL; /*!< CRM PLL configuration register, Address offset: 0x2C */ + __IO uint32_t MISC1; /*!< CRM Additional register 1, Address offset: 0x30 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x34 ~ 0x40 */ + __IO uint32_t OTG_EXTCTRL; /*!< CRM OTG_FS extended control register, Address offset: 0x44 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x48 - 0x50 */ + __IO uint32_t MISC2; /*!< CRM Additional register 2, Address offset: 0x54 */ +} CRM_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< DEBUG device ID, Address offset: 0xE004_2000 */ + __IO uint32_t CTRL; /*!< DEBUG control register, Address offset: 0xE004_2004 */ +} DEBUG_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) x = 1 ... 7 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t CLR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ + uint32_t RESERVED[38]; /*!< Reserved, Address offset: 0x08 ~ 0x9C */ + __IO uint32_t SRC_SEL0; /*!< DMA Channel source register 0, Address offset: 0xA0 */ + __IO uint32_t SRC_SEL1; /*!< DMA Channel source register 1, Address offset: 0xA4 */ +} DMA_TypeDef; + +/** + * @brief Enhanced Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TIME; /*!< ERTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< ERTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< ERTC control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< ERTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t DIV; /*!< ERTC divider register, Address offset: 0x10 */ + __IO uint32_t WAT; /*!< ERTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CCAL; /*!< ERTC coarse calibration register, Address offset: 0x18 */ + __IO uint32_t ALA; /*!< ERTC alarm clock A register, Address offset: 0x1C */ + __IO uint32_t ALB; /*!< ERTC alarm clock B register, Address offset: 0x20 */ + __IO uint32_t WP; /*!< ERTC write protection register, Address offset: 0x24 */ + __IO uint32_t SBS; /*!< ERTC subsecond register, Address offset: 0x28 */ + __IO uint32_t TADJ; /*!< ERTC time adjustment register, Address offset: 0x2C */ + __IO uint32_t TSTM; /*!< ERTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDT; /*!< ERTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSBS; /*!< ERTC time stamp subsecond register, Address offset: 0x38 */ + __IO uint32_t SCAL; /*!< ERTC smooth calibration register, Address offset: 0x3C */ + __IO uint32_t TAMP; /*!< ERTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALASBS; /*!< ERTC alarm clock A subsecond register, Address offset: 0x44 */ + __IO uint32_t ALBSBS; /*!< ERTC alarm clock B subsecond register, Address offset: 0x48 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t BPR1; /*!< ERTC battery powered domain data register 1, Address offset: 0x50 */ + __IO uint32_t BPR2; /*!< ERTC battery powered domain data register 2, Address offset: 0x54 */ + __IO uint32_t BPR3; /*!< ERTC battery powered domain data register 3, Address offset: 0x58 */ + __IO uint32_t BPR4; /*!< ERTC battery powered domain data register 4, Address offset: 0x5C */ + __IO uint32_t BPR5; /*!< ERTC battery powered domain data register 5, Address offset: 0x60 */ + __IO uint32_t BPR6; /*!< ERTC battery powered domain data register 6, Address offset: 0x64 */ + __IO uint32_t BPR7; /*!< ERTC battery powered domain data register 7, Address offset: 0x68 */ + __IO uint32_t BPR8; /*!< ERTC battery powered domain data register 8, Address offset: 0x6C */ + __IO uint32_t BPR9; /*!< ERTC battery powered domain data register 9, Address offset: 0x70 */ + __IO uint32_t BPR10; /*!< ERTC BAT powered domain data register 10, Address offset: 0x74 */ + __IO uint32_t BPR11; /*!< ERTC BAT powered domain data register 11, Address offset: 0x78 */ + __IO uint32_t BPR12; /*!< ERTC BAT powered domain data register 12, Address offset: 0x7C */ + __IO uint32_t BPR13; /*!< ERTC BAT powered domain data register 13, Address offset: 0x80 */ + __IO uint32_t BPR14; /*!< ERTC BAT powered domain data register 14, Address offset: 0x84 */ + __IO uint32_t BPR15; /*!< ERTC BAT powered domain data register 15, Address offset: 0x88 */ + __IO uint32_t BPR16; /*!< ERTC BAT powered domain data register 16, Address offset: 0x8C */ + __IO uint32_t BPR17; /*!< ERTC BAT powered domain data register 17, Address offset: 0x90 */ + __IO uint32_t BPR18; /*!< ERTC BAT powered domain data register 18, Address offset: 0x94 */ + __IO uint32_t BPR19; /*!< ERTC BAT powered domain data register 19, Address offset: 0x98 */ + __IO uint32_t BPR20; /*!< ERTC BAT powered domain data register 20, Address offset: 0x9C */ +} ERTC_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t INTEN; /*!< EXINT Interrupt enable register, Address offset: 0x00 */ + __IO uint32_t EVTEN; /*!< EXINT Event enable register, Address offset: 0x04 */ + __IO uint32_t POLCFG1; /*!< EXINT Polarity configuration register 1, Address offset: 0x08 */ + __IO uint32_t POLCFG2; /*!< EXINT Polarity configuration register 2, Address offset: 0x0C */ + __IO uint32_t SWTRG; /*!< EXINT Software trigger register, Address offset: 0x10 */ + __IO uint32_t INTSTS; /*!< EXINT Interrupt status register, Address offset: 0x14 */ +} EXINT_TypeDef; + +/** + * @brief Flash Memory Registers + */ + +typedef struct +{ + __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register 1, Address offset: 0x04 */ + __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t ADDR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t USD; /*!< FLASH user system data register, Address offset: 0x1C */ + __IO uint32_t EPPS; /*!< FLASH erase/program protection status reg, Address offset: 0x20 */ + uint32_t RESERVED1[20]; /*!< Reserved, Address offset: 0x24 ~ 0x70 */ + __IO uint32_t SLIB_STS0; /*!< FLASH security library status register 0, Address offset: 0x74 */ + __IO uint32_t SLIB_STS1; /*!< FLASH security library status register 1, Address offset: 0x78 */ + __IO uint32_t SLIB_PWD_CLR; /*!< FLASH security library password clear reg, Address offset: 0x7C */ + __IO uint32_t SLIB_MISC_STS; /*!< FLASH security library additional stat reg, Address offset: 0x80 */ + __IO uint32_t CRC_ADDR; /*!< FLASH CRC address register, Address offset: 0x84 */ + __IO uint32_t CRC_CTRL; /*!< FLASH CRC control register, Address offset: 0x88 */ + __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register, Address offset: 0x8C */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x90 ~ 0x15C */ + __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ + __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ + __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot mode setting register, Address offset: 0x16C */ + __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ +} FLASH_TypeDef; + +/** + * @brief User System Data Registers + */ + +typedef struct +{ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ +} USD_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ + __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ + __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ +} GPIO_TypeDef; + +/** + * @brief Multiplex Function I/O + */ + +typedef struct +{ + __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ + __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ + __IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */ + __IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */ + __IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */ + __IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ + __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ + __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ + __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ + __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ + __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ + __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ +} IOMUX_TypeDef; + +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OADDR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OADDR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DT; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t STS1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t STS2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CLKCTRL; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TMRISE; /*!< I2C timer rise time register, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< PWC Power control register, Address offset: 0x00 */ + __IO uint32_t CTRLSTS; /*!< PWC Power control/status register, Address offset: 0x04 */ +} PWC_TypeDef; + +/** + * @brief SD Host Interface + */ + +typedef struct +{ + __IO uint32_t PWRCTRL; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCTRL; /*!< SDIO clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RSPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RSP1; /*!< SDIO response register 1, Address offset: 0x14 */ + __I uint32_t RSP2; /*!< SDIO response register 2, Address offset: 0x18 */ + __I uint32_t RSP3; /*!< SDIO response register 3, Address offset: 0x1C */ + __I uint32_t RSP4; /*!< SDIO response register 4, Address offset: 0x20 */ + __IO uint32_t DTTMR; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DTLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DTCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DTCNTR; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STS; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t INTCLR; /*!< SDIO clear interrupt register, Address offset: 0x38 */ + __IO uint32_t INTEN; /*!< SDIO interrupt mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x40 ~ 0x44 */ + __I uint32_t BUFCNTR; /*!< SDIO BUF counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, Address offset: 0x4C ~ 0x7C */ + __IO uint32_t BUF; /*!< SDIO data BUF register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< SPI control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ + __IO uint32_t RCRC; /*!< SPI RX CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI TX CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S register, Address offset: 0x1C */ + __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TMR Timers + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< TMR control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< TMR control register 2, Address offset: 0x04 */ + __IO uint32_t STCTRL; /*!< TMR slave timer control register, Address offset: 0x08 */ + __IO uint32_t IDEN; /*!< TMR DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t ISTS; /*!< TMR interrupt status register, Address offset: 0x10 */ + __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ + __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ + __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ + __IO uint32_t CCTRL; /*!< TMR Channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value, Address offset: 0x28 */ + __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ + __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ + __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ + __IO uint32_t C2DT; /*!< TMR channel 2 data register, Address offset: 0x38 */ + __IO uint32_t C3DT; /*!< TMR channel 3 data register, Address offset: 0x3C */ + __IO uint32_t C4DT; /*!< TMR channel 4 data register, Address offset: 0x40 */ + __IO uint32_t BRK; /*!< TMR break register, Address offset: 0x44 */ + __IO uint32_t DMACTRL; /*!< TMR DMA control register, Address offset: 0x48 */ + __IO uint32_t DMADT; /*!< TMR DMA data register, Address offset: 0x4C */ +} TMR_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< USART status register, Address offset: 0x00 */ + __IO uint32_t DT; /*!< USART data register, Address offset: 0x04 */ + __IO uint32_t BAUDR; /*!< USART baud rate register, Address offset: 0x08 */ + __IO uint32_t CTRL1; /*!< USART control register 1, Address offset: 0x0C */ + __IO uint32_t CTRL2; /*!< USART control register 2, Address offset: 0x10 */ + __IO uint32_t CTRL3; /*!< USART control register 3, Address offset: 0x14 */ + __IO uint32_t GDIV; /*!< USART guard time and divider register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CMD; /*!< WDT Command register, Address offset: 0x00 */ + __IO uint32_t DIV; /*!< WDT Divider register, Address offset: 0x04 */ + __IO uint32_t RLD; /*!< WDT Reload register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< WDT Status register, Address offset: 0x0C */ +} WDT_TypeDef; + +/** + * @brief Window WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< WWDT Control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< WWDT Configuration register, Address offset: 0x04 */ + __IO uint32_t STS; /*!< WWDT Status register, Address offset: 0x08 */ +} WWDT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH end address of bank 1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE /*!< APB1 base address */ +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) /*!< APB2 base address */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< AHB base address */ + +#define TMR2_BASE (APB1PERIPH_BASE + 0x00000000U) /*!< TMR2 base address */ +#define TMR3_BASE (APB1PERIPH_BASE + 0x00000400U) /*!< TMR3 base address */ +#define TMR4_BASE (APB1PERIPH_BASE + 0x00000800U) /*!< TMR4 base address */ +#define TMR5_BASE (APB1PERIPH_BASE + 0x00000C00U) /*!< TMR5 base address */ +#define CMP_BASE (APB1PERIPH_BASE + 0x00002400U) /*!< CMP base address */ +#define ERTC_BASE (APB1PERIPH_BASE + 0x00002800U) /*!< ERTC base address */ +#define WWDT_BASE (APB1PERIPH_BASE + 0x00002C00U) /*!< WWDT base address */ +#define WDT_BASE (APB1PERIPH_BASE + 0x00003000U) /*!< WDT base address */ +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) /*!< SPI2 base address */ +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) /*!< USART2 base address */ +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) /*!< USART3 base address */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) /*!< I2C1 base address */ +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ +#define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ +#define IOMUX_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< IOMUX base address */ +#define EXINT_BASE (APB2PERIPH_BASE + 0x00000400U) /*!< EXINT base address */ +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) /*!< GPIOA base address */ +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) /*!< GPIOB base address */ +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) /*!< GPIOC base address */ +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) /*!< GPIOD base address */ +#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U) /*!< GPIOF base address */ +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) /*!< ADC1 base address */ +#define TMR1_BASE (APB2PERIPH_BASE + 0x00002C00U) /*!< TMR1 base address */ +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) /*!< SPI1 base address */ +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< USART1 base address */ +#define TMR9_BASE (APB2PERIPH_BASE + 0x00004C00U) /*!< TMR9 base address */ +#define TMR10_BASE (APB2PERIPH_BASE + 0x00005000U) /*!< TMR10 base address */ +#define TMR11_BASE (APB2PERIPH_BASE + 0x00005400U) /*!< TMR11 base address */ + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) /*!< SDIO base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) /*!< DMA1 base address */ +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) /*!< DMA1 Channel 1 base address */ +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) /*!< DMA1 Channel 2 base address */ +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) /*!< DMA1 Channel 3 base address */ +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) /*!< DMA1 Channel 4 base address */ +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) /*!< DMA1 Channel 5 base address */ +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) /*!< DMA1 Channel 6 base address */ +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) /*!< DMA1 Channel 7 base address */ +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U) /*!< DMA2 base address */ +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U) /*!< DMA2 Channel 1 base address */ +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU) /*!< DMA2 Channel 2 base address */ +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U) /*!< DMA2 Channel 3 base address */ +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U) /*!< DMA2 Channel 4 base address */ +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U) /*!< DMA2 Channel 5 base address */ +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x0000046CU) /*!< DMA2 Channel 6 base address */ +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x00000480U) /*!< DMA2 Channel 7 base address */ +#define CRM_BASE (AHBPERIPH_BASE + 0x00001000U) /*!< CRM base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) /*!< CRC base address */ + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */ +#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */ +#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */ +#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ + +#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB OTG device FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG Peripheral Registers base address */ + +#define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ +#define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U /*!< USB OTG IN Endpoint Registers base address */ +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U /*!< USB OTG OUT Endpoint Registers base address */ +#define USB_OTG_EP_REG_SIZE 0x00000020U /*!< USB OTG All Endpoint Registers size address */ +#define USB_OTG_HOST_BASE 0x00000400U /*!< USB OTG Host Mode Registers base address */ +#define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ +#define USB_OTG_DEP3RMPEN_BASE 0x00000D0CU /*!< USB OTG DEP3RMPEN Registers base address */ +#define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ +#define USB_OTG_USBDIVRST_BASE 0x00000E10U /*!< USB OTG USBDIVRST Registers base address */ +#define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ +#define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CMP ((CMP_TypeDef *)CMP_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR5 ((TMR_TypeDef *)TMR5_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral registers bits definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Power Control (PWC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for PWC_CTRL register *******************/ +#define PWC_CTRL_VRSEL_Pos (0U) +#define PWC_CTRL_VRSEL_Msk (0x1U << PWC_CTRL_VRSEL_Pos) /*!< 0x00000001 */ +#define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ +#define PWC_CTRL_LPSEL_Pos (1U) +#define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep */ +#define PWC_CTRL_CLSWEF_Pos (2U) +#define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ +#define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ +#define PWC_CTRL_CLSEF_Pos (3U) +#define PWC_CTRL_CLSEF_Msk (0x1U << PWC_CTRL_CLSEF_Pos) /*!< 0x00000008 */ +#define PWC_CTRL_CLSEF PWC_CTRL_CLSEF_Msk /*!< Clear SEF flag */ +#define PWC_CTRL_PVMEN_Pos (4U) +#define PWC_CTRL_PVMEN_Msk (0x1U << PWC_CTRL_PVMEN_Pos) /*!< 0x00000010 */ +#define PWC_CTRL_PVMEN PWC_CTRL_PVMEN_Msk /*!< Power voltage monitoring enable */ + +/*!< PVM level configuration */ +#define PWC_CTRL_PVMSEL_Pos (5U) +#define PWC_CTRL_PVMSEL_Msk (0x7U << PWC_CTRL_PVMSEL_Pos) /*!< 0x000000E0 */ +#define PWC_CTRL_PVMSEL PWC_CTRL_PVMSEL_Msk /*!< PVMSEL[2:0] bits (Power voltage monitoring boundary select) */ +#define PWC_CTRL_PVMSEL_0 (0x1U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000020 */ +#define PWC_CTRL_PVMSEL_1 (0x2U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000040 */ +#define PWC_CTRL_PVMSEL_2 (0x4U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000080 */ + +#define PWC_CTRL_PVMSEL_LEV1 0x00000020U /*!< PVM level 2.3V */ +#define PWC_CTRL_PVMSEL_LEV2 0x00000040U /*!< PVM level 2.4V */ +#define PWC_CTRL_PVMSEL_LEV3 0x00000060U /*!< PVM level 2.5V */ +#define PWC_CTRL_PVMSEL_LEV4 0x00000080U /*!< PVM level 2.6V */ +#define PWC_CTRL_PVMSEL_LEV5 0x000000A0U /*!< PVM level 2.7V */ +#define PWC_CTRL_PVMSEL_LEV6 0x000000C0U /*!< PVM level 2.8V */ +#define PWC_CTRL_PVMSEL_LEV7 0x000000E0U /*!< PVM level 2.9V */ + +/* Legacy defines */ +#define PWC_CTRL_PVMSEL_2V3 PWC_CTRL_PVMSEL_LEV1 +#define PWC_CTRL_PVMSEL_2V4 PWC_CTRL_PVMSEL_LEV2 +#define PWC_CTRL_PVMSEL_2V5 PWC_CTRL_PVMSEL_LEV3 +#define PWC_CTRL_PVMSEL_2V6 PWC_CTRL_PVMSEL_LEV4 +#define PWC_CTRL_PVMSEL_2V7 PWC_CTRL_PVMSEL_LEV5 +#define PWC_CTRL_PVMSEL_2V8 PWC_CTRL_PVMSEL_LEV6 +#define PWC_CTRL_PVMSEL_2V9 PWC_CTRL_PVMSEL_LEV7 + +#define PWC_CTRL_BPWEN_Pos (8U) +#define PWC_CTRL_BPWEN_Msk (0x1U << PWC_CTRL_BPWEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRL_BPWEN PWC_CTRL_BPWEN_Msk /*!< Battery powered domain write enable */ + +/***************** Bit definition for PWC_CTRLSTS register ******************/ +#define PWC_CTRLSTS_SWEF_Pos (0U) +#define PWC_CTRLSTS_SWEF_Msk (0x1U << PWC_CTRLSTS_SWEF_Pos) /*!< 0x00000001 */ +#define PWC_CTRLSTS_SWEF PWC_CTRLSTS_SWEF_Msk /*!< Standby wake-up event flag */ +#define PWC_CTRLSTS_SEF_Pos (1U) +#define PWC_CTRLSTS_SEF_Msk (0x1U << PWC_CTRLSTS_SEF_Pos) /*!< 0x00000002 */ +#define PWC_CTRLSTS_SEF PWC_CTRLSTS_SEF_Msk /*!< Standby mode entry flag */ +#define PWC_CTRLSTS_PVMOF_Pos (2U) +#define PWC_CTRLSTS_PVMOF_Msk (0x1U << PWC_CTRLSTS_PVMOF_Pos) /*!< 0x00000004 */ +#define PWC_CTRLSTS_PVMOF PWC_CTRLSTS_PVMOF_Msk /*!< Power voltage monitoring output flag */ +#define PWC_CTRLSTS_SWPEN_Pos (8U) +#define PWC_CTRLSTS_SWPEN_Msk (0x1U << PWC_CTRLSTS_SWPEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRLSTS_SWPEN PWC_CTRLSTS_SWPEN_Msk /*!< Standby wake-up pin enable */ + +/******************************************************************************/ +/* */ +/* Clock and reset manage (CRM) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRM_CTRL register *******************/ +#define CRM_CTRL_HICKEN_Pos (0U) +#define CRM_CTRL_HICKEN_Msk (0x1U << CRM_CTRL_HICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRL_HICKEN CRM_CTRL_HICKEN_Msk /*!< High speed internal clock enable */ +#define CRM_CTRL_HICKSTBL_Pos (1U) +#define CRM_CTRL_HICKSTBL_Msk (0x1U << CRM_CTRL_HICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRL_HICKSTBL CRM_CTRL_HICKSTBL_Msk /*!< High speed internal clock stable */ +#define CRM_CTRL_HICKTRIM_Pos (2U) +#define CRM_CTRL_HICKTRIM_Msk (0x3FU << CRM_CTRL_HICKTRIM_Pos) /*!< 0x000000FC */ +#define CRM_CTRL_HICKTRIM CRM_CTRL_HICKTRIM_Msk /*!< High speed internal clock trimming */ +#define CRM_CTRL_HICKCAL_Pos (8U) +#define CRM_CTRL_HICKCAL_Msk (0xFFU << CRM_CTRL_HICKCAL_Pos) /*!< 0x0000FF00 */ +#define CRM_CTRL_HICKCAL CRM_CTRL_HICKCAL_Msk /*!< High speed internal clock calibration */ +#define CRM_CTRL_HEXTEN_Pos (16U) +#define CRM_CTRL_HEXTEN_Msk (0x1U << CRM_CTRL_HEXTEN_Pos) /*!< 0x00010000 */ +#define CRM_CTRL_HEXTEN CRM_CTRL_HEXTEN_Msk /*!< High speed external crystal enable */ +#define CRM_CTRL_HEXTSTBL_Pos (17U) +#define CRM_CTRL_HEXTSTBL_Msk (0x1U << CRM_CTRL_HEXTSTBL_Pos) /*!< 0x00020000 */ +#define CRM_CTRL_HEXTSTBL CRM_CTRL_HEXTSTBL_Msk /*!< High speed external crystal stable */ +#define CRM_CTRL_HEXTBYPS_Pos (18U) +#define CRM_CTRL_HEXTBYPS_Msk (0x1U << CRM_CTRL_HEXTBYPS_Pos) /*!< 0x00040000 */ +#define CRM_CTRL_HEXTBYPS CRM_CTRL_HEXTBYPS_Msk /*!< High speed external crystal bypass */ +#define CRM_CTRL_CFDEN_Pos (19U) +#define CRM_CTRL_CFDEN_Msk (0x1U << CRM_CTRL_CFDEN_Pos) /*!< 0x00080000 */ +#define CRM_CTRL_CFDEN CRM_CTRL_CFDEN_Msk /*!< Clock failure detector enable */ +#define CRM_CTRL_PLLEN_Pos (24U) +#define CRM_CTRL_PLLEN_Msk (0x1U << CRM_CTRL_PLLEN_Pos) /*!< 0x01000000 */ +#define CRM_CTRL_PLLEN CRM_CTRL_PLLEN_Msk /*!< PLL enable */ +#define CRM_CTRL_PLLSTBL_Pos (25U) +#define CRM_CTRL_PLLSTBL_Msk (0x1U << CRM_CTRL_PLLSTBL_Pos) /*!< 0x02000000 */ +#define CRM_CTRL_PLLSTBL CRM_CTRL_PLLSTBL_Msk /*!< PLL clock stable */ + +/******************* Bit definition for CRM_CFG register ********************/ +/*!< SCLKSEL configuration */ +#define CRM_CFG_SCLKSEL_Pos (0U) +#define CRM_CFG_SCLKSEL_Msk (0x3U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000003 */ +#define CRM_CFG_SCLKSEL CRM_CFG_SCLKSEL_Msk /*!< SCLKSEL[1:0] bits (System clock select) */ +#define CRM_CFG_SCLKSEL_0 (0x1U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000001 */ +#define CRM_CFG_SCLKSEL_1 (0x2U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000002 */ + +#define CRM_CFG_SCLKSEL_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSEL_HEXT 0x00000001U /*!< HEXT */ +#define CRM_CFG_SCLKSEL_PLL 0x00000002U /*!< PLL */ + +/*!< SCLKSTS configuration */ +#define CRM_CFG_SCLKSTS_Pos (2U) +#define CRM_CFG_SCLKSTS_Msk (0x3U << CRM_CFG_SCLKSTS_Pos) /*!< 0x0000000C */ +#define CRM_CFG_SCLKSTS CRM_CFG_SCLKSTS_Msk /*!< SCLKSTS[1:0] bits (System clock select status) */ +#define CRM_CFG_SCLKSTS_0 (0x1U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000004 */ +#define CRM_CFG_SCLKSTS_1 (0x2U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000008 */ + +#define CRM_CFG_SCLKSTS_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSTS_HEXT 0x00000004U /*!< HEXT */ +#define CRM_CFG_SCLKSTS_PLL 0x00000008U /*!< PLL */ + +/*!< AHBDIV configuration */ +#define CRM_CFG_AHBDIV_Pos (4U) +#define CRM_CFG_AHBDIV_Msk (0xFU << CRM_CFG_AHBDIV_Pos) /*!< 0x000000F0 */ +#define CRM_CFG_AHBDIV CRM_CFG_AHBDIV_Msk /*!< AHBDIV[3:0] bits (AHB division) */ +#define CRM_CFG_AHBDIV_0 (0x1U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000010 */ +#define CRM_CFG_AHBDIV_1 (0x2U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000020 */ +#define CRM_CFG_AHBDIV_2 (0x4U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000040 */ +#define CRM_CFG_AHBDIV_3 (0x8U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000080 */ + +#define CRM_CFG_AHBDIV_DIV1 0x00000000U /*!< SCLK is not divided */ +#define CRM_CFG_AHBDIV_DIV2 0x00000080U /*!< SCLK is divided by 2 */ +#define CRM_CFG_AHBDIV_DIV4 0x00000090U /*!< SCLK is divided by 4 */ +#define CRM_CFG_AHBDIV_DIV8 0x000000A0U /*!< SCLK is divided by 8 */ +#define CRM_CFG_AHBDIV_DIV16 0x000000B0U /*!< SCLK is divided by 16 */ +#define CRM_CFG_AHBDIV_DIV64 0x000000C0U /*!< SCLK is divided by 64 */ +#define CRM_CFG_AHBDIV_DIV128 0x000000D0U /*!< SCLK is divided by 128 */ +#define CRM_CFG_AHBDIV_DIV256 0x000000E0U /*!< SCLK is divided by 256 */ +#define CRM_CFG_AHBDIV_DIV512 0x000000F0U /*!< SCLK is divided by 512 */ + +/*!< APB1DIV configuration */ +#define CRM_CFG_APB1DIV_Pos (8U) +#define CRM_CFG_APB1DIV_Msk (0x7U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000700 */ +#define CRM_CFG_APB1DIV CRM_CFG_APB1DIV_Msk /*!< APB1DIV[2:0] bits (APB1 division) */ +#define CRM_CFG_APB1DIV_0 (0x1U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000100 */ +#define CRM_CFG_APB1DIV_1 (0x2U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000200 */ +#define CRM_CFG_APB1DIV_2 (0x4U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000400 */ + +#define CRM_CFG_APB1DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB1DIV_DIV2 0x00000400U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB1DIV_DIV4 0x00000500U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB1DIV_DIV8 0x00000600U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB1DIV_DIV16 0x00000700U /*!< HCLK is divided by 16 */ + +/*!< APB2DIV configuration */ +#define CRM_CFG_APB2DIV_Pos (11U) +#define CRM_CFG_APB2DIV_Msk (0x7U << CRM_CFG_APB2DIV_Pos) /*!< 0x00003800 */ +#define CRM_CFG_APB2DIV CRM_CFG_APB2DIV_Msk /*!< APB2DIV[2:0] bits (APB2 division) */ +#define CRM_CFG_APB2DIV_0 (0x1U << CRM_CFG_APB2DIV_Pos) /*!< 0x00000800 */ +#define CRM_CFG_APB2DIV_1 (0x2U << CRM_CFG_APB2DIV_Pos) /*!< 0x00001000 */ +#define CRM_CFG_APB2DIV_2 (0x4U << CRM_CFG_APB2DIV_Pos) /*!< 0x00002000 */ + +#define CRM_CFG_APB2DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB2DIV_DIV2 0x00002000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB2DIV_DIV4 0x00002800U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB2DIV_DIV8 0x00003000U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB2DIV_DIV16 0x00003800U /*!< HCLK is divided by 16 */ + +/*!< ADCDIV configuration */ +#define CRM_CFG_ADCDIV_Msk ((0x3U << 14) | (0x1U << 28)) /*!< 0x0100C000 */ +#define CRM_CFG_ADCDIV CRM_CFG_ADCDIV_Msk /*!< ADCDIV[2:0] bits (ADC division) */ +#define CRM_CFG_ADCDIV_0 (0x1U << 14) /*!< 0x00004000 */ +#define CRM_CFG_ADCDIV_1 (0x2U << 14) /*!< 0x00008000 */ +#define CRM_CFG_ADCDIV_2 (0x1U << 28) /*!< 0x10000000 */ + +#define CRM_CFG_ADCDIV_DIV2 0x00000000U /*!< PCLK/2 */ +#define CRM_CFG_ADCDIV_DIV4 0x00004000U /*!< PCLK/4 */ +#define CRM_CFG_ADCDIV_DIV6 0x00008000U /*!< PCLK/6 */ +#define CRM_CFG_ADCDIV_DIV8 0x0000C000U /*!< PCLK/8 */ +#define CRM_CFG_ADCDIV_DIV12 0x10004000U /*!< PCLK2/12 */ +#define CRM_CFG_ADCDIV_DIV16 0x1000C000U /*!< PCLK2/16 */ + +#define CRM_CFG_PLLRCS_Pos (16U) +#define CRM_CFG_PLLRCS_Msk (0x1U << CRM_CFG_PLLRCS_Pos) /*!< 0x00010000 */ +#define CRM_CFG_PLLRCS CRM_CFG_PLLRCS_Msk /*!< PLL entry clock select */ + +#define CRM_CFG_PLLHEXTDIV_Pos (17U) +#define CRM_CFG_PLLHEXTDIV_Msk (0x1U << CRM_CFG_PLLHEXTDIV_Pos) /*!< 0x00020000 */ +#define CRM_CFG_PLLHEXTDIV CRM_CFG_PLLHEXTDIV_Msk /*!< HEXT division selection for PLL entry clock */ + +/*!< PLLMULT configuration */ +#define CRM_CFG_PLLMULT_Msk ((0xFU << 18) | (0x3U << 29)) /*!< 0x603C0000 */ +#define CRM_CFG_PLLMULT CRM_CFG_PLLMULT_Msk /*!< PLLMULT[5:0] bits (PLL multiplication factor) */ +#define CRM_CFG_PLLMULT_0 (0x1U << 18) /*!< 0x00040000 */ +#define CRM_CFG_PLLMULT_1 (0x2U << 18) /*!< 0x00080000 */ +#define CRM_CFG_PLLMULT_2 (0x4U << 18) /*!< 0x00100000 */ +#define CRM_CFG_PLLMULT_3 (0x8U << 18) /*!< 0x00200000 */ +#define CRM_CFG_PLLMULT_4 (0x1U << 29) /*!< 0x20000000 */ +#define CRM_CFG_PLLMULT_5 (0x2U << 29) /*!< 0x40000000 */ + +#define CRM_CFG_PLLMULT_MULT2 0x00000000U /*!< PLL input clock * 2 */ +#define CRM_CFG_PLLMULT_MULT3_Pos (18U) +#define CRM_CFG_PLLMULT_MULT3_Msk (0x1U << CRM_CFG_PLLMULT_MULT3_Pos) /*!< 0x00040000 */ +#define CRM_CFG_PLLMULT_MULT3 CRM_CFG_PLLMULT_MULT3_Msk /*!< PLL input clock * 3 */ +#define CRM_CFG_PLLMULT_MULT4_Pos (19U) +#define CRM_CFG_PLLMULT_MULT4_Msk (0x1U << CRM_CFG_PLLMULT_MULT4_Pos) /*!< 0x00080000 */ +#define CRM_CFG_PLLMULT_MULT4 CRM_CFG_PLLMULT_MULT4_Msk /*!< PLL input clock * 4 */ +#define CRM_CFG_PLLMULT_MULT5_Pos (18U) +#define CRM_CFG_PLLMULT_MULT5_Msk (0x3U << CRM_CFG_PLLMULT_MULT5_Pos) /*!< 0x000C0000 */ +#define CRM_CFG_PLLMULT_MULT5 CRM_CFG_PLLMULT_MULT5_Msk /*!< PLL input clock * 5 */ +#define CRM_CFG_PLLMULT_MULT6_Pos (20U) +#define CRM_CFG_PLLMULT_MULT6_Msk (0x1U << CRM_CFG_PLLMULT_MULT6_Pos) /*!< 0x00100000 */ +#define CRM_CFG_PLLMULT_MULT6 CRM_CFG_PLLMULT_MULT6_Msk /*!< PLL input clock * 6 */ +#define CRM_CFG_PLLMULT_MULT7_Pos (18U) +#define CRM_CFG_PLLMULT_MULT7_Msk (0x5U << CRM_CFG_PLLMULT_MULT7_Pos) /*!< 0x00140000 */ +#define CRM_CFG_PLLMULT_MULT7 CRM_CFG_PLLMULT_MULT7_Msk /*!< PLL input clock * 7 */ +#define CRM_CFG_PLLMULT_MULT8_Pos (19U) +#define CRM_CFG_PLLMULT_MULT8_Msk (0x3U << CRM_CFG_PLLMULT_MULT8_Pos) /*!< 0x00180000 */ +#define CRM_CFG_PLLMULT_MULT8 CRM_CFG_PLLMULT_MULT8_Msk /*!< PLL input clock * 8 */ +#define CRM_CFG_PLLMULT_MULT9_Pos (18U) +#define CRM_CFG_PLLMULT_MULT9_Msk (0x7U << CRM_CFG_PLLMULT_MULT9_Pos) /*!< 0x001C0000 */ +#define CRM_CFG_PLLMULT_MULT9 CRM_CFG_PLLMULT_MULT9_Msk /*!< PLL input clock * 9 */ +#define CRM_CFG_PLLMULT_MULT10_Pos (21U) +#define CRM_CFG_PLLMULT_MULT10_Msk (0x1U << CRM_CFG_PLLMULT_MULT10_Pos) /*!< 0x00200000 */ +#define CRM_CFG_PLLMULT_MULT10 CRM_CFG_PLLMULT_MULT10_Msk /*!< PLL input clock * 10 */ +#define CRM_CFG_PLLMULT_MULT11_Pos (18U) +#define CRM_CFG_PLLMULT_MULT11_Msk (0x9U << CRM_CFG_PLLMULT_MULT11_Pos) /*!< 0x00240000 */ +#define CRM_CFG_PLLMULT_MULT11 CRM_CFG_PLLMULT_MULT11_Msk /*!< PLL input clock * 11 */ +#define CRM_CFG_PLLMULT_MULT12_Pos (19U) +#define CRM_CFG_PLLMULT_MULT12_Msk (0x5U << CRM_CFG_PLLMULT_MULT12_Pos) /*!< 0x00280000 */ +#define CRM_CFG_PLLMULT_MULT12 CRM_CFG_PLLMULT_MULT12_Msk /*!< PLL input clock * 12 */ +#define CRM_CFG_PLLMULT_MULT13_Pos (18U) +#define CRM_CFG_PLLMULT_MULT13_Msk (0xBU << CRM_CFG_PLLMULT_MULT13_Pos) /*!< 0x002C0000 */ +#define CRM_CFG_PLLMULT_MULT13 CRM_CFG_PLLMULT_MULT13_Msk /*!< PLL input clock * 13 */ +#define CRM_CFG_PLLMULT_MULT14_Pos (20U) +#define CRM_CFG_PLLMULT_MULT14_Msk (0x3U << CRM_CFG_PLLMULT_MULT14_Pos) /*!< 0x00300000 */ +#define CRM_CFG_PLLMULT_MULT14 CRM_CFG_PLLMULT_MULT14_Msk /*!< PLL input clock * 14 */ +#define CRM_CFG_PLLMULT_MULT15_Pos (18U) +#define CRM_CFG_PLLMULT_MULT15_Msk (0xDU << CRM_CFG_PLLMULT_MULT15_Pos) /*!< 0x00340000 */ +#define CRM_CFG_PLLMULT_MULT15 CRM_CFG_PLLMULT_MULT15_Msk /*!< PLL input clock * 15 */ +#define CRM_CFG_PLLMULT_MULT16_Pos (19U) +#define CRM_CFG_PLLMULT_MULT16_Msk (0x7U << CRM_CFG_PLLMULT_MULT16_Pos) /*!< 0x00380000 */ +#define CRM_CFG_PLLMULT_MULT16 CRM_CFG_PLLMULT_MULT16_Msk /*!< PLL input clock * 16 */ +#define CRM_CFG_PLLMULT_MULT17 0x20000000U /*!< PLL input clock * 17 */ +#define CRM_CFG_PLLMULT_MULT18 0x20040000U /*!< PLL input clock * 18 */ +#define CRM_CFG_PLLMULT_MULT19 0x20080000U /*!< PLL input clock * 19 */ +#define CRM_CFG_PLLMULT_MULT20 0x200C0000U /*!< PLL input clock * 20 */ +#define CRM_CFG_PLLMULT_MULT21 0x20100000U /*!< PLL input clock * 21 */ +#define CRM_CFG_PLLMULT_MULT22 0x20140000U /*!< PLL input clock * 22 */ +#define CRM_CFG_PLLMULT_MULT23 0x20180000U /*!< PLL input clock * 23 */ +#define CRM_CFG_PLLMULT_MULT24 0x201C0000U /*!< PLL input clock * 24 */ +#define CRM_CFG_PLLMULT_MULT25 0x20200000U /*!< PLL input clock * 25 */ +#define CRM_CFG_PLLMULT_MULT26 0x20240000U /*!< PLL input clock * 26 */ +#define CRM_CFG_PLLMULT_MULT27 0x20280000U /*!< PLL input clock * 27 */ +#define CRM_CFG_PLLMULT_MULT28 0x202C0000U /*!< PLL input clock * 28 */ +#define CRM_CFG_PLLMULT_MULT29 0x20300000U /*!< PLL input clock * 29 */ +#define CRM_CFG_PLLMULT_MULT30 0x20340000U /*!< PLL input clock * 30 */ +#define CRM_CFG_PLLMULT_MULT31 0x20380000U /*!< PLL input clock * 31 */ +#define CRM_CFG_PLLMULT_MULT32 0x203C0000U /*!< PLL input clock * 32 */ +#define CRM_CFG_PLLMULT_MULT33 0x40000000U /*!< PLL input clock * 33 */ +#define CRM_CFG_PLLMULT_MULT34 0x40040000U /*!< PLL input clock * 34 */ +#define CRM_CFG_PLLMULT_MULT35 0x40080000U /*!< PLL input clock * 35 */ +#define CRM_CFG_PLLMULT_MULT36 0x400C0000U /*!< PLL input clock * 36 */ +#define CRM_CFG_PLLMULT_MULT37 0x40100000U /*!< PLL input clock * 37 */ +#define CRM_CFG_PLLMULT_MULT38 0x40140000U /*!< PLL input clock * 38 */ +#define CRM_CFG_PLLMULT_MULT39 0x40180000U /*!< PLL input clock * 39 */ +#define CRM_CFG_PLLMULT_MULT40 0x401C0000U /*!< PLL input clock * 40 */ +#define CRM_CFG_PLLMULT_MULT41 0x40200000U /*!< PLL input clock * 41 */ +#define CRM_CFG_PLLMULT_MULT42 0x40240000U /*!< PLL input clock * 42 */ +#define CRM_CFG_PLLMULT_MULT43 0x40280000U /*!< PLL input clock * 43 */ +#define CRM_CFG_PLLMULT_MULT44 0x402C0000U /*!< PLL input clock * 44 */ +#define CRM_CFG_PLLMULT_MULT45 0x40300000U /*!< PLL input clock * 45 */ +#define CRM_CFG_PLLMULT_MULT46 0x40340000U /*!< PLL input clock * 46 */ +#define CRM_CFG_PLLMULT_MULT47 0x40380000U /*!< PLL input clock * 47 */ +#define CRM_CFG_PLLMULT_MULT48 0x403C0000U /*!< PLL input clock * 48 */ +#define CRM_CFG_PLLMULT_MULT49 0x60000000U /*!< PLL input clock * 49 */ +#define CRM_CFG_PLLMULT_MULT50 0x60040000U /*!< PLL input clock * 50 */ +#define CRM_CFG_PLLMULT_MULT51 0x60080000U /*!< PLL input clock * 51 */ +#define CRM_CFG_PLLMULT_MULT52 0x600C0000U /*!< PLL input clock * 52 */ +#define CRM_CFG_PLLMULT_MULT53 0x60100000U /*!< PLL input clock * 53 */ +#define CRM_CFG_PLLMULT_MULT54 0x60140000U /*!< PLL input clock * 54 */ +#define CRM_CFG_PLLMULT_MULT55 0x60180000U /*!< PLL input clock * 55 */ +#define CRM_CFG_PLLMULT_MULT56 0x601C0000U /*!< PLL input clock * 56 */ +#define CRM_CFG_PLLMULT_MULT57 0x60200000U /*!< PLL input clock * 57 */ +#define CRM_CFG_PLLMULT_MULT58 0x60240000U /*!< PLL input clock * 58 */ +#define CRM_CFG_PLLMULT_MULT59 0x60280000U /*!< PLL input clock * 59 */ +#define CRM_CFG_PLLMULT_MULT60 0x602C0000U /*!< PLL input clock * 60 */ +#define CRM_CFG_PLLMULT_MULT61 0x60300000U /*!< PLL input clock * 61 */ +#define CRM_CFG_PLLMULT_MULT62 0x60340000U /*!< PLL input clock * 62 */ +#define CRM_CFG_PLLMULT_MULT63 0x60380000U /*!< PLL input clock * 63 */ +#define CRM_CFG_PLLMULT_MULT64 0x603C0000U /*!< PLL input clock * 64 */ + +/*!< USBDIV configuration */ +#define CRM_CFG_USBDIV_Msk ((0x3U << 22) | (0x1U << 27)) /*!< 0x08C00000 */ +#define CRM_CFG_USBDIV CRM_CFG_USBDIV_Msk /*!< USBDIV[2:0] bits (USB division factor) */ +#define CRM_CFG_USBDIV_0 (0x1U << 22) /*!< 0x00400000 */ +#define CRM_CFG_USBDIV_1 (0x2U << 22) /*!< 0x00800000 */ +#define CRM_CFG_USBDIV_2 (0x1U << 27) /*!< 0x08000000 */ + +#define CRM_CFG_USBDIV_DIV1_5 0x00000000U /*!< PLL/1.5 */ +#define CRM_CFG_USBDIV_DIV1 0x00400000U /*!< PLL/1 */ +#define CRM_CFG_USBDIV_DIV2_5 0x00800000U /*!< PLL/2.5 */ +#define CRM_CFG_USBDIV_DIV2 0x00C00000U /*!< PLL/2 */ +#define CRM_CFG_USBDIV_DIV3_5 0x08000000U /*!< PLL/3.5 */ +#define CRM_CFG_USBDIV_DIV3 0x08400000U /*!< PLL/3 */ +#define CRM_CFG_USBDIV_DIV4 0x08800000U /*!< PLL/4 */ + +/*!< CLKOUT_SEL configuration */ +#define CRM_CFG_CLKOUT_SEL_Msk ((CRM_MISC1_CLKOUT_SEL) | (0x7U << 24)) /*!< 0x07010000 */ +#define CRM_CFG_CLKOUT_SEL CRM_CFG_CLKOUT_SEL_Msk /*!< CLKOUT_SEL[3:0] bits (Clock output selection) */ +#define CRM_CFG_CLKOUT_SEL_0 (0x1U << 24) /*!< 0x01000000 */ +#define CRM_CFG_CLKOUT_SEL_1 (0x2U << 24) /*!< 0x02000000 */ +#define CRM_CFG_CLKOUT_SEL_2 (0x4U << 24) /*!< 0x04000000 */ +#define CRM_CFG_CLKOUT_SEL_3 CRM_MISC1_CLKOUT_SEL /*!< 0x00010000 */ + +#define CRM_CFG_CLKOUT_SEL_NOCLOCK 0x00000000U /*!< Not clock output */ +#define CRM_CFG_CLKOUT_SEL_LICK 0x02000000U /*!< LICK */ +#define CRM_CFG_CLKOUT_SEL_LEXT 0x03000000U /*!< LEXT */ +#define CRM_CFG_CLKOUT_SEL_SCLK 0x04000000U /*!< SCLK */ +#define CRM_CFG_CLKOUT_SEL_HICK 0x05000000U /*!< HICK */ +#define CRM_CFG_CLKOUT_SEL_HEXT 0x06000000U /*!< HEXT */ +#define CRM_CFG_CLKOUT_SEL_PLL_DIV2 0x07000000U /*!< PLL/2 */ +#define CRM_MISC1_CLKOUT_SEL_PLL_DIV4 0x04010000U /*!< PLL/4 */ +#define CRM_MISC1_CLKOUT_SEL_USB 0x05010000U /*!< USB */ +#define CRM_MISC1_CLKOUT_SEL_ADC 0x06010000U /*!< ADC */ + +/* Reference defines */ +#define CRM_CFG_CLKSEL CRM_CFG_CLKOUT_SEL +#define CRM_CFG_CLKSEL_0 CRM_CFG_CLKOUT_SEL_0 +#define CRM_CFG_CLKSEL_1 CRM_CFG_CLKOUT_SEL_1 +#define CRM_CFG_CLKSEL_2 CRM_CFG_CLKOUT_SEL_2 +#define CRM_CFG_CLKSEL_NOCLOCK CRM_CFG_CLKOUT_SEL_NOCLOCK +#define CRM_CFG_CLKSEL_LICK CRM_CFG_CLKOUT_SEL_LICK +#define CRM_CFG_CLKSEL_LEXT CRM_CFG_CLKOUT_SEL_LEXT +#define CRM_CFG_CLKSEL_SCLK CRM_CFG_CLKOUT_SEL_SCLK +#define CRM_CFG_CLKSEL_HICK CRM_CFG_CLKOUT_SEL_HICK +#define CRM_CFG_CLKSEL_HEXT CRM_CFG_CLKOUT_SEL_HEXT +#define CRM_CFG_CLKSEL_PLL_DIV2 CRM_CFG_CLKOUT_SEL_PLL_DIV2 +#define CRM_MISC1_CLKSEL_PLL_DIV4 CRM_MISC1_CLKOUT_SEL_PLL_DIV4 +#define CRM_MISC1_CLKSEL_USB CRM_MISC1_CLKOUT_SEL_USB +#define CRM_MISC1_CLKSEL_ADC CRM_MISC1_CLKOUT_SEL_ADC + +/*!<*************** Bit definition for CRM_CLKINT register ******************/ +#define CRM_CLKINT_LICKSTBLF_Pos (0U) +#define CRM_CLKINT_LICKSTBLF_Msk (0x1U << CRM_CLKINT_LICKSTBLF_Pos) /*!< 0x00000001 */ +#define CRM_CLKINT_LICKSTBLF CRM_CLKINT_LICKSTBLF_Msk /*!< LICK stable interrupt flag */ +#define CRM_CLKINT_LEXTSTBLF_Pos (1U) +#define CRM_CLKINT_LEXTSTBLF_Msk (0x1U << CRM_CLKINT_LEXTSTBLF_Pos) /*!< 0x00000002 */ +#define CRM_CLKINT_LEXTSTBLF CRM_CLKINT_LEXTSTBLF_Msk /*!< LEXT stable flag */ +#define CRM_CLKINT_HICKSTBLF_Pos (2U) +#define CRM_CLKINT_HICKSTBLF_Msk (0x1U << CRM_CLKINT_HICKSTBLF_Pos) /*!< 0x00000004 */ +#define CRM_CLKINT_HICKSTBLF CRM_CLKINT_HICKSTBLF_Msk /*!< HICK stable flag */ +#define CRM_CLKINT_HEXTSTBLF_Pos (3U) +#define CRM_CLKINT_HEXTSTBLF_Msk (0x1U << CRM_CLKINT_HEXTSTBLF_Pos) /*!< 0x00000008 */ +#define CRM_CLKINT_HEXTSTBLF CRM_CLKINT_HEXTSTBLF_Msk /*!< HEXT stable flag */ +#define CRM_CLKINT_PLLSTBLF_Pos (4U) +#define CRM_CLKINT_PLLSTBLF_Msk (0x1U << CRM_CLKINT_PLLSTBLF_Pos) /*!< 0x00000010 */ +#define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ +#define CRM_CLKINT_CFDF_Pos (7U) +#define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock Failure Detection flag */ +#define CRM_CLKINT_LICKSTBLIEN_Pos (8U) +#define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ +#define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ +#define CRM_CLKINT_LEXTSTBLIEN_Pos (9U) +#define CRM_CLKINT_LEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_LEXTSTBLIEN_Pos) /*!< 0x00000200 */ +#define CRM_CLKINT_LEXTSTBLIEN CRM_CLKINT_LEXTSTBLIEN_Msk /*!< LEXT stable interrupt enable */ +#define CRM_CLKINT_HICKSTBLIEN_Pos (10U) +#define CRM_CLKINT_HICKSTBLIEN_Msk (0x1U << CRM_CLKINT_HICKSTBLIEN_Pos) /*!< 0x00000400 */ +#define CRM_CLKINT_HICKSTBLIEN CRM_CLKINT_HICKSTBLIEN_Msk /*!< HICK stable interrupt enable */ +#define CRM_CLKINT_HEXTSTBLIEN_Pos (11U) +#define CRM_CLKINT_HEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_HEXTSTBLIEN_Pos) /*!< 0x00000800 */ +#define CRM_CLKINT_HEXTSTBLIEN CRM_CLKINT_HEXTSTBLIEN_Msk /*!< HEXT stable interrupt enable */ +#define CRM_CLKINT_PLLSTBLIEN_Pos (12U) +#define CRM_CLKINT_PLLSTBLIEN_Msk (0x1U << CRM_CLKINT_PLLSTBLIEN_Pos) /*!< 0x00001000 */ +#define CRM_CLKINT_PLLSTBLIEN CRM_CLKINT_PLLSTBLIEN_Msk /*!< PLL stable interrupt enable */ +#define CRM_CLKINT_LICKSTBLFC_Pos (16U) +#define CRM_CLKINT_LICKSTBLFC_Msk (0x1U << CRM_CLKINT_LICKSTBLFC_Pos) /*!< 0x00010000 */ +#define CRM_CLKINT_LICKSTBLFC CRM_CLKINT_LICKSTBLFC_Msk /*!< LICK stable flag clear */ +#define CRM_CLKINT_LEXTSTBLFC_Pos (17U) +#define CRM_CLKINT_LEXTSTBLFC_Msk (0x1U << CRM_CLKINT_LEXTSTBLFC_Pos) /*!< 0x00020000 */ +#define CRM_CLKINT_LEXTSTBLFC CRM_CLKINT_LEXTSTBLFC_Msk /*!< LEXT stable flag clear */ +#define CRM_CLKINT_HICKSTBLFC_Pos (18U) +#define CRM_CLKINT_HICKSTBLFC_Msk (0x1U << CRM_CLKINT_HICKSTBLFC_Pos) /*!< 0x00040000 */ +#define CRM_CLKINT_HICKSTBLFC CRM_CLKINT_HICKSTBLFC_Msk /*!< HICK stable flag clear */ +#define CRM_CLKINT_HEXTSTBLFC_Pos (19U) +#define CRM_CLKINT_HEXTSTBLFC_Msk (0x1U << CRM_CLKINT_HEXTSTBLFC_Pos) /*!< 0x00080000 */ +#define CRM_CLKINT_HEXTSTBLFC CRM_CLKINT_HEXTSTBLFC_Msk /*!< HEXT stable flag clear */ +#define CRM_CLKINT_PLLSTBLFC_Pos (20U) +#define CRM_CLKINT_PLLSTBLFC_Msk (0x1U << CRM_CLKINT_PLLSTBLFC_Pos) /*!< 0x00100000 */ +#define CRM_CLKINT_PLLSTBLFC CRM_CLKINT_PLLSTBLFC_Msk /*!< PLL stable flag clear */ +#define CRM_CLKINT_CFDFC_Pos (23U) +#define CRM_CLKINT_CFDFC_Msk (0x1U << CRM_CLKINT_CFDFC_Pos) /*!< 0x00800000 */ +#define CRM_CLKINT_CFDFC CRM_CLKINT_CFDFC_Msk /*!< Clock failure detection flag clear */ + +/***************** Bit definition for CRM_APB2RST register ******************/ +#define CRM_APB2RST_IOMUXRST_Pos (0U) +#define CRM_APB2RST_IOMUXRST_Msk (0x1U << CRM_APB2RST_IOMUXRST_Pos) /*!< 0x00000001 */ +#define CRM_APB2RST_IOMUXRST CRM_APB2RST_IOMUXRST_Msk /*!< IOMUX reset */ +#define CRM_APB2RST_EXINTRST_Pos (1U) +#define CRM_APB2RST_EXINTRST_Msk (0x1U << CRM_APB2RST_EXINTRST_Pos) /*!< 0x00000002 */ +#define CRM_APB2RST_EXINTRST CRM_APB2RST_EXINTRST_Msk /*!< EXINT reset */ +#define CRM_APB2RST_GPIOARST_Pos (2U) +#define CRM_APB2RST_GPIOARST_Msk (0x1U << CRM_APB2RST_GPIOARST_Pos) /*!< 0x00000004 */ +#define CRM_APB2RST_GPIOARST CRM_APB2RST_GPIOARST_Msk /*!< GPIOA reset */ +#define CRM_APB2RST_GPIOBRST_Pos (3U) +#define CRM_APB2RST_GPIOBRST_Msk (0x1U << CRM_APB2RST_GPIOBRST_Pos) /*!< 0x00000008 */ +#define CRM_APB2RST_GPIOBRST CRM_APB2RST_GPIOBRST_Msk /*!< GPIOB reset */ +#define CRM_APB2RST_GPIOCRST_Pos (4U) +#define CRM_APB2RST_GPIOCRST_Msk (0x1U << CRM_APB2RST_GPIOCRST_Pos) /*!< 0x00000010 */ +#define CRM_APB2RST_GPIOCRST CRM_APB2RST_GPIOCRST_Msk /*!< GPIOC reset */ +#define CRM_APB2RST_GPIODRST_Pos (5U) +#define CRM_APB2RST_GPIODRST_Msk (0x1U << CRM_APB2RST_GPIODRST_Pos) /*!< 0x00000020 */ +#define CRM_APB2RST_GPIODRST CRM_APB2RST_GPIODRST_Msk /*!< GPIOD reset */ +#define CRM_APB2RST_GPIOFRST_Pos (7U) +#define CRM_APB2RST_GPIOFRST_Msk (0x1U << CRM_APB2RST_GPIOFRST_Pos) /*!< 0x00000080 */ +#define CRM_APB2RST_GPIOFRST CRM_APB2RST_GPIOFRST_Msk /*!< GPIOF reset */ +#define CRM_APB2RST_ADC1RST_Pos (9U) +#define CRM_APB2RST_ADC1RST_Msk (0x1U << CRM_APB2RST_ADC1RST_Pos) /*!< 0x00000200 */ +#define CRM_APB2RST_ADC1RST CRM_APB2RST_ADC1RST_Msk /*!< ADC1 reset */ +#define CRM_APB2RST_TMR1RST_Pos (11U) +#define CRM_APB2RST_TMR1RST_Msk (0x1U << CRM_APB2RST_TMR1RST_Pos) /*!< 0x00000800 */ +#define CRM_APB2RST_TMR1RST CRM_APB2RST_TMR1RST_Msk /*!< TMR1 reset */ +#define CRM_APB2RST_SPI1RST_Pos (12U) +#define CRM_APB2RST_SPI1RST_Msk (0x1U << CRM_APB2RST_SPI1RST_Pos) /*!< 0x00001000 */ +#define CRM_APB2RST_SPI1RST CRM_APB2RST_SPI1RST_Msk /*!< SPI1 reset */ +#define CRM_APB2RST_USART1RST_Pos (14U) +#define CRM_APB2RST_USART1RST_Msk (0x1U << CRM_APB2RST_USART1RST_Pos) /*!< 0x00004000 */ +#define CRM_APB2RST_USART1RST CRM_APB2RST_USART1RST_Msk /*!< USART1 reset */ +#define CRM_APB2RST_TMR9RST_Pos (19U) +#define CRM_APB2RST_TMR9RST_Msk (0x1U << CRM_APB2RST_TMR9RST_Pos) /*!< 0x00080000 */ +#define CRM_APB2RST_TMR9RST CRM_APB2RST_TMR9RST_Msk /*!< TMR9 reset */ +#define CRM_APB2RST_TMR10RST_Pos (20U) +#define CRM_APB2RST_TMR10RST_Msk (0x1U << CRM_APB2RST_TMR10RST_Pos) /*!< 0x00100000 */ +#define CRM_APB2RST_TMR10RST CRM_APB2RST_TMR10RST_Msk /*!< TMR10 reset */ +#define CRM_APB2RST_TMR11RST_Pos (21U) +#define CRM_APB2RST_TMR11RST_Msk (0x1U << CRM_APB2RST_TMR11RST_Pos) /*!< 0x00200000 */ +#define CRM_APB2RST_TMR11RST CRM_APB2RST_TMR11RST_Msk /*!< TMR11 reset */ + +/***************** Bit definition for CRM_APB1RST register ******************/ +#define CRM_APB1RST_TMR2RST_Pos (0U) +#define CRM_APB1RST_TMR2RST_Msk (0x1U << CRM_APB1RST_TMR2RST_Pos) /*!< 0x00000001 */ +#define CRM_APB1RST_TMR2RST CRM_APB1RST_TMR2RST_Msk /*!< TMR2 reset */ +#define CRM_APB1RST_TMR3RST_Pos (1U) +#define CRM_APB1RST_TMR3RST_Msk (0x1U << CRM_APB1RST_TMR3RST_Pos) /*!< 0x00000002 */ +#define CRM_APB1RST_TMR3RST CRM_APB1RST_TMR3RST_Msk /*!< TMR3 reset */ +#define CRM_APB1RST_TMR4RST_Pos (2U) +#define CRM_APB1RST_TMR4RST_Msk (0x1U << CRM_APB1RST_TMR4RST_Pos) /*!< 0x00000004 */ +#define CRM_APB1RST_TMR4RST CRM_APB1RST_TMR4RST_Msk /*!< TMR4 reset */ +#define CRM_APB1RST_TMR5RST_Pos (3U) +#define CRM_APB1RST_TMR5RST_Msk (0x1U << CRM_APB1RST_TMR5RST_Pos) /*!< 0x00000008 */ +#define CRM_APB1RST_TMR5RST CRM_APB1RST_TMR5RST_Msk /*!< TMR5 reset */ +#define CRM_APB1RST_CMPRST_Pos (9U) +#define CRM_APB1RST_CMPRST_Msk (0x1U << CRM_APB1RST_CMPRST_Pos) /*!< 0x00000200 */ +#define CRM_APB1RST_CMPRST CRM_APB1RST_CMPRST_Msk /*!< CMP reset */ +#define CRM_APB1RST_WWDTRST_Pos (11U) +#define CRM_APB1RST_WWDTRST_Msk (0x1U << CRM_APB1RST_WWDTRST_Pos) /*!< 0x00000800 */ +#define CRM_APB1RST_WWDTRST CRM_APB1RST_WWDTRST_Msk /*!< WWDT reset */ +#define CRM_APB1RST_SPI2RST_Pos (14U) +#define CRM_APB1RST_SPI2RST_Msk (0x1U << CRM_APB1RST_SPI2RST_Pos) /*!< 0x00004000 */ +#define CRM_APB1RST_SPI2RST CRM_APB1RST_SPI2RST_Msk /*!< SPI2 reset */ +#define CRM_APB1RST_USART2RST_Pos (17U) +#define CRM_APB1RST_USART2RST_Msk (0x1U << CRM_APB1RST_USART2RST_Pos) /*!< 0x00020000 */ +#define CRM_APB1RST_USART2RST CRM_APB1RST_USART2RST_Msk /*!< USART2 reset */ +#define CRM_APB1RST_USART3RST_Pos (18U) +#define CRM_APB1RST_USART3RST_Msk (0x1U << CRM_APB1RST_USART3RST_Pos) /*!< 0x00040000 */ +#define CRM_APB1RST_USART3RST CRM_APB1RST_USART3RST_Msk /*!< USART3 reset */ +#define CRM_APB1RST_I2C1RST_Pos (21U) +#define CRM_APB1RST_I2C1RST_Msk (0x1U << CRM_APB1RST_I2C1RST_Pos) /*!< 0x00200000 */ +#define CRM_APB1RST_I2C1RST CRM_APB1RST_I2C1RST_Msk /*!< I2C1 reset */ +#define CRM_APB1RST_I2C2RST_Pos (22U) +#define CRM_APB1RST_I2C2RST_Msk (0x1U << CRM_APB1RST_I2C2RST_Pos) /*!< 0x00400000 */ +#define CRM_APB1RST_I2C2RST CRM_APB1RST_I2C2RST_Msk /*!< I2C2 reset */ +#define CRM_APB1RST_CAN1RST_Pos (25U) +#define CRM_APB1RST_CAN1RST_Msk (0x1U << CRM_APB1RST_CAN1RST_Pos) /*!< 0x02000000 */ +#define CRM_APB1RST_CAN1RST CRM_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ +#define CRM_APB1RST_PWCRST_Pos (28U) +#define CRM_APB1RST_PWCRST_Msk (0x1U << CRM_APB1RST_PWCRST_Pos) /*!< 0x10000000 */ +#define CRM_APB1RST_PWCRST CRM_APB1RST_PWCRST_Msk /*!< PWC reset */ + +/****************** Bit definition for CRM_AHBEN register *******************/ +#define CRM_AHBEN_DMA1EN_Pos (0U) +#define CRM_AHBEN_DMA1EN_Msk (0x1U << CRM_AHBEN_DMA1EN_Pos) /*!< 0x00000001 */ +#define CRM_AHBEN_DMA1EN CRM_AHBEN_DMA1EN_Msk /*!< DMA1 clock enable */ +#define CRM_AHBEN_DMA2EN_Pos (1U) +#define CRM_AHBEN_DMA2EN_Msk (0x1U << CRM_AHBEN_DMA2EN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN_DMA2EN CRM_AHBEN_DMA2EN_Msk /*!< DMA2 clock enable */ +#define CRM_AHBEN_SRAMEN_Pos (2U) +#define CRM_AHBEN_SRAMEN_Msk (0x1U << CRM_AHBEN_SRAMEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBEN_SRAMEN CRM_AHBEN_SRAMEN_Msk /*!< SRAM clock enable */ +#define CRM_AHBEN_FLASHEN_Pos (4U) +#define CRM_AHBEN_FLASHEN_Msk (0x1U << CRM_AHBEN_FLASHEN_Pos) /*!< 0x00000010 */ +#define CRM_AHBEN_FLASHEN CRM_AHBEN_FLASHEN_Msk /*!< Flash clock enable */ +#define CRM_AHBEN_CRCEN_Pos (6U) +#define CRM_AHBEN_CRCEN_Msk (0x1U << CRM_AHBEN_CRCEN_Pos) /*!< 0x00000040 */ +#define CRM_AHBEN_CRCEN CRM_AHBEN_CRCEN_Msk /*!< CRC clock enable */ +#define CRM_AHBEN_SDIOEN_Pos (10U) +#define CRM_AHBEN_SDIOEN_Msk (0x1U << CRM_AHBEN_SDIOEN_Pos) /*!< 0x00000400 */ +#define CRM_AHBEN_SDIOEN CRM_AHBEN_SDIOEN_Msk /*!< SDIO clock enable */ +#define CRM_AHBEN_OTGFSEN_Pos (12U) +#define CRM_AHBEN_OTGFSEN_Msk (0x1U << CRM_AHBEN_OTGFSEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBEN_OTGFSEN CRM_AHBEN_OTGFSEN_Msk /*!< OTGFS clock enable */ + +/****************** Bit definition for CRM_APB2EN register ******************/ +#define CRM_APB2EN_IOMUXEN_Pos (0U) +#define CRM_APB2EN_IOMUXEN_Msk (0x1U << CRM_APB2EN_IOMUXEN_Pos) /*!< 0x00000001 */ +#define CRM_APB2EN_IOMUXEN CRM_APB2EN_IOMUXEN_Msk /*!< IOMUX clock enable */ +#define CRM_APB2EN_GPIOAEN_Pos (2U) +#define CRM_APB2EN_GPIOAEN_Msk (0x1U << CRM_APB2EN_GPIOAEN_Pos) /*!< 0x00000004 */ +#define CRM_APB2EN_GPIOAEN CRM_APB2EN_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define CRM_APB2EN_GPIOBEN_Pos (3U) +#define CRM_APB2EN_GPIOBEN_Msk (0x1U << CRM_APB2EN_GPIOBEN_Pos) /*!< 0x00000008 */ +#define CRM_APB2EN_GPIOBEN CRM_APB2EN_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define CRM_APB2EN_GPIOCEN_Pos (4U) +#define CRM_APB2EN_GPIOCEN_Msk (0x1U << CRM_APB2EN_GPIOCEN_Pos) /*!< 0x00000010 */ +#define CRM_APB2EN_GPIOCEN CRM_APB2EN_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define CRM_APB2EN_GPIODEN_Pos (5U) +#define CRM_APB2EN_GPIODEN_Msk (0x1U << CRM_APB2EN_GPIODEN_Pos) /*!< 0x00000020 */ +#define CRM_APB2EN_GPIODEN CRM_APB2EN_GPIODEN_Msk /*!< GPIOD clock enable */ +#define CRM_APB2EN_GPIOFEN_Pos (7U) +#define CRM_APB2EN_GPIOFEN_Msk (0x1U << CRM_APB2EN_GPIOFEN_Pos) /*!< 0x00000080 */ +#define CRM_APB2EN_GPIOFEN CRM_APB2EN_GPIOFEN_Msk /*!< GPIOF clock enable */ +#define CRM_APB2EN_ADC1EN_Pos (9U) +#define CRM_APB2EN_ADC1EN_Msk (0x1U << CRM_APB2EN_ADC1EN_Pos) /*!< 0x00000200 */ +#define CRM_APB2EN_ADC1EN CRM_APB2EN_ADC1EN_Msk /*!< ADC1 clock enable */ +#define CRM_APB2EN_TMR1EN_Pos (11U) +#define CRM_APB2EN_TMR1EN_Msk (0x1U << CRM_APB2EN_TMR1EN_Pos) /*!< 0x00000800 */ +#define CRM_APB2EN_TMR1EN CRM_APB2EN_TMR1EN_Msk /*!< TMR1 clock enable */ +#define CRM_APB2EN_SPI1EN_Pos (12U) +#define CRM_APB2EN_SPI1EN_Msk (0x1U << CRM_APB2EN_SPI1EN_Pos) /*!< 0x00001000 */ +#define CRM_APB2EN_SPI1EN CRM_APB2EN_SPI1EN_Msk /*!< SPI1 clock enable */ +#define CRM_APB2EN_USART1EN_Pos (14U) +#define CRM_APB2EN_USART1EN_Msk (0x1U << CRM_APB2EN_USART1EN_Pos) /*!< 0x00004000 */ +#define CRM_APB2EN_USART1EN CRM_APB2EN_USART1EN_Msk /*!< USART1 clock enable */ +#define CRM_APB2EN_TMR9EN_Pos (19U) +#define CRM_APB2EN_TMR9EN_Msk (0x1U << CRM_APB2EN_TMR9EN_Pos) /*!< 0x00080000 */ +#define CRM_APB2EN_TMR9EN CRM_APB2EN_TMR9EN_Msk /*!< TMR9 clock enable */ +#define CRM_APB2EN_TMR10EN_Pos (20U) +#define CRM_APB2EN_TMR10EN_Msk (0x1U << CRM_APB2EN_TMR10EN_Pos) /*!< 0x00100000 */ +#define CRM_APB2EN_TMR10EN CRM_APB2EN_TMR10EN_Msk /*!< TMR10 clock enable */ +#define CRM_APB2EN_TMR11EN_Pos (21U) +#define CRM_APB2EN_TMR11EN_Msk (0x1U << CRM_APB2EN_TMR11EN_Pos) /*!< 0x00200000 */ +#define CRM_APB2EN_TMR11EN CRM_APB2EN_TMR11EN_Msk /*!< TMR11 clock enable */ + +/****************** Bit definition for CRM_APB1EN register ******************/ +#define CRM_APB1EN_TMR2EN_Pos (0U) +#define CRM_APB1EN_TMR2EN_Msk (0x1U << CRM_APB1EN_TMR2EN_Pos) /*!< 0x00000001 */ +#define CRM_APB1EN_TMR2EN CRM_APB1EN_TMR2EN_Msk /*!< TMR2 clock enable */ +#define CRM_APB1EN_TMR3EN_Pos (1U) +#define CRM_APB1EN_TMR3EN_Msk (0x1U << CRM_APB1EN_TMR3EN_Pos) /*!< 0x00000002 */ +#define CRM_APB1EN_TMR3EN CRM_APB1EN_TMR3EN_Msk /*!< TMR3 clock enable */ +#define CRM_APB1EN_TMR4EN_Pos (2U) +#define CRM_APB1EN_TMR4EN_Msk (0x1U << CRM_APB1EN_TMR4EN_Pos) /*!< 0x00000004 */ +#define CRM_APB1EN_TMR4EN CRM_APB1EN_TMR4EN_Msk /*!< TMR4 clock enable */ +#define CRM_APB1EN_TMR5EN_Pos (3U) +#define CRM_APB1EN_TMR5EN_Msk (0x1U << CRM_APB1EN_TMR5EN_Pos) /*!< 0x00000008 */ +#define CRM_APB1EN_TMR5EN CRM_APB1EN_TMR5EN_Msk /*!< TMR5 clock enable */ +#define CRM_APB1EN_CMPEN_Pos (9U) +#define CRM_APB1EN_CMPEN_Msk (0x1U << CRM_APB1EN_CMPEN_Pos) /*!< 0x00000200 */ +#define CRM_APB1EN_CMPEN CRM_APB1EN_CMPEN_Msk /*!< CMP clock enable */ +#define CRM_APB1EN_WWDTEN_Pos (11U) +#define CRM_APB1EN_WWDTEN_Msk (0x1U << CRM_APB1EN_WWDTEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1EN_WWDTEN CRM_APB1EN_WWDTEN_Msk /*!< WWDT clock enable */ +#define CRM_APB1EN_SPI2EN_Pos (14U) +#define CRM_APB1EN_SPI2EN_Msk (0x1U << CRM_APB1EN_SPI2EN_Pos) /*!< 0x00004000 */ +#define CRM_APB1EN_SPI2EN CRM_APB1EN_SPI2EN_Msk /*!< SPI2 clock enable */ +#define CRM_APB1EN_USART2EN_Pos (17U) +#define CRM_APB1EN_USART2EN_Msk (0x1U << CRM_APB1EN_USART2EN_Pos) /*!< 0x00020000 */ +#define CRM_APB1EN_USART2EN CRM_APB1EN_USART2EN_Msk /*!< USART2 clock enable */ +#define CRM_APB1EN_USART3EN_Pos (18U) +#define CRM_APB1EN_USART3EN_Msk (0x1U << CRM_APB1EN_USART3EN_Pos) /*!< 0x00040000 */ +#define CRM_APB1EN_USART3EN CRM_APB1EN_USART3EN_Msk /*!< USART3 clock enable */ +#define CRM_APB1EN_I2C1EN_Pos (21U) +#define CRM_APB1EN_I2C1EN_Msk (0x1U << CRM_APB1EN_I2C1EN_Pos) /*!< 0x00200000 */ +#define CRM_APB1EN_I2C1EN CRM_APB1EN_I2C1EN_Msk /*!< I2C1 clock enable */ +#define CRM_APB1EN_I2C2EN_Pos (22U) +#define CRM_APB1EN_I2C2EN_Msk (0x1U << CRM_APB1EN_I2C2EN_Pos) /*!< 0x00400000 */ +#define CRM_APB1EN_I2C2EN CRM_APB1EN_I2C2EN_Msk /*!< I2C2 clock enable */ +#define CRM_APB1EN_CAN1EN_Pos (25U) +#define CRM_APB1EN_CAN1EN_Msk (0x1U << CRM_APB1EN_CAN1EN_Pos) /*!< 0x02000000 */ +#define CRM_APB1EN_CAN1EN CRM_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ +#define CRM_APB1EN_PWCEN_Pos (28U) +#define CRM_APB1EN_PWCEN_Msk (0x1U << CRM_APB1EN_PWCEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1EN_PWCEN CRM_APB1EN_PWCEN_Msk /*!< Power control clock enable */ + +/******************* Bit definition for CRM_BPDC register *******************/ +#define CRM_BPDC_LEXTEN_Pos (0U) +#define CRM_BPDC_LEXTEN_Msk (0x1U << CRM_BPDC_LEXTEN_Pos) /*!< 0x00000001 */ +#define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ +#define CRM_BPDC_LEXTSTBL_Pos (1U) +#define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< Low speed external oscillator stable */ +#define CRM_BPDC_LEXTBYPS_Pos (2U) +#define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< Low speed external crystal bypass */ + +/*!< ERTCSEL congiguration */ +#define CRM_BPDC_ERTCSEL_Pos (8U) +#define CRM_BPDC_ERTCSEL_Msk (0x3U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000300 */ +#define CRM_BPDC_ERTCSEL CRM_BPDC_ERTCSEL_Msk /*!< ERTCSEL[1:0] bits (ERTC clock selection) */ +#define CRM_BPDC_ERTCSEL_0 (0x1U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000100 */ +#define CRM_BPDC_ERTCSEL_1 (0x2U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000200 */ + +#define CRM_BPDC_ERTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define CRM_BPDC_ERTCSEL_LEXT 0x00000100U /*!< LEXT */ +#define CRM_BPDC_ERTCSEL_LICK 0x00000200U /*!< LICK */ +#define CRM_BPDC_ERTCSEL_HEXT 0x00000300U /*!< HEXT/128 */ + +#define CRM_BPDC_ERTCEN_Pos (15U) +#define CRM_BPDC_ERTCEN_Msk (0x1U << CRM_BPDC_ERTCEN_Pos) /*!< 0x00008000 */ +#define CRM_BPDC_ERTCEN CRM_BPDC_ERTCEN_Msk /*!< ERTC clock enable */ +#define CRM_BPDC_BPDRST_Pos (16U) +#define CRM_BPDC_BPDRST_Msk (0x1U << CRM_BPDC_BPDRST_Pos) /*!< 0x00010000 */ +#define CRM_BPDC_BPDRST CRM_BPDC_BPDRST_Msk /*!< Battery powered domain software reset */ + +/***************** Bit definition for CRM_CTRLSTS register ******************/ +#define CRM_CTRLSTS_LICKEN_Pos (0U) +#define CRM_CTRLSTS_LICKEN_Msk (0x1U << CRM_CTRLSTS_LICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRLSTS_LICKEN CRM_CTRLSTS_LICKEN_Msk /*!< LICK enable */ +#define CRM_CTRLSTS_LICKSTBL_Pos (1U) +#define CRM_CTRLSTS_LICKSTBL_Msk (0x1U << CRM_CTRLSTS_LICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRLSTS_LICKSTBL CRM_CTRLSTS_LICKSTBL_Msk /*!< LICK stable */ +#define CRM_CTRLSTS_RSTFC_Pos (24U) +#define CRM_CTRLSTS_RSTFC_Msk (0x1U << CRM_CTRLSTS_RSTFC_Pos) /*!< 0x01000000 */ +#define CRM_CTRLSTS_RSTFC CRM_CTRLSTS_RSTFC_Msk /*!< Reset flag clear */ +#define CRM_CTRLSTS_NRSTF_Pos (26U) +#define CRM_CTRLSTS_NRSTF_Msk (0x1U << CRM_CTRLSTS_NRSTF_Pos) /*!< 0x04000000 */ +#define CRM_CTRLSTS_NRSTF CRM_CTRLSTS_NRSTF_Msk /*!< NRST pin reset flag */ +#define CRM_CTRLSTS_PORRSTF_Pos (27U) +#define CRM_CTRLSTS_PORRSTF_Msk (0x1U << CRM_CTRLSTS_PORRSTF_Pos) /*!< 0x08000000 */ +#define CRM_CTRLSTS_PORRSTF CRM_CTRLSTS_PORRSTF_Msk /*!< POR/LVR reset flag */ +#define CRM_CTRLSTS_SWRSTF_Pos (28U) +#define CRM_CTRLSTS_SWRSTF_Msk (0x1U << CRM_CTRLSTS_SWRSTF_Pos) /*!< 0x10000000 */ +#define CRM_CTRLSTS_SWRSTF CRM_CTRLSTS_SWRSTF_Msk /*!< Software reset flag */ +#define CRM_CTRLSTS_WDTRSTF_Pos (29U) +#define CRM_CTRLSTS_WDTRSTF_Msk (0x1U << CRM_CTRLSTS_WDTRSTF_Pos) /*!< 0x20000000 */ +#define CRM_CTRLSTS_WDTRSTF CRM_CTRLSTS_WDTRSTF_Msk /*!< Watchdog timer reset flag */ +#define CRM_CTRLSTS_WWDTRSTF_Pos (30U) +#define CRM_CTRLSTS_WWDTRSTF_Msk (0x1U << CRM_CTRLSTS_WWDTRSTF_Pos) /*!< 0x40000000 */ +#define CRM_CTRLSTS_WWDTRSTF CRM_CTRLSTS_WWDTRSTF_Msk /*!< Window watchdog timer reset flag */ +#define CRM_CTRLSTS_LPRSTF_Pos (31U) +#define CRM_CTRLSTS_LPRSTF_Msk (0x1U << CRM_CTRLSTS_LPRSTF_Pos) /*!< 0x80000000 */ +#define CRM_CTRLSTS_LPRSTF CRM_CTRLSTS_LPRSTF_Msk /*!< Low-power reset flag */ + +/****************** Bit definition for CRM_AHBRST register ******************/ +#define CRM_AHBRST_OTGFSRST_Pos (12U) +#define CRM_AHBRST_OTGFSRST_Msk (0x1U << CRM_AHBRST_OTGFSRST_Pos) /*!< 0x00001000 */ +#define CRM_AHBRST_OTGFSRST CRM_AHBRST_OTGFSRST_Msk /*!< OTGFS reset */ + +/******************* Bit definition for CRM_PLL register ********************/ +/*!< PLL_FR congiguration */ +#define CRM_PLL_PLL_FR_Pos (0U) +#define CRM_PLL_PLL_FR_Msk (0x7U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000007 */ +#define CRM_PLL_PLL_FR CRM_PLL_PLL_FR_Msk /*!< PLL_FR[2:0] bits (PLL post-division factor) */ +#define CRM_PLL_PLL_FR_0 (0x1U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000001 */ +#define CRM_PLL_PLL_FR_1 (0x2U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000002 */ +#define CRM_PLL_PLL_FR_2 (0x4U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000004 */ + +/*!< PLL_MS congiguration */ +#define CRM_PLL_PLL_MS_Pos (4U) +#define CRM_PLL_PLL_MS_Msk (0xFU << CRM_PLL_PLL_MS_Pos) /*!< 0x000000F0 */ +#define CRM_PLL_PLL_MS CRM_PLL_PLL_MS_Msk /*!< PLL_MS[3:0] bits (PLL pre-division) */ +#define CRM_PLL_PLL_MS_0 (0x1U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000010 */ +#define CRM_PLL_PLL_MS_1 (0x2U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000020 */ +#define CRM_PLL_PLL_MS_2 (0x4U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000040 */ +#define CRM_PLL_PLL_MS_3 (0x8U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000080 */ + +/*!< PLL_NS congiguration */ +#define CRM_PLL_PLL_NS_Pos (8U) +#define CRM_PLL_PLL_NS_Msk (0x1FFU << CRM_PLL_PLL_NS_Pos) /*!< 0x0001FF00 */ +#define CRM_PLL_PLL_NS CRM_PLL_PLL_NS_Msk /*!< PLL_NS[8:0] bits (PLL multiplication factor) */ +#define CRM_PLL_PLL_NS_0 (0x001U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000100 */ +#define CRM_PLL_PLL_NS_1 (0x002U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000200 */ +#define CRM_PLL_PLL_NS_2 (0x004U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000400 */ +#define CRM_PLL_PLL_NS_3 (0x008U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000800 */ +#define CRM_PLL_PLL_NS_4 (0x010U << CRM_PLL_PLL_NS_Pos) /*!< 0x00001000 */ +#define CRM_PLL_PLL_NS_5 (0x020U << CRM_PLL_PLL_NS_Pos) /*!< 0x00002000 */ +#define CRM_PLL_PLL_NS_6 (0x040U << CRM_PLL_PLL_NS_Pos) /*!< 0x00004000 */ +#define CRM_PLL_PLL_NS_7 (0x080U << CRM_PLL_PLL_NS_Pos) /*!< 0x00008000 */ +#define CRM_PLL_PLL_NS_8 (0x100U << CRM_PLL_PLL_NS_Pos) /*!< 0x00010000 */ + +/*!< PLL_FREF congiguration */ +#define CRM_PLL_PLL_FREF_Pos (24U) +#define CRM_PLL_PLL_FREF_Msk (0x7U << CRM_PLL_PLL_FREF_Pos) /*!< 0x07000000 */ +#define CRM_PLL_PLL_FREF CRM_PLL_PLL_FREF_Msk /*!< PLL_FREF[2:0] bits (PLL input clock selection) */ +#define CRM_PLL_PLL_FREF_0 (0x1U << CRM_PLL_PLL_FREF_Pos) /*!< 0x01000000 */ +#define CRM_PLL_PLL_FREF_1 (0x2U << CRM_PLL_PLL_FREF_Pos) /*!< 0x02000000 */ +#define CRM_PLL_PLL_FREF_2 (0x4U << CRM_PLL_PLL_FREF_Pos) /*!< 0x04000000 */ + +#define CRM_PLL_PLL_FREF_4M 0x00000000U /*!< 3.9 ~ 5 MHz */ +#define CRM_PLL_PLL_FREF_6M 0x01000000U /*!< 5.2 ~ 6.25 MHz */ +#define CRM_PLL_PLL_FREF_8M 0x02000000U /*!< 7.8125 ~ 8.33 MHz */ +#define CRM_PLL_PLL_FREF_12M 0x03000000U /*!< 8.33 ~ 12.5 MHz */ +#define CRM_PLL_PLL_FREF_16M 0x04000000U /*!< 15.625 ~ 20.83 MHz */ +#define CRM_PLL_PLL_FREF_25M 0x05000000U /*!< 20.83 ~ 31.255 MHz */ + +#define CRM_PLL_PLLCFGEN_Pos (31U) +#define CRM_PLL_PLLCFGEN_Msk (0x1U << CRM_PLL_PLLCFGEN_Pos) /*!< 0x80000000 */ +#define CRM_PLL_PLLCFGEN CRM_PLL_PLLCFGEN_Msk /*!< PLL configuration enable */ + +/****************** Bit definition for CRM_MISC1 register *******************/ +#define CRM_MISC1_HICKCAL_KEY_Pos (0U) +#define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ +#define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ +#define CRM_MISC1_CLKOUT_SEL_Pos (16U) +#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRN_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL CRM_MISC1_CLKOUT_SEL_Msk /*!< Clock output selection */ +#define CRM_MISC1_CLKFMC_SRC_Pos (20U) +#define CRM_MISC1_CLKFMC_SRC_Msk (0x1U << CRM_MISC1_CLKFMC_SRC_Pos) /*!< 0x00100000 */ +#define CRM_MISC1_CLKFMC_SRC CRM_MISC1_CLKFMC_SRC_Msk /*!< FMC clock source */ +#define CRM_MISC1_HICKDIV_Pos (25U) +#define CRM_MISC1_HICKDIV_Msk (0x1U << CRM_MISC1_HICKDIV_Pos) /*!< 0x02000000 */ +#define CRM_MISC1_HICKDIV CRM_MISC1_HICKDIV_Msk /*!< HICK 6 divider selection */ + +/*!< CLKOUTDIV congiguration */ +#define CRM_MISC1_CLKOUTDIV_Pos (28U) +#define CRM_MISC1_CLKOUTDIV_Msk (0xFU << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0xF0000000 */ +#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division */ +#define CRM_MISC1_CLKOUTDIV_0 (0x1U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x10000000 */ +#define CRM_MISC1_CLKOUTDIV_1 (0x2U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x20000000 */ +#define CRM_MISC1_CLKOUTDIV_2 (0x4U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x40000000 */ +#define CRM_MISC1_CLKOUTDIV_3 (0x8U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x80000000 */ + +#define CRM_MISC1_CLKOUTDIV_DIV1 0x00000000U /*!< No clock output */ +#define CRM_MISC1_CLKOUTDIV_DIV2 0x80000000U /*!< Clock output divided by 2 */ +#define CRM_MISC1_CLKOUTDIV_DIV4 0x90000000U /*!< Clock output divided by 4 */ +#define CRM_MISC1_CLKOUTDIV_DIV8 0xA0000000U /*!< Clock output divided by 8 */ +#define CRM_MISC1_CLKOUTDIV_DIV16 0xB0000000U /*!< Clock output divided by 16 */ +#define CRM_MISC1_CLKOUTDIV_DIV64 0xC0000000U /*!< Clock output divided by 64 */ +#define CRM_MISC1_CLKOUTDIV_DIV128 0xD0000000U /*!< Clock output divided by 128 */ +#define CRM_MISC1_CLKOUTDIV_DIV256 0xE0000000U /*!< Clock output divided by 256 */ +#define CRM_MISC1_CLKOUTDIV_DIV512 0xF0000000U /*!< Clock output divided by 512 */ + +/*************** Bit definition for CRM_OTG_EXTCTRL register ****************/ +#define CRM_OTG_EXTCTRL_USBDIV_RST_Pos (30U) /*!< 0x40000000 */ +#define CRM_OTG_EXTCTRL_USBDIV_RST_Msk (0x1U << CRM_OTG_EXTCTRL_USBDIV_RST_Pos) +#define CRM_OTG_EXTCTRL_USBDIV_RST CRM_OTG_EXTCTRL_USBDIV_RST_Msk /*!< USB divider reset */ +#define CRM_OTG_EXTCTRL_EP3_RMPEN_Pos (31U) +#define CRM_OTG_EXTCTRL_EP3_RMPEN_Msk (0x1U << CRM_OTG_EXTCTRL_EP3_RMPEN_Pos) /*!< 0x80000000 */ +#define CRM_OTG_EXTCTRL_EP3_RMPEN CRM_OTG_EXTCTRL_EP3_RMPEN_Msk /*!< Endpoint 3 remap enable */ + +/****************** Bit definition for CRM_MISC2 register *******************/ +/*!< AUTO_STEP_EN congiguration */ +#define CRM_MISC2_AUTO_STEP_EN_Pos (4U) +#define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] Auto step-by-step SCLK switch enable */ +#define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ +#define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ + +#define CRM_MISC2_HICK_TO_SCLK_Pos (9U) +#define CRM_MISC2_HICK_TO_SCLK_Msk (0x1U << CRM_MISC2_HICK_TO_SCLK_Pos) /*!< 0x00000200 */ +#define CRM_MISC2_HICK_TO_SCLK CRM_MISC2_HICK_TO_SCLK_Msk /*!< HICK as system clock frequency select */ + +/******************************************************************************/ +/* */ +/* Flash and User System Data Registers (FLASH) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_PSR register ******************/ +/*!< WTCYC congiguration */ +#define FLASH_PSR_WTCYC_Pos (0U) +#define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] Wait states */ +#define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ +#define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ +#define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ + +#define FLASH_PSR_HFCYC_EN_Pos (3U) +#define FLASH_PSR_HFCYC_EN_Msk (0x1U << FLASH_PSR_HFCYC_EN_Pos) /*!< 0x00000008 */ +#define FLASH_PSR_HFCYC_EN FLASH_PSR_HFCYC_EN_Msk /*!< Half cycle acceleration access enable */ +#define FLASH_PSR_PFT_EN_Pos (4U) +#define FLASH_PSR_PFT_EN_Msk (0x1U << FLASH_PSR_PFT_EN_Pos) /*!< 0x00000010 */ +#define FLASH_PSR_PFT_EN FLASH_PSR_PFT_EN_Msk /*!< Prefetch enable */ +#define FLASH_PSR_PFT_ENF_Pos (5U) +#define FLASH_PSR_PFT_ENF_Msk (0x1U << FLASH_PSR_PFT_ENF_Pos) /*!< 0x00000020 */ +#define FLASH_PSR_PFT_ENF FLASH_PSR_PFT_ENF_Msk /*!< Prefetch enable flag */ + +/***************** Bit definition for FLASH_UNLOCK register *****************/ +#define FLASH_UNLOCK_UKVAL_Pos (0U) +#define FLASH_UNLOCK_UKVAL_Msk (0xFFFFFFFFU << FLASH_UNLOCK_UKVAL_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_UNLOCK_UKVAL FLASH_UNLOCK_UKVAL_Msk /*!< Unlock key value */ + +#define FAP_KEY_Pos (0U) +#define FAP_KEY_Msk (0xA5U << FAP_KEY_Pos) /*!< 0x000000A5 */ +#define FAP_KEY FAP_KEY_Msk /*!< Flash access protection key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash key 1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash key 2 */ + +/*************** Bit definition for FLASH_USD_UNLOCK register ***************/ +#define FLASH_USD_UNLOCK_USD_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_USD_UNLOCK_USD_UKVAL_Msk (0xFFFFFFFFU << FLASH_USD_UNLOCK_USD_UKVAL_Pos) +#define FLASH_USD_UNLOCK_USD_UKVAL FLASH_USD_UNLOCK_USD_UKVAL_Msk /*!< User system data unlock key value */ + +#define FLASH_USDKEY1 FLASH_KEY1 /*!< User system data key 1 */ +#define FLASH_USDKEY2 FLASH_KEY2 /*!< User system data key 2 */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_OBF_Pos (0U) +#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation done flag */ +#define FLASH_STS_PRGMERR_Pos (2U) +#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ +#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ +#define FLASH_STS_EPPERR_Pos (4U) +#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */ +#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk /*!< Erase/program protection error */ +#define FLASH_STS_ODF_Pos (5U) +#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */ +#define FLASH_STS_ODF FLASH_STS_ODF_Msk /*!< Operation done flag */ + +/****************** Bit definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_FPRGM_Pos (0U) +#define FLASH_CTRL_FPRGM_Msk (0x1U << FLASH_CTRL_FPRGM_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_FPRGM FLASH_CTRL_FPRGM_Msk /*!< Flash program */ +#define FLASH_CTRL_SECERS_Pos (1U) +#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk /*!< Page erase */ +#define FLASH_CTRL_BANKERS_Pos (2U) +#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk /*!< Bank erase */ +#define FLASH_CTRL_USDPRGM_Pos (4U) +#define FLASH_CTRL_USDPRGM_Msk (0x1U << FLASH_CTRL_USDPRGM_Pos) /*!< 0x00000010 */ +#define FLASH_CTRL_USDPRGM FLASH_CTRL_USDPRGM_Msk /*!< User system data program */ +#define FLASH_CTRL_USDERS_Pos (5U) +#define FLASH_CTRL_USDERS_Msk (0x1U << FLASH_CTRL_USDERS_Pos) /*!< 0x00000020 */ +#define FLASH_CTRL_USDERS FLASH_CTRL_USDERS_Msk /*!< User system data erase */ +#define FLASH_CTRL_ERSTR_Pos (6U) +#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x00000040 */ +#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk /*!< Erase start */ +#define FLASH_CTRL_OPLK_Pos (7U) +#define FLASH_CTRL_OPLK_Msk (0x1U << FLASH_CTRL_OPLK_Pos) /*!< 0x00000080 */ +#define FLASH_CTRL_OPLK FLASH_CTRL_OPLK_Msk /*!< Operation lock */ +#define FLASH_CTRL_USDULKS_Pos (9U) +#define FLASH_CTRL_USDULKS_Msk (0x1U << FLASH_CTRL_USDULKS_Pos) /*!< 0x00000200 */ +#define FLASH_CTRL_USDULKS FLASH_CTRL_USDULKS_Msk /*!< User system data unlock success */ +#define FLASH_CTRL_ERRIE_Pos (10U) +#define FLASH_CTRL_ERRIE_Msk (0x1U << FLASH_CTRL_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CTRL_ERRIE FLASH_CTRL_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CTRL_ODFIE_Pos (12U) +#define FLASH_CTRL_ODFIE_Msk (0x1U << FLASH_CTRL_ODFIE_Pos) /*!< 0x00001000 */ +#define FLASH_CTRL_ODFIE FLASH_CTRL_ODFIE_Msk /*!< Operation done flag interrupt enable */ +#define FLASH_CTRL_FAP_HL_DIS_Pos (16U) +#define FLASH_CTRL_FAP_HL_DIS_Msk (0x1U << FLASH_CTRL_FAP_HL_DIS_Pos) /*!< 0x00010000 */ +#define FLASH_CTRL_FAP_HL_DIS FLASH_CTRL_FAP_HL_DIS_Msk /*!< High level Flash access protection disable */ + +/****************** Bit definition for FLASH_ADDR register ******************/ +#define FLASH_ADDR_FA_Pos (0U) +#define FLASH_ADDR_FA_Msk (0xFFFFFFFFU << FLASH_ADDR_FA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_ADDR_FA FLASH_ADDR_FA_Msk /*!< Flash address */ + +/****************** Bit definition for FLASH_USD register *******************/ +#define FLASH_USD_USDERR_Pos (0U) +#define FLASH_USD_USDERR_Msk (0x1U << FLASH_USD_USDERR_Pos) /*!< 0x00000001 */ +#define FLASH_USD_USDERR FLASH_USD_USDERR_Msk /*!< User system data error */ +#define FLASH_USD_FAP_Pos (1U) +#define FLASH_USD_FAP_Msk (0x1U << FLASH_USD_FAP_Pos) /*!< 0x00000002 */ +#define FLASH_USD_FAP FLASH_USD_FAP_Msk /*!< Flash access protection */ + +/*!< SSB congiguration */ +#define FLASH_USD_WDT_ATO_EN_Pos (2U) +#define FLASH_USD_WDT_ATO_EN_Msk (0x1U << FLASH_USD_WDT_ATO_EN_Pos) /*!< 0x00000004 */ +#define FLASH_USD_WDT_ATO_EN FLASH_USD_WDT_ATO_EN_Msk /*!< nWDT_ATO_EN */ +#define FLASH_USD_DEPSLP_RST_Pos (3U) +#define FLASH_USD_DEPSLP_RST_Msk (0x1U << FLASH_USD_DEPSLP_RST_Pos) /*!< 0x00000008 */ +#define FLASH_USD_DEPSLP_RST FLASH_USD_DEPSLP_RST_Msk /*!< nDEPSLP_RST */ +#define FLASH_USD_STDBY_RST_Pos (4U) +#define FLASH_USD_STDBY_RST_Msk (0x1U << FLASH_USD_STDBY_RST_Pos) /*!< 0x00000010 */ +#define FLASH_USD_STDBY_RST FLASH_USD_STDBY_RST_Msk /*!< nSTDBY_RST */ +#define FLASH_USD_SSB_Pos (2U) +#define FLASH_USD_SSB_Msk (0x7U << FLASH_USD_SSB_Pos) /*!< 0x0000001C */ +#define FLASH_USD_SSB FLASH_USD_SSB_Msk /*!< System setting byte */ + +#define FLASH_USD_USER_D0_Pos (10U) +#define FLASH_USD_USER_D0_Msk (0xFFU << FLASH_USD_USER_D0_Pos) /*!< 0x0003FC00 */ +#define FLASH_USD_USER_D0 FLASH_USD_USER_D0_Msk /*!< User data 0 */ +#define FLASH_USD_USER_D1_Pos (18U) +#define FLASH_USD_USER_D1_Msk (0xFFU << FLASH_USD_USER_D1_Pos) /*!< 0x03FC0000 */ +#define FLASH_USD_USER_D1 FLASH_USD_USER_D1_Msk /*!< User data 1 */ +#define FLASH_USD_FAP_HL_Pos (26U) +#define FLASH_USD_FAP_HL_Msk (0x1U << FLASH_USD_FAP_HL_Pos) /*!< 0x04000000 */ +#define FLASH_USD_FAP_HL FLASH_USD_FAP_HL_Msk /*!< Flash access protection high level */ + +/****************** Bit definition for FLASH_EPPS register ******************/ +#define FLASH_EPPS_EPPS_Pos (0U) +#define FLASH_EPPS_EPPS_Msk (0xFFFFFFFFU << FLASH_EPPS_EPPS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_EPPS_EPPS FLASH_EPPS_EPPS_Msk /*!< Erase/Program protection status */ + +/******************* Bit definition for SLIB_STS0 register *******************/ +#define SLIB_STS0_BTM_AP_ENF_Pos (0U) +#define SLIB_STS0_BTM_AP_ENF_Msk (0x1U << SLIB_STS0_BTM_AP_ENF_Pos) /*!< 0x00000001 */ +#define SLIB_STS0_BTM_AP_ENF SLIB_STS0_BTM_AP_ENF_Msk /*!< Boot memory store application code enabled flag */ +#define SLIB_STS0_EM_SLIB_ENF_Pos (2U) +#define SLIB_STS0_EM_SLIB_ENF_Msk (0x1U << SLIB_STS0_EM_SLIB_ENF_Pos) /*!< 0x00000004 */ +#define SLIB_STS0_EM_SLIB_ENF SLIB_STS0_EM_SLIB_ENF_Msk /*!< Extension memory sLib enable flag */ +#define SLIB_STS0_SLIB_ENF_Pos (3U) +#define SLIB_STS0_SLIB_ENF_Msk (0x1U << SLIB_STS0_SLIB_ENF_Pos) /*!< 0x00000008 */ +#define SLIB_STS0_SLIB_ENF SLIB_STS0_SLIB_ENF_Msk /*!< Security library enable flag */ +#define SLIB_STS0_EM_SLIB_DAT_SS_Pos (16U) +#define SLIB_STS0_EM_SLIB_DAT_SS_Msk (0xFFU << SLIB_STS0_EM_SLIB_DAT_SS_Pos) /*!< 0x00FF0000 */ +#define SLIB_STS0_EM_SLIB_DAT_SS SLIB_STS0_EM_SLIB_DAT_SS_Msk /*!< Extension memory sLib data start page */ + +/******************* Bit definition for SLIB_STS1 register *******************/ +#define SLIB_STS1_SLIB_SS_Pos (0U) +#define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ +#define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ +#define SLIB_STS1_SLIB_DAT_SS_Pos (11U) +#define SLIB_STS1_SLIB_DAT_SS_Msk (0x3FF8U << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_DAT_SS SLIB_STS1_SLIB_DAT_SS_Msk /*!< Security library data start page */ +#define SLIB_STS1_SLIB_ES_Pos (22U) +#define SLIB_STS1_SLIB_ES_Msk (0xFFCU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ + +/***************** Bit definition for SLIB_PWD_CLR register ******************/ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk (0xFFFFFFFFU << SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos) +#define SLIB_PWD_CLR_SLIB_PCLR_VAL SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk /*!< Security library password clear value */ + +/***************** Bit definition for SLIB_MISC_STS register *****************/ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Pos (0U) /*!< 0x00000001 */ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_ERR_Pos) +#define SLIB_MISC_STS_SLIB_PWD_ERR SLIB_MISC_STS_SLIB_PWD_ERR_Msk /*!< Security library password error */ +#define SLIB_MISC_STS_SLIB_PWD_OK_Pos (1U) +#define SLIB_MISC_STS_SLIB_PWD_OK_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_OK_Pos) /*!< 0x00000002 */ +#define SLIB_MISC_STS_SLIB_PWD_OK SLIB_MISC_STS_SLIB_PWD_OK_Msk /*!< Security library password ok */ +#define SLIB_MISC_STS_SLIB_ULKF_Pos (2U) +#define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ +#define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ + +/***************** Bit definition for FLASH_CRC_ARR register *****************/ +#define FLASH_CRC_ARR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ARR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ARR_CRC_ADDR_Pos) +#define FLASH_CRC_ARR_CRC_ADDR FLASH_CRC_ARR_CRC_ADDR_Msk /*!< CRC address */ + +/**************** Bit definition for FLASH_CRC_CTRL register *****************/ +#define FLASH_CRC_CTRL_CRC_SN_Pos (0U) +#define FLASH_CRC_CTRL_CRC_SN_Msk (0xFFFFU << FLASH_CRC_CTRL_CRC_SN_Pos) /*!< 0x0000FFFF */ +#define FLASH_CRC_CTRL_CRC_SN FLASH_CRC_CTRL_CRC_SN_Msk /*!< CRC page number */ +#define FLASH_CRC_CTRL_CRC_STRT_Pos (16U) +#define FLASH_CRC_CTRL_CRC_STRT_Msk (0x1U << FLASH_CRC_CTRL_CRC_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CRC_CTRL_CRC_STRT FLASH_CRC_CTRL_CRC_STRT_Msk /*!< CRC start */ + +/**************** Bit definition for FLASH_CRC_CHKR register *****************/ +#define FLASH_CRC_CHKR_CRC_CHKR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_CHKR_CRC_CHKR_Msk (0xFFFFFFFFU << FLASH_CRC_CHKR_CRC_CHKR_Pos) +#define FLASH_CRC_CHKR_CRC_CHKR FLASH_CRC_CHKR_CRC_CHKR_Msk /*!< CRC check result */ + +/***************** Bit definition for SLIB_SET_PWD register ******************/ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< sLib password setting value */ + +/**************** Bit definition for SLIB_SET_RANGE register *****************/ +#define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ +#define SLIB_SET_RANGE_SLIB_SS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_SS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_SS_SET SLIB_SET_RANGE_SLIB_SS_SET_Msk /*!< Security library start page setting */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Pos (11U) /*!< 0x003FF800 */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Msk (0x3FF8U << SLIB_SET_RANGE_SLIB_ISS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ISS_SET SLIB_SET_RANGE_SLIB_ISS_SET_Msk /*!< Security library instruction start page setting */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Pos (22U) /*!< 0xFFC00000 */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Msk (0xFFCU << SLIB_SET_RANGE_SLIB_ES_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ES_SET SLIB_SET_RANGE_SLIB_ES_SET_Msk /*!< Security library end page setting */ + +/****************** Bit definition for EM_SLIB_SET register ******************/ +#define EM_SLIB_SET_EM_SLIB_SET_Pos (0U) /*!< 0x0000FFFF */ +#define EM_SLIB_SET_EM_SLIB_SET_Msk (0xFFFFU << EM_SLIB_SET_EM_SLIB_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page */ + +/***************** Bit definition for BTM_MODE_SET register ******************/ +#define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ +#define BTM_MODE_SET_BTM_MODE_SET_Msk (0xFFU << BTM_MODE_SET_BTM_MODE_SET_Pos) +#define BTM_MODE_SET_BTM_MODE_SET BTM_MODE_SET_BTM_MODE_SET_Msk /*!< Boot memory mode setting */ + +/***************** Bit definition for SLIB_UNLOCK register ******************/ +#define SLIB_UNLOCK_SLIB_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) +#define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ + +#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ +#define SLIB_KEY SLIB_KEY_Msk + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_FAP register *******************/ +#define FLASH_FAP_FAP_Pos (0U) +#define FLASH_FAP_FAP_Msk (0xFFU << FLASH_FAP_FAP_Pos) /*!< 0x000000FF */ +#define FLASH_FAP_FAP FLASH_FAP_FAP_Msk /*!< Flash memory access protection */ +#define FLASH_FAP_nFAP_Pos (8U) +#define FLASH_FAP_nFAP_Msk (0xFFU << FLASH_FAP_nFAP_Pos) /*!< 0x0000FF00 */ +#define FLASH_FAP_nFAP FLASH_FAP_nFAP_Msk /*!< Inverse code of flash memory access protection */ + +/****************** Bit definition for FLASH_SSB register *******************/ +#define FLASH_SSB_SSB_Pos (16U) +#define FLASH_SSB_SSB_Msk (0xFFU << FLASH_SSB_SSB_Pos) /*!< 0x00FF0000 */ +#define FLASH_SSB_SSB FLASH_SSB_SSB_Msk /*!< System configuration byte */ +#define FLASH_SSB_nSSB_Pos (24U) +#define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ +#define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ + +/****************** Bit definition for FLASH_DATA0 register *****************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ + +/****************** Bit definition for FLASH_DATA1 register *****************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< Inverse code of user data 1 */ + +/****************** Bit definition for FLASH_EPP0 register ******************/ +#define FLASH_EPP0_EPP0_Pos (0U) +#define FLASH_EPP0_EPP0_Msk (0xFFU << FLASH_EPP0_EPP0_Pos) /*!< 0x000000FF */ +#define FLASH_EPP0_EPP0 FLASH_EPP0_EPP0_Msk /*!< Flash erase/write protection byte 0 */ +#define FLASH_EPP0_nEPP0_Pos (8U) +#define FLASH_EPP0_nEPP0_Msk (0xFFU << FLASH_EPP0_nEPP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP0_nEPP0 FLASH_EPP0_nEPP0_Msk /*!< Inverse code of flash erase/write protection byte 0 */ + +/****************** Bit definition for FLASH_EPP1 register ******************/ +#define FLASH_EPP1_EPP1_Pos (16U) +#define FLASH_EPP1_EPP1_Msk (0xFFU << FLASH_EPP1_EPP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP1_EPP1 FLASH_EPP1_EPP1_Msk /*!< Flash erase/write protection byte 1 */ +#define FLASH_EPP1_nEPP1_Pos (24U) +#define FLASH_EPP1_nEPP1_Msk (0xFFU << FLASH_EPP1_nEPP1_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP1_nEPP1 FLASH_EPP1_nEPP1_Msk /*!< Inverse code of flash erase/write protection byte 1 */ + +/****************** Bit definition for FLASH_EPP2 register ******************/ +#define FLASH_EPP2_EPP2_Pos (0U) +#define FLASH_EPP2_EPP2_Msk (0xFFU << FLASH_EPP2_EPP2_Pos) /*!< 0x000000FF */ +#define FLASH_EPP2_EPP2 FLASH_EPP2_EPP2_Msk /*!< Flash erase/write protection byte 2 */ +#define FLASH_EPP2_nEPP2_Pos (8U) +#define FLASH_EPP2_nEPP2_Msk (0xFFU << FLASH_EPP2_nEPP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP2_nEPP2 FLASH_EPP2_nEPP2_Msk /*!< Inverse code of flash erase/write protection byte 2 */ + +/****************** Bit definition for FLASH_EPP3 register ******************/ +#define FLASH_EPP3_EPP3_Pos (16U) +#define FLASH_EPP3_EPP3_Msk (0xFFU << FLASH_EPP3_EPP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP3_EPP3 FLASH_EPP3_EPP3_Msk /*!< Flash erase/write protection byte 3 */ +#define FLASH_EPP3_nEPP3_Pos (24U) +#define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ + +/***************** Bit definition for FLASH_EOPB0 register ******************/ +#define FLASH_EOPB0_EOPB0_Pos (0U) +#define FLASH_EOPB0_EOPB0_Msk (0xFFU << FLASH_EOPB0_EOPB0_Pos) /*!< 0x000000FF */ +#define FLASH_EOPB0_EOPB0 FLASH_EOPB0_EOPB0_Msk /*!< Extended system options */ +#define FLASH_EOPB0_nEOPB0_Pos (8U) +#define FLASH_EOPB0_nEOPB0_Msk (0xFFU << FLASH_EOPB0_nEOPB0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EOPB0_nEOPB0 FLASH_EOPB0_nEOPB0_Msk /*!< Inverse code of extended system options */ + +/****************** Bit definition for FLASH_DATA2 register *****************/ +#define FLASH_DATA2_DATA2_Pos (0U) +#define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ +#define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ +#define FLASH_DATA2_nDATA2_Pos (8U) +#define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ + +/****************** Bit definition for FLASH_DATA3 register *****************/ +#define FLASH_DATA3_DATA3_Pos (16U) +#define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ +#define FLASH_DATA3_nDATA3_Pos (24U) +#define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ + +/****************** Bit definition for FLASH_DATA4 register *****************/ +#define FLASH_DATA4_DATA4_Pos (0U) +#define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ +#define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ +#define FLASH_DATA4_nDATA4_Pos (8U) +#define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ + +/****************** Bit definition for FLASH_DATA5 register *****************/ +#define FLASH_DATA5_DATA5_Pos (16U) +#define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ +#define FLASH_DATA5_nDATA5_Pos (24U) +#define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ + +/****************** Bit definition for FLASH_DATA6 register *****************/ +#define FLASH_DATA6_DATA6_Pos (0U) +#define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ +#define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ +#define FLASH_DATA6_nDATA6_Pos (8U) +#define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ + +/****************** Bit definition for FLASH_DATA7 register *****************/ +#define FLASH_DATA7_DATA7_Pos (16U) +#define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ +#define FLASH_DATA7_nDATA7_Pos (24U) +#define FLASH_DATA7_nDATA7_Msk (0xFFU << FLASH_DATA7_nDATA7_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA7_nDATA7 FLASH_DATA7_nDATA7_Msk /*!< Inverse code of user data 7 */ + +/*!< Noted: The FLASH_DATA go up to 505, it too long for added in here */ + +/******************************************************************************/ +/* */ +/* General-purpose I/Os (GPIO) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for GPIO_CFGLR register ******************/ +#define GPIO_CFGLR_IOMC_Pos (0U) +#define GPIO_CFGLR_IOMC_Msk (0x33333333U << GPIO_CFGLR_IOMC_Pos) /*!< 0x33333333 */ +#define GPIO_CFGLR_IOMC GPIO_CFGLR_IOMC_Msk /*!< GPIO x mode configuration */ + +#define GPIO_CFGLR_IOMC0_Pos (0U) +#define GPIO_CFGLR_IOMC0_Msk (0x3U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000003 */ +#define GPIO_CFGLR_IOMC0 GPIO_CFGLR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ +#define GPIO_CFGLR_IOMC0_0 (0x1U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000001 */ +#define GPIO_CFGLR_IOMC0_1 (0x2U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000002 */ + +#define GPIO_CFGLR_IOMC1_Pos (4U) +#define GPIO_CFGLR_IOMC1_Msk (0x3U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000030 */ +#define GPIO_CFGLR_IOMC1 GPIO_CFGLR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ +#define GPIO_CFGLR_IOMC1_0 (0x1U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000010 */ +#define GPIO_CFGLR_IOMC1_1 (0x2U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000020 */ + +#define GPIO_CFGLR_IOMC2_Pos (8U) +#define GPIO_CFGLR_IOMC2_Msk (0x3U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000300 */ +#define GPIO_CFGLR_IOMC2 GPIO_CFGLR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ +#define GPIO_CFGLR_IOMC2_0 (0x1U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000100 */ +#define GPIO_CFGLR_IOMC2_1 (0x2U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000200 */ + +#define GPIO_CFGLR_IOMC3_Pos (12U) +#define GPIO_CFGLR_IOMC3_Msk (0x3U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00003000 */ +#define GPIO_CFGLR_IOMC3 GPIO_CFGLR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ +#define GPIO_CFGLR_IOMC3_0 (0x1U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00001000 */ +#define GPIO_CFGLR_IOMC3_1 (0x2U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00002000 */ + +#define GPIO_CFGLR_IOMC4_Pos (16U) +#define GPIO_CFGLR_IOMC4_Msk (0x3U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00030000 */ +#define GPIO_CFGLR_IOMC4 GPIO_CFGLR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ +#define GPIO_CFGLR_IOMC4_0 (0x1U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00010000 */ +#define GPIO_CFGLR_IOMC4_1 (0x2U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00020000 */ + +#define GPIO_CFGLR_IOMC5_Pos (20U) +#define GPIO_CFGLR_IOMC5_Msk (0x3U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00300000 */ +#define GPIO_CFGLR_IOMC5 GPIO_CFGLR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ +#define GPIO_CFGLR_IOMC5_0 (0x1U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00100000 */ +#define GPIO_CFGLR_IOMC5_1 (0x2U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00200000 */ + +#define GPIO_CFGLR_IOMC6_Pos (24U) +#define GPIO_CFGLR_IOMC6_Msk (0x3U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x03000000 */ +#define GPIO_CFGLR_IOMC6 GPIO_CFGLR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ +#define GPIO_CFGLR_IOMC6_0 (0x1U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x01000000 */ +#define GPIO_CFGLR_IOMC6_1 (0x2U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x02000000 */ + +#define GPIO_CFGLR_IOMC7_Pos (28U) +#define GPIO_CFGLR_IOMC7_Msk (0x3U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x30000000 */ +#define GPIO_CFGLR_IOMC7 GPIO_CFGLR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ +#define GPIO_CFGLR_IOMC7_0 (0x1U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x10000000 */ +#define GPIO_CFGLR_IOMC7_1 (0x2U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x20000000 */ + +#define GPIO_CFGLR_IOFC_Pos (2U) +#define GPIO_CFGLR_IOFC_Msk (0x33333333U << GPIO_CFGLR_IOFC_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CFGLR_IOFC GPIO_CFGLR_IOFC_Msk /*!< GPIO x function configuration */ + +#define GPIO_CFGLR_IOFC0_Pos (2U) +#define GPIO_CFGLR_IOFC0_Msk (0x3U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x0000000C */ +#define GPIO_CFGLR_IOFC0 GPIO_CFGLR_IOFC0_Msk /*!< IOFC0[1:0] bits (GPIO x function configuration, pin 0) */ +#define GPIO_CFGLR_IOFC0_0 (0x1U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000004 */ +#define GPIO_CFGLR_IOFC0_1 (0x2U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000008 */ + +#define GPIO_CFGLR_IOFC1_Pos (6U) +#define GPIO_CFGLR_IOFC1_Msk (0x3U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGLR_IOFC1 GPIO_CFGLR_IOFC1_Msk /*!< IOFC1[1:0] bits (GPIO x function configuration, pin 1) */ +#define GPIO_CFGLR_IOFC1_0 (0x1U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000040 */ +#define GPIO_CFGLR_IOFC1_1 (0x2U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000080 */ + +#define GPIO_CFGLR_IOFC2_Pos (10U) +#define GPIO_CFGLR_IOFC2_Msk (0x3U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGLR_IOFC2 GPIO_CFGLR_IOFC2_Msk /*!< IOFC2[1:0] bits (GPIO x function configuration, pin 2) */ +#define GPIO_CFGLR_IOFC2_0 (0x1U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000400 */ +#define GPIO_CFGLR_IOFC2_1 (0x2U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000800 */ + +#define GPIO_CFGLR_IOFC3_Pos (14U) +#define GPIO_CFGLR_IOFC3_Msk (0x3U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGLR_IOFC3 GPIO_CFGLR_IOFC3_Msk /*!< IOFC3[1:0] bits (GPIO x function configuration, pin 3) */ +#define GPIO_CFGLR_IOFC3_0 (0x1U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00004000 */ +#define GPIO_CFGLR_IOFC3_1 (0x2U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00008000 */ + +#define GPIO_CFGLR_IOFC4_Pos (18U) +#define GPIO_CFGLR_IOFC4_Msk (0x3U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGLR_IOFC4 GPIO_CFGLR_IOFC4_Msk /*!< IOFC4[1:0] bits (GPIO x function configuration, pin 4) */ +#define GPIO_CFGLR_IOFC4_0 (0x1U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00040000 */ +#define GPIO_CFGLR_IOFC4_1 (0x2U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00080000 */ + +#define GPIO_CFGLR_IOFC5_Pos (22U) +#define GPIO_CFGLR_IOFC5_Msk (0x3U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGLR_IOFC5 GPIO_CFGLR_IOFC5_Msk /*!< IOFC5[1:0] bits (GPIO x function configuration, pin 5) */ +#define GPIO_CFGLR_IOFC5_0 (0x1U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00400000 */ +#define GPIO_CFGLR_IOFC5_1 (0x2U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00800000 */ + +#define GPIO_CFGLR_IOFC6_Pos (26U) +#define GPIO_CFGLR_IOFC6_Msk (0x3U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGLR_IOFC6 GPIO_CFGLR_IOFC6_Msk /*!< IOFC6[1:0] bits (GPIO x function configuration, pin 6) */ +#define GPIO_CFGLR_IOFC6_0 (0x1U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x04000000 */ +#define GPIO_CFGLR_IOFC6_1 (0x2U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x08000000 */ + +#define GPIO_CFGLR_IOFC7_Pos (30U) +#define GPIO_CFGLR_IOFC7_Msk (0x3U << GPIO_CFGLR_IOFC7_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGLR_IOFC7 GPIO_CFGLR_IOFC7_Msk /*!< IOFC7[1:0] bits (GPIO x function configuration, pin 7) */ +#define GPIO_CFGLR_IOFC7_0 (0x1U << GPIO_CFGLR_IOFC7_Pos) /*!< 0x40000000 */ +#define GPIO_CFGLR_IOFC7_1 (0x2U << GPIO_CFGLR_IOFC7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_CFGHR register ******************/ +#define GPIO_CFGHR_IOMC_Pos (0U) +#define GPIO_CFGHR_IOMC_Msk (0x33333333U << GPIO_CFGHR_IOMC_Pos) /*!< 0x33333333 */ +#define GPIO_CFGHR_IOMC GPIO_CFGHR_IOMC_Msk /*!< GPIO x mode configuration */ + +#define GPIO_CFGHR_IOMC8_Pos (0U) +#define GPIO_CFGHR_IOMC8_Msk (0x3U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000003 */ +#define GPIO_CFGHR_IOMC8 GPIO_CFGHR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ +#define GPIO_CFGHR_IOMC8_0 (0x1U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000001 */ +#define GPIO_CFGHR_IOMC8_1 (0x2U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000002 */ + +#define GPIO_CFGHR_IOMC9_Pos (4U) +#define GPIO_CFGHR_IOMC9_Msk (0x3U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000030 */ +#define GPIO_CFGHR_IOMC9 GPIO_CFGHR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ +#define GPIO_CFGHR_IOMC9_0 (0x1U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000010 */ +#define GPIO_CFGHR_IOMC9_1 (0x2U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000020 */ + +#define GPIO_CFGHR_IOMC10_Pos (8U) +#define GPIO_CFGHR_IOMC10_Msk (0x3U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000300 */ +#define GPIO_CFGHR_IOMC10 GPIO_CFGHR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ +#define GPIO_CFGHR_IOMC10_0 (0x1U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000100 */ +#define GPIO_CFGHR_IOMC10_1 (0x2U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000200 */ + +#define GPIO_CFGHR_IOMC11_Pos (12U) +#define GPIO_CFGHR_IOMC11_Msk (0x3U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00003000 */ +#define GPIO_CFGHR_IOMC11 GPIO_CFGHR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ +#define GPIO_CFGHR_IOMC11_0 (0x1U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00001000 */ +#define GPIO_CFGHR_IOMC11_1 (0x2U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00002000 */ + +#define GPIO_CFGHR_IOMC12_Pos (16U) +#define GPIO_CFGHR_IOMC12_Msk (0x3U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00030000 */ +#define GPIO_CFGHR_IOMC12 GPIO_CFGHR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ +#define GPIO_CFGHR_IOMC12_0 (0x1U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00010000 */ +#define GPIO_CFGHR_IOMC12_1 (0x2U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00020000 */ + +#define GPIO_CFGHR_IOMC13_Pos (20U) +#define GPIO_CFGHR_IOMC13_Msk (0x3U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00300000 */ +#define GPIO_CFGHR_IOMC13 GPIO_CFGHR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ +#define GPIO_CFGHR_IOMC13_0 (0x1U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00100000 */ +#define GPIO_CFGHR_IOMC13_1 (0x2U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00200000 */ + +#define GPIO_CFGHR_IOMC14_Pos (24U) +#define GPIO_CFGHR_IOMC14_Msk (0x3U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x03000000 */ +#define GPIO_CFGHR_IOMC14 GPIO_CFGHR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ +#define GPIO_CFGHR_IOMC14_0 (0x1U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x01000000 */ +#define GPIO_CFGHR_IOMC14_1 (0x2U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x02000000 */ + +#define GPIO_CFGHR_IOMC15_Pos (28U) +#define GPIO_CFGHR_IOMC15_Msk (0x3U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x30000000 */ +#define GPIO_CFGHR_IOMC15 GPIO_CFGHR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ +#define GPIO_CFGHR_IOMC15_0 (0x1U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x10000000 */ +#define GPIO_CFGHR_IOMC15_1 (0x2U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x20000000 */ + +#define GPIO_CFGHR_IOFC_Pos (2U) +#define GPIO_CFGHR_IOFC_Msk (0x33333333U << GPIO_CFGHR_IOFC_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CFGHR_IOFC GPIO_CFGHR_IOFC_Msk /*!< GPIO x function configuration */ + +#define GPIO_CFGHR_IOFC8_Pos (2U) +#define GPIO_CFGHR_IOFC8_Msk (0x3U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x0000000C */ +#define GPIO_CFGHR_IOFC8 GPIO_CFGHR_IOFC8_Msk /*!< IOFC8[1:0] bits (GPIO x function configuration, pin 8) */ +#define GPIO_CFGHR_IOFC8_0 (0x1U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000004 */ +#define GPIO_CFGHR_IOFC8_1 (0x2U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000008 */ + +#define GPIO_CFGHR_IOFC9_Pos (6U) +#define GPIO_CFGHR_IOFC9_Msk (0x3U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGHR_IOFC9 GPIO_CFGHR_IOFC9_Msk /*!< IOFC9[1:0] bits (GPIO x function configuration, pin 9) */ +#define GPIO_CFGHR_IOFC9_0 (0x1U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000040 */ +#define GPIO_CFGHR_IOFC9_1 (0x2U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000080 */ + +#define GPIO_CFGHR_IOFC10_Pos (10U) +#define GPIO_CFGHR_IOFC10_Msk (0x3U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGHR_IOFC10 GPIO_CFGHR_IOFC10_Msk /*!< IOFC10[1:0] bits (GPIO x function configuration, pin 10) */ +#define GPIO_CFGHR_IOFC10_0 (0x1U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000400 */ +#define GPIO_CFGHR_IOFC10_1 (0x2U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000800 */ + +#define GPIO_CFGHR_IOFC11_Pos (14U) +#define GPIO_CFGHR_IOFC11_Msk (0x3U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGHR_IOFC11 GPIO_CFGHR_IOFC11_Msk /*!< IOFC11[1:0] bits (GPIO x function configuration, pin 11) */ +#define GPIO_CFGHR_IOFC11_0 (0x1U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00004000 */ +#define GPIO_CFGHR_IOFC11_1 (0x2U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00008000 */ + +#define GPIO_CFGHR_IOFC12_Pos (18U) +#define GPIO_CFGHR_IOFC12_Msk (0x3U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGHR_IOFC12 GPIO_CFGHR_IOFC12_Msk /*!< IOFC12[1:0] bits (GPIO x function configuration, pin 12) */ +#define GPIO_CFGHR_IOFC12_0 (0x1U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00040000 */ +#define GPIO_CFGHR_IOFC12_1 (0x2U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00080000 */ + +#define GPIO_CFGHR_IOFC13_Pos (22U) +#define GPIO_CFGHR_IOFC13_Msk (0x3U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGHR_IOFC13 GPIO_CFGHR_IOFC13_Msk /*!< IOFC13[1:0] bits (GPIO x function configuration, pin 13) */ +#define GPIO_CFGHR_IOFC13_0 (0x1U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00400000 */ +#define GPIO_CFGHR_IOFC13_1 (0x2U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00800000 */ + +#define GPIO_CFGHR_IOFC14_Pos (26U) +#define GPIO_CFGHR_IOFC14_Msk (0x3U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGHR_IOFC14 GPIO_CFGHR_IOFC14_Msk /*!< IOFC14[1:0] bits (GPIO x function configuration, pin 14) */ +#define GPIO_CFGHR_IOFC14_0 (0x1U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x04000000 */ +#define GPIO_CFGHR_IOFC14_1 (0x2U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x08000000 */ + +#define GPIO_CFGHR_IOFC15_Pos (30U) +#define GPIO_CFGHR_IOFC15_Msk (0x3U << GPIO_CFGHR_IOFC15_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGHR_IOFC15 GPIO_CFGHR_IOFC15_Msk /*!< IOFC15[1:0] bits (GPIO x function configuration, pin 15) */ +#define GPIO_CFGHR_IOFC15_0 (0x1U << GPIO_CFGHR_IOFC15_Pos) /*!< 0x40000000 */ +#define GPIO_CFGHR_IOFC15_1 (0x2U << GPIO_CFGHR_IOFC15_Pos) /*!< 0x80000000 */ + +/*!<**************** Bit definition for GPIO_IDT register *******************/ +#define GPIO_IDT_IDT0_Pos (0U) +#define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, bit 0 */ +#define GPIO_IDT_IDT1_Pos (1U) +#define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, bit 1 */ +#define GPIO_IDT_IDT2_Pos (2U) +#define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, bit 2 */ +#define GPIO_IDT_IDT3_Pos (3U) +#define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, bit 3 */ +#define GPIO_IDT_IDT4_Pos (4U) +#define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, bit 4 */ +#define GPIO_IDT_IDT5_Pos (5U) +#define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, bit 5 */ +#define GPIO_IDT_IDT6_Pos (6U) +#define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, bit 6 */ +#define GPIO_IDT_IDT7_Pos (7U) +#define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, bit 7 */ +#define GPIO_IDT_IDT8_Pos (8U) +#define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, bit 8 */ +#define GPIO_IDT_IDT9_Pos (9U) +#define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, bit 9 */ +#define GPIO_IDT_IDT10_Pos (10U) +#define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, bit 10 */ +#define GPIO_IDT_IDT11_Pos (11U) +#define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, bit 11 */ +#define GPIO_IDT_IDT12_Pos (12U) +#define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, bit 12 */ +#define GPIO_IDT_IDT13_Pos (13U) +#define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, bit 13 */ +#define GPIO_IDT_IDT14_Pos (14U) +#define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, bit 14 */ +#define GPIO_IDT_IDT15_Pos (15U) +#define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, bit 15 */ + +/******************* Bit definition for GPIO_ODT register *******************/ +#define GPIO_ODT_ODT0_Pos (0U) +#define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, bit 0 */ +#define GPIO_ODT_ODT1_Pos (1U) +#define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, bit 1 */ +#define GPIO_ODT_ODT2_Pos (2U) +#define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, bit 2 */ +#define GPIO_ODT_ODT3_Pos (3U) +#define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, bit 3 */ +#define GPIO_ODT_ODT4_Pos (4U) +#define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, bit 4 */ +#define GPIO_ODT_ODT5_Pos (5U) +#define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, bit 5 */ +#define GPIO_ODT_ODT6_Pos (6U) +#define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, bit 6 */ +#define GPIO_ODT_ODT7_Pos (7U) +#define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, bit 7 */ +#define GPIO_ODT_ODT8_Pos (8U) +#define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, bit 8 */ +#define GPIO_ODT_ODT9_Pos (9U) +#define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, bit 9 */ +#define GPIO_ODT_ODT10_Pos (10U) +#define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, bit 10 */ +#define GPIO_ODT_ODT11_Pos (11U) +#define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, bit 11 */ +#define GPIO_ODT_ODT12_Pos (12U) +#define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, bit 12 */ +#define GPIO_ODT_ODT13_Pos (13U) +#define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, bit 13 */ +#define GPIO_ODT_ODT14_Pos (14U) +#define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, bit 14 */ +#define GPIO_ODT_ODT15_Pos (15U) +#define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, bit 15 */ + +/******************* Bit definition for GPIO_SCR register *******************/ +#define GPIO_SCR_IOSB0_Pos (0U) +#define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit 0 */ +#define GPIO_SCR_IOSB1_Pos (1U) +#define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit 1 */ +#define GPIO_SCR_IOSB2_Pos (2U) +#define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit 2 */ +#define GPIO_SCR_IOSB3_Pos (3U) +#define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit 3 */ +#define GPIO_SCR_IOSB4_Pos (4U) +#define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit 4 */ +#define GPIO_SCR_IOSB5_Pos (5U) +#define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit 5 */ +#define GPIO_SCR_IOSB6_Pos (6U) +#define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit 6 */ +#define GPIO_SCR_IOSB7_Pos (7U) +#define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit 7 */ +#define GPIO_SCR_IOSB8_Pos (8U) +#define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit 8 */ +#define GPIO_SCR_IOSB9_Pos (9U) +#define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit 9 */ +#define GPIO_SCR_IOSB10_Pos (10U) +#define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit 10 */ +#define GPIO_SCR_IOSB11_Pos (11U) +#define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit 11 */ +#define GPIO_SCR_IOSB12_Pos (12U) +#define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit 12 */ +#define GPIO_SCR_IOSB13_Pos (13U) +#define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit 13 */ +#define GPIO_SCR_IOSB14_Pos (14U) +#define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit 14 */ +#define GPIO_SCR_IOSB15_Pos (15U) +#define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit 15 */ +#define GPIO_SCR_IOCB0_Pos (16U) +#define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_SCR_IOCB1_Pos (17U) +#define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_SCR_IOCB2_Pos (18U) +#define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_SCR_IOCB3_Pos (19U) +#define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_SCR_IOCB4_Pos (20U) +#define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_SCR_IOCB5_Pos (21U) +#define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_SCR_IOCB6_Pos (22U) +#define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_SCR_IOCB7_Pos (23U) +#define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_SCR_IOCB8_Pos (24U) +#define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_SCR_IOCB9_Pos (25U) +#define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_SCR_IOCB10_Pos (26U) +#define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_SCR_IOCB11_Pos (27U) +#define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_SCR_IOCB12_Pos (28U) +#define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_SCR_IOCB13_Pos (29U) +#define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_SCR_IOCB14_Pos (30U) +#define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_SCR_IOCB15_Pos (31U) +#define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit 15 */ + +/******************* Bit definition for GPIO_CLR register *******************/ +#define GPIO_CLR_IOCB0_Pos (0U) +#define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_CLR_IOCB1_Pos (1U) +#define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_CLR_IOCB2_Pos (2U) +#define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_CLR_IOCB3_Pos (3U) +#define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_CLR_IOCB4_Pos (4U) +#define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_CLR_IOCB5_Pos (5U) +#define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_CLR_IOCB6_Pos (6U) +#define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_CLR_IOCB7_Pos (7U) +#define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_CLR_IOCB8_Pos (8U) +#define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_CLR_IOCB9_Pos (9U) +#define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_CLR_IOCB10_Pos (10U) +#define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_CLR_IOCB11_Pos (11U) +#define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_CLR_IOCB12_Pos (12U) +#define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_CLR_IOCB13_Pos (13U) +#define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_CLR_IOCB14_Pos (14U) +#define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_CLR_IOCB15_Pos (15U) +#define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit 15 */ + +/******************* Bit definition for GPIO_WPR register *******************/ +#define GPIO_WPR_WPEN0_Pos (0U) +#define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable bit 0 */ +#define GPIO_WPR_WPEN1_Pos (1U) +#define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable bit 1 */ +#define GPIO_WPR_WPEN2_Pos (2U) +#define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable bit 2 */ +#define GPIO_WPR_WPEN3_Pos (3U) +#define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable bit 3 */ +#define GPIO_WPR_WPEN4_Pos (4U) +#define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable bit 4 */ +#define GPIO_WPR_WPEN5_Pos (5U) +#define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable bit 5 */ +#define GPIO_WPR_WPEN6_Pos (6U) +#define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable bit 6 */ +#define GPIO_WPR_WPEN7_Pos (7U) +#define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable bit 7 */ +#define GPIO_WPR_WPEN8_Pos (8U) +#define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable bit 8 */ +#define GPIO_WPR_WPEN9_Pos (9U) +#define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable bit 9 */ +#define GPIO_WPR_WPEN10_Pos (10U) +#define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable bit 10 */ +#define GPIO_WPR_WPEN11_Pos (11U) +#define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable bit 11 */ +#define GPIO_WPR_WPEN12_Pos (12U) +#define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable bit 12 */ +#define GPIO_WPR_WPEN13_Pos (13U) +#define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable bit 13 */ +#define GPIO_WPR_WPEN14_Pos (14U) +#define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable bit 14 */ +#define GPIO_WPR_WPEN15_Pos (15U) +#define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable bit 15 */ +#define GPIO_WPR_WPSEQ_Pos (16U) +#define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ +#define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ + +/******************************************************************************/ +/* */ +/* Multiplex function I/Os (IOMUX) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for IOMUX_EVTOUT register *****************/ +/*!< SELPIN configuration */ +#define IOMUX_EVTOUT_SELPIN_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_Msk (0xFU << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x0000000F */ +#define IOMUX_EVTOUT_SELPIN IOMUX_EVTOUT_SELPIN_Msk /*!< SELPIN[3:0] bits (Selection IO pin) */ +#define IOMUX_EVTOUT_SELPIN_0 (0x1U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000001 */ +#define IOMUX_EVTOUT_SELPIN_1 (0x2U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000002 */ +#define IOMUX_EVTOUT_SELPIN_2 (0x4U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000004 */ +#define IOMUX_EVTOUT_SELPIN_3 (0x8U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000008 */ + +#define IOMUX_EVTOUT_SELPIN_PIN0 0x00000000U /*!< Pin 0 */ +#define IOMUX_EVTOUT_SELPIN_PIN1_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN1_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN1_Pos) /*!< 0x00000001 */ +#define IOMUX_EVTOUT_SELPIN_PIN1 IOMUX_EVTOUT_SELPIN_PIN1_Msk /*!< Pin 1 */ +#define IOMUX_EVTOUT_SELPIN_PIN2_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN2_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN2_Pos) /*!< 0x00000002 */ +#define IOMUX_EVTOUT_SELPIN_PIN2 IOMUX_EVTOUT_SELPIN_PIN2_Msk /*!< Pin 2 */ +#define IOMUX_EVTOUT_SELPIN_PIN3_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN3_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN3_Pos) /*!< 0x00000003 */ +#define IOMUX_EVTOUT_SELPIN_PIN3 IOMUX_EVTOUT_SELPIN_PIN3_Msk /*!< Pin 3 */ +#define IOMUX_EVTOUT_SELPIN_PIN4_Pos (2U) +#define IOMUX_EVTOUT_SELPIN_PIN4_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN4_Pos) /*!< 0x00000004 */ +#define IOMUX_EVTOUT_SELPIN_PIN4 IOMUX_EVTOUT_SELPIN_PIN4_Msk /*!< Pin 4 */ +#define IOMUX_EVTOUT_SELPIN_PIN5_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN5_Msk (0x5U << IOMUX_EVTOUT_SELPIN_PIN5_Pos) /*!< 0x00000005 */ +#define IOMUX_EVTOUT_SELPIN_PIN5 IOMUX_EVTOUT_SELPIN_PIN5_Msk /*!< Pin 5 */ +#define IOMUX_EVTOUT_SELPIN_PIN6_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN6_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN6_Pos) /*!< 0x00000006 */ +#define IOMUX_EVTOUT_SELPIN_PIN6 IOMUX_EVTOUT_SELPIN_PIN6_Msk /*!< Pin 6 */ +#define IOMUX_EVTOUT_SELPIN_PIN7_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN7_Msk (0x7U << IOMUX_EVTOUT_SELPIN_PIN7_Pos) /*!< 0x00000007 */ +#define IOMUX_EVTOUT_SELPIN_PIN7 IOMUX_EVTOUT_SELPIN_PIN7_Msk /*!< Pin 7 */ +#define IOMUX_EVTOUT_SELPIN_PIN8_Pos (3U) +#define IOMUX_EVTOUT_SELPIN_PIN8_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN8_Pos) /*!< 0x00000008 */ +#define IOMUX_EVTOUT_SELPIN_PIN8 IOMUX_EVTOUT_SELPIN_PIN8_Msk /*!< Pin 8 */ +#define IOMUX_EVTOUT_SELPIN_PIN9_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN9_Msk (0x9U << IOMUX_EVTOUT_SELPIN_PIN9_Pos) /*!< 0x00000009 */ +#define IOMUX_EVTOUT_SELPIN_PIN9 IOMUX_EVTOUT_SELPIN_PIN9_Msk /*!< Pin 9 */ +#define IOMUX_EVTOUT_SELPIN_PIN10_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN10_Msk (0x5U << IOMUX_EVTOUT_SELPIN_PIN10_Pos) /*!< 0x0000000A */ +#define IOMUX_EVTOUT_SELPIN_PIN10 IOMUX_EVTOUT_SELPIN_PIN10_Msk /*!< Pin 10 */ +#define IOMUX_EVTOUT_SELPIN_PIN11_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN11_Msk (0xBU << IOMUX_EVTOUT_SELPIN_PIN11_Pos) /*!< 0x0000000B */ +#define IOMUX_EVTOUT_SELPIN_PIN11 IOMUX_EVTOUT_SELPIN_PIN11_Msk /*!< Pin 11 */ +#define IOMUX_EVTOUT_SELPIN_PIN12_Pos (2U) +#define IOMUX_EVTOUT_SELPIN_PIN12_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN12_Pos) /*!< 0x0000000C */ +#define IOMUX_EVTOUT_SELPIN_PIN12 IOMUX_EVTOUT_SELPIN_PIN12_Msk /*!< Pin 12 */ +#define IOMUX_EVTOUT_SELPIN_PIN13_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN13_Msk (0xDU << IOMUX_EVTOUT_SELPIN_PIN13_Pos) /*!< 0x0000000D */ +#define IOMUX_EVTOUT_SELPIN_PIN13 IOMUX_EVTOUT_SELPIN_PIN13_Msk /*!< Pin 13 */ +#define IOMUX_EVTOUT_SELPIN_PIN14_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN14_Msk (0x7U << IOMUX_EVTOUT_SELPIN_PIN14_Pos) /*!< 0x0000000E */ +#define IOMUX_EVTOUT_SELPIN_PIN14 IOMUX_EVTOUT_SELPIN_PIN14_Msk /*!< Pin 14 */ +#define IOMUX_EVTOUT_SELPIN_PIN15_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN15_Msk (0xFU << IOMUX_EVTOUT_SELPIN_PIN15_Pos) /*!< 0x0000000F */ +#define IOMUX_EVTOUT_SELPIN_PIN15 IOMUX_EVTOUT_SELPIN_PIN15_Msk /*!< Pin 15 */ + +/*!< SELPORT configuration */ +#define IOMUX_EVTOUT_SELPORT_Pos (4U) +#define IOMUX_EVTOUT_SELPORT_Msk (0x7U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000070 */ +#define IOMUX_EVTOUT_SELPORT IOMUX_EVTOUT_SELPORT_Msk /*!< SELPORT[2:0] bits (Selection IO port) */ +#define IOMUX_EVTOUT_SELPORT_0 (0x1U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000010 */ +#define IOMUX_EVTOUT_SELPORT_1 (0x2U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000020 */ +#define IOMUX_EVTOUT_SELPORT_2 (0x4U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000040 */ + +#define IOMUX_EVTOUT_SELPORT_GPIOA 0x00000000 /*!< GPIOA */ +#define IOMUX_EVTOUT_SELPORT_GPIOB_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_EVTOUT_SELPORT_GPIOB_Msk (0x1U << IOMUX_EVTOUT_SELPORT_GPIOB_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOB IOMUX_EVTOUT_SELPORT_GPIOB_Msk /*!< GPIOB */ +#define IOMUX_EVTOUT_SELPORT_GPIOC_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_EVTOUT_SELPORT_GPIOC_Msk (0x1U << IOMUX_EVTOUT_SELPORT_GPIOC_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOC IOMUX_EVTOUT_SELPORT_GPIOC_Msk /*!< GPIOC */ +#define IOMUX_EVTOUT_SELPORT_GPIOD_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_EVTOUT_SELPORT_GPIOD_Msk (0x3U << IOMUX_EVTOUT_SELPORT_GPIOD_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOD IOMUX_EVTOUT_SELPORT_GPIOD_Msk /*!< GPIOD */ +#define IOMUX_EVTOUT_SELPORT_GPIOF_Pos (4U) /*!< 0x00000050 */ +#define IOMUX_EVTOUT_SELPORT_GPIOF_Msk (0x5U << IOMUX_EVTOUT_SELPORT_GPIOF_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOF IOMUX_EVTOUT_SELPORT_GPIOF_Msk /*!< GPIOF */ + +#define IOMUX_EVTOUT_EVOEN_Pos (7U) +#define IOMUX_EVTOUT_EVOEN_Msk (0x1U << IOMUX_EVTOUT_EVOEN_Pos) /*!< 0x00000080 */ +#define IOMUX_EVTOUT_EVOEN IOMUX_EVTOUT_EVOEN_Msk /*!< Event output enable */ + +/***************** Bit definition for IOMUX_REMAP register ******************/ +/*!< SPI1_MUX configuration */ +#define IOMUX_REMAP_SPI1_MUX_Pos (0U) +#define IOMUX_REMAP_SPI1_MUX_Msk (0x1U << IOMUX_REMAP_SPI1_MUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP_SPI1_MUX IOMUX_REMAP_SPI1_MUX_Msk /*!< SPI1 IO multiplexing */ +#define IOMUX_REMAP_I2C1_MUX_Pos (1U) +#define IOMUX_REMAP_I2C1_MUX_Msk (0x1U << IOMUX_REMAP_I2C1_MUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP_I2C1_MUX IOMUX_REMAP_I2C1_MUX_Msk /*!< I2C1 IO multiplexing */ +#define IOMUX_REMAP_USART1_MUX_Pos (2U) +#define IOMUX_REMAP_USART1_MUX_Msk (0x1U << IOMUX_REMAP_USART1_MUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP_USART1_MUX IOMUX_REMAP_USART1_MUX_Msk /*!< USART1 IO multiplexing */ + +/*!< USART3_MUX configuration */ +#define IOMUX_REMAP_USART3_MUX_Pos (4U) +#define IOMUX_REMAP_USART3_MUX_Msk (0x3U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000030 */ +#define IOMUX_REMAP_USART3_MUX IOMUX_REMAP_USART3_MUX_Msk /*!< USART3_MUX[1:0] bits (USART3 IO multiplexing) */ +#define IOMUX_REMAP_USART3_MUX_0 (0x1U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_1 (0x2U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000020 */ + +#define IOMUX_REMAP_USART3_MUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX1_Pos) +#define IOMUX_REMAP_USART3_MUX_MUX1 IOMUX_REMAP_USART3_MUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP_USART3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX2_Pos) +#define IOMUX_REMAP_USART3_MUX_MUX2 IOMUX_REMAP_USART3_MUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ + +/*!< TMR1_MUX configuration */ +#define IOMUX_REMAP_TMR1_MUX_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_Msk (0x3U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x000000C0 */ +#define IOMUX_REMAP_TMR1_MUX IOMUX_REMAP_TMR1_MUX_Msk /*!< TMR1_MUX[1:0] bits (TMR1 IO multiplexing) */ +#define IOMUX_REMAP_TMR1_MUX_0 (0x1U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_1 (0x2U << IOMUX_REMAP_TMR1_MUX_Pos /*!< 0x00000080 */ + +#define IOMUX_REMAP_TMR1_MUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX1_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1 IOMUX_REMAP_TMR1_MUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ + +/*!< TMR2_MUX configuration */ +#define IOMUX_REMAP_TMR2_MUX_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX IOMUX_REMAP_TMR2_MUX_Msk /*!< TMR2_MUX[1:0] bits (TMR2 IO multiplexing) */ +#define IOMUX_REMAP_TMR2_MUX_0 (0x1U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_1 (0x2U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000200 */ + +#define IOMUX_REMAP_TMR2_MUX_MUX0 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX1_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1 IOMUX_REMAP_TMR2_MUX_MUX1_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (9U) +#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ + +/*!< TMR3_MUX configuration */ +#define IOMUX_REMAP_TMR3_MUX_Pos (10U) +#define IOMUX_REMAP_TMR3_MUX_Msk (0x3U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000C00 */ +#define IOMUX_REMAP_TMR3_MUX IOMUX_REMAP_TMR3_MUX_Msk /*!< TMR3_MUX[1:0] bits (TMR3 IO multiplexing) */ +#define IOMUX_REMAP_TMR3_MUX_0 (0x1U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP_TMR3_MUX_1 (0x2U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP_TMR3_MUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX2_Pos (11U) +#define IOMUX_REMAP_TMR3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR3_MUX_MUX2_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP_TMR3_MUX_MUX2 IOMUX_REMAP_TMR3_MUX_MUX2_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX3_Pos (10U) +#define IOMUX_REMAP_TMR3_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR3_MUX_MUX3_Pos) /*!< 0x00000C00 */ +#define IOMUX_REMAP_TMR3_MUX_MUX3 IOMUX_REMAP_TMR3_MUX_MUX3_Msk /*!< CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9 */ + +/*!< CAN1_MUX configuration */ +#define IOMUX_REMAP_CAN1_MUX_Pos (13U) +#define IOMUX_REMAP_CAN1_MUX_Msk (0x3U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00006000 */ +#define IOMUX_REMAP_CAN1_MUX IOMUX_REMAP_CAN1_MUX_Msk /*!< CAN1_MUX[1:0] bits (CAN1 IO multiplexing) */ +#define IOMUX_REMAP_CAN1_MUX_0 (0x1U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00002000 */ +#define IOMUX_REMAP_CAN1_MUX_1 (0x2U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00004000 */ + +#define IOMUX_REMAP_CAN1_MUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP_CAN1_MUX_MUX2_Pos (14U) +#define IOMUX_REMAP_CAN1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_CAN1_MUX_MUX2_Pos) /*!< 0x00004000 */ +#define IOMUX_REMAP_CAN1_MUX_MUX2 IOMUX_REMAP_CAN1_MUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + +#define IOMUX_REMAP_PD01_MUX_Pos (15U) +#define IOMUX_REMAP_PD01_MUX_Msk (0x1U << IOMUX_REMAP_PD01_MUX_Pos) /*!< 0x00008000 */ +#define IOMUX_REMAP_PD01_MUX IOMUX_REMAP_PD01_MUX_Msk /*!< PD0/PD1 mapped on HEXT_IN/HEXT_OUT */ +#define IOMUX_REMAP_TMR5CH4_MUX_Pos (16U) +#define IOMUX_REMAP_TMR5CH4_MUX_Msk (0x1U << IOMUX_REMAP_TMR5CH4_MUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP_TMR5CH4_MUX IOMUX_REMAP_TMR5CH4_MUX_Msk /*!< TMR5 channel 4 multiplexing */ +#define IOMUX_REMAP_ADC1_ETP_MUX_Pos (17U) +#define IOMUX_REMAP_ADC1_ETP_MUX_Msk (0x1U << IOMUX_REMAP_ADC1_ETP_MUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP_ADC1_ETP_MUX IOMUX_REMAP_ADC1_ETP_MUX_Msk /*!< ADC1 external trigger preempted conversion multiplexing */ +#define IOMUX_REMAP_ADC1_ETO_MUX_Pos (18U) +#define IOMUX_REMAP_ADC1_ETO_MUX_Msk (0x1U << IOMUX_REMAP_ADC1_ETO_MUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP_ADC1_ETO_MUX IOMUX_REMAP_ADC1_ETO_MUX_Msk /*!< ADC1 external trigger regular conversion mutiplexing */ + +/*!< SWJTAG_MUX configuration */ +#define IOMUX_REMAP_SWJTAG_MUX_Pos (24U) +#define IOMUX_REMAP_SWJTAG_MUX_Msk (0x7U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x07000000 */ +#define IOMUX_REMAP_SWJTAG_MUX IOMUX_REMAP_SWJTAG_MUX_Msk /*!< SWJTAG_MUX[2:0] bits (SWD JTAG mutiplexing) */ +#define IOMUX_REMAP_SWJTAG_MUX_0 (0x1U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x01000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_1 (0x2U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x02000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_2 (0x4U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x04000000 */ + +#define IOMUX_REMAP_SWJTAG_MUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIOs */ +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Pos (25U) /*!< 0x02000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Msk /*!< Supports SWD but JTAG is disabled. PA15/PB3/PB4 can be used as GPIOs */ +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE_Pos (26U) /*!< 0x04000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_DISABLE_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE IOMUX_REMAP_SWJTAG_MUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIOs */ + +/**************** Bit definition for IOMUX_EXINTC1 register *****************/ +/*!< EXINT0 configuration */ +#define IOMUX_EXINTC1_EXINT0_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_Msk (0xFU << IOMUX_EXINTC1_EXINT0_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC1_EXINT0 IOMUX_EXINTC1_EXINT0_Msk /*!< EXINT0[3:0] bits (EXINT0 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT0_GPA 0x00000000U /*!< GPIOA pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPB_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC1_EXINT0_GPB IOMUX_EXINTC1_EXINT0_GPB_Msk /*!< GPIOB pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPC_Pos (1U) +#define IOMUX_EXINTC1_EXINT0_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC1_EXINT0_GPC IOMUX_EXINTC1_EXINT0_GPC_Msk /*!< GPIOC pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPD_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT0_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC1_EXINT0_GPD IOMUX_EXINTC1_EXINT0_GPD_Msk /*!< GPIOD pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPF_Pos (2U) +#define IOMUX_EXINTC1_EXINT0_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC1_EXINT0_GPF IOMUX_EXINTC1_EXINT0_GPF_Msk /*!< GPIOF pin 0 */ + +/*!< EXINT1 configuration */ +#define IOMUX_EXINTC1_EXINT1_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_Msk (0xFU << IOMUX_EXINTC1_EXINT1_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC1_EXINT1 IOMUX_EXINTC1_EXINT1_Msk /*!< EXINT1[3:0] bits (EXINT1 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT1_GPA 0x00000000U /*!< GPIOA pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPB_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC1_EXINT1_GPB IOMUX_EXINTC1_EXINT1_GPB_Msk /*!< GPIOB pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPC_Pos (5U) +#define IOMUX_EXINTC1_EXINT1_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC1_EXINT1_GPC IOMUX_EXINTC1_EXINT1_GPC_Msk /*!< GPIOC pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPD_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT1_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC1_EXINT1_GPD IOMUX_EXINTC1_EXINT1_GPD_Msk /*!< GPIOD pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPF_Pos (6U) +#define IOMUX_EXINTC1_EXINT1_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC1_EXINT1_GPF IOMUX_EXINTC1_EXINT1_GPF_Msk /*!< GPIOF pin 1 */ + +/*!< EXINT2 configuration */ +#define IOMUX_EXINTC1_EXINT2_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_Msk (0xFU << IOMUX_EXINTC1_EXINT2_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC1_EXINT2 IOMUX_EXINTC1_EXINT2_Msk /*!< EXINT2[3:0] bits (EXINT2 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT2_GPA 0x00000000U /*!< GPIOA pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPB_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC1_EXINT2_GPB IOMUX_EXINTC1_EXINT2_GPB_Msk /*!< GPIOB pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPC_Pos (9U) +#define IOMUX_EXINTC1_EXINT2_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC1_EXINT2_GPC IOMUX_EXINTC1_EXINT2_GPC_Msk /*!< GPIOC pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPD_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT2_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC1_EXINT2_GPD IOMUX_EXINTC1_EXINT2_GPD_Msk /*!< GPIOD pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPF_Pos (10U) +#define IOMUX_EXINTC1_EXINT2_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC1_EXINT2_GPF IOMUX_EXINTC1_EXINT2_GPF_Msk /*!< GPIOF pin 2 */ + +/*!< EXINT3 configuration */ +#define IOMUX_EXINTC1_EXINT3_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_Msk (0xFU << IOMUX_EXINTC1_EXINT3_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC1_EXINT3 IOMUX_EXINTC1_EXINT3_Msk /*!< EXINT3[3:0] bits (EXINT3 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT3_GPA 0x00000000U /*!< GPIOA pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPB_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC1_EXINT3_GPB IOMUX_EXINTC1_EXINT3_GPB_Msk /*!< GPIOB pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPC_Pos (13U) +#define IOMUX_EXINTC1_EXINT3_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC1_EXINT3_GPC IOMUX_EXINTC1_EXINT3_GPC_Msk /*!< GPIOC pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPD_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT3_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC1_EXINT3_GPD IOMUX_EXINTC1_EXINT3_GPD_Msk /*!< GPIOD pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPF_Pos (14U) +#define IOMUX_EXINTC1_EXINT3_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC1_EXINT3_GPF IOMUX_EXINTC1_EXINT3_GPF_Msk /*!< GPIOF pin 3 */ + +/**************** Bit definition for IOMUX_EXINTC2 register *****************/ +/*!< EXINT4 configuration */ +#define IOMUX_EXINTC2_EXINT4_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_Msk (0xFU << IOMUX_EXINTC2_EXINT4_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC2_EXINT4 IOMUX_EXINTC2_EXINT4_Msk /*!< EXINT4[3:0] bits (EXINT4 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT4_GPA 0x00000000U /*!< GPIOA pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPB_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC2_EXINT4_GPB IOMUX_EXINTC2_EXINT4_GPB_Msk /*!< GPIOB pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPC_Pos (1U) +#define IOMUX_EXINTC2_EXINT4_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC2_EXINT4_GPC IOMUX_EXINTC2_EXINT4_GPC_Msk /*!< GPIOC pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPD_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT4_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC2_EXINT4_GPD IOMUX_EXINTC2_EXINT4_GPD_Msk /*!< GPIOD pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPF_Pos (2U) +#define IOMUX_EXINTC2_EXINT4_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC2_EXINT4_GPF IOMUX_EXINTC2_EXINT4_GPF_Msk /*!< GPIOF pin 4 */ + +/* EXINT5 configuration */ +#define IOMUX_EXINTC2_EXINT5_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_Msk (0xFU << IOMUX_EXINTC2_EXINT5_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC2_EXINT5 IOMUX_EXINTC2_EXINT5_Msk /*!< EXINT5[3:0] bits (EXINT5 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT5_GPA 0x00000000U /*!< GPIOA pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPB_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC2_EXINT5_GPB IOMUX_EXINTC2_EXINT5_GPB_Msk /*!< GPIOB pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPC_Pos (5U) +#define IOMUX_EXINTC2_EXINT5_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC2_EXINT5_GPC IOMUX_EXINTC2_EXINT5_GPC_Msk /*!< GPIOC pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPD_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT5_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC2_EXINT5_GPD IOMUX_EXINTC2_EXINT5_GPD_Msk /*!< GPIOD pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPF_Pos (6U) +#define IOMUX_EXINTC2_EXINT5_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC2_EXINT5_GPF IOMUX_EXINTC2_EXINT5_GPF_Msk /*!< GPIOF pin 5 */ + +/*!< EXINT6 configuration */ +#define IOMUX_EXINTC2_EXINT6_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_Msk (0xFU << IOMUX_EXINTC2_EXINT6_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC2_EXINT6 IOMUX_EXINTC2_EXINT6_Msk /*!< EXINT6[3:0] bits (EXINT6 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT6_GPA 0x00000000U /*!< GPIOA pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPB_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC2_EXINT6_GPB IOMUX_EXINTC2_EXINT6_GPB_Msk /*!< GPIOB pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPC_Pos (9U) +#define IOMUX_EXINTC2_EXINT6_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC2_EXINT6_GPC IOMUX_EXINTC2_EXINT6_GPC_Msk /*!< GPIOC pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPD_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT6_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC2_EXINT6_GPD IOMUX_EXINTC2_EXINT6_GPD_Msk /*!< GPIOD pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPF_Pos (10U) +#define IOMUX_EXINTC2_EXINT6_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC2_EXINT6_GPF IOMUX_EXINTC2_EXINT6_GPF_Msk /*!< GPIOF pin 6 */ + +/*!< EXINT7 configuration */ +#define IOMUX_EXINTC2_EXINT7_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_Msk (0xFU << IOMUX_EXINTC2_EXINT7_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC2_EXINT7 IOMUX_EXINTC2_EXINT7_Msk /*!< EXINT7[3:0] bits (EXINT7 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT7_GPA 0x00000000U /*!< GPIOA pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPB_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC2_EXINT7_GPB IOMUX_EXINTC2_EXINT7_GPB_Msk /*!< GPIOB pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPC_Pos (13U) +#define IOMUX_EXINTC2_EXINT7_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC2_EXINT7_GPC IOMUX_EXINTC2_EXINT7_GPC_Msk /*!< GPIOC pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPD_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT7_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC2_EXINT7_GPD IOMUX_EXINTC2_EXINT7_GPD_Msk /*!< GPIOD pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPF_Pos (14U) +#define IOMUX_EXINTC2_EXINT7_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC2_EXINT7_GPF IOMUX_EXINTC2_EXINT7_GPF_Msk /*!< GPIOF pin 7 */ + +/**************** Bit definition for IOMUX_EXINTC3 register *****************/ +/*!< EXINT8 configuration */ +#define IOMUX_EXINTC3_EXINT8_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_Msk (0xFU << IOMUX_EXINTC3_EXINT8_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC3_EXINT8 IOMUX_EXINTC3_EXINT8_Msk /*!< EXINT8[3:0] bits (EXINT8 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT8_GPA 0x00000000U /*!< GPIOA pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPB_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC3_EXINT8_GPB IOMUX_EXINTC3_EXINT8_GPB_Msk /*!< GPIOB pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPC_Pos (1U) +#define IOMUX_EXINTC3_EXINT8_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC3_EXINT8_GPC IOMUX_EXINTC3_EXINT8_GPC_Msk /*!< GPIOC pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPD_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT8_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC3_EXINT8_GPD IOMUX_EXINTC3_EXINT8_GPD_Msk /*!< GPIOD pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPF_Pos (2U) +#define IOMUX_EXINTC3_EXINT8_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC3_EXINT8_GPF IOMUX_EXINTC3_EXINT8_GPF_Msk /*!< GPIOF pin 8 */ + +/*!< EXINT9 configuration */ +#define IOMUX_EXINTC3_EXINT9_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_Msk (0xFU << IOMUX_EXINTC3_EXINT9_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC3_EXINT9 IOMUX_EXINTC3_EXINT9_Msk /*!< EXINT9[3:0] bits (EXINT9 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT9_GPA 0x00000000U /*!< GPIOA pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPB_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC3_EXINT9_GPB IOMUX_EXINTC3_EXINT9_GPB_Msk /*!< GPIOB pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPC_Pos (5U) +#define IOMUX_EXINTC3_EXINT9_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC3_EXINT9_GPC IOMUX_EXINTC3_EXINT9_GPC_Msk /*!< GPIOC pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPD_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT9_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC3_EXINT9_GPD IOMUX_EXINTC3_EXINT9_GPD_Msk /*!< GPIOD pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPF_Pos (6U) +#define IOMUX_EXINTC3_EXINT9_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC3_EXINT9_GPF IOMUX_EXINTC3_EXINT9_GPF_Msk /*!< GPIOF pin 9 */ + +/*!< EXINT10 configuration */ +#define IOMUX_EXINTC3_EXINT10_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_Msk (0xFU << IOMUX_EXINTC3_EXINT10_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC3_EXINT10 IOMUX_EXINTC3_EXINT10_Msk /*!< EXINT10[3:0] bits (EXINT10 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT10_GPA 0x00000000U /*!< GPIOA pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPB_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC3_EXINT10_GPB IOMUX_EXINTC3_EXINT10_GPB_Msk /*!< GPIOB pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPC_Pos (9U) +#define IOMUX_EXINTC3_EXINT10_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC3_EXINT10_GPC IOMUX_EXINTC3_EXINT10_GPC_Msk /*!< GPIOC pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPD_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT10_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC3_EXINT10_GPD IOMUX_EXINTC3_EXINT10_GPD_Msk /*!< GPIOD pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPF_Pos (10U) +#define IOMUX_EXINTC3_EXINT10_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC3_EXINT10_GPF IOMUX_EXINTC3_EXINT10_GPF_Msk /*!< GPIOF pin 10 */ + +/*!< EXINT11 configuration */ +#define IOMUX_EXINTC3_EXINT11_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_Msk (0xFU << IOMUX_EXINTC3_EXINT11_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC3_EXINT11 IOMUX_EXINTC3_EXINT11_Msk /*!< EXINT11[3:0] bits (EXINT11 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT11_GPA 0x00000000U /*!< GPIOA pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPB_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC3_EXINT11_GPB IOMUX_EXINTC3_EXINT11_GPB_Msk /*!< GPIOB pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPC_Pos (13U) +#define IOMUX_EXINTC3_EXINT11_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC3_EXINT11_GPC IOMUX_EXINTC3_EXINT11_GPC_Msk /*!< GPIOC pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPD_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT11_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC3_EXINT11_GPD IOMUX_EXINTC3_EXINT11_GPD_Msk /*!< GPIOD pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPF_Pos (14U) +#define IOMUX_EXINTC3_EXINT11_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC3_EXINT11_GPF IOMUX_EXINTC3_EXINT11_GPF_Msk /*!< GPIOF pin 11 */ + +/**************** Bit definition for IOMUX_EXINTC4 register *****************/ +/* EXINT12 configuration */ +#define IOMUX_EXINTC4_EXINT12_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_Msk (0xFU << IOMUX_EXINTC4_EXINT12_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC4_EXINT12 IOMUX_EXINTC4_EXINT12_Msk /*!< EXINT12[3:0] bits (EXINT12 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT12_GPA 0x00000000U /*!< GPIOA pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPB_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC4_EXINT12_GPB IOMUX_EXINTC4_EXINT12_GPB_Msk /*!< GPIOB pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPC_Pos (1U) +#define IOMUX_EXINTC4_EXINT12_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC4_EXINT12_GPC IOMUX_EXINTC4_EXINT12_GPC_Msk /*!< GPIOC pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPD_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT12_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC4_EXINT12_GPD IOMUX_EXINTC4_EXINT12_GPD_Msk /*!< GPIOD pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPF_Pos (2U) +#define IOMUX_EXINTC4_EXINT12_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC4_EXINT12_GPF IOMUX_EXINTC4_EXINT12_GPF_Msk /*!< GPIOF pin 12 */ + +/* EXINT13 configuration */ +#define IOMUX_EXINTC4_EXINT13_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_Msk (0xFU << IOMUX_EXINTC4_EXINT13_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC4_EXINT13 IOMUX_EXINTC4_EXINT13_Msk /*!< EXINT13[3:0] bits (EXINT13 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT13_GPA 0x00000000U /*!< GPIOA pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPB_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC4_EXINT13_GPB IOMUX_EXINTC4_EXINT13_GPB_Msk /*!< GPIOB pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPC_Pos (5U) +#define IOMUX_EXINTC4_EXINT13_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC4_EXINT13_GPC IOMUX_EXINTC4_EXINT13_GPC_Msk /*!< GPIOC pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPD_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT13_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC4_EXINT13_GPD IOMUX_EXINTC4_EXINT13_GPD_Msk /*!< GPIOD pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPF_Pos (6U) +#define IOMUX_EXINTC4_EXINT13_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC4_EXINT13_GPF IOMUX_EXINTC4_EXINT13_GPF_Msk /*!< GPIOF pin 13 */ + +/*!< EXINT14 configuration */ +#define IOMUX_EXINTC4_EXINT14_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_Msk (0xFU << IOMUX_EXINTC4_EXINT14_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC4_EXINT14 IOMUX_EXINTC4_EXINT14_Msk /*!< EXINT14[3:0] bits (EXINT14 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT14_GPA 0x00000000U /*!< GPIOA pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPB_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC4_EXINT14_GPB IOMUX_EXINTC4_EXINT14_GPB_Msk /*!< GPIOB pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPC_Pos (9U) +#define IOMUX_EXINTC4_EXINT14_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC4_EXINT14_GPC IOMUX_EXINTC4_EXINT14_GPC_Msk /*!< GPIOC pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPD_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT14_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC4_EXINT14_GPD IOMUX_EXINTC4_EXINT14_GPD_Msk /*!< GPIOD pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPF_Pos (10U) +#define IOMUX_EXINTC4_EXINT14_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC4_EXINT14_GPF IOMUX_EXINTC4_EXINT14_GPF_Msk /*!< GPIOF pin 14 */ + +/*!< EXINT15 configuration */ +#define IOMUX_EXINTC4_EXINT15_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_Msk (0xFU << IOMUX_EXINTC4_EXINT15_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC4_EXINT15 IOMUX_EXINTC4_EXINT15_Msk /*!< EXINT15[3:0] bits (EXINT15 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT15_GPA 0x00000000U /*!< GPIOA pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPB_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC4_EXINT15_GPB IOMUX_EXINTC4_EXINT15_GPB_Msk /*!< GPIOB pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPC_Pos (13U) +#define IOMUX_EXINTC4_EXINT15_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC4_EXINT15_GPC IOMUX_EXINTC4_EXINT15_GPC_Msk /*!< GPIOC pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPD_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT15_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC4_EXINT15_GPD IOMUX_EXINTC4_EXINT15_GPD_Msk /*!< GPIOD pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPF_Pos (14U) +#define IOMUX_EXINTC4_EXINT15_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC4_EXINT15_GPF IOMUX_EXINTC4_EXINT15_GPF_Msk /*!< GPIOF pin 15 */ + +/***************** Bit definition for IOMUX_REMAP2 register *****************/ +/*!< CMP_MUX configuration */ +#define IOMUX_REMAP2_CMP_MUX_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ +#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ +#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP2_CMP_MUX_MUX0 0x00000000U /*!< CMP1_OUT is connected to PA0, CMP2_OUT is connected to PA2 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_MUX1_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX1_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1 IOMUX_REMAP2_CMP_MUX_MUX1_Msk /*!< CMP1_OUT is connected to PA6, CMP2_OUT is connected to PA7 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2_Pos (27U) +#define IOMUX_REMAP2_CMP_MUX_MUX2_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX2_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2 IOMUX_REMAP2_CMP_MUX_MUX2_Msk /*!< CMP1_OUT is connected to PA11, CMP2_OUT is connected to PA12 */ + +/***************** Bit definition for IOMUX_REMAP3 register *****************/ +/*!< TMR9_GMUX configuration */ +#define IOMUX_REMAP3_TMR9_GMUX_Pos (0U) +#define IOMUX_REMAP3_TMR9_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP3_TMR9_GMUX IOMUX_REMAP3_TMR9_GMUX_Msk /*!< TMR9_GMUX[3:0] bits (TMR9 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR9_GMUX_0 (0x1U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP3_TMR9_GMUX_1 (0x2U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_2 (0x4U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP3_TMR9_GMUX_3 (0x8U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP3_TMR9_GMUX_MUX0 0x00000000U /*!< CH1/PA2, CH2/PA3 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR9_GMUX_MUX2 IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk /*!< CH1/PB14, CH2/PB15 */ + +/*!< TMR10_GMUX configuration */ +#define IOMUX_REMAP3_TMR10_GMUX_Pos (4U) +#define IOMUX_REMAP3_TMR10_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x000000F0 */ +#define IOMUX_REMAP3_TMR10_GMUX IOMUX_REMAP3_TMR10_GMUX_Msk /*!< TMR10_GMUX[3:0] bits (TMR10 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR10_GMUX_0 (0x1U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP3_TMR10_GMUX_1 (0x2U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_2 (0x4U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP3_TMR10_GMUX_3 (0x8U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP3_TMR10_GMUX_MUX0 0x00000000U /*!< CH1/PB8 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR10_GMUX_MUX2 IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk /*!< CH1/PA6 */ + +/*!< TMR11_GMUX configuration */ +#define IOMUX_REMAP3_TMR11_GMUX_Pos (8U) +#define IOMUX_REMAP3_TMR11_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP3_TMR11_GMUX IOMUX_REMAP3_TMR11_GMUX_Msk /*!< TMR11_GMUX[3:0] bits (TMR11 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR11_GMUX_0 (0x1U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP3_TMR11_GMUX_1 (0x2U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP3_TMR11_GMUX_2 (0x4U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */ + +/***************** Bit definition for IOMUX_REMAP4 register *****************/ +/*!< TMR1_GMUX configuration */ +#define IOMUX_REMAP4_TMR1_GMUX_Pos (0U) +#define IOMUX_REMAP4_TMR1_GMUX_Msk (0xFU << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP4_TMR1_GMUX IOMUX_REMAP4_TMR1_GMUX_Msk /*!< TMR1_GMUX[3:0] bits (TMR1 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR1_GMUX_0 (0x1U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_1 (0x2U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP4_TMR1_GMUX_2 (0x4U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP4_TMR1_GMUX_3 (0x8U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP4_TMR1_GMUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX1 IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ + +/*!< TMR2_GMUX configuration */ +#define IOMUX_REMAP4_TMR2_GMUX_Pos (4U) +#define IOMUX_REMAP4_TMR2_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000070 */ +#define IOMUX_REMAP4_TMR2_GMUX IOMUX_REMAP4_TMR2_GMUX_Msk /*!< TMR2_GMUX[2:0] bits (TMR2 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR2_GMUX_0 (0x1U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_1 (0x2U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP4_TMR2_GMUX_2 (0x4U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000040 */ + +#define IOMUX_REMAP4_TMR2_GMUX_MUX0 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX1 IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ + +/*!< TMR3_GMUX configuration */ +#define IOMUX_REMAP4_TMR3_GMUX_Pos (8U) +#define IOMUX_REMAP4_TMR3_GMUX_Msk (0xFU << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP4_TMR3_GMUX IOMUX_REMAP4_TMR3_GMUX_Msk /*!< TMR3_GMUX[3:0] bits (TMR3 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR3_GMUX_0 (0x1U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_1 (0x2U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP4_TMR3_GMUX_2 (0x4U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP4_TMR3_GMUX_3 (0x8U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP4_TMR3_GMUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR3_GMUX_MUX1 IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ + +/*!< TMR5_GMUX configuration */ +#define IOMUX_REMAP4_TMR5_GMUX_Pos (16U) +#define IOMUX_REMAP4_TMR5_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00070000 */ +#define IOMUX_REMAP4_TMR5_GMUX IOMUX_REMAP4_TMR5_GMUX_Msk /*!< TMR5_GMUX[2:0] bits (TMR5 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR5_GMUX_0 (0x1U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_1 (0x2U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP4_TMR5_GMUX_2 (0x4U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00040000 */ + +#define IOMUX_REMAP4_TMR5_GMUX_MUX0 0x00000000U /*!< CH1/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR5_GMUX_MUX1 IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk /*!< CH1/PF4, CH2/PF5, CH3/PA2, CH4/PA3 */ + +#define IOMUX_REMAP4_TMR5CH4_GMUX_Pos (19U) +#define IOMUX_REMAP4_TMR5CH4_GMUX_Msk (0x1U << IOMUX_REMAP4_TMR5CH4_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP4_TMR5CH4_GMUX IOMUX_REMAP4_TMR5CH4_GMUX_Msk /*!< TMR5 channel 4 general multiplexing */ + +/***************** Bit definition for IOMUX_REMAP5 register *****************/ +/*!< I2C1_GMUX configuration */ +#define IOMUX_REMAP5_I2C1_GMUX_Pos (4U) +#define IOMUX_REMAP5_I2C1_GMUX_Msk (0xFU << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x000000F0 */ +#define IOMUX_REMAP5_I2C1_GMUX IOMUX_REMAP5_I2C1_GMUX_Msk /*!< I2C1_GMUX[3:0] bits (I2C1 IO general multiplexing) */ +#define IOMUX_REMAP5_I2C1_GMUX_0 (0x1U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_1 (0x2U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP5_I2C1_GMUX_2 (0x4U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP5_I2C1_GMUX_3 (0x8U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP5_I2C1_GMUX_MUX0 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX1 IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ + +/*!< I2C2_GMUX configuration */ +#define IOMUX_REMAP5_I2C2_GMUX_Pos (8U) +#define IOMUX_REMAP5_I2C2_GMUX_Msk (0xFU << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP5_I2C2_GMUX IOMUX_REMAP5_I2C2_GMUX_Msk /*!< I2C2_GMUX[3:0] bits (I2C2 IO general multiplexing) */ +#define IOMUX_REMAP5_I2C2_GMUX_0 (0x1U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_1 (0x2U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP5_I2C2_GMUX_2 (0x4U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP5_I2C2_GMUX_3 (0x8U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP5_I2C2_GMUX_MUX0 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX1 IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (8U) /*!< 0x00000300 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ + +/*!< SPI1_GMUX configuration */ +#define IOMUX_REMAP5_SPI1_GMUX_Pos (16U) +#define IOMUX_REMAP5_SPI1_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x000F0000 */ +#define IOMUX_REMAP5_SPI1_GMUX IOMUX_REMAP5_SPI1_GMUX_Msk /*!< SPI1_GMUX[3:0] bits (SPI1 IO general multiplexing) */ +#define IOMUX_REMAP5_SPI1_GMUX_0 (0x1U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_1 (0x2U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP5_SPI1_GMUX_2 (0x4U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP5_SPI1_GMUX_3 (0x8U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00080000 */ + +#define IOMUX_REMAP5_SPI1_GMUX_MUX0 0x00000000U /*!< CS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7, MCK/PB0 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI1_GMUX_MUX1 IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PB6 */ + +/*!< SPI2_GMUX configuration */ +#define IOMUX_REMAP5_SPI2_GMUX_Pos (20U) +#define IOMUX_REMAP5_SPI2_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00F00000 */ +#define IOMUX_REMAP5_SPI2_GMUX IOMUX_REMAP5_SPI2_GMUX_Msk /*!< SPI2_GMUX[3:0] bits (SPI2 IO general multiplexing) */ +#define IOMUX_REMAP5_SPI2_GMUX_0 (0x1U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_1 (0x2U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00200000 */ +#define IOMUX_REMAP5_SPI2_GMUX_2 (0x4U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00400000 */ +#define IOMUX_REMAP5_SPI2_GMUX_3 (0x8U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00800000 */ + +#define IOMUX_REMAP5_SPI2_GMUX_MUX0 0x00000000U /*!< CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15, MCK/PC6 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos (20U) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI2_GMUX_MUX1 IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PC7 */ + +/***************** Bit definition for IOMUX_REMAP6 register *****************/ +/*!< CAN1_GMUX configuration */ +#define IOMUX_REMAP6_CAN1_GMUX_Pos (0U) +#define IOMUX_REMAP6_CAN1_GMUX_Msk (0xFU << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP6_CAN1_GMUX IOMUX_REMAP6_CAN1_GMUX_Msk /*!< CAN1_GMUX[3:0] bits (CAN1 IO general multiplexing) */ +#define IOMUX_REMAP6_CAN1_GMUX_0 (0x1U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP6_CAN1_GMUX_1 (0x2U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_2 (0x4U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP6_CAN1_GMUX_3 (0x8U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP6_CAN1_GMUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_CAN1_GMUX_MUX2 IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + +/*!< SDIO_GMUX configuration */ +#define IOMUX_REMAP6_SDIO_GMUX_Pos (8U) +#define IOMUX_REMAP6_SDIO_GMUX_Msk (0xFU << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP6_SDIO_GMUX IOMUX_REMAP6_SDIO_GMUX_Msk /*!< SDIO_GMUX[3:0] bits (SDIO IO general multiplexing) */ +#define IOMUX_REMAP6_SDIO_GMUX_0 (0x1U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP6_SDIO_GMUX_1 (0x2U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP6_SDIO_GMUX_2 (0x4U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_3 (0x8U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP6_SDIO_GMUX_MUX0 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (10U) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000500 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos (9U) /*!< 0x00000600 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX6 IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos (8U) /*!< 0x00000700 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX7 IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ + +/*!< USART1_GMUX configuration */ +#define IOMUX_REMAP6_USART1_GMUX_Pos (16U) +#define IOMUX_REMAP6_USART1_GMUX_Msk (0xFU << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x000F0000 */ +#define IOMUX_REMAP6_USART1_GMUX IOMUX_REMAP6_USART1_GMUX_Msk /*!< USART1_GMUX[3:0] bits (USART1 IO general multiplexing) */ +#define IOMUX_REMAP6_USART1_GMUX_0 (0x1U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_1 (0x2U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP6_USART1_GMUX_2 (0x4U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP6_USART1_GMUX_3 (0x8U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00080000 */ + +#define IOMUX_REMAP6_USART1_GMUX_MUX0 0x00000000U /*!< TX/PA9, RX/PA10 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART1_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART1_GMUX_MUX1 IOMUX_REMAP6_USART1_GMUX_MUX1_Msk /*!< TX/PB6, RX/PB7 */ + +/*!< USART3_GMUX configuration */ +#define IOMUX_REMAP6_USART3_GMUX_Pos (24U) +#define IOMUX_REMAP6_USART3_GMUX_Msk (0xFU << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x0F000000 */ +#define IOMUX_REMAP6_USART3_GMUX IOMUX_REMAP6_USART3_GMUX_Msk /*!< USART3_GMUX[3:0] bits (USART3 IO general multiplexing) */ +#define IOMUX_REMAP6_USART3_GMUX_0 (0x1U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_1 (0x2U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x02000000 */ +#define IOMUX_REMAP6_USART3_GMUX_2 (0x4U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP6_USART3_GMUX_3 (0x8U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP6_USART3_GMUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART3_GMUX_MUX1 IOMUX_REMAP6_USART3_GMUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2_Pos (25U) /*!< 0x02000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_USART3_GMUX_MUX2 IOMUX_REMAP6_USART3_GMUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ + +/***************** Bit definition for IOMUX_REMAP7 register *****************/ +#define IOMUX_REMAP7_ADC1_ETP_GMUX_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP7_ADC1_ETP_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETP_GMUX_Pos) +#define IOMUX_REMAP7_ADC1_ETP_GMUX IOMUX_REMAP7_ADC1_ETP_GMUX_Msk /*!< ADC1 External trigger preempted conversion general multiplexing */ +#define IOMUX_REMAP7_ADC1_ETO_GMUX_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP7_ADC1_ETO_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETO_GMUX_Pos) +#define IOMUX_REMAP7_ADC1_ETO_GMUX IOMUX_REMAP7_ADC1_ETO_GMUX_Msk /*!< ADC1 external trigger regular conversion general multiplexing */ + +/*!< SWJTAG_GMUX configuration */ +#define IOMUX_REMAP7_SWJTAG_GMUX_Pos (16U) +#define IOMUX_REMAP7_SWJTAG_GMUX_Msk (0x7U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00070000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX IOMUX_REMAP7_SWJTAG_GMUX_Msk /*!< SWJTAG_GMUX[2:0] bits (SWD JTAG IO general mutiplexing) */ +#define IOMUX_REMAP7_SWJTAG_GMUX_0 (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_1 (0x2U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_2 (0x4U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00040000 */ + +#define IOMUX_REMAP7_SWJTAG_GMUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos (17U) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos (18U) /*!< 0x00040000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ + +#define IOMUX_REMAP7_PD01_GMUX_Pos (20U) +#define IOMUX_REMAP7_PD01_GMUX_Msk (0x1U << IOMUX_REMAP7_PD01_GMUX_Pos) /*!< 0x00100000 */ +#define IOMUX_REMAP7_PD01_GMUX IOMUX_REMAP7_PD01_GMUX_Msk /*!< PD0/PD1 mapped onto HEXT_IN / HEXT_OUT */ + +/***************** Bit definition for IOMUX_REMAP8 register *****************/ +/*!< TMR1_BK1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Msk /*!< TMR1_BK1_CMP_GMUX[1:0] bits (TMR1 break channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */ + +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ + +/*!< TMR1_CH1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk /*!< TMR1_CH1_CMP_GMUX[1:0] bits (TMR1 channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 channel 1 */ + +/*!< TMR2_CH4_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk /*!< TMR2_CH4_CMP_GMUX[1:0] bits (TMR2 channel 4 internal mapping) */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */ + +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 */ + +/*!< TMR3_CH1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk /*!< TMR3_CH1_CMP_GMUX[1:0] bits (TMR3 channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR3_GMUX IO signal is connected to TMR3 channel 1 */ + +/******************************************************************************/ +/* */ +/* External interrupt/Event controller (EXINT) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for EXINT_INTEN register ******************/ +#define EXINT_INTEN_INTEN0_Pos (0U) +#define EXINT_INTEN_INTEN0_Msk (0x1U << EXINT_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_INTEN_INTEN0 EXINT_INTEN_INTEN0_Msk /*!< Interrupt enable or disable on line 0 */ +#define EXINT_INTEN_INTEN1_Pos (1U) +#define EXINT_INTEN_INTEN1_Msk (0x1U << EXINT_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_INTEN_INTEN1 EXINT_INTEN_INTEN1_Msk /*!< Interrupt enable or disable on line 1 */ +#define EXINT_INTEN_INTEN2_Pos (2U) +#define EXINT_INTEN_INTEN2_Msk (0x1U << EXINT_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_INTEN_INTEN2 EXINT_INTEN_INTEN2_Msk /*!< Interrupt enable or disable on line 2 */ +#define EXINT_INTEN_INTEN3_Pos (3U) +#define EXINT_INTEN_INTEN3_Msk (0x1U << EXINT_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_INTEN_INTEN3 EXINT_INTEN_INTEN3_Msk /*!< Interrupt enable or disable on line 3 */ +#define EXINT_INTEN_INTEN4_Pos (4U) +#define EXINT_INTEN_INTEN4_Msk (0x1U << EXINT_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_INTEN_INTEN4 EXINT_INTEN_INTEN4_Msk /*!< Interrupt enable or disable on line 4 */ +#define EXINT_INTEN_INTEN5_Pos (5U) +#define EXINT_INTEN_INTEN5_Msk (0x1U << EXINT_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_INTEN_INTEN5 EXINT_INTEN_INTEN5_Msk /*!< Interrupt enable or disable on line 5 */ +#define EXINT_INTEN_INTEN6_Pos (6U) +#define EXINT_INTEN_INTEN6_Msk (0x1U << EXINT_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_INTEN_INTEN6 EXINT_INTEN_INTEN6_Msk /*!< Interrupt enable or disable on line 6 */ +#define EXINT_INTEN_INTEN7_Pos (7U) +#define EXINT_INTEN_INTEN7_Msk (0x1U << EXINT_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_INTEN_INTEN7 EXINT_INTEN_INTEN7_Msk /*!< Interrupt enable or disable on line 7 */ +#define EXINT_INTEN_INTEN8_Pos (8U) +#define EXINT_INTEN_INTEN8_Msk (0x1U << EXINT_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_INTEN_INTEN8 EXINT_INTEN_INTEN8_Msk /*!< Interrupt enable or disable on line 8 */ +#define EXINT_INTEN_INTEN9_Pos (9U) +#define EXINT_INTEN_INTEN9_Msk (0x1U << EXINT_INTEN_INTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_INTEN_INTEN9 EXINT_INTEN_INTEN9_Msk /*!< Interrupt enable or disable on line 9 */ +#define EXINT_INTEN_INTEN10_Pos (10U) +#define EXINT_INTEN_INTEN10_Msk (0x1U << EXINT_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_INTEN_INTEN10 EXINT_INTEN_INTEN10_Msk /*!< Interrupt enable or disable on line 10 */ +#define EXINT_INTEN_INTEN11_Pos (11U) +#define EXINT_INTEN_INTEN11_Msk (0x1U << EXINT_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_INTEN_INTEN11 EXINT_INTEN_INTEN11_Msk /*!< Interrupt enable or disable on line 11 */ +#define EXINT_INTEN_INTEN12_Pos (12U) +#define EXINT_INTEN_INTEN12_Msk (0x1U << EXINT_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_INTEN_INTEN12 EXINT_INTEN_INTEN12_Msk /*!< Interrupt enable or disable on line 12 */ +#define EXINT_INTEN_INTEN13_Pos (13U) +#define EXINT_INTEN_INTEN13_Msk (0x1U << EXINT_INTEN_INTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_INTEN_INTEN13 EXINT_INTEN_INTEN13_Msk /*!< Interrupt enable or disable on line 13 */ +#define EXINT_INTEN_INTEN14_Pos (14U) +#define EXINT_INTEN_INTEN14_Msk (0x1U << EXINT_INTEN_INTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_INTEN_INTEN14 EXINT_INTEN_INTEN14_Msk /*!< Interrupt enable or disable on line 14 */ +#define EXINT_INTEN_INTEN15_Pos (15U) +#define EXINT_INTEN_INTEN15_Msk (0x1U << EXINT_INTEN_INTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_INTEN_INTEN15 EXINT_INTEN_INTEN15_Msk /*!< Interrupt enable or disable on line 15 */ +#define EXINT_INTEN_INTEN16_Pos (16U) +#define EXINT_INTEN_INTEN16_Msk (0x1U << EXINT_INTEN_INTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_INTEN_INTEN16 EXINT_INTEN_INTEN16_Msk /*!< Interrupt enable or disable on line 16 */ +#define EXINT_INTEN_INTEN17_Pos (17U) +#define EXINT_INTEN_INTEN17_Msk (0x1U << EXINT_INTEN_INTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_INTEN_INTEN17 EXINT_INTEN_INTEN17_Msk /*!< Interrupt enable or disable on line 17 */ +#define EXINT_INTEN_INTEN18_Pos (18U) +#define EXINT_INTEN_INTEN18_Msk (0x1U << EXINT_INTEN_INTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_INTEN_INTEN18 EXINT_INTEN_INTEN18_Msk /*!< Interrupt enable or disable on line 18 */ +#define EXINT_INTEN_INTEN19_Pos (19U) +#define EXINT_INTEN_INTEN19_Msk (0x1U << EXINT_INTEN_INTEN19_Pos) /*!< 0x00080000 */ +#define EXINT_INTEN_INTEN19 EXINT_INTEN_INTEN19_Msk /*!< Interrupt enable or disable on line 19 */ +#define EXINT_INTEN_INTEN20_Pos (20U) +#define EXINT_INTEN_INTEN20_Msk (0x1U << EXINT_INTEN_INTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_INTEN_INTEN20 EXINT_INTEN_INTEN20_Msk /*!< Interrupt enable or disable on line 20 */ +#define EXINT_INTEN_INTEN21_Pos (21U) +#define EXINT_INTEN_INTEN21_Msk (0x1U << EXINT_INTEN_INTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_INTEN_INTEN21 EXINT_INTEN_INTEN21_Msk /*!< Interrupt enable or disable on line 21 */ +#define EXINT_INTEN_INTEN22_Pos (22U) +#define EXINT_INTEN_INTEN22_Msk (0x1U << EXINT_INTEN_INTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_INTEN_INTEN22 EXINT_INTEN_INTEN22_Msk /*!< Interrupt enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_INTEN_INT0 EXINT_INTEN_INTEN0 +#define EXINT_INTEN_INT1 EXINT_INTEN_INTEN1 +#define EXINT_INTEN_INT2 EXINT_INTEN_INTEN2 +#define EXINT_INTEN_INT3 EXINT_INTEN_INTEN3 +#define EXINT_INTEN_INT4 EXINT_INTEN_INTEN4 +#define EXINT_INTEN_INT5 EXINT_INTEN_INTEN5 +#define EXINT_INTEN_INT6 EXINT_INTEN_INTEN6 +#define EXINT_INTEN_INT7 EXINT_INTEN_INTEN7 +#define EXINT_INTEN_INT8 EXINT_INTEN_INTEN8 +#define EXINT_INTEN_INT9 EXINT_INTEN_INTEN9 +#define EXINT_INTEN_INT10 EXINT_INTEN_INTEN10 +#define EXINT_INTEN_INT11 EXINT_INTEN_INTEN11 +#define EXINT_INTEN_INT12 EXINT_INTEN_INTEN12 +#define EXINT_INTEN_INT13 EXINT_INTEN_INTEN13 +#define EXINT_INTEN_INT14 EXINT_INTEN_INTEN14 +#define EXINT_INTEN_INT15 EXINT_INTEN_INTEN15 +#define EXINT_INTEN_INT16 EXINT_INTEN_INTEN16 +#define EXINT_INTEN_INT17 EXINT_INTEN_INTEN17 +#define EXINT_INTEN_INT18 EXINT_INTEN_INTEN18 +#define EXINT_INTEN_INT19 EXINT_INTEN_INTEN19 +#define EXINT_INTEN_INT20 EXINT_INTEN_INTEN20 +#define EXINT_INTEN_INT21 EXINT_INTEN_INTEN21 +#define EXINT_INTEN_INT22 EXINT_INTEN_INTEN22 +#define EXINT_INTEN_INT 0x007FFFFFU /*!< Interrupt enable or disable all */ + +/***************** Bit definition for EXINT_EVTEN register ******************/ +#define EXINT_EVTEN_EVTEN0_Pos (0U) +#define EXINT_EVTEN_EVTEN0_Msk (0x1U << EXINT_EVTEN_EVTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_EVTEN_EVTEN0 EXINT_EVTEN_EVTEN0_Msk /*!< Event enable or disable on line 0 */ +#define EXINT_EVTEN_EVTEN1_Pos (1U) +#define EXINT_EVTEN_EVTEN1_Msk (0x1U << EXINT_EVTEN_EVTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_EVTEN_EVTEN1 EXINT_EVTEN_EVTEN1_Msk /*!< Event enable or disable on line 1 */ +#define EXINT_EVTEN_EVTEN2_Pos (2U) +#define EXINT_EVTEN_EVTEN2_Msk (0x1U << EXINT_EVTEN_EVTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_EVTEN_EVTEN2 EXINT_EVTEN_EVTEN2_Msk /*!< Event enable or disable on line 2 */ +#define EXINT_EVTEN_EVTEN3_Pos (3U) +#define EXINT_EVTEN_EVTEN3_Msk (0x1U << EXINT_EVTEN_EVTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_EVTEN_EVTEN3 EXINT_EVTEN_EVTEN3_Msk /*!< Event enable or disable on line 3 */ +#define EXINT_EVTEN_EVTEN4_Pos (4U) +#define EXINT_EVTEN_EVTEN4_Msk (0x1U << EXINT_EVTEN_EVTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_EVTEN_EVTEN4 EXINT_EVTEN_EVTEN4_Msk /*!< Event enable or disable on line 4 */ +#define EXINT_EVTEN_EVTEN5_Pos (5U) +#define EXINT_EVTEN_EVTEN5_Msk (0x1U << EXINT_EVTEN_EVTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_EVTEN_EVTEN5 EXINT_EVTEN_EVTEN5_Msk /*!< Event enable or disable on line 5 */ +#define EXINT_EVTEN_EVTEN6_Pos (6U) +#define EXINT_EVTEN_EVTEN6_Msk (0x1U << EXINT_EVTEN_EVTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_EVTEN_EVTEN6 EXINT_EVTEN_EVTEN6_Msk /*!< Event enable or disable on line 6 */ +#define EXINT_EVTEN_EVTEN7_Pos (7U) +#define EXINT_EVTEN_EVTEN7_Msk (0x1U << EXINT_EVTEN_EVTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_EVTEN_EVTEN7 EXINT_EVTEN_EVTEN7_Msk /*!< Event enable or disable on line 7 */ +#define EXINT_EVTEN_EVTEN8_Pos (8U) +#define EXINT_EVTEN_EVTEN8_Msk (0x1U << EXINT_EVTEN_EVTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_EVTEN_EVTEN8 EXINT_EVTEN_EVTEN8_Msk /*!< Event enable or disable on line 8 */ +#define EXINT_EVTEN_EVTEN9_Pos (9U) +#define EXINT_EVTEN_EVTEN9_Msk (0x1U << EXINT_EVTEN_EVTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_EVTEN_EVTEN9 EXINT_EVTEN_EVTEN9_Msk /*!< Event enable or disable on line 9 */ +#define EXINT_EVTEN_EVTEN10_Pos (10U) +#define EXINT_EVTEN_EVTEN10_Msk (0x1U << EXINT_EVTEN_EVTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_EVTEN_EVTEN10 EXINT_EVTEN_EVTEN10_Msk /*!< Event enable or disable on line 10 */ +#define EXINT_EVTEN_EVTEN11_Pos (11U) +#define EXINT_EVTEN_EVTEN11_Msk (0x1U << EXINT_EVTEN_EVTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_EVTEN_EVTEN11 EXINT_EVTEN_EVTEN11_Msk /*!< Event enable or disable on line 11 */ +#define EXINT_EVTEN_EVTEN12_Pos (12U) +#define EXINT_EVTEN_EVTEN12_Msk (0x1U << EXINT_EVTEN_EVTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_EVTEN_EVTEN12 EXINT_EVTEN_EVTEN12_Msk /*!< Event enable or disable on line 12 */ +#define EXINT_EVTEN_EVTEN13_Pos (13U) +#define EXINT_EVTEN_EVTEN13_Msk (0x1U << EXINT_EVTEN_EVTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_EVTEN_EVTEN13 EXINT_EVTEN_EVTEN13_Msk /*!< Event enable or disable on line 13 */ +#define EXINT_EVTEN_EVTEN14_Pos (14U) +#define EXINT_EVTEN_EVTEN14_Msk (0x1U << EXINT_EVTEN_EVTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_EVTEN_EVTEN14 EXINT_EVTEN_EVTEN14_Msk /*!< Event enable or disable on line 14 */ +#define EXINT_EVTEN_EVTEN15_Pos (15U) +#define EXINT_EVTEN_EVTEN15_Msk (0x1U << EXINT_EVTEN_EVTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_EVTEN_EVTEN15 EXINT_EVTEN_EVTEN15_Msk /*!< Event enable or disable on line 15 */ +#define EXINT_EVTEN_EVTEN16_Pos (16U) +#define EXINT_EVTEN_EVTEN16_Msk (0x1U << EXINT_EVTEN_EVTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_EVTEN_EVTEN16 EXINT_EVTEN_EVTEN16_Msk /*!< Event enable or disable on line 16 */ +#define EXINT_EVTEN_EVTEN17_Pos (17U) +#define EXINT_EVTEN_EVTEN17_Msk (0x1U << EXINT_EVTEN_EVTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_EVTEN_EVTEN17 EXINT_EVTEN_EVTEN17_Msk /*!< Event enable or disable on line 17 */ +#define EXINT_EVTEN_EVTEN18_Pos (18U) +#define EXINT_EVTEN_EVTEN18_Msk (0x1U << EXINT_EVTEN_EVTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_EVTEN_EVTEN18 EXINT_EVTEN_EVTEN18_Msk /*!< Event enable or disable on line 18 */ +#define EXINT_EVTEN_EVTEN19_Pos (19U) +#define EXINT_EVTEN_EVTEN19_Msk (0x1U << EXINT_EVTEN_EVTEN19_Pos) /*!< 0x00080000 */ +#define EXINT_EVTEN_EVTEN19 EXINT_EVTEN_EVTEN19_Msk /*!< Event enable or disable on line 19 */ +#define EXINT_EVTEN_EVTEN20_Pos (20U) +#define EXINT_EVTEN_EVTEN20_Msk (0x1U << EXINT_EVTEN_EVTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_EVTEN_EVTEN20 EXINT_EVTEN_EVTEN20_Msk /*!< Event enable or disable on line 20 */ +#define EXINT_EVTEN_EVTEN21_Pos (21U) +#define EXINT_EVTEN_EVTEN21_Msk (0x1U << EXINT_EVTEN_EVTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_EVTEN_EVTEN21 EXINT_EVTEN_EVTEN21_Msk /*!< Event enable or disable on line 21 */ +#define EXINT_EVTEN_EVTEN22_Pos (22U) +#define EXINT_EVTEN_EVTEN22_Msk (0x1U << EXINT_EVTEN_EVTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_EVTEN_EVTEN22 EXINT_EVTEN_EVTEN22_Msk /*!< Event enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_EVTEN_EVT0 EXINT_EVTEN_EVTEN0 +#define EXINT_EVTEN_EVT1 EXINT_EVTEN_EVTEN1 +#define EXINT_EVTEN_EVT2 EXINT_EVTEN_EVTEN2 +#define EXINT_EVTEN_EVT3 EXINT_EVTEN_EVTEN3 +#define EXINT_EVTEN_EVT4 EXINT_EVTEN_EVTEN4 +#define EXINT_EVTEN_EVT5 EXINT_EVTEN_EVTEN5 +#define EXINT_EVTEN_EVT6 EXINT_EVTEN_EVTEN6 +#define EXINT_EVTEN_EVT7 EXINT_EVTEN_EVTEN7 +#define EXINT_EVTEN_EVT8 EXINT_EVTEN_EVTEN8 +#define EXINT_EVTEN_EVT9 EXINT_EVTEN_EVTEN9 +#define EXINT_EVTEN_EVT10 EXINT_EVTEN_EVTEN10 +#define EXINT_EVTEN_EVT11 EXINT_EVTEN_EVTEN11 +#define EXINT_EVTEN_EVT12 EXINT_EVTEN_EVTEN12 +#define EXINT_EVTEN_EVT13 EXINT_EVTEN_EVTEN13 +#define EXINT_EVTEN_EVT14 EXINT_EVTEN_EVTEN14 +#define EXINT_EVTEN_EVT15 EXINT_EVTEN_EVTEN15 +#define EXINT_EVTEN_EVT16 EXINT_EVTEN_EVTEN16 +#define EXINT_EVTEN_EVT17 EXINT_EVTEN_EVTEN17 +#define EXINT_EVTEN_EVT18 EXINT_EVTEN_EVTEN18 +#define EXINT_EVTEN_EVT19 EXINT_EVTEN_EVTEN19 +#define EXINT_EVTEN_EVT20 EXINT_EVTEN_EVTEN20 +#define EXINT_EVTEN_EVT21 EXINT_EVTEN_EVTEN21 +#define EXINT_EVTEN_EVT22 EXINT_EVTEN_EVTEN22 + +/**************** Bit definition for EXINT_POLCFG1 register *****************/ +#define EXINT_POLCFG1_RP0_Pos (0U) +#define EXINT_POLCFG1_RP0_Msk (0x1U << EXINT_POLCFG1_RP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG1_RP0 EXINT_POLCFG1_RP0_Msk /*!< Rising edge event configuration bit on line 0 */ +#define EXINT_POLCFG1_RP1_Pos (1U) +#define EXINT_POLCFG1_RP1_Msk (0x1U << EXINT_POLCFG1_RP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG1_RP1 EXINT_POLCFG1_RP1_Msk /*!< Rising edge event configuration bit on line 1 */ +#define EXINT_POLCFG1_RP2_Pos (2U) +#define EXINT_POLCFG1_RP2_Msk (0x1U << EXINT_POLCFG1_RP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG1_RP2 EXINT_POLCFG1_RP2_Msk /*!< Rising edge event configuration bit on line 2 */ +#define EXINT_POLCFG1_RP3_Pos (3U) +#define EXINT_POLCFG1_RP3_Msk (0x1U << EXINT_POLCFG1_RP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG1_RP3 EXINT_POLCFG1_RP3_Msk /*!< Rising edge event configuration bit on line 3 */ +#define EXINT_POLCFG1_RP4_Pos (4U) +#define EXINT_POLCFG1_RP4_Msk (0x1U << EXINT_POLCFG1_RP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG1_RP4 EXINT_POLCFG1_RP4_Msk /*!< Rising edge event configuration bit on line 4 */ +#define EXINT_POLCFG1_RP5_Pos (5U) +#define EXINT_POLCFG1_RP5_Msk (0x1U << EXINT_POLCFG1_RP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG1_RP5 EXINT_POLCFG1_RP5_Msk /*!< Rising edge event configuration bit on line 5 */ +#define EXINT_POLCFG1_RP6_Pos (6U) +#define EXINT_POLCFG1_RP6_Msk (0x1U << EXINT_POLCFG1_RP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG1_RP6 EXINT_POLCFG1_RP6_Msk /*!< Rising edge event configuration bit on line 6 */ +#define EXINT_POLCFG1_RP7_Pos (7U) +#define EXINT_POLCFG1_RP7_Msk (0x1U << EXINT_POLCFG1_RP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG1_RP7 EXINT_POLCFG1_RP7_Msk /*!< Rising edge event configuration bit on line 7 */ +#define EXINT_POLCFG1_RP8_Pos (8U) +#define EXINT_POLCFG1_RP8_Msk (0x1U << EXINT_POLCFG1_RP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG1_RP8 EXINT_POLCFG1_RP8_Msk /*!< Rising edge event configuration bit on line 8 */ +#define EXINT_POLCFG1_RP9_Pos (9U) +#define EXINT_POLCFG1_RP9_Msk (0x1U << EXINT_POLCFG1_RP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG1_RP9 EXINT_POLCFG1_RP9_Msk /*!< Rising edge event configuration bit on line 9 */ +#define EXINT_POLCFG1_RP10_Pos (10U) +#define EXINT_POLCFG1_RP10_Msk (0x1U << EXINT_POLCFG1_RP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG1_RP10 EXINT_POLCFG1_RP10_Msk /*!< Rising edge event configuration bit on line 10 */ +#define EXINT_POLCFG1_RP11_Pos (11U) +#define EXINT_POLCFG1_RP11_Msk (0x1U << EXINT_POLCFG1_RP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG1_RP11 EXINT_POLCFG1_RP11_Msk /*!< Rising edge event configuration bit on line 11 */ +#define EXINT_POLCFG1_RP12_Pos (12U) +#define EXINT_POLCFG1_RP12_Msk (0x1U << EXINT_POLCFG1_RP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG1_RP12 EXINT_POLCFG1_RP12_Msk /*!< Rising edge event configuration bit on line 12 */ +#define EXINT_POLCFG1_RP13_Pos (13U) +#define EXINT_POLCFG1_RP13_Msk (0x1U << EXINT_POLCFG1_RP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG1_RP13 EXINT_POLCFG1_RP13_Msk /*!< Rising edge event configuration bit on line 13 */ +#define EXINT_POLCFG1_RP14_Pos (14U) +#define EXINT_POLCFG1_RP14_Msk (0x1U << EXINT_POLCFG1_RP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG1_RP14 EXINT_POLCFG1_RP14_Msk /*!< Rising edge event configuration bit on line 14 */ +#define EXINT_POLCFG1_RP15_Pos (15U) +#define EXINT_POLCFG1_RP15_Msk (0x1U << EXINT_POLCFG1_RP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG1_RP15 EXINT_POLCFG1_RP15_Msk /*!< Rising edge event configuration bit on line 15 */ +#define EXINT_POLCFG1_RP16_Pos (16U) +#define EXINT_POLCFG1_RP16_Msk (0x1U << EXINT_POLCFG1_RP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG1_RP16 EXINT_POLCFG1_RP16_Msk /*!< Rising edge event configuration bit on line 16 */ +#define EXINT_POLCFG1_RP17_Pos (17U) +#define EXINT_POLCFG1_RP17_Msk (0x1U << EXINT_POLCFG1_RP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG1_RP17 EXINT_POLCFG1_RP17_Msk /*!< Rising edge event configuration bit on line 17 */ +#define EXINT_POLCFG1_RP18_Pos (18U) +#define EXINT_POLCFG1_RP18_Msk (0x1U << EXINT_POLCFG1_RP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG1_RP18 EXINT_POLCFG1_RP18_Msk /*!< Rising edge event configuration bit on line 18 */ +#define EXINT_POLCFG1_RP19_Pos (19U) +#define EXINT_POLCFG1_RP19_Msk (0x1U << EXINT_POLCFG1_RP19_Pos) /*!< 0x00080000 */ +#define EXINT_POLCFG1_RP19 EXINT_POLCFG1_RP19_Msk /*!< Rising edge event configuration bit on line 19 */ +#define EXINT_POLCFG1_RP20_Pos (20U) +#define EXINT_POLCFG1_RP20_Msk (0x1U << EXINT_POLCFG1_RP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG1_RP20 EXINT_POLCFG1_RP20_Msk /*!< Rising edge event configuration bit on line 20 */ +#define EXINT_POLCFG1_RP21_Pos (21U) +#define EXINT_POLCFG1_RP21_Msk (0x1U << EXINT_POLCFG1_RP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG1_RP21 EXINT_POLCFG1_RP21_Msk /*!< Rising edge event configuration bit on line 21 */ +#define EXINT_POLCFG1_RP22_Pos (22U) +#define EXINT_POLCFG1_RP22_Msk (0x1U << EXINT_POLCFG1_RP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG1_RP22 EXINT_POLCFG1_RP22_Msk /*!< Rising edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG1_POL0 EXINT_POLCFG1_RP0 +#define EXINT_POLCFG1_POL1 EXINT_POLCFG1_RP1 +#define EXINT_POLCFG1_POL2 EXINT_POLCFG1_RP2 +#define EXINT_POLCFG1_POL3 EXINT_POLCFG1_RP3 +#define EXINT_POLCFG1_POL4 EXINT_POLCFG1_RP4 +#define EXINT_POLCFG1_POL5 EXINT_POLCFG1_RP5 +#define EXINT_POLCFG1_POL6 EXINT_POLCFG1_RP6 +#define EXINT_POLCFG1_POL7 EXINT_POLCFG1_RP7 +#define EXINT_POLCFG1_POL8 EXINT_POLCFG1_RP8 +#define EXINT_POLCFG1_POL9 EXINT_POLCFG1_RP9 +#define EXINT_POLCFG1_POL10 EXINT_POLCFG1_RP10 +#define EXINT_POLCFG1_POL11 EXINT_POLCFG1_RP11 +#define EXINT_POLCFG1_POL12 EXINT_POLCFG1_RP12 +#define EXINT_POLCFG1_POL13 EXINT_POLCFG1_RP13 +#define EXINT_POLCFG1_POL14 EXINT_POLCFG1_RP14 +#define EXINT_POLCFG1_POL15 EXINT_POLCFG1_RP15 +#define EXINT_POLCFG1_POL16 EXINT_POLCFG1_RP16 +#define EXINT_POLCFG1_POL17 EXINT_POLCFG1_RP17 +#define EXINT_POLCFG1_POL18 EXINT_POLCFG1_RP18 +#define EXINT_POLCFG1_POL19 EXINT_POLCFG1_RP19 +#define EXINT_POLCFG1_POL20 EXINT_POLCFG1_RP20 +#define EXINT_POLCFG1_POL21 EXINT_POLCFG1_RP21 +#define EXINT_POLCFG1_POL22 EXINT_POLCFG1_RP22 + +/**************** Bit definition for EXINT_POLCFG2 register *****************/ +#define EXINT_POLCFG2_FP0_Pos (0U) +#define EXINT_POLCFG2_FP0_Msk (0x1U << EXINT_POLCFG2_FP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG2_FP0 EXINT_POLCFG2_FP0_Msk /*!< Falling edge event configuration bit on line 0 */ +#define EXINT_POLCFG2_FP1_Pos (1U) +#define EXINT_POLCFG2_FP1_Msk (0x1U << EXINT_POLCFG2_FP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG2_FP1 EXINT_POLCFG2_FP1_Msk /*!< Falling edge event configuration bit on line 1 */ +#define EXINT_POLCFG2_FP2_Pos (2U) +#define EXINT_POLCFG2_FP2_Msk (0x1U << EXINT_POLCFG2_FP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG2_FP2 EXINT_POLCFG2_FP2_Msk /*!< Falling edge event configuration bit on line 2 */ +#define EXINT_POLCFG2_FP3_Pos (3U) +#define EXINT_POLCFG2_FP3_Msk (0x1U << EXINT_POLCFG2_FP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG2_FP3 EXINT_POLCFG2_FP3_Msk /*!< Falling edge event configuration bit on line 3 */ +#define EXINT_POLCFG2_FP4_Pos (4U) +#define EXINT_POLCFG2_FP4_Msk (0x1U << EXINT_POLCFG2_FP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG2_FP4 EXINT_POLCFG2_FP4_Msk /*!< Falling edge event configuration bit on line 4 */ +#define EXINT_POLCFG2_FP5_Pos (5U) +#define EXINT_POLCFG2_FP5_Msk (0x1U << EXINT_POLCFG2_FP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG2_FP5 EXINT_POLCFG2_FP5_Msk /*!< Falling edge event configuration bit on line 5 */ +#define EXINT_POLCFG2_FP6_Pos (6U) +#define EXINT_POLCFG2_FP6_Msk (0x1U << EXINT_POLCFG2_FP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG2_FP6 EXINT_POLCFG2_FP6_Msk /*!< Falling edge event configuration bit on line 6 */ +#define EXINT_POLCFG2_FP7_Pos (7U) +#define EXINT_POLCFG2_FP7_Msk (0x1U << EXINT_POLCFG2_FP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG2_FP7 EXINT_POLCFG2_FP7_Msk /*!< Falling edge event configuration bit on line 7 */ +#define EXINT_POLCFG2_FP8_Pos (8U) +#define EXINT_POLCFG2_FP8_Msk (0x1U << EXINT_POLCFG2_FP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG2_FP8 EXINT_POLCFG2_FP8_Msk /*!< Falling edge event configuration bit on line 8 */ +#define EXINT_POLCFG2_FP9_Pos (9U) +#define EXINT_POLCFG2_FP9_Msk (0x1U << EXINT_POLCFG2_FP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG2_FP9 EXINT_POLCFG2_FP9_Msk /*!< Falling edge event configuration bit on line 9 */ +#define EXINT_POLCFG2_FP10_Pos (10U) +#define EXINT_POLCFG2_FP10_Msk (0x1U << EXINT_POLCFG2_FP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG2_FP10 EXINT_POLCFG2_FP10_Msk /*!< Falling edge event configuration bit on line 10 */ +#define EXINT_POLCFG2_FP11_Pos (11U) +#define EXINT_POLCFG2_FP11_Msk (0x1U << EXINT_POLCFG2_FP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG2_FP11 EXINT_POLCFG2_FP11_Msk /*!< Falling edge event configuration bit on line 11 */ +#define EXINT_POLCFG2_FP12_Pos (12U) +#define EXINT_POLCFG2_FP12_Msk (0x1U << EXINT_POLCFG2_FP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG2_FP12 EXINT_POLCFG2_FP12_Msk /*!< Falling edge event configuration bit on line 12 */ +#define EXINT_POLCFG2_FP13_Pos (13U) +#define EXINT_POLCFG2_FP13_Msk (0x1U << EXINT_POLCFG2_FP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG2_FP13 EXINT_POLCFG2_FP13_Msk /*!< Falling edge event configuration bit on line 13 */ +#define EXINT_POLCFG2_FP14_Pos (14U) +#define EXINT_POLCFG2_FP14_Msk (0x1U << EXINT_POLCFG2_FP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG2_FP14 EXINT_POLCFG2_FP14_Msk /*!< Falling edge event configuration bit on line 14 */ +#define EXINT_POLCFG2_FP15_Pos (15U) +#define EXINT_POLCFG2_FP15_Msk (0x1U << EXINT_POLCFG2_FP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG2_FP15 EXINT_POLCFG2_FP15_Msk /*!< Falling edge event configuration bit on line 15 */ +#define EXINT_POLCFG2_FP16_Pos (16U) +#define EXINT_POLCFG2_FP16_Msk (0x1U << EXINT_POLCFG2_FP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG2_FP16 EXINT_POLCFG2_FP16_Msk /*!< Falling edge event configuration bit on line 16 */ +#define EXINT_POLCFG2_FP17_Pos (17U) +#define EXINT_POLCFG2_FP17_Msk (0x1U << EXINT_POLCFG2_FP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG2_FP17 EXINT_POLCFG2_FP17_Msk /*!< Falling edge event configuration bit on line 17 */ +#define EXINT_POLCFG2_FP18_Pos (18U) +#define EXINT_POLCFG2_FP18_Msk (0x1U << EXINT_POLCFG2_FP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG2_FP18 EXINT_POLCFG2_FP18_Msk /*!< Falling edge event configuration bit on line 18 */ +#define EXINT_POLCFG2_FP19_Pos (19U) +#define EXINT_POLCFG2_FP19_Msk (0x1U << EXINT_POLCFG2_FP19_Pos) /*!< 0x00080000 */ +#define EXINT_POLCFG2_FP19 EXINT_POLCFG2_FP19_Msk /*!< Falling edge event configuration bit on line 19 */ +#define EXINT_POLCFG2_FP20_Pos (20U) +#define EXINT_POLCFG2_FP20_Msk (0x1U << EXINT_POLCFG2_FP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG2_FP20 EXINT_POLCFG2_FP20_Msk /*!< Falling edge event configuration bit on line 20 */ +#define EXINT_POLCFG2_FP21_Pos (21U) +#define EXINT_POLCFG2_FP21_Msk (0x1U << EXINT_POLCFG2_FP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG2_FP21 EXINT_POLCFG2_FP21_Msk /*!< Falling edge event configuration bit on line 21 */ +#define EXINT_POLCFG2_FP22_Pos (22U) +#define EXINT_POLCFG2_FP22_Msk (0x1U << EXINT_POLCFG2_FP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG2_FP22 EXINT_POLCFG2_FP22_Msk /*!< Falling edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG2_POL0 EXINT_POLCFG2_FP0 +#define EXINT_POLCFG2_POL1 EXINT_POLCFG2_FP1 +#define EXINT_POLCFG2_POL2 EXINT_POLCFG2_FP2 +#define EXINT_POLCFG2_POL3 EXINT_POLCFG2_FP3 +#define EXINT_POLCFG2_POL4 EXINT_POLCFG2_FP4 +#define EXINT_POLCFG2_POL5 EXINT_POLCFG2_FP5 +#define EXINT_POLCFG2_POL6 EXINT_POLCFG2_FP6 +#define EXINT_POLCFG2_POL7 EXINT_POLCFG2_FP7 +#define EXINT_POLCFG2_POL8 EXINT_POLCFG2_FP8 +#define EXINT_POLCFG2_POL9 EXINT_POLCFG2_FP9 +#define EXINT_POLCFG2_POL10 EXINT_POLCFG2_FP10 +#define EXINT_POLCFG2_POL11 EXINT_POLCFG2_FP11 +#define EXINT_POLCFG2_POL12 EXINT_POLCFG2_FP12 +#define EXINT_POLCFG2_POL13 EXINT_POLCFG2_FP13 +#define EXINT_POLCFG2_POL14 EXINT_POLCFG2_FP14 +#define EXINT_POLCFG2_POL15 EXINT_POLCFG2_FP15 +#define EXINT_POLCFG2_POL16 EXINT_POLCFG2_FP16 +#define EXINT_POLCFG2_POL17 EXINT_POLCFG2_FP17 +#define EXINT_POLCFG2_POL18 EXINT_POLCFG2_FP18 +#define EXINT_POLCFG2_POL19 EXINT_POLCFG2_FP19 +#define EXINT_POLCFG2_POL20 EXINT_POLCFG2_FP20 +#define EXINT_POLCFG2_POL21 EXINT_POLCFG2_FP21 +#define EXINT_POLCFG2_POL22 EXINT_POLCFG2_FP22 + +/***************** Bit definition for EXINT_SWTRG register ******************/ +#define EXINT_SWTRG_SWT0_Pos (0U) +#define EXINT_SWTRG_SWT0_Msk (0x1U << EXINT_SWTRG_SWT0_Pos) /*!< 0x00000001 */ +#define EXINT_SWTRG_SWT0 EXINT_SWTRG_SWT0_Msk /*!< Software trigger on line 0 */ +#define EXINT_SWTRG_SWT1_Pos (1U) +#define EXINT_SWTRG_SWT1_Msk (0x1U << EXINT_SWTRG_SWT1_Pos) /*!< 0x00000002 */ +#define EXINT_SWTRG_SWT1 EXINT_SWTRG_SWT1_Msk /*!< Software trigger on line 1 */ +#define EXINT_SWTRG_SWT2_Pos (2U) +#define EXINT_SWTRG_SWT2_Msk (0x1U << EXINT_SWTRG_SWT2_Pos) /*!< 0x00000004 */ +#define EXINT_SWTRG_SWT2 EXINT_SWTRG_SWT2_Msk /*!< Software trigger on line 2 */ +#define EXINT_SWTRG_SWT3_Pos (3U) +#define EXINT_SWTRG_SWT3_Msk (0x1U << EXINT_SWTRG_SWT3_Pos) /*!< 0x00000008 */ +#define EXINT_SWTRG_SWT3 EXINT_SWTRG_SWT3_Msk /*!< Software trigger on line 3 */ +#define EXINT_SWTRG_SWT4_Pos (4U) +#define EXINT_SWTRG_SWT4_Msk (0x1U << EXINT_SWTRG_SWT4_Pos) /*!< 0x00000010 */ +#define EXINT_SWTRG_SWT4 EXINT_SWTRG_SWT4_Msk /*!< Software trigger on line 4 */ +#define EXINT_SWTRG_SWT5_Pos (5U) +#define EXINT_SWTRG_SWT5_Msk (0x1U << EXINT_SWTRG_SWT5_Pos) /*!< 0x00000020 */ +#define EXINT_SWTRG_SWT5 EXINT_SWTRG_SWT5_Msk /*!< Software trigger on line 5 */ +#define EXINT_SWTRG_SWT6_Pos (6U) +#define EXINT_SWTRG_SWT6_Msk (0x1U << EXINT_SWTRG_SWT6_Pos) /*!< 0x00000040 */ +#define EXINT_SWTRG_SWT6 EXINT_SWTRG_SWT6_Msk /*!< Software trigger on line 6 */ +#define EXINT_SWTRG_SWT7_Pos (7U) +#define EXINT_SWTRG_SWT7_Msk (0x1U << EXINT_SWTRG_SWT7_Pos) /*!< 0x00000080 */ +#define EXINT_SWTRG_SWT7 EXINT_SWTRG_SWT7_Msk /*!< Software trigger on line 7 */ +#define EXINT_SWTRG_SWT8_Pos (8U) +#define EXINT_SWTRG_SWT8_Msk (0x1U << EXINT_SWTRG_SWT8_Pos) /*!< 0x00000100 */ +#define EXINT_SWTRG_SWT8 EXINT_SWTRG_SWT8_Msk /*!< Software trigger on line 8 */ +#define EXINT_SWTRG_SWT9_Pos (9U) +#define EXINT_SWTRG_SWT9_Msk (0x1U << EXINT_SWTRG_SWT9_Pos) /*!< 0x00000200 */ +#define EXINT_SWTRG_SWT9 EXINT_SWTRG_SWT9_Msk /*!< Software trigger on line 9 */ +#define EXINT_SWTRG_SWT10_Pos (10U) +#define EXINT_SWTRG_SWT10_Msk (0x1U << EXINT_SWTRG_SWT10_Pos) /*!< 0x00000400 */ +#define EXINT_SWTRG_SWT10 EXINT_SWTRG_SWT10_Msk /*!< Software trigger on line 10 */ +#define EXINT_SWTRG_SWT11_Pos (11U) +#define EXINT_SWTRG_SWT11_Msk (0x1U << EXINT_SWTRG_SWT11_Pos) /*!< 0x00000800 */ +#define EXINT_SWTRG_SWT11 EXINT_SWTRG_SWT11_Msk /*!< Software trigger on line 11 */ +#define EXINT_SWTRG_SWT12_Pos (12U) +#define EXINT_SWTRG_SWT12_Msk (0x1U << EXINT_SWTRG_SWT12_Pos) /*!< 0x00001000 */ +#define EXINT_SWTRG_SWT12 EXINT_SWTRG_SWT12_Msk /*!< Software trigger on line 12 */ +#define EXINT_SWTRG_SWT13_Pos (13U) +#define EXINT_SWTRG_SWT13_Msk (0x1U << EXINT_SWTRG_SWT13_Pos) /*!< 0x00002000 */ +#define EXINT_SWTRG_SWT13 EXINT_SWTRG_SWT13_Msk /*!< Software trigger on line 13 */ +#define EXINT_SWTRG_SWT14_Pos (14U) +#define EXINT_SWTRG_SWT14_Msk (0x1U << EXINT_SWTRG_SWT14_Pos) /*!< 0x00004000 */ +#define EXINT_SWTRG_SWT14 EXINT_SWTRG_SWT14_Msk /*!< Software trigger on line 14 */ +#define EXINT_SWTRG_SWT15_Pos (15U) +#define EXINT_SWTRG_SWT15_Msk (0x1U << EXINT_SWTRG_SWT15_Pos) /*!< 0x00008000 */ +#define EXINT_SWTRG_SWT15 EXINT_SWTRG_SWT15_Msk /*!< Software trigger on line 15 */ +#define EXINT_SWTRG_SWT16_Pos (16U) +#define EXINT_SWTRG_SWT16_Msk (0x1U << EXINT_SWTRG_SWT16_Pos) /*!< 0x00010000 */ +#define EXINT_SWTRG_SWT16 EXINT_SWTRG_SWT16_Msk /*!< Software trigger on line 16 */ +#define EXINT_SWTRG_SWT17_Pos (17U) +#define EXINT_SWTRG_SWT17_Msk (0x1U << EXINT_SWTRG_SWT17_Pos) /*!< 0x00020000 */ +#define EXINT_SWTRG_SWT17 EXINT_SWTRG_SWT17_Msk /*!< Software trigger on line 17 */ +#define EXINT_SWTRG_SWT18_Pos (18U) +#define EXINT_SWTRG_SWT18_Msk (0x1U << EXINT_SWTRG_SWT18_Pos) /*!< 0x00040000 */ +#define EXINT_SWTRG_SWT18 EXINT_SWTRG_SWT18_Msk /*!< Software trigger on line 18 */ +#define EXINT_SWTRG_SWT19_Pos (19U) +#define EXINT_SWTRG_SWT19_Msk (0x1U << EXINT_SWTRG_SWT19_Pos) /*!< 0x00080000 */ +#define EXINT_SWTRG_SWT19 EXINT_SWTRG_SWT19_Msk /*!< Software trigger on line 19 */ +#define EXINT_SWTRG_SWT20_Pos (20U) +#define EXINT_SWTRG_SWT20_Msk (0x1U << EXINT_SWTRG_SWT20_Pos) /*!< 0x00100000 */ +#define EXINT_SWTRG_SWT20 EXINT_SWTRG_SWT20_Msk /*!< Software trigger on line 20 */ +#define EXINT_SWTRG_SWT21_Pos (21U) +#define EXINT_SWTRG_SWT21_Msk (0x1U << EXINT_SWTRG_SWT21_Pos) /*!< 0x00200000 */ +#define EXINT_SWTRG_SWT21 EXINT_SWTRG_SWT21_Msk /*!< Software trigger on line 21 */ +#define EXINT_SWTRG_SWT22_Pos (22U) +#define EXINT_SWTRG_SWT22_Msk (0x1U << EXINT_SWTRG_SWT22_Pos) /*!< 0x00400000 */ +#define EXINT_SWTRG_SWT22 EXINT_SWTRG_SWT22_Msk /*!< Software trigger on line 22 */ + +/* References Defines */ +#define EXINT_SWTRG_SW0 EXINT_SWTRG_SWT0 +#define EXINT_SWTRG_SW1 EXINT_SWTRG_SWT1 +#define EXINT_SWTRG_SW2 EXINT_SWTRG_SWT2 +#define EXINT_SWTRG_SW3 EXINT_SWTRG_SWT3 +#define EXINT_SWTRG_SW4 EXINT_SWTRG_SWT4 +#define EXINT_SWTRG_SW5 EXINT_SWTRG_SWT5 +#define EXINT_SWTRG_SW6 EXINT_SWTRG_SWT6 +#define EXINT_SWTRG_SW7 EXINT_SWTRG_SWT7 +#define EXINT_SWTRG_SW8 EXINT_SWTRG_SWT8 +#define EXINT_SWTRG_SW9 EXINT_SWTRG_SWT9 +#define EXINT_SWTRG_SW10 EXINT_SWTRG_SWT10 +#define EXINT_SWTRG_SW11 EXINT_SWTRG_SWT11 +#define EXINT_SWTRG_SW12 EXINT_SWTRG_SWT12 +#define EXINT_SWTRG_SW13 EXINT_SWTRG_SWT13 +#define EXINT_SWTRG_SW14 EXINT_SWTRG_SWT14 +#define EXINT_SWTRG_SW15 EXINT_SWTRG_SWT15 +#define EXINT_SWTRG_SW16 EXINT_SWTRG_SWT16 +#define EXINT_SWTRG_SW17 EXINT_SWTRG_SWT17 +#define EXINT_SWTRG_SW18 EXINT_SWTRG_SWT18 +#define EXINT_SWTRG_SW19 EXINT_SWTRG_SWT19 +#define EXINT_SWTRG_SW20 EXINT_SWTRG_SWT20 +#define EXINT_SWTRG_SW21 EXINT_SWTRG_SWT21 +#define EXINT_SWTRG_SW22 EXINT_SWTRG_SWT22 + +/***************** Bit definition for EXINT_INTSTS register *****************/ +#define EXINT_INTSTS_LINE0_Pos (0U) +#define EXINT_INTSTS_LINE0_Msk (0x1U << EXINT_INTSTS_LINE0_Pos) /*!< 0x00000001 */ +#define EXINT_INTSTS_LINE0 EXINT_INTSTS_LINE0_Msk /*!< Status bit for line 0 */ +#define EXINT_INTSTS_LINE1_Pos (1U) +#define EXINT_INTSTS_LINE1_Msk (0x1U << EXINT_INTSTS_LINE1_Pos) /*!< 0x00000002 */ +#define EXINT_INTSTS_LINE1 EXINT_INTSTS_LINE1_Msk /*!< Status bit for line 1 */ +#define EXINT_INTSTS_LINE2_Pos (2U) +#define EXINT_INTSTS_LINE2_Msk (0x1U << EXINT_INTSTS_LINE2_Pos) /*!< 0x00000004 */ +#define EXINT_INTSTS_LINE2 EXINT_INTSTS_LINE2_Msk /*!< Status bit for line 2 */ +#define EXINT_INTSTS_LINE3_Pos (3U) +#define EXINT_INTSTS_LINE3_Msk (0x1U << EXINT_INTSTS_LINE3_Pos) /*!< 0x00000008 */ +#define EXINT_INTSTS_LINE3 EXINT_INTSTS_LINE3_Msk /*!< Status bit for line 3 */ +#define EXINT_INTSTS_LINE4_Pos (4U) +#define EXINT_INTSTS_LINE4_Msk (0x1U << EXINT_INTSTS_LINE4_Pos) /*!< 0x00000010 */ +#define EXINT_INTSTS_LINE4 EXINT_INTSTS_LINE4_Msk /*!< Status bit for line 4 */ +#define EXINT_INTSTS_LINE5_Pos (5U) +#define EXINT_INTSTS_LINE5_Msk (0x1U << EXINT_INTSTS_LINE5_Pos) /*!< 0x00000020 */ +#define EXINT_INTSTS_LINE5 EXINT_INTSTS_LINE5_Msk /*!< Status bit for line 5 */ +#define EXINT_INTSTS_LINE6_Pos (6U) +#define EXINT_INTSTS_LINE6_Msk (0x1U << EXINT_INTSTS_LINE6_Pos) /*!< 0x00000040 */ +#define EXINT_INTSTS_LINE6 EXINT_INTSTS_LINE6_Msk /*!< Status bit for line 6 */ +#define EXINT_INTSTS_LINE7_Pos (7U) +#define EXINT_INTSTS_LINE7_Msk (0x1U << EXINT_INTSTS_LINE7_Pos) /*!< 0x00000080 */ +#define EXINT_INTSTS_LINE7 EXINT_INTSTS_LINE7_Msk /*!< Status bit for line 7 */ +#define EXINT_INTSTS_LINE8_Pos (8U) +#define EXINT_INTSTS_LINE8_Msk (0x1U << EXINT_INTSTS_LINE8_Pos) /*!< 0x00000100 */ +#define EXINT_INTSTS_LINE8 EXINT_INTSTS_LINE8_Msk /*!< Status bit for line 8 */ +#define EXINT_INTSTS_LINE9_Pos (9U) +#define EXINT_INTSTS_LINE9_Msk (0x1U << EXINT_INTSTS_LINE9_Pos) /*!< 0x00000200 */ +#define EXINT_INTSTS_LINE9 EXINT_INTSTS_LINE9_Msk /*!< Status bit for line 9 */ +#define EXINT_INTSTS_LINE10_Pos (10U) +#define EXINT_INTSTS_LINE10_Msk (0x1U << EXINT_INTSTS_LINE10_Pos) /*!< 0x00000400 */ +#define EXINT_INTSTS_LINE10 EXINT_INTSTS_LINE10_Msk /*!< Status bit for line 10 */ +#define EXINT_INTSTS_LINE11_Pos (11U) +#define EXINT_INTSTS_LINE11_Msk (0x1U << EXINT_INTSTS_LINE11_Pos) /*!< 0x00000800 */ +#define EXINT_INTSTS_LINE11 EXINT_INTSTS_LINE11_Msk /*!< Status bit for line 11 */ +#define EXINT_INTSTS_LINE12_Pos (12U) +#define EXINT_INTSTS_LINE12_Msk (0x1U << EXINT_INTSTS_LINE12_Pos) /*!< 0x00001000 */ +#define EXINT_INTSTS_LINE12 EXINT_INTSTS_LINE12_Msk /*!< Status bit for line 12 */ +#define EXINT_INTSTS_LINE13_Pos (13U) +#define EXINT_INTSTS_LINE13_Msk (0x1U << EXINT_INTSTS_LINE13_Pos) /*!< 0x00002000 */ +#define EXINT_INTSTS_LINE13 EXINT_INTSTS_LINE13_Msk /*!< Status bit for line 13 */ +#define EXINT_INTSTS_LINE14_Pos (14U) +#define EXINT_INTSTS_LINE14_Msk (0x1U << EXINT_INTSTS_LINE14_Pos) /*!< 0x00004000 */ +#define EXINT_INTSTS_LINE14 EXINT_INTSTS_LINE14_Msk /*!< Status bit for line 14 */ +#define EXINT_INTSTS_LINE15_Pos (15U) +#define EXINT_INTSTS_LINE15_Msk (0x1U << EXINT_INTSTS_LINE15_Pos) /*!< 0x00008000 */ +#define EXINT_INTSTS_LINE15 EXINT_INTSTS_LINE15_Msk /*!< Status bit for line 15 */ +#define EXINT_INTSTS_LINE16_Pos (16U) +#define EXINT_INTSTS_LINE16_Msk (0x1U << EXINT_INTSTS_LINE16_Pos) /*!< 0x00010000 */ +#define EXINT_INTSTS_LINE16 EXINT_INTSTS_LINE16_Msk /*!< Status bit for line 16 */ +#define EXINT_INTSTS_LINE17_Pos (17U) +#define EXINT_INTSTS_LINE17_Msk (0x1U << EXINT_INTSTS_LINE17_Pos) /*!< 0x00020000 */ +#define EXINT_INTSTS_LINE17 EXINT_INTSTS_LINE17_Msk /*!< Status bit for line 17 */ +#define EXINT_INTSTS_LINE18_Pos (18U) +#define EXINT_INTSTS_LINE18_Msk (0x1U << EXINT_INTSTS_LINE18_Pos) /*!< 0x00040000 */ +#define EXINT_INTSTS_LINE18 EXINT_INTSTS_LINE18_Msk /*!< Status bit for line 18 */ +#define EXINT_INTSTS_LINE19_Pos (19U) +#define EXINT_INTSTS_LINE19_Msk (0x1U << EXINT_INTSTS_LINE19_Pos) /*!< 0x00080000 */ +#define EXINT_INTSTS_LINE19 EXINT_INTSTS_LINE19_Msk /*!< Status bit for line 19 */ +#define EXINT_INTSTS_LINE20_Pos (20U) +#define EXINT_INTSTS_LINE20_Msk (0x1U << EXINT_INTSTS_LINE20_Pos) /*!< 0x00100000 */ +#define EXINT_INTSTS_LINE20 EXINT_INTSTS_LINE20_Msk /*!< Status bit for line 20 */ +#define EXINT_INTSTS_LINE21_Pos (21U) +#define EXINT_INTSTS_LINE21_Msk (0x1U << EXINT_INTSTS_LINE21_Pos) /*!< 0x00200000 */ +#define EXINT_INTSTS_LINE21 EXINT_INTSTS_LINE21_Msk /*!< Status bit for line 21 */ +#define EXINT_INTSTS_LINE22_Pos (22U) +#define EXINT_INTSTS_LINE22_Msk (0x1U << EXINT_INTSTS_LINE22_Pos) /*!< 0x00400000 */ +#define EXINT_INTSTS_LINE22 EXINT_INTSTS_LINE22_Msk /*!< Status bit for line 22 */ + +/* References Defines */ +#define EXINT_INTSTS_INT0 EXINT_INTSTS_LINE0 +#define EXINT_INTSTS_INT1 EXINT_INTSTS_LINE1 +#define EXINT_INTSTS_INT2 EXINT_INTSTS_LINE2 +#define EXINT_INTSTS_INT3 EXINT_INTSTS_LINE3 +#define EXINT_INTSTS_INT4 EXINT_INTSTS_LINE4 +#define EXINT_INTSTS_INT5 EXINT_INTSTS_LINE5 +#define EXINT_INTSTS_INT6 EXINT_INTSTS_LINE6 +#define EXINT_INTSTS_INT7 EXINT_INTSTS_LINE7 +#define EXINT_INTSTS_INT8 EXINT_INTSTS_LINE8 +#define EXINT_INTSTS_INT9 EXINT_INTSTS_LINE9 +#define EXINT_INTSTS_INT10 EXINT_INTSTS_LINE10 +#define EXINT_INTSTS_INT11 EXINT_INTSTS_LINE11 +#define EXINT_INTSTS_INT12 EXINT_INTSTS_LINE12 +#define EXINT_INTSTS_INT13 EXINT_INTSTS_LINE13 +#define EXINT_INTSTS_INT14 EXINT_INTSTS_LINE14 +#define EXINT_INTSTS_INT15 EXINT_INTSTS_LINE15 +#define EXINT_INTSTS_INT16 EXINT_INTSTS_LINE16 +#define EXINT_INTSTS_INT17 EXINT_INTSTS_LINE17 +#define EXINT_INTSTS_INT18 EXINT_INTSTS_LINE18 +#define EXINT_INTSTS_INT19 EXINT_INTSTS_LINE19 +#define EXINT_INTSTS_INT20 EXINT_INTSTS_LINE20 +#define EXINT_INTSTS_INT21 EXINT_INTSTS_LINE21 +#define EXINT_INTSTS_INT22 EXINT_INTSTS_LINE22 + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_STS register ********************/ +#define DMA_STS_GF1_Pos (0U) +#define DMA_STS_GF1_Msk (0x1U << DMA_STS_GF1_Pos) /*!< 0x00000001 */ +#define DMA_STS_GF1 DMA_STS_GF1_Msk /*!< Channel 1 global event flag */ +#define DMA_STS_FDTF1_Pos (1U) +#define DMA_STS_FDTF1_Msk (0x1U << DMA_STS_FDTF1_Pos) /*!< 0x00000002 */ +#define DMA_STS_FDTF1 DMA_STS_FDTF1_Msk /*!< Channel 1 transfer complete event flag */ +#define DMA_STS_HDTF1_Pos (2U) +#define DMA_STS_HDTF1_Msk (0x1U << DMA_STS_HDTF1_Pos) /*!< 0x00000004 */ +#define DMA_STS_HDTF1 DMA_STS_HDTF1_Msk /*!< Channel 1 half transfer event flag */ +#define DMA_STS_DTERRF1_Pos (3U) +#define DMA_STS_DTERRF1_Msk (0x1U << DMA_STS_DTERRF1_Pos) /*!< 0x00000008 */ +#define DMA_STS_DTERRF1 DMA_STS_DTERRF1_Msk /*!< Channel 1 transfer error event flag */ +#define DMA_STS_GF2_Pos (4U) +#define DMA_STS_GF2_Msk (0x1U << DMA_STS_GF2_Pos) /*!< 0x00000010 */ +#define DMA_STS_GF2 DMA_STS_GF2_Msk /*!< Channel 2 global event flag */ +#define DMA_STS_FDTF2_Pos (5U) +#define DMA_STS_FDTF2_Msk (0x1U << DMA_STS_FDTF2_Pos) /*!< 0x00000020 */ +#define DMA_STS_FDTF2 DMA_STS_FDTF2_Msk /*!< Channel 2 transfer complete event flag */ +#define DMA_STS_HDTF2_Pos (6U) +#define DMA_STS_HDTF2_Msk (0x1U << DMA_STS_HDTF2_Pos) /*!< 0x00000040 */ +#define DMA_STS_HDTF2 DMA_STS_HDTF2_Msk /*!< Channel 2 half transfer event flag */ +#define DMA_STS_DTERRF2_Pos (7U) +#define DMA_STS_DTERRF2_Msk (0x1U << DMA_STS_DTERRF2_Pos) /*!< 0x00000080 */ +#define DMA_STS_DTERRF2 DMA_STS_DTERRF2_Msk /*!< Channel 2 transfer error event flag */ +#define DMA_STS_GF3_Pos (8U) +#define DMA_STS_GF3_Msk (0x1U << DMA_STS_GF3_Pos) /*!< 0x00000100 */ +#define DMA_STS_GF3 DMA_STS_GF3_Msk /*!< Channel 3 global event flag */ +#define DMA_STS_FDTF3_Pos (9U) +#define DMA_STS_FDTF3_Msk (0x1U << DMA_STS_FDTF3_Pos) /*!< 0x00000200 */ +#define DMA_STS_FDTF3 DMA_STS_FDTF3_Msk /*!< Channel 3 transfer complete event flag */ +#define DMA_STS_HDTF3_Pos (10U) +#define DMA_STS_HDTF3_Msk (0x1U << DMA_STS_HDTF3_Pos) /*!< 0x00000400 */ +#define DMA_STS_HDTF3 DMA_STS_HDTF3_Msk /*!< Channel 3 half transfer event flag */ +#define DMA_STS_DTERRF3_Pos (11U) +#define DMA_STS_DTERRF3_Msk (0x1U << DMA_STS_DTERRF3_Pos) /*!< 0x00000800 */ +#define DMA_STS_DTERRF3 DMA_STS_DTERRF3_Msk /*!< Channel 3 transfer error event flag */ +#define DMA_STS_GF4_Pos (12U) +#define DMA_STS_GF4_Msk (0x1U << DMA_STS_GF4_Pos) /*!< 0x00001000 */ +#define DMA_STS_GF4 DMA_STS_GF4_Msk /*!< Channel 4 global event flag */ +#define DMA_STS_FDTF4_Pos (13U) +#define DMA_STS_FDTF4_Msk (0x1U << DMA_STS_FDTF4_Pos) /*!< 0x00002000 */ +#define DMA_STS_FDTF4 DMA_STS_FDTF4_Msk /*!< Channel 4 transfer complete event flag */ +#define DMA_STS_HDTF4_Pos (14U) +#define DMA_STS_HDTF4_Msk (0x1U << DMA_STS_HDTF4_Pos) /*!< 0x00004000 */ +#define DMA_STS_HDTF4 DMA_STS_HDTF4_Msk /*!< Channel 4 half transfer event flag */ +#define DMA_STS_DTERRF4_Pos (15U) +#define DMA_STS_DTERRF4_Msk (0x1U << DMA_STS_DTERRF4_Pos) /*!< 0x00008000 */ +#define DMA_STS_DTERRF4 DMA_STS_DTERRF4_Msk /*!< Channel 4 transfer error event flag */ +#define DMA_STS_GF5_Pos (16U) +#define DMA_STS_GF5_Msk (0x1U << DMA_STS_GF5_Pos) /*!< 0x00010000 */ +#define DMA_STS_GF5 DMA_STS_GF5_Msk /*!< Channel 5 global event flag */ +#define DMA_STS_FDTF5_Pos (17U) +#define DMA_STS_FDTF5_Msk (0x1U << DMA_STS_FDTF5_Pos) /*!< 0x00020000 */ +#define DMA_STS_FDTF5 DMA_STS_FDTF5_Msk /*!< Channel 5 transfer complete event flag */ +#define DMA_STS_HDTF5_Pos (18U) +#define DMA_STS_HDTF5_Msk (0x1U << DMA_STS_HDTF5_Pos) /*!< 0x00040000 */ +#define DMA_STS_HDTF5 DMA_STS_HDTF5_Msk /*!< Channel 5 half transfer event flag */ +#define DMA_STS_DTERRF5_Pos (19U) +#define DMA_STS_DTERRF5_Msk (0x1U << DMA_STS_DTERRF5_Pos) /*!< 0x00080000 */ +#define DMA_STS_DTERRF5 DMA_STS_DTERRF5_Msk /*!< Channel 5 transfer error event flag */ +#define DMA_STS_GF6_Pos (20U) +#define DMA_STS_GF6_Msk (0x1U << DMA_STS_GF6_Pos) /*!< 0x00100000 */ +#define DMA_STS_GF6 DMA_STS_GF6_Msk /*!< Channel 6 global event flag */ +#define DMA_STS_FDTF6_Pos (21U) +#define DMA_STS_FDTF6_Msk (0x1U << DMA_STS_FDTF6_Pos) /*!< 0x00200000 */ +#define DMA_STS_FDTF6 DMA_STS_FDTF6_Msk /*!< Channel 6 transfer complete event flag */ +#define DMA_STS_HDTF6_Pos (22U) +#define DMA_STS_HDTF6_Msk (0x1U << DMA_STS_HDTF6_Pos) /*!< 0x00400000 */ +#define DMA_STS_HDTF6 DMA_STS_HDTF6_Msk /*!< Channel 6 half transfer event flag */ +#define DMA_STS_DTERRF6_Pos (23U) +#define DMA_STS_DTERRF6_Msk (0x1U << DMA_STS_DTERRF6_Pos) /*!< 0x00800000 */ +#define DMA_STS_DTERRF6 DMA_STS_DTERRF6_Msk /*!< Channel 6 transfer error event flag */ +#define DMA_STS_GF7_Pos (24U) +#define DMA_STS_GF7_Msk (0x1U << DMA_STS_GF7_Pos) /*!< 0x01000000 */ +#define DMA_STS_GF7 DMA_STS_GF7_Msk /*!< Channel 7 global event flag */ +#define DMA_STS_FDTF7_Pos (25U) +#define DMA_STS_FDTF7_Msk (0x1U << DMA_STS_FDTF7_Pos) /*!< 0x02000000 */ +#define DMA_STS_FDTF7 DMA_STS_FDTF7_Msk /*!< Channel 7 transfer complete event flag */ +#define DMA_STS_HDTF7_Pos (26U) +#define DMA_STS_HDTF7_Msk (0x1U << DMA_STS_HDTF7_Pos) /*!< 0x04000000 */ +#define DMA_STS_HDTF7 DMA_STS_HDTF7_Msk /*!< Channel 7 half transfer event flag */ +#define DMA_STS_DTERRF7_Pos (27U) +#define DMA_STS_DTERRF7_Msk (0x1U << DMA_STS_DTERRF7_Pos) /*!< 0x08000000 */ +#define DMA_STS_DTERRF7 DMA_STS_DTERRF7_Msk /*!< Channel 7 transfer error event flag */ + +/******************* Bit definition for DMA_CLR register ********************/ +#define DMA_CLR_GFC1_Pos (0U) +#define DMA_CLR_GFC1_Msk (0x1U << DMA_CLR_GFC1_Pos) /*!< 0x00000001 */ +#define DMA_CLR_GFC1 DMA_CLR_GFC1_Msk /*!< Channel 1 global interrupt flag clear */ +#define DMA_CLR_FDTFC1_Pos (1U) +#define DMA_CLR_FDTFC1_Msk (0x1U << DMA_CLR_FDTFC1_Pos) /*!< 0x00000002 */ +#define DMA_CLR_FDTFC1 DMA_CLR_FDTFC1_Msk /*!< Channel 1 transfer complete flag clear */ +#define DMA_CLR_HDTFC1_Pos (2U) +#define DMA_CLR_HDTFC1_Msk (0x1U << DMA_CLR_HDTFC1_Pos) /*!< 0x00000004 */ +#define DMA_CLR_HDTFC1 DMA_CLR_HDTFC1_Msk /*!< Channel 1 half transfer flag clear */ +#define DMA_CLR_DTERRFC1_Pos (3U) +#define DMA_CLR_DTERRFC1_Msk (0x1U << DMA_CLR_DTERRFC1_Pos) /*!< 0x00000008 */ +#define DMA_CLR_DTERRFC1 DMA_CLR_DTERRFC1_Msk /*!< Channel 1 data transfer error flag clear */ +#define DMA_CLR_GFC2_Pos (4U) +#define DMA_CLR_GFC2_Msk (0x1U << DMA_CLR_GFC2_Pos) /*!< 0x00000010 */ +#define DMA_CLR_GFC2 DMA_CLR_GFC2_Msk /*!< Channel 2 global interrupt flag clear */ +#define DMA_CLR_FDTFC2_Pos (5U) +#define DMA_CLR_FDTFC2_Msk (0x1U << DMA_CLR_FDTFC2_Pos) /*!< 0x00000020 */ +#define DMA_CLR_FDTFC2 DMA_CLR_FDTFC2_Msk /*!< Channel 2 transfer complete flag clear */ +#define DMA_CLR_HDTFC2_Pos (6U) +#define DMA_CLR_HDTFC2_Msk (0x1U << DMA_CLR_HDTFC2_Pos) /*!< 0x00000040 */ +#define DMA_CLR_HDTFC2 DMA_CLR_HDTFC2_Msk /*!< Channel 2 half transfer flag clear */ +#define DMA_CLR_DTERRFC2_Pos (7U) +#define DMA_CLR_DTERRFC2_Msk (0x1U << DMA_CLR_DTERRFC2_Pos) /*!< 0x00000080 */ +#define DMA_CLR_DTERRFC2 DMA_CLR_DTERRFC2_Msk /*!< Channel 2 data transfer error flag clear */ +#define DMA_CLR_GFC3_Pos (8U) +#define DMA_CLR_GFC3_Msk (0x1U << DMA_CLR_GFC3_Pos) /*!< 0x00000100 */ +#define DMA_CLR_GFC3 DMA_CLR_GFC3_Msk /*!< Channel 3 global interrupt flag clear */ +#define DMA_CLR_FDTFC3_Pos (9U) +#define DMA_CLR_FDTFC3_Msk (0x1U << DMA_CLR_FDTFC3_Pos) /*!< 0x00000200 */ +#define DMA_CLR_FDTFC3 DMA_CLR_FDTFC3_Msk /*!< Channel 3 transfer complete flag clear */ +#define DMA_CLR_HDTFC3_Pos (10U) +#define DMA_CLR_HDTFC3_Msk (0x1U << DMA_CLR_HDTFC3_Pos) /*!< 0x00000400 */ +#define DMA_CLR_HDTFC3 DMA_CLR_HDTFC3_Msk /*!< Channel 3 half transfer flag clear */ +#define DMA_CLR_DTERRFC3_Pos (11U) +#define DMA_CLR_DTERRFC3_Msk (0x1U << DMA_CLR_DTERRFC3_Pos) /*!< 0x00000800 */ +#define DMA_CLR_DTERRFC3 DMA_CLR_DTERRFC3_Msk /*!< Channel 3 data transfer error flag clear */ +#define DMA_CLR_GFC4_Pos (12U) +#define DMA_CLR_GFC4_Msk (0x1U << DMA_CLR_GFC4_Pos) /*!< 0x00001000 */ +#define DMA_CLR_GFC4 DMA_CLR_GFC4_Msk /*!< Channel 4 global interrupt flag clear */ +#define DMA_CLR_FDTFC4_Pos (13U) +#define DMA_CLR_FDTFC4_Msk (0x1U << DMA_CLR_FDTFC4_Pos) /*!< 0x00002000 */ +#define DMA_CLR_FDTFC4 DMA_CLR_FDTFC4_Msk /*!< Channel 4 transfer complete flag clear */ +#define DMA_CLR_HDTFC4_Pos (14U) +#define DMA_CLR_HDTFC4_Msk (0x1U << DMA_CLR_HDTFC4_Pos) /*!< 0x00004000 */ +#define DMA_CLR_HDTFC4 DMA_CLR_HDTFC4_Msk /*!< Channel 4 half transfer flag clear */ +#define DMA_CLR_DTERRFC4_Pos (15U) +#define DMA_CLR_DTERRFC4_Msk (0x1U << DMA_CLR_DTERRFC4_Pos) /*!< 0x00008000 */ +#define DMA_CLR_DTERRFC4 DMA_CLR_DTERRFC4_Msk /*!< Channel 4 data transfer error flag clear */ +#define DMA_CLR_GFC5_Pos (16U) +#define DMA_CLR_GFC5_Msk (0x1U << DMA_CLR_GFC5_Pos) /*!< 0x00010000 */ +#define DMA_CLR_GFC5 DMA_CLR_GFC5_Msk /*!< Channel 5 global interrupt flag clear */ +#define DMA_CLR_FDTFC5_Pos (17U) +#define DMA_CLR_FDTFC5_Msk (0x1U << DMA_CLR_FDTFC5_Pos) /*!< 0x00020000 */ +#define DMA_CLR_FDTFC5 DMA_CLR_FDTFC5_Msk /*!< Channel 5 transfer complete flag clear */ +#define DMA_CLR_HDTFC5_Pos (18U) +#define DMA_CLR_HDTFC5_Msk (0x1U << DMA_CLR_HDTFC5_Pos) /*!< 0x00040000 */ +#define DMA_CLR_HDTFC5 DMA_CLR_HDTFC5_Msk /*!< Channel 5 half transfer flag clear */ +#define DMA_CLR_DTERRFC5_Pos (19U) +#define DMA_CLR_DTERRFC5_Msk (0x1U << DMA_CLR_DTERRFC5_Pos) /*!< 0x00080000 */ +#define DMA_CLR_DTERRFC5 DMA_CLR_DTERRFC5_Msk /*!< Channel 5 data transfer error flag clear */ +#define DMA_CLR_GFC6_Pos (20U) +#define DMA_CLR_GFC6_Msk (0x1U << DMA_CLR_GFC6_Pos) /*!< 0x00100000 */ +#define DMA_CLR_GFC6 DMA_CLR_GFC6_Msk /*!< Channel 6 global interrupt flag clear */ +#define DMA_CLR_FDTFC6_Pos (21U) +#define DMA_CLR_FDTFC6_Msk (0x1U << DMA_CLR_FDTFC6_Pos) /*!< 0x00200000 */ +#define DMA_CLR_FDTFC6 DMA_CLR_FDTFC6_Msk /*!< Channel 6 transfer complete flag clear */ +#define DMA_CLR_HDTFC6_Pos (22U) +#define DMA_CLR_HDTFC6_Msk (0x1U << DMA_CLR_HDTFC6_Pos) /*!< 0x00400000 */ +#define DMA_CLR_HDTFC6 DMA_CLR_HDTFC6_Msk /*!< Channel 6 half transfer flag clear */ +#define DMA_CLR_DTERRFC6_Pos (23U) +#define DMA_CLR_DTERRFC6_Msk (0x1U << DMA_CLR_DTERRFC6_Pos) /*!< 0x00800000 */ +#define DMA_CLR_DTERRFC6 DMA_CLR_DTERRFC6_Msk /*!< Channel 6 data transfer error flag clear */ +#define DMA_CLR_GFC7_Pos (24U) +#define DMA_CLR_GFC7_Msk (0x1U << DMA_CLR_GFC7_Pos) /*!< 0x01000000 */ +#define DMA_CLR_GFC7 DMA_CLR_GFC7_Msk /*!< Channel 7 global interrupt flag clear */ +#define DMA_CLR_FDTFC7_Pos (25U) +#define DMA_CLR_FDTFC7_Msk (0x1U << DMA_CLR_FDTFC7_Pos) /*!< 0x02000000 */ +#define DMA_CLR_FDTFC7 DMA_CLR_FDTFC7_Msk /*!< Channel 7 transfer complete flag clear */ +#define DMA_CLR_HDTFC7_Pos (26U) +#define DMA_CLR_HDTFC7_Msk (0x1U << DMA_CLR_HDTFC7_Pos) /*!< 0x04000000 */ +#define DMA_CLR_HDTFC7 DMA_CLR_HDTFC7_Msk /*!< Channel 7 half transfer flag clear */ +#define DMA_CLR_DTERRFC7_Pos (27U) +#define DMA_CLR_DTERRFC7_Msk (0x1U << DMA_CLR_DTERRFC7_Pos) /*!< 0x08000000 */ +#define DMA_CLR_DTERRFC7 DMA_CLR_DTERRFC7_Msk /*!< Channel 7 data transfer error flag clear */ + +/****************** Bit definition for DMA_CCTRL register *******************/ +#define DMA_CCTRL_CHEN_Pos (0U) +#define DMA_CCTRL_CHEN_Msk (0x1U << DMA_CCTRL_CHEN_Pos) /*!< 0x00000001 */ +#define DMA_CCTRL_CHEN DMA_CCTRL_CHEN_Msk /*!< Channel enable */ +#define DMA_CCTRL_FDTIEN_Pos (1U) +#define DMA_CCTRL_FDTIEN_Msk (0x1U << DMA_CCTRL_FDTIEN_Pos) /*!< 0x00000002 */ +#define DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCTRL_HDTIEN_Pos (2U) +#define DMA_CCTRL_HDTIEN_Msk (0x1U << DMA_CCTRL_HDTIEN_Pos) /*!< 0x00000004 */ +#define DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN_Msk /*!< Half-transfer interrupt enable */ +#define DMA_CCTRL_DTERRIEN_Pos (3U) +#define DMA_CCTRL_DTERRIEN_Msk (0x1U << DMA_CCTRL_DTERRIEN_Pos) /*!< 0x00000008 */ +#define DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCTRL_DTD_Pos (4U) +#define DMA_CCTRL_DTD_Msk (0x1U << DMA_CCTRL_DTD_Pos) /*!< 0x00000010 */ +#define DMA_CCTRL_DTD DMA_CCTRL_DTD_Msk /*!< Data transfer direction */ +#define DMA_CCTRL_LM_Pos (5U) +#define DMA_CCTRL_LM_Msk (0x1U << DMA_CCTRL_LM_Pos) /*!< 0x00000020 */ +#define DMA_CCTRL_LM DMA_CCTRL_LM_Msk /*!< Circular mode */ +#define DMA_CCTRL_PINCM_Pos (6U) +#define DMA_CCTRL_PINCM_Msk (0x1U << DMA_CCTRL_PINCM_Pos) /*!< 0x00000040 */ +#define DMA_CCTRL_PINCM DMA_CCTRL_PINCM_Msk /*!< Peripheral address increment mode */ +#define DMA_CCTRL_MINCM_Pos (7U) +#define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ +#define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ + +#define DMA_CCTRL_PWIDTH_Pos (8U) +#define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ +#define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ +#define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ +#define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ + +#define DMA_CCTRL_MWIDTH_Pos (10U) +#define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ +#define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ +#define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ +#define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ + +#define DMA_CCTRL_CHPL_Pos (12U) +#define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ +#define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ +#define DMA_CCTRL_CHPL_0 (0x1U << DMA_CCTRL_CHPL_Pos) /*!< 0x00001000 */ +#define DMA_CCTRL_CHPL_1 (0x2U << DMA_CCTRL_CHPL_Pos) /*!< 0x00002000 */ + +#define DMA_CCTRL_M2M_Pos (14U) +#define DMA_CCTRL_M2M_Msk (0x1U << DMA_CCTRL_M2M_Pos) /*!< 0x00004000 */ +#define DMA_CCTRL_M2M DMA_CCTRL_M2M_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CDTCNT register ******************/ +#define DMA_CDTCNT_CNT_Pos (0U) +#define DMA_CDTCNT_CNT_Msk (0xFFFFU << DMA_CDTCNT_CNT_Pos) /*!< 0x0000FFFF */ +#define DMA_CDTCNT_CNT DMA_CDTCNT_CNT_Msk /*!< Number of data to transfer */ + +/****************** Bit definition for DMA_CPADDR register ******************/ +#define DMA_CPADDR_PADDR_Pos (0U) +#define DMA_CPADDR_PADDR_Msk (0xFFFFFFFFU << DMA_CPADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPADDR_PADDR DMA_CPADDR_PADDR_Msk /*!< Peripheral base address */ + +/****************** Bit definition for DMA_CMADDR register ******************/ +#define DMA_CMADDR_MADDR_Pos (0U) +#define DMA_CMADDR_MADDR_Msk (0xFFFFFFFFU << DMA_CMADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMADDR_MADDR DMA_CMADDR_MADDR_Msk /*!< Memory base address */ + +/***************** Bit definition for DMA_SRC_SEL0 register *****************/ +#define DMA_SRC_SEL0_CH1_SRC_Pos (0U) +#define DMA_SRC_SEL0_CH1_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH1_SRC_Pos) /*!< 0x000000FF */ +#define DMA_SRC_SEL0_CH1_SRC DMA_SRC_SEL0_CH1_SRC_Msk /*!< CH1 source select */ +#define DMA_SRC_SEL0_CH2_SRC_Pos (8U) +#define DMA_SRC_SEL0_CH2_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH2_SRC_Pos) /*!< 0x0000FF00 */ +#define DMA_SRC_SEL0_CH2_SRC DMA_SRC_SEL0_CH2_SRC_Msk /*!< CH2 source select */ +#define DMA_SRC_SEL0_CH3_SRC_Pos (16U) +#define DMA_SRC_SEL0_CH3_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH3_SRC_Pos) /*!< 0x00FF0000 */ +#define DMA_SRC_SEL0_CH3_SRC DMA_SRC_SEL0_CH3_SRC_Msk /*!< CH3 source select */ +#define DMA_SRC_SEL0_CH4_SRC_Pos (24U) +#define DMA_SRC_SEL0_CH4_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH4_SRC_Pos) /*!< 0xFF000000 */ +#define DMA_SRC_SEL0_CH4_SRC DMA_SRC_SEL0_CH4_SRC_Msk /*!< CH4 source select */ + +/***************** Bit definition for DMA_SRC_SEL1 register *****************/ +#define DMA_SRC_SEL1_CH5_SRC_Pos (0U) +#define DMA_SRC_SEL1_CH5_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH5_SRC_Pos) /*!< 0x000000FF */ +#define DMA_SRC_SEL1_CH5_SRC DMA_SRC_SEL1_CH5_SRC_Msk /*!< CH5 source select */ +#define DMA_SRC_SEL1_CH6_SRC_Pos (8U) +#define DMA_SRC_SEL1_CH6_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH6_SRC_Pos) /*!< 0x0000FF00 */ +#define DMA_SRC_SEL1_CH6_SRC DMA_SRC_SEL1_CH6_SRC_Msk /*!< CH6 source select */ +#define DMA_SRC_SEL1_CH7_SRC_Pos (16U) +#define DMA_SRC_SEL1_CH7_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH7_SRC_Pos) /*!< 0x00FF0000 */ +#define DMA_SRC_SEL1_CH7_SRC DMA_SRC_SEL1_CH7_SRC_Msk /*!< CH7 source select */ +#define DMA_SRC_SEL1_DMA_FLEX_EN_Pos (24U) +#define DMA_SRC_SEL1_DMA_FLEX_EN_Msk (0x1U << DMA_SRC_SEL1_DMA_FLEX_EN_Pos) /*!< 0x01000000 */ +#define DMA_SRC_SEL1_DMA_FLEX_EN DMA_SRC_SEL1_DMA_FLEX_EN_Msk /*!< DMA flexible request mapping enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for CRC_DT register ********************/ +#define CRC_DT_DT_Pos (0U) +#define CRC_DT_DT_Msk (0xFFFFFFFFU << CRC_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DT_DT CRC_DT_DT_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_CDT register ********************/ +#define CRC_CDT_CDT_Pos (0U) +#define CRC_CDT_CDT_Msk (0xFFU << CRC_CDT_CDT_Pos) /*!< 0x000000FF */ +#define CRC_CDT_CDT CRC_CDT_CDT_Msk /*!< General-purpose 8-bit data register bits */ + +/******************* Bit definition for CRC_CTRL register *******************/ +#define CRC_CTRL_RST_Pos (0U) +#define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ +#define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ + +/*!< REVID configuration */ +#define CRC_CTRL_REVID_Pos (5U) +#define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID CRC_CTRL_REVID_Msk /*!< REVID[1:0] bits (Reverse input data) */ +#define CRC_CTRL_REVID_0 (0x1U << CRC_CTRL_REVID_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_1 (0x2U << CRC_CTRL_REVID_Pos) /*!< 0x00000040 */ + +#define CRC_CTRL_REVID_NOREV 0x00000000U /*!< No effect */ +#define CRC_CTRL_REVID_BYTEREV_Pos (5U) +#define CRC_CTRL_REVID_BYTEREV_Msk (0x1U << CRC_CTRL_REVID_BYTEREV_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_BYTEREV CRC_CTRL_REVID_BYTEREV_Msk /*!< Byte reverse */ +#define CRC_CTRL_REVID_HALFREV_Pos (6U) +#define CRC_CTRL_REVID_HALFREV_Msk (0x1U << CRC_CTRL_REVID_HALFREV_Pos) /*!< 0x00000040 */ +#define CRC_CTRL_REVID_HALFREV CRC_CTRL_REVID_HALFREV_Msk /*!< Half-word reverse */ +#define CRC_CTRL_REVID_WORDREV_Pos (5U) +#define CRC_CTRL_REVID_WORDREV_Msk (0x3U << CRC_CTRL_REVID_WORDREV_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID_WORDREV CRC_CTRL_REVID_WORDREV_Msk /*!< Word reverse */ + +#define CRC_CTRL_REVOD_Pos (7U) +#define CRC_CTRL_REVOD_Msk (0x1U << CRC_CTRL_REVOD_Pos) /*!< 0x00000080 */ +#define CRC_CTRL_REVOD CRC_CTRL_REVOD_Msk /*!< Reverse output data */ + +/******************* Bit definition for CRC_IDT register ********************/ +#define CRC_IDT_IDT_Pos (0U) +#define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ + +/******************************************************************************/ +/* */ +/* Inter-integrated circuit interface (I2C) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2C_CTRL1 register *******************/ +#define I2C_CTRL1_I2CEN_Pos (0U) +#define I2C_CTRL1_I2CEN_Msk (0x1U << I2C_CTRL1_I2CEN_Pos) /*!< 0x00000001 */ +#define I2C_CTRL1_I2CEN I2C_CTRL1_I2CEN_Msk /*!< I2C peripheral enable */ +#define I2C_CTRL1_PERMODE_Pos (1U) +#define I2C_CTRL1_PERMODE_Msk (0x1U << I2C_CTRL1_PERMODE_Pos) /*!< 0x00000002 */ +#define I2C_CTRL1_PERMODE I2C_CTRL1_PERMODE_Msk /*!< I2C peripheral mode */ +#define I2C_CTRL1_SMBMODE_Pos (3U) +#define I2C_CTRL1_SMBMODE_Msk (0x1U << I2C_CTRL1_SMBMODE_Pos) /*!< 0x00000008 */ +#define I2C_CTRL1_SMBMODE I2C_CTRL1_SMBMODE_Msk /*!< SMBus device mode */ +#define I2C_CTRL1_ARPEN_Pos (4U) +#define I2C_CTRL1_ARPEN_Msk (0x1U << I2C_CTRL1_ARPEN_Pos) /*!< 0x00000010 */ +#define I2C_CTRL1_ARPEN I2C_CTRL1_ARPEN_Msk /*!< SMBus address resolution protocol enable */ +#define I2C_CTRL1_PECEN_Pos (5U) +#define I2C_CTRL1_PECEN_Msk (0x1U << I2C_CTRL1_PECEN_Pos) /*!< 0x00000020 */ +#define I2C_CTRL1_PECEN I2C_CTRL1_PECEN_Msk /*!< PEC calculation enable */ +#define I2C_CTRL1_GCAEN_Pos (6U) +#define I2C_CTRL1_GCAEN_Msk (0x1U << I2C_CTRL1_GCAEN_Pos) /*!< 0x00000040 */ +#define I2C_CTRL1_GCAEN I2C_CTRL1_GCAEN_Msk /*!< General call address enable */ +#define I2C_CTRL1_STRETCH_Pos (7U) +#define I2C_CTRL1_STRETCH_Msk (0x1U << I2C_CTRL1_STRETCH_Pos) /*!< 0x00000080 */ +#define I2C_CTRL1_STRETCH I2C_CTRL1_STRETCH_Msk /*!< Clock stretching mode */ +#define I2C_CTRL1_GENSTART_Pos (8U) +#define I2C_CTRL1_GENSTART_Msk (0x1U << I2C_CTRL1_GENSTART_Pos) /*!< 0x00000100 */ +#define I2C_CTRL1_GENSTART I2C_CTRL1_GENSTART_Msk /*!< Generate start condition */ +#define I2C_CTRL1_GENSTOP_Pos (9U) +#define I2C_CTRL1_GENSTOP_Msk (0x1U << I2C_CTRL1_GENSTOP_Pos) /*!< 0x00000200 */ +#define I2C_CTRL1_GENSTOP I2C_CTRL1_GENSTOP_Msk /*!< Generate stop condition */ +#define I2C_CTRL1_ACKEN_Pos (10U) +#define I2C_CTRL1_ACKEN_Msk (0x1U << I2C_CTRL1_ACKEN_Pos) /*!< 0x00000400 */ +#define I2C_CTRL1_ACKEN I2C_CTRL1_ACKEN_Msk /*!< Acknowledge enable */ +#define I2C_CTRL1_MACKCTRL_Pos (11U) +#define I2C_CTRL1_MACKCTRL_Msk (0x1U << I2C_CTRL1_MACKCTRL_Pos) /*!< 0x00000800 */ +#define I2C_CTRL1_MACKCTRL I2C_CTRL1_MACKCTRL_Msk /*!< Master receive mode acknowledge control */ +#define I2C_CTRL1_PECTEN_Pos (12U) +#define I2C_CTRL1_PECTEN_Msk (0x1U << I2C_CTRL1_PECTEN_Pos) /*!< 0x00001000 */ +#define I2C_CTRL1_PECTEN I2C_CTRL1_PECTEN_Msk /*!< Request PEC transfer enable */ +#define I2C_CTRL1_SMBALERT_Pos (13U) +#define I2C_CTRL1_SMBALERT_Msk (0x1U << I2C_CTRL1_SMBALERT_Pos) /*!< 0x00002000 */ +#define I2C_CTRL1_SMBALERT I2C_CTRL1_SMBALERT_Msk /*!< SMBus alert pin set */ +#define I2C_CTRL1_RESET_Pos (15U) +#define I2C_CTRL1_RESET_Msk (0x1U << I2C_CTRL1_RESET_Pos) /*!< 0x00008000 */ +#define I2C_CTRL1_RESET I2C_CTRL1_RESET_Msk /*!< I2C peripheral reset */ + +/****************** Bit definition for I2C_CTRL2 register *******************/ +/*!< CLKFREQ configuration */ +#define I2C_CTRL2_CLKFREQ_Pos (0U) +#define I2C_CTRL2_CLKFREQ_Msk (0xFFU << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x000000FF */ +#define I2C_CTRL2_CLKFREQ I2C_CTRL2_CLKFREQ_Msk /*!< CLKFREQ[7:0] bits (I2C input clock frequency) */ +#define I2C_CTRL2_CLKFREQ_0 (0x01U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000001 */ +#define I2C_CTRL2_CLKFREQ_1 (0x02U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000002 */ +#define I2C_CTRL2_CLKFREQ_2 (0x04U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000004 */ +#define I2C_CTRL2_CLKFREQ_3 (0x08U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000008 */ +#define I2C_CTRL2_CLKFREQ_4 (0x10U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000010 */ +#define I2C_CTRL2_CLKFREQ_5 (0x20U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000020 */ +#define I2C_CTRL2_CLKFREQ_6 (0x40U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000040 */ +#define I2C_CTRL2_CLKFREQ_7 (0x80U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000080 */ + +#define I2C_CTRL2_ERRIEN_Pos (8U) +#define I2C_CTRL2_ERRIEN_Msk (0x1U << I2C_CTRL2_ERRIEN_Pos) /*!< 0x00000100 */ +#define I2C_CTRL2_ERRIEN I2C_CTRL2_ERRIEN_Msk /*!< Error interrupt enable */ +#define I2C_CTRL2_EVTIEN_Pos (9U) +#define I2C_CTRL2_EVTIEN_Msk (0x1U << I2C_CTRL2_EVTIEN_Pos) /*!< 0x00000200 */ +#define I2C_CTRL2_EVTIEN I2C_CTRL2_EVTIEN_Msk /*!< Event interrupt enable */ +#define I2C_CTRL2_DATAIEN_Pos (10U) +#define I2C_CTRL2_DATAIEN_Msk (0x1U << I2C_CTRL2_DATAIEN_Pos) /*!< 0x00000400 */ +#define I2C_CTRL2_DATAIEN I2C_CTRL2_DATAIEN_Msk /*!< Data transfer interrupt enable */ +#define I2C_CTRL2_DMAEN_Pos (11U) +#define I2C_CTRL2_DMAEN_Msk (0x1U << I2C_CTRL2_DMAEN_Pos) /*!< 0x00000800 */ +#define I2C_CTRL2_DMAEN I2C_CTRL2_DMAEN_Msk /*!< DMA transfer enable */ +#define I2C_CTRL2_DMAEND_Pos (12U) +#define I2C_CTRL2_DMAEND_Msk (0x1U << I2C_CTRL2_DMAEND_Pos) /*!< 0x00001000 */ +#define I2C_CTRL2_DMAEND I2C_CTRL2_DMAEND_Msk /*!< End of DMA transfer */ + +/****************** Bit definition for I2C_OADDR1 register ******************/ +/*!< ADDR1 configuration */ +#define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ +#define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ +#define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ +#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ +#define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ +#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ +#define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ +#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ +#define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ +#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ +#define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ +#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ +#define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ +#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ +#define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ +#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ +#define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ +#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ +#define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ + +#define I2C_OADDR1_ADDR1MODE_Pos (15U) +#define I2C_OADDR1_ADDR1MODE_Msk (0x1U << I2C_OADDR1_ADDR1MODE_Pos) /*!< 0x00008000 */ +#define I2C_OADDR1_ADDR1MODE I2C_OADDR1_ADDR1MODE_Msk /*!< Address mode */ + +/****************** Bit definition for I2C_OADDR2 register ******************/ +#define I2C_OADDR2_ADDR2EN_Pos (0U) +#define I2C_OADDR2_ADDR2EN_Msk (0x1U << I2C_OADDR2_ADDR2EN_Pos) /*!< 0x00000001 */ +#define I2C_OADDR2_ADDR2EN I2C_OADDR2_ADDR2EN_Msk /*!< Own address 2 enable */ +#define I2C_OADDR2_ADDR2_Pos (1U) +#define I2C_OADDR2_ADDR2_Msk (0x7FU << I2C_OADDR2_ADDR2_Pos) /*!< 0x000000FE */ +#define I2C_OADDR2_ADDR2 I2C_OADDR2_ADDR2_Msk /*!< Own address 2 */ + +/******************** Bit definition for I2C_DT register ********************/ +#define I2C_DT_DT_Pos (0U) +#define I2C_DT_DT_Msk (0xFFU << I2C_DT_DT_Pos) /*!< 0x000000FF */ +#define I2C_DT_DT I2C_DT_DT_Msk /*!< This field is used to store data received or to be transferred */ + +/******************* Bit definition for I2C_STS1 register *******************/ +#define I2C_STS1_STARTF_Pos (0U) +#define I2C_STS1_STARTF_Msk (0x1U << I2C_STS1_STARTF_Pos) /*!< 0x00000001 */ +#define I2C_STS1_STARTF I2C_STS1_STARTF_Msk /*!< Start condition generation complete flag */ +#define I2C_STS1_ADDR7F_Pos (1U) +#define I2C_STS1_ADDR7F_Msk (0x1U << I2C_STS1_ADDR7F_Pos) /*!< 0x00000002 */ +#define I2C_STS1_ADDR7F I2C_STS1_ADDR7F_Msk /*!< 0 ~ 7 bit address match flag */ +#define I2C_STS1_TDC_Pos (2U) +#define I2C_STS1_TDC_Msk (0x1U << I2C_STS1_TDC_Pos) /*!< 0x00000004 */ +#define I2C_STS1_TDC I2C_STS1_TDC_Msk /*!< Data transfer complete flag */ +#define I2C_STS1_ADDRHF_Pos (3U) +#define I2C_STS1_ADDRHF_Msk (0x1U << I2C_STS1_ADDRHF_Pos) /*!< 0x00000008 */ +#define I2C_STS1_ADDRHF I2C_STS1_ADDRHF_Msk /*!< Master 9 ~ 8 bit address head match flag */ +#define I2C_STS1_STOPF_Pos (4U) +#define I2C_STS1_STOPF_Msk (0x1U << I2C_STS1_STOPF_Pos) /*!< 0x00000010 */ +#define I2C_STS1_STOPF I2C_STS1_STOPF_Msk /*!< Stop condition generation complete flag */ +#define I2C_STS1_RDBF_Pos (6U) +#define I2C_STS1_RDBF_Msk (0x1U << I2C_STS1_RDBF_Pos) /*!< 0x00000040 */ +#define I2C_STS1_RDBF I2C_STS1_RDBF_Msk /*!< Receive data buffer full flag */ +#define I2C_STS1_TDBE_Pos (7U) +#define I2C_STS1_TDBE_Msk (0x1U << I2C_STS1_TDBE_Pos) /*!< 0x00000080 */ +#define I2C_STS1_TDBE I2C_STS1_TDBE_Msk /*!< Transmit data buffer empty flag */ +#define I2C_STS1_BUSERR_Pos (8U) +#define I2C_STS1_BUSERR_Msk (0x1U << I2C_STS1_BUSERR_Pos) /*!< 0x00000100 */ +#define I2C_STS1_BUSERR I2C_STS1_BUSERR_Msk /*!< Bus error flag */ +#define I2C_STS1_ARLOST_Pos (9U) +#define I2C_STS1_ARLOST_Msk (0x1U << I2C_STS1_ARLOST_Pos) /*!< 0x00000200 */ +#define I2C_STS1_ARLOST I2C_STS1_ARLOST_Msk /*!< Arbitration lost flag */ +#define I2C_STS1_ACKFAIL_Pos (10U) +#define I2C_STS1_ACKFAIL_Msk (0x1U << I2C_STS1_ACKFAIL_Pos) /*!< 0x00000400 */ +#define I2C_STS1_ACKFAIL I2C_STS1_ACKFAIL_Msk /*!< Acknowledge failure flag */ +#define I2C_STS1_OUF_Pos (11U) +#define I2C_STS1_OUF_Msk (0x1U << I2C_STS1_OUF_Pos) /*!< 0x00000800 */ +#define I2C_STS1_OUF I2C_STS1_OUF_Msk /*!< Overload / underload flag */ +#define I2C_STS1_PECERR_Pos (12U) +#define I2C_STS1_PECERR_Msk (0x1U << I2C_STS1_PECERR_Pos) /*!< 0x00001000 */ +#define I2C_STS1_PECERR I2C_STS1_PECERR_Msk /*!< PEC receive error flag */ +#define I2C_STS1_TMOUT_Pos (14U) +#define I2C_STS1_TMOUT_Msk (0x1U << I2C_STS1_TMOUT_Pos) /*!< 0x00004000 */ +#define I2C_STS1_TMOUT I2C_STS1_TMOUT_Msk /*!< SMBus timeout flag */ +#define I2C_STS1_ALERTF_Pos (15U) +#define I2C_STS1_ALERTF_Msk (0x1U << I2C_STS1_ALERTF_Pos) /*!< 0x00008000 */ +#define I2C_STS1_ALERTF I2C_STS1_ALERTF_Msk /*!< SMBus alert flag */ + +/******************* Bit definition for I2C_STS2 register *******************/ +#define I2C_STS2_TRMODE_Pos (0U) +#define I2C_STS2_TRMODE_Msk (0x1U << I2C_STS2_TRMODE_Pos) /*!< 0x00000001 */ +#define I2C_STS2_TRMODE I2C_STS2_TRMODE_Msk /*!< Transmission mode */ +#define I2C_STS2_BUSYF_Pos (1U) +#define I2C_STS2_BUSYF_Msk (0x1U << I2C_STS2_BUSYF_Pos) /*!< 0x00000002 */ +#define I2C_STS2_BUSYF I2C_STS2_BUSYF_Msk /*!< Bus busy flag transmission mode */ +#define I2C_STS2_DIRF_Pos (2U) +#define I2C_STS2_DIRF_Msk (0x1U << I2C_STS2_DIRF_Pos) /*!< 0x00000004 */ +#define I2C_STS2_DIRF I2C_STS2_DIRF_Msk /*!< Transmission direction flag */ +#define I2C_STS2_GCADDRF_Pos (4U) +#define I2C_STS2_GCADDRF_Msk (0x1U << I2C_STS2_GCADDRF_Pos) /*!< 0x00000010 */ +#define I2C_STS2_GCADDRF I2C_STS2_GCADDRF_Msk /*!< General call address reception flag */ +#define I2C_STS2_DEVADDRF_Pos (5U) +#define I2C_STS2_DEVADDRF_Msk (0x1U << I2C_STS2_DEVADDRF_Pos) /*!< 0x00000020 */ +#define I2C_STS2_DEVADDRF I2C_STS2_DEVADDRF_Msk /*!< SMBus device address reception flag */ +#define I2C_STS2_HOSTADDRF_Pos (6U) +#define I2C_STS2_HOSTADDRF_Msk (0x1U << I2C_STS2_HOSTADDRF_Pos) /*!< 0x00000040 */ +#define I2C_STS2_HOSTADDRF I2C_STS2_HOSTADDRF_Msk /*!< SMBus host address reception flag */ +#define I2C_STS2_ADDR2F_Pos (7U) +#define I2C_STS2_ADDR2F_Msk (0x1U << I2C_STS2_ADDR2F_Pos) /*!< 0x00000080 */ +#define I2C_STS2_ADDR2F I2C_STS2_ADDR2F_Msk /*!< Received address 2 flag */ +#define I2C_STS2_PECVAL_Pos (8U) +#define I2C_STS2_PECVAL_Msk (0xFFU << I2C_STS2_PECVAL_Pos) /*!< 0x0000FF00 */ +#define I2C_STS2_PECVAL I2C_STS2_PECVAL_Msk /*!< PEC value */ + +/***************** Bit definition for I2C_CLKCTRL register ******************/ +#define I2C_CLKCTRL_SPEED_Pos (0U) +#define I2C_CLKCTRL_SPEED_Msk (0xFFFU << I2C_CLKCTRL_SPEED_Pos) /*!< 0x00000FFF */ +#define I2C_CLKCTRL_SPEED I2C_CLKCTRL_SPEED_Msk /*!< I2C bus speed config */ +#define I2C_CLKCTRL_DUTYMODE_Pos (14U) +#define I2C_CLKCTRL_DUTYMODE_Msk (0x1U << I2C_CLKCTRL_DUTYMODE_Pos) /*!< 0x00004000 */ +#define I2C_CLKCTRL_DUTYMODE I2C_CLKCTRL_DUTYMODE_Msk /*!< Fast mode duty cycle */ +#define I2C_CLKCTRL_SPEEDMODE_Pos (15U) +#define I2C_CLKCTRL_SPEEDMODE_Msk (0x1U << I2C_CLKCTRL_SPEEDMODE_Pos) /*!< 0x00008000 */ +#define I2C_CLKCTRL_SPEEDMODE I2C_CLKCTRL_SPEEDMODE_Msk /*!< Speed mode selection */ + +/****************** Bit definition for I2C_TMRISE register ******************/ +#define I2C_TMRISE_RISETIME_Pos (0U) +#define I2C_TMRISE_RISETIME_Msk (0x3FU << I2C_TMRISE_RISETIME_Pos) /*!< 0x0000003F */ +#define I2C_TMRISE_RISETIME I2C_TMRISE_RISETIME_Msk /*!< I2C bus rise time */ + +/******************************************************************************/ +/* */ +/* Universal synchronous/asynchronous receiver/transmitter (USART) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for USART_STS register *******************/ +#define USART_STS_PERR_Pos (0U) +#define USART_STS_PERR_Msk (0x1U << USART_STS_PERR_Pos) /*!< 0x00000001 */ +#define USART_STS_PERR USART_STS_PERR_Msk /*!< Parity error */ +#define USART_STS_FERR_Pos (1U) +#define USART_STS_FERR_Msk (0x1U << USART_STS_FERR_Pos) /*!< 0x00000002 */ +#define USART_STS_FERR USART_STS_FERR_Msk /*!< Framing error */ +#define USART_STS_NERR_Pos (2U) +#define USART_STS_NERR_Msk (0x1U << USART_STS_NERR_Pos) /*!< 0x00000004 */ +#define USART_STS_NERR USART_STS_NERR_Msk /*!< Noise error */ +#define USART_STS_ROERR_Pos (3U) +#define USART_STS_ROERR_Msk (0x1U << USART_STS_ROERR_Pos) /*!< 0x00000008 */ +#define USART_STS_ROERR USART_STS_ROERR_Msk /*!< Receiver overflow error */ +#define USART_STS_IDLEF_Pos (4U) +#define USART_STS_IDLEF_Msk (0x1U << USART_STS_IDLEF_Pos) /*!< 0x00000010 */ +#define USART_STS_IDLEF USART_STS_IDLEF_Msk /*!< Idle flag */ +#define USART_STS_RDBF_Pos (5U) +#define USART_STS_RDBF_Msk (0x1U << USART_STS_RDBF_Pos) /*!< 0x00000020 */ +#define USART_STS_RDBF USART_STS_RDBF_Msk /*!< Receive data buffer full */ +#define USART_STS_TDC_Pos (6U) +#define USART_STS_TDC_Msk (0x1U << USART_STS_TDC_Pos) /*!< 0x00000040 */ +#define USART_STS_TDC USART_STS_TDC_Msk /*!< Transmit data complete */ +#define USART_STS_TDBE_Pos (7U) +#define USART_STS_TDBE_Msk (0x1U << USART_STS_TDBE_Pos) /*!< 0x00000080 */ +#define USART_STS_TDBE USART_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define USART_STS_BFF_Pos (8U) +#define USART_STS_BFF_Msk (0x1U << USART_STS_BFF_Pos) /*!< 0x00000100 */ +#define USART_STS_BFF USART_STS_BFF_Msk /*!< Break frame flag */ +#define USART_STS_CTSCF_Pos (9U) +#define USART_STS_CTSCF_Msk (0x1U << USART_STS_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_STS_CTSCF USART_STS_CTSCF_Msk /*!< CTS change flag */ + +/******************* Bit definition for USART_DT register *******************/ +#define USART_DT_DT_Pos (0U) +#define USART_DT_DT_Msk (0x1FFU << USART_DT_DT_Pos) /*!< 0x000001FF */ +#define USART_DT_DT USART_DT_DT_Msk /*!< Data value */ + +/***************** Bit definition for USART_BAUDR register ******************/ +#define USART_BAUDR_DIV_Pos (0U) +#define USART_BAUDR_DIV_Msk (0xFFFFU << USART_BAUDR_DIV_Pos) /*!< 0x0000FFFF */ +#define USART_BAUDR_DIV USART_BAUDR_DIV_Msk /*!< Divider */ + +/***************** Bit definition for USART_CTRL1 register ******************/ +#define USART_CTRL1_SBF_Pos (0U) +#define USART_CTRL1_SBF_Msk (0x1U << USART_CTRL1_SBF_Pos) /*!< 0x00000001 */ +#define USART_CTRL1_SBF USART_CTRL1_SBF_Msk /*!< Send break frame */ +#define USART_CTRL1_RM_Pos (1U) +#define USART_CTRL1_RM_Msk (0x1U << USART_CTRL1_RM_Pos) /*!< 0x00000002 */ +#define USART_CTRL1_RM USART_CTRL1_RM_Msk /*!< Receiver mute */ +#define USART_CTRL1_REN_Pos (2U) +#define USART_CTRL1_REN_Msk (0x1U << USART_CTRL1_REN_Pos) /*!< 0x00000004 */ +#define USART_CTRL1_REN USART_CTRL1_REN_Msk /*!< Receiver enable */ +#define USART_CTRL1_TEN_Pos (3U) +#define USART_CTRL1_TEN_Msk (0x1U << USART_CTRL1_TEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL1_TEN USART_CTRL1_TEN_Msk /*!< Transmitter enable */ +#define USART_CTRL1_IDLEIEN_Pos (4U) +#define USART_CTRL1_IDLEIEN_Msk (0x1U << USART_CTRL1_IDLEIEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL1_IDLEIEN USART_CTRL1_IDLEIEN_Msk /*!< IDLE interrupt enable */ +#define USART_CTRL1_RDBFIEN_Pos (5U) +#define USART_CTRL1_RDBFIEN_Msk (0x1U << USART_CTRL1_RDBFIEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL1_RDBFIEN USART_CTRL1_RDBFIEN_Msk /*!< RDBF interrupt enable */ +#define USART_CTRL1_TDCIEN_Pos (6U) +#define USART_CTRL1_TDCIEN_Msk (0x1U << USART_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL1_TDCIEN USART_CTRL1_TDCIEN_Msk /*!< TDC interrupt enable */ +#define USART_CTRL1_TDBEIEN_Pos (7U) +#define USART_CTRL1_TDBEIEN_Msk (0x1U << USART_CTRL1_TDBEIEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL1_TDBEIEN USART_CTRL1_TDBEIEN_Msk /*!< TDBE interrupt enable */ +#define USART_CTRL1_PERRIEN_Pos (8U) +#define USART_CTRL1_PERRIEN_Msk (0x1U << USART_CTRL1_PERRIEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL1_PERRIEN USART_CTRL1_PERRIEN_Msk /*!< PERR interrupt enable */ +#define USART_CTRL1_PSEL_Pos (9U) +#define USART_CTRL1_PSEL_Msk (0x1U << USART_CTRL1_PSEL_Pos) /*!< 0x00000200 */ +#define USART_CTRL1_PSEL USART_CTRL1_PSEL_Msk /*!< Parity selection */ +#define USART_CTRL1_PEN_Pos (10U) +#define USART_CTRL1_PEN_Msk (0x1U << USART_CTRL1_PEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL1_PEN USART_CTRL1_PEN_Msk /*!< Parity enable */ +#define USART_CTRL1_WUM_Pos (11U) +#define USART_CTRL1_WUM_Msk (0x1U << USART_CTRL1_WUM_Pos) /*!< 0x00000800 */ +#define USART_CTRL1_WUM USART_CTRL1_WUM_Msk /*!< Wakeup mode */ +#define USART_CTRL1_DBN_Pos (12U) +#define USART_CTRL1_DBN_Msk (0x1U << USART_CTRL1_DBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL1_DBN USART_CTRL1_DBN_Msk /*!< Data bit num */ +#define USART_CTRL1_UEN_Pos (13U) +#define USART_CTRL1_UEN_Msk (0x1U << USART_CTRL1_UEN_Pos) /*!< 0x00002000 */ +#define USART_CTRL1_UEN USART_CTRL1_UEN_Msk /*!< USART enable */ + +/***************** Bit definition for USART_CTRL2 register ******************/ +#define USART_CTRL2_ID_Pos (0U) +#define USART_CTRL2_ID_Msk (0xFU << USART_CTRL2_ID_Pos) /*!< 0x0000000F */ +#define USART_CTRL2_ID USART_CTRL2_ID_Msk /*!< USART identification */ +#define USART_CTRL2_BFBN_Pos (5U) +#define USART_CTRL2_BFBN_Msk (0x1U << USART_CTRL2_BFBN_Pos) /*!< 0x00000020 */ +#define USART_CTRL2_BFBN USART_CTRL2_BFBN_Msk /*!< Break frame bit num */ +#define USART_CTRL2_BFIEN_Pos (6U) +#define USART_CTRL2_BFIEN_Msk (0x1U << USART_CTRL2_BFIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL2_BFIEN USART_CTRL2_BFIEN_Msk /*!< Break frame interrupt enable */ +#define USART_CTRL2_LBCP_Pos (8U) +#define USART_CTRL2_LBCP_Msk (0x1U << USART_CTRL2_LBCP_Pos) /*!< 0x00000100 */ +#define USART_CTRL2_LBCP USART_CTRL2_LBCP_Msk /*!< Last bit clock pulse */ +#define USART_CTRL2_CLKPHA_Pos (9U) +#define USART_CTRL2_CLKPHA_Msk (0x1U << USART_CTRL2_CLKPHA_Pos) /*!< 0x00000200 */ +#define USART_CTRL2_CLKPHA USART_CTRL2_CLKPHA_Msk /*!< Clock phase */ +#define USART_CTRL2_CLKPOL_Pos (10U) +#define USART_CTRL2_CLKPOL_Msk (0x1U << USART_CTRL2_CLKPOL_Pos) /*!< 0x00000400 */ +#define USART_CTRL2_CLKPOL USART_CTRL2_CLKPOL_Msk /*!< Clock polarity */ +#define USART_CTRL2_CLKEN_Pos (11U) +#define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ + +#define USART_CTRL2_STOPBN_Pos (12U) +#define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ +#define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ +#define USART_CTRL2_STOPBN_0 (0x1U << USART_CTRL2_STOPBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL2_STOPBN_1 (0x2U << USART_CTRL2_STOPBN_Pos) /*!< 0x00002000 */ + +#define USART_CTRL2_LINEN_Pos (14U) +#define USART_CTRL2_LINEN_Msk (0x1U << USART_CTRL2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CTRL2_LINEN USART_CTRL2_LINEN_Msk /*!< LIN mode enable */ + +/***************** Bit definition for USART_CTRL3 register ******************/ +#define USART_CTRL3_ERRIEN_Pos (0U) +#define USART_CTRL3_ERRIEN_Msk (0x1U << USART_CTRL3_ERRIEN_Pos) /*!< 0x00000001 */ +#define USART_CTRL3_ERRIEN USART_CTRL3_ERRIEN_Msk /*!< Error interrupt enable */ +#define USART_CTRL3_IRDAEN_Pos (1U) +#define USART_CTRL3_IRDAEN_Msk (0x1U << USART_CTRL3_IRDAEN_Pos) /*!< 0x00000002 */ +#define USART_CTRL3_IRDAEN USART_CTRL3_IRDAEN_Msk /*!< IrDA enable */ +#define USART_CTRL3_IRDALP_Pos (2U) +#define USART_CTRL3_IRDALP_Msk (0x1U << USART_CTRL3_IRDALP_Pos) /*!< 0x00000004 */ +#define USART_CTRL3_IRDALP USART_CTRL3_IRDALP_Msk /*!< IrDA low-power mode */ +#define USART_CTRL3_SLBEN_Pos (3U) +#define USART_CTRL3_SLBEN_Msk (0x1U << USART_CTRL3_SLBEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL3_SLBEN USART_CTRL3_SLBEN_Msk /*!< Single-wire bidirectional half-duplex enable */ +#define USART_CTRL3_SCNACKEN_Pos (4U) +#define USART_CTRL3_SCNACKEN_Msk (0x1U << USART_CTRL3_SCNACKEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL3_SCNACKEN USART_CTRL3_SCNACKEN_Msk /*!< Smart Card NACK enable */ +#define USART_CTRL3_SCMEN_Pos (5U) +#define USART_CTRL3_SCMEN_Msk (0x1U << USART_CTRL3_SCMEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL3_SCMEN USART_CTRL3_SCMEN_Msk /*!< Smart Card mode enable */ +#define USART_CTRL3_DMAREN_Pos (6U) +#define USART_CTRL3_DMAREN_Msk (0x1U << USART_CTRL3_DMAREN_Pos) /*!< 0x00000040 */ +#define USART_CTRL3_DMAREN USART_CTRL3_DMAREN_Msk /*!< DMA receiver enable */ +#define USART_CTRL3_DMATEN_Pos (7U) +#define USART_CTRL3_DMATEN_Msk (0x1U << USART_CTRL3_DMATEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL3_DMATEN USART_CTRL3_DMATEN_Msk /*!< DMA transmitter enable */ +#define USART_CTRL3_RTSEN_Pos (8U) +#define USART_CTRL3_RTSEN_Msk (0x1U << USART_CTRL3_RTSEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL3_RTSEN USART_CTRL3_RTSEN_Msk /*!< RTS enable */ +#define USART_CTRL3_CTSEN_Pos (9U) +#define USART_CTRL3_CTSEN_Msk (0x1U << USART_CTRL3_CTSEN_Pos) /*!< 0x00000200 */ +#define USART_CTRL3_CTSEN USART_CTRL3_CTSEN_Msk /*!< CTS enable */ +#define USART_CTRL3_CTSCFIEN_Pos (10U) +#define USART_CTRL3_CTSCFIEN_Msk (0x1U << USART_CTRL3_CTSCFIEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ + +/****************** Bit definition for USART_GDIV register ******************/ +#define USART_GDIV_ISDIV_Pos (0U) +#define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ +#define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ +#define USART_GDIV_ISDIV_0 (0x01U << USART_GDIV_ISDIV_Pos) /*!< 0x00000001 */ +#define USART_GDIV_ISDIV_1 (0x02U << USART_GDIV_ISDIV_Pos) /*!< 0x00000002 */ +#define USART_GDIV_ISDIV_2 (0x04U << USART_GDIV_ISDIV_Pos) /*!< 0x00000004 */ +#define USART_GDIV_ISDIV_3 (0x08U << USART_GDIV_ISDIV_Pos) /*!< 0x00000008 */ +#define USART_GDIV_ISDIV_4 (0x10U << USART_GDIV_ISDIV_Pos) /*!< 0x00000010 */ +#define USART_GDIV_ISDIV_5 (0x20U << USART_GDIV_ISDIV_Pos) /*!< 0x00000020 */ +#define USART_GDIV_ISDIV_6 (0x40U << USART_GDIV_ISDIV_Pos) /*!< 0x00000040 */ +#define USART_GDIV_ISDIV_7 (0x80U << USART_GDIV_ISDIV_Pos) /*!< 0x00000080 */ + +#define USART_GDIV_SCGT_Pos (8U) +#define USART_GDIV_SCGT_Msk (0xFFU << USART_GDIV_SCGT_Pos) /*!< 0x0000FF00 */ +#define USART_GDIV_SCGT USART_GDIV_SCGT_Msk /*!< Smart Card guard time value */ + +/******************************************************************************/ +/* */ +/* Serial peripheral interface (SPI) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SPI_CTRL1 register *******************/ +#define SPI_CTRL1_CLKPHA_Pos (0U) +#define SPI_CTRL1_CLKPHA_Msk (0x1U << SPI_CTRL1_CLKPHA_Pos) /*!< 0x00000001 */ +#define SPI_CTRL1_CLKPHA SPI_CTRL1_CLKPHA_Msk /*!< Clock phase */ +#define SPI_CTRL1_CLKPOL_Pos (1U) +#define SPI_CTRL1_CLKPOL_Msk (0x1U << SPI_CTRL1_CLKPOL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL1_CLKPOL SPI_CTRL1_CLKPOL_Msk /*!< Clock polarity */ +#define SPI_CTRL1_MSTEN_Pos (2U) +#define SPI_CTRL1_MSTEN_Msk (0x1U << SPI_CTRL1_MSTEN_Pos) /*!< 0x00000004 */ +#define SPI_CTRL1_MSTEN SPI_CTRL1_MSTEN_Msk /*!< Master enable */ + +/*!< MDIV configuration */ +#define SPI_CTRL1_MDIV_Msk ((SPI_CTRL2_MDIV) | (0x7U << 3) /*!< 0x00000138 */ +#define SPI_CTRL1_MDIV SPI_CTRL1_MDIV_Msk /*!< MDIV[3:0] bits (Master clock frequency division) */ +#define SPI_CTRL1_MDIV_0 (0x1U << 3) /*!< 0x00000008 */ +#define SPI_CTRL1_MDIV_1 (0x2U << 3) /*!< 0x00000010 */ +#define SPI_CTRL1_MDIV_2 (0x4U << 3) /*!< 0x00000020 */ +#define SPI_CTRL1_MDIV_3 SPI_CTRL2_MDIV /*!< 0x00000100 */ + +#define SPI_CTRL1_SPIEN_Pos (6U) +#define SPI_CTRL1_SPIEN_Msk (0x1U << SPI_CTRL1_SPIEN_Pos) /*!< 0x00000040 */ +#define SPI_CTRL1_SPIEN SPI_CTRL1_SPIEN_Msk /*!< SPI enable */ +#define SPI_CTRL1_LTF_Pos (7U) +#define SPI_CTRL1_LTF_Msk (0x1U << SPI_CTRL1_LTF_Pos) /*!< 0x00000080 */ +#define SPI_CTRL1_LTF SPI_CTRL1_LTF_Msk /*!< LSB transmit first */ +#define SPI_CTRL1_SWCSIL_Pos (8U) +#define SPI_CTRL1_SWCSIL_Msk (0x1U << SPI_CTRL1_SWCSIL_Pos) /*!< 0x00000100 */ +#define SPI_CTRL1_SWCSIL SPI_CTRL1_SWCSIL_Msk /*!< Software CS internal level */ +#define SPI_CTRL1_SWCSEN_Pos (9U) +#define SPI_CTRL1_SWCSEN_Msk (0x1U << SPI_CTRL1_SWCSEN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL1_SWCSEN SPI_CTRL1_SWCSEN_Msk /*!< Software CS enable */ +#define SPI_CTRL1_ORA_Pos (10U) +#define SPI_CTRL1_ORA_Msk (0x1U << SPI_CTRL1_ORA_Pos) /*!< 0x00000400 */ +#define SPI_CTRL1_ORA SPI_CTRL1_ORA_Msk /*!< Receive-only active */ +#define SPI_CTRL1_FBN_Pos (11U) +#define SPI_CTRL1_FBN_Msk (0x1U << SPI_CTRL1_FBN_Pos) /*!< 0x00000800 */ +#define SPI_CTRL1_FBN SPI_CTRL1_FBN_Msk /*!< Frame bit num */ +#define SPI_CTRL1_NTC_Pos (12U) +#define SPI_CTRL1_NTC_Msk (0x1U << SPI_CTRL1_NTC_Pos) /*!< 0x00001000 */ +#define SPI_CTRL1_NTC SPI_CTRL1_NTC_Msk /*!< Transmit CRC next */ +#define SPI_CTRL1_CCEN_Pos (13U) +#define SPI_CTRL1_CCEN_Msk (0x1U << SPI_CTRL1_CCEN_Pos) /*!< 0x00002000 */ +#define SPI_CTRL1_CCEN SPI_CTRL1_CCEN_Msk /*!< RC calculation enable */ +#define SPI_CTRL1_SLBTD_Pos (14U) +#define SPI_CTRL1_SLBTD_Msk (0x1U << SPI_CTRL1_SLBTD_Pos) /*!< 0x00004000 */ +#define SPI_CTRL1_SLBTD SPI_CTRL1_SLBTD_Msk /*!< Single line bidirectional half-duplex transmission direction */ +#define SPI_CTRL1_SLBEN_Pos (15U) +#define SPI_CTRL1_SLBEN_Msk (0x1U << SPI_CTRL1_SLBEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL1_SLBEN SPI_CTRL1_SLBEN_Msk /*!< Single line bidirectional half-duplex enable */ + +/****************** Bit definition for SPI_CTRL2 register *******************/ +#define SPI_CTRL2_DMAREN_Pos (0U) +#define SPI_CTRL2_DMAREN_Msk (0x1U << SPI_CTRL2_DMAREN_Pos) /*!< 0x00000001 */ +#define SPI_CTRL2_DMAREN SPI_CTRL2_DMAREN_Msk /*!< DMA receive enable */ +#define SPI_CTRL2_DMATEN_Pos (1U) +#define SPI_CTRL2_DMATEN_Msk (0x1U << SPI_CTRL2_DMATEN_Pos) /*!< 0x00000002 */ +#define SPI_CTRL2_DMATEN SPI_CTRL2_DMATEN_Msk /*!< DMA transmit enable */ +#define SPI_CTRL2_HWCSOE_Pos (2U) +#define SPI_CTRL2_HWCSOE_Msk (0x1U << SPI_CTRL2_HWCSOE_Pos) /*!< 0x00000004 */ +#define SPI_CTRL2_HWCSOE SPI_CTRL2_HWCSOE_Msk /*!< Hardware CS output enable */ +#define SPI_CTRL2_ERRIE_Pos (5U) +#define SPI_CTRL2_ERRIE_Msk (0x1U << SPI_CTRL2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CTRL2_ERRIE SPI_CTRL2_ERRIE_Msk /*!< Error interrupt enable */ +#define SPI_CTRL2_RDBFIE_Pos (6U) +#define SPI_CTRL2_RDBFIE_Msk (0x1U << SPI_CTRL2_RDBFIE_Pos) /*!< 0x00000040 */ +#define SPI_CTRL2_RDBFIE SPI_CTRL2_RDBFIE_Msk /*!< Receive data buffer full interrupt enable */ +#define SPI_CTRL2_TDBEIE_Pos (7U) +#define SPI_CTRL2_TDBEIE_Msk (0x1U << SPI_CTRL2_TDBEIE_Pos) /*!< 0x00000080 */ +#define SPI_CTRL2_TDBEIE SPI_CTRL2_TDBEIE_Msk /*!< Transmit data buffer empty interrupt enable */ +#define SPI_CTRL2_MDIV_Pos (8U) +#define SPI_CTRL2_MDIV_Msk (0x1U << SPI_CTRL2_MDIV_Pos) /*!< 0x00000100 */ +#define SPI_CTRL2_MDIV SPI_CTRL2_MDIV_Msk /*!< Master clock frequency division */ + +/******************* Bit definition for SPI_STS register ********************/ +#define SPI_STS_RDBF_Pos (0U) +#define SPI_STS_RDBF_Msk (0x1U << SPI_STS_RDBF_Pos) /*!< 0x00000001 */ +#define SPI_STS_RDBF SPI_STS_RDBF_Msk /*!< Receive data buffer full */ +#define SPI_STS_TDBE_Pos (1U) +#define SPI_STS_TDBE_Msk (0x1U << SPI_STS_TDBE_Pos) /*!< 0x00000002 */ +#define SPI_STS_TDBE SPI_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define SPI_STS_ACS_Pos (2U) +#define SPI_STS_ACS_Msk (0x1U << SPI_STS_ACS_Pos) /*!< 0x00000004 */ +#define SPI_STS_ACS SPI_STS_ACS_Msk /*!< Audio channel state */ +#define SPI_STS_TUERR_Pos (3U) +#define SPI_STS_TUERR_Msk (0x1U << SPI_STS_TUERR_Pos) /*!< 0x00000008 */ +#define SPI_STS_TUERR SPI_STS_TUERR_Msk /*!< Transmitter underload error */ +#define SPI_STS_CCERR_Pos (4U) +#define SPI_STS_CCERR_Msk (0x1U << SPI_STS_CCERR_Pos) /*!< 0x00000010 */ +#define SPI_STS_CCERR SPI_STS_CCERR_Msk /*!< CRC error */ +#define SPI_STS_MMERR_Pos (5U) +#define SPI_STS_MMERR_Msk (0x1U << SPI_STS_MMERR_Pos) /*!< 0x00000020 */ +#define SPI_STS_MMERR SPI_STS_MMERR_Msk /*!< Master mode error */ +#define SPI_STS_ROERR_Pos (6U) +#define SPI_STS_ROERR_Msk (0x1U << SPI_STS_ROERR_Pos) /*!< 0x00000040 */ +#define SPI_STS_ROERR SPI_STS_ROERR_Msk /*!< Receiver overflow error */ +#define SPI_STS_BF_Pos (7U) +#define SPI_STS_BF_Msk (0x1U << SPI_STS_BF_Pos) /*!< 0x00000080 */ +#define SPI_STS_BF SPI_STS_BF_Msk /*!< Busy flag */ + +/******************** Bit definition for SPI_DT register ********************/ +#define SPI_DT_DT_Pos (0U) +#define SPI_DT_DT_Msk (0xFFFFU << SPI_DT_DT_Pos) /*!< 0x0000FFFF */ +#define SPI_DT_DT SPI_DT_DT_Msk /*!< Data value */ + +/******************* Bit definition for SPI_CPOLY register ******************/ +#define SPI_CPOLY_CPOLY_Pos (0U) +#define SPI_CPOLY_CPOLY_Msk (0xFFFFU << SPI_CPOLY_CPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CPOLY_CPOLY SPI_CPOLY_CPOLY_Msk /*!< CRC polynomial */ + +/******************* Bit definition for SPI_RCRC register *******************/ +#define SPI_RCRC_RCRC_Pos (0U) +#define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Receive CRC */ + +/******************* Bit definition for SPI_TCRC register *******************/ +#define SPI_TCRC_TCRC_Pos (0U) +#define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Transmit CRC */ + +/***************** Bit definition for SPI_I2SCTRL register ******************/ +#define SPI_I2SCTRL_I2SCBN_Pos (0U) +#define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ + +#define SPI_I2SCTRL_I2SDBN_Pos (1U) +#define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ +#define SPI_I2SCTRL_I2SDBN_0 (0x1U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCTRL_I2SDBN_1 (0x2U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCTRL_I2SCLKPOL_Pos (3U) +#define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ + +#define SPI_I2SCTRL_STDSEL_Pos (4U) +#define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ +#define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ +#define SPI_I2SCTRL_STDSEL_0 (0x1U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000010 */ +#define SPI_I2SCTRL_STDSEL_1 (0x2U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCTRL_PCMFSSEL_Pos (7U) +#define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ +#define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ + +#define SPI_I2SCTRL_OPERSEL_Pos (8U) +#define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ +#define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ +#define SPI_I2SCTRL_OPERSEL_0 (0x1U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000100 */ +#define SPI_I2SCTRL_OPERSEL_1 (0x2U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCTRL_I2SEN_Pos (10U) +#define SPI_I2SCTRL_I2SEN_Msk (0x1U << SPI_I2SCTRL_I2SEN_Pos) /*!< 0x00000400 */ +#define SPI_I2SCTRL_I2SEN SPI_I2SCTRL_I2SEN_Msk /*!< I2S enable */ +#define SPI_I2SCTRL_I2SMSEL_Pos (11U) +#define SPI_I2SCTRL_I2SMSEL_Msk (0x1U << SPI_I2SCTRL_I2SMSEL_Pos) /*!< 0x00000800 */ +#define SPI_I2SCTRL_I2SMSEL SPI_I2SCTRL_I2SMSEL_Msk /*!< I2S mode select */ + +/***************** Bit definition for SPI_I2SCLKP register ******************/ +#define SPI_I2SCLKP_I2SDIV_Msk ((0xFFU << 0) | (0x3U << 10)) /*!< 0x00000CFF */ +#define SPI_I2SCLKP_I2SDIV SPI_I2SCLKP_I2SDIV_Msk /*!< I2SDIV[9:0] bits (I2S division) */ +#define SPI_I2SCLKP_I2SODD_Pos (8U) +#define SPI_I2SCLKP_I2SODD_Msk (0x1U << SPI_I2SCLKP_I2SODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SCLKP_I2SODD SPI_I2SCLKP_I2SODD_Msk /*!< Odd factor for I2S division */ +#define SPI_I2SCLKP_I2SMCLKOE_Pos (9U) +#define SPI_I2SCLKP_I2SMCLKOE_Msk (0x1U << SPI_I2SCLKP_I2SMCLKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SCLKP_I2SMCLKOE SPI_I2SCLKP_I2SMCLKOE_Msk /*!< I2S Master clock output enable */ + +/******************************************************************************/ +/* */ +/* Window watchdog timer (WWDT) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for WWDT_CTRL register *******************/ +#define WWDT_CTRL_CNT_Pos (0U) +#define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ +#define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ +#define WWDT_CTRL_CNT_0 (0x01U << WWDT_CTRL_CNT_Pos) /*!< 0x00000001 */ +#define WWDT_CTRL_CNT_1 (0x02U << WWDT_CTRL_CNT_Pos) /*!< 0x00000002 */ +#define WWDT_CTRL_CNT_2 (0x04U << WWDT_CTRL_CNT_Pos) /*!< 0x00000004 */ +#define WWDT_CTRL_CNT_3 (0x08U << WWDT_CTRL_CNT_Pos) /*!< 0x00000008 */ +#define WWDT_CTRL_CNT_4 (0x10U << WWDT_CTRL_CNT_Pos) /*!< 0x00000010 */ +#define WWDT_CTRL_CNT_5 (0x20U << WWDT_CTRL_CNT_Pos) /*!< 0x00000020 */ +#define WWDT_CTRL_CNT_6 (0x40U << WWDT_CTRL_CNT_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CTRL_CNT0 WWDT_CTRL_CNT_0 +#define WWDT_CTRL_CNT1 WWDT_CTRL_CNT_1 +#define WWDT_CTRL_CNT2 WWDT_CTRL_CNT_2 +#define WWDT_CTRL_CNT3 WWDT_CTRL_CNT_3 +#define WWDT_CTRL_CNT4 WWDT_CTRL_CNT_4 +#define WWDT_CTRL_CNT5 WWDT_CTRL_CNT_5 +#define WWDT_CTRL_CNT6 WWDT_CTRL_CNT_6 + +#define WWDT_CTRL_WWDTEN_Pos (7U) +#define WWDT_CTRL_WWDTEN_Msk (0x1U << WWDT_CTRL_WWDTEN_Pos) /*!< 0x00000080 */ +#define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ + +/******************* Bit definition for WWDT_CFG register *******************/ +#define WWDT_CFG_WIN_Pos (0U) +#define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ +#define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ +#define WWDT_CFG_WIN_0 (0x01U << WWDT_CFG_WIN_Pos) /*!< 0x00000001 */ +#define WWDT_CFG_WIN_1 (0x02U << WWDT_CFG_WIN_Pos) /*!< 0x00000002 */ +#define WWDT_CFG_WIN_2 (0x04U << WWDT_CFG_WIN_Pos) /*!< 0x00000004 */ +#define WWDT_CFG_WIN_3 (0x08U << WWDT_CFG_WIN_Pos) /*!< 0x00000008 */ +#define WWDT_CFG_WIN_4 (0x10U << WWDT_CFG_WIN_Pos) /*!< 0x00000010 */ +#define WWDT_CFG_WIN_5 (0x20U << WWDT_CFG_WIN_Pos) /*!< 0x00000020 */ +#define WWDT_CFG_WIN_6 (0x40U << WWDT_CFG_WIN_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CFG_WIN0 WWDT_CFG_WIN_0 +#define WWDT_CFG_WIN1 WWDT_CFG_WIN_1 +#define WWDT_CFG_WIN2 WWDT_CFG_WIN_2 +#define WWDT_CFG_WIN3 WWDT_CFG_WIN_3 +#define WWDT_CFG_WIN4 WWDT_CFG_WIN_4 +#define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 +#define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 + +#define WWDT_CFG_DIV_Pos (7U) +#define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ +#define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ +#define WWDT_CFG_DIV_0 (0x1U << WWDT_CFG_DIV_Pos) /*!< 0x00000080 */ +#define WWDT_CFG_DIV_1 (0x2U << WWDT_CFG_DIV_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDT_CFG_DIV0 WWDT_CFG_DIV_0 +#define WWDT_CFG_DIV1 WWDT_CFG_DIV_1 + +#define WWDT_CFG_RLDIEN_Pos (9U) +#define WWDT_CFG_RLDIEN_Msk (0x1U << WWDT_CFG_RLDIEN_Pos) /*!< 0x00000200 */ +#define WWDT_CFG_RLDIEN WWDT_CFG_RLDIEN_Msk /*!< Reload counter interrupt */ + +/******************* Bit definition for WWDT_STS register *******************/ +#define WWDT_STS_RLDF_Pos (0U) +#define WWDT_STS_RLDF_Msk (0x1U << WWDT_STS_RLDF_Pos) /*!< 0x00000001 */ +#define WWDT_STS_RLDF WWDT_STS_RLDF_Msk /*!< Reload counter interrupt flag */ + +/******************************************************************************/ +/* */ +/* Watchdog timer (WDT) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WDT_CMD register ********************/ +#define WDT_CMD_CMD_Pos (0U) +#define WDT_CMD_CMD_Msk (0xFFFFU << WDT_CMD_CMD_Pos) /*!< 0x0000FFFF */ +#define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ + +/******************* Bit definition for WDT_DIV register ********************/ +#define WDT_DIV_DIV_Pos (0U) +#define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ +#define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ +#define WDT_DIV_DIV_0 (0x1U << WDT_DIV_DIV_Pos) /*!< 0x00000001 */ +#define WDT_DIV_DIV_1 (0x2U << WDT_DIV_DIV_Pos) /*!< 0x00000002 */ +#define WDT_DIV_DIV_2 (0x4U << WDT_DIV_DIV_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for WDT_RLD register ********************/ +#define WDT_RLD_RLD_Pos (0U) +#define WDT_RLD_RLD_Msk (0xFFFU << WDT_RLD_RLD_Pos) /*!< 0x00000FFF */ +#define WDT_RLD_RLD WDT_RLD_RLD_Msk /*!< Reload value */ + +/******************* Bit definition for WDT_STS register ********************/ +#define WDT_STS_DIVF_Pos (0U) +#define WDT_STS_DIVF_Msk (0x1U << WDT_STS_DIVF_Pos) /*!< 0x00000001 */ +#define WDT_STS_DIVF WDT_STS_DIVF_Msk /*!< Division value update complete flag */ +#define WDT_STS_RLDF_Pos (1U) +#define WDT_STS_RLDF_Msk (0x1U << WDT_STS_RLDF_Pos) /*!< 0x00000002 */ +#define WDT_STS_RLDF WDT_STS_RLDF_Msk /*!< Reload value update complete flag */ + +/******************************************************************************/ +/* */ +/* Enhanced real-time clock (ERTC) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for ERTC_TIME register *******************/ +#define ERTC_TIME_SU_Pos (0U) +#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_TIME_ST_Pos (4U) +#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_TIME_MU_Pos (8U) +#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TIME_MT_Pos (12U) +#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_TIME_HU_Pos (16U) +#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_TIME_HT_Pos (20U) +#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TIME_AMPM_Pos (22U) +#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_DATE register *******************/ +#define ERTC_DATE_DU_Pos (0U) +#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ +#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ +#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ +#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ +#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ + +#define ERTC_DATE_DT_Pos (4U) +#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ +#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ +#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ + +#define ERTC_DATE_MU_Pos (8U) +#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ +#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ +#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ +#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_DATE_MT_Pos (12U) +#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ +#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ + +#define ERTC_DATE_WK_Pos (13U) +#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ +#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ +#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ + +#define ERTC_DATE_YU_Pos (16U) +#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ +#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ +#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ +#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ +#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ +#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ + +#define ERTC_DATE_YT_Pos (20U) +#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ +#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ +#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ +#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ +#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ +#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ERTC_CTRL register *******************/ +#define ERTC_CTRL_WATCLK_Pos (0U) +#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ +#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ +#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ +#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ +#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ + +#define ERTC_CTRL_TSEDG_Pos (3U) +#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ +#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ +#define ERTC_CTRL_RCDEN_Pos (4U) +#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ +#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ +#define ERTC_CTRL_DREN_Pos (5U) +#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ +#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ +#define ERTC_CTRL_HM_Pos (6U) +#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ +#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ +#define ERTC_CTRL_CCALEN_Pos (7U) +#define ERTC_CTRL_CCALEN_Msk (0x1U << ERTC_CTRL_CCALEN_Pos) /*!< 0x00000080 */ +#define ERTC_CTRL_CCALEN ERTC_CTRL_CCALEN_Msk /*!< Coarse calibration enable */ +#define ERTC_CTRL_ALAEN_Pos (8U) +#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ +#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ +#define ERTC_CTRL_ALBEN_Pos (9U) +#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ +#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ +#define ERTC_CTRL_WATEN_Pos (10U) +#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ +#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ +#define ERTC_CTRL_TSEN_Pos (11U) +#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ +#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ +#define ERTC_CTRL_ALAIEN_Pos (12U) +#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ +#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ +#define ERTC_CTRL_ALBIEN_Pos (13U) +#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ +#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ +#define ERTC_CTRL_WATIEN_Pos (14U) +#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ +#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ +#define ERTC_CTRL_TSIEN_Pos (15U) +#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ +#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ +#define ERTC_CTRL_ADD1H_Pos (16U) +#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ +#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ +#define ERTC_CTRL_DEC1H_Pos (17U) +#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ +#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ +#define ERTC_CTRL_BPR_Pos (18U) +#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ +#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ +#define ERTC_CTRL_CALOSEL_Pos (19U) +#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ +#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ +#define ERTC_CTRL_OUTP_Pos (20U) +#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ +#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ + +#define ERTC_CTRL_OUTSEL_Pos (21U) +#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< WATCLK[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ +#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ + +#define ERTC_CTRL_CALOEN_Pos (23U) +#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ +#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ + +/******************* Bit definition for ERTC_STS register *******************/ +#define ERTC_STS_ALAWF_Pos (0U) +#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ +#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ +#define ERTC_STS_ALBWF_Pos (1U) +#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ +#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ +#define ERTC_STS_WATWF_Pos (2U) +#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ +#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ +#define ERTC_STS_TADJF_Pos (3U) +#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ +#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ +#define ERTC_STS_INITF_Pos (4U) +#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ +#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ +#define ERTC_STS_UPDF_Pos (5U) +#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ +#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ +#define ERTC_STS_IMF_Pos (6U) +#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ +#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ +#define ERTC_STS_IMEN_Pos (7U) +#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ +#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ +#define ERTC_STS_ALAF_Pos (8U) +#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ +#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ +#define ERTC_STS_ALBF_Pos (9U) +#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ +#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ +#define ERTC_STS_WATF_Pos (10U) +#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ +#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ +#define ERTC_STS_TSF_Pos (11U) +#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ +#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ +#define ERTC_STS_TSOF_Pos (12U) +#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ +#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ +#define ERTC_STS_TP1F_Pos (13U) +#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ +#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ +#define ERTC_STS_CALUPDF_Pos (16U) +#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ +#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ + +/******************* Bit definition for ERTC_DIV register *******************/ +#define ERTC_DIV_DIVB_Pos (0U) +#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ +#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ +#define ERTC_DIV_DIVA_Pos (16U) +#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ +#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ + +/******************* Bit definition for ERTC_WAT register *******************/ +#define ERTC_WAT_VAL_Pos (0U) +#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ +#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ + +/****************** Bit definition for ERTC_CCAL register *******************/ +#define ERTC_CCAL_CALVAL_Pos (0U) +#define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ +#define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ +#define ERTC_CCAL_CALVAL_0 (0x1U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000001 */ +#define ERTC_CCAL_CALVAL_1 (0x2U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000002 */ +#define ERTC_CCAL_CALVAL_2 (0x4U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000004 */ +#define ERTC_CCAL_CALVAL_3 (0x8U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000008 */ +#define ERTC_CCAL_CALVAL_4 (0x10U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000010 */ + +#define ERTC_CCAL_CALDIR_Pos (7U) +#define ERTC_CCAL_CALDIR_Msk (0x1U << ERTC_CCAL_CALDIR_Pos) /*!< 0x00000080 */ +#define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ + +/******************* Bit definition for ERTC_ALA register *******************/ +#define ERTC_ALA_SU_Pos (0U) +#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_ALA_ST_Pos (4U) +#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALA_MASK1_Pos (7U) +#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ + +#define ERTC_ALA_MU_Pos (8U) +#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_ALA_MT_Pos (12U) +#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALA_MASK2_Pos (15U) +#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ + +#define ERTC_ALA_HU_Pos (16U) +#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_ALA_HT_Pos (20U) +#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALA_AMPM_Pos (22U) +#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALA_MASK3_Pos (23U) +#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ + +#define ERTC_ALA_DU_Pos (24U) +#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ + +#define ERTC_ALA_DT_Pos (28U) +#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALA_WKSEL_Pos (30U) +#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALA_MASK4_Pos (31U) +#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_ALB register *******************/ +#define ERTC_ALB_SU_Pos (0U) +#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_ALB_ST_Pos (4U) +#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALB_MASK1_Pos (7U) +#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ + +#define ERTC_ALB_MU_Pos (8U) +#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_ALB_MT_Pos (12U) +#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALB_MASK2_Pos (15U) +#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ + +#define ERTC_ALB_HU_Pos (16U) +#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_ALB_HT_Pos (20U) +#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALB_AMPM_Pos (22U) +#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALB_MASK3_Pos (23U) +#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ + +#define ERTC_ALB_DU_Pos (24U) +#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ + +#define ERTC_ALB_DT_Pos (28U) +#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALB_WKSEL_Pos (30U) +#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALB_MASK4_Pos (31U) +#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_WP register ********************/ +#define ERTC_WP_CMD_Pos (0U) +#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ +#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ + +/******************* Bit definition for ERTC_SBS register *******************/ +#define ERTC_SBS_SBS_Pos (0U) +#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_TADJ register *******************/ +#define ERTC_TADJ_DECSBS_Pos (0U) +#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ +#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ +#define ERTC_TADJ_ADD1S_Pos (31U) +#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ +#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ + +/****************** Bit definition for ERTC_TSTM register *******************/ +#define ERTC_TSTM_SU_Pos (0U) +#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_TSTM_ST_Pos (4U) +#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_TSTM_MU_Pos (8U) +#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSTM_MT_Pos (12U) +#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_TSTM_HU_Pos (16U) +#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_TSTM_HT_Pos (20U) +#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TSTM_AMPM_Pos (22U) +#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_TSDT register *******************/ +#define ERTC_TSDT_DU_Pos (0U) +#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ +#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ +#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ +#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ +#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ + +#define ERTC_TSDT_DT_Pos (4U) +#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ +#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ +#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ + +#define ERTC_TSDT_MU_Pos (8U) +#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSDT_MT_Pos (12U) +#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ + +#define ERTC_TSDT_WK_Pos (13U) +#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ +#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ +#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for ERTC_TSSBS register ******************/ +#define ERTC_TSSBS_SBS_Pos (0U) +#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_SCAL register *******************/ +#define ERTC_SCAL_DEC_Pos (0U) +#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ +#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ +#define ERTC_SCAL_CAL16_Pos (13U) +#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ +#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ +#define ERTC_SCAL_CAL8_Pos (14U) +#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ +#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ +#define ERTC_SCAL_ADD_Pos (15U) +#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ +#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ + +/****************** Bit definition for ERTC_TAMP register *******************/ +#define ERTC_TAMP_TP1EN_Pos (0U) +#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ +#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ +#define ERTC_TAMP_TP1EDG_Pos (1U) +#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ +#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ +#define ERTC_TAMP_TPIEN_Pos (2U) +#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ +#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ +#define ERTC_TAMP_TPTSEN_Pos (7U) +#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ +#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ + +#define ERTC_TAMP_TPFREQ_Pos (8U) +#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ +#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ +#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ +#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ +#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ + +#define ERTC_TAMP_TPFLT_Pos (11U) +#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ +#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ +#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ +#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ + +#define ERTC_TAMP_TPPR_Pos (13U) +#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ +#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ +#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ +#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ + +#define ERTC_TAMP_TPPU_Pos (15U) +#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ +#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ +#define ERTC_TAMP_OUTTYPE_Pos (18U) +#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ +#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ + +/***************** Bit definition for ERTC_ALASBS register ******************/ +#define ERTC_ALASBS_SBS_Pos (0U) +#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ + +#define ERTC_ALASBS_SBSMSK_Pos (24U) +#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for ERTC_ALBSBS register ******************/ +#define ERTC_ALBSBS_SBS_Pos (0U) +#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ + +#define ERTC_ALBSBS_SBSMSK_Pos (24U) +#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ERTC_BPR1 register *******************/ +#define ERTC_BPR1_DT_Pos (0U) +#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ + +/****************** Bit definition for ERTC_BPR2 register *******************/ +#define ERTC_BPR2_DT_Pos (0U) +#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ + +/****************** Bit definition for ERTC_BPR3 register *******************/ +#define ERTC_BPR3_DT_Pos (0U) +#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ + +/****************** Bit definition for ERTC_BPR4 register *******************/ +#define ERTC_BPR4_DT_Pos (0U) +#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ + +/****************** Bit definition for ERTC_BPR5 register *******************/ +#define ERTC_BPR5_DT_Pos (0U) +#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ + +/****************** Bit definition for ERTC_BPR6 register *******************/ +#define ERTC_BPR6_DT_Pos (0U) +#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ + +/****************** Bit definition for ERTC_BPR7 register *******************/ +#define ERTC_BPR7_DT_Pos (0U) +#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ + +/****************** Bit definition for ERTC_BPR8 register *******************/ +#define ERTC_BPR8_DT_Pos (0U) +#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ + +/****************** Bit definition for ERTC_BPR9 register *******************/ +#define ERTC_BPR9_DT_Pos (0U) +#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ + +/****************** Bit definition for ERTC_BPR10 register ******************/ +#define ERTC_BPR10_DT_Pos (0U) +#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ + +/****************** Bit definition for ERTC_BPR11 register ******************/ +#define ERTC_BPR11_DT_Pos (0U) +#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ + +/****************** Bit definition for ERTC_BPR12 register ******************/ +#define ERTC_BPR12_DT_Pos (0U) +#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ + +/****************** Bit definition for ERTC_BPR13 register ******************/ +#define ERTC_BPR13_DT_Pos (0U) +#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ + +/****************** Bit definition for ERTC_BPR14 register ******************/ +#define ERTC_BPR14_DT_Pos (0U) +#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ + +/****************** Bit definition for ERTC_BPR15 register ******************/ +#define ERTC_BPR15_DT_Pos (0U) +#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ + +/****************** Bit definition for ERTC_BPR16 register ******************/ +#define ERTC_BPR16_DT_Pos (0U) +#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ + +/****************** Bit definition for ERTC_BPR17 register ******************/ +#define ERTC_BPR17_DT_Pos (0U) +#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ + +/****************** Bit definition for ERTC_BPR18 register ******************/ +#define ERTC_BPR18_DT_Pos (0U) +#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ + +/****************** Bit definition for ERTC_BPR19 register ******************/ +#define ERTC_BPR19_DT_Pos (0U) +#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ + +/****************** Bit definition for ERTC_BPR20 register ******************/ +#define ERTC_BPR20_DT_Pos (0U) +#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ + +/************************* Number of backup registers *************************/ +#define ERTC_BPR_NUMBER 0x000000014U + +/******************************************************************************/ +/* */ +/* Analog-to-digital converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ADC_STS register ********************/ +#define ADC_STS_VMOR_Pos (0U) +#define ADC_STS_VMOR_Msk (0x1U << ADC_STS_VMOR_Pos) /*!< 0x00000001 */ +#define ADC_STS_VMOR ADC_STS_VMOR_Msk /*!< Voltage monitoring out of range flag */ +#define ADC_STS_OCCC_Pos (1U) +#define ADC_STS_OCCC_Msk (0x1U << ADC_STS_OCCC_Pos) /*!< 0x00000002 */ +#define ADC_STS_OCCC ADC_STS_OCCC_Msk /*!< End of conversion flag */ +#define ADC_STS_PCCC_Pos (2U) +#define ADC_STS_PCCC_Msk (0x1U << ADC_STS_PCCC_Pos) /*!< 0x00000004 */ +#define ADC_STS_PCCC ADC_STS_PCCC_Msk /*!< Preempted channel end of conversion flag */ +#define ADC_STS_PCCS_Pos (3U) +#define ADC_STS_PCCS_Msk (0x1U << ADC_STS_PCCS_Pos) /*!< 0x00000008 */ +#define ADC_STS_PCCS ADC_STS_PCCS_Msk /*!< Preempted channel conversion start flag */ +#define ADC_STS_OCCS_Pos (4U) +#define ADC_STS_OCCS_Msk (0x1U << ADC_STS_OCCS_Pos) /*!< 0x00000010 */ +#define ADC_STS_OCCS ADC_STS_OCCS_Msk /*!< Ordinary channel conversion start flag */ + +/* Legacy defines */ +#define ADC_STS_OCCE (ADC_STS_OCCC) +#define ADC_STS_PCCE (ADC_STS_PCCC) + +/****************** Bit definition for ADC_CTRL1 register *******************/ +#define ADC_CTRL1_VMCSEL_Pos (0U) +#define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ +#define ADC_CTRL1_VMCSEL_0 (0x01U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTRL1_VMCSEL_1 (0x02U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTRL1_VMCSEL_2 (0x04U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL1_VMCSEL_3 (0x08U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTRL1_VMCSEL_4 (0x10U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000010 */ + +#define ADC_CTRL1_CCCIEN_Pos (5U) +#define ADC_CTRL1_CCCIEN_Msk (0x1U << ADC_CTRL1_CCCIEN_Pos) /*!< 0x00000020 */ +#define ADC_CTRL1_CCCIEN ADC_CTRL1_CCCIEN_Msk /*!< Channel conversion end interrupt enable */ +#define ADC_CTRL1_VMORIEN_Pos (6U) +#define ADC_CTRL1_VMORIEN_Msk (0x1U << ADC_CTRL1_VMORIEN_Pos) /*!< 0x00000040 */ +#define ADC_CTRL1_VMORIEN ADC_CTRL1_VMORIEN_Msk /*!< Voltage monitoring out of range interrupt enable */ +#define ADC_CTRL1_PCCCIEN_Pos (7U) +#define ADC_CTRL1_PCCCIEN_Msk (0x1U << ADC_CTRL1_PCCCIEN_Pos) /*!< 0x00000080 */ +#define ADC_CTRL1_PCCCIEN ADC_CTRL1_PCCCIEN_Msk /*!< Conversion end interrupt enable on Preempted channels */ +#define ADC_CTRL1_SQEN_Pos (8U) +#define ADC_CTRL1_SQEN_Msk (0x1U << ADC_CTRL1_SQEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL1_SQEN ADC_CTRL1_SQEN_Msk /*!< Sequence mode enable */ +#define ADC_CTRL1_VMSGEN_Pos (9U) +#define ADC_CTRL1_VMSGEN_Msk (0x1U << ADC_CTRL1_VMSGEN_Pos) /*!< 0x00000200 */ +#define ADC_CTRL1_VMSGEN ADC_CTRL1_VMSGEN_Msk /*!< Voltage monitoring enable on a single channel */ +#define ADC_CTRL1_PCAUTOEN_Pos (10U) +#define ADC_CTRL1_PCAUTOEN_Msk (0x1U << ADC_CTRL1_PCAUTOEN_Pos) /*!< 0x00000400 */ +#define ADC_CTRL1_PCAUTOEN ADC_CTRL1_PCAUTOEN_Msk /*!< Preempted group automatic conversion enable after ordinary group */ +#define ADC_CTRL1_OCPEN_Pos (11U) +#define ADC_CTRL1_OCPEN_Msk (0x1U << ADC_CTRL1_OCPEN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL1_OCPEN ADC_CTRL1_OCPEN_Msk /*!< Partitioned mode enable on ordinary channels */ +#define ADC_CTRL1_PCPEN_Pos (12U) +#define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ +#define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ + +#define ADC_CTRL1_OCPCNT_Pos (13U) +#define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ +#define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ +#define ADC_CTRL1_OCPCNT_0 (0x1U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00002000 */ +#define ADC_CTRL1_OCPCNT_1 (0x2U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00004000 */ +#define ADC_CTRL1_OCPCNT_2 (0x4U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00008000 */ + +#define ADC_CTRL1_PCVMEN_Pos (22U) +#define ADC_CTRL1_PCVMEN_Msk (0x1U << ADC_CTRL1_PCVMEN_Pos) /*!< 0x00400000 */ +#define ADC_CTRL1_PCVMEN ADC_CTRL1_PCVMEN_Msk /*!< Voltage monitoring enable on preempted channels */ +#define ADC_CTRL1_OCVMEN_Pos (23U) +#define ADC_CTRL1_OCVMEN_Msk (0x1U << ADC_CTRL1_OCVMEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL1_OCVMEN ADC_CTRL1_OCVMEN_Msk /*!< Voltage monitoring enable on ordinary channels */ + +/* Legacy defines */ +#define ADC_CTRL1_CCEIEN (ADC_CTRL1_CCCIEN) +#define ADC_CTRL1_PCCEIEN (ADC_CTRL1_PCCCIEN) + +/****************** Bit definition for ADC_CTRL2 register *******************/ +#define ADC_CTRL2_ADCEN_Pos (0U) +#define ADC_CTRL2_ADCEN_Msk (0x1U << ADC_CTRL2_ADCEN_Pos) /*!< 0x00000001 */ +#define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ +#define ADC_CTRL2_RPEN_Pos (1U) +#define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repition mode enable */ +#define ADC_CTRL2_ADCAL_Pos (2U) +#define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ +#define ADC_CTRL2_ADCALINIT_Pos (3U) +#define ADC_CTRL2_ADCALINIT_Msk (0x1U << ADC_CTRL2_ADCALINIT_Pos) /*!< 0x00000008 */ +#define ADC_CTRL2_ADCALINIT ADC_CTRL2_ADCALINIT_Msk /*!< Initialize A/D calibration */ +#define ADC_CTRL2_OCDMAEN_Pos (8U) +#define ADC_CTRL2_OCDMAEN_Msk (0x1U << ADC_CTRL2_OCDMAEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL2_OCDMAEN ADC_CTRL2_OCDMAEN_Msk /*!< DMA transfer enable of ordinary channels */ +#define ADC_CTRL2_DTALIGN_Pos (11U) +#define ADC_CTRL2_DTALIGN_Msk (0x1U << ADC_CTRL2_DTALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL2_DTALIGN ADC_CTRL2_DTALIGN_Msk /*!< Data alignment */ + +/*!< PCTESEL configuration */ +#define ADC_CTRL2_PCTESEL_Msk ((0x7U << 12) | (0x1U << 24)) /*!< 0x01007000 */ +#define ADC_CTRL2_PCTESEL ADC_CTRL2_PCTESEL_Msk /*!< PCTESEL[3:0] bits (Trigger event select for preempted channels conversion) */ +#define ADC_CTRL2_PCTESEL_0 (0x1U << 12) /*!< 0x00001000 */ +#define ADC_CTRL2_PCTESEL_1 (0x2U << 12) /*!< 0x00002000 */ +#define ADC_CTRL2_PCTESEL_2 (0x4U << 12) /*!< 0x00004000 */ +#define ADC_CTRL2_PCTESEL_3 (0x1U << 24) /*!< 0x01000000 */ + +#define ADC_CTRL2_PCTEN_Pos (15U) +#define ADC_CTRL2_PCTEN_Msk (0x1U << ADC_CTRL2_PCTEN_Pos) /*!< 0x00008000 */ +#define ADC_CTRL2_PCTEN ADC_CTRL2_PCTEN_Msk /*!< Trigger mode enable for preempted channels conversion */ + +/*!< OCTESEL configuration */ +#define ADC_CTRL2_OCTESEL_Msk ((0x7U << 17) | (0x1U << 25)) /*!< 0x020E0000 */ +#define ADC_CTRL2_OCTESEL ADC_CTRL2_OCTESEL_Msk /*!< OCTESEL[3:0] bits (Trigger event select for ordinary channels conversion) */ +#define ADC_CTRL2_OCTESEL_0 (0x1U << 17) /*!< 0x00020000 */ +#define ADC_CTRL2_OCTESEL_1 (0x2U << 17) /*!< 0x00040000 */ +#define ADC_CTRL2_OCTESEL_2 (0x4U << 17) /*!< 0x00080000 */ +#define ADC_CTRL2_OCTESEL_3 (0x1U << 25) /*!< 0x02000000 */ + +#define ADC_CTRL2_OCTEN_Pos (20U) +#define ADC_CTRL2_OCTEN_Msk (0x1U << ADC_CTRL2_OCTEN_Pos) /*!< 0x00100000 */ +#define ADC_CTRL2_OCTEN ADC_CTRL2_OCTEN_Msk /*!< Trigger mode enable for ordinary channels conversion */ +#define ADC_CTRL2_PCSWTRG_Pos (21U) +#define ADC_CTRL2_PCSWTRG_Msk (0x1U << ADC_CTRL2_PCSWTRG_Pos) /*!< 0x00200000 */ +#define ADC_CTRL2_PCSWTRG ADC_CTRL2_PCSWTRG_Msk /*!< Conversion of preempted channels triggered by software */ +#define ADC_CTRL2_OCSWTRG_Pos (22U) +#define ADC_CTRL2_OCSWTRG_Msk (0x1U << ADC_CTRL2_OCSWTRG_Pos) /*!< 0x00400000 */ +#define ADC_CTRL2_OCSWTRG ADC_CTRL2_OCSWTRG_Msk /*!< Conversion of ordinary channels triggered by software */ +#define ADC_CTRL2_ITSRVEN_Pos (23U) +#define ADC_CTRL2_ITSRVEN_Msk (0x1U << ADC_CTRL2_ITSRVEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ + +/******************* Bit definition for ADC_SPT1 register *******************/ +#define ADC_SPT1_CSPT10_Pos (0U) +#define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ +#define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ +#define ADC_SPT1_CSPT10_0 (0x1U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000001 */ +#define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ +#define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ + +#define ADC_SPT1_CSPT11_Pos (3U) +#define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ +#define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ +#define ADC_SPT1_CSPT11_0 (0x1U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000008 */ +#define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ +#define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ + +#define ADC_SPT1_CSPT12_Pos (6U) +#define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ +#define ADC_SPT1_CSPT12_0 (0x1U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000040 */ +#define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ +#define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ + +#define ADC_SPT1_CSPT13_Pos (9U) +#define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ +#define ADC_SPT1_CSPT13_0 (0x1U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000200 */ +#define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ +#define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ + +#define ADC_SPT1_CSPT14_Pos (12U) +#define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ +#define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ +#define ADC_SPT1_CSPT14_0 (0x1U << ADC_SPT1_CSPT14_Pos) /*!< 0x00001000 */ +#define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ +#define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ + +#define ADC_SPT1_CSPT15_Pos (15U) +#define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ +#define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ +#define ADC_SPT1_CSPT15_0 (0x1U << ADC_SPT1_CSPT15_Pos) /*!< 0x00008000 */ +#define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ +#define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ + +#define ADC_SPT1_CSPT16_Pos (18U) +#define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ +#define ADC_SPT1_CSPT16_0 (0x1U << ADC_SPT1_CSPT16_Pos) /*!< 0x00040000 */ +#define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ +#define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ + +#define ADC_SPT1_CSPT17_Pos (21U) +#define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ +#define ADC_SPT1_CSPT17_0 (0x1U << ADC_SPT1_CSPT17_Pos) /*!< 0x00200000 */ +#define ADC_SPT1_CSPT17_1 (0x2U << ADC_SPT1_CSPT17_Pos) /*!< 0x00400000 */ +#define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SPT2 register *******************/ +#define ADC_SPT2_CSPT0_Pos (0U) +#define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ +#define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ +#define ADC_SPT2_CSPT0_0 (0x1U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000001 */ +#define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ +#define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ + +#define ADC_SPT2_CSPT1_Pos (3U) +#define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ +#define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ +#define ADC_SPT2_CSPT1_0 (0x1U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000008 */ +#define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ +#define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ + +#define ADC_SPT2_CSPT2_Pos (6U) +#define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ +#define ADC_SPT2_CSPT2_0 (0x1U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000040 */ +#define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ +#define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ + +#define ADC_SPT2_CSPT3_Pos (9U) +#define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ +#define ADC_SPT2_CSPT3_0 (0x1U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000200 */ +#define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ +#define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ + +#define ADC_SPT2_CSPT4_Pos (12U) +#define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ +#define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ +#define ADC_SPT2_CSPT4_0 (0x1U << ADC_SPT2_CSPT4_Pos) /*!< 0x00001000 */ +#define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ +#define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ + +#define ADC_SPT2_CSPT5_Pos (15U) +#define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ +#define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ +#define ADC_SPT2_CSPT5_0 (0x1U << ADC_SPT2_CSPT5_Pos) /*!< 0x00008000 */ +#define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ +#define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ + +#define ADC_SPT2_CSPT6_Pos (18U) +#define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ +#define ADC_SPT2_CSPT6_0 (0x1U << ADC_SPT2_CSPT6_Pos) /*!< 0x00040000 */ +#define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ +#define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ + +#define ADC_SPT2_CSPT7_Pos (21U) +#define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ +#define ADC_SPT2_CSPT7_0 (0x1U << ADC_SPT2_CSPT7_Pos) /*!< 0x00200000 */ +#define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ +#define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ + +#define ADC_SPT2_CSPT8_Pos (24U) +#define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ +#define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ +#define ADC_SPT2_CSPT8_0 (0x1U << ADC_SPT2_CSPT8_Pos) /*!< 0x01000000 */ +#define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ +#define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ + +#define ADC_SPT2_CSPT9_Pos (27U) +#define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ +#define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ +#define ADC_SPT2_CSPT9_0 (0x1U << ADC_SPT2_CSPT9_Pos) /*!< 0x08000000 */ +#define ADC_SPT2_CSPT9_1 (0x2U << ADC_SPT2_CSPT9_Pos) /*!< 0x10000000 */ +#define ADC_SPT2_CSPT9_2 (0x4U << ADC_SPT2_CSPT9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_PCDTO1 register ******************/ +#define ADC_PCDTO1_PCDTO1_Pos (0U) +#define ADC_PCDTO1_PCDTO1_Msk (0xFFFU << ADC_PCDTO1_PCDTO1_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO1_PCDTO1 ADC_PCDTO1_PCDTO1_Msk /*!< Data offset for Preempted channel 1 */ + +/****************** Bit definition for ADC_PCDTO2 register ******************/ +#define ADC_PCDTO2_PCDTO2_Pos (0U) +#define ADC_PCDTO2_PCDTO2_Msk (0xFFFU << ADC_PCDTO2_PCDTO2_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO2_PCDTO2 ADC_PCDTO2_PCDTO2_Msk /*!< Data offset for Preempted channel 2 */ + +/****************** Bit definition for ADC_PCDTO3 register ******************/ +#define ADC_PCDTO3_PCDTO3_Pos (0U) +#define ADC_PCDTO3_PCDTO3_Msk (0xFFFU << ADC_PCDTO3_PCDTO3_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO3_PCDTO3 ADC_PCDTO3_PCDTO3_Msk /*!< Data offset for Preempted channel 3 */ + +/****************** Bit definition for ADC_PCDTO4 register ******************/ +#define ADC_PCDTO4_PCDTO4_Pos (0U) +#define ADC_PCDTO4_PCDTO4_Msk (0xFFFU << ADC_PCDTO4_PCDTO4_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO4_PCDTO4 ADC_PCDTO4_PCDTO4_Msk /*!< Data offset for Preempted channel 4 */ + +/******************* Bit definition for ADC_VMHB register ********************/ +#define ADC_VMHB_VMHB_Pos (0U) +#define ADC_VMHB_VMHB_Msk (0xFFFU << ADC_VMHB_VMHB_Pos) /*!< 0x00000FFF */ +#define ADC_VMHB_VMHB ADC_VMHB_VMHB_Msk /*!< Voltage monitoring high boundary */ + +/******************* Bit definition for ADC_VMLB register ********************/ +#define ADC_VMLB_VMLB_Pos (0U) +#define ADC_VMLB_VMLB_Msk (0xFFFU << ADC_VMLB_VMLB_Pos) /*!< 0x00000FFF */ +#define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ + +/******************* Bit definition for ADC_OSQ1 register *******************/ +#define ADC_OSQ1_OSN13_Pos (0U) +#define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ +#define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN13_0 (0x01U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000001 */ +#define ADC_OSQ1_OSN13_1 (0x02U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000002 */ +#define ADC_OSQ1_OSN13_2 (0x04U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000004 */ +#define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ +#define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ1_OSN14_Pos (5U) +#define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN14_0 (0x01U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000020 */ +#define ADC_OSQ1_OSN14_1 (0x02U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000040 */ +#define ADC_OSQ1_OSN14_2 (0x04U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000080 */ +#define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ +#define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ1_OSN15_Pos (10U) +#define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN15_0 (0x01U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000400 */ +#define ADC_OSQ1_OSN15_1 (0x02U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000800 */ +#define ADC_OSQ1_OSN15_2 (0x04U << ADC_OSQ1_OSN15_Pos) /*!< 0x00001000 */ +#define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ +#define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ1_OSN16_Pos (15U) +#define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN16_0 (0x01U << ADC_OSQ1_OSN16_Pos) /*!< 0x00008000 */ +#define ADC_OSQ1_OSN16_1 (0x02U << ADC_OSQ1_OSN16_Pos) /*!< 0x00010000 */ +#define ADC_OSQ1_OSN16_2 (0x04U << ADC_OSQ1_OSN16_Pos) /*!< 0x00020000 */ +#define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ +#define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ1_OCLEN_Pos (20U) +#define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ +#define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ +#define ADC_OSQ1_OCLEN_0 (0x1U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00100000 */ +#define ADC_OSQ1_OCLEN_1 (0x2U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00200000 */ +#define ADC_OSQ1_OCLEN_2 (0x4U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00400000 */ +#define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_OSQ2 register *******************/ +#define ADC_OSQ2_OSN7_Pos (0U) +#define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ +#define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN7_0 (0x01U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000001 */ +#define ADC_OSQ2_OSN7_1 (0x02U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000002 */ +#define ADC_OSQ2_OSN7_2 (0x04U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000004 */ +#define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ +#define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ2_OSN8_Pos (5U) +#define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN8_0 (0x01U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000020 */ +#define ADC_OSQ2_OSN8_1 (0x02U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000040 */ +#define ADC_OSQ2_OSN8_2 (0x04U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000080 */ +#define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ +#define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ2_OSN9_Pos (10U) +#define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN9_0 (0x01U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000400 */ +#define ADC_OSQ2_OSN9_1 (0x02U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000800 */ +#define ADC_OSQ2_OSN9_2 (0x04U << ADC_OSQ2_OSN9_Pos) /*!< 0x00001000 */ +#define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ +#define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ2_OSN10_Pos (15U) +#define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN10_0 (0x01U << ADC_OSQ2_OSN10_Pos) /*!< 0x00008000 */ +#define ADC_OSQ2_OSN10_1 (0x02U << ADC_OSQ2_OSN10_Pos) /*!< 0x00010000 */ +#define ADC_OSQ2_OSN10_2 (0x04U << ADC_OSQ2_OSN10_Pos) /*!< 0x00020000 */ +#define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ +#define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ2_OSN11_Pos (20U) +#define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN11_0 (0x01U << ADC_OSQ2_OSN11_Pos) /*!< 0x00100000 */ +#define ADC_OSQ2_OSN11_1 (0x02U << ADC_OSQ2_OSN11_Pos) /*!< 0x00200000 */ +#define ADC_OSQ2_OSN11_2 (0x04U << ADC_OSQ2_OSN11_Pos) /*!< 0x00400000 */ +#define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ +#define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ + +#define ADC_OSQ2_OSN12_Pos (25U) +#define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN12_0 (0x01U << ADC_OSQ2_OSN12_Pos) /*!< 0x02000000 */ +#define ADC_OSQ2_OSN12_1 (0x02U << ADC_OSQ2_OSN12_Pos) /*!< 0x04000000 */ +#define ADC_OSQ2_OSN12_2 (0x04U << ADC_OSQ2_OSN12_Pos) /*!< 0x08000000 */ +#define ADC_OSQ2_OSN12_3 (0x08U << ADC_OSQ2_OSN12_Pos) /*!< 0x10000000 */ +#define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_OSQ3 register *******************/ +#define ADC_OSQ3_OSN1_Pos (0U) +#define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ +#define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN1_0 (0x01U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000001 */ +#define ADC_OSQ3_OSN1_1 (0x02U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000002 */ +#define ADC_OSQ3_OSN1_2 (0x04U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000004 */ +#define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ +#define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ3_OSN2_Pos (5U) +#define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN2_0 (0x01U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000020 */ +#define ADC_OSQ3_OSN2_1 (0x02U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000040 */ +#define ADC_OSQ3_OSN2_2 (0x04U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000080 */ +#define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ +#define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ3_OSN3_Pos (10U) +#define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN3_0 (0x01U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000400 */ +#define ADC_OSQ3_OSN3_1 (0x02U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000800 */ +#define ADC_OSQ3_OSN3_2 (0x04U << ADC_OSQ3_OSN3_Pos) /*!< 0x00001000 */ +#define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ +#define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ3_OSN4_Pos (15U) +#define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN4_0 (0x01U << ADC_OSQ3_OSN4_Pos) /*!< 0x00008000 */ +#define ADC_OSQ3_OSN4_1 (0x02U << ADC_OSQ3_OSN4_Pos) /*!< 0x00010000 */ +#define ADC_OSQ3_OSN4_2 (0x04U << ADC_OSQ3_OSN4_Pos) /*!< 0x00020000 */ +#define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ +#define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ3_OSN5_Pos (20U) +#define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN5_0 (0x01U << ADC_OSQ3_OSN5_Pos) /*!< 0x00100000 */ +#define ADC_OSQ3_OSN5_1 (0x02U << ADC_OSQ3_OSN5_Pos) /*!< 0x00200000 */ +#define ADC_OSQ3_OSN5_2 (0x04U << ADC_OSQ3_OSN5_Pos) /*!< 0x00400000 */ +#define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ +#define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ + +#define ADC_OSQ3_OSN6_Pos (25U) +#define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN6_0 (0x01U << ADC_OSQ3_OSN6_Pos) /*!< 0x02000000 */ +#define ADC_OSQ3_OSN6_1 (0x02U << ADC_OSQ3_OSN6_Pos) /*!< 0x04000000 */ +#define ADC_OSQ3_OSN6_2 (0x04U << ADC_OSQ3_OSN6_Pos) /*!< 0x08000000 */ +#define ADC_OSQ3_OSN6_3 (0x08U << ADC_OSQ3_OSN6_Pos) /*!< 0x10000000 */ +#define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_PSQ register ********************/ +#define ADC_PSQ_PSN1_Pos (0U) +#define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ +#define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ +#define ADC_PSQ_PSN1_0 (0x01U << ADC_PSQ_PSN1_Pos) /*!< 0x00000001 */ +#define ADC_PSQ_PSN1_1 (0x02U << ADC_PSQ_PSN1_Pos) /*!< 0x00000002 */ +#define ADC_PSQ_PSN1_2 (0x04U << ADC_PSQ_PSN1_Pos) /*!< 0x00000004 */ +#define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ +#define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ + +#define ADC_PSQ_PSN2_Pos (5U) +#define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ +#define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ +#define ADC_PSQ_PSN2_0 (0x01U << ADC_PSQ_PSN2_Pos) /*!< 0x00000020 */ +#define ADC_PSQ_PSN2_1 (0x02U << ADC_PSQ_PSN2_Pos) /*!< 0x00000040 */ +#define ADC_PSQ_PSN2_2 (0x04U << ADC_PSQ_PSN2_Pos) /*!< 0x00000080 */ +#define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ +#define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ + +#define ADC_PSQ_PSN3_Pos (10U) +#define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ +#define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ +#define ADC_PSQ_PSN3_0 (0x01U << ADC_PSQ_PSN3_Pos) /*!< 0x00000400 */ +#define ADC_PSQ_PSN3_1 (0x02U << ADC_PSQ_PSN3_Pos) /*!< 0x00000800 */ +#define ADC_PSQ_PSN3_2 (0x04U << ADC_PSQ_PSN3_Pos) /*!< 0x00001000 */ +#define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ +#define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ + +#define ADC_PSQ_PSN4_Pos (15U) +#define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ +#define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ +#define ADC_PSQ_PSN4_0 (0x01U << ADC_PSQ_PSN4_Pos) /*!< 0x00008000 */ +#define ADC_PSQ_PSN4_1 (0x02U << ADC_PSQ_PSN4_Pos) /*!< 0x00010000 */ +#define ADC_PSQ_PSN4_2 (0x04U << ADC_PSQ_PSN4_Pos) /*!< 0x00020000 */ +#define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ +#define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ + +#define ADC_PSQ_PCLEN_Pos (20U) +#define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ +#define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ +#define ADC_PSQ_PCLEN_0 (0x1U << ADC_PSQ_PCLEN_Pos) /*!< 0x00100000 */ +#define ADC_PSQ_PCLEN_1 (0x2U << ADC_PSQ_PCLEN_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_PDT1 register *******************/ +#define ADC_PDT1_PDT1_Pos (0U) +#define ADC_PDT1_PDT1_Msk (0xFFFFU << ADC_PDT1_PDT1_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT1_PDT1 ADC_PDT1_PDT1_Msk /*!< Conversion data from preempted channel 1 */ + +/******************* Bit definition for ADC_PDT2 register *******************/ +#define ADC_PDT2_PDT2_Pos (0U) +#define ADC_PDT2_PDT2_Msk (0xFFFFU << ADC_PDT2_PDT2_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT2_PDT2 ADC_PDT2_PDT2_Msk /*!< Conversion data from preempted channel 2 */ + +/******************* Bit definition for ADC_PDT3 register *******************/ +#define ADC_PDT3_PDT3_Pos (0U) +#define ADC_PDT3_PDT3_Msk (0xFFFFU << ADC_PDT3_PDT3_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT3_PDT3 ADC_PDT3_PDT3_Msk /*!< Conversion data from preempted channel 3 */ + +/******************* Bit definition for ADC_PDT4 register *******************/ +#define ADC_PDT4_PDT4_Pos (0U) +#define ADC_PDT4_PDT4_Msk (0xFFFFU << ADC_PDT4_PDT4_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT4_PDT4 ADC_PDT4_PDT4_Msk /*!< Conversion data from preempted channel 4 */ + +/******************* Bit definition for ADC_ODT register ********************/ +#define ADC_ODT_ODT_Pos (0U) +#define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ +#define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ +#define ADC_ODT_ADC2ODT_Pos (16U) +#define ADC_ODT_ADC2ODT_Msk (0xFFFFU << ADC_ODT_ADC2ODT_Pos) /*!< 0xFFFF0000 */ +#define ADC_ODT_ADC2ODT ADC_ODT_ADC2ODT_Msk /*!< ADC2 conversion data of ordinary channel */ + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN) */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/****************** Bit definition for CAN_MCTRL register *******************/ +#define CAN_MCTRL_FZEN_Pos (0U) +#define CAN_MCTRL_FZEN_Msk (0x1U << CAN_MCTRL_FZEN_Pos) /*!< 0x00000001 */ +#define CAN_MCTRL_FZEN CAN_MCTRL_FZEN_Msk /*!< Freeze mode enable */ +#define CAN_MCTRL_DZEN_Pos (1U) +#define CAN_MCTRL_DZEN_Msk (0x1U << CAN_MCTRL_DZEN_Pos) /*!< 0x00000002 */ +#define CAN_MCTRL_DZEN CAN_MCTRL_DZEN_Msk /*!< Doze mode enable */ +#define CAN_MCTRL_MMSSR_Pos (2U) +#define CAN_MCTRL_MMSSR_Msk (0x1U << CAN_MCTRL_MMSSR_Pos) /*!< 0x00000004 */ +#define CAN_MCTRL_MMSSR CAN_MCTRL_MMSSR_Msk /*!< Multiple message transmit sequence rule */ +#define CAN_MCTRL_MDRSEL_Pos (3U) +#define CAN_MCTRL_MDRSEL_Msk (0x1U << CAN_MCTRL_MDRSEL_Pos) /*!< 0x00000008 */ +#define CAN_MCTRL_MDRSEL CAN_MCTRL_MDRSEL_Msk /*!< Message discard rule select when overflow */ +#define CAN_MCTRL_PRSFEN_Pos (4U) +#define CAN_MCTRL_PRSFEN_Msk (0x1U << CAN_MCTRL_PRSFEN_Pos) /*!< 0x00000010 */ +#define CAN_MCTRL_PRSFEN CAN_MCTRL_PRSFEN_Msk /*!< Prohibit retransmission enable when sending fails enable */ +#define CAN_MCTRL_AEDEN_Pos (5U) +#define CAN_MCTRL_AEDEN_Msk (0x1U << CAN_MCTRL_AEDEN_Pos) /*!< 0x00000020 */ +#define CAN_MCTRL_AEDEN CAN_MCTRL_AEDEN_Msk /*!< Automatic exit doze mode enable */ +#define CAN_MCTRL_AEBOEN_Pos (6U) +#define CAN_MCTRL_AEBOEN_Msk (0x1U << CAN_MCTRL_AEBOEN_Pos) /*!< 0x00000040 */ +#define CAN_MCTRL_AEBOEN CAN_MCTRL_AEBOEN_Msk /*!< Automatic exit bus-off enable */ +#define CAN_MCTRL_TTCEN_Pos (7U) +#define CAN_MCTRL_TTCEN_Msk (0x1U << CAN_MCTRL_TTCEN_Pos) /*!< 0x00000080 */ +#define CAN_MCTRL_TTCEN CAN_MCTRL_TTCEN_Msk /*!< Time triggered communication mode enable */ +#define CAN_MCTRL_SPRST_Pos (15U) +#define CAN_MCTRL_SPRST_Msk (0x1U << CAN_MCTRL_SPRST_Pos) /*!< 0x00008000 */ +#define CAN_MCTRL_SPRST CAN_MCTRL_SPRST_Msk /*!< Software partial reset */ +#define CAN_MCTRL_PTD_Pos (16U) +#define CAN_MCTRL_PTD_Msk (0x1U << CAN_MCTRL_PTD_Pos) /*!< 0x00010000 */ +#define CAN_MCTRL_PTD CAN_MCTRL_PTD_Msk /*!< Prohibit trans when debug */ + +/******************* Bit definition for CAN_MSTS register *******************/ +#define CAN_MSTS_FZC_Pos (0U) +#define CAN_MSTS_FZC_Msk (0x1U << CAN_MSTS_FZC_Pos) /*!< 0x00000001 */ +#define CAN_MSTS_FZC CAN_MSTS_FZC_Msk /*!< Freeze mode confirm */ +#define CAN_MSTS_DZC_Pos (1U) +#define CAN_MSTS_DZC_Msk (0x1U << CAN_MSTS_DZC_Pos) /*!< 0x00000002 */ +#define CAN_MSTS_DZC CAN_MSTS_DZC_Msk /*!< Doze mode acknowledge */ +#define CAN_MSTS_EOIF_Pos (2U) +#define CAN_MSTS_EOIF_Msk (0x1U << CAN_MSTS_EOIF_Pos) /*!< 0x00000004 */ +#define CAN_MSTS_EOIF CAN_MSTS_EOIF_Msk /*!< Error occur interrupt flag */ +#define CAN_MSTS_QDZIF_Pos (3U) +#define CAN_MSTS_QDZIF_Msk (0x1U << CAN_MSTS_QDZIF_Pos) /*!< 0x00000008 */ +#define CAN_MSTS_QDZIF CAN_MSTS_QDZIF_Msk /*!< Exit doze mode interrupt flag */ +#define CAN_MSTS_EDZIF_Pos (4U) +#define CAN_MSTS_EDZIF_Msk (0x1U << CAN_MSTS_EDZIF_Pos) /*!< 0x00000010 */ +#define CAN_MSTS_EDZIF CAN_MSTS_EDZIF_Msk /*!< Enter doze mode interrupt flag */ +#define CAN_MSTS_CUSS_Pos (8U) +#define CAN_MSTS_CUSS_Msk (0x1U << CAN_MSTS_CUSS_Pos) /*!< 0x00000100 */ +#define CAN_MSTS_CUSS CAN_MSTS_CUSS_Msk /*!< Current transmit status */ +#define CAN_MSTS_CURS_Pos (9U) +#define CAN_MSTS_CURS_Msk (0x1U << CAN_MSTS_CURS_Pos) /*!< 0x00000200 */ +#define CAN_MSTS_CURS CAN_MSTS_CURS_Msk /*!< Current receive status */ +#define CAN_MSTS_LSAMPRX_Pos (10U) +#define CAN_MSTS_LSAMPRX_Msk (0x1U << CAN_MSTS_LSAMPRX_Pos) /*!< 0x00000400 */ +#define CAN_MSTS_LSAMPRX CAN_MSTS_LSAMPRX_Msk /*!< Last sample level on RX pin */ +#define CAN_MSTS_REALRX_Pos (11U) +#define CAN_MSTS_REALRX_Msk (0x1U << CAN_MSTS_REALRX_Pos) /*!< 0x00000800 */ +#define CAN_MSTS_REALRX CAN_MSTS_REALRX_Msk /*!< Real time level on RX pin */ + +/******************* Bit definition for CAN_TSTS register *******************/ +#define CAN_TSTS_TM0TCF_Pos (0U) +#define CAN_TSTS_TM0TCF_Msk (0x1U << CAN_TSTS_TM0TCF_Pos) /*!< 0x00000001 */ +#define CAN_TSTS_TM0TCF CAN_TSTS_TM0TCF_Msk /*!< Transmit mailbox 0 transmission completed flag */ +#define CAN_TSTS_TM0TSF_Pos (1U) +#define CAN_TSTS_TM0TSF_Msk (0x1U << CAN_TSTS_TM0TSF_Pos) /*!< 0x00000002 */ +#define CAN_TSTS_TM0TSF CAN_TSTS_TM0TSF_Msk /*!< Transmit mailbox 0 transmission success flag */ +#define CAN_TSTS_TM0ALF_Pos (2U) +#define CAN_TSTS_TM0ALF_Msk (0x1U << CAN_TSTS_TM0ALF_Pos) /*!< 0x00000004 */ +#define CAN_TSTS_TM0ALF CAN_TSTS_TM0ALF_Msk /*!< Transmit mailbox 0 arbitration lost flag */ +#define CAN_TSTS_TM0TEF_Pos (3U) +#define CAN_TSTS_TM0TEF_Msk (0x1U << CAN_TSTS_TM0TEF_Pos) /*!< 0x00000008 */ +#define CAN_TSTS_TM0TEF CAN_TSTS_TM0TEF_Msk /*!< Transmit mailbox 0 transmission error flag */ +#define CAN_TSTS_TM0CT_Pos (7U) +#define CAN_TSTS_TM0CT_Msk (0x1U << CAN_TSTS_TM0CT_Pos) /*!< 0x00000080 */ +#define CAN_TSTS_TM0CT CAN_TSTS_TM0CT_Msk /*!< Transmit mailbox 0 cancel transmit */ +#define CAN_TSTS_TM1TCF_Pos (8U) +#define CAN_TSTS_TM1TCF_Msk (0x1U << CAN_TSTS_TM1TCF_Pos) /*!< 0x00000100 */ +#define CAN_TSTS_TM1TCF CAN_TSTS_TM1TCF_Msk /*!< Transmit mailbox 1 transmission completed flag */ +#define CAN_TSTS_TM1TSF_Pos (9U) +#define CAN_TSTS_TM1TSF_Msk (0x1U << CAN_TSTS_TM1TSF_Pos) /*!< 0x00000200 */ +#define CAN_TSTS_TM1TSF CAN_TSTS_TM1TSF_Msk /*!< Transmit mailbox 1 transmission success flag */ +#define CAN_TSTS_TM1ALF_Pos (10U) +#define CAN_TSTS_TM1ALF_Msk (0x1U << CAN_TSTS_TM1ALF_Pos) /*!< 0x00000400 */ +#define CAN_TSTS_TM1ALF CAN_TSTS_TM1ALF_Msk /*!< Transmit mailbox 1 arbitration lost flag */ +#define CAN_TSTS_TM1TEF_Pos (11U) +#define CAN_TSTS_TM1TEF_Msk (0x1U << CAN_TSTS_TM1TEF_Pos) /*!< 0x00000800 */ +#define CAN_TSTS_TM1TEF CAN_TSTS_TM1TEF_Msk /*!< Transmit mailbox 1 transmission error flag */ +#define CAN_TSTS_TM1CT_Pos (15U) +#define CAN_TSTS_TM1CT_Msk (0x1U << CAN_TSTS_TM1CT_Pos) /*!< 0x00008000 */ +#define CAN_TSTS_TM1CT CAN_TSTS_TM1CT_Msk /*!< Transmit mailbox 1 cancel transmit */ +#define CAN_TSTS_TM2TCF_Pos (16U) +#define CAN_TSTS_TM2TCF_Msk (0x1U << CAN_TSTS_TM2TCF_Pos) /*!< 0x00010000 */ +#define CAN_TSTS_TM2TCF CAN_TSTS_TM2TCF_Msk /*!< Transmit mailbox 2 transmission completed flag */ +#define CAN_TSTS_TM2TSF_Pos (17U) +#define CAN_TSTS_TM2TSF_Msk (0x1U << CAN_TSTS_TM2TSF_Pos) /*!< 0x00020000 */ +#define CAN_TSTS_TM2TSF CAN_TSTS_TM2TSF_Msk /*!< Transmit mailbox 2 transmission success flag */ +#define CAN_TSTS_TM2ALF_Pos (18U) +#define CAN_TSTS_TM2ALF_Msk (0x1U << CAN_TSTS_TM2ALF_Pos) /*!< 0x00040000 */ +#define CAN_TSTS_TM2ALF CAN_TSTS_TM2ALF_Msk /*!< Transmit mailbox 2 arbitration lost flag */ +#define CAN_TSTS_TM2TEF_Pos (19U) +#define CAN_TSTS_TM2TEF_Msk (0x1U << CAN_TSTS_TM2TEF_Pos) /*!< 0x00080000 */ +#define CAN_TSTS_TM2TEF CAN_TSTS_TM2TEF_Msk /*!< Transmit mailbox 2 transmission error flag */ +#define CAN_TSTS_TM2CT_Pos (23U) +#define CAN_TSTS_TM2CT_Msk (0x1U << CAN_TSTS_TM2CT_Pos) /*!< 0x00800000 */ +#define CAN_TSTS_TM2CT CAN_TSTS_TM2CT_Msk /*!< Transmit mailbox 2 cancel transmit */ +#define CAN_TSTS_TMNR_Pos (24U) +#define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ +#define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ + +#define CAN_TSTS_TMEF_Pos (26U) +#define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ +#define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ +#define CAN_TSTS_TM0EF_Pos (26U) +#define CAN_TSTS_TM0EF_Msk (0x1U << CAN_TSTS_TM0EF_Pos) /*!< 0x04000000 */ +#define CAN_TSTS_TM0EF CAN_TSTS_TM0EF_Msk /*!< Transmit mailbox 0 empty flag */ +#define CAN_TSTS_TM1EF_Pos (27U) +#define CAN_TSTS_TM1EF_Msk (0x1U << CAN_TSTS_TM1EF_Pos) /*!< 0x08000000 */ +#define CAN_TSTS_TM1EF CAN_TSTS_TM1EF_Msk /*!< Transmit mailbox 1 empty flag */ +#define CAN_TSTS_TM2EF_Pos (28U) +#define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ +#define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ + +#define CAN_TSTS_TMLPF_Pos (29U) +#define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ +#define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ +#define CAN_TSTS_TM0LPF_Pos (29U) +#define CAN_TSTS_TM0LPF_Msk (0x1U << CAN_TSTS_TM0LPF_Pos) /*!< 0x20000000 */ +#define CAN_TSTS_TM0LPF CAN_TSTS_TM0LPF_Msk /*!< Transmit mailbox 0 lowest priority flag */ +#define CAN_TSTS_TM1LPF_Pos (30U) +#define CAN_TSTS_TM1LPF_Msk (0x1U << CAN_TSTS_TM1LPF_Pos) /*!< 0x40000000 */ +#define CAN_TSTS_TM1LPF CAN_TSTS_TM1LPF_Msk /*!< Transmit mailbox 1 lowest priority flag */ +#define CAN_TSTS_TM2LPF_Pos (31U) +#define CAN_TSTS_TM2LPF_Msk (0x1U << CAN_TSTS_TM2LPF_Pos) /*!< 0x80000000 */ +#define CAN_TSTS_TM2LPF CAN_TSTS_TM2LPF_Msk /*!< Transmit mailbox 2 lowest priority flag */ + +/******************* Bit definition for CAN_RF0 register ********************/ +#define CAN_RF0_RF0MN_Pos (0U) +#define CAN_RF0_RF0MN_Msk (0x3U << CAN_RF0_RF0MN_Pos) /*!< 0x00000003 */ +#define CAN_RF0_RF0MN CAN_RF0_RF0MN_Msk /*!< Receive FIFO 0 message num */ +#define CAN_RF0_RF0FF_Pos (3U) +#define CAN_RF0_RF0FF_Msk (0x1U << CAN_RF0_RF0FF_Pos) /*!< 0x00000008 */ +#define CAN_RF0_RF0FF CAN_RF0_RF0FF_Msk /*!< Receive FIFO 0 full flag */ +#define CAN_RF0_RF0OF_Pos (4U) +#define CAN_RF0_RF0OF_Msk (0x1U << CAN_RF0_RF0OF_Pos) /*!< 0x00000010 */ +#define CAN_RF0_RF0OF CAN_RF0_RF0OF_Msk /*!< Receive FIFO 0 overflow flag */ +#define CAN_RF0_RF0R_Pos (5U) +#define CAN_RF0_RF0R_Msk (0x1U << CAN_RF0_RF0R_Pos) /*!< 0x00000020 */ +#define CAN_RF0_RF0R CAN_RF0_RF0R_Msk /*!< Receive FIFO 0 release */ + +/******************* Bit definition for CAN_RF1 register ********************/ +#define CAN_RF1_RF1MN_Pos (0U) +#define CAN_RF1_RF1MN_Msk (0x3U << CAN_RF1_RF1MN_Pos) /*!< 0x00000003 */ +#define CAN_RF1_RF1MN CAN_RF1_RF1MN_Msk /*!< Receive FIFO 1 message num */ +#define CAN_RF1_RF1FF_Pos (3U) +#define CAN_RF1_RF1FF_Msk (0x1U << CAN_RF1_RF1FF_Pos) /*!< 0x00000008 */ +#define CAN_RF1_RF1FF CAN_RF1_RF1FF_Msk /*!< Receive FIFO 1 full flag */ +#define CAN_RF1_RF1OF_Pos (4U) +#define CAN_RF1_RF1OF_Msk (0x1U << CAN_RF1_RF1OF_Pos) /*!< 0x00000010 */ +#define CAN_RF1_RF1OF CAN_RF1_RF1OF_Msk /*!< Receive FIFO 1 overflow flag */ +#define CAN_RF1_RF1R_Pos (5U) +#define CAN_RF1_RF1R_Msk (0x1U << CAN_RF1_RF1R_Pos) /*!< 0x00000020 */ +#define CAN_RF1_RF1R CAN_RF1_RF1R_Msk /*!< Receive FIFO 1 release */ + +/****************** Bit definition for CAN_INTEN register *******************/ +#define CAN_INTEN_TCIEN_Pos (0U) +#define CAN_INTEN_TCIEN_Msk (0x1U << CAN_INTEN_TCIEN_Pos) /*!< 0x00000001 */ +#define CAN_INTEN_TCIEN CAN_INTEN_TCIEN_Msk /*!< Transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RF0MIEN_Pos (1U) +#define CAN_INTEN_RF0MIEN_Msk (0x1U << CAN_INTEN_RF0MIEN_Pos) /*!< 0x00000002 */ +#define CAN_INTEN_RF0MIEN CAN_INTEN_RF0MIEN_Msk /*!< FIFO 0 receive message interrupt enable */ +#define CAN_INTEN_RF0FIEN_Pos (2U) +#define CAN_INTEN_RF0FIEN_Msk (0x1U << CAN_INTEN_RF0FIEN_Pos) /*!< 0x00000004 */ +#define CAN_INTEN_RF0FIEN CAN_INTEN_RF0FIEN_Msk /*!< Receive FIFO 0 full interrupt enable */ +#define CAN_INTEN_RF0OIEN_Pos (3U) +#define CAN_INTEN_RF0OIEN_Msk (0x1U << CAN_INTEN_RF0OIEN_Pos) /*!< 0x00000008 */ +#define CAN_INTEN_RF0OIEN CAN_INTEN_RF0OIEN_Msk /*!< Receive FIFO 0 overflow interrupt enable */ +#define CAN_INTEN_RF1MIEN_Pos (4U) +#define CAN_INTEN_RF1MIEN_Msk (0x1U << CAN_INTEN_RF1MIEN_Pos) /*!< 0x00000010 */ +#define CAN_INTEN_RF1MIEN CAN_INTEN_RF1MIEN_Msk /*!< FIFO 1 receive message interrupt enable */ +#define CAN_INTEN_RF1FIEN_Pos (5U) +#define CAN_INTEN_RF1FIEN_Msk (0x1U << CAN_INTEN_RF1FIEN_Pos) /*!< 0x00000020 */ +#define CAN_INTEN_RF1FIEN CAN_INTEN_RF1FIEN_Msk /*!< Receive FIFO 1 full interrupt enable */ +#define CAN_INTEN_RF1OIEN_Pos (6U) +#define CAN_INTEN_RF1OIEN_Msk (0x1U << CAN_INTEN_RF1OIEN_Pos) /*!< 0x00000040 */ +#define CAN_INTEN_RF1OIEN CAN_INTEN_RF1OIEN_Msk /*!< Receive FIFO 1 overflow interrupt enable */ +#define CAN_INTEN_EAIEN_Pos (8U) +#define CAN_INTEN_EAIEN_Msk (0x1U << CAN_INTEN_EAIEN_Pos) /*!< 0x00000100 */ +#define CAN_INTEN_EAIEN CAN_INTEN_EAIEN_Msk /*!< Error active interrupt enable */ +#define CAN_INTEN_EPIEN_Pos (9U) +#define CAN_INTEN_EPIEN_Msk (0x1U << CAN_INTEN_EPIEN_Pos) /*!< 0x00000200 */ +#define CAN_INTEN_EPIEN CAN_INTEN_EPIEN_Msk /*!< Error passive interrupt enable */ +#define CAN_INTEN_BOIEN_Pos (10U) +#define CAN_INTEN_BOIEN_Msk (0x1U << CAN_INTEN_BOIEN_Pos) /*!< 0x00000400 */ +#define CAN_INTEN_BOIEN CAN_INTEN_BOIEN_Msk /*!< Bus-off interrupt enable */ +#define CAN_INTEN_ETRIEN_Pos (11U) +#define CAN_INTEN_ETRIEN_Msk (0x1U << CAN_INTEN_ETRIEN_Pos) /*!< 0x00000800 */ +#define CAN_INTEN_ETRIEN CAN_INTEN_ETRIEN_Msk /*!< Error type record interrupt enable */ +#define CAN_INTEN_EOIEN_Pos (15U) +#define CAN_INTEN_EOIEN_Msk (0x1U << CAN_INTEN_EOIEN_Pos) /*!< 0x00008000 */ +#define CAN_INTEN_EOIEN CAN_INTEN_EOIEN_Msk /*!< Error occur interrupt enable */ +#define CAN_INTEN_QDZIEN_Pos (16U) +#define CAN_INTEN_QDZIEN_Msk (0x1U << CAN_INTEN_QDZIEN_Pos) /*!< 0x00010000 */ +#define CAN_INTEN_QDZIEN CAN_INTEN_QDZIEN_Msk /*!< Quit doze mode interrupt enable */ +#define CAN_INTEN_EDZIEN_Pos (17U) +#define CAN_INTEN_EDZIEN_Msk (0x1U << CAN_INTEN_EDZIEN_Pos) /*!< 0x00020000 */ +#define CAN_INTEN_EDZIEN CAN_INTEN_EDZIEN_Msk /*!< Enter doze mode interrupt enable */ + +/******************* Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EAF_Pos (0U) +#define CAN_ESTS_EAF_Msk (0x1U << CAN_ESTS_EAF_Pos) /*!< 0x00000001 */ +#define CAN_ESTS_EAF CAN_ESTS_EAF_Msk /*!< Error active flag */ +#define CAN_ESTS_EPF_Pos (1U) +#define CAN_ESTS_EPF_Msk (0x1U << CAN_ESTS_EPF_Pos) /*!< 0x00000002 */ +#define CAN_ESTS_EPF CAN_ESTS_EPF_Msk /*!< Error passive flag */ +#define CAN_ESTS_BOF_Pos (2U) +#define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ +#define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ + +#define CAN_ESTS_ETR_Pos (4U) +#define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ +#define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ +#define CAN_ESTS_ETR_0 (0x1U << CAN_ESTS_ETR_Pos) /*!< 0x00000010 */ +#define CAN_ESTS_ETR_1 (0x2U << CAN_ESTS_ETR_Pos) /*!< 0x00000020 */ +#define CAN_ESTS_ETR_2 (0x4U << CAN_ESTS_ETR_Pos) /*!< 0x00000040 */ + +#define CAN_ESTS_TEC_Pos (16U) +#define CAN_ESTS_TEC_Msk (0xFFU << CAN_ESTS_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESTS_TEC CAN_ESTS_TEC_Msk /*!< Transmit error counter */ +#define CAN_ESTS_REC_Pos (24U) +#define CAN_ESTS_REC_Msk (0xFFU << CAN_ESTS_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESTS_REC CAN_ESTS_REC_Msk /*!< Receive error counter */ + +/******************* Bit definition for CAN_BTMG register ********************/ +#define CAN_BTMG_BRDIV_Pos (0U) +#define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ +#define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ + +#define CAN_BTMG_BTS1_Pos (16U) +#define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ +#define CAN_BTMG_BTS1_0 (0x1U << CAN_BTMG_BTS1_Pos) /*!< 0x00010000 */ +#define CAN_BTMG_BTS1_1 (0x2U << CAN_BTMG_BTS1_Pos) /*!< 0x00020000 */ +#define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ +#define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ + +#define CAN_BTMG_BTS2_Pos (20U) +#define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ +#define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ +#define CAN_BTMG_BTS2_0 (0x1U << CAN_BTMG_BTS2_Pos) /*!< 0x00100000 */ +#define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ +#define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ + +#define CAN_BTMG_RSAW_Pos (24U) +#define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ +#define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ +#define CAN_BTMG_RSAW_0 (0x1U << CAN_BTMG_RSAW_Pos) /*!< 0x01000000 */ +#define CAN_BTMG_RSAW_1 (0x2U << CAN_BTMG_RSAW_Pos) /*!< 0x02000000 */ + +#define CAN_BTMG_LBEN_Pos (30U) +#define CAN_BTMG_LBEN_Msk (0x1U << CAN_BTMG_LBEN_Pos) /*!< 0x40000000 */ +#define CAN_BTMG_LBEN CAN_BTMG_LBEN_Msk /*!< Loop back mode */ +#define CAN_BTMG_LOEN_Pos (31U) +#define CAN_BTMG_LOEN_Msk (0x1U << CAN_BTMG_LOEN_Pos) /*!< 0x80000000 */ +#define CAN_BTMG_LOEN CAN_BTMG_LOEN_Msk /*!< Listen-Only mode */ + +/*!< Mailbox registers */ +/******************* Bit definition for CAN_TMI0 register *******************/ +#define CAN_TMI0_TMSR_Pos (0U) +#define CAN_TMI0_TMSR_Msk (0x1U << CAN_TMI0_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI0_TMSR CAN_TMI0_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI0_TMFRSEL_Pos (1U) +#define CAN_TMI0_TMFRSEL_Msk (0x1U << CAN_TMI0_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI0_TMFRSEL CAN_TMI0_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI0_TMIDSEL_Pos (2U) +#define CAN_TMI0_TMIDSEL_Msk (0x1U << CAN_TMI0_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI0_TMIDSEL CAN_TMI0_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI0_TMEID_Pos (3U) +#define CAN_TMI0_TMEID_Msk (0x3FFFFU << CAN_TMI0_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI0_TMEID CAN_TMI0_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI0_TMSID_Pos (21U) +#define CAN_TMI0_TMSID_Msk (0x7FFU << CAN_TMI0_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI0_TMSID CAN_TMI0_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC0 register *******************/ +#define CAN_TMC0_TMDTBL_Pos (0U) +#define CAN_TMC0_TMDTBL_Msk (0xFU << CAN_TMC0_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC0_TMDTBL CAN_TMC0_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC0_TMTSTEN_Pos (8U) +#define CAN_TMC0_TMTSTEN_Msk (0x1U << CAN_TMC0_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC0_TMTSTEN CAN_TMC0_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC0_TMTS_Pos (16U) +#define CAN_TMC0_TMTS_Msk (0xFFFFU << CAN_TMC0_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC0_TMTS CAN_TMC0_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL0 register ******************/ +#define CAN_TMDTL0_TMDT0_Pos (0U) +#define CAN_TMDTL0_TMDT0_Msk (0xFFU << CAN_TMDTL0_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL0_TMDT0 CAN_TMDTL0_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL0_TMDT1_Pos (8U) +#define CAN_TMDTL0_TMDT1_Msk (0xFFU << CAN_TMDTL0_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL0_TMDT1 CAN_TMDTL0_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL0_TMDT2_Pos (16U) +#define CAN_TMDTL0_TMDT2_Msk (0xFFU << CAN_TMDTL0_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL0_TMDT2 CAN_TMDTL0_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL0_TMDT3_Pos (24U) +#define CAN_TMDTL0_TMDT3_Msk (0xFFU << CAN_TMDTL0_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL0_TMDT3 CAN_TMDTL0_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH0 register ******************/ +#define CAN_TMDTH0_TMDT4_Pos (0U) +#define CAN_TMDTH0_TMDT4_Msk (0xFFU << CAN_TMDTH0_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH0_TMDT4 CAN_TMDTH0_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH0_TMDT5_Pos (8U) +#define CAN_TMDTH0_TMDT5_Msk (0xFFU << CAN_TMDTH0_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH0_TMDT5 CAN_TMDTH0_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH0_TMDT6_Pos (16U) +#define CAN_TMDTH0_TMDT6_Msk (0xFFU << CAN_TMDTH0_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH0_TMDT6 CAN_TMDTH0_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH0_TMDT7_Pos (24U) +#define CAN_TMDTH0_TMDT7_Msk (0xFFU << CAN_TMDTH0_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH0_TMDT7 CAN_TMDTH0_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI1 register *******************/ +#define CAN_TMI1_TMSR_Pos (0U) +#define CAN_TMI1_TMSR_Msk (0x1U << CAN_TMI1_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI1_TMSR CAN_TMI1_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI1_TMFRSEL_Pos (1U) +#define CAN_TMI1_TMFRSEL_Msk (0x1U << CAN_TMI1_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI1_TMFRSEL CAN_TMI1_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI1_TMIDSEL_Pos (2U) +#define CAN_TMI1_TMIDSEL_Msk (0x1U << CAN_TMI1_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI1_TMIDSEL CAN_TMI1_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI1_TMEID_Pos (3U) +#define CAN_TMI1_TMEID_Msk (0x3FFFFU << CAN_TMI1_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI1_TMEID CAN_TMI1_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI1_TMSID_Pos (21U) +#define CAN_TMI1_TMSID_Msk (0x7FFU << CAN_TMI1_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI1_TMSID CAN_TMI1_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC1 register *******************/ +#define CAN_TMC1_TMDTBL_Pos (0U) +#define CAN_TMC1_TMDTBL_Msk (0xFU << CAN_TMC1_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC1_TMDTBL CAN_TMC1_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC1_TMTSTEN_Pos (8U) +#define CAN_TMC1_TMTSTEN_Msk (0x1U << CAN_TMC1_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC1_TMTSTEN CAN_TMC1_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC1_TMTS_Pos (16U) +#define CAN_TMC1_TMTS_Msk (0xFFFFU << CAN_TMC1_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC1_TMTS CAN_TMC1_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL1 register ******************/ +#define CAN_TMDTL1_TMDT0_Pos (0U) +#define CAN_TMDTL1_TMDT0_Msk (0xFFU << CAN_TMDTL1_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL1_TMDT0 CAN_TMDTL1_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL1_TMDT1_Pos (8U) +#define CAN_TMDTL1_TMDT1_Msk (0xFFU << CAN_TMDTL1_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL1_TMDT1 CAN_TMDTL1_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL1_TMDT2_Pos (16U) +#define CAN_TMDTL1_TMDT2_Msk (0xFFU << CAN_TMDTL1_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL1_TMDT2 CAN_TMDTL1_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL1_TMDT3_Pos (24U) +#define CAN_TMDTL1_TMDT3_Msk (0xFFU << CAN_TMDTL1_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL1_TMDT3 CAN_TMDTL1_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH1 register ******************/ +#define CAN_TMDTH1_TMDT4_Pos (0U) +#define CAN_TMDTH1_TMDT4_Msk (0xFFU << CAN_TMDTH1_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH1_TMDT4 CAN_TMDTH1_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH1_TMDT5_Pos (8U) +#define CAN_TMDTH1_TMDT5_Msk (0xFFU << CAN_TMDTH1_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH1_TMDT5 CAN_TMDTH1_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH1_TMDT6_Pos (16U) +#define CAN_TMDTH1_TMDT6_Msk (0xFFU << CAN_TMDTH1_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH1_TMDT6 CAN_TMDTH1_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH1_TMDT7_Pos (24U) +#define CAN_TMDTH1_TMDT7_Msk (0xFFU << CAN_TMDTH1_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH1_TMDT7 CAN_TMDTH1_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI2 register *******************/ +#define CAN_TMI2_TMSR_Pos (0U) +#define CAN_TMI2_TMSR_Msk (0x1U << CAN_TMI2_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI2_TMSR CAN_TMI2_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI2_TMFRSEL_Pos (1U) +#define CAN_TMI2_TMFRSEL_Msk (0x1U << CAN_TMI2_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI2_TMFRSEL CAN_TMI2_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI2_TMIDSEL_Pos (2U) +#define CAN_TMI2_TMIDSEL_Msk (0x1U << CAN_TMI2_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI2_TMIDSEL CAN_TMI2_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI2_TMEID_Pos (3U) +#define CAN_TMI2_TMEID_Msk (0x3FFFFU << CAN_TMI2_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI2_TMEID CAN_TMI2_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI2_TMSID_Pos (21U) +#define CAN_TMI2_TMSID_Msk (0x7FFU << CAN_TMI2_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI2_TMSID CAN_TMI2_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC2 register *******************/ +#define CAN_TMC2_TMDTBL_Pos (0U) +#define CAN_TMC2_TMDTBL_Msk (0xFU << CAN_TMC2_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC2_TMDTBL CAN_TMC2_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC2_TMTSTEN_Pos (8U) +#define CAN_TMC2_TMTSTEN_Msk (0x1U << CAN_TMC2_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC2_TMTSTEN CAN_TMC2_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC2_TMTS_Pos (16U) +#define CAN_TMC2_TMTS_Msk (0xFFFFU << CAN_TMC2_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC2_TMTS CAN_TMC2_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL2 register ******************/ +#define CAN_TMDTL2_TMDT0_Pos (0U) +#define CAN_TMDTL2_TMDT0_Msk (0xFFU << CAN_TMDTL2_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL2_TMDT0 CAN_TMDTL2_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL2_TMDT1_Pos (8U) +#define CAN_TMDTL2_TMDT1_Msk (0xFFU << CAN_TMDTL2_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL2_TMDT1 CAN_TMDTL2_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL2_TMDT2_Pos (16U) +#define CAN_TMDTL2_TMDT2_Msk (0xFFU << CAN_TMDTL2_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL2_TMDT2 CAN_TMDTL2_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL2_TMDT3_Pos (24U) +#define CAN_TMDTL2_TMDT3_Msk (0xFFU << CAN_TMDTL2_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL2_TMDT3 CAN_TMDTL2_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH2 register ******************/ +#define CAN_TMDTH2_TMDT4_Pos (0U) +#define CAN_TMDTH2_TMDT4_Msk (0xFFU << CAN_TMDTH2_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH2_TMDT4 CAN_TMDTH2_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH2_TMDT5_Pos (8U) +#define CAN_TMDTH2_TMDT5_Msk (0xFFU << CAN_TMDTH2_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH2_TMDT5 CAN_TMDTH2_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH2_TMDT6_Pos (16U) +#define CAN_TMDTH2_TMDT6_Msk (0xFFU << CAN_TMDTH2_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH2_TMDT6 CAN_TMDTH2_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH2_TMDT7_Pos (24U) +#define CAN_TMDTH2_TMDT7_Msk (0xFFU << CAN_TMDTH2_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH2_TMDT7 CAN_TMDTH2_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_RFI0 register *******************/ +#define CAN_RFI0_RFFRI_Pos (1U) +#define CAN_RFI0_RFFRI_Msk (0x1U << CAN_RFI0_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI0_RFFRI CAN_RFI0_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI0_RFIDI_Pos (2U) +#define CAN_RFI0_RFIDI_Msk (0x1U << CAN_RFI0_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI0_RFIDI CAN_RFI0_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI0_RFEID_Pos (3U) +#define CAN_RFI0_RFEID_Msk (0x3FFFFU << CAN_RFI0_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI0_RFEID CAN_RFI0_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI0_RFSID_Pos (21U) +#define CAN_RFI0_RFSID_Msk (0x7FFU << CAN_RFI0_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI0_RFSID CAN_RFI0_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC0 register *******************/ +#define CAN_RFC0_RFDTL_Pos (0U) +#define CAN_RFC0_RFDTL_Msk (0xFU << CAN_RFC0_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC0_RFDTL CAN_RFC0_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC0_RFFMN_Pos (8U) +#define CAN_RFC0_RFFMN_Msk (0xFFU << CAN_RFC0_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC0_RFFMN CAN_RFC0_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC0_RFTS_Pos (16U) +#define CAN_RFC0_RFTS_Msk (0xFFFFU << CAN_RFC0_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC0_RFTS CAN_RFC0_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL0 register ******************/ +#define CAN_RFDTL0_RFDT0_Pos (0U) +#define CAN_RFDTL0_RFDT0_Msk (0xFFU << CAN_RFDTL0_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL0_RFDT0 CAN_RFDTL0_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL0_RFDT1_Pos (8U) +#define CAN_RFDTL0_RFDT1_Msk (0xFFU << CAN_RFDTL0_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL0_RFDT1 CAN_RFDTL0_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL0_RFDT2_Pos (16U) +#define CAN_RFDTL0_RFDT2_Msk (0xFFU << CAN_RFDTL0_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL0_RFDT2 CAN_RFDTL0_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL0_RFDT3_Pos (24U) +#define CAN_RFDTL0_RFDT3_Msk (0xFFU << CAN_RFDTL0_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL0_RFDT3 CAN_RFDTL0_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH0 register ******************/ +#define CAN_RFDTH0_RFDT4_Pos (0U) +#define CAN_RFDTH0_RFDT4_Msk (0xFFU << CAN_RFDTH0_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH0_RFDT4 CAN_RFDTH0_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH0_RFDT5_Pos (8U) +#define CAN_RFDTH0_RFDT5_Msk (0xFFU << CAN_RFDTH0_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH0_RFDT5 CAN_RFDTH0_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH0_RFDT6_Pos (16U) +#define CAN_RFDTH0_RFDT6_Msk (0xFFU << CAN_RFDTH0_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH0_RFDT6 CAN_RFDTH0_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH0_RFDT7_Pos (24U) +#define CAN_RFDTH0_RFDT7_Msk (0xFFU << CAN_RFDTH0_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH0_RFDT7 CAN_RFDTH0_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/******************* Bit definition for CAN_RFI1 register *******************/ +#define CAN_RFI1_RFFRI_Pos (1U) +#define CAN_RFI1_RFFRI_Msk (0x1U << CAN_RFI1_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI1_RFFRI CAN_RFI1_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI1_RFIDI_Pos (2U) +#define CAN_RFI1_RFIDI_Msk (0x1U << CAN_RFI1_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI1_RFIDI CAN_RFI1_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI1_RFEID_Pos (3U) +#define CAN_RFI1_RFEID_Msk (0x3FFFFU << CAN_RFI1_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI1_RFEID CAN_RFI1_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI1_RFSID_Pos (21U) +#define CAN_RFI1_RFSID_Msk (0x7FFU << CAN_RFI1_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI1_RFSID CAN_RFI1_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC1 register *******************/ +#define CAN_RFC1_RFDTL_Pos (0U) +#define CAN_RFC1_RFDTL_Msk (0xFU << CAN_RFC1_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC1_RFDTL CAN_RFC1_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC1_RFFMN_Pos (8U) +#define CAN_RFC1_RFFMN_Msk (0xFFU << CAN_RFC1_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC1_RFFMN CAN_RFC1_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC1_RFTS_Pos (16U) +#define CAN_RFC1_RFTS_Msk (0xFFFFU << CAN_RFC1_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC1_RFTS CAN_RFC1_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL1 register ******************/ +#define CAN_RFDTL1_RFDT0_Pos (0U) +#define CAN_RFDTL1_RFDT0_Msk (0xFFU << CAN_RFDTL1_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL1_RFDT0 CAN_RFDTL1_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL1_RFDT1_Pos (8U) +#define CAN_RFDTL1_RFDT1_Msk (0xFFU << CAN_RFDTL1_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL1_RFDT1 CAN_RFDTL1_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL1_RFDT2_Pos (16U) +#define CAN_RFDTL1_RFDT2_Msk (0xFFU << CAN_RFDTL1_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL1_RFDT2 CAN_RFDTL1_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL1_RFDT3_Pos (24U) +#define CAN_RFDTL1_RFDT3_Msk (0xFFU << CAN_RFDTL1_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL1_RFDT3 CAN_RFDTL1_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH1 register ******************/ +#define CAN_RFDTH1_RFDT4_Pos (0U) +#define CAN_RFDTH1_RFDT4_Msk (0xFFU << CAN_RFDTH1_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH1_RFDT4 CAN_RFDTH1_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH1_RFDT5_Pos (8U) +#define CAN_RFDTH1_RFDT5_Msk (0xFFU << CAN_RFDTH1_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH1_RFDT5 CAN_RFDTH1_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH1_RFDT6_Pos (16U) +#define CAN_RFDTH1_RFDT6_Msk (0xFFU << CAN_RFDTH1_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH1_RFDT6 CAN_RFDTH1_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH1_RFDT7_Pos (24U) +#define CAN_RFDTH1_RFDT7_Msk (0xFFU << CAN_RFDTH1_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH1_RFDT7 CAN_RFDTH1_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/*!< CAN filter registers */ +/****************** Bit definition for CAN_FCTRL register *******************/ +#define CAN_FCTRL_FCS_Pos (0U) +#define CAN_FCTRL_FCS_Msk (0x1U << CAN_FCTRL_FCS_Pos) /*!< 0x00000001 */ +#define CAN_FCTRL_FCS CAN_FCTRL_FCS_Msk /*!< Filter configuration switch */ + +/****************** Bit definition for CAN_FMCFG register *******************/ +#define CAN_FMCFG_FMSEL_Pos (0U) +#define CAN_FMCFG_FMSEL_Msk (0x3FFFU << CAN_FMCFG_FMSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FMCFG_FMSEL CAN_FMCFG_FMSEL_Msk /*!< Filter mode select */ +#define CAN_FMCFG_FMSEL0_Pos (0U) +#define CAN_FMCFG_FMSEL0_Msk (0x1U << CAN_FMCFG_FMSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FMCFG_FMSEL0 CAN_FMCFG_FMSEL0_Msk /*!< Filter mode select for filter 0 */ +#define CAN_FMCFG_FMSEL1_Pos (1U) +#define CAN_FMCFG_FMSEL1_Msk (0x1U << CAN_FMCFG_FMSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FMCFG_FMSEL1 CAN_FMCFG_FMSEL1_Msk /*!< Filter mode select for filter 1 */ +#define CAN_FMCFG_FMSEL2_Pos (2U) +#define CAN_FMCFG_FMSEL2_Msk (0x1U << CAN_FMCFG_FMSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FMCFG_FMSEL2 CAN_FMCFG_FMSEL2_Msk /*!< Filter mode select for filter 2 */ +#define CAN_FMCFG_FMSEL3_Pos (3U) +#define CAN_FMCFG_FMSEL3_Msk (0x1U << CAN_FMCFG_FMSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FMCFG_FMSEL3 CAN_FMCFG_FMSEL3_Msk /*!< Filter mode select for filter 3 */ +#define CAN_FMCFG_FMSEL4_Pos (4U) +#define CAN_FMCFG_FMSEL4_Msk (0x1U << CAN_FMCFG_FMSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FMCFG_FMSEL4 CAN_FMCFG_FMSEL4_Msk /*!< Filter mode select for filter 4 */ +#define CAN_FMCFG_FMSEL5_Pos (5U) +#define CAN_FMCFG_FMSEL5_Msk (0x1U << CAN_FMCFG_FMSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FMCFG_FMSEL5 CAN_FMCFG_FMSEL5_Msk /*!< Filter mode select for filter 5 */ +#define CAN_FMCFG_FMSEL6_Pos (6U) +#define CAN_FMCFG_FMSEL6_Msk (0x1U << CAN_FMCFG_FMSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FMCFG_FMSEL6 CAN_FMCFG_FMSEL6_Msk /*!< Filter mode select for filter 6 */ +#define CAN_FMCFG_FMSEL7_Pos (7U) +#define CAN_FMCFG_FMSEL7_Msk (0x1U << CAN_FMCFG_FMSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FMCFG_FMSEL7 CAN_FMCFG_FMSEL7_Msk /*!< Filter mode select for filter 7 */ +#define CAN_FMCFG_FMSEL8_Pos (8U) +#define CAN_FMCFG_FMSEL8_Msk (0x1U << CAN_FMCFG_FMSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FMCFG_FMSEL8 CAN_FMCFG_FMSEL8_Msk /*!< Filter mode select for filter 8 */ +#define CAN_FMCFG_FMSEL9_Pos (9U) +#define CAN_FMCFG_FMSEL9_Msk (0x1U << CAN_FMCFG_FMSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FMCFG_FMSEL9 CAN_FMCFG_FMSEL9_Msk /*!< Filter mode select for filter 9 */ +#define CAN_FMCFG_FMSEL10_Pos (10U) +#define CAN_FMCFG_FMSEL10_Msk (0x1U << CAN_FMCFG_FMSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FMCFG_FMSEL10 CAN_FMCFG_FMSEL10_Msk /*!< Filter mode select for filter 10 */ +#define CAN_FMCFG_FMSEL11_Pos (11U) +#define CAN_FMCFG_FMSEL11_Msk (0x1U << CAN_FMCFG_FMSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FMCFG_FMSEL11 CAN_FMCFG_FMSEL11_Msk /*!< Filter mode select for filter 11 */ +#define CAN_FMCFG_FMSEL12_Pos (12U) +#define CAN_FMCFG_FMSEL12_Msk (0x1U << CAN_FMCFG_FMSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FMCFG_FMSEL12 CAN_FMCFG_FMSEL12_Msk /*!< Filter mode select for filter 12 */ +#define CAN_FMCFG_FMSEL13_Pos (13U) +#define CAN_FMCFG_FMSEL13_Msk (0x1U << CAN_FMCFG_FMSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FMCFG_FMSEL13 CAN_FMCFG_FMSEL13_Msk /*!< Filter mode select for filter 13 */ + +/****************** Bit definition for CAN_FBWCFG register ******************/ +#define CAN_FBWCFG_FBWSEL_Pos (0U) +#define CAN_FBWCFG_FBWSEL_Msk (0x3FFFU << CAN_FBWCFG_FBWSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FBWCFG_FBWSEL CAN_FBWCFG_FBWSEL_Msk /*!< Filter bit width select */ +#define CAN_FBWCFG_FBWSEL0_Pos (0U) +#define CAN_FBWCFG_FBWSEL0_Msk (0x1U << CAN_FBWCFG_FBWSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FBWCFG_FBWSEL0 CAN_FBWCFG_FBWSEL0_Msk /*!< Filter bit width select for filter 0 */ +#define CAN_FBWCFG_FBWSEL1_Pos (1U) +#define CAN_FBWCFG_FBWSEL1_Msk (0x1U << CAN_FBWCFG_FBWSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FBWCFG_FBWSEL1 CAN_FBWCFG_FBWSEL1_Msk /*!< Filter bit width select for filter 1 */ +#define CAN_FBWCFG_FBWSEL2_Pos (2U) +#define CAN_FBWCFG_FBWSEL2_Msk (0x1U << CAN_FBWCFG_FBWSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FBWCFG_FBWSEL2 CAN_FBWCFG_FBWSEL2_Msk /*!< Filter bit width select for filter 2 */ +#define CAN_FBWCFG_FBWSEL3_Pos (3U) +#define CAN_FBWCFG_FBWSEL3_Msk (0x1U << CAN_FBWCFG_FBWSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FBWCFG_FBWSEL3 CAN_FBWCFG_FBWSEL3_Msk /*!< Filter bit width select for filter 3 */ +#define CAN_FBWCFG_FBWSEL4_Pos (4U) +#define CAN_FBWCFG_FBWSEL4_Msk (0x1U << CAN_FBWCFG_FBWSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FBWCFG_FBWSEL4 CAN_FBWCFG_FBWSEL4_Msk /*!< Filter bit width select for filter 4 */ +#define CAN_FBWCFG_FBWSEL5_Pos (5U) +#define CAN_FBWCFG_FBWSEL5_Msk (0x1U << CAN_FBWCFG_FBWSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FBWCFG_FBWSEL5 CAN_FBWCFG_FBWSEL5_Msk /*!< Filter bit width select for filter 5 */ +#define CAN_FBWCFG_FBWSEL6_Pos (6U) +#define CAN_FBWCFG_FBWSEL6_Msk (0x1U << CAN_FBWCFG_FBWSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FBWCFG_FBWSEL6 CAN_FBWCFG_FBWSEL6_Msk /*!< Filter bit width select for filter 6 */ +#define CAN_FBWCFG_FBWSEL7_Pos (7U) +#define CAN_FBWCFG_FBWSEL7_Msk (0x1U << CAN_FBWCFG_FBWSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FBWCFG_FBWSEL7 CAN_FBWCFG_FBWSEL7_Msk /*!< Filter bit width select for filter 7 */ +#define CAN_FBWCFG_FBWSEL8_Pos (8U) +#define CAN_FBWCFG_FBWSEL8_Msk (0x1U << CAN_FBWCFG_FBWSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FBWCFG_FBWSEL8 CAN_FBWCFG_FBWSEL8_Msk /*!< Filter bit width select for filter 8 */ +#define CAN_FBWCFG_FBWSEL9_Pos (9U) +#define CAN_FBWCFG_FBWSEL9_Msk (0x1U << CAN_FBWCFG_FBWSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FBWCFG_FBWSEL9 CAN_FBWCFG_FBWSEL9_Msk /*!< Filter bit width select for filter 9 */ +#define CAN_FBWCFG_FBWSEL10_Pos (10U) +#define CAN_FBWCFG_FBWSEL10_Msk (0x1U << CAN_FBWCFG_FBWSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FBWCFG_FBWSEL10 CAN_FBWCFG_FBWSEL10_Msk /*!< Filter bit width select for filter 10 */ +#define CAN_FBWCFG_FBWSEL11_Pos (11U) +#define CAN_FBWCFG_FBWSEL11_Msk (0x1U << CAN_FBWCFG_FBWSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FBWCFG_FBWSEL11 CAN_FBWCFG_FBWSEL11_Msk /*!< Filter bit width select for filter 11 */ +#define CAN_FBWCFG_FBWSEL12_Pos (12U) +#define CAN_FBWCFG_FBWSEL12_Msk (0x1U << CAN_FBWCFG_FBWSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FBWCFG_FBWSEL12 CAN_FBWCFG_FBWSEL12_Msk /*!< Filter bit width select for filter 12 */ +#define CAN_FBWCFG_FBWSEL13_Pos (13U) +#define CAN_FBWCFG_FBWSEL13_Msk (0x1U << CAN_FBWCFG_FBWSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FBWCFG_FBWSEL13 CAN_FBWCFG_FBWSEL13_Msk /*!< Filter bit width select for filter 13 */ + +/******************* Bit definition for CAN_FRF register ********************/ +#define CAN_FRF_FRFSEL_Pos (0U) +#define CAN_FRF_FRFSEL_Msk (0x3FFFU << CAN_FRF_FRFSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FRF_FRFSEL CAN_FRF_FRFSEL_Msk /*!< Filter relation FIFO select */ +#define CAN_FRF_FRFSEL0_Pos (0U) +#define CAN_FRF_FRFSEL0_Msk (0x1U << CAN_FRF_FRFSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FRF_FRFSEL0 CAN_FRF_FRFSEL0_Msk /*!< Filter relation FIFO select for filter 0 */ +#define CAN_FRF_FRFSEL1_Pos (1U) +#define CAN_FRF_FRFSEL1_Msk (0x1U << CAN_FRF_FRFSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FRF_FRFSEL1 CAN_FRF_FRFSEL1_Msk /*!< Filter relation FIFO select for filter 1 */ +#define CAN_FRF_FRFSEL2_Pos (2U) +#define CAN_FRF_FRFSEL2_Msk (0x1U << CAN_FRF_FRFSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FRF_FRFSEL2 CAN_FRF_FRFSEL2_Msk /*!< Filter relation FIFO select for filter 2 */ +#define CAN_FRF_FRFSEL3_Pos (3U) +#define CAN_FRF_FRFSEL3_Msk (0x1U << CAN_FRF_FRFSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FRF_FRFSEL3 CAN_FRF_FRFSEL3_Msk /*!< Filter relation FIFO select for filter 3 */ +#define CAN_FRF_FRFSEL4_Pos (4U) +#define CAN_FRF_FRFSEL4_Msk (0x1U << CAN_FRF_FRFSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FRF_FRFSEL4 CAN_FRF_FRFSEL4_Msk /*!< Filter relation FIFO select for filter 4 */ +#define CAN_FRF_FRFSEL5_Pos (5U) +#define CAN_FRF_FRFSEL5_Msk (0x1U << CAN_FRF_FRFSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FRF_FRFSEL5 CAN_FRF_FRFSEL5_Msk /*!< Filter relation FIFO select for filter 5 */ +#define CAN_FRF_FRFSEL6_Pos (6U) +#define CAN_FRF_FRFSEL6_Msk (0x1U << CAN_FRF_FRFSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FRF_FRFSEL6 CAN_FRF_FRFSEL6_Msk /*!< Filter relation FIFO select for filter 6 */ +#define CAN_FRF_FRFSEL7_Pos (7U) +#define CAN_FRF_FRFSEL7_Msk (0x1U << CAN_FRF_FRFSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FRF_FRFSEL7 CAN_FRF_FRFSEL7_Msk /*!< Filter relation FIFO select for filter 7 */ +#define CAN_FRF_FRFSEL8_Pos (8U) +#define CAN_FRF_FRFSEL8_Msk (0x1U << CAN_FRF_FRFSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FRF_FRFSEL8 CAN_FRF_FRFSEL8_Msk /*!< Filter relation FIFO select for filter 8 */ +#define CAN_FRF_FRFSEL9_Pos (9U) +#define CAN_FRF_FRFSEL9_Msk (0x1U << CAN_FRF_FRFSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FRF_FRFSEL9 CAN_FRF_FRFSEL9_Msk /*!< Filter relation FIFO select for filter 9 */ +#define CAN_FRF_FRFSEL10_Pos (10U) +#define CAN_FRF_FRFSEL10_Msk (0x1U << CAN_FRF_FRFSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FRF_FRFSEL10 CAN_FRF_FRFSEL10_Msk /*!< Filter relation FIFO select for filter 10 */ +#define CAN_FRF_FRFSEL11_Pos (11U) +#define CAN_FRF_FRFSEL11_Msk (0x1U << CAN_FRF_FRFSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FRF_FRFSEL11 CAN_FRF_FRFSEL11_Msk /*!< Filter relation FIFO select for filter 11 */ +#define CAN_FRF_FRFSEL12_Pos (12U) +#define CAN_FRF_FRFSEL12_Msk (0x1U << CAN_FRF_FRFSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FRF_FRFSEL12 CAN_FRF_FRFSEL12_Msk /*!< Filter relation FIFO select for filter 12 */ +#define CAN_FRF_FRFSEL13_Pos (13U) +#define CAN_FRF_FRFSEL13_Msk (0x1U << CAN_FRF_FRFSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FRF_FRFSEL13 CAN_FRF_FRFSEL13_Msk /*!< Filter relation FIFO select for filter 13 */ + +/****************** Bit definition for CAN_FACFG register *******************/ +#define CAN_FACFG_FAEN_Pos (0U) +#define CAN_FACFG_FAEN_Msk (0x3FFFU << CAN_FACFG_FAEN_Pos) /*!< 0x00003FFF */ +#define CAN_FACFG_FAEN CAN_FACFG_FAEN_Msk /*!< Filter active enable */ +#define CAN_FACFG_FAEN0_Pos (0U) +#define CAN_FACFG_FAEN0_Msk (0x1U << CAN_FACFG_FAEN0_Pos) /*!< 0x00000001 */ +#define CAN_FACFG_FAEN0 CAN_FACFG_FAEN0_Msk /*!< Filter 0 active enable */ +#define CAN_FACFG_FAEN1_Pos (1U) +#define CAN_FACFG_FAEN1_Msk (0x1U << CAN_FACFG_FAEN1_Pos) /*!< 0x00000002 */ +#define CAN_FACFG_FAEN1 CAN_FACFG_FAEN1_Msk /*!< Filter 1 active enable */ +#define CAN_FACFG_FAEN2_Pos (2U) +#define CAN_FACFG_FAEN2_Msk (0x1U << CAN_FACFG_FAEN2_Pos) /*!< 0x00000004 */ +#define CAN_FACFG_FAEN2 CAN_FACFG_FAEN2_Msk /*!< Filter 2 active enable */ +#define CAN_FACFG_FAEN3_Pos (3U) +#define CAN_FACFG_FAEN3_Msk (0x1U << CAN_FACFG_FAEN3_Pos) /*!< 0x00000008 */ +#define CAN_FACFG_FAEN3 CAN_FACFG_FAEN3_Msk /*!< Filter 3 active enable */ +#define CAN_FACFG_FAEN4_Pos (4U) +#define CAN_FACFG_FAEN4_Msk (0x1U << CAN_FACFG_FAEN4_Pos) /*!< 0x00000010 */ +#define CAN_FACFG_FAEN4 CAN_FACFG_FAEN4_Msk /*!< Filter 4 active enable */ +#define CAN_FACFG_FAEN5_Pos (5U) +#define CAN_FACFG_FAEN5_Msk (0x1U << CAN_FACFG_FAEN5_Pos) /*!< 0x00000020 */ +#define CAN_FACFG_FAEN5 CAN_FACFG_FAEN5_Msk /*!< Filter 5 active enable */ +#define CAN_FACFG_FAEN6_Pos (6U) +#define CAN_FACFG_FAEN6_Msk (0x1U << CAN_FACFG_FAEN6_Pos) /*!< 0x00000040 */ +#define CAN_FACFG_FAEN6 CAN_FACFG_FAEN6_Msk /*!< Filter 6 active enable */ +#define CAN_FACFG_FAEN7_Pos (7U) +#define CAN_FACFG_FAEN7_Msk (0x1U << CAN_FACFG_FAEN7_Pos) /*!< 0x00000080 */ +#define CAN_FACFG_FAEN7 CAN_FACFG_FAEN7_Msk /*!< Filter 7 active enable */ +#define CAN_FACFG_FAEN8_Pos (8U) +#define CAN_FACFG_FAEN8_Msk (0x1U << CAN_FACFG_FAEN8_Pos) /*!< 0x00000100 */ +#define CAN_FACFG_FAEN8 CAN_FACFG_FAEN8_Msk /*!< Filter 8 active enable */ +#define CAN_FACFG_FAEN9_Pos (9U) +#define CAN_FACFG_FAEN9_Msk (0x1U << CAN_FACFG_FAEN9_Pos) /*!< 0x00000200 */ +#define CAN_FACFG_FAEN9 CAN_FACFG_FAEN9_Msk /*!< Filter 9 active enable */ +#define CAN_FACFG_FAEN10_Pos (10U) +#define CAN_FACFG_FAEN10_Msk (0x1U << CAN_FACFG_FAEN10_Pos) /*!< 0x00000400 */ +#define CAN_FACFG_FAEN10 CAN_FACFG_FAEN10_Msk /*!< Filter 10 active enable */ +#define CAN_FACFG_FAEN11_Pos (11U) +#define CAN_FACFG_FAEN11_Msk (0x1U << CAN_FACFG_FAEN11_Pos) /*!< 0x00000800 */ +#define CAN_FACFG_FAEN11 CAN_FACFG_FAEN11_Msk /*!< Filter 11 active enable */ +#define CAN_FACFG_FAEN12_Pos (12U) +#define CAN_FACFG_FAEN12_Msk (0x1U << CAN_FACFG_FAEN12_Pos) /*!< 0x00001000 */ +#define CAN_FACFG_FAEN12 CAN_FACFG_FAEN12_Msk /*!< Filter 12 active enable */ +#define CAN_FACFG_FAEN13_Pos (13U) +#define CAN_FACFG_FAEN13_Msk (0x1U << CAN_FACFG_FAEN13_Pos) /*!< 0x00002000 */ +#define CAN_FACFG_FAEN13 CAN_FACFG_FAEN13_Msk /*!< Filter 13 active enable */ + +/****************** Bit definition for CAN_F0FB1 register *******************/ +#define CAN_F0FB1_FFDB0_Pos (0U) +#define CAN_F0FB1_FFDB0_Msk (0x1U << CAN_F0FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB1_FFDB0 CAN_F0FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB1_FFDB1_Pos (1U) +#define CAN_F0FB1_FFDB1_Msk (0x1U << CAN_F0FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB1_FFDB1 CAN_F0FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB1_FFDB2_Pos (2U) +#define CAN_F0FB1_FFDB2_Msk (0x1U << CAN_F0FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB1_FFDB2 CAN_F0FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB1_FFDB3_Pos (3U) +#define CAN_F0FB1_FFDB3_Msk (0x1U << CAN_F0FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB1_FFDB3 CAN_F0FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB1_FFDB4_Pos (4U) +#define CAN_F0FB1_FFDB4_Msk (0x1U << CAN_F0FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB1_FFDB4 CAN_F0FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB1_FFDB5_Pos (5U) +#define CAN_F0FB1_FFDB5_Msk (0x1U << CAN_F0FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB1_FFDB5 CAN_F0FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB1_FFDB6_Pos (6U) +#define CAN_F0FB1_FFDB6_Msk (0x1U << CAN_F0FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB1_FFDB6 CAN_F0FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB1_FFDB7_Pos (7U) +#define CAN_F0FB1_FFDB7_Msk (0x1U << CAN_F0FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB1_FFDB7 CAN_F0FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB1_FFDB8_Pos (8U) +#define CAN_F0FB1_FFDB8_Msk (0x1U << CAN_F0FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB1_FFDB8 CAN_F0FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB1_FFDB9_Pos (9U) +#define CAN_F0FB1_FFDB9_Msk (0x1U << CAN_F0FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB1_FFDB9 CAN_F0FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB1_FFDB10_Pos (10U) +#define CAN_F0FB1_FFDB10_Msk (0x1U << CAN_F0FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB1_FFDB10 CAN_F0FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB1_FFDB11_Pos (11U) +#define CAN_F0FB1_FFDB11_Msk (0x1U << CAN_F0FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB1_FFDB11 CAN_F0FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB1_FFDB12_Pos (12U) +#define CAN_F0FB1_FFDB12_Msk (0x1U << CAN_F0FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB1_FFDB12 CAN_F0FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB1_FFDB13_Pos (13U) +#define CAN_F0FB1_FFDB13_Msk (0x1U << CAN_F0FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB1_FFDB13 CAN_F0FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB1_FFDB14_Pos (14U) +#define CAN_F0FB1_FFDB14_Msk (0x1U << CAN_F0FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB1_FFDB14 CAN_F0FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB1_FFDB15_Pos (15U) +#define CAN_F0FB1_FFDB15_Msk (0x1U << CAN_F0FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB1_FFDB15 CAN_F0FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB1_FFDB16_Pos (16U) +#define CAN_F0FB1_FFDB16_Msk (0x1U << CAN_F0FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB1_FFDB16 CAN_F0FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB1_FFDB17_Pos (17U) +#define CAN_F0FB1_FFDB17_Msk (0x1U << CAN_F0FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB1_FFDB17 CAN_F0FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB1_FFDB18_Pos (18U) +#define CAN_F0FB1_FFDB18_Msk (0x1U << CAN_F0FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB1_FFDB18 CAN_F0FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB1_FFDB19_Pos (19U) +#define CAN_F0FB1_FFDB19_Msk (0x1U << CAN_F0FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB1_FFDB19 CAN_F0FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB1_FFDB20_Pos (20U) +#define CAN_F0FB1_FFDB20_Msk (0x1U << CAN_F0FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB1_FFDB20 CAN_F0FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB1_FFDB21_Pos (21U) +#define CAN_F0FB1_FFDB21_Msk (0x1U << CAN_F0FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB1_FFDB21 CAN_F0FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB1_FFDB22_Pos (22U) +#define CAN_F0FB1_FFDB22_Msk (0x1U << CAN_F0FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB1_FFDB22 CAN_F0FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB1_FFDB23_Pos (23U) +#define CAN_F0FB1_FFDB23_Msk (0x1U << CAN_F0FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB1_FFDB23 CAN_F0FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB1_FFDB24_Pos (24U) +#define CAN_F0FB1_FFDB24_Msk (0x1U << CAN_F0FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB1_FFDB24 CAN_F0FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB1_FFDB25_Pos (25U) +#define CAN_F0FB1_FFDB25_Msk (0x1U << CAN_F0FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB1_FFDB25 CAN_F0FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB1_FFDB26_Pos (26U) +#define CAN_F0FB1_FFDB26_Msk (0x1U << CAN_F0FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB1_FFDB26 CAN_F0FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB1_FFDB27_Pos (27U) +#define CAN_F0FB1_FFDB27_Msk (0x1U << CAN_F0FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB1_FFDB27 CAN_F0FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB1_FFDB28_Pos (28U) +#define CAN_F0FB1_FFDB28_Msk (0x1U << CAN_F0FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB1_FFDB28 CAN_F0FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB1_FFDB29_Pos (29U) +#define CAN_F0FB1_FFDB29_Msk (0x1U << CAN_F0FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB1_FFDB29 CAN_F0FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB1_FFDB30_Pos (30U) +#define CAN_F0FB1_FFDB30_Msk (0x1U << CAN_F0FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB1_FFDB30 CAN_F0FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB1_FFDB31_Pos (31U) +#define CAN_F0FB1_FFDB31_Msk (0x1U << CAN_F0FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB1_FFDB31 CAN_F0FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB1 register *******************/ +#define CAN_F1FB1_FFDB0_Pos (0U) +#define CAN_F1FB1_FFDB0_Msk (0x1U << CAN_F1FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB1_FFDB0 CAN_F1FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB1_FFDB1_Pos (1U) +#define CAN_F1FB1_FFDB1_Msk (0x1U << CAN_F1FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB1_FFDB1 CAN_F1FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB1_FFDB2_Pos (2U) +#define CAN_F1FB1_FFDB2_Msk (0x1U << CAN_F1FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB1_FFDB2 CAN_F1FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB1_FFDB3_Pos (3U) +#define CAN_F1FB1_FFDB3_Msk (0x1U << CAN_F1FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB1_FFDB3 CAN_F1FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB1_FFDB4_Pos (4U) +#define CAN_F1FB1_FFDB4_Msk (0x1U << CAN_F1FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB1_FFDB4 CAN_F1FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB1_FFDB5_Pos (5U) +#define CAN_F1FB1_FFDB5_Msk (0x1U << CAN_F1FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB1_FFDB5 CAN_F1FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB1_FFDB6_Pos (6U) +#define CAN_F1FB1_FFDB6_Msk (0x1U << CAN_F1FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB1_FFDB6 CAN_F1FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB1_FFDB7_Pos (7U) +#define CAN_F1FB1_FFDB7_Msk (0x1U << CAN_F1FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB1_FFDB7 CAN_F1FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB1_FFDB8_Pos (8U) +#define CAN_F1FB1_FFDB8_Msk (0x1U << CAN_F1FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB1_FFDB8 CAN_F1FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB1_FFDB9_Pos (9U) +#define CAN_F1FB1_FFDB9_Msk (0x1U << CAN_F1FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB1_FFDB9 CAN_F1FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB1_FFDB10_Pos (10U) +#define CAN_F1FB1_FFDB10_Msk (0x1U << CAN_F1FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB1_FFDB10 CAN_F1FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB1_FFDB11_Pos (11U) +#define CAN_F1FB1_FFDB11_Msk (0x1U << CAN_F1FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB1_FFDB11 CAN_F1FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB1_FFDB12_Pos (12U) +#define CAN_F1FB1_FFDB12_Msk (0x1U << CAN_F1FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB1_FFDB12 CAN_F1FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB1_FFDB13_Pos (13U) +#define CAN_F1FB1_FFDB13_Msk (0x1U << CAN_F1FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB1_FFDB13 CAN_F1FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB1_FFDB14_Pos (14U) +#define CAN_F1FB1_FFDB14_Msk (0x1U << CAN_F1FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB1_FFDB14 CAN_F1FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB1_FFDB15_Pos (15U) +#define CAN_F1FB1_FFDB15_Msk (0x1U << CAN_F1FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB1_FFDB15 CAN_F1FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB1_FFDB16_Pos (16U) +#define CAN_F1FB1_FFDB16_Msk (0x1U << CAN_F1FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB1_FFDB16 CAN_F1FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB1_FFDB17_Pos (17U) +#define CAN_F1FB1_FFDB17_Msk (0x1U << CAN_F1FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB1_FFDB17 CAN_F1FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB1_FFDB18_Pos (18U) +#define CAN_F1FB1_FFDB18_Msk (0x1U << CAN_F1FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB1_FFDB18 CAN_F1FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB1_FFDB19_Pos (19U) +#define CAN_F1FB1_FFDB19_Msk (0x1U << CAN_F1FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB1_FFDB19 CAN_F1FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB1_FFDB20_Pos (20U) +#define CAN_F1FB1_FFDB20_Msk (0x1U << CAN_F1FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB1_FFDB20 CAN_F1FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB1_FFDB21_Pos (21U) +#define CAN_F1FB1_FFDB21_Msk (0x1U << CAN_F1FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB1_FFDB21 CAN_F1FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB1_FFDB22_Pos (22U) +#define CAN_F1FB1_FFDB22_Msk (0x1U << CAN_F1FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB1_FFDB22 CAN_F1FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB1_FFDB23_Pos (23U) +#define CAN_F1FB1_FFDB23_Msk (0x1U << CAN_F1FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB1_FFDB23 CAN_F1FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB1_FFDB24_Pos (24U) +#define CAN_F1FB1_FFDB24_Msk (0x1U << CAN_F1FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB1_FFDB24 CAN_F1FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB1_FFDB25_Pos (25U) +#define CAN_F1FB1_FFDB25_Msk (0x1U << CAN_F1FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB1_FFDB25 CAN_F1FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB1_FFDB26_Pos (26U) +#define CAN_F1FB1_FFDB26_Msk (0x1U << CAN_F1FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB1_FFDB26 CAN_F1FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB1_FFDB27_Pos (27U) +#define CAN_F1FB1_FFDB27_Msk (0x1U << CAN_F1FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB1_FFDB27 CAN_F1FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB1_FFDB28_Pos (28U) +#define CAN_F1FB1_FFDB28_Msk (0x1U << CAN_F1FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB1_FFDB28 CAN_F1FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB1_FFDB29_Pos (29U) +#define CAN_F1FB1_FFDB29_Msk (0x1U << CAN_F1FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB1_FFDB29 CAN_F1FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB1_FFDB30_Pos (30U) +#define CAN_F1FB1_FFDB30_Msk (0x1U << CAN_F1FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB1_FFDB30 CAN_F1FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB1_FFDB31_Pos (31U) +#define CAN_F1FB1_FFDB31_Msk (0x1U << CAN_F1FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB1_FFDB31 CAN_F1FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB1 register *******************/ +#define CAN_F2FB1_FFDB0_Pos (0U) +#define CAN_F2FB1_FFDB0_Msk (0x1U << CAN_F2FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB1_FFDB0 CAN_F2FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB1_FFDB1_Pos (1U) +#define CAN_F2FB1_FFDB1_Msk (0x1U << CAN_F2FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB1_FFDB1 CAN_F2FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB1_FFDB2_Pos (2U) +#define CAN_F2FB1_FFDB2_Msk (0x1U << CAN_F2FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB1_FFDB2 CAN_F2FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB1_FFDB3_Pos (3U) +#define CAN_F2FB1_FFDB3_Msk (0x1U << CAN_F2FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB1_FFDB3 CAN_F2FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB1_FFDB4_Pos (4U) +#define CAN_F2FB1_FFDB4_Msk (0x1U << CAN_F2FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB1_FFDB4 CAN_F2FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB1_FFDB5_Pos (5U) +#define CAN_F2FB1_FFDB5_Msk (0x1U << CAN_F2FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB1_FFDB5 CAN_F2FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB1_FFDB6_Pos (6U) +#define CAN_F2FB1_FFDB6_Msk (0x1U << CAN_F2FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB1_FFDB6 CAN_F2FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB1_FFDB7_Pos (7U) +#define CAN_F2FB1_FFDB7_Msk (0x1U << CAN_F2FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB1_FFDB7 CAN_F2FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB1_FFDB8_Pos (8U) +#define CAN_F2FB1_FFDB8_Msk (0x1U << CAN_F2FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB1_FFDB8 CAN_F2FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB1_FFDB9_Pos (9U) +#define CAN_F2FB1_FFDB9_Msk (0x1U << CAN_F2FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB1_FFDB9 CAN_F2FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB1_FFDB10_Pos (10U) +#define CAN_F2FB1_FFDB10_Msk (0x1U << CAN_F2FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB1_FFDB10 CAN_F2FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB1_FFDB11_Pos (11U) +#define CAN_F2FB1_FFDB11_Msk (0x1U << CAN_F2FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB1_FFDB11 CAN_F2FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB1_FFDB12_Pos (12U) +#define CAN_F2FB1_FFDB12_Msk (0x1U << CAN_F2FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB1_FFDB12 CAN_F2FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB1_FFDB13_Pos (13U) +#define CAN_F2FB1_FFDB13_Msk (0x1U << CAN_F2FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB1_FFDB13 CAN_F2FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB1_FFDB14_Pos (14U) +#define CAN_F2FB1_FFDB14_Msk (0x1U << CAN_F2FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB1_FFDB14 CAN_F2FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB1_FFDB15_Pos (15U) +#define CAN_F2FB1_FFDB15_Msk (0x1U << CAN_F2FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB1_FFDB15 CAN_F2FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB1_FFDB16_Pos (16U) +#define CAN_F2FB1_FFDB16_Msk (0x1U << CAN_F2FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB1_FFDB16 CAN_F2FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB1_FFDB17_Pos (17U) +#define CAN_F2FB1_FFDB17_Msk (0x1U << CAN_F2FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB1_FFDB17 CAN_F2FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB1_FFDB18_Pos (18U) +#define CAN_F2FB1_FFDB18_Msk (0x1U << CAN_F2FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB1_FFDB18 CAN_F2FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB1_FFDB19_Pos (19U) +#define CAN_F2FB1_FFDB19_Msk (0x1U << CAN_F2FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB1_FFDB19 CAN_F2FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB1_FFDB20_Pos (20U) +#define CAN_F2FB1_FFDB20_Msk (0x1U << CAN_F2FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB1_FFDB20 CAN_F2FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB1_FFDB21_Pos (21U) +#define CAN_F2FB1_FFDB21_Msk (0x1U << CAN_F2FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB1_FFDB21 CAN_F2FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB1_FFDB22_Pos (22U) +#define CAN_F2FB1_FFDB22_Msk (0x1U << CAN_F2FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB1_FFDB22 CAN_F2FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB1_FFDB23_Pos (23U) +#define CAN_F2FB1_FFDB23_Msk (0x1U << CAN_F2FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB1_FFDB23 CAN_F2FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB1_FFDB24_Pos (24U) +#define CAN_F2FB1_FFDB24_Msk (0x1U << CAN_F2FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB1_FFDB24 CAN_F2FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB1_FFDB25_Pos (25U) +#define CAN_F2FB1_FFDB25_Msk (0x1U << CAN_F2FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB1_FFDB25 CAN_F2FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB1_FFDB26_Pos (26U) +#define CAN_F2FB1_FFDB26_Msk (0x1U << CAN_F2FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB1_FFDB26 CAN_F2FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB1_FFDB27_Pos (27U) +#define CAN_F2FB1_FFDB27_Msk (0x1U << CAN_F2FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB1_FFDB27 CAN_F2FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB1_FFDB28_Pos (28U) +#define CAN_F2FB1_FFDB28_Msk (0x1U << CAN_F2FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB1_FFDB28 CAN_F2FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB1_FFDB29_Pos (29U) +#define CAN_F2FB1_FFDB29_Msk (0x1U << CAN_F2FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB1_FFDB29 CAN_F2FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB1_FFDB30_Pos (30U) +#define CAN_F2FB1_FFDB30_Msk (0x1U << CAN_F2FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB1_FFDB30 CAN_F2FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB1_FFDB31_Pos (31U) +#define CAN_F2FB1_FFDB31_Msk (0x1U << CAN_F2FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB1_FFDB31 CAN_F2FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB1 register *******************/ +#define CAN_F3FB1_FFDB0_Pos (0U) +#define CAN_F3FB1_FFDB0_Msk (0x1U << CAN_F3FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB1_FFDB0 CAN_F3FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB1_FFDB1_Pos (1U) +#define CAN_F3FB1_FFDB1_Msk (0x1U << CAN_F3FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB1_FFDB1 CAN_F3FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB1_FFDB2_Pos (2U) +#define CAN_F3FB1_FFDB2_Msk (0x1U << CAN_F3FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB1_FFDB2 CAN_F3FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB1_FFDB3_Pos (3U) +#define CAN_F3FB1_FFDB3_Msk (0x1U << CAN_F3FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB1_FFDB3 CAN_F3FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB1_FFDB4_Pos (4U) +#define CAN_F3FB1_FFDB4_Msk (0x1U << CAN_F3FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB1_FFDB4 CAN_F3FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB1_FFDB5_Pos (5U) +#define CAN_F3FB1_FFDB5_Msk (0x1U << CAN_F3FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB1_FFDB5 CAN_F3FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB1_FFDB6_Pos (6U) +#define CAN_F3FB1_FFDB6_Msk (0x1U << CAN_F3FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB1_FFDB6 CAN_F3FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB1_FFDB7_Pos (7U) +#define CAN_F3FB1_FFDB7_Msk (0x1U << CAN_F3FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB1_FFDB7 CAN_F3FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB1_FFDB8_Pos (8U) +#define CAN_F3FB1_FFDB8_Msk (0x1U << CAN_F3FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB1_FFDB8 CAN_F3FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB1_FFDB9_Pos (9U) +#define CAN_F3FB1_FFDB9_Msk (0x1U << CAN_F3FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB1_FFDB9 CAN_F3FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB1_FFDB10_Pos (10U) +#define CAN_F3FB1_FFDB10_Msk (0x1U << CAN_F3FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB1_FFDB10 CAN_F3FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB1_FFDB11_Pos (11U) +#define CAN_F3FB1_FFDB11_Msk (0x1U << CAN_F3FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB1_FFDB11 CAN_F3FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB1_FFDB12_Pos (12U) +#define CAN_F3FB1_FFDB12_Msk (0x1U << CAN_F3FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB1_FFDB12 CAN_F3FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB1_FFDB13_Pos (13U) +#define CAN_F3FB1_FFDB13_Msk (0x1U << CAN_F3FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB1_FFDB13 CAN_F3FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB1_FFDB14_Pos (14U) +#define CAN_F3FB1_FFDB14_Msk (0x1U << CAN_F3FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB1_FFDB14 CAN_F3FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB1_FFDB15_Pos (15U) +#define CAN_F3FB1_FFDB15_Msk (0x1U << CAN_F3FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB1_FFDB15 CAN_F3FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB1_FFDB16_Pos (16U) +#define CAN_F3FB1_FFDB16_Msk (0x1U << CAN_F3FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB1_FFDB16 CAN_F3FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB1_FFDB17_Pos (17U) +#define CAN_F3FB1_FFDB17_Msk (0x1U << CAN_F3FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB1_FFDB17 CAN_F3FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB1_FFDB18_Pos (18U) +#define CAN_F3FB1_FFDB18_Msk (0x1U << CAN_F3FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB1_FFDB18 CAN_F3FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB1_FFDB19_Pos (19U) +#define CAN_F3FB1_FFDB19_Msk (0x1U << CAN_F3FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB1_FFDB19 CAN_F3FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB1_FFDB20_Pos (20U) +#define CAN_F3FB1_FFDB20_Msk (0x1U << CAN_F3FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB1_FFDB20 CAN_F3FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB1_FFDB21_Pos (21U) +#define CAN_F3FB1_FFDB21_Msk (0x1U << CAN_F3FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB1_FFDB21 CAN_F3FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB1_FFDB22_Pos (22U) +#define CAN_F3FB1_FFDB22_Msk (0x1U << CAN_F3FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB1_FFDB22 CAN_F3FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB1_FFDB23_Pos (23U) +#define CAN_F3FB1_FFDB23_Msk (0x1U << CAN_F3FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB1_FFDB23 CAN_F3FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB1_FFDB24_Pos (24U) +#define CAN_F3FB1_FFDB24_Msk (0x1U << CAN_F3FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB1_FFDB24 CAN_F3FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB1_FFDB25_Pos (25U) +#define CAN_F3FB1_FFDB25_Msk (0x1U << CAN_F3FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB1_FFDB25 CAN_F3FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB1_FFDB26_Pos (26U) +#define CAN_F3FB1_FFDB26_Msk (0x1U << CAN_F3FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB1_FFDB26 CAN_F3FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB1_FFDB27_Pos (27U) +#define CAN_F3FB1_FFDB27_Msk (0x1U << CAN_F3FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB1_FFDB27 CAN_F3FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB1_FFDB28_Pos (28U) +#define CAN_F3FB1_FFDB28_Msk (0x1U << CAN_F3FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB1_FFDB28 CAN_F3FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB1_FFDB29_Pos (29U) +#define CAN_F3FB1_FFDB29_Msk (0x1U << CAN_F3FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB1_FFDB29 CAN_F3FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB1_FFDB30_Pos (30U) +#define CAN_F3FB1_FFDB30_Msk (0x1U << CAN_F3FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB1_FFDB30 CAN_F3FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB1_FFDB31_Pos (31U) +#define CAN_F3FB1_FFDB31_Msk (0x1U << CAN_F3FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB1_FFDB31 CAN_F3FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB1 register *******************/ +#define CAN_F4FB1_FFDB0_Pos (0U) +#define CAN_F4FB1_FFDB0_Msk (0x1U << CAN_F4FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB1_FFDB0 CAN_F4FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB1_FFDB1_Pos (1U) +#define CAN_F4FB1_FFDB1_Msk (0x1U << CAN_F4FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB1_FFDB1 CAN_F4FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB1_FFDB2_Pos (2U) +#define CAN_F4FB1_FFDB2_Msk (0x1U << CAN_F4FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB1_FFDB2 CAN_F4FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB1_FFDB3_Pos (3U) +#define CAN_F4FB1_FFDB3_Msk (0x1U << CAN_F4FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB1_FFDB3 CAN_F4FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB1_FFDB4_Pos (4U) +#define CAN_F4FB1_FFDB4_Msk (0x1U << CAN_F4FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB1_FFDB4 CAN_F4FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB1_FFDB5_Pos (5U) +#define CAN_F4FB1_FFDB5_Msk (0x1U << CAN_F4FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB1_FFDB5 CAN_F4FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB1_FFDB6_Pos (6U) +#define CAN_F4FB1_FFDB6_Msk (0x1U << CAN_F4FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB1_FFDB6 CAN_F4FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB1_FFDB7_Pos (7U) +#define CAN_F4FB1_FFDB7_Msk (0x1U << CAN_F4FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB1_FFDB7 CAN_F4FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB1_FFDB8_Pos (8U) +#define CAN_F4FB1_FFDB8_Msk (0x1U << CAN_F4FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB1_FFDB8 CAN_F4FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB1_FFDB9_Pos (9U) +#define CAN_F4FB1_FFDB9_Msk (0x1U << CAN_F4FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB1_FFDB9 CAN_F4FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB1_FFDB10_Pos (10U) +#define CAN_F4FB1_FFDB10_Msk (0x1U << CAN_F4FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB1_FFDB10 CAN_F4FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB1_FFDB11_Pos (11U) +#define CAN_F4FB1_FFDB11_Msk (0x1U << CAN_F4FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB1_FFDB11 CAN_F4FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB1_FFDB12_Pos (12U) +#define CAN_F4FB1_FFDB12_Msk (0x1U << CAN_F4FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB1_FFDB12 CAN_F4FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB1_FFDB13_Pos (13U) +#define CAN_F4FB1_FFDB13_Msk (0x1U << CAN_F4FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB1_FFDB13 CAN_F4FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB1_FFDB14_Pos (14U) +#define CAN_F4FB1_FFDB14_Msk (0x1U << CAN_F4FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB1_FFDB14 CAN_F4FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB1_FFDB15_Pos (15U) +#define CAN_F4FB1_FFDB15_Msk (0x1U << CAN_F4FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB1_FFDB15 CAN_F4FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB1_FFDB16_Pos (16U) +#define CAN_F4FB1_FFDB16_Msk (0x1U << CAN_F4FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB1_FFDB16 CAN_F4FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB1_FFDB17_Pos (17U) +#define CAN_F4FB1_FFDB17_Msk (0x1U << CAN_F4FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB1_FFDB17 CAN_F4FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB1_FFDB18_Pos (18U) +#define CAN_F4FB1_FFDB18_Msk (0x1U << CAN_F4FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB1_FFDB18 CAN_F4FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB1_FFDB19_Pos (19U) +#define CAN_F4FB1_FFDB19_Msk (0x1U << CAN_F4FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB1_FFDB19 CAN_F4FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB1_FFDB20_Pos (20U) +#define CAN_F4FB1_FFDB20_Msk (0x1U << CAN_F4FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB1_FFDB20 CAN_F4FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB1_FFDB21_Pos (21U) +#define CAN_F4FB1_FFDB21_Msk (0x1U << CAN_F4FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB1_FFDB21 CAN_F4FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB1_FFDB22_Pos (22U) +#define CAN_F4FB1_FFDB22_Msk (0x1U << CAN_F4FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB1_FFDB22 CAN_F4FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB1_FFDB23_Pos (23U) +#define CAN_F4FB1_FFDB23_Msk (0x1U << CAN_F4FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB1_FFDB23 CAN_F4FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB1_FFDB24_Pos (24U) +#define CAN_F4FB1_FFDB24_Msk (0x1U << CAN_F4FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB1_FFDB24 CAN_F4FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB1_FFDB25_Pos (25U) +#define CAN_F4FB1_FFDB25_Msk (0x1U << CAN_F4FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB1_FFDB25 CAN_F4FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB1_FFDB26_Pos (26U) +#define CAN_F4FB1_FFDB26_Msk (0x1U << CAN_F4FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB1_FFDB26 CAN_F4FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB1_FFDB27_Pos (27U) +#define CAN_F4FB1_FFDB27_Msk (0x1U << CAN_F4FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB1_FFDB27 CAN_F4FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB1_FFDB28_Pos (28U) +#define CAN_F4FB1_FFDB28_Msk (0x1U << CAN_F4FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB1_FFDB28 CAN_F4FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB1_FFDB29_Pos (29U) +#define CAN_F4FB1_FFDB29_Msk (0x1U << CAN_F4FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB1_FFDB29 CAN_F4FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB1_FFDB30_Pos (30U) +#define CAN_F4FB1_FFDB30_Msk (0x1U << CAN_F4FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB1_FFDB30 CAN_F4FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB1_FFDB31_Pos (31U) +#define CAN_F4FB1_FFDB31_Msk (0x1U << CAN_F4FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB1_FFDB31 CAN_F4FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB1 register *******************/ +#define CAN_F5FB1_FFDB0_Pos (0U) +#define CAN_F5FB1_FFDB0_Msk (0x1U << CAN_F5FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB1_FFDB0 CAN_F5FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB1_FFDB1_Pos (1U) +#define CAN_F5FB1_FFDB1_Msk (0x1U << CAN_F5FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB1_FFDB1 CAN_F5FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB1_FFDB2_Pos (2U) +#define CAN_F5FB1_FFDB2_Msk (0x1U << CAN_F5FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB1_FFDB2 CAN_F5FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB1_FFDB3_Pos (3U) +#define CAN_F5FB1_FFDB3_Msk (0x1U << CAN_F5FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB1_FFDB3 CAN_F5FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB1_FFDB4_Pos (4U) +#define CAN_F5FB1_FFDB4_Msk (0x1U << CAN_F5FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB1_FFDB4 CAN_F5FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB1_FFDB5_Pos (5U) +#define CAN_F5FB1_FFDB5_Msk (0x1U << CAN_F5FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB1_FFDB5 CAN_F5FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB1_FFDB6_Pos (6U) +#define CAN_F5FB1_FFDB6_Msk (0x1U << CAN_F5FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB1_FFDB6 CAN_F5FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB1_FFDB7_Pos (7U) +#define CAN_F5FB1_FFDB7_Msk (0x1U << CAN_F5FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB1_FFDB7 CAN_F5FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB1_FFDB8_Pos (8U) +#define CAN_F5FB1_FFDB8_Msk (0x1U << CAN_F5FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB1_FFDB8 CAN_F5FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB1_FFDB9_Pos (9U) +#define CAN_F5FB1_FFDB9_Msk (0x1U << CAN_F5FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB1_FFDB9 CAN_F5FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB1_FFDB10_Pos (10U) +#define CAN_F5FB1_FFDB10_Msk (0x1U << CAN_F5FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB1_FFDB10 CAN_F5FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB1_FFDB11_Pos (11U) +#define CAN_F5FB1_FFDB11_Msk (0x1U << CAN_F5FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB1_FFDB11 CAN_F5FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB1_FFDB12_Pos (12U) +#define CAN_F5FB1_FFDB12_Msk (0x1U << CAN_F5FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB1_FFDB12 CAN_F5FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB1_FFDB13_Pos (13U) +#define CAN_F5FB1_FFDB13_Msk (0x1U << CAN_F5FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB1_FFDB13 CAN_F5FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB1_FFDB14_Pos (14U) +#define CAN_F5FB1_FFDB14_Msk (0x1U << CAN_F5FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB1_FFDB14 CAN_F5FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB1_FFDB15_Pos (15U) +#define CAN_F5FB1_FFDB15_Msk (0x1U << CAN_F5FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB1_FFDB15 CAN_F5FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB1_FFDB16_Pos (16U) +#define CAN_F5FB1_FFDB16_Msk (0x1U << CAN_F5FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB1_FFDB16 CAN_F5FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB1_FFDB17_Pos (17U) +#define CAN_F5FB1_FFDB17_Msk (0x1U << CAN_F5FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB1_FFDB17 CAN_F5FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB1_FFDB18_Pos (18U) +#define CAN_F5FB1_FFDB18_Msk (0x1U << CAN_F5FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB1_FFDB18 CAN_F5FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB1_FFDB19_Pos (19U) +#define CAN_F5FB1_FFDB19_Msk (0x1U << CAN_F5FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB1_FFDB19 CAN_F5FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB1_FFDB20_Pos (20U) +#define CAN_F5FB1_FFDB20_Msk (0x1U << CAN_F5FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB1_FFDB20 CAN_F5FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB1_FFDB21_Pos (21U) +#define CAN_F5FB1_FFDB21_Msk (0x1U << CAN_F5FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB1_FFDB21 CAN_F5FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB1_FFDB22_Pos (22U) +#define CAN_F5FB1_FFDB22_Msk (0x1U << CAN_F5FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB1_FFDB22 CAN_F5FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB1_FFDB23_Pos (23U) +#define CAN_F5FB1_FFDB23_Msk (0x1U << CAN_F5FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB1_FFDB23 CAN_F5FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB1_FFDB24_Pos (24U) +#define CAN_F5FB1_FFDB24_Msk (0x1U << CAN_F5FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB1_FFDB24 CAN_F5FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB1_FFDB25_Pos (25U) +#define CAN_F5FB1_FFDB25_Msk (0x1U << CAN_F5FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB1_FFDB25 CAN_F5FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB1_FFDB26_Pos (26U) +#define CAN_F5FB1_FFDB26_Msk (0x1U << CAN_F5FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB1_FFDB26 CAN_F5FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB1_FFDB27_Pos (27U) +#define CAN_F5FB1_FFDB27_Msk (0x1U << CAN_F5FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB1_FFDB27 CAN_F5FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB1_FFDB28_Pos (28U) +#define CAN_F5FB1_FFDB28_Msk (0x1U << CAN_F5FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB1_FFDB28 CAN_F5FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB1_FFDB29_Pos (29U) +#define CAN_F5FB1_FFDB29_Msk (0x1U << CAN_F5FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB1_FFDB29 CAN_F5FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB1_FFDB30_Pos (30U) +#define CAN_F5FB1_FFDB30_Msk (0x1U << CAN_F5FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB1_FFDB30 CAN_F5FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB1_FFDB31_Pos (31U) +#define CAN_F5FB1_FFDB31_Msk (0x1U << CAN_F5FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB1_FFDB31 CAN_F5FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB1 register *******************/ +#define CAN_F6FB1_FFDB0_Pos (0U) +#define CAN_F6FB1_FFDB0_Msk (0x1U << CAN_F6FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB1_FFDB0 CAN_F6FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB1_FFDB1_Pos (1U) +#define CAN_F6FB1_FFDB1_Msk (0x1U << CAN_F6FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB1_FFDB1 CAN_F6FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB1_FFDB2_Pos (2U) +#define CAN_F6FB1_FFDB2_Msk (0x1U << CAN_F6FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB1_FFDB2 CAN_F6FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB1_FFDB3_Pos (3U) +#define CAN_F6FB1_FFDB3_Msk (0x1U << CAN_F6FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB1_FFDB3 CAN_F6FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB1_FFDB4_Pos (4U) +#define CAN_F6FB1_FFDB4_Msk (0x1U << CAN_F6FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB1_FFDB4 CAN_F6FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB1_FFDB5_Pos (5U) +#define CAN_F6FB1_FFDB5_Msk (0x1U << CAN_F6FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB1_FFDB5 CAN_F6FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB1_FFDB6_Pos (6U) +#define CAN_F6FB1_FFDB6_Msk (0x1U << CAN_F6FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB1_FFDB6 CAN_F6FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB1_FFDB7_Pos (7U) +#define CAN_F6FB1_FFDB7_Msk (0x1U << CAN_F6FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB1_FFDB7 CAN_F6FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB1_FFDB8_Pos (8U) +#define CAN_F6FB1_FFDB8_Msk (0x1U << CAN_F6FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB1_FFDB8 CAN_F6FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB1_FFDB9_Pos (9U) +#define CAN_F6FB1_FFDB9_Msk (0x1U << CAN_F6FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB1_FFDB9 CAN_F6FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB1_FFDB10_Pos (10U) +#define CAN_F6FB1_FFDB10_Msk (0x1U << CAN_F6FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB1_FFDB10 CAN_F6FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB1_FFDB11_Pos (11U) +#define CAN_F6FB1_FFDB11_Msk (0x1U << CAN_F6FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB1_FFDB11 CAN_F6FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB1_FFDB12_Pos (12U) +#define CAN_F6FB1_FFDB12_Msk (0x1U << CAN_F6FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB1_FFDB12 CAN_F6FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB1_FFDB13_Pos (13U) +#define CAN_F6FB1_FFDB13_Msk (0x1U << CAN_F6FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB1_FFDB13 CAN_F6FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB1_FFDB14_Pos (14U) +#define CAN_F6FB1_FFDB14_Msk (0x1U << CAN_F6FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB1_FFDB14 CAN_F6FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB1_FFDB15_Pos (15U) +#define CAN_F6FB1_FFDB15_Msk (0x1U << CAN_F6FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB1_FFDB15 CAN_F6FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB1_FFDB16_Pos (16U) +#define CAN_F6FB1_FFDB16_Msk (0x1U << CAN_F6FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB1_FFDB16 CAN_F6FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB1_FFDB17_Pos (17U) +#define CAN_F6FB1_FFDB17_Msk (0x1U << CAN_F6FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB1_FFDB17 CAN_F6FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB1_FFDB18_Pos (18U) +#define CAN_F6FB1_FFDB18_Msk (0x1U << CAN_F6FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB1_FFDB18 CAN_F6FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB1_FFDB19_Pos (19U) +#define CAN_F6FB1_FFDB19_Msk (0x1U << CAN_F6FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB1_FFDB19 CAN_F6FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB1_FFDB20_Pos (20U) +#define CAN_F6FB1_FFDB20_Msk (0x1U << CAN_F6FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB1_FFDB20 CAN_F6FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB1_FFDB21_Pos (21U) +#define CAN_F6FB1_FFDB21_Msk (0x1U << CAN_F6FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB1_FFDB21 CAN_F6FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB1_FFDB22_Pos (22U) +#define CAN_F6FB1_FFDB22_Msk (0x1U << CAN_F6FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB1_FFDB22 CAN_F6FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB1_FFDB23_Pos (23U) +#define CAN_F6FB1_FFDB23_Msk (0x1U << CAN_F6FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB1_FFDB23 CAN_F6FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB1_FFDB24_Pos (24U) +#define CAN_F6FB1_FFDB24_Msk (0x1U << CAN_F6FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB1_FFDB24 CAN_F6FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB1_FFDB25_Pos (25U) +#define CAN_F6FB1_FFDB25_Msk (0x1U << CAN_F6FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB1_FFDB25 CAN_F6FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB1_FFDB26_Pos (26U) +#define CAN_F6FB1_FFDB26_Msk (0x1U << CAN_F6FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB1_FFDB26 CAN_F6FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB1_FFDB27_Pos (27U) +#define CAN_F6FB1_FFDB27_Msk (0x1U << CAN_F6FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB1_FFDB27 CAN_F6FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB1_FFDB28_Pos (28U) +#define CAN_F6FB1_FFDB28_Msk (0x1U << CAN_F6FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB1_FFDB28 CAN_F6FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB1_FFDB29_Pos (29U) +#define CAN_F6FB1_FFDB29_Msk (0x1U << CAN_F6FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB1_FFDB29 CAN_F6FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB1_FFDB30_Pos (30U) +#define CAN_F6FB1_FFDB30_Msk (0x1U << CAN_F6FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB1_FFDB30 CAN_F6FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB1_FFDB31_Pos (31U) +#define CAN_F6FB1_FFDB31_Msk (0x1U << CAN_F6FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB1_FFDB31 CAN_F6FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB1 register *******************/ +#define CAN_F7FB1_FFDB0_Pos (0U) +#define CAN_F7FB1_FFDB0_Msk (0x1U << CAN_F7FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB1_FFDB0 CAN_F7FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB1_FFDB1_Pos (1U) +#define CAN_F7FB1_FFDB1_Msk (0x1U << CAN_F7FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB1_FFDB1 CAN_F7FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB1_FFDB2_Pos (2U) +#define CAN_F7FB1_FFDB2_Msk (0x1U << CAN_F7FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB1_FFDB2 CAN_F7FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB1_FFDB3_Pos (3U) +#define CAN_F7FB1_FFDB3_Msk (0x1U << CAN_F7FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB1_FFDB3 CAN_F7FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB1_FFDB4_Pos (4U) +#define CAN_F7FB1_FFDB4_Msk (0x1U << CAN_F7FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB1_FFDB4 CAN_F7FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB1_FFDB5_Pos (5U) +#define CAN_F7FB1_FFDB5_Msk (0x1U << CAN_F7FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB1_FFDB5 CAN_F7FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB1_FFDB6_Pos (6U) +#define CAN_F7FB1_FFDB6_Msk (0x1U << CAN_F7FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB1_FFDB6 CAN_F7FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB1_FFDB7_Pos (7U) +#define CAN_F7FB1_FFDB7_Msk (0x1U << CAN_F7FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB1_FFDB7 CAN_F7FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB1_FFDB8_Pos (8U) +#define CAN_F7FB1_FFDB8_Msk (0x1U << CAN_F7FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB1_FFDB8 CAN_F7FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB1_FFDB9_Pos (9U) +#define CAN_F7FB1_FFDB9_Msk (0x1U << CAN_F7FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB1_FFDB9 CAN_F7FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB1_FFDB10_Pos (10U) +#define CAN_F7FB1_FFDB10_Msk (0x1U << CAN_F7FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB1_FFDB10 CAN_F7FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB1_FFDB11_Pos (11U) +#define CAN_F7FB1_FFDB11_Msk (0x1U << CAN_F7FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB1_FFDB11 CAN_F7FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB1_FFDB12_Pos (12U) +#define CAN_F7FB1_FFDB12_Msk (0x1U << CAN_F7FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB1_FFDB12 CAN_F7FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB1_FFDB13_Pos (13U) +#define CAN_F7FB1_FFDB13_Msk (0x1U << CAN_F7FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB1_FFDB13 CAN_F7FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB1_FFDB14_Pos (14U) +#define CAN_F7FB1_FFDB14_Msk (0x1U << CAN_F7FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB1_FFDB14 CAN_F7FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB1_FFDB15_Pos (15U) +#define CAN_F7FB1_FFDB15_Msk (0x1U << CAN_F7FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB1_FFDB15 CAN_F7FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB1_FFDB16_Pos (16U) +#define CAN_F7FB1_FFDB16_Msk (0x1U << CAN_F7FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB1_FFDB16 CAN_F7FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB1_FFDB17_Pos (17U) +#define CAN_F7FB1_FFDB17_Msk (0x1U << CAN_F7FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB1_FFDB17 CAN_F7FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB1_FFDB18_Pos (18U) +#define CAN_F7FB1_FFDB18_Msk (0x1U << CAN_F7FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB1_FFDB18 CAN_F7FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB1_FFDB19_Pos (19U) +#define CAN_F7FB1_FFDB19_Msk (0x1U << CAN_F7FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB1_FFDB19 CAN_F7FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB1_FFDB20_Pos (20U) +#define CAN_F7FB1_FFDB20_Msk (0x1U << CAN_F7FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB1_FFDB20 CAN_F7FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB1_FFDB21_Pos (21U) +#define CAN_F7FB1_FFDB21_Msk (0x1U << CAN_F7FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB1_FFDB21 CAN_F7FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB1_FFDB22_Pos (22U) +#define CAN_F7FB1_FFDB22_Msk (0x1U << CAN_F7FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB1_FFDB22 CAN_F7FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB1_FFDB23_Pos (23U) +#define CAN_F7FB1_FFDB23_Msk (0x1U << CAN_F7FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB1_FFDB23 CAN_F7FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB1_FFDB24_Pos (24U) +#define CAN_F7FB1_FFDB24_Msk (0x1U << CAN_F7FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB1_FFDB24 CAN_F7FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB1_FFDB25_Pos (25U) +#define CAN_F7FB1_FFDB25_Msk (0x1U << CAN_F7FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB1_FFDB25 CAN_F7FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB1_FFDB26_Pos (26U) +#define CAN_F7FB1_FFDB26_Msk (0x1U << CAN_F7FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB1_FFDB26 CAN_F7FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB1_FFDB27_Pos (27U) +#define CAN_F7FB1_FFDB27_Msk (0x1U << CAN_F7FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB1_FFDB27 CAN_F7FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB1_FFDB28_Pos (28U) +#define CAN_F7FB1_FFDB28_Msk (0x1U << CAN_F7FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB1_FFDB28 CAN_F7FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB1_FFDB29_Pos (29U) +#define CAN_F7FB1_FFDB29_Msk (0x1U << CAN_F7FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB1_FFDB29 CAN_F7FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB1_FFDB30_Pos (30U) +#define CAN_F7FB1_FFDB30_Msk (0x1U << CAN_F7FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB1_FFDB30 CAN_F7FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB1_FFDB31_Pos (31U) +#define CAN_F7FB1_FFDB31_Msk (0x1U << CAN_F7FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB1_FFDB31 CAN_F7FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB1 register *******************/ +#define CAN_F8FB1_FFDB0_Pos (0U) +#define CAN_F8FB1_FFDB0_Msk (0x1U << CAN_F8FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB1_FFDB0 CAN_F8FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB1_FFDB1_Pos (1U) +#define CAN_F8FB1_FFDB1_Msk (0x1U << CAN_F8FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB1_FFDB1 CAN_F8FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB1_FFDB2_Pos (2U) +#define CAN_F8FB1_FFDB2_Msk (0x1U << CAN_F8FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB1_FFDB2 CAN_F8FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB1_FFDB3_Pos (3U) +#define CAN_F8FB1_FFDB3_Msk (0x1U << CAN_F8FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB1_FFDB3 CAN_F8FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB1_FFDB4_Pos (4U) +#define CAN_F8FB1_FFDB4_Msk (0x1U << CAN_F8FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB1_FFDB4 CAN_F8FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB1_FFDB5_Pos (5U) +#define CAN_F8FB1_FFDB5_Msk (0x1U << CAN_F8FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB1_FFDB5 CAN_F8FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB1_FFDB6_Pos (6U) +#define CAN_F8FB1_FFDB6_Msk (0x1U << CAN_F8FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB1_FFDB6 CAN_F8FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB1_FFDB7_Pos (7U) +#define CAN_F8FB1_FFDB7_Msk (0x1U << CAN_F8FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB1_FFDB7 CAN_F8FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB1_FFDB8_Pos (8U) +#define CAN_F8FB1_FFDB8_Msk (0x1U << CAN_F8FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB1_FFDB8 CAN_F8FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB1_FFDB9_Pos (9U) +#define CAN_F8FB1_FFDB9_Msk (0x1U << CAN_F8FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB1_FFDB9 CAN_F8FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB1_FFDB10_Pos (10U) +#define CAN_F8FB1_FFDB10_Msk (0x1U << CAN_F8FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB1_FFDB10 CAN_F8FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB1_FFDB11_Pos (11U) +#define CAN_F8FB1_FFDB11_Msk (0x1U << CAN_F8FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB1_FFDB11 CAN_F8FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB1_FFDB12_Pos (12U) +#define CAN_F8FB1_FFDB12_Msk (0x1U << CAN_F8FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB1_FFDB12 CAN_F8FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB1_FFDB13_Pos (13U) +#define CAN_F8FB1_FFDB13_Msk (0x1U << CAN_F8FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB1_FFDB13 CAN_F8FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB1_FFDB14_Pos (14U) +#define CAN_F8FB1_FFDB14_Msk (0x1U << CAN_F8FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB1_FFDB14 CAN_F8FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB1_FFDB15_Pos (15U) +#define CAN_F8FB1_FFDB15_Msk (0x1U << CAN_F8FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB1_FFDB15 CAN_F8FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB1_FFDB16_Pos (16U) +#define CAN_F8FB1_FFDB16_Msk (0x1U << CAN_F8FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB1_FFDB16 CAN_F8FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB1_FFDB17_Pos (17U) +#define CAN_F8FB1_FFDB17_Msk (0x1U << CAN_F8FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB1_FFDB17 CAN_F8FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB1_FFDB18_Pos (18U) +#define CAN_F8FB1_FFDB18_Msk (0x1U << CAN_F8FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB1_FFDB18 CAN_F8FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB1_FFDB19_Pos (19U) +#define CAN_F8FB1_FFDB19_Msk (0x1U << CAN_F8FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB1_FFDB19 CAN_F8FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB1_FFDB20_Pos (20U) +#define CAN_F8FB1_FFDB20_Msk (0x1U << CAN_F8FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB1_FFDB20 CAN_F8FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB1_FFDB21_Pos (21U) +#define CAN_F8FB1_FFDB21_Msk (0x1U << CAN_F8FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB1_FFDB21 CAN_F8FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB1_FFDB22_Pos (22U) +#define CAN_F8FB1_FFDB22_Msk (0x1U << CAN_F8FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB1_FFDB22 CAN_F8FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB1_FFDB23_Pos (23U) +#define CAN_F8FB1_FFDB23_Msk (0x1U << CAN_F8FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB1_FFDB23 CAN_F8FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB1_FFDB24_Pos (24U) +#define CAN_F8FB1_FFDB24_Msk (0x1U << CAN_F8FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB1_FFDB24 CAN_F8FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB1_FFDB25_Pos (25U) +#define CAN_F8FB1_FFDB25_Msk (0x1U << CAN_F8FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB1_FFDB25 CAN_F8FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB1_FFDB26_Pos (26U) +#define CAN_F8FB1_FFDB26_Msk (0x1U << CAN_F8FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB1_FFDB26 CAN_F8FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB1_FFDB27_Pos (27U) +#define CAN_F8FB1_FFDB27_Msk (0x1U << CAN_F8FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB1_FFDB27 CAN_F8FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB1_FFDB28_Pos (28U) +#define CAN_F8FB1_FFDB28_Msk (0x1U << CAN_F8FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB1_FFDB28 CAN_F8FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB1_FFDB29_Pos (29U) +#define CAN_F8FB1_FFDB29_Msk (0x1U << CAN_F8FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB1_FFDB29 CAN_F8FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB1_FFDB30_Pos (30U) +#define CAN_F8FB1_FFDB30_Msk (0x1U << CAN_F8FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB1_FFDB30 CAN_F8FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB1_FFDB31_Pos (31U) +#define CAN_F8FB1_FFDB31_Msk (0x1U << CAN_F8FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB1_FFDB31 CAN_F8FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB1 register *******************/ +#define CAN_F9FB1_FFDB0_Pos (0U) +#define CAN_F9FB1_FFDB0_Msk (0x1U << CAN_F9FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB1_FFDB0 CAN_F9FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB1_FFDB1_Pos (1U) +#define CAN_F9FB1_FFDB1_Msk (0x1U << CAN_F9FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB1_FFDB1 CAN_F9FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB1_FFDB2_Pos (2U) +#define CAN_F9FB1_FFDB2_Msk (0x1U << CAN_F9FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB1_FFDB2 CAN_F9FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB1_FFDB3_Pos (3U) +#define CAN_F9FB1_FFDB3_Msk (0x1U << CAN_F9FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB1_FFDB3 CAN_F9FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB1_FFDB4_Pos (4U) +#define CAN_F9FB1_FFDB4_Msk (0x1U << CAN_F9FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB1_FFDB4 CAN_F9FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB1_FFDB5_Pos (5U) +#define CAN_F9FB1_FFDB5_Msk (0x1U << CAN_F9FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB1_FFDB5 CAN_F9FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB1_FFDB6_Pos (6U) +#define CAN_F9FB1_FFDB6_Msk (0x1U << CAN_F9FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB1_FFDB6 CAN_F9FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB1_FFDB7_Pos (7U) +#define CAN_F9FB1_FFDB7_Msk (0x1U << CAN_F9FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB1_FFDB7 CAN_F9FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB1_FFDB8_Pos (8U) +#define CAN_F9FB1_FFDB8_Msk (0x1U << CAN_F9FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB1_FFDB8 CAN_F9FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB1_FFDB9_Pos (9U) +#define CAN_F9FB1_FFDB9_Msk (0x1U << CAN_F9FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB1_FFDB9 CAN_F9FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB1_FFDB10_Pos (10U) +#define CAN_F9FB1_FFDB10_Msk (0x1U << CAN_F9FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB1_FFDB10 CAN_F9FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB1_FFDB11_Pos (11U) +#define CAN_F9FB1_FFDB11_Msk (0x1U << CAN_F9FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB1_FFDB11 CAN_F9FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB1_FFDB12_Pos (12U) +#define CAN_F9FB1_FFDB12_Msk (0x1U << CAN_F9FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB1_FFDB12 CAN_F9FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB1_FFDB13_Pos (13U) +#define CAN_F9FB1_FFDB13_Msk (0x1U << CAN_F9FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB1_FFDB13 CAN_F9FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB1_FFDB14_Pos (14U) +#define CAN_F9FB1_FFDB14_Msk (0x1U << CAN_F9FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB1_FFDB14 CAN_F9FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB1_FFDB15_Pos (15U) +#define CAN_F9FB1_FFDB15_Msk (0x1U << CAN_F9FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB1_FFDB15 CAN_F9FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB1_FFDB16_Pos (16U) +#define CAN_F9FB1_FFDB16_Msk (0x1U << CAN_F9FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB1_FFDB16 CAN_F9FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB1_FFDB17_Pos (17U) +#define CAN_F9FB1_FFDB17_Msk (0x1U << CAN_F9FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB1_FFDB17 CAN_F9FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB1_FFDB18_Pos (18U) +#define CAN_F9FB1_FFDB18_Msk (0x1U << CAN_F9FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB1_FFDB18 CAN_F9FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB1_FFDB19_Pos (19U) +#define CAN_F9FB1_FFDB19_Msk (0x1U << CAN_F9FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB1_FFDB19 CAN_F9FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB1_FFDB20_Pos (20U) +#define CAN_F9FB1_FFDB20_Msk (0x1U << CAN_F9FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB1_FFDB20 CAN_F9FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB1_FFDB21_Pos (21U) +#define CAN_F9FB1_FFDB21_Msk (0x1U << CAN_F9FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB1_FFDB21 CAN_F9FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB1_FFDB22_Pos (22U) +#define CAN_F9FB1_FFDB22_Msk (0x1U << CAN_F9FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB1_FFDB22 CAN_F9FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB1_FFDB23_Pos (23U) +#define CAN_F9FB1_FFDB23_Msk (0x1U << CAN_F9FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB1_FFDB23 CAN_F9FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB1_FFDB24_Pos (24U) +#define CAN_F9FB1_FFDB24_Msk (0x1U << CAN_F9FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB1_FFDB24 CAN_F9FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB1_FFDB25_Pos (25U) +#define CAN_F9FB1_FFDB25_Msk (0x1U << CAN_F9FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB1_FFDB25 CAN_F9FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB1_FFDB26_Pos (26U) +#define CAN_F9FB1_FFDB26_Msk (0x1U << CAN_F9FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB1_FFDB26 CAN_F9FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB1_FFDB27_Pos (27U) +#define CAN_F9FB1_FFDB27_Msk (0x1U << CAN_F9FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB1_FFDB27 CAN_F9FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB1_FFDB28_Pos (28U) +#define CAN_F9FB1_FFDB28_Msk (0x1U << CAN_F9FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB1_FFDB28 CAN_F9FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB1_FFDB29_Pos (29U) +#define CAN_F9FB1_FFDB29_Msk (0x1U << CAN_F9FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB1_FFDB29 CAN_F9FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB1_FFDB30_Pos (30U) +#define CAN_F9FB1_FFDB30_Msk (0x1U << CAN_F9FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB1_FFDB30 CAN_F9FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB1_FFDB31_Pos (31U) +#define CAN_F9FB1_FFDB31_Msk (0x1U << CAN_F9FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB1_FFDB31 CAN_F9FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB1 register ******************/ +#define CAN_F10FB1_FFDB0_Pos (0U) +#define CAN_F10FB1_FFDB0_Msk (0x1U << CAN_F10FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB1_FFDB0 CAN_F10FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB1_FFDB1_Pos (1U) +#define CAN_F10FB1_FFDB1_Msk (0x1U << CAN_F10FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB1_FFDB1 CAN_F10FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB1_FFDB2_Pos (2U) +#define CAN_F10FB1_FFDB2_Msk (0x1U << CAN_F10FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB1_FFDB2 CAN_F10FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB1_FFDB3_Pos (3U) +#define CAN_F10FB1_FFDB3_Msk (0x1U << CAN_F10FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB1_FFDB3 CAN_F10FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB1_FFDB4_Pos (4U) +#define CAN_F10FB1_FFDB4_Msk (0x1U << CAN_F10FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB1_FFDB4 CAN_F10FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB1_FFDB5_Pos (5U) +#define CAN_F10FB1_FFDB5_Msk (0x1U << CAN_F10FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB1_FFDB5 CAN_F10FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB1_FFDB6_Pos (6U) +#define CAN_F10FB1_FFDB6_Msk (0x1U << CAN_F10FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB1_FFDB6 CAN_F10FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB1_FFDB7_Pos (7U) +#define CAN_F10FB1_FFDB7_Msk (0x1U << CAN_F10FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB1_FFDB7 CAN_F10FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB1_FFDB8_Pos (8U) +#define CAN_F10FB1_FFDB8_Msk (0x1U << CAN_F10FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB1_FFDB8 CAN_F10FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB1_FFDB9_Pos (9U) +#define CAN_F10FB1_FFDB9_Msk (0x1U << CAN_F10FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB1_FFDB9 CAN_F10FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB1_FFDB10_Pos (10U) +#define CAN_F10FB1_FFDB10_Msk (0x1U << CAN_F10FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB1_FFDB10 CAN_F10FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB1_FFDB11_Pos (11U) +#define CAN_F10FB1_FFDB11_Msk (0x1U << CAN_F10FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB1_FFDB11 CAN_F10FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB1_FFDB12_Pos (12U) +#define CAN_F10FB1_FFDB12_Msk (0x1U << CAN_F10FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB1_FFDB12 CAN_F10FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB1_FFDB13_Pos (13U) +#define CAN_F10FB1_FFDB13_Msk (0x1U << CAN_F10FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB1_FFDB13 CAN_F10FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB1_FFDB14_Pos (14U) +#define CAN_F10FB1_FFDB14_Msk (0x1U << CAN_F10FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB1_FFDB14 CAN_F10FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB1_FFDB15_Pos (15U) +#define CAN_F10FB1_FFDB15_Msk (0x1U << CAN_F10FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB1_FFDB15 CAN_F10FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB1_FFDB16_Pos (16U) +#define CAN_F10FB1_FFDB16_Msk (0x1U << CAN_F10FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB1_FFDB16 CAN_F10FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB1_FFDB17_Pos (17U) +#define CAN_F10FB1_FFDB17_Msk (0x1U << CAN_F10FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB1_FFDB17 CAN_F10FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB1_FFDB18_Pos (18U) +#define CAN_F10FB1_FFDB18_Msk (0x1U << CAN_F10FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB1_FFDB18 CAN_F10FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB1_FFDB19_Pos (19U) +#define CAN_F10FB1_FFDB19_Msk (0x1U << CAN_F10FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB1_FFDB19 CAN_F10FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB1_FFDB20_Pos (20U) +#define CAN_F10FB1_FFDB20_Msk (0x1U << CAN_F10FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB1_FFDB20 CAN_F10FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB1_FFDB21_Pos (21U) +#define CAN_F10FB1_FFDB21_Msk (0x1U << CAN_F10FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB1_FFDB21 CAN_F10FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB1_FFDB22_Pos (22U) +#define CAN_F10FB1_FFDB22_Msk (0x1U << CAN_F10FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB1_FFDB22 CAN_F10FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB1_FFDB23_Pos (23U) +#define CAN_F10FB1_FFDB23_Msk (0x1U << CAN_F10FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB1_FFDB23 CAN_F10FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB1_FFDB24_Pos (24U) +#define CAN_F10FB1_FFDB24_Msk (0x1U << CAN_F10FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB1_FFDB24 CAN_F10FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB1_FFDB25_Pos (25U) +#define CAN_F10FB1_FFDB25_Msk (0x1U << CAN_F10FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB1_FFDB25 CAN_F10FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB1_FFDB26_Pos (26U) +#define CAN_F10FB1_FFDB26_Msk (0x1U << CAN_F10FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB1_FFDB26 CAN_F10FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB1_FFDB27_Pos (27U) +#define CAN_F10FB1_FFDB27_Msk (0x1U << CAN_F10FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB1_FFDB27 CAN_F10FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB1_FFDB28_Pos (28U) +#define CAN_F10FB1_FFDB28_Msk (0x1U << CAN_F10FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB1_FFDB28 CAN_F10FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB1_FFDB29_Pos (29U) +#define CAN_F10FB1_FFDB29_Msk (0x1U << CAN_F10FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB1_FFDB29 CAN_F10FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB1_FFDB30_Pos (30U) +#define CAN_F10FB1_FFDB30_Msk (0x1U << CAN_F10FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB1_FFDB30 CAN_F10FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB1_FFDB31_Pos (31U) +#define CAN_F10FB1_FFDB31_Msk (0x1U << CAN_F10FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB1_FFDB31 CAN_F10FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB1 register ******************/ +#define CAN_F11FB1_FFDB0_Pos (0U) +#define CAN_F11FB1_FFDB0_Msk (0x1U << CAN_F11FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB1_FFDB0 CAN_F11FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB1_FFDB1_Pos (1U) +#define CAN_F11FB1_FFDB1_Msk (0x1U << CAN_F11FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB1_FFDB1 CAN_F11FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB1_FFDB2_Pos (2U) +#define CAN_F11FB1_FFDB2_Msk (0x1U << CAN_F11FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB1_FFDB2 CAN_F11FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB1_FFDB3_Pos (3U) +#define CAN_F11FB1_FFDB3_Msk (0x1U << CAN_F11FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB1_FFDB3 CAN_F11FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB1_FFDB4_Pos (4U) +#define CAN_F11FB1_FFDB4_Msk (0x1U << CAN_F11FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB1_FFDB4 CAN_F11FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB1_FFDB5_Pos (5U) +#define CAN_F11FB1_FFDB5_Msk (0x1U << CAN_F11FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB1_FFDB5 CAN_F11FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB1_FFDB6_Pos (6U) +#define CAN_F11FB1_FFDB6_Msk (0x1U << CAN_F11FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB1_FFDB6 CAN_F11FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB1_FFDB7_Pos (7U) +#define CAN_F11FB1_FFDB7_Msk (0x1U << CAN_F11FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB1_FFDB7 CAN_F11FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB1_FFDB8_Pos (8U) +#define CAN_F11FB1_FFDB8_Msk (0x1U << CAN_F11FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB1_FFDB8 CAN_F11FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB1_FFDB9_Pos (9U) +#define CAN_F11FB1_FFDB9_Msk (0x1U << CAN_F11FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB1_FFDB9 CAN_F11FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB1_FFDB10_Pos (10U) +#define CAN_F11FB1_FFDB10_Msk (0x1U << CAN_F11FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB1_FFDB10 CAN_F11FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB1_FFDB11_Pos (11U) +#define CAN_F11FB1_FFDB11_Msk (0x1U << CAN_F11FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB1_FFDB11 CAN_F11FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB1_FFDB12_Pos (12U) +#define CAN_F11FB1_FFDB12_Msk (0x1U << CAN_F11FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB1_FFDB12 CAN_F11FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB1_FFDB13_Pos (13U) +#define CAN_F11FB1_FFDB13_Msk (0x1U << CAN_F11FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB1_FFDB13 CAN_F11FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB1_FFDB14_Pos (14U) +#define CAN_F11FB1_FFDB14_Msk (0x1U << CAN_F11FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB1_FFDB14 CAN_F11FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB1_FFDB15_Pos (15U) +#define CAN_F11FB1_FFDB15_Msk (0x1U << CAN_F11FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB1_FFDB15 CAN_F11FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB1_FFDB16_Pos (16U) +#define CAN_F11FB1_FFDB16_Msk (0x1U << CAN_F11FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB1_FFDB16 CAN_F11FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB1_FFDB17_Pos (17U) +#define CAN_F11FB1_FFDB17_Msk (0x1U << CAN_F11FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB1_FFDB17 CAN_F11FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB1_FFDB18_Pos (18U) +#define CAN_F11FB1_FFDB18_Msk (0x1U << CAN_F11FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB1_FFDB18 CAN_F11FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB1_FFDB19_Pos (19U) +#define CAN_F11FB1_FFDB19_Msk (0x1U << CAN_F11FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB1_FFDB19 CAN_F11FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB1_FFDB20_Pos (20U) +#define CAN_F11FB1_FFDB20_Msk (0x1U << CAN_F11FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB1_FFDB20 CAN_F11FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB1_FFDB21_Pos (21U) +#define CAN_F11FB1_FFDB21_Msk (0x1U << CAN_F11FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB1_FFDB21 CAN_F11FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB1_FFDB22_Pos (22U) +#define CAN_F11FB1_FFDB22_Msk (0x1U << CAN_F11FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB1_FFDB22 CAN_F11FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB1_FFDB23_Pos (23U) +#define CAN_F11FB1_FFDB23_Msk (0x1U << CAN_F11FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB1_FFDB23 CAN_F11FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB1_FFDB24_Pos (24U) +#define CAN_F11FB1_FFDB24_Msk (0x1U << CAN_F11FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB1_FFDB24 CAN_F11FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB1_FFDB25_Pos (25U) +#define CAN_F11FB1_FFDB25_Msk (0x1U << CAN_F11FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB1_FFDB25 CAN_F11FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB1_FFDB26_Pos (26U) +#define CAN_F11FB1_FFDB26_Msk (0x1U << CAN_F11FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB1_FFDB26 CAN_F11FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB1_FFDB27_Pos (27U) +#define CAN_F11FB1_FFDB27_Msk (0x1U << CAN_F11FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB1_FFDB27 CAN_F11FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB1_FFDB28_Pos (28U) +#define CAN_F11FB1_FFDB28_Msk (0x1U << CAN_F11FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB1_FFDB28 CAN_F11FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB1_FFDB29_Pos (29U) +#define CAN_F11FB1_FFDB29_Msk (0x1U << CAN_F11FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB1_FFDB29 CAN_F11FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB1_FFDB30_Pos (30U) +#define CAN_F11FB1_FFDB30_Msk (0x1U << CAN_F11FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB1_FFDB30 CAN_F11FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB1_FFDB31_Pos (31U) +#define CAN_F11FB1_FFDB31_Msk (0x1U << CAN_F11FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB1_FFDB31 CAN_F11FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB1 register ******************/ +#define CAN_F12FB1_FFDB0_Pos (0U) +#define CAN_F12FB1_FFDB0_Msk (0x1U << CAN_F12FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB1_FFDB0 CAN_F12FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB1_FFDB1_Pos (1U) +#define CAN_F12FB1_FFDB1_Msk (0x1U << CAN_F12FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB1_FFDB1 CAN_F12FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB1_FFDB2_Pos (2U) +#define CAN_F12FB1_FFDB2_Msk (0x1U << CAN_F12FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB1_FFDB2 CAN_F12FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB1_FFDB3_Pos (3U) +#define CAN_F12FB1_FFDB3_Msk (0x1U << CAN_F12FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB1_FFDB3 CAN_F12FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB1_FFDB4_Pos (4U) +#define CAN_F12FB1_FFDB4_Msk (0x1U << CAN_F12FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB1_FFDB4 CAN_F12FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB1_FFDB5_Pos (5U) +#define CAN_F12FB1_FFDB5_Msk (0x1U << CAN_F12FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB1_FFDB5 CAN_F12FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB1_FFDB6_Pos (6U) +#define CAN_F12FB1_FFDB6_Msk (0x1U << CAN_F12FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB1_FFDB6 CAN_F12FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB1_FFDB7_Pos (7U) +#define CAN_F12FB1_FFDB7_Msk (0x1U << CAN_F12FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB1_FFDB7 CAN_F12FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB1_FFDB8_Pos (8U) +#define CAN_F12FB1_FFDB8_Msk (0x1U << CAN_F12FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB1_FFDB8 CAN_F12FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB1_FFDB9_Pos (9U) +#define CAN_F12FB1_FFDB9_Msk (0x1U << CAN_F12FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB1_FFDB9 CAN_F12FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB1_FFDB10_Pos (10U) +#define CAN_F12FB1_FFDB10_Msk (0x1U << CAN_F12FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB1_FFDB10 CAN_F12FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB1_FFDB11_Pos (11U) +#define CAN_F12FB1_FFDB11_Msk (0x1U << CAN_F12FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB1_FFDB11 CAN_F12FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB1_FFDB12_Pos (12U) +#define CAN_F12FB1_FFDB12_Msk (0x1U << CAN_F12FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB1_FFDB12 CAN_F12FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB1_FFDB13_Pos (13U) +#define CAN_F12FB1_FFDB13_Msk (0x1U << CAN_F12FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB1_FFDB13 CAN_F12FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB1_FFDB14_Pos (14U) +#define CAN_F12FB1_FFDB14_Msk (0x1U << CAN_F12FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB1_FFDB14 CAN_F12FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB1_FFDB15_Pos (15U) +#define CAN_F12FB1_FFDB15_Msk (0x1U << CAN_F12FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB1_FFDB15 CAN_F12FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB1_FFDB16_Pos (16U) +#define CAN_F12FB1_FFDB16_Msk (0x1U << CAN_F12FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB1_FFDB16 CAN_F12FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB1_FFDB17_Pos (17U) +#define CAN_F12FB1_FFDB17_Msk (0x1U << CAN_F12FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB1_FFDB17 CAN_F12FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB1_FFDB18_Pos (18U) +#define CAN_F12FB1_FFDB18_Msk (0x1U << CAN_F12FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB1_FFDB18 CAN_F12FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB1_FFDB19_Pos (19U) +#define CAN_F12FB1_FFDB19_Msk (0x1U << CAN_F12FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB1_FFDB19 CAN_F12FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB1_FFDB20_Pos (20U) +#define CAN_F12FB1_FFDB20_Msk (0x1U << CAN_F12FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB1_FFDB20 CAN_F12FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB1_FFDB21_Pos (21U) +#define CAN_F12FB1_FFDB21_Msk (0x1U << CAN_F12FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB1_FFDB21 CAN_F12FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB1_FFDB22_Pos (22U) +#define CAN_F12FB1_FFDB22_Msk (0x1U << CAN_F12FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB1_FFDB22 CAN_F12FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB1_FFDB23_Pos (23U) +#define CAN_F12FB1_FFDB23_Msk (0x1U << CAN_F12FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB1_FFDB23 CAN_F12FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB1_FFDB24_Pos (24U) +#define CAN_F12FB1_FFDB24_Msk (0x1U << CAN_F12FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB1_FFDB24 CAN_F12FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB1_FFDB25_Pos (25U) +#define CAN_F12FB1_FFDB25_Msk (0x1U << CAN_F12FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB1_FFDB25 CAN_F12FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB1_FFDB26_Pos (26U) +#define CAN_F12FB1_FFDB26_Msk (0x1U << CAN_F12FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB1_FFDB26 CAN_F12FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB1_FFDB27_Pos (27U) +#define CAN_F12FB1_FFDB27_Msk (0x1U << CAN_F12FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB1_FFDB27 CAN_F12FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB1_FFDB28_Pos (28U) +#define CAN_F12FB1_FFDB28_Msk (0x1U << CAN_F12FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB1_FFDB28 CAN_F12FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB1_FFDB29_Pos (29U) +#define CAN_F12FB1_FFDB29_Msk (0x1U << CAN_F12FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB1_FFDB29 CAN_F12FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB1_FFDB30_Pos (30U) +#define CAN_F12FB1_FFDB30_Msk (0x1U << CAN_F12FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB1_FFDB30 CAN_F12FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB1_FFDB31_Pos (31U) +#define CAN_F12FB1_FFDB31_Msk (0x1U << CAN_F12FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB1_FFDB31 CAN_F12FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB1 register ******************/ +#define CAN_F13FB1_FFDB0_Pos (0U) +#define CAN_F13FB1_FFDB0_Msk (0x1U << CAN_F13FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB1_FFDB0 CAN_F13FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB1_FFDB1_Pos (1U) +#define CAN_F13FB1_FFDB1_Msk (0x1U << CAN_F13FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB1_FFDB1 CAN_F13FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB1_FFDB2_Pos (2U) +#define CAN_F13FB1_FFDB2_Msk (0x1U << CAN_F13FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB1_FFDB2 CAN_F13FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB1_FFDB3_Pos (3U) +#define CAN_F13FB1_FFDB3_Msk (0x1U << CAN_F13FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB1_FFDB3 CAN_F13FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB1_FFDB4_Pos (4U) +#define CAN_F13FB1_FFDB4_Msk (0x1U << CAN_F13FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB1_FFDB4 CAN_F13FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB1_FFDB5_Pos (5U) +#define CAN_F13FB1_FFDB5_Msk (0x1U << CAN_F13FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB1_FFDB5 CAN_F13FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB1_FFDB6_Pos (6U) +#define CAN_F13FB1_FFDB6_Msk (0x1U << CAN_F13FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB1_FFDB6 CAN_F13FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB1_FFDB7_Pos (7U) +#define CAN_F13FB1_FFDB7_Msk (0x1U << CAN_F13FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB1_FFDB7 CAN_F13FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB1_FFDB8_Pos (8U) +#define CAN_F13FB1_FFDB8_Msk (0x1U << CAN_F13FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB1_FFDB8 CAN_F13FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB1_FFDB9_Pos (9U) +#define CAN_F13FB1_FFDB9_Msk (0x1U << CAN_F13FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB1_FFDB9 CAN_F13FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB1_FFDB10_Pos (10U) +#define CAN_F13FB1_FFDB10_Msk (0x1U << CAN_F13FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB1_FFDB10 CAN_F13FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB1_FFDB11_Pos (11U) +#define CAN_F13FB1_FFDB11_Msk (0x1U << CAN_F13FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB1_FFDB11 CAN_F13FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB1_FFDB12_Pos (12U) +#define CAN_F13FB1_FFDB12_Msk (0x1U << CAN_F13FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB1_FFDB12 CAN_F13FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB1_FFDB13_Pos (13U) +#define CAN_F13FB1_FFDB13_Msk (0x1U << CAN_F13FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB1_FFDB13 CAN_F13FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB1_FFDB14_Pos (14U) +#define CAN_F13FB1_FFDB14_Msk (0x1U << CAN_F13FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB1_FFDB14 CAN_F13FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB1_FFDB15_Pos (15U) +#define CAN_F13FB1_FFDB15_Msk (0x1U << CAN_F13FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB1_FFDB15 CAN_F13FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB1_FFDB16_Pos (16U) +#define CAN_F13FB1_FFDB16_Msk (0x1U << CAN_F13FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB1_FFDB16 CAN_F13FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB1_FFDB17_Pos (17U) +#define CAN_F13FB1_FFDB17_Msk (0x1U << CAN_F13FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB1_FFDB17 CAN_F13FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB1_FFDB18_Pos (18U) +#define CAN_F13FB1_FFDB18_Msk (0x1U << CAN_F13FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB1_FFDB18 CAN_F13FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB1_FFDB19_Pos (19U) +#define CAN_F13FB1_FFDB19_Msk (0x1U << CAN_F13FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB1_FFDB19 CAN_F13FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB1_FFDB20_Pos (20U) +#define CAN_F13FB1_FFDB20_Msk (0x1U << CAN_F13FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB1_FFDB20 CAN_F13FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB1_FFDB21_Pos (21U) +#define CAN_F13FB1_FFDB21_Msk (0x1U << CAN_F13FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB1_FFDB21 CAN_F13FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB1_FFDB22_Pos (22U) +#define CAN_F13FB1_FFDB22_Msk (0x1U << CAN_F13FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB1_FFDB22 CAN_F13FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB1_FFDB23_Pos (23U) +#define CAN_F13FB1_FFDB23_Msk (0x1U << CAN_F13FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB1_FFDB23 CAN_F13FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB1_FFDB24_Pos (24U) +#define CAN_F13FB1_FFDB24_Msk (0x1U << CAN_F13FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB1_FFDB24 CAN_F13FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB1_FFDB25_Pos (25U) +#define CAN_F13FB1_FFDB25_Msk (0x1U << CAN_F13FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB1_FFDB25 CAN_F13FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB1_FFDB26_Pos (26U) +#define CAN_F13FB1_FFDB26_Msk (0x1U << CAN_F13FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB1_FFDB26 CAN_F13FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB1_FFDB27_Pos (27U) +#define CAN_F13FB1_FFDB27_Msk (0x1U << CAN_F13FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB1_FFDB27 CAN_F13FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB1_FFDB28_Pos (28U) +#define CAN_F13FB1_FFDB28_Msk (0x1U << CAN_F13FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB1_FFDB28 CAN_F13FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB1_FFDB29_Pos (29U) +#define CAN_F13FB1_FFDB29_Msk (0x1U << CAN_F13FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB1_FFDB29 CAN_F13FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB1_FFDB30_Pos (30U) +#define CAN_F13FB1_FFDB30_Msk (0x1U << CAN_F13FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB1_FFDB30 CAN_F13FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB1_FFDB31_Pos (31U) +#define CAN_F13FB1_FFDB31_Msk (0x1U << CAN_F13FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB1_FFDB31 CAN_F13FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F0FB2 register *******************/ +#define CAN_F0FB2_FFDB0_Pos (0U) +#define CAN_F0FB2_FFDB0_Msk (0x1U << CAN_F0FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB2_FFDB0 CAN_F0FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB2_FFDB1_Pos (1U) +#define CAN_F0FB2_FFDB1_Msk (0x1U << CAN_F0FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB2_FFDB1 CAN_F0FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB2_FFDB2_Pos (2U) +#define CAN_F0FB2_FFDB2_Msk (0x1U << CAN_F0FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB2_FFDB2 CAN_F0FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB2_FFDB3_Pos (3U) +#define CAN_F0FB2_FFDB3_Msk (0x1U << CAN_F0FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB2_FFDB3 CAN_F0FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB2_FFDB4_Pos (4U) +#define CAN_F0FB2_FFDB4_Msk (0x1U << CAN_F0FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB2_FFDB4 CAN_F0FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB2_FFDB5_Pos (5U) +#define CAN_F0FB2_FFDB5_Msk (0x1U << CAN_F0FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB2_FFDB5 CAN_F0FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB2_FFDB6_Pos (6U) +#define CAN_F0FB2_FFDB6_Msk (0x1U << CAN_F0FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB2_FFDB6 CAN_F0FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB2_FFDB7_Pos (7U) +#define CAN_F0FB2_FFDB7_Msk (0x1U << CAN_F0FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB2_FFDB7 CAN_F0FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB2_FFDB8_Pos (8U) +#define CAN_F0FB2_FFDB8_Msk (0x1U << CAN_F0FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB2_FFDB8 CAN_F0FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB2_FFDB9_Pos (9U) +#define CAN_F0FB2_FFDB9_Msk (0x1U << CAN_F0FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB2_FFDB9 CAN_F0FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB2_FFDB10_Pos (10U) +#define CAN_F0FB2_FFDB10_Msk (0x1U << CAN_F0FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB2_FFDB10 CAN_F0FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB2_FFDB11_Pos (11U) +#define CAN_F0FB2_FFDB11_Msk (0x1U << CAN_F0FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB2_FFDB11 CAN_F0FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB2_FFDB12_Pos (12U) +#define CAN_F0FB2_FFDB12_Msk (0x1U << CAN_F0FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB2_FFDB12 CAN_F0FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB2_FFDB13_Pos (13U) +#define CAN_F0FB2_FFDB13_Msk (0x1U << CAN_F0FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB2_FFDB13 CAN_F0FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB2_FFDB14_Pos (14U) +#define CAN_F0FB2_FFDB14_Msk (0x1U << CAN_F0FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB2_FFDB14 CAN_F0FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB2_FFDB15_Pos (15U) +#define CAN_F0FB2_FFDB15_Msk (0x1U << CAN_F0FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB2_FFDB15 CAN_F0FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB2_FFDB16_Pos (16U) +#define CAN_F0FB2_FFDB16_Msk (0x1U << CAN_F0FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB2_FFDB16 CAN_F0FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB2_FFDB17_Pos (17U) +#define CAN_F0FB2_FFDB17_Msk (0x1U << CAN_F0FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB2_FFDB17 CAN_F0FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB2_FFDB18_Pos (18U) +#define CAN_F0FB2_FFDB18_Msk (0x1U << CAN_F0FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB2_FFDB18 CAN_F0FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB2_FFDB19_Pos (19U) +#define CAN_F0FB2_FFDB19_Msk (0x1U << CAN_F0FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB2_FFDB19 CAN_F0FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB2_FFDB20_Pos (20U) +#define CAN_F0FB2_FFDB20_Msk (0x1U << CAN_F0FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB2_FFDB20 CAN_F0FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB2_FFDB21_Pos (21U) +#define CAN_F0FB2_FFDB21_Msk (0x1U << CAN_F0FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB2_FFDB21 CAN_F0FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB2_FFDB22_Pos (22U) +#define CAN_F0FB2_FFDB22_Msk (0x1U << CAN_F0FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB2_FFDB22 CAN_F0FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB2_FFDB23_Pos (23U) +#define CAN_F0FB2_FFDB23_Msk (0x1U << CAN_F0FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB2_FFDB23 CAN_F0FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB2_FFDB24_Pos (24U) +#define CAN_F0FB2_FFDB24_Msk (0x1U << CAN_F0FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB2_FFDB24 CAN_F0FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB2_FFDB25_Pos (25U) +#define CAN_F0FB2_FFDB25_Msk (0x1U << CAN_F0FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB2_FFDB25 CAN_F0FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB2_FFDB26_Pos (26U) +#define CAN_F0FB2_FFDB26_Msk (0x1U << CAN_F0FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB2_FFDB26 CAN_F0FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB2_FFDB27_Pos (27U) +#define CAN_F0FB2_FFDB27_Msk (0x1U << CAN_F0FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB2_FFDB27 CAN_F0FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB2_FFDB28_Pos (28U) +#define CAN_F0FB2_FFDB28_Msk (0x1U << CAN_F0FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB2_FFDB28 CAN_F0FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB2_FFDB29_Pos (29U) +#define CAN_F0FB2_FFDB29_Msk (0x1U << CAN_F0FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB2_FFDB29 CAN_F0FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB2_FFDB30_Pos (30U) +#define CAN_F0FB2_FFDB30_Msk (0x1U << CAN_F0FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB2_FFDB30 CAN_F0FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB2_FFDB31_Pos (31U) +#define CAN_F0FB2_FFDB31_Msk (0x1U << CAN_F0FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB2_FFDB31 CAN_F0FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB2 register *******************/ +#define CAN_F1FB2_FFDB0_Pos (0U) +#define CAN_F1FB2_FFDB0_Msk (0x1U << CAN_F1FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB2_FFDB0 CAN_F1FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB2_FFDB1_Pos (1U) +#define CAN_F1FB2_FFDB1_Msk (0x1U << CAN_F1FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB2_FFDB1 CAN_F1FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB2_FFDB2_Pos (2U) +#define CAN_F1FB2_FFDB2_Msk (0x1U << CAN_F1FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB2_FFDB2 CAN_F1FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB2_FFDB3_Pos (3U) +#define CAN_F1FB2_FFDB3_Msk (0x1U << CAN_F1FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB2_FFDB3 CAN_F1FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB2_FFDB4_Pos (4U) +#define CAN_F1FB2_FFDB4_Msk (0x1U << CAN_F1FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB2_FFDB4 CAN_F1FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB2_FFDB5_Pos (5U) +#define CAN_F1FB2_FFDB5_Msk (0x1U << CAN_F1FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB2_FFDB5 CAN_F1FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB2_FFDB6_Pos (6U) +#define CAN_F1FB2_FFDB6_Msk (0x1U << CAN_F1FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB2_FFDB6 CAN_F1FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB2_FFDB7_Pos (7U) +#define CAN_F1FB2_FFDB7_Msk (0x1U << CAN_F1FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB2_FFDB7 CAN_F1FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB2_FFDB8_Pos (8U) +#define CAN_F1FB2_FFDB8_Msk (0x1U << CAN_F1FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB2_FFDB8 CAN_F1FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB2_FFDB9_Pos (9U) +#define CAN_F1FB2_FFDB9_Msk (0x1U << CAN_F1FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB2_FFDB9 CAN_F1FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB2_FFDB10_Pos (10U) +#define CAN_F1FB2_FFDB10_Msk (0x1U << CAN_F1FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB2_FFDB10 CAN_F1FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB2_FFDB11_Pos (11U) +#define CAN_F1FB2_FFDB11_Msk (0x1U << CAN_F1FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB2_FFDB11 CAN_F1FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB2_FFDB12_Pos (12U) +#define CAN_F1FB2_FFDB12_Msk (0x1U << CAN_F1FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB2_FFDB12 CAN_F1FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB2_FFDB13_Pos (13U) +#define CAN_F1FB2_FFDB13_Msk (0x1U << CAN_F1FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB2_FFDB13 CAN_F1FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB2_FFDB14_Pos (14U) +#define CAN_F1FB2_FFDB14_Msk (0x1U << CAN_F1FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB2_FFDB14 CAN_F1FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB2_FFDB15_Pos (15U) +#define CAN_F1FB2_FFDB15_Msk (0x1U << CAN_F1FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB2_FFDB15 CAN_F1FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB2_FFDB16_Pos (16U) +#define CAN_F1FB2_FFDB16_Msk (0x1U << CAN_F1FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB2_FFDB16 CAN_F1FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB2_FFDB17_Pos (17U) +#define CAN_F1FB2_FFDB17_Msk (0x1U << CAN_F1FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB2_FFDB17 CAN_F1FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB2_FFDB18_Pos (18U) +#define CAN_F1FB2_FFDB18_Msk (0x1U << CAN_F1FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB2_FFDB18 CAN_F1FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB2_FFDB19_Pos (19U) +#define CAN_F1FB2_FFDB19_Msk (0x1U << CAN_F1FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB2_FFDB19 CAN_F1FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB2_FFDB20_Pos (20U) +#define CAN_F1FB2_FFDB20_Msk (0x1U << CAN_F1FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB2_FFDB20 CAN_F1FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB2_FFDB21_Pos (21U) +#define CAN_F1FB2_FFDB21_Msk (0x1U << CAN_F1FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB2_FFDB21 CAN_F1FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB2_FFDB22_Pos (22U) +#define CAN_F1FB2_FFDB22_Msk (0x1U << CAN_F1FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB2_FFDB22 CAN_F1FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB2_FFDB23_Pos (23U) +#define CAN_F1FB2_FFDB23_Msk (0x1U << CAN_F1FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB2_FFDB23 CAN_F1FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB2_FFDB24_Pos (24U) +#define CAN_F1FB2_FFDB24_Msk (0x1U << CAN_F1FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB2_FFDB24 CAN_F1FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB2_FFDB25_Pos (25U) +#define CAN_F1FB2_FFDB25_Msk (0x1U << CAN_F1FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB2_FFDB25 CAN_F1FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB2_FFDB26_Pos (26U) +#define CAN_F1FB2_FFDB26_Msk (0x1U << CAN_F1FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB2_FFDB26 CAN_F1FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB2_FFDB27_Pos (27U) +#define CAN_F1FB2_FFDB27_Msk (0x1U << CAN_F1FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB2_FFDB27 CAN_F1FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB2_FFDB28_Pos (28U) +#define CAN_F1FB2_FFDB28_Msk (0x1U << CAN_F1FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB2_FFDB28 CAN_F1FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB2_FFDB29_Pos (29U) +#define CAN_F1FB2_FFDB29_Msk (0x1U << CAN_F1FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB2_FFDB29 CAN_F1FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB2_FFDB30_Pos (30U) +#define CAN_F1FB2_FFDB30_Msk (0x1U << CAN_F1FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB2_FFDB30 CAN_F1FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB2_FFDB31_Pos (31U) +#define CAN_F1FB2_FFDB31_Msk (0x1U << CAN_F1FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB2_FFDB31 CAN_F1FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB2 register *******************/ +#define CAN_F2FB2_FFDB0_Pos (0U) +#define CAN_F2FB2_FFDB0_Msk (0x1U << CAN_F2FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB2_FFDB0 CAN_F2FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB2_FFDB1_Pos (1U) +#define CAN_F2FB2_FFDB1_Msk (0x1U << CAN_F2FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB2_FFDB1 CAN_F2FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB2_FFDB2_Pos (2U) +#define CAN_F2FB2_FFDB2_Msk (0x1U << CAN_F2FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB2_FFDB2 CAN_F2FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB2_FFDB3_Pos (3U) +#define CAN_F2FB2_FFDB3_Msk (0x1U << CAN_F2FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB2_FFDB3 CAN_F2FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB2_FFDB4_Pos (4U) +#define CAN_F2FB2_FFDB4_Msk (0x1U << CAN_F2FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB2_FFDB4 CAN_F2FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB2_FFDB5_Pos (5U) +#define CAN_F2FB2_FFDB5_Msk (0x1U << CAN_F2FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB2_FFDB5 CAN_F2FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB2_FFDB6_Pos (6U) +#define CAN_F2FB2_FFDB6_Msk (0x1U << CAN_F2FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB2_FFDB6 CAN_F2FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB2_FFDB7_Pos (7U) +#define CAN_F2FB2_FFDB7_Msk (0x1U << CAN_F2FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB2_FFDB7 CAN_F2FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB2_FFDB8_Pos (8U) +#define CAN_F2FB2_FFDB8_Msk (0x1U << CAN_F2FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB2_FFDB8 CAN_F2FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB2_FFDB9_Pos (9U) +#define CAN_F2FB2_FFDB9_Msk (0x1U << CAN_F2FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB2_FFDB9 CAN_F2FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB2_FFDB10_Pos (10U) +#define CAN_F2FB2_FFDB10_Msk (0x1U << CAN_F2FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB2_FFDB10 CAN_F2FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB2_FFDB11_Pos (11U) +#define CAN_F2FB2_FFDB11_Msk (0x1U << CAN_F2FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB2_FFDB11 CAN_F2FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB2_FFDB12_Pos (12U) +#define CAN_F2FB2_FFDB12_Msk (0x1U << CAN_F2FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB2_FFDB12 CAN_F2FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB2_FFDB13_Pos (13U) +#define CAN_F2FB2_FFDB13_Msk (0x1U << CAN_F2FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB2_FFDB13 CAN_F2FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB2_FFDB14_Pos (14U) +#define CAN_F2FB2_FFDB14_Msk (0x1U << CAN_F2FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB2_FFDB14 CAN_F2FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB2_FFDB15_Pos (15U) +#define CAN_F2FB2_FFDB15_Msk (0x1U << CAN_F2FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB2_FFDB15 CAN_F2FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB2_FFDB16_Pos (16U) +#define CAN_F2FB2_FFDB16_Msk (0x1U << CAN_F2FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB2_FFDB16 CAN_F2FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB2_FFDB17_Pos (17U) +#define CAN_F2FB2_FFDB17_Msk (0x1U << CAN_F2FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB2_FFDB17 CAN_F2FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB2_FFDB18_Pos (18U) +#define CAN_F2FB2_FFDB18_Msk (0x1U << CAN_F2FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB2_FFDB18 CAN_F2FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB2_FFDB19_Pos (19U) +#define CAN_F2FB2_FFDB19_Msk (0x1U << CAN_F2FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB2_FFDB19 CAN_F2FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB2_FFDB20_Pos (20U) +#define CAN_F2FB2_FFDB20_Msk (0x1U << CAN_F2FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB2_FFDB20 CAN_F2FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB2_FFDB21_Pos (21U) +#define CAN_F2FB2_FFDB21_Msk (0x1U << CAN_F2FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB2_FFDB21 CAN_F2FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB2_FFDB22_Pos (22U) +#define CAN_F2FB2_FFDB22_Msk (0x1U << CAN_F2FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB2_FFDB22 CAN_F2FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB2_FFDB23_Pos (23U) +#define CAN_F2FB2_FFDB23_Msk (0x1U << CAN_F2FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB2_FFDB23 CAN_F2FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB2_FFDB24_Pos (24U) +#define CAN_F2FB2_FFDB24_Msk (0x1U << CAN_F2FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB2_FFDB24 CAN_F2FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB2_FFDB25_Pos (25U) +#define CAN_F2FB2_FFDB25_Msk (0x1U << CAN_F2FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB2_FFDB25 CAN_F2FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB2_FFDB26_Pos (26U) +#define CAN_F2FB2_FFDB26_Msk (0x1U << CAN_F2FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB2_FFDB26 CAN_F2FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB2_FFDB27_Pos (27U) +#define CAN_F2FB2_FFDB27_Msk (0x1U << CAN_F2FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB2_FFDB27 CAN_F2FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB2_FFDB28_Pos (28U) +#define CAN_F2FB2_FFDB28_Msk (0x1U << CAN_F2FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB2_FFDB28 CAN_F2FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB2_FFDB29_Pos (29U) +#define CAN_F2FB2_FFDB29_Msk (0x1U << CAN_F2FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB2_FFDB29 CAN_F2FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB2_FFDB30_Pos (30U) +#define CAN_F2FB2_FFDB30_Msk (0x1U << CAN_F2FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB2_FFDB30 CAN_F2FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB2_FFDB31_Pos (31U) +#define CAN_F2FB2_FFDB31_Msk (0x1U << CAN_F2FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB2_FFDB31 CAN_F2FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB2 register *******************/ +#define CAN_F3FB2_FFDB0_Pos (0U) +#define CAN_F3FB2_FFDB0_Msk (0x1U << CAN_F3FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB2_FFDB0 CAN_F3FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB2_FFDB1_Pos (1U) +#define CAN_F3FB2_FFDB1_Msk (0x1U << CAN_F3FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB2_FFDB1 CAN_F3FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB2_FFDB2_Pos (2U) +#define CAN_F3FB2_FFDB2_Msk (0x1U << CAN_F3FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB2_FFDB2 CAN_F3FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB2_FFDB3_Pos (3U) +#define CAN_F3FB2_FFDB3_Msk (0x1U << CAN_F3FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB2_FFDB3 CAN_F3FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB2_FFDB4_Pos (4U) +#define CAN_F3FB2_FFDB4_Msk (0x1U << CAN_F3FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB2_FFDB4 CAN_F3FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB2_FFDB5_Pos (5U) +#define CAN_F3FB2_FFDB5_Msk (0x1U << CAN_F3FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB2_FFDB5 CAN_F3FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB2_FFDB6_Pos (6U) +#define CAN_F3FB2_FFDB6_Msk (0x1U << CAN_F3FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB2_FFDB6 CAN_F3FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB2_FFDB7_Pos (7U) +#define CAN_F3FB2_FFDB7_Msk (0x1U << CAN_F3FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB2_FFDB7 CAN_F3FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB2_FFDB8_Pos (8U) +#define CAN_F3FB2_FFDB8_Msk (0x1U << CAN_F3FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB2_FFDB8 CAN_F3FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB2_FFDB9_Pos (9U) +#define CAN_F3FB2_FFDB9_Msk (0x1U << CAN_F3FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB2_FFDB9 CAN_F3FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB2_FFDB10_Pos (10U) +#define CAN_F3FB2_FFDB10_Msk (0x1U << CAN_F3FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB2_FFDB10 CAN_F3FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB2_FFDB11_Pos (11U) +#define CAN_F3FB2_FFDB11_Msk (0x1U << CAN_F3FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB2_FFDB11 CAN_F3FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB2_FFDB12_Pos (12U) +#define CAN_F3FB2_FFDB12_Msk (0x1U << CAN_F3FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB2_FFDB12 CAN_F3FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB2_FFDB13_Pos (13U) +#define CAN_F3FB2_FFDB13_Msk (0x1U << CAN_F3FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB2_FFDB13 CAN_F3FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB2_FFDB14_Pos (14U) +#define CAN_F3FB2_FFDB14_Msk (0x1U << CAN_F3FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB2_FFDB14 CAN_F3FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB2_FFDB15_Pos (15U) +#define CAN_F3FB2_FFDB15_Msk (0x1U << CAN_F3FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB2_FFDB15 CAN_F3FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB2_FFDB16_Pos (16U) +#define CAN_F3FB2_FFDB16_Msk (0x1U << CAN_F3FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB2_FFDB16 CAN_F3FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB2_FFDB17_Pos (17U) +#define CAN_F3FB2_FFDB17_Msk (0x1U << CAN_F3FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB2_FFDB17 CAN_F3FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB2_FFDB18_Pos (18U) +#define CAN_F3FB2_FFDB18_Msk (0x1U << CAN_F3FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB2_FFDB18 CAN_F3FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB2_FFDB19_Pos (19U) +#define CAN_F3FB2_FFDB19_Msk (0x1U << CAN_F3FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB2_FFDB19 CAN_F3FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB2_FFDB20_Pos (20U) +#define CAN_F3FB2_FFDB20_Msk (0x1U << CAN_F3FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB2_FFDB20 CAN_F3FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB2_FFDB21_Pos (21U) +#define CAN_F3FB2_FFDB21_Msk (0x1U << CAN_F3FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB2_FFDB21 CAN_F3FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB2_FFDB22_Pos (22U) +#define CAN_F3FB2_FFDB22_Msk (0x1U << CAN_F3FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB2_FFDB22 CAN_F3FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB2_FFDB23_Pos (23U) +#define CAN_F3FB2_FFDB23_Msk (0x1U << CAN_F3FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB2_FFDB23 CAN_F3FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB2_FFDB24_Pos (24U) +#define CAN_F3FB2_FFDB24_Msk (0x1U << CAN_F3FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB2_FFDB24 CAN_F3FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB2_FFDB25_Pos (25U) +#define CAN_F3FB2_FFDB25_Msk (0x1U << CAN_F3FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB2_FFDB25 CAN_F3FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB2_FFDB26_Pos (26U) +#define CAN_F3FB2_FFDB26_Msk (0x1U << CAN_F3FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB2_FFDB26 CAN_F3FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB2_FFDB27_Pos (27U) +#define CAN_F3FB2_FFDB27_Msk (0x1U << CAN_F3FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB2_FFDB27 CAN_F3FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB2_FFDB28_Pos (28U) +#define CAN_F3FB2_FFDB28_Msk (0x1U << CAN_F3FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB2_FFDB28 CAN_F3FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB2_FFDB29_Pos (29U) +#define CAN_F3FB2_FFDB29_Msk (0x1U << CAN_F3FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB2_FFDB29 CAN_F3FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB2_FFDB30_Pos (30U) +#define CAN_F3FB2_FFDB30_Msk (0x1U << CAN_F3FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB2_FFDB30 CAN_F3FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB2_FFDB31_Pos (31U) +#define CAN_F3FB2_FFDB31_Msk (0x1U << CAN_F3FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB2_FFDB31 CAN_F3FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB2 register *******************/ +#define CAN_F4FB2_FFDB0_Pos (0U) +#define CAN_F4FB2_FFDB0_Msk (0x1U << CAN_F4FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB2_FFDB0 CAN_F4FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB2_FFDB1_Pos (1U) +#define CAN_F4FB2_FFDB1_Msk (0x1U << CAN_F4FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB2_FFDB1 CAN_F4FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB2_FFDB2_Pos (2U) +#define CAN_F4FB2_FFDB2_Msk (0x1U << CAN_F4FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB2_FFDB2 CAN_F4FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB2_FFDB3_Pos (3U) +#define CAN_F4FB2_FFDB3_Msk (0x1U << CAN_F4FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB2_FFDB3 CAN_F4FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB2_FFDB4_Pos (4U) +#define CAN_F4FB2_FFDB4_Msk (0x1U << CAN_F4FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB2_FFDB4 CAN_F4FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB2_FFDB5_Pos (5U) +#define CAN_F4FB2_FFDB5_Msk (0x1U << CAN_F4FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB2_FFDB5 CAN_F4FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB2_FFDB6_Pos (6U) +#define CAN_F4FB2_FFDB6_Msk (0x1U << CAN_F4FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB2_FFDB6 CAN_F4FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB2_FFDB7_Pos (7U) +#define CAN_F4FB2_FFDB7_Msk (0x1U << CAN_F4FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB2_FFDB7 CAN_F4FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB2_FFDB8_Pos (8U) +#define CAN_F4FB2_FFDB8_Msk (0x1U << CAN_F4FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB2_FFDB8 CAN_F4FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB2_FFDB9_Pos (9U) +#define CAN_F4FB2_FFDB9_Msk (0x1U << CAN_F4FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB2_FFDB9 CAN_F4FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB2_FFDB10_Pos (10U) +#define CAN_F4FB2_FFDB10_Msk (0x1U << CAN_F4FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB2_FFDB10 CAN_F4FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB2_FFDB11_Pos (11U) +#define CAN_F4FB2_FFDB11_Msk (0x1U << CAN_F4FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB2_FFDB11 CAN_F4FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB2_FFDB12_Pos (12U) +#define CAN_F4FB2_FFDB12_Msk (0x1U << CAN_F4FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB2_FFDB12 CAN_F4FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB2_FFDB13_Pos (13U) +#define CAN_F4FB2_FFDB13_Msk (0x1U << CAN_F4FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB2_FFDB13 CAN_F4FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB2_FFDB14_Pos (14U) +#define CAN_F4FB2_FFDB14_Msk (0x1U << CAN_F4FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB2_FFDB14 CAN_F4FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB2_FFDB15_Pos (15U) +#define CAN_F4FB2_FFDB15_Msk (0x1U << CAN_F4FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB2_FFDB15 CAN_F4FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB2_FFDB16_Pos (16U) +#define CAN_F4FB2_FFDB16_Msk (0x1U << CAN_F4FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB2_FFDB16 CAN_F4FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB2_FFDB17_Pos (17U) +#define CAN_F4FB2_FFDB17_Msk (0x1U << CAN_F4FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB2_FFDB17 CAN_F4FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB2_FFDB18_Pos (18U) +#define CAN_F4FB2_FFDB18_Msk (0x1U << CAN_F4FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB2_FFDB18 CAN_F4FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB2_FFDB19_Pos (19U) +#define CAN_F4FB2_FFDB19_Msk (0x1U << CAN_F4FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB2_FFDB19 CAN_F4FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB2_FFDB20_Pos (20U) +#define CAN_F4FB2_FFDB20_Msk (0x1U << CAN_F4FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB2_FFDB20 CAN_F4FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB2_FFDB21_Pos (21U) +#define CAN_F4FB2_FFDB21_Msk (0x1U << CAN_F4FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB2_FFDB21 CAN_F4FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB2_FFDB22_Pos (22U) +#define CAN_F4FB2_FFDB22_Msk (0x1U << CAN_F4FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB2_FFDB22 CAN_F4FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB2_FFDB23_Pos (23U) +#define CAN_F4FB2_FFDB23_Msk (0x1U << CAN_F4FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB2_FFDB23 CAN_F4FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB2_FFDB24_Pos (24U) +#define CAN_F4FB2_FFDB24_Msk (0x1U << CAN_F4FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB2_FFDB24 CAN_F4FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB2_FFDB25_Pos (25U) +#define CAN_F4FB2_FFDB25_Msk (0x1U << CAN_F4FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB2_FFDB25 CAN_F4FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB2_FFDB26_Pos (26U) +#define CAN_F4FB2_FFDB26_Msk (0x1U << CAN_F4FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB2_FFDB26 CAN_F4FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB2_FFDB27_Pos (27U) +#define CAN_F4FB2_FFDB27_Msk (0x1U << CAN_F4FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB2_FFDB27 CAN_F4FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB2_FFDB28_Pos (28U) +#define CAN_F4FB2_FFDB28_Msk (0x1U << CAN_F4FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB2_FFDB28 CAN_F4FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB2_FFDB29_Pos (29U) +#define CAN_F4FB2_FFDB29_Msk (0x1U << CAN_F4FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB2_FFDB29 CAN_F4FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB2_FFDB30_Pos (30U) +#define CAN_F4FB2_FFDB30_Msk (0x1U << CAN_F4FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB2_FFDB30 CAN_F4FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB2_FFDB31_Pos (31U) +#define CAN_F4FB2_FFDB31_Msk (0x1U << CAN_F4FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB2_FFDB31 CAN_F4FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB2 register *******************/ +#define CAN_F5FB2_FFDB0_Pos (0U) +#define CAN_F5FB2_FFDB0_Msk (0x1U << CAN_F5FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB2_FFDB0 CAN_F5FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB2_FFDB1_Pos (1U) +#define CAN_F5FB2_FFDB1_Msk (0x1U << CAN_F5FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB2_FFDB1 CAN_F5FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB2_FFDB2_Pos (2U) +#define CAN_F5FB2_FFDB2_Msk (0x1U << CAN_F5FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB2_FFDB2 CAN_F5FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB2_FFDB3_Pos (3U) +#define CAN_F5FB2_FFDB3_Msk (0x1U << CAN_F5FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB2_FFDB3 CAN_F5FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB2_FFDB4_Pos (4U) +#define CAN_F5FB2_FFDB4_Msk (0x1U << CAN_F5FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB2_FFDB4 CAN_F5FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB2_FFDB5_Pos (5U) +#define CAN_F5FB2_FFDB5_Msk (0x1U << CAN_F5FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB2_FFDB5 CAN_F5FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB2_FFDB6_Pos (6U) +#define CAN_F5FB2_FFDB6_Msk (0x1U << CAN_F5FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB2_FFDB6 CAN_F5FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB2_FFDB7_Pos (7U) +#define CAN_F5FB2_FFDB7_Msk (0x1U << CAN_F5FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB2_FFDB7 CAN_F5FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB2_FFDB8_Pos (8U) +#define CAN_F5FB2_FFDB8_Msk (0x1U << CAN_F5FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB2_FFDB8 CAN_F5FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB2_FFDB9_Pos (9U) +#define CAN_F5FB2_FFDB9_Msk (0x1U << CAN_F5FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB2_FFDB9 CAN_F5FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB2_FFDB10_Pos (10U) +#define CAN_F5FB2_FFDB10_Msk (0x1U << CAN_F5FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB2_FFDB10 CAN_F5FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB2_FFDB11_Pos (11U) +#define CAN_F5FB2_FFDB11_Msk (0x1U << CAN_F5FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB2_FFDB11 CAN_F5FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB2_FFDB12_Pos (12U) +#define CAN_F5FB2_FFDB12_Msk (0x1U << CAN_F5FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB2_FFDB12 CAN_F5FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB2_FFDB13_Pos (13U) +#define CAN_F5FB2_FFDB13_Msk (0x1U << CAN_F5FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB2_FFDB13 CAN_F5FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB2_FFDB14_Pos (14U) +#define CAN_F5FB2_FFDB14_Msk (0x1U << CAN_F5FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB2_FFDB14 CAN_F5FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB2_FFDB15_Pos (15U) +#define CAN_F5FB2_FFDB15_Msk (0x1U << CAN_F5FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB2_FFDB15 CAN_F5FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB2_FFDB16_Pos (16U) +#define CAN_F5FB2_FFDB16_Msk (0x1U << CAN_F5FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB2_FFDB16 CAN_F5FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB2_FFDB17_Pos (17U) +#define CAN_F5FB2_FFDB17_Msk (0x1U << CAN_F5FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB2_FFDB17 CAN_F5FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB2_FFDB18_Pos (18U) +#define CAN_F5FB2_FFDB18_Msk (0x1U << CAN_F5FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB2_FFDB18 CAN_F5FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB2_FFDB19_Pos (19U) +#define CAN_F5FB2_FFDB19_Msk (0x1U << CAN_F5FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB2_FFDB19 CAN_F5FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB2_FFDB20_Pos (20U) +#define CAN_F5FB2_FFDB20_Msk (0x1U << CAN_F5FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB2_FFDB20 CAN_F5FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB2_FFDB21_Pos (21U) +#define CAN_F5FB2_FFDB21_Msk (0x1U << CAN_F5FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB2_FFDB21 CAN_F5FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB2_FFDB22_Pos (22U) +#define CAN_F5FB2_FFDB22_Msk (0x1U << CAN_F5FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB2_FFDB22 CAN_F5FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB2_FFDB23_Pos (23U) +#define CAN_F5FB2_FFDB23_Msk (0x1U << CAN_F5FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB2_FFDB23 CAN_F5FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB2_FFDB24_Pos (24U) +#define CAN_F5FB2_FFDB24_Msk (0x1U << CAN_F5FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB2_FFDB24 CAN_F5FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB2_FFDB25_Pos (25U) +#define CAN_F5FB2_FFDB25_Msk (0x1U << CAN_F5FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB2_FFDB25 CAN_F5FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB2_FFDB26_Pos (26U) +#define CAN_F5FB2_FFDB26_Msk (0x1U << CAN_F5FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB2_FFDB26 CAN_F5FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB2_FFDB27_Pos (27U) +#define CAN_F5FB2_FFDB27_Msk (0x1U << CAN_F5FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB2_FFDB27 CAN_F5FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB2_FFDB28_Pos (28U) +#define CAN_F5FB2_FFDB28_Msk (0x1U << CAN_F5FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB2_FFDB28 CAN_F5FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB2_FFDB29_Pos (29U) +#define CAN_F5FB2_FFDB29_Msk (0x1U << CAN_F5FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB2_FFDB29 CAN_F5FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB2_FFDB30_Pos (30U) +#define CAN_F5FB2_FFDB30_Msk (0x1U << CAN_F5FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB2_FFDB30 CAN_F5FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB2_FFDB31_Pos (31U) +#define CAN_F5FB2_FFDB31_Msk (0x1U << CAN_F5FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB2_FFDB31 CAN_F5FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB2 register *******************/ +#define CAN_F6FB2_FFDB0_Pos (0U) +#define CAN_F6FB2_FFDB0_Msk (0x1U << CAN_F6FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB2_FFDB0 CAN_F6FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB2_FFDB1_Pos (1U) +#define CAN_F6FB2_FFDB1_Msk (0x1U << CAN_F6FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB2_FFDB1 CAN_F6FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB2_FFDB2_Pos (2U) +#define CAN_F6FB2_FFDB2_Msk (0x1U << CAN_F6FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB2_FFDB2 CAN_F6FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB2_FFDB3_Pos (3U) +#define CAN_F6FB2_FFDB3_Msk (0x1U << CAN_F6FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB2_FFDB3 CAN_F6FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB2_FFDB4_Pos (4U) +#define CAN_F6FB2_FFDB4_Msk (0x1U << CAN_F6FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB2_FFDB4 CAN_F6FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB2_FFDB5_Pos (5U) +#define CAN_F6FB2_FFDB5_Msk (0x1U << CAN_F6FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB2_FFDB5 CAN_F6FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB2_FFDB6_Pos (6U) +#define CAN_F6FB2_FFDB6_Msk (0x1U << CAN_F6FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB2_FFDB6 CAN_F6FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB2_FFDB7_Pos (7U) +#define CAN_F6FB2_FFDB7_Msk (0x1U << CAN_F6FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB2_FFDB7 CAN_F6FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB2_FFDB8_Pos (8U) +#define CAN_F6FB2_FFDB8_Msk (0x1U << CAN_F6FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB2_FFDB8 CAN_F6FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB2_FFDB9_Pos (9U) +#define CAN_F6FB2_FFDB9_Msk (0x1U << CAN_F6FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB2_FFDB9 CAN_F6FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB2_FFDB10_Pos (10U) +#define CAN_F6FB2_FFDB10_Msk (0x1U << CAN_F6FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB2_FFDB10 CAN_F6FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB2_FFDB11_Pos (11U) +#define CAN_F6FB2_FFDB11_Msk (0x1U << CAN_F6FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB2_FFDB11 CAN_F6FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB2_FFDB12_Pos (12U) +#define CAN_F6FB2_FFDB12_Msk (0x1U << CAN_F6FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB2_FFDB12 CAN_F6FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB2_FFDB13_Pos (13U) +#define CAN_F6FB2_FFDB13_Msk (0x1U << CAN_F6FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB2_FFDB13 CAN_F6FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB2_FFDB14_Pos (14U) +#define CAN_F6FB2_FFDB14_Msk (0x1U << CAN_F6FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB2_FFDB14 CAN_F6FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB2_FFDB15_Pos (15U) +#define CAN_F6FB2_FFDB15_Msk (0x1U << CAN_F6FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB2_FFDB15 CAN_F6FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB2_FFDB16_Pos (16U) +#define CAN_F6FB2_FFDB16_Msk (0x1U << CAN_F6FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB2_FFDB16 CAN_F6FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB2_FFDB17_Pos (17U) +#define CAN_F6FB2_FFDB17_Msk (0x1U << CAN_F6FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB2_FFDB17 CAN_F6FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB2_FFDB18_Pos (18U) +#define CAN_F6FB2_FFDB18_Msk (0x1U << CAN_F6FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB2_FFDB18 CAN_F6FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB2_FFDB19_Pos (19U) +#define CAN_F6FB2_FFDB19_Msk (0x1U << CAN_F6FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB2_FFDB19 CAN_F6FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB2_FFDB20_Pos (20U) +#define CAN_F6FB2_FFDB20_Msk (0x1U << CAN_F6FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB2_FFDB20 CAN_F6FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB2_FFDB21_Pos (21U) +#define CAN_F6FB2_FFDB21_Msk (0x1U << CAN_F6FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB2_FFDB21 CAN_F6FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB2_FFDB22_Pos (22U) +#define CAN_F6FB2_FFDB22_Msk (0x1U << CAN_F6FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB2_FFDB22 CAN_F6FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB2_FFDB23_Pos (23U) +#define CAN_F6FB2_FFDB23_Msk (0x1U << CAN_F6FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB2_FFDB23 CAN_F6FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB2_FFDB24_Pos (24U) +#define CAN_F6FB2_FFDB24_Msk (0x1U << CAN_F6FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB2_FFDB24 CAN_F6FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB2_FFDB25_Pos (25U) +#define CAN_F6FB2_FFDB25_Msk (0x1U << CAN_F6FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB2_FFDB25 CAN_F6FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB2_FFDB26_Pos (26U) +#define CAN_F6FB2_FFDB26_Msk (0x1U << CAN_F6FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB2_FFDB26 CAN_F6FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB2_FFDB27_Pos (27U) +#define CAN_F6FB2_FFDB27_Msk (0x1U << CAN_F6FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB2_FFDB27 CAN_F6FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB2_FFDB28_Pos (28U) +#define CAN_F6FB2_FFDB28_Msk (0x1U << CAN_F6FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB2_FFDB28 CAN_F6FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB2_FFDB29_Pos (29U) +#define CAN_F6FB2_FFDB29_Msk (0x1U << CAN_F6FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB2_FFDB29 CAN_F6FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB2_FFDB30_Pos (30U) +#define CAN_F6FB2_FFDB30_Msk (0x1U << CAN_F6FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB2_FFDB30 CAN_F6FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB2_FFDB31_Pos (31U) +#define CAN_F6FB2_FFDB31_Msk (0x1U << CAN_F6FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB2_FFDB31 CAN_F6FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB2 register *******************/ +#define CAN_F7FB2_FFDB0_Pos (0U) +#define CAN_F7FB2_FFDB0_Msk (0x1U << CAN_F7FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB2_FFDB0 CAN_F7FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB2_FFDB1_Pos (1U) +#define CAN_F7FB2_FFDB1_Msk (0x1U << CAN_F7FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB2_FFDB1 CAN_F7FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB2_FFDB2_Pos (2U) +#define CAN_F7FB2_FFDB2_Msk (0x1U << CAN_F7FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB2_FFDB2 CAN_F7FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB2_FFDB3_Pos (3U) +#define CAN_F7FB2_FFDB3_Msk (0x1U << CAN_F7FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB2_FFDB3 CAN_F7FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB2_FFDB4_Pos (4U) +#define CAN_F7FB2_FFDB4_Msk (0x1U << CAN_F7FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB2_FFDB4 CAN_F7FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB2_FFDB5_Pos (5U) +#define CAN_F7FB2_FFDB5_Msk (0x1U << CAN_F7FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB2_FFDB5 CAN_F7FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB2_FFDB6_Pos (6U) +#define CAN_F7FB2_FFDB6_Msk (0x1U << CAN_F7FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB2_FFDB6 CAN_F7FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB2_FFDB7_Pos (7U) +#define CAN_F7FB2_FFDB7_Msk (0x1U << CAN_F7FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB2_FFDB7 CAN_F7FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB2_FFDB8_Pos (8U) +#define CAN_F7FB2_FFDB8_Msk (0x1U << CAN_F7FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB2_FFDB8 CAN_F7FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB2_FFDB9_Pos (9U) +#define CAN_F7FB2_FFDB9_Msk (0x1U << CAN_F7FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB2_FFDB9 CAN_F7FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB2_FFDB10_Pos (10U) +#define CAN_F7FB2_FFDB10_Msk (0x1U << CAN_F7FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB2_FFDB10 CAN_F7FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB2_FFDB11_Pos (11U) +#define CAN_F7FB2_FFDB11_Msk (0x1U << CAN_F7FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB2_FFDB11 CAN_F7FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB2_FFDB12_Pos (12U) +#define CAN_F7FB2_FFDB12_Msk (0x1U << CAN_F7FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB2_FFDB12 CAN_F7FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB2_FFDB13_Pos (13U) +#define CAN_F7FB2_FFDB13_Msk (0x1U << CAN_F7FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB2_FFDB13 CAN_F7FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB2_FFDB14_Pos (14U) +#define CAN_F7FB2_FFDB14_Msk (0x1U << CAN_F7FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB2_FFDB14 CAN_F7FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB2_FFDB15_Pos (15U) +#define CAN_F7FB2_FFDB15_Msk (0x1U << CAN_F7FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB2_FFDB15 CAN_F7FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB2_FFDB16_Pos (16U) +#define CAN_F7FB2_FFDB16_Msk (0x1U << CAN_F7FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB2_FFDB16 CAN_F7FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB2_FFDB17_Pos (17U) +#define CAN_F7FB2_FFDB17_Msk (0x1U << CAN_F7FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB2_FFDB17 CAN_F7FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB2_FFDB18_Pos (18U) +#define CAN_F7FB2_FFDB18_Msk (0x1U << CAN_F7FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB2_FFDB18 CAN_F7FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB2_FFDB19_Pos (19U) +#define CAN_F7FB2_FFDB19_Msk (0x1U << CAN_F7FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB2_FFDB19 CAN_F7FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB2_FFDB20_Pos (20U) +#define CAN_F7FB2_FFDB20_Msk (0x1U << CAN_F7FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB2_FFDB20 CAN_F7FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB2_FFDB21_Pos (21U) +#define CAN_F7FB2_FFDB21_Msk (0x1U << CAN_F7FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB2_FFDB21 CAN_F7FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB2_FFDB22_Pos (22U) +#define CAN_F7FB2_FFDB22_Msk (0x1U << CAN_F7FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB2_FFDB22 CAN_F7FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB2_FFDB23_Pos (23U) +#define CAN_F7FB2_FFDB23_Msk (0x1U << CAN_F7FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB2_FFDB23 CAN_F7FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB2_FFDB24_Pos (24U) +#define CAN_F7FB2_FFDB24_Msk (0x1U << CAN_F7FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB2_FFDB24 CAN_F7FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB2_FFDB25_Pos (25U) +#define CAN_F7FB2_FFDB25_Msk (0x1U << CAN_F7FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB2_FFDB25 CAN_F7FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB2_FFDB26_Pos (26U) +#define CAN_F7FB2_FFDB26_Msk (0x1U << CAN_F7FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB2_FFDB26 CAN_F7FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB2_FFDB27_Pos (27U) +#define CAN_F7FB2_FFDB27_Msk (0x1U << CAN_F7FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB2_FFDB27 CAN_F7FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB2_FFDB28_Pos (28U) +#define CAN_F7FB2_FFDB28_Msk (0x1U << CAN_F7FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB2_FFDB28 CAN_F7FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB2_FFDB29_Pos (29U) +#define CAN_F7FB2_FFDB29_Msk (0x1U << CAN_F7FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB2_FFDB29 CAN_F7FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB2_FFDB30_Pos (30U) +#define CAN_F7FB2_FFDB30_Msk (0x1U << CAN_F7FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB2_FFDB30 CAN_F7FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB2_FFDB31_Pos (31U) +#define CAN_F7FB2_FFDB31_Msk (0x1U << CAN_F7FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB2_FFDB31 CAN_F7FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB2 register *******************/ +#define CAN_F8FB2_FFDB0_Pos (0U) +#define CAN_F8FB2_FFDB0_Msk (0x1U << CAN_F8FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB2_FFDB0 CAN_F8FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB2_FFDB1_Pos (1U) +#define CAN_F8FB2_FFDB1_Msk (0x1U << CAN_F8FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB2_FFDB1 CAN_F8FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB2_FFDB2_Pos (2U) +#define CAN_F8FB2_FFDB2_Msk (0x1U << CAN_F8FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB2_FFDB2 CAN_F8FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB2_FFDB3_Pos (3U) +#define CAN_F8FB2_FFDB3_Msk (0x1U << CAN_F8FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB2_FFDB3 CAN_F8FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB2_FFDB4_Pos (4U) +#define CAN_F8FB2_FFDB4_Msk (0x1U << CAN_F8FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB2_FFDB4 CAN_F8FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB2_FFDB5_Pos (5U) +#define CAN_F8FB2_FFDB5_Msk (0x1U << CAN_F8FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB2_FFDB5 CAN_F8FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB2_FFDB6_Pos (6U) +#define CAN_F8FB2_FFDB6_Msk (0x1U << CAN_F8FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB2_FFDB6 CAN_F8FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB2_FFDB7_Pos (7U) +#define CAN_F8FB2_FFDB7_Msk (0x1U << CAN_F8FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB2_FFDB7 CAN_F8FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB2_FFDB8_Pos (8U) +#define CAN_F8FB2_FFDB8_Msk (0x1U << CAN_F8FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB2_FFDB8 CAN_F8FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB2_FFDB9_Pos (9U) +#define CAN_F8FB2_FFDB9_Msk (0x1U << CAN_F8FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB2_FFDB9 CAN_F8FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB2_FFDB10_Pos (10U) +#define CAN_F8FB2_FFDB10_Msk (0x1U << CAN_F8FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB2_FFDB10 CAN_F8FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB2_FFDB11_Pos (11U) +#define CAN_F8FB2_FFDB11_Msk (0x1U << CAN_F8FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB2_FFDB11 CAN_F8FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB2_FFDB12_Pos (12U) +#define CAN_F8FB2_FFDB12_Msk (0x1U << CAN_F8FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB2_FFDB12 CAN_F8FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB2_FFDB13_Pos (13U) +#define CAN_F8FB2_FFDB13_Msk (0x1U << CAN_F8FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB2_FFDB13 CAN_F8FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB2_FFDB14_Pos (14U) +#define CAN_F8FB2_FFDB14_Msk (0x1U << CAN_F8FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB2_FFDB14 CAN_F8FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB2_FFDB15_Pos (15U) +#define CAN_F8FB2_FFDB15_Msk (0x1U << CAN_F8FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB2_FFDB15 CAN_F8FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB2_FFDB16_Pos (16U) +#define CAN_F8FB2_FFDB16_Msk (0x1U << CAN_F8FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB2_FFDB16 CAN_F8FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB2_FFDB17_Pos (17U) +#define CAN_F8FB2_FFDB17_Msk (0x1U << CAN_F8FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB2_FFDB17 CAN_F8FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB2_FFDB18_Pos (18U) +#define CAN_F8FB2_FFDB18_Msk (0x1U << CAN_F8FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB2_FFDB18 CAN_F8FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB2_FFDB19_Pos (19U) +#define CAN_F8FB2_FFDB19_Msk (0x1U << CAN_F8FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB2_FFDB19 CAN_F8FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB2_FFDB20_Pos (20U) +#define CAN_F8FB2_FFDB20_Msk (0x1U << CAN_F8FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB2_FFDB20 CAN_F8FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB2_FFDB21_Pos (21U) +#define CAN_F8FB2_FFDB21_Msk (0x1U << CAN_F8FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB2_FFDB21 CAN_F8FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB2_FFDB22_Pos (22U) +#define CAN_F8FB2_FFDB22_Msk (0x1U << CAN_F8FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB2_FFDB22 CAN_F8FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB2_FFDB23_Pos (23U) +#define CAN_F8FB2_FFDB23_Msk (0x1U << CAN_F8FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB2_FFDB23 CAN_F8FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB2_FFDB24_Pos (24U) +#define CAN_F8FB2_FFDB24_Msk (0x1U << CAN_F8FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB2_FFDB24 CAN_F8FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB2_FFDB25_Pos (25U) +#define CAN_F8FB2_FFDB25_Msk (0x1U << CAN_F8FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB2_FFDB25 CAN_F8FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB2_FFDB26_Pos (26U) +#define CAN_F8FB2_FFDB26_Msk (0x1U << CAN_F8FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB2_FFDB26 CAN_F8FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB2_FFDB27_Pos (27U) +#define CAN_F8FB2_FFDB27_Msk (0x1U << CAN_F8FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB2_FFDB27 CAN_F8FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB2_FFDB28_Pos (28U) +#define CAN_F8FB2_FFDB28_Msk (0x1U << CAN_F8FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB2_FFDB28 CAN_F8FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB2_FFDB29_Pos (29U) +#define CAN_F8FB2_FFDB29_Msk (0x1U << CAN_F8FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB2_FFDB29 CAN_F8FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB2_FFDB30_Pos (30U) +#define CAN_F8FB2_FFDB30_Msk (0x1U << CAN_F8FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB2_FFDB30 CAN_F8FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB2_FFDB31_Pos (31U) +#define CAN_F8FB2_FFDB31_Msk (0x1U << CAN_F8FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB2_FFDB31 CAN_F8FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB2 register *******************/ +#define CAN_F9FB2_FFDB0_Pos (0U) +#define CAN_F9FB2_FFDB0_Msk (0x1U << CAN_F9FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB2_FFDB0 CAN_F9FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB2_FFDB1_Pos (1U) +#define CAN_F9FB2_FFDB1_Msk (0x1U << CAN_F9FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB2_FFDB1 CAN_F9FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB2_FFDB2_Pos (2U) +#define CAN_F9FB2_FFDB2_Msk (0x1U << CAN_F9FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB2_FFDB2 CAN_F9FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB2_FFDB3_Pos (3U) +#define CAN_F9FB2_FFDB3_Msk (0x1U << CAN_F9FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB2_FFDB3 CAN_F9FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB2_FFDB4_Pos (4U) +#define CAN_F9FB2_FFDB4_Msk (0x1U << CAN_F9FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB2_FFDB4 CAN_F9FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB2_FFDB5_Pos (5U) +#define CAN_F9FB2_FFDB5_Msk (0x1U << CAN_F9FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB2_FFDB5 CAN_F9FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB2_FFDB6_Pos (6U) +#define CAN_F9FB2_FFDB6_Msk (0x1U << CAN_F9FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB2_FFDB6 CAN_F9FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB2_FFDB7_Pos (7U) +#define CAN_F9FB2_FFDB7_Msk (0x1U << CAN_F9FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB2_FFDB7 CAN_F9FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB2_FFDB8_Pos (8U) +#define CAN_F9FB2_FFDB8_Msk (0x1U << CAN_F9FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB2_FFDB8 CAN_F9FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB2_FFDB9_Pos (9U) +#define CAN_F9FB2_FFDB9_Msk (0x1U << CAN_F9FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB2_FFDB9 CAN_F9FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB2_FFDB10_Pos (10U) +#define CAN_F9FB2_FFDB10_Msk (0x1U << CAN_F9FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB2_FFDB10 CAN_F9FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB2_FFDB11_Pos (11U) +#define CAN_F9FB2_FFDB11_Msk (0x1U << CAN_F9FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB2_FFDB11 CAN_F9FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB2_FFDB12_Pos (12U) +#define CAN_F9FB2_FFDB12_Msk (0x1U << CAN_F9FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB2_FFDB12 CAN_F9FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB2_FFDB13_Pos (13U) +#define CAN_F9FB2_FFDB13_Msk (0x1U << CAN_F9FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB2_FFDB13 CAN_F9FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB2_FFDB14_Pos (14U) +#define CAN_F9FB2_FFDB14_Msk (0x1U << CAN_F9FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB2_FFDB14 CAN_F9FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB2_FFDB15_Pos (15U) +#define CAN_F9FB2_FFDB15_Msk (0x1U << CAN_F9FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB2_FFDB15 CAN_F9FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB2_FFDB16_Pos (16U) +#define CAN_F9FB2_FFDB16_Msk (0x1U << CAN_F9FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB2_FFDB16 CAN_F9FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB2_FFDB17_Pos (17U) +#define CAN_F9FB2_FFDB17_Msk (0x1U << CAN_F9FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB2_FFDB17 CAN_F9FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB2_FFDB18_Pos (18U) +#define CAN_F9FB2_FFDB18_Msk (0x1U << CAN_F9FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB2_FFDB18 CAN_F9FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB2_FFDB19_Pos (19U) +#define CAN_F9FB2_FFDB19_Msk (0x1U << CAN_F9FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB2_FFDB19 CAN_F9FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB2_FFDB20_Pos (20U) +#define CAN_F9FB2_FFDB20_Msk (0x1U << CAN_F9FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB2_FFDB20 CAN_F9FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB2_FFDB21_Pos (21U) +#define CAN_F9FB2_FFDB21_Msk (0x1U << CAN_F9FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB2_FFDB21 CAN_F9FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB2_FFDB22_Pos (22U) +#define CAN_F9FB2_FFDB22_Msk (0x1U << CAN_F9FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB2_FFDB22 CAN_F9FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB2_FFDB23_Pos (23U) +#define CAN_F9FB2_FFDB23_Msk (0x1U << CAN_F9FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB2_FFDB23 CAN_F9FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB2_FFDB24_Pos (24U) +#define CAN_F9FB2_FFDB24_Msk (0x1U << CAN_F9FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB2_FFDB24 CAN_F9FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB2_FFDB25_Pos (25U) +#define CAN_F9FB2_FFDB25_Msk (0x1U << CAN_F9FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB2_FFDB25 CAN_F9FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB2_FFDB26_Pos (26U) +#define CAN_F9FB2_FFDB26_Msk (0x1U << CAN_F9FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB2_FFDB26 CAN_F9FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB2_FFDB27_Pos (27U) +#define CAN_F9FB2_FFDB27_Msk (0x1U << CAN_F9FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB2_FFDB27 CAN_F9FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB2_FFDB28_Pos (28U) +#define CAN_F9FB2_FFDB28_Msk (0x1U << CAN_F9FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB2_FFDB28 CAN_F9FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB2_FFDB29_Pos (29U) +#define CAN_F9FB2_FFDB29_Msk (0x1U << CAN_F9FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB2_FFDB29 CAN_F9FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB2_FFDB30_Pos (30U) +#define CAN_F9FB2_FFDB30_Msk (0x1U << CAN_F9FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB2_FFDB30 CAN_F9FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB2_FFDB31_Pos (31U) +#define CAN_F9FB2_FFDB31_Msk (0x1U << CAN_F9FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB2_FFDB31 CAN_F9FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB2 register ******************/ +#define CAN_F10FB2_FFDB0_Pos (0U) +#define CAN_F10FB2_FFDB0_Msk (0x1U << CAN_F10FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB2_FFDB0 CAN_F10FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB2_FFDB1_Pos (1U) +#define CAN_F10FB2_FFDB1_Msk (0x1U << CAN_F10FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB2_FFDB1 CAN_F10FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB2_FFDB2_Pos (2U) +#define CAN_F10FB2_FFDB2_Msk (0x1U << CAN_F10FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB2_FFDB2 CAN_F10FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB2_FFDB3_Pos (3U) +#define CAN_F10FB2_FFDB3_Msk (0x1U << CAN_F10FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB2_FFDB3 CAN_F10FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB2_FFDB4_Pos (4U) +#define CAN_F10FB2_FFDB4_Msk (0x1U << CAN_F10FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB2_FFDB4 CAN_F10FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB2_FFDB5_Pos (5U) +#define CAN_F10FB2_FFDB5_Msk (0x1U << CAN_F10FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB2_FFDB5 CAN_F10FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB2_FFDB6_Pos (6U) +#define CAN_F10FB2_FFDB6_Msk (0x1U << CAN_F10FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB2_FFDB6 CAN_F10FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB2_FFDB7_Pos (7U) +#define CAN_F10FB2_FFDB7_Msk (0x1U << CAN_F10FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB2_FFDB7 CAN_F10FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB2_FFDB8_Pos (8U) +#define CAN_F10FB2_FFDB8_Msk (0x1U << CAN_F10FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB2_FFDB8 CAN_F10FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB2_FFDB9_Pos (9U) +#define CAN_F10FB2_FFDB9_Msk (0x1U << CAN_F10FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB2_FFDB9 CAN_F10FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB2_FFDB10_Pos (10U) +#define CAN_F10FB2_FFDB10_Msk (0x1U << CAN_F10FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB2_FFDB10 CAN_F10FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB2_FFDB11_Pos (11U) +#define CAN_F10FB2_FFDB11_Msk (0x1U << CAN_F10FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB2_FFDB11 CAN_F10FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB2_FFDB12_Pos (12U) +#define CAN_F10FB2_FFDB12_Msk (0x1U << CAN_F10FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB2_FFDB12 CAN_F10FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB2_FFDB13_Pos (13U) +#define CAN_F10FB2_FFDB13_Msk (0x1U << CAN_F10FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB2_FFDB13 CAN_F10FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB2_FFDB14_Pos (14U) +#define CAN_F10FB2_FFDB14_Msk (0x1U << CAN_F10FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB2_FFDB14 CAN_F10FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB2_FFDB15_Pos (15U) +#define CAN_F10FB2_FFDB15_Msk (0x1U << CAN_F10FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB2_FFDB15 CAN_F10FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB2_FFDB16_Pos (16U) +#define CAN_F10FB2_FFDB16_Msk (0x1U << CAN_F10FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB2_FFDB16 CAN_F10FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB2_FFDB17_Pos (17U) +#define CAN_F10FB2_FFDB17_Msk (0x1U << CAN_F10FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB2_FFDB17 CAN_F10FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB2_FFDB18_Pos (18U) +#define CAN_F10FB2_FFDB18_Msk (0x1U << CAN_F10FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB2_FFDB18 CAN_F10FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB2_FFDB19_Pos (19U) +#define CAN_F10FB2_FFDB19_Msk (0x1U << CAN_F10FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB2_FFDB19 CAN_F10FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB2_FFDB20_Pos (20U) +#define CAN_F10FB2_FFDB20_Msk (0x1U << CAN_F10FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB2_FFDB20 CAN_F10FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB2_FFDB21_Pos (21U) +#define CAN_F10FB2_FFDB21_Msk (0x1U << CAN_F10FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB2_FFDB21 CAN_F10FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB2_FFDB22_Pos (22U) +#define CAN_F10FB2_FFDB22_Msk (0x1U << CAN_F10FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB2_FFDB22 CAN_F10FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB2_FFDB23_Pos (23U) +#define CAN_F10FB2_FFDB23_Msk (0x1U << CAN_F10FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB2_FFDB23 CAN_F10FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB2_FFDB24_Pos (24U) +#define CAN_F10FB2_FFDB24_Msk (0x1U << CAN_F10FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB2_FFDB24 CAN_F10FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB2_FFDB25_Pos (25U) +#define CAN_F10FB2_FFDB25_Msk (0x1U << CAN_F10FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB2_FFDB25 CAN_F10FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB2_FFDB26_Pos (26U) +#define CAN_F10FB2_FFDB26_Msk (0x1U << CAN_F10FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB2_FFDB26 CAN_F10FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB2_FFDB27_Pos (27U) +#define CAN_F10FB2_FFDB27_Msk (0x1U << CAN_F10FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB2_FFDB27 CAN_F10FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB2_FFDB28_Pos (28U) +#define CAN_F10FB2_FFDB28_Msk (0x1U << CAN_F10FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB2_FFDB28 CAN_F10FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB2_FFDB29_Pos (29U) +#define CAN_F10FB2_FFDB29_Msk (0x1U << CAN_F10FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB2_FFDB29 CAN_F10FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB2_FFDB30_Pos (30U) +#define CAN_F10FB2_FFDB30_Msk (0x1U << CAN_F10FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB2_FFDB30 CAN_F10FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB2_FFDB31_Pos (31U) +#define CAN_F10FB2_FFDB31_Msk (0x1U << CAN_F10FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB2_FFDB31 CAN_F10FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB2 register ******************/ +#define CAN_F11FB2_FFDB0_Pos (0U) +#define CAN_F11FB2_FFDB0_Msk (0x1U << CAN_F11FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB2_FFDB0 CAN_F11FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB2_FFDB1_Pos (1U) +#define CAN_F11FB2_FFDB1_Msk (0x1U << CAN_F11FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB2_FFDB1 CAN_F11FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB2_FFDB2_Pos (2U) +#define CAN_F11FB2_FFDB2_Msk (0x1U << CAN_F11FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB2_FFDB2 CAN_F11FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB2_FFDB3_Pos (3U) +#define CAN_F11FB2_FFDB3_Msk (0x1U << CAN_F11FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB2_FFDB3 CAN_F11FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB2_FFDB4_Pos (4U) +#define CAN_F11FB2_FFDB4_Msk (0x1U << CAN_F11FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB2_FFDB4 CAN_F11FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB2_FFDB5_Pos (5U) +#define CAN_F11FB2_FFDB5_Msk (0x1U << CAN_F11FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB2_FFDB5 CAN_F11FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB2_FFDB6_Pos (6U) +#define CAN_F11FB2_FFDB6_Msk (0x1U << CAN_F11FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB2_FFDB6 CAN_F11FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB2_FFDB7_Pos (7U) +#define CAN_F11FB2_FFDB7_Msk (0x1U << CAN_F11FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB2_FFDB7 CAN_F11FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB2_FFDB8_Pos (8U) +#define CAN_F11FB2_FFDB8_Msk (0x1U << CAN_F11FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB2_FFDB8 CAN_F11FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB2_FFDB9_Pos (9U) +#define CAN_F11FB2_FFDB9_Msk (0x1U << CAN_F11FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB2_FFDB9 CAN_F11FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB2_FFDB10_Pos (10U) +#define CAN_F11FB2_FFDB10_Msk (0x1U << CAN_F11FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB2_FFDB10 CAN_F11FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB2_FFDB11_Pos (11U) +#define CAN_F11FB2_FFDB11_Msk (0x1U << CAN_F11FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB2_FFDB11 CAN_F11FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB2_FFDB12_Pos (12U) +#define CAN_F11FB2_FFDB12_Msk (0x1U << CAN_F11FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB2_FFDB12 CAN_F11FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB2_FFDB13_Pos (13U) +#define CAN_F11FB2_FFDB13_Msk (0x1U << CAN_F11FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB2_FFDB13 CAN_F11FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB2_FFDB14_Pos (14U) +#define CAN_F11FB2_FFDB14_Msk (0x1U << CAN_F11FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB2_FFDB14 CAN_F11FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB2_FFDB15_Pos (15U) +#define CAN_F11FB2_FFDB15_Msk (0x1U << CAN_F11FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB2_FFDB15 CAN_F11FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB2_FFDB16_Pos (16U) +#define CAN_F11FB2_FFDB16_Msk (0x1U << CAN_F11FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB2_FFDB16 CAN_F11FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB2_FFDB17_Pos (17U) +#define CAN_F11FB2_FFDB17_Msk (0x1U << CAN_F11FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB2_FFDB17 CAN_F11FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB2_FFDB18_Pos (18U) +#define CAN_F11FB2_FFDB18_Msk (0x1U << CAN_F11FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB2_FFDB18 CAN_F11FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB2_FFDB19_Pos (19U) +#define CAN_F11FB2_FFDB19_Msk (0x1U << CAN_F11FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB2_FFDB19 CAN_F11FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB2_FFDB20_Pos (20U) +#define CAN_F11FB2_FFDB20_Msk (0x1U << CAN_F11FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB2_FFDB20 CAN_F11FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB2_FFDB21_Pos (21U) +#define CAN_F11FB2_FFDB21_Msk (0x1U << CAN_F11FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB2_FFDB21 CAN_F11FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB2_FFDB22_Pos (22U) +#define CAN_F11FB2_FFDB22_Msk (0x1U << CAN_F11FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB2_FFDB22 CAN_F11FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB2_FFDB23_Pos (23U) +#define CAN_F11FB2_FFDB23_Msk (0x1U << CAN_F11FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB2_FFDB23 CAN_F11FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB2_FFDB24_Pos (24U) +#define CAN_F11FB2_FFDB24_Msk (0x1U << CAN_F11FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB2_FFDB24 CAN_F11FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB2_FFDB25_Pos (25U) +#define CAN_F11FB2_FFDB25_Msk (0x1U << CAN_F11FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB2_FFDB25 CAN_F11FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB2_FFDB26_Pos (26U) +#define CAN_F11FB2_FFDB26_Msk (0x1U << CAN_F11FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB2_FFDB26 CAN_F11FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB2_FFDB27_Pos (27U) +#define CAN_F11FB2_FFDB27_Msk (0x1U << CAN_F11FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB2_FFDB27 CAN_F11FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB2_FFDB28_Pos (28U) +#define CAN_F11FB2_FFDB28_Msk (0x1U << CAN_F11FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB2_FFDB28 CAN_F11FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB2_FFDB29_Pos (29U) +#define CAN_F11FB2_FFDB29_Msk (0x1U << CAN_F11FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB2_FFDB29 CAN_F11FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB2_FFDB30_Pos (30U) +#define CAN_F11FB2_FFDB30_Msk (0x1U << CAN_F11FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB2_FFDB30 CAN_F11FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB2_FFDB31_Pos (31U) +#define CAN_F11FB2_FFDB31_Msk (0x1U << CAN_F11FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB2_FFDB31 CAN_F11FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB2 register ******************/ +#define CAN_F12FB2_FFDB0_Pos (0U) +#define CAN_F12FB2_FFDB0_Msk (0x1U << CAN_F12FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB2_FFDB0 CAN_F12FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB2_FFDB1_Pos (1U) +#define CAN_F12FB2_FFDB1_Msk (0x1U << CAN_F12FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB2_FFDB1 CAN_F12FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB2_FFDB2_Pos (2U) +#define CAN_F12FB2_FFDB2_Msk (0x1U << CAN_F12FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB2_FFDB2 CAN_F12FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB2_FFDB3_Pos (3U) +#define CAN_F12FB2_FFDB3_Msk (0x1U << CAN_F12FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB2_FFDB3 CAN_F12FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB2_FFDB4_Pos (4U) +#define CAN_F12FB2_FFDB4_Msk (0x1U << CAN_F12FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB2_FFDB4 CAN_F12FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB2_FFDB5_Pos (5U) +#define CAN_F12FB2_FFDB5_Msk (0x1U << CAN_F12FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB2_FFDB5 CAN_F12FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB2_FFDB6_Pos (6U) +#define CAN_F12FB2_FFDB6_Msk (0x1U << CAN_F12FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB2_FFDB6 CAN_F12FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB2_FFDB7_Pos (7U) +#define CAN_F12FB2_FFDB7_Msk (0x1U << CAN_F12FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB2_FFDB7 CAN_F12FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB2_FFDB8_Pos (8U) +#define CAN_F12FB2_FFDB8_Msk (0x1U << CAN_F12FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB2_FFDB8 CAN_F12FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB2_FFDB9_Pos (9U) +#define CAN_F12FB2_FFDB9_Msk (0x1U << CAN_F12FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB2_FFDB9 CAN_F12FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB2_FFDB10_Pos (10U) +#define CAN_F12FB2_FFDB10_Msk (0x1U << CAN_F12FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB2_FFDB10 CAN_F12FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB2_FFDB11_Pos (11U) +#define CAN_F12FB2_FFDB11_Msk (0x1U << CAN_F12FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB2_FFDB11 CAN_F12FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB2_FFDB12_Pos (12U) +#define CAN_F12FB2_FFDB12_Msk (0x1U << CAN_F12FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB2_FFDB12 CAN_F12FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB2_FFDB13_Pos (13U) +#define CAN_F12FB2_FFDB13_Msk (0x1U << CAN_F12FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB2_FFDB13 CAN_F12FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB2_FFDB14_Pos (14U) +#define CAN_F12FB2_FFDB14_Msk (0x1U << CAN_F12FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB2_FFDB14 CAN_F12FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB2_FFDB15_Pos (15U) +#define CAN_F12FB2_FFDB15_Msk (0x1U << CAN_F12FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB2_FFDB15 CAN_F12FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB2_FFDB16_Pos (16U) +#define CAN_F12FB2_FFDB16_Msk (0x1U << CAN_F12FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB2_FFDB16 CAN_F12FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB2_FFDB17_Pos (17U) +#define CAN_F12FB2_FFDB17_Msk (0x1U << CAN_F12FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB2_FFDB17 CAN_F12FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB2_FFDB18_Pos (18U) +#define CAN_F12FB2_FFDB18_Msk (0x1U << CAN_F12FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB2_FFDB18 CAN_F12FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB2_FFDB19_Pos (19U) +#define CAN_F12FB2_FFDB19_Msk (0x1U << CAN_F12FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB2_FFDB19 CAN_F12FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB2_FFDB20_Pos (20U) +#define CAN_F12FB2_FFDB20_Msk (0x1U << CAN_F12FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB2_FFDB20 CAN_F12FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB2_FFDB21_Pos (21U) +#define CAN_F12FB2_FFDB21_Msk (0x1U << CAN_F12FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB2_FFDB21 CAN_F12FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB2_FFDB22_Pos (22U) +#define CAN_F12FB2_FFDB22_Msk (0x1U << CAN_F12FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB2_FFDB22 CAN_F12FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB2_FFDB23_Pos (23U) +#define CAN_F12FB2_FFDB23_Msk (0x1U << CAN_F12FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB2_FFDB23 CAN_F12FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB2_FFDB24_Pos (24U) +#define CAN_F12FB2_FFDB24_Msk (0x1U << CAN_F12FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB2_FFDB24 CAN_F12FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB2_FFDB25_Pos (25U) +#define CAN_F12FB2_FFDB25_Msk (0x1U << CAN_F12FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB2_FFDB25 CAN_F12FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB2_FFDB26_Pos (26U) +#define CAN_F12FB2_FFDB26_Msk (0x1U << CAN_F12FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB2_FFDB26 CAN_F12FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB2_FFDB27_Pos (27U) +#define CAN_F12FB2_FFDB27_Msk (0x1U << CAN_F12FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB2_FFDB27 CAN_F12FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB2_FFDB28_Pos (28U) +#define CAN_F12FB2_FFDB28_Msk (0x1U << CAN_F12FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB2_FFDB28 CAN_F12FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB2_FFDB29_Pos (29U) +#define CAN_F12FB2_FFDB29_Msk (0x1U << CAN_F12FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB2_FFDB29 CAN_F12FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB2_FFDB30_Pos (30U) +#define CAN_F12FB2_FFDB30_Msk (0x1U << CAN_F12FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB2_FFDB30 CAN_F12FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB2_FFDB31_Pos (31U) +#define CAN_F12FB2_FFDB31_Msk (0x1U << CAN_F12FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB2_FFDB31 CAN_F12FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB2 register ******************/ +#define CAN_F13FB2_FFDB0_Pos (0U) +#define CAN_F13FB2_FFDB0_Msk (0x1U << CAN_F13FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB2_FFDB0 CAN_F13FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB2_FFDB1_Pos (1U) +#define CAN_F13FB2_FFDB1_Msk (0x1U << CAN_F13FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB2_FFDB1 CAN_F13FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB2_FFDB2_Pos (2U) +#define CAN_F13FB2_FFDB2_Msk (0x1U << CAN_F13FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB2_FFDB2 CAN_F13FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB2_FFDB3_Pos (3U) +#define CAN_F13FB2_FFDB3_Msk (0x1U << CAN_F13FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB2_FFDB3 CAN_F13FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB2_FFDB4_Pos (4U) +#define CAN_F13FB2_FFDB4_Msk (0x1U << CAN_F13FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB2_FFDB4 CAN_F13FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB2_FFDB5_Pos (5U) +#define CAN_F13FB2_FFDB5_Msk (0x1U << CAN_F13FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB2_FFDB5 CAN_F13FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB2_FFDB6_Pos (6U) +#define CAN_F13FB2_FFDB6_Msk (0x1U << CAN_F13FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB2_FFDB6 CAN_F13FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB2_FFDB7_Pos (7U) +#define CAN_F13FB2_FFDB7_Msk (0x1U << CAN_F13FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB2_FFDB7 CAN_F13FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB2_FFDB8_Pos (8U) +#define CAN_F13FB2_FFDB8_Msk (0x1U << CAN_F13FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB2_FFDB8 CAN_F13FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB2_FFDB9_Pos (9U) +#define CAN_F13FB2_FFDB9_Msk (0x1U << CAN_F13FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB2_FFDB9 CAN_F13FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB2_FFDB10_Pos (10U) +#define CAN_F13FB2_FFDB10_Msk (0x1U << CAN_F13FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB2_FFDB10 CAN_F13FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB2_FFDB11_Pos (11U) +#define CAN_F13FB2_FFDB11_Msk (0x1U << CAN_F13FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB2_FFDB11 CAN_F13FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB2_FFDB12_Pos (12U) +#define CAN_F13FB2_FFDB12_Msk (0x1U << CAN_F13FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB2_FFDB12 CAN_F13FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB2_FFDB13_Pos (13U) +#define CAN_F13FB2_FFDB13_Msk (0x1U << CAN_F13FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB2_FFDB13 CAN_F13FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB2_FFDB14_Pos (14U) +#define CAN_F13FB2_FFDB14_Msk (0x1U << CAN_F13FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB2_FFDB14 CAN_F13FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB2_FFDB15_Pos (15U) +#define CAN_F13FB2_FFDB15_Msk (0x1U << CAN_F13FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB2_FFDB15 CAN_F13FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB2_FFDB16_Pos (16U) +#define CAN_F13FB2_FFDB16_Msk (0x1U << CAN_F13FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB2_FFDB16 CAN_F13FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB2_FFDB17_Pos (17U) +#define CAN_F13FB2_FFDB17_Msk (0x1U << CAN_F13FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB2_FFDB17 CAN_F13FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB2_FFDB18_Pos (18U) +#define CAN_F13FB2_FFDB18_Msk (0x1U << CAN_F13FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB2_FFDB18 CAN_F13FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB2_FFDB19_Pos (19U) +#define CAN_F13FB2_FFDB19_Msk (0x1U << CAN_F13FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB2_FFDB19 CAN_F13FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB2_FFDB20_Pos (20U) +#define CAN_F13FB2_FFDB20_Msk (0x1U << CAN_F13FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB2_FFDB20 CAN_F13FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB2_FFDB21_Pos (21U) +#define CAN_F13FB2_FFDB21_Msk (0x1U << CAN_F13FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB2_FFDB21 CAN_F13FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB2_FFDB22_Pos (22U) +#define CAN_F13FB2_FFDB22_Msk (0x1U << CAN_F13FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB2_FFDB22 CAN_F13FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB2_FFDB23_Pos (23U) +#define CAN_F13FB2_FFDB23_Msk (0x1U << CAN_F13FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB2_FFDB23 CAN_F13FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB2_FFDB24_Pos (24U) +#define CAN_F13FB2_FFDB24_Msk (0x1U << CAN_F13FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB2_FFDB24 CAN_F13FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB2_FFDB25_Pos (25U) +#define CAN_F13FB2_FFDB25_Msk (0x1U << CAN_F13FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB2_FFDB25 CAN_F13FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB2_FFDB26_Pos (26U) +#define CAN_F13FB2_FFDB26_Msk (0x1U << CAN_F13FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB2_FFDB26 CAN_F13FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB2_FFDB27_Pos (27U) +#define CAN_F13FB2_FFDB27_Msk (0x1U << CAN_F13FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB2_FFDB27 CAN_F13FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB2_FFDB28_Pos (28U) +#define CAN_F13FB2_FFDB28_Msk (0x1U << CAN_F13FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB2_FFDB28 CAN_F13FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB2_FFDB29_Pos (29U) +#define CAN_F13FB2_FFDB29_Msk (0x1U << CAN_F13FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB2_FFDB29 CAN_F13FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB2_FFDB30_Pos (30U) +#define CAN_F13FB2_FFDB30_Msk (0x1U << CAN_F13FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB2_FFDB30 CAN_F13FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB2_FFDB31_Pos (31U) +#define CAN_F13FB2_FFDB31_Msk (0x1U << CAN_F13FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB2_FFDB31 CAN_F13FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/******************************************************************************/ +/* */ +/* SD/SDIO MMC card host interface (SDIO) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SDIO_PWRCTRL register *****************/ +#define SDIO_PWRCTRL_PS_Pos (0U) +#define SDIO_PWRCTRL_PS_Msk (0x3U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000003 */ +#define SDIO_PWRCTRL_PS SDIO_PWRCTRL_PS_Msk /*!< PS[1:0] bits (Power switch) */ +#define SDIO_PWRCTRL_PS_0 (0x1U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000001 */ +#define SDIO_PWRCTRL_PS_1 (0x2U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for SDIO_CLKCTRL register *****************/ +#define SDIO_CLKCTRL_CLKDIV_Msk ((0xFFU << 0) | (0x3U << 15)) /*!< 0x000180FF */ +#define SDIO_CLKCTRL_CLKDIV SDIO_CLKCTRL_CLKDIV_Msk /*!< CLKDIV[9:0] bits (Clock division) */ +#define SDIO_CLKCTRL_CLKOEN_Pos (8U) +#define SDIO_CLKCTRL_CLKOEN_Msk (0x1U << SDIO_CLKCTRL_CLKOEN_Pos) /*!< 0x00000100 */ +#define SDIO_CLKCTRL_CLKOEN SDIO_CLKCTRL_CLKOEN_Msk /*!< Clock output enable */ +#define SDIO_CLKCTRL_PWRSVEN_Pos (9U) +#define SDIO_CLKCTRL_PWRSVEN_Msk (0x1U << SDIO_CLKCTRL_PWRSVEN_Pos) /*!< 0x00000200 */ +#define SDIO_CLKCTRL_PWRSVEN SDIO_CLKCTRL_PWRSVEN_Msk /*!< Power saving mode enable */ +#define SDIO_CLKCTRL_BYPSEN_Pos (10U) +#define SDIO_CLKCTRL_BYPSEN_Msk (0x1U << SDIO_CLKCTRL_BYPSEN_Pos) /*!< 0x00000400 */ +#define SDIO_CLKCTRL_BYPSEN SDIO_CLKCTRL_BYPSEN_Msk /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCTRL_BUSWS_Pos (11U) +#define SDIO_CLKCTRL_BUSWS_Msk (0x3U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001800 */ +#define SDIO_CLKCTRL_BUSWS SDIO_CLKCTRL_BUSWS_Msk /*!< BUSWS[1:0] bits (Bus width selection) */ +#define SDIO_CLKCTRL_BUSWS_0 (0x1U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00000800 */ +#define SDIO_CLKCTRL_BUSWS_1 (0x2U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001000 */ + +#define SDIO_CLKCTRL_CLKEGS_Pos (13U) +#define SDIO_CLKCTRL_CLKEGS_Msk (0x1U << SDIO_CLKCTRL_CLKEGS_Pos) /*!< 0x00002000 */ +#define SDIO_CLKCTRL_CLKEGS SDIO_CLKCTRL_CLKEGS_Msk /*!< SDIO_CK edge selection */ +#define SDIO_CLKCTRL_HFCEN_Pos (14U) +#define SDIO_CLKCTRL_HFCEN_Msk (0x1U << SDIO_CLKCTRL_HFCEN_Pos) /*!< 0x00004000 */ +#define SDIO_CLKCTRL_HFCEN SDIO_CLKCTRL_HFCEN_Msk /*!< Hardware flow control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_ARGU_Pos (0U) +#define SDIO_ARG_ARGU_Msk (0xFFFFFFFFU << SDIO_ARG_ARGU_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_ARG_ARGU SDIO_ARG_ARGU_Msk /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDIDX_Pos (0U) +#define SDIO_CMD_CMDIDX_Msk (0x3FU << SDIO_CMD_CMDIDX_Pos) /*!< 0x0000003F */ +#define SDIO_CMD_CMDIDX SDIO_CMD_CMDIDX_Msk /*!< Command index */ + +#define SDIO_CMD_RSPWT_Pos (6U) +#define SDIO_CMD_RSPWT_Msk (0x3U << SDIO_CMD_RSPWT_Pos) /*!< 0x000000C0 */ +#define SDIO_CMD_RSPWT SDIO_CMD_RSPWT_Msk /*!< RSPWT[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_RSPWT_0 (0x1U << SDIO_CMD_RSPWT_Pos) /*!< 0x00000040 */ +#define SDIO_CMD_RSPWT_1 (0x2U << SDIO_CMD_RSPWT_Pos) /*!< 0x00000080 */ + +#define SDIO_CMD_INTWT_Pos (8U) +#define SDIO_CMD_INTWT_Msk (0x1U << SDIO_CMD_INTWT_Pos) /*!< 0x00000100 */ +#define SDIO_CMD_INTWT SDIO_CMD_INTWT_Msk /*!< CCSM waits for interrupt request */ +#define SDIO_CMD_PNDWT_Pos (9U) +#define SDIO_CMD_PNDWT_Msk (0x1U << SDIO_CMD_PNDWT_Pos) /*!< 0x00000200 */ +#define SDIO_CMD_PNDWT SDIO_CMD_PNDWT_Msk /*!< CCSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CCSMEN_Pos (10U) +#define SDIO_CMD_CCSMEN_Msk (0x1U << SDIO_CMD_CCSMEN_Pos) /*!< 0x00000400 */ +#define SDIO_CMD_CCSMEN SDIO_CMD_CCSMEN_Msk /*!< Command channel state machine (CCSM) enable bit */ +#define SDIO_CMD_IOSUSP_Pos (11U) +#define SDIO_CMD_IOSUSP_Msk (0x1U << SDIO_CMD_IOSUSP_Pos) /*!< 0x00000800 */ +#define SDIO_CMD_IOSUSP SDIO_CMD_IOSUSP_Msk /*!< SD I/O suspend command */ + +/***************** Bit definition for SDIO_RSPCMD register ******************/ +#define SDIO_RSPCMD_RSPCMD_Pos (0U) +#define SDIO_RSPCMD_RSPCMD_Msk (0x3FU << SDIO_RSPCMD_RSPCMD_Pos) /*!< 0x0000003F */ +#define SDIO_RSPCMD_RSPCMD SDIO_RSPCMD_RSPCMD_Msk /*!< Response command index */ + +/****************** Bit definition for SDIO_RSP1 register *******************/ +#define SDIO_RSP1_CARDSTS1_Pos (0U) +#define SDIO_RSP1_CARDSTS1_Msk (0xFFFFFFFFU << SDIO_RSP1_CARDSTS1_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP1_CARDSTS1 SDIO_RSP1_CARDSTS1_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP2 register *******************/ +#define SDIO_RSP2_CARDSTS2_Pos (0U) +#define SDIO_RSP2_CARDSTS2_Msk (0xFFFFFFFFU << SDIO_RSP2_CARDSTS2_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP2_CARDSTS2 SDIO_RSP2_CARDSTS2_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP3 register *******************/ +#define SDIO_RSP3_CARDSTS3_Pos (0U) +#define SDIO_RSP3_CARDSTS3_Msk (0xFFFFFFFFU << SDIO_RSP3_CARDSTS3_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP3_CARDSTS3 SDIO_RSP3_CARDSTS3_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP4 register *******************/ +#define SDIO_RSP4_CARDSTS4_Pos (0U) +#define SDIO_RSP4_CARDSTS4_Msk (0xFFFFFFFFU << SDIO_RSP4_CARDSTS4_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP4_CARDSTS4 SDIO_RSP4_CARDSTS4_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_DTTMR register ******************/ +#define SDIO_DTTMR_TIMEOUT_Pos (0U) +#define SDIO_DTTMR_TIMEOUT_Msk (0xFFFFFFFFU << SDIO_DTTMR_TIMEOUT_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_DTTMR_TIMEOUT SDIO_DTTMR_TIMEOUT_Msk /*!< Data timeout period */ + +/****************** Bit definition for SDIO_DTLEN register ******************/ +#define SDIO_DTLEN_DTLEN_Pos (0U) +#define SDIO_DTLEN_DTLEN_Msk (0x1FFFFFFU << SDIO_DTLEN_DTLEN_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DTLEN_DTLEN SDIO_DTLEN_DTLEN_Msk /*!< Data length value */ + +/***************** Bit definition for SDIO_DTCTRL register ******************/ +#define SDIO_DTCTRL_TFREN_Pos (0U) +#define SDIO_DTCTRL_TFREN_Msk (0x1U << SDIO_DTCTRL_TFREN_Pos) /*!< 0x00000001 */ +#define SDIO_DTCTRL_TFREN SDIO_DTCTRL_TFREN_Msk /*!< Data transfer enabled bit */ +#define SDIO_DTCTRL_TFRDIR_Pos (1U) +#define SDIO_DTCTRL_TFRDIR_Msk (0x1U << SDIO_DTCTRL_TFRDIR_Pos) /*!< 0x00000002 */ +#define SDIO_DTCTRL_TFRDIR SDIO_DTCTRL_TFRDIR_Msk /*!< Data transfer direction selection */ +#define SDIO_DTCTRL_TFRMODE_Pos (2U) +#define SDIO_DTCTRL_TFRMODE_Msk (0x1U << SDIO_DTCTRL_TFRMODE_Pos) /*!< 0x00000004 */ +#define SDIO_DTCTRL_TFRMODE SDIO_DTCTRL_TFRMODE_Msk /*!< Data transfer mode selection */ +#define SDIO_DTCTRL_DMAEN_Pos (3U) +#define SDIO_DTCTRL_DMAEN_Msk (0x1U << SDIO_DTCTRL_DMAEN_Pos) /*!< 0x00000008 */ +#define SDIO_DTCTRL_DMAEN SDIO_DTCTRL_DMAEN_Msk /*!< DMA enable bit */ + +#define SDIO_DTCTRL_BLKSIZE_Pos (4U) +#define SDIO_DTCTRL_BLKSIZE_Msk (0xFU << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x000000F0 */ +#define SDIO_DTCTRL_BLKSIZE SDIO_DTCTRL_BLKSIZE_Msk /*!< BLKSIZE[3:0] bits (Data block size) */ +#define SDIO_DTCTRL_BLKSIZE_0 (0x1U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000010 */ +#define SDIO_DTCTRL_BLKSIZE_1 (0x2U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000020 */ +#define SDIO_DTCTRL_BLKSIZE_2 (0x4U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000040 */ +#define SDIO_DTCTRL_BLKSIZE_3 (0x8U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000080 */ + +#define SDIO_DTCTRL_RDWTSTART_Pos (8U) +#define SDIO_DTCTRL_RDWTSTART_Msk (0x1U << SDIO_DTCTRL_RDWTSTART_Pos) /*!< 0x00000100 */ +#define SDIO_DTCTRL_RDWTSTART SDIO_DTCTRL_RDWTSTART_Msk /*!< Read wait start */ +#define SDIO_DTCTRL_RDWTSTOP_Pos (9U) +#define SDIO_DTCTRL_RDWTSTOP_Msk (0x1U << SDIO_DTCTRL_RDWTSTOP_Pos) /*!< 0x00000200 */ +#define SDIO_DTCTRL_RDWTSTOP SDIO_DTCTRL_RDWTSTOP_Msk /*!< Read wait stop */ +#define SDIO_DTCTRL_RDWTMODE_Pos (10U) +#define SDIO_DTCTRL_RDWTMODE_Msk (0x1U << SDIO_DTCTRL_RDWTMODE_Pos) /*!< 0x00000400 */ +#define SDIO_DTCTRL_RDWTMODE SDIO_DTCTRL_RDWTMODE_Msk /*!< Read wait mode */ +#define SDIO_DTCTRL_IOEN_Pos (11U) +#define SDIO_DTCTRL_IOEN_Msk (0x1U << SDIO_DTCTRL_IOEN_Pos) /*!< 0x00000800 */ +#define SDIO_DTCTRL_IOEN SDIO_DTCTRL_IOEN_Msk /*!< SD I/O enable functions */ + +/***************** Bit definition for SDIO_DTCNTR register ******************/ +#define SDIO_DTCNTR_CNT_Pos (0U) +#define SDIO_DTCNTR_CNT_Msk (0x1FFFFFFU << SDIO_DTCNTR_CNT_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DTCNTR_CNT SDIO_DTCNTR_CNT_Msk /*!< Data count value */ + +/******************* Bit definition for SDIO_STS register *******************/ +#define SDIO_STS_CMDFAIL_Pos (0U) +#define SDIO_STS_CMDFAIL_Msk (0x1U << SDIO_STS_CMDFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_STS_CMDFAIL SDIO_STS_CMDFAIL_Msk /*!< Command response received (CRC check failed) */ +#define SDIO_STS_DTFAIL_Pos (1U) +#define SDIO_STS_DTFAIL_Msk (0x1U << SDIO_STS_DTFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_STS_DTFAIL SDIO_STS_DTFAIL_Msk /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STS_CMDTIMEOUT_Pos (2U) +#define SDIO_STS_CMDTIMEOUT_Msk (0x1U << SDIO_STS_CMDTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_STS_CMDTIMEOUT SDIO_STS_CMDTIMEOUT_Msk /*!< Command response timeout */ +#define SDIO_STS_DTTIMEOUT_Pos (3U) +#define SDIO_STS_DTTIMEOUT_Msk (0x1U << SDIO_STS_DTTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_STS_DTTIMEOUT SDIO_STS_DTTIMEOUT_Msk /*!< Data timeout */ +#define SDIO_STS_TXERRU_Pos (4U) +#define SDIO_STS_TXERRU_Msk (0x1U << SDIO_STS_TXERRU_Pos) /*!< 0x00000010 */ +#define SDIO_STS_TXERRU SDIO_STS_TXERRU_Msk /*!< Transmit BUF underrun error */ +#define SDIO_STS_RXERRO_Pos (5U) +#define SDIO_STS_RXERRO_Msk (0x1U << SDIO_STS_RXERRO_Pos) /*!< 0x00000020 */ +#define SDIO_STS_RXERRO SDIO_STS_RXERRO_Msk /*!< Received BUF overrun error */ +#define SDIO_STS_CMDRSPCMPL_Pos (6U) +#define SDIO_STS_CMDRSPCMPL_Msk (0x1U << SDIO_STS_CMDRSPCMPL_Pos) /*!< 0x00000040 */ +#define SDIO_STS_CMDRSPCMPL SDIO_STS_CMDRSPCMPL_Msk /*!< Command response (CRC check passed) */ +#define SDIO_STS_CMDCMPL_Pos (7U) +#define SDIO_STS_CMDCMPL_Msk (0x1U << SDIO_STS_CMDCMPL_Pos) /*!< 0x00000080 */ +#define SDIO_STS_CMDCMPL SDIO_STS_CMDCMPL_Msk /*!< Command sent (no response required) */ +#define SDIO_STS_DTCMPL_Pos (8U) +#define SDIO_STS_DTCMPL_Msk (0x1U << SDIO_STS_DTCMPL_Pos) /*!< 0x00000100 */ +#define SDIO_STS_DTCMPL SDIO_STS_DTCMPL_Msk /*!< Data end (data counter, SDIO CNT, is zero) */ +#define SDIO_STS_SBITERR_Pos (9U) +#define SDIO_STS_SBITERR_Msk (0x1U << SDIO_STS_SBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_STS_SBITERR SDIO_STS_SBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STS_DTBLKCMPL_Pos (10U) +#define SDIO_STS_DTBLKCMPL_Msk (0x1U << SDIO_STS_DTBLKCMPL_Pos) /*!< 0x00000400 */ +#define SDIO_STS_DTBLKCMPL SDIO_STS_DTBLKCMPL_Msk /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STS_DOCMD_Pos (11U) +#define SDIO_STS_DOCMD_Msk (0x1U << SDIO_STS_DOCMD_Pos) /*!< 0x00000800 */ +#define SDIO_STS_DOCMD SDIO_STS_DOCMD_Msk /*!< Command transfer in progress */ +#define SDIO_STS_DOTX_Pos (12U) +#define SDIO_STS_DOTX_Msk (0x1U << SDIO_STS_DOTX_Pos) /*!< 0x00001000 */ +#define SDIO_STS_DOTX SDIO_STS_DOTX_Msk /*!< Data transmit in progress */ +#define SDIO_STS_DORX_Pos (13U) +#define SDIO_STS_DORX_Msk (0x1U << SDIO_STS_DORX_Pos) /*!< 0x00002000 */ +#define SDIO_STS_DORX SDIO_STS_DORX_Msk /*!< Data receive in progress */ +#define SDIO_STS_TXBUFH_Pos (14U) +#define SDIO_STS_TXBUFH_Msk (0x1U << SDIO_STS_TXBUFH_Pos) /*!< 0x00004000 */ +#define SDIO_STS_TXBUFH SDIO_STS_TXBUFH_Msk /*!< Transmit BUF half empty: At least 8 words can be written to the BUF */ +#define SDIO_STS_RXBUFH_Pos (15U) +#define SDIO_STS_RXBUFH_Msk (0x1U << SDIO_STS_RXBUFH_Pos) /*!< 0x00008000 */ +#define SDIO_STS_RXBUFH SDIO_STS_RXBUFH_Msk /*!< Receive BUF half full: There are at least 8 words in the BUF */ +#define SDIO_STS_TXBUFF_Pos (16U) +#define SDIO_STS_TXBUFF_Msk (0x1U << SDIO_STS_TXBUFF_Pos) /*!< 0x00010000 */ +#define SDIO_STS_TXBUFF SDIO_STS_TXBUFF_Msk /*!< Transmit BUF full */ +#define SDIO_STS_RXBUFF_Pos (17U) +#define SDIO_STS_RXBUFF_Msk (0x1U << SDIO_STS_RXBUFF_Pos) /*!< 0x00020000 */ +#define SDIO_STS_RXBUFF SDIO_STS_RXBUFF_Msk /*!< Receive BUF full */ +#define SDIO_STS_TXBUFE_Pos (18U) +#define SDIO_STS_TXBUFE_Msk (0x1U << SDIO_STS_TXBUFE_Pos) /*!< 0x00040000 */ +#define SDIO_STS_TXBUFE SDIO_STS_TXBUFE_Msk /*!< Transmit BUF empty */ +#define SDIO_STS_RXBUFE_Pos (19U) +#define SDIO_STS_RXBUFE_Msk (0x1U << SDIO_STS_RXBUFE_Pos) /*!< 0x00080000 */ +#define SDIO_STS_RXBUFE SDIO_STS_RXBUFE_Msk /*!< Receive BUF empty */ +#define SDIO_STS_TXBUF_Pos (20U) +#define SDIO_STS_TXBUF_Msk (0x1U << SDIO_STS_TXBUF_Pos) /*!< 0x00100000 */ +#define SDIO_STS_TXBUF SDIO_STS_TXBUF_Msk /*!< Data available in transmit BUF */ +#define SDIO_STS_RXBUF_Pos (21U) +#define SDIO_STS_RXBUF_Msk (0x1U << SDIO_STS_RXBUF_Pos) /*!< 0x00200000 */ +#define SDIO_STS_RXBUF SDIO_STS_RXBUF_Msk /*!< Data available in receive BUF */ +#define SDIO_STS_IOIF_Pos (22U) +#define SDIO_STS_IOIF_Msk (0x1U << SDIO_STS_IOIF_Pos) /*!< 0x00400000 */ +#define SDIO_STS_IOIF SDIO_STS_IOIF_Msk /*!< SD I/O interrupt received */ + +/***************** Bit definition for SDIO_INTCLR register ******************/ +#define SDIO_INTCLR_CMDFAIL_Pos (0U) +#define SDIO_INTCLR_CMDFAIL_Msk (0x1U << SDIO_INTCLR_CMDFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_INTCLR_CMDFAIL SDIO_INTCLR_CMDFAIL_Msk /*!< CMDFAIL flag clear bit */ +#define SDIO_INTCLR_DTFAIL_Pos (1U) +#define SDIO_INTCLR_DTFAIL_Msk (0x1U << SDIO_INTCLR_DTFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_INTCLR_DTFAIL SDIO_INTCLR_DTFAIL_Msk /*!< DTFAIL flag clear bit */ +#define SDIO_INTCLR_CMDTIMEOUT_Pos (2U) +#define SDIO_INTCLR_CMDTIMEOUT_Msk (0x1U << SDIO_INTCLR_CMDTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_INTCLR_CMDTIMEOUT SDIO_INTCLR_CMDTIMEOUT_Msk /*!< CMDTIMEOUT flag clear bit */ +#define SDIO_INTCLR_DTTIMEOUT_Pos (3U) +#define SDIO_INTCLR_DTTIMEOUT_Msk (0x1U << SDIO_INTCLR_DTTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_INTCLR_DTTIMEOUT SDIO_INTCLR_DTTIMEOUT_Msk /*!< DTTIMEOUT flag clear bit */ +#define SDIO_INTCLR_TXERRU_Pos (4U) +#define SDIO_INTCLR_TXERRU_Msk (0x1U << SDIO_INTCLR_TXERRU_Pos) /*!< 0x00000010 */ +#define SDIO_INTCLR_TXERRU SDIO_INTCLR_TXERRU_Msk /*!< TXERRU flag clear bit */ +#define SDIO_INTCLR_RXERRO_Pos (5U) +#define SDIO_INTCLR_RXERRO_Msk (0x1U << SDIO_INTCLR_RXERRO_Pos) /*!< 0x00000020 */ +#define SDIO_INTCLR_RXERRO SDIO_INTCLR_RXERRO_Msk /*!< RXERRO flag clear bit */ +#define SDIO_INTCLR_CMDRSPCMPL_Pos (6U) +#define SDIO_INTCLR_CMDRSPCMPL_Msk (0x1U << SDIO_INTCLR_CMDRSPCMPL_Pos) /*!< 0x00000040 */ +#define SDIO_INTCLR_CMDRSPCMPL SDIO_INTCLR_CMDRSPCMPL_Msk /*!< CMDRSPCMPL flag clear bit */ +#define SDIO_INTCLR_CMDCMPL_Pos (7U) +#define SDIO_INTCLR_CMDCMPL_Msk (0x1U << SDIO_INTCLR_CMDCMPL_Pos) /*!< 0x00000080 */ +#define SDIO_INTCLR_CMDCMPL SDIO_INTCLR_CMDCMPL_Msk /*!< CMDCMPL flag clear bit */ +#define SDIO_INTCLR_DTCMPL_Pos (8U) +#define SDIO_INTCLR_DTCMPL_Msk (0x1U << SDIO_INTCLR_DTCMPL_Pos) /*!< 0x00000100 */ +#define SDIO_INTCLR_DTCMPL SDIO_INTCLR_DTCMPL_Msk /*!< DTCMPL flag clear bit */ +#define SDIO_INTCLR_SBITERR_Pos (9U) +#define SDIO_INTCLR_SBITERR_Msk (0x1U << SDIO_INTCLR_SBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_INTCLR_SBITERR SDIO_INTCLR_SBITERR_Msk /*!< SBITERR flag clear bit */ +#define SDIO_INTCLR_DTBLKCMPL_Pos (10U) +#define SDIO_INTCLR_DTBLKCMPL_Msk (0x1U << SDIO_INTCLR_DTBLKCMPL_Pos) /*!< 0x00000400 */ +#define SDIO_INTCLR_DTBLKCMPL SDIO_INTCLR_DTBLKCMPL_Msk /*!< DTBLKCMPL flag clear bit */ +#define SDIO_INTCLR_IOIF_Pos (22U) +#define SDIO_INTCLR_IOIF_Msk (0x1U << SDIO_INTCLR_IOIF_Pos) /*!< 0x00400000 */ +#define SDIO_INTCLR_IOIF SDIO_INTCLR_IOIF_Msk /*!< SD I/O interface flag clear bit */ + +/****************** Bit definition for SDIO_INTEN register ******************/ +#define SDIO_INTEN_CMDFAILIEN_Pos (0U) +#define SDIO_INTEN_CMDFAILIEN_Msk (0x1U << SDIO_INTEN_CMDFAILIEN_Pos) /*!< 0x00000001 */ +#define SDIO_INTEN_CMDFAILIEN SDIO_INTEN_CMDFAILIEN_Msk /*!< Command CRC fail interrupt enable */ +#define SDIO_INTEN_DTFAILIEN_Pos (1U) +#define SDIO_INTEN_DTFAILIEN_Msk (0x1U << SDIO_INTEN_DTFAILIEN_Pos) /*!< 0x00000002 */ +#define SDIO_INTEN_DTFAILIEN SDIO_INTEN_DTFAILIEN_Msk /*!< Data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTIMEOUTIEN_Pos (2U) +#define SDIO_INTEN_CMDTIMEOUTIEN_Msk (0x1U << SDIO_INTEN_CMDTIMEOUTIEN_Pos) /*!< 0x00000004 */ +#define SDIO_INTEN_CMDTIMEOUTIEN SDIO_INTEN_CMDTIMEOUTIEN_Msk /*!< Command timeout interrupt enable */ +#define SDIO_INTEN_DTTIMEOUTIEN_Pos (3U) +#define SDIO_INTEN_DTTIMEOUTIEN_Msk (0x1U << SDIO_INTEN_DTTIMEOUTIEN_Pos) /*!< 0x00000008 */ +#define SDIO_INTEN_DTTIMEOUTIEN SDIO_INTEN_DTTIMEOUTIEN_Msk /*!< Data timeout interrupt enable */ +#define SDIO_INTEN_TXERRUIEN_Pos (4U) +#define SDIO_INTEN_TXERRUIEN_Msk (0x1U << SDIO_INTEN_TXERRUIEN_Pos) /*!< 0x00000010 */ +#define SDIO_INTEN_TXERRUIEN SDIO_INTEN_TXERRUIEN_Msk /*!< TxBUF underrun error interrupt enable */ +#define SDIO_INTEN_RXERROIEN_Pos (5U) +#define SDIO_INTEN_RXERROIEN_Msk (0x1U << SDIO_INTEN_RXERROIEN_Pos) /*!< 0x00000020 */ +#define SDIO_INTEN_RXERROIEN SDIO_INTEN_RXERROIEN_Msk /*!< RxBUF overrun error interrupt enable */ +#define SDIO_INTEN_CMDRSPCMPLIEN_Pos (6U) +#define SDIO_INTEN_CMDRSPCMPLIEN_Msk (0x1U << SDIO_INTEN_CMDRSPCMPLIEN_Pos) /*!< 0x00000040 */ +#define SDIO_INTEN_CMDRSPCMPLIEN SDIO_INTEN_CMDRSPCMPLIEN_Msk /*!< Command response received interrupt enable */ +#define SDIO_INTEN_CMDCMPLIEN_Pos (7U) +#define SDIO_INTEN_CMDCMPLIEN_Msk (0x1U << SDIO_INTEN_CMDCMPLIEN_Pos) /*!< 0x00000080 */ +#define SDIO_INTEN_CMDCMPLIEN SDIO_INTEN_CMDCMPLIEN_Msk /*!< Command sent interrupt enable */ +#define SDIO_INTEN_DTCMPLIEN_Pos (8U) +#define SDIO_INTEN_DTCMPLIEN_Msk (0x1U << SDIO_INTEN_DTCMPLIEN_Pos) /*!< 0x00000100 */ +#define SDIO_INTEN_DTCMPLIEN SDIO_INTEN_DTCMPLIEN_Msk /*!< Data end interrupt enable */ +#define SDIO_INTEN_SBITERRIEN_Pos (9U) +#define SDIO_INTEN_SBITERRIEN_Msk (0x1U << SDIO_INTEN_SBITERRIEN_Pos) /*!< 0x00000200 */ +#define SDIO_INTEN_SBITERRIEN SDIO_INTEN_SBITERRIEN_Msk /*!< Start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKCMPLIEN_Pos (10U) +#define SDIO_INTEN_DTBLKCMPLIEN_Msk (0x1U << SDIO_INTEN_DTBLKCMPLIEN_Pos) /*!< 0x00000400 */ +#define SDIO_INTEN_DTBLKCMPLIEN SDIO_INTEN_DTBLKCMPLIEN_Msk /*!< Data block end interrupt enable */ +#define SDIO_INTEN_DOCMDIEN_Pos (11U) +#define SDIO_INTEN_DOCMDIEN_Msk (0x1U << SDIO_INTEN_DOCMDIEN_Pos) /*!< 0x00000800 */ +#define SDIO_INTEN_DOCMDIEN SDIO_INTEN_DOCMDIEN_Msk /*!< Command acting interrupt enable */ +#define SDIO_INTEN_DOTXIEN_Pos (12U) +#define SDIO_INTEN_DOTXIEN_Msk (0x1U << SDIO_INTEN_DOTXIEN_Pos) /*!< 0x00001000 */ +#define SDIO_INTEN_DOTXIEN SDIO_INTEN_DOTXIEN_Msk /*!< Data transmit acting interrupt enable */ +#define SDIO_INTEN_DORXIEN_Pos (13U) +#define SDIO_INTEN_DORXIEN_Msk (0x1U << SDIO_INTEN_DORXIEN_Pos) /*!< 0x00002000 */ +#define SDIO_INTEN_DORXIEN SDIO_INTEN_DORXIEN_Msk /*!< Data receive acting interrupt enable */ +#define SDIO_INTEN_TXBUFHIEN_Pos (14U) +#define SDIO_INTEN_TXBUFHIEN_Msk (0x1U << SDIO_INTEN_TXBUFHIEN_Pos) /*!< 0x00004000 */ +#define SDIO_INTEN_TXBUFHIEN SDIO_INTEN_TXBUFHIEN_Msk /*!< TxBUF half empty interrupt enable */ +#define SDIO_INTEN_RXBUFHIEN_Pos (15U) +#define SDIO_INTEN_RXBUFHIEN_Msk (0x1U << SDIO_INTEN_RXBUFHIEN_Pos) /*!< 0x00008000 */ +#define SDIO_INTEN_RXBUFHIEN SDIO_INTEN_RXBUFHIEN_Msk /*!< RxBUF half full interrupt enable */ +#define SDIO_INTEN_TXBUFFIEN_Pos (16U) +#define SDIO_INTEN_TXBUFFIEN_Msk (0x1U << SDIO_INTEN_TXBUFFIEN_Pos) /*!< 0x00010000 */ +#define SDIO_INTEN_TXBUFFIEN SDIO_INTEN_TXBUFFIEN_Msk /*!< TxBUF full interrupt enable */ +#define SDIO_INTEN_RXBUFFIEN_Pos (17U) +#define SDIO_INTEN_RXBUFFIEN_Msk (0x1U << SDIO_INTEN_RXBUFFIEN_Pos) /*!< 0x00020000 */ +#define SDIO_INTEN_RXBUFFIEN SDIO_INTEN_RXBUFFIEN_Msk /*!< RxBUF full interrupt enable */ +#define SDIO_INTEN_TXBUFEIEN_Pos (18U) +#define SDIO_INTEN_TXBUFEIEN_Msk (0x1U << SDIO_INTEN_TXBUFEIEN_Pos) /*!< 0x00040000 */ +#define SDIO_INTEN_TXBUFEIEN SDIO_INTEN_TXBUFEIEN_Msk /*!< TxBUF empty interrupt enable */ +#define SDIO_INTEN_RXBUFEIEN_Pos (19U) +#define SDIO_INTEN_RXBUFEIEN_Msk (0x1U << SDIO_INTEN_RXBUFEIEN_Pos) /*!< 0x00080000 */ +#define SDIO_INTEN_RXBUFEIEN SDIO_INTEN_RXBUFEIEN_Msk /*!< RxBUF empty interrupt enable */ +#define SDIO_INTEN_TXBUFIEN_Pos (20U) +#define SDIO_INTEN_TXBUFIEN_Msk (0x1U << SDIO_INTEN_TXBUFIEN_Pos) /*!< 0x00100000 */ +#define SDIO_INTEN_TXBUFIEN SDIO_INTEN_TXBUFIEN_Msk /*!< Data available in TxBUF interrupt enable */ +#define SDIO_INTEN_RXBUFIEN_Pos (21U) +#define SDIO_INTEN_RXBUFIEN_Msk (0x1U << SDIO_INTEN_RXBUFIEN_Pos) /*!< 0x00200000 */ +#define SDIO_INTEN_RXBUFIEN SDIO_INTEN_RXBUFIEN_Msk /*!< Data available in RxBUF interrupt enable */ +#define SDIO_INTEN_IOIFIEN_Pos (22U) +#define SDIO_INTEN_IOIFIEN_Msk (0x1U << SDIO_INTEN_IOIFIEN_Pos) /*!< 0x00400000 */ +#define SDIO_INTEN_IOIFIEN SDIO_INTEN_IOIFIEN_Msk /*!< SD I/O mode received interrupt enable */ + +/***************** Bit definition for SDIO_BUFCNTR register ******************/ +#define SDIO_BUFCNTR_CNT_Pos (0U) +#define SDIO_BUFCNTR_CNT_Msk (0xFFFFFFU << SDIO_BUFCNTR_CNT_Pos) /*!< 0x00FFFFFF */ +#define SDIO_BUFCNTR_CNT SDIO_BUFCNTR_CNT_Msk /*!< Number of words to be written to or read from the BUF */ + +/******************* Bit definition for SDIO_BUF register *******************/ +#define SDIO_BUF_DT_Pos (0U) +#define SDIO_BUF_DT_Msk (0xFFFFFFFFU << SDIO_BUF_DT_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_BUF_DT SDIO_BUF_DT_Msk /*!< Receive and transmit BUF data */ + +/******************************************************************************/ +/* */ +/* Comparator (COMP) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for CMP_CTRLSTS1 register *****************/ +#define CMP_CTRLSTS1_CMP1EN_Pos (0U) +#define CMP_CTRLSTS1_CMP1EN_Msk (0x1U << CMP_CTRLSTS1_CMP1EN_Pos) /*!< 0x00000001 */ +#define CMP_CTRLSTS1_CMP1EN CMP_CTRLSTS1_CMP1EN_Msk /*!< Comparator 1 enable */ +#define CMP_CTRLSTS1_CMP1IS_Pos (1U) +#define CMP_CTRLSTS1_CMP1IS_Msk (0x1U << CMP_CTRLSTS1_CMP1IS_Pos) /*!< 0x00000002 */ +#define CMP_CTRLSTS1_CMP1IS CMP_CTRLSTS1_CMP1IS_Msk /*!< Comparator 1 input shift */ +#define CMP_CTRLSTS1_CMP1SSEL_Pos (2U) +#define CMP_CTRLSTS1_CMP1SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP1SSEL_Pos) /*!< 0x00000004 */ +#define CMP_CTRLSTS1_CMP1SSEL CMP_CTRLSTS1_CMP1SSEL_Msk /*!< Comparator 1 speed selection */ + +#define CMP_CTRLSTS1_CMP1INVSEL_Pos (4U) +#define CMP_CTRLSTS1_CMP1INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000070 */ +#define CMP_CTRLSTS1_CMP1INVSEL CMP_CTRLSTS1_CMP1INVSEL_Msk /*!< CMP1INVSEL[2:0] bits (Comparator 1 inverting selection) */ +#define CMP_CTRLSTS1_CMP1INVSEL_0 (0x1U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000010 */ +#define CMP_CTRLSTS1_CMP1INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000020 */ +#define CMP_CTRLSTS1_CMP1INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000040 */ + +#define CMP_CTRLSTS1_CMP1TAG_Pos (8U) +#define CMP_CTRLSTS1_CMP1TAG_Msk (0x7U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000700 */ +#define CMP_CTRLSTS1_CMP1TAG CMP_CTRLSTS1_CMP1TAG_Msk /*!< CMP1TAG[2:0] bits (Comparator 1 output target) */ +#define CMP_CTRLSTS1_CMP1TAG_0 (0x1U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000100 */ +#define CMP_CTRLSTS1_CMP1TAG_1 (0x2U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000200 */ +#define CMP_CTRLSTS1_CMP1TAG_2 (0x4U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000400 */ + +#define CMP_CTRLSTS1_CMP1P_Pos (11U) +#define CMP_CTRLSTS1_CMP1P_Msk (0x1U << CMP_CTRLSTS1_CMP1P_Pos) /*!< 0x00000800 */ +#define CMP_CTRLSTS1_CMP1P CMP_CTRLSTS1_CMP1P_Msk /*!< Comparator 1 polarity */ + +#define CMP_CTRLSTS1_CMP1HYST_Pos (12U) +#define CMP_CTRLSTS1_CMP1HYST_Msk (0x3U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00003000 */ +#define CMP_CTRLSTS1_CMP1HYST CMP_CTRLSTS1_CMP1HYST_Msk /*!< CMP1HYST[1:0] bits (Comparator 1 hysteresis) */ +#define CMP_CTRLSTS1_CMP1HYST_0 (0x1U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00001000 */ +#define CMP_CTRLSTS1_CMP1HYST_1 (0x2U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00002000 */ + +#define CMP_CTRLSTS1_CMP1VALUE_Pos (14U) +#define CMP_CTRLSTS1_CMP1VALUE_Msk (0x1U << CMP_CTRLSTS1_CMP1VALUE_Pos) /*!< 0x00004000 */ +#define CMP_CTRLSTS1_CMP1VALUE CMP_CTRLSTS1_CMP1VALUE_Msk /*!< Comparator 1 output value */ +#define CMP_CTRLSTS1_CMP1WP_Pos (15U) +#define CMP_CTRLSTS1_CMP1WP_Msk (0x1U << CMP_CTRLSTS1_CMP1WP_Pos) /*!< 0x00008000 */ +#define CMP_CTRLSTS1_CMP1WP CMP_CTRLSTS1_CMP1WP_Msk /*!< Comparator 1 write protect */ +#define CMP_CTRLSTS1_CMP2EN_Pos (16U) +#define CMP_CTRLSTS1_CMP2EN_Msk (0x1U << CMP_CTRLSTS1_CMP2EN_Pos) /*!< 0x00010000 */ +#define CMP_CTRLSTS1_CMP2EN CMP_CTRLSTS1_CMP2EN_Msk /*!< Comparator 2 enable */ +#define CMP_CTRLSTS1_CMP2SSEL_Pos (18U) +#define CMP_CTRLSTS1_CMP2SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP2SSEL_Pos) /*!< 0x00040000 */ +#define CMP_CTRLSTS1_CMP2SSEL CMP_CTRLSTS1_CMP2SSEL_Msk /*!< Comparator 2 speed selection */ + +#define CMP_CTRLSTS1_CMP2INVSEL_Pos (20U) +#define CMP_CTRLSTS1_CMP2INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00700000 */ +#define CMP_CTRLSTS1_CMP2INVSEL CMP_CTRLSTS1_CMP2INVSEL_Msk /*!< CMP2INVSEL[2:0] bits (Comparator 2 inverting selection) */ +#define CMP_CTRLSTS1_CMP2INVSEL_0 (0x1U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00100000 */ +#define CMP_CTRLSTS1_CMP2INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00200000 */ +#define CMP_CTRLSTS1_CMP2INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00400000 */ + +#define CMP_CTRLSTS1_DCMPEN_Pos (23U) +#define CMP_CTRLSTS1_DCMPEN_Msk (0x1U << CMP_CTRLSTS1_DCMPEN_Pos) /*!< 0x00800000 */ +#define CMP_CTRLSTS1_DCMPEN CMP_CTRLSTS1_DCMPEN_Msk /*!< Double comparator mode enable */ + +#define CMP_CTRLSTS1_CMP2TAG_Pos (24U) +#define CMP_CTRLSTS1_CMP2TAG_Msk (0x7U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x07000000 */ +#define CMP_CTRLSTS1_CMP2TAG CMP_CTRLSTS1_CMP2TAG_Msk /*!< CMP2TAG[2:0] bits (Comparator 2 output target) */ +#define CMP_CTRLSTS1_CMP2TAG_0 (0x1U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x01000000 */ +#define CMP_CTRLSTS1_CMP2TAG_1 (0x2U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x02000000 */ +#define CMP_CTRLSTS1_CMP2TAG_2 (0x4U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x04000000 */ + +#define CMP_CTRLSTS1_CMP2P_Pos (27U) +#define CMP_CTRLSTS1_CMP2P_Msk (0x1U << CMP_CTRLSTS1_CMP2P_Pos) /*!< 0x08000000 */ +#define CMP_CTRLSTS1_CMP2P CMP_CTRLSTS1_CMP2P_Msk /*!< Comparator 2 polarity */ + +#define CMP_CTRLSTS1_CMP2HYST_Pos (28U) +#define CMP_CTRLSTS1_CMP2HYST_Msk (0x3U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x30000000 */ +#define CMP_CTRLSTS1_CMP2HYST CMP_CTRLSTS1_CMP2HYST_Msk /*!< CMP2HYST[1:0] bits (Comparator 2 hysteresis) */ +#define CMP_CTRLSTS1_CMP2HYST_0 (0x1U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x10000000 */ +#define CMP_CTRLSTS1_CMP2HYST_1 (0x2U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x20000000 */ + +#define CMP_CTRLSTS1_CMP2VALUE_Pos (30U) +#define CMP_CTRLSTS1_CMP2VALUE_Msk (0x1U << CMP_CTRLSTS1_CMP2VALUE_Pos) /*!< 0x40000000 */ +#define CMP_CTRLSTS1_CMP2VALUE CMP_CTRLSTS1_CMP2VALUE_Msk /*!< Comparator 2 output value */ +#define CMP_CTRLSTS1_CMP2WP_Pos (31U) +#define CMP_CTRLSTS1_CMP2WP_Msk (0x1U << CMP_CTRLSTS1_CMP2WP_Pos) /*!< 0x80000000 */ +#define CMP_CTRLSTS1_CMP2WP CMP_CTRLSTS1_CMP2WP_Msk /*!< Comparator 2 write protect */ + +/***************** Bit definition for CMP_CTRLSTS2 register *****************/ +#define CMP_CTRLSTS2_CMP1NINVSEL_Pos (0U) +#define CMP_CTRLSTS2_CMP1NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000003 */ +#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< Comparator 1 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP1NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000001 */ +#define CMP_CTRLSTS2_CMP1NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000002 */ + +#define CMP_CTRLSTS2_CMP2NINVSEL_Pos (16U) +#define CMP_CTRLSTS2_CMP2NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00030000 */ +#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< Comparator 2 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP2NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00010000 */ +#define CMP_CTRLSTS2_CMP2NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00020000 */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DEBUG) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DEBUG_IDCODE register *****************/ +#define DEBUG_IDCODE_PID_Pos (0U) +#define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ +#define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ +#define DEBUG_IDCODE_PID_0 (0x00000001U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000001 */ +#define DEBUG_IDCODE_PID_1 (0x00000002U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000002 */ +#define DEBUG_IDCODE_PID_2 (0x00000004U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000004 */ +#define DEBUG_IDCODE_PID_3 (0x00000008U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000008 */ +#define DEBUG_IDCODE_PID_4 (0x00000010U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000010 */ +#define DEBUG_IDCODE_PID_5 (0x00000020U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000020 */ +#define DEBUG_IDCODE_PID_6 (0x00000040U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000040 */ +#define DEBUG_IDCODE_PID_7 (0x00000080U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000080 */ +#define DEBUG_IDCODE_PID_8 (0x00000100U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000100 */ +#define DEBUG_IDCODE_PID_9 (0x00000200U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000200 */ +#define DEBUG_IDCODE_PID_10 (0x00000400U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000400 */ +#define DEBUG_IDCODE_PID_11 (0x00000800U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000800 */ +#define DEBUG_IDCODE_PID_12 (0x00001000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00001000 */ +#define DEBUG_IDCODE_PID_13 (0x00002000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00002000 */ +#define DEBUG_IDCODE_PID_14 (0x00004000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00004000 */ +#define DEBUG_IDCODE_PID_15 (0x00008000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00008000 */ +#define DEBUG_IDCODE_PID_16 (0x00010000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00010000 */ +#define DEBUG_IDCODE_PID_17 (0x00020000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00020000 */ +#define DEBUG_IDCODE_PID_18 (0x00040000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00040000 */ +#define DEBUG_IDCODE_PID_19 (0x00080000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00080000 */ +#define DEBUG_IDCODE_PID_20 (0x00100000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00100000 */ +#define DEBUG_IDCODE_PID_21 (0x00200000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00200000 */ +#define DEBUG_IDCODE_PID_22 (0x00400000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00400000 */ +#define DEBUG_IDCODE_PID_23 (0x00800000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00800000 */ +#define DEBUG_IDCODE_PID_24 (0x01000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x01000000 */ +#define DEBUG_IDCODE_PID_25 (0x02000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x02000000 */ +#define DEBUG_IDCODE_PID_26 (0x04000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x04000000 */ +#define DEBUG_IDCODE_PID_27 (0x08000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x08000000 */ +#define DEBUG_IDCODE_PID_28 (0x10000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x10000000 */ +#define DEBUG_IDCODE_PID_29 (0x20000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x20000000 */ +#define DEBUG_IDCODE_PID_30 (0x40000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x40000000 */ +#define DEBUG_IDCODE_PID_31 (0x80000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DEBUG_CTRL register ******************/ +#define DEBUG_CTRL_SLEEP_DEBUG_Pos (0U) +#define DEBUG_CTRL_SLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_SLEEP_DEBUG_Pos) /*!< 0x00000001 */ +#define DEBUG_CTRL_SLEEP_DEBUG DEBUG_CTRL_SLEEP_DEBUG_Msk /*!< Debug Sleep mode control bit */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos) +#define DEBUG_CTRL_DEEPSLEEP_DEBUG DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk /*!< Debug Deep sleep mode control bit */ +#define DEBUG_CTRL_STANDBY_DEBUG_Pos (2U) +#define DEBUG_CTRL_STANDBY_DEBUG_Msk (0x1U << DEBUG_CTRL_STANDBY_DEBUG_Pos) /*!< 0x00000004 */ +#define DEBUG_CTRL_STANDBY_DEBUG DEBUG_CTRL_STANDBY_DEBUG_Msk /*!< Debug Standby mode control bit */ +#define DEBUG_CTRL_TRACE_IOEN_Pos (5U) +#define DEBUG_CTRL_TRACE_IOEN_Msk (0x1U << DEBUG_CTRL_TRACE_IOEN_Pos) /*!< 0x00000020 */ +#define DEBUG_CTRL_TRACE_IOEN DEBUG_CTRL_TRACE_IOEN_Msk /*!< Trace pin assignment enable */ + +#define DEBUG_CTRL_TRACE_MODE_Pos (6U) +#define DEBUG_CTRL_TRACE_MODE_Msk (0x3U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DEBUG_CTRL_TRACE_MODE DEBUG_CTRL_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace pin assignment control) */ +#define DEBUG_CTRL_TRACE_MODE_0 (0x1U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DEBUG_CTRL_TRACE_MODE_1 (0x2U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x00000080 */ + +#define DEBUG_CTRL_WDT_PAUSE_Pos (8U) +#define DEBUG_CTRL_WDT_PAUSE_Msk (0x1U << DEBUG_CTRL_WDT_PAUSE_Pos) /*!< 0x00000100 */ +#define DEBUG_CTRL_WDT_PAUSE DEBUG_CTRL_WDT_PAUSE_Msk /*!< Watchdog pause control bit */ +#define DEBUG_CTRL_WWDT_PAUSE_Pos (9U) +#define DEBUG_CTRL_WWDT_PAUSE_Msk (0x1U << DEBUG_CTRL_WWDT_PAUSE_Pos) /*!< 0x00000200 */ +#define DEBUG_CTRL_WWDT_PAUSE DEBUG_CTRL_WWDT_PAUSE_Msk /*!< Window watchdog pause control bit */ +#define DEBUG_CTRL_TMR1_PAUSE_Pos (10U) +#define DEBUG_CTRL_TMR1_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR1_PAUSE_Pos) /*!< 0x00000400 */ +#define DEBUG_CTRL_TMR1_PAUSE DEBUG_CTRL_TMR1_PAUSE_Msk /*!< TMR1 pause control bit */ +#define DEBUG_CTRL_TMR2_PAUSE_Pos (11U) +#define DEBUG_CTRL_TMR2_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR2_PAUSE_Pos) /*!< 0x00000800 */ +#define DEBUG_CTRL_TMR2_PAUSE DEBUG_CTRL_TMR2_PAUSE_Msk /*!< TMR2 pause control bit */ +#define DEBUG_CTRL_TMR3_PAUSE_Pos (12U) +#define DEBUG_CTRL_TMR3_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR3_PAUSE_Pos) /*!< 0x00001000 */ +#define DEBUG_CTRL_TMR3_PAUSE DEBUG_CTRL_TMR3_PAUSE_Msk /*!< TMR3 pause control bit */ +#define DEBUG_CTRL_TMR4_PAUSE_Pos (13U) +#define DEBUG_CTRL_TMR4_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR4_PAUSE_Pos) /*!< 0x00002000 */ +#define DEBUG_CTRL_TMR4_PAUSE DEBUG_CTRL_TMR4_PAUSE_Msk /*!< TMR4 pause control bit */ +#define DEBUG_CTRL_CAN1_PAUSE_Pos (14U) +#define DEBUG_CTRL_CAN1_PAUSE_Msk (0x1U << DEBUG_CTRL_CAN1_PAUSE_Pos) /*!< 0x00004000 */ +#define DEBUG_CTRL_CAN1_PAUSE DEBUG_CTRL_CAN1_PAUSE_Msk /*!< CAN1 pause control bit */ +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Pos (15U) /*!< 0x00008000 */ +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Pos) +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 pause control bit */ +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Pos (16U) /*!< 0x00010000 */ +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Pos) +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Msk /*!< I2C2 pause control bit */ +#define DEBUG_CTRL_TMR5_PAUSE_Pos (18U) +#define DEBUG_CTRL_TMR5_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR5_PAUSE_Pos) /*!< 0x00040000 */ +#define DEBUG_CTRL_TMR5_PAUSE DEBUG_CTRL_TMR5_PAUSE_Msk /*!< TMR5 pause control bit */ +#define DEBUG_CTRL_TMR9_PAUSE_Pos (28U) +#define DEBUG_CTRL_TMR9_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR9_PAUSE_Pos) /*!< 0x10000000 */ +#define DEBUG_CTRL_TMR9_PAUSE DEBUG_CTRL_TMR9_PAUSE_Msk /*!< TMR9 pause control bit */ +#define DEBUG_CTRL_TMR10_PAUSE_Pos (29U) +#define DEBUG_CTRL_TMR10_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR10_PAUSE_Pos) /*!< 0x20000000 */ +#define DEBUG_CTRL_TMR10_PAUSE DEBUG_CTRL_TMR10_PAUSE_Msk /*!< TMR10 pause control bit */ +#define DEBUG_CTRL_TMR11_PAUSE_Pos (30U) +#define DEBUG_CTRL_TMR11_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR11_PAUSE_Pos) /*!< 0x40000000 */ +#define DEBUG_CTRL_TMR11_PAUSE DEBUG_CTRL_TMR11_PAUSE_Msk /*!< TMR11 pause control bit */ + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +/******************************* CAN Instances ********************************/ +#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + +/******************************* DMA Instances ********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ + ((INSTANCE) == DMA1_Channel2) || \ + ((INSTANCE) == DMA1_Channel3) || \ + ((INSTANCE) == DMA1_Channel4) || \ + ((INSTANCE) == DMA1_Channel5) || \ + ((INSTANCE) == DMA1_Channel6) || \ + ((INSTANCE) == DMA1_Channel7) || \ + ((INSTANCE) == DMA2_Channel1) || \ + ((INSTANCE) == DMA2_Channel2) || \ + ((INSTANCE) == DMA2_Channel3) || \ + ((INSTANCE) == DMA2_Channel4) || \ + ((INSTANCE) == DMA2_Channel5) || \ + ((INSTANCE) == DMA2_Channel6) || \ + ((INSTANCE) == DMA2_Channel7)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOF)) + +/********************* IOMUX Multiplex Function Instances *********************/ +#define IS_IOMUX_ALL_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************* I2C Instances ********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE + +/******************************* I2S Instances ********************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/******************************* WDT Instances ********************************/ +#define IS_WDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WDT) + +/******************************* SDIO Instances *******************************/ +#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) + +/******************************* SPI Instances ********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/**************************** START TMR Instances *****************************/ +/******************************* TMR Instances ********************************/ +#define IS_TMR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_C1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_C2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_C3_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_C4_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_CLOCKSOURCE_EXTMODE1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_CLOCKSOURCE_EXTMODE2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_CLOCKSOURCE_TRGIN_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_CLOCKSOURCE_ISX_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_XOR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_MASTER_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_SLAVE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_DMABURST_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_BREAK_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_CX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TMR1) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR2) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR3) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR4) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR5) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR9) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2))) \ + || \ + (((INSTANCE) == TMR10) && \ + (((CHANNEL) == TMR_CHANNEL_1))) \ + || \ + (((INSTANCE) == TMR11) && \ + (((CHANNEL) == TMR_CHANNEL_1)))) + +#define IS_TMR_CXN_INSTANCE(INSTANCE, CHANNEL) \ + (((INSTANCE) == TMR1) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3))) + +#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_DMA_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_DMA_CC_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1)) + +#define IS_TMR_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE) 0U + +/***************************** END TMR Instances ******************************/ + +/********************* USART Instances : Synchronous mode *********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/********************* UART Instances : Asynchronous mode *********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/********************* UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/************************* UART Instances : LIN mode **************************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************* UART Instances : Hardware Flow control *******************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/********************* UART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/************************* UART Instances : IRDA mode *************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************* UART Instances : Multi-Processor mode ********************/ +#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************** UART Instances : DMA mode available *********************/ +#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************************* ERTC Instances *******************************/ +#define IS_ERTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ERTC) + +/******************************* WWDT Instances *******************************/ +#define IS_WWDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDT) + +#define CRM_HEXT_MIN 4000000U +#define CRM_HEXT_MAX 25000000U + +#define CRM_MAX_FREQUENCY 150000000U + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F415Cx_H */ + +/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h new file mode 100644 index 0000000000..cbf383d983 --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -0,0 +1,10447 @@ +/** + ****************************************************************************** + * @file at32f415kx.h + * @author Artery Technology & HorrorTroll & Zhaqian + * @version v2.1.1 + * @date 26-October-2023 + * @brief AT32F415Kx header file. + * + ****************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f415kx + * @{ + */ + +#ifndef __AT32F415Kx_H +#define __AT32F415Kx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief CMSIS Device version number V2.1.1 + */ +#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ +#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ + |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ + |(__AT32F415_LIBRARY_VERSION_MINOR << 8 )\ + |(__AT32F415_LIBRARY_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< AT32 devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< AT32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< AT32 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief AT32F415Kx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector Interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** AT32 specific Interrupt Numbers **********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ + PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ + ERTC_IRQn = 3, /*!< ERTC Interrupt linked to EXINT22 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + CRM_IRQn = 5, /*!< CRM global Interrupt */ + EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ + EXINT1_IRQn = 7, /*!< EXINT Line 1 Interrupt */ + EXINT2_IRQn = 8, /*!< EXINT Line 2 Interrupt */ + EXINT3_IRQn = 9, /*!< EXINT Line 3 Interrupt */ + EXINT4_IRQn = 10, /*!< EXINT Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SE_IRQn = 22, /*!< CAN1 SE Interrupt */ + EXINT9_5_IRQn = 23, /*!< EXINT Line[9:5] Interrupts */ + TMR1_BRK_TMR9_IRQn = 24, /*!< TMR1 Break Interrupt and TMR9 global Interrupt */ + TMR1_OVF_TMR10_IRQn = 25, /*!< TMR1 Overflow Interrupt and TMR10 global Interrupt */ + TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< TMR1 Trigger and Hall Interrupt and TMR11 global IRQ */ + TMR1_CH_IRQn = 27, /*!< TMR1 Channel Interrupt */ + TMR2_GLOBAL_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_GLOBAL_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_GLOBAL_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EVT_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ERR_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EVT_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ERR_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXINT15_10_IRQn = 40, /*!< EXINT Line[15:10] Interrupts */ + ERTCAlarm_IRQn = 41, /*!< ERTC Alarm Interrupt linked to EXINT17 */ + OTGFS_WKUP_IRQn = 42, /*!< OTGFS Wake Up Interrupt linked to EXINT18 */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_GLOBAL_IRQn = 50, /*!< TMR5 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + OTGFS_IRQn = 67, /*!< OTGFS global Interrupt */ + CMP1_IRQn = 70, /*!< CMP1 Interrupt linked to EXINT19 */ + CMP2_IRQn = 71, /*!< CMP2 Interrupt linked to EXINT20 */ + DMA2_Channel6_7_IRQn = 75, /*!< DMA2 Channel 6 and Channel 7 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" +#include "system_at32f415.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CTRL2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SPT1; /*!< ADC sampling time register 1, Address offset: 0x0C */ + __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x10 */ + __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x14 */ + __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x18 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3 Address offset: 0x1C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4 Address offset: 0x20 */ + __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x24 */ + __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x28 */ + __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x2C */ + __IO uint32_t OSQ2; /*!< ADC ordinary sequence register 2, Address offset: 0x30 */ + __IO uint32_t OSQ3; /*!< ADC ordinary sequence register 3, Address offset: 0x34 */ + __IO uint32_t PSQ; /*!< ADC preempted sequence register, Address offset: 0x38 */ + __IO uint32_t PDT1; /*!< ADC preempted data register 1, Address offset: 0x3C */ + __IO uint32_t PDT2; /*!< ADC preempted data register 2, Address offset: 0x40 */ + __IO uint32_t PDT3; /*!< ADC preempted data register 3, Address offset: 0x44 */ + __IO uint32_t PDT4; /*!< ADC preempted data register 4, Address offset: 0x48 */ + __IO uint32_t ODT; /*!< ADC ordinary data register, Address offset: 0x4C */ +} ADC_TypeDef; + +/** + * @brief Controller Area Network TX Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMC; + __IO uint32_t TMDTL; + __IO uint32_t TMDTH; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFO Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t RFI; + __IO uint32_t RFC; + __IO uint32_t RFDTL; + __IO uint32_t RFDTH; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network Filter Registers + */ + +typedef struct +{ + __IO uint32_t FFB1; + __IO uint32_t FFB2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; /*!< CAN master control register, Address offset: 0x000 */ + __IO uint32_t MSTS; /*!< CAN master status register, Address offset: 0x004 */ + __IO uint32_t TSTS; /*!< CAN transmit status register, Address offset: 0x008 */ + __IO uint32_t RF0; /*!< CAN receive FIFO 0 register, Address offset: 0x00C */ + __IO uint32_t RF1; /*!< CAN receive FIFO 1 register, Address offset: 0x010 */ + __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ + __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ + __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FF */ + __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ + __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ + __IO uint32_t FBWCFG; /*!< CAN filter bit width configuration register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x210 */ + __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ + __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ +} CAN_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CTRLSTS1; /*!< CMP control and status register 1, Address offset: 0x00 */ + __IO uint32_t CTRLSTS2; /*!< CMP control and status register 2, Address offset: 0x04 */ +} CMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DT; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t CDT; /*!< CRC Common data register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ +} CRC_TypeDef; + +/** + * @brief Clock and Reset Manage + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< CRM Clock control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< CRM Clock configuration register, Address offset: 0x04 */ + __IO uint32_t CLKINT; /*!< CRM Clock interrupt register, Address offset: 0x08 */ + __IO uint32_t APB2RST; /*!< CRM APB2 peripheral reset register, Address offset: 0x0C */ + __IO uint32_t APB1RST; /*!< CRM APB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHBEN; /*!< CRM APB peripheral clock enable register, Address offset: 0x14 */ + __IO uint32_t APB2EN; /*!< CRM APB2 peripheral clock enable register, Address offset: 0x18 */ + __IO uint32_t APB1EN; /*!< CRM APB1 peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t BPDC; /*!< CRM Battery powered domain control register, Address offset: 0x20 */ + __IO uint32_t CTRLSTS; /*!< CRM Control/status register, Address offset: 0x24 */ + __IO uint32_t AHBRST; /*!< CRM APB peripheral reset register, Address offset: 0x28 */ + __IO uint32_t PLL; /*!< CRM PLL configuration register, Address offset: 0x2C */ + __IO uint32_t MISC1; /*!< CRM Additional register 1, Address offset: 0x30 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x34 ~ 0x40 */ + __IO uint32_t OTG_EXTCTRL; /*!< CRM OTG_FS extended control register, Address offset: 0x44 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x48 - 0x50 */ + __IO uint32_t MISC2; /*!< CRM Additional register 2, Address offset: 0x54 */ +} CRM_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< DEBUG device ID, Address offset: 0xE004_2000 */ + __IO uint32_t CTRL; /*!< DEBUG control register, Address offset: 0xE004_2004 */ +} DEBUG_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) x = 1 ... 7 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t CLR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ + uint32_t RESERVED[38]; /*!< Reserved, Address offset: 0x08 ~ 0x9C */ + __IO uint32_t SRC_SEL0; /*!< DMA Channel source register 0, Address offset: 0xA0 */ + __IO uint32_t SRC_SEL1; /*!< DMA Channel source register 1, Address offset: 0xA4 */ +} DMA_TypeDef; + +/** + * @brief Enhanced Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TIME; /*!< ERTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< ERTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< ERTC control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< ERTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t DIV; /*!< ERTC divider register, Address offset: 0x10 */ + __IO uint32_t WAT; /*!< ERTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CCAL; /*!< ERTC coarse calibration register, Address offset: 0x18 */ + __IO uint32_t ALA; /*!< ERTC alarm clock A register, Address offset: 0x1C */ + __IO uint32_t ALB; /*!< ERTC alarm clock B register, Address offset: 0x20 */ + __IO uint32_t WP; /*!< ERTC write protection register, Address offset: 0x24 */ + __IO uint32_t SBS; /*!< ERTC subsecond register, Address offset: 0x28 */ + __IO uint32_t TADJ; /*!< ERTC time adjustment register, Address offset: 0x2C */ + __IO uint32_t TSTM; /*!< ERTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDT; /*!< ERTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSBS; /*!< ERTC time stamp subsecond register, Address offset: 0x38 */ + __IO uint32_t SCAL; /*!< ERTC smooth calibration register, Address offset: 0x3C */ + __IO uint32_t TAMP; /*!< ERTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALASBS; /*!< ERTC alarm clock A subsecond register, Address offset: 0x44 */ + __IO uint32_t ALBSBS; /*!< ERTC alarm clock B subsecond register, Address offset: 0x48 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t BPR1; /*!< ERTC battery powered domain data register 1, Address offset: 0x50 */ + __IO uint32_t BPR2; /*!< ERTC battery powered domain data register 2, Address offset: 0x54 */ + __IO uint32_t BPR3; /*!< ERTC battery powered domain data register 3, Address offset: 0x58 */ + __IO uint32_t BPR4; /*!< ERTC battery powered domain data register 4, Address offset: 0x5C */ + __IO uint32_t BPR5; /*!< ERTC battery powered domain data register 5, Address offset: 0x60 */ + __IO uint32_t BPR6; /*!< ERTC battery powered domain data register 6, Address offset: 0x64 */ + __IO uint32_t BPR7; /*!< ERTC battery powered domain data register 7, Address offset: 0x68 */ + __IO uint32_t BPR8; /*!< ERTC battery powered domain data register 8, Address offset: 0x6C */ + __IO uint32_t BPR9; /*!< ERTC battery powered domain data register 9, Address offset: 0x70 */ + __IO uint32_t BPR10; /*!< ERTC BAT powered domain data register 10, Address offset: 0x74 */ + __IO uint32_t BPR11; /*!< ERTC BAT powered domain data register 11, Address offset: 0x78 */ + __IO uint32_t BPR12; /*!< ERTC BAT powered domain data register 12, Address offset: 0x7C */ + __IO uint32_t BPR13; /*!< ERTC BAT powered domain data register 13, Address offset: 0x80 */ + __IO uint32_t BPR14; /*!< ERTC BAT powered domain data register 14, Address offset: 0x84 */ + __IO uint32_t BPR15; /*!< ERTC BAT powered domain data register 15, Address offset: 0x88 */ + __IO uint32_t BPR16; /*!< ERTC BAT powered domain data register 16, Address offset: 0x8C */ + __IO uint32_t BPR17; /*!< ERTC BAT powered domain data register 17, Address offset: 0x90 */ + __IO uint32_t BPR18; /*!< ERTC BAT powered domain data register 18, Address offset: 0x94 */ + __IO uint32_t BPR19; /*!< ERTC BAT powered domain data register 19, Address offset: 0x98 */ + __IO uint32_t BPR20; /*!< ERTC BAT powered domain data register 20, Address offset: 0x9C */ +} ERTC_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t INTEN; /*!< EXINT Interrupt enable register, Address offset: 0x00 */ + __IO uint32_t EVTEN; /*!< EXINT Event enable register, Address offset: 0x04 */ + __IO uint32_t POLCFG1; /*!< EXINT Polarity configuration register 1, Address offset: 0x08 */ + __IO uint32_t POLCFG2; /*!< EXINT Polarity configuration register 2, Address offset: 0x0C */ + __IO uint32_t SWTRG; /*!< EXINT Software trigger register, Address offset: 0x10 */ + __IO uint32_t INTSTS; /*!< EXINT Interrupt status register, Address offset: 0x14 */ +} EXINT_TypeDef; + +/** + * @brief Flash Memory Registers + */ + +typedef struct +{ + __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register 1, Address offset: 0x04 */ + __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t ADDR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t USD; /*!< FLASH user system data register, Address offset: 0x1C */ + __IO uint32_t EPPS; /*!< FLASH erase/program protection status reg, Address offset: 0x20 */ + uint32_t RESERVED1[20]; /*!< Reserved, Address offset: 0x24 ~ 0x70 */ + __IO uint32_t SLIB_STS0; /*!< FLASH security library status register 0, Address offset: 0x74 */ + __IO uint32_t SLIB_STS1; /*!< FLASH security library status register 1, Address offset: 0x78 */ + __IO uint32_t SLIB_PWD_CLR; /*!< FLASH security library password clear reg, Address offset: 0x7C */ + __IO uint32_t SLIB_MISC_STS; /*!< FLASH security library additional stat reg, Address offset: 0x80 */ + __IO uint32_t CRC_ADDR; /*!< FLASH CRC address register, Address offset: 0x84 */ + __IO uint32_t CRC_CTRL; /*!< FLASH CRC control register, Address offset: 0x88 */ + __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register, Address offset: 0x8C */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x90 ~ 0x15C */ + __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ + __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ + __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot mode setting register, Address offset: 0x16C */ + __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ +} FLASH_TypeDef; + +/** + * @brief User System Data Registers + */ + +typedef struct +{ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ +} USD_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ + __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ + __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ +} GPIO_TypeDef; + +/** + * @brief Multiplex Function I/O + */ + +typedef struct +{ + __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ + __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ + __IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */ + __IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */ + __IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */ + __IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ + __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ + __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ + __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ + __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ + __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ + __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ +} IOMUX_TypeDef; + +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OADDR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OADDR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DT; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t STS1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t STS2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CLKCTRL; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TMRISE; /*!< I2C timer rise time register, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< PWC Power control register, Address offset: 0x00 */ + __IO uint32_t CTRLSTS; /*!< PWC Power control/status register, Address offset: 0x04 */ +} PWC_TypeDef; + +/** + * @brief SD Host Interface + */ + +typedef struct +{ + __IO uint32_t PWRCTRL; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCTRL; /*!< SDIO clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RSPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RSP1; /*!< SDIO response register 1, Address offset: 0x14 */ + __I uint32_t RSP2; /*!< SDIO response register 2, Address offset: 0x18 */ + __I uint32_t RSP3; /*!< SDIO response register 3, Address offset: 0x1C */ + __I uint32_t RSP4; /*!< SDIO response register 4, Address offset: 0x20 */ + __IO uint32_t DTTMR; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DTLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DTCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DTCNTR; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STS; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t INTCLR; /*!< SDIO clear interrupt register, Address offset: 0x38 */ + __IO uint32_t INTEN; /*!< SDIO interrupt mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x40 ~ 0x44 */ + __I uint32_t BUFCNTR; /*!< SDIO BUF counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, Address offset: 0x4C ~ 0x7C */ + __IO uint32_t BUF; /*!< SDIO data BUF register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< SPI control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ + __IO uint32_t RCRC; /*!< SPI RX CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI TX CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S register, Address offset: 0x1C */ + __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TMR Timers + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< TMR control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< TMR control register 2, Address offset: 0x04 */ + __IO uint32_t STCTRL; /*!< TMR slave timer control register, Address offset: 0x08 */ + __IO uint32_t IDEN; /*!< TMR DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t ISTS; /*!< TMR interrupt status register, Address offset: 0x10 */ + __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ + __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ + __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ + __IO uint32_t CCTRL; /*!< TMR Channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value, Address offset: 0x28 */ + __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ + __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ + __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ + __IO uint32_t C2DT; /*!< TMR channel 2 data register, Address offset: 0x38 */ + __IO uint32_t C3DT; /*!< TMR channel 3 data register, Address offset: 0x3C */ + __IO uint32_t C4DT; /*!< TMR channel 4 data register, Address offset: 0x40 */ + __IO uint32_t BRK; /*!< TMR break register, Address offset: 0x44 */ + __IO uint32_t DMACTRL; /*!< TMR DMA control register, Address offset: 0x48 */ + __IO uint32_t DMADT; /*!< TMR DMA data register, Address offset: 0x4C */ +} TMR_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< USART status register, Address offset: 0x00 */ + __IO uint32_t DT; /*!< USART data register, Address offset: 0x04 */ + __IO uint32_t BAUDR; /*!< USART baud rate register, Address offset: 0x08 */ + __IO uint32_t CTRL1; /*!< USART control register 1, Address offset: 0x0C */ + __IO uint32_t CTRL2; /*!< USART control register 2, Address offset: 0x10 */ + __IO uint32_t CTRL3; /*!< USART control register 3, Address offset: 0x14 */ + __IO uint32_t GDIV; /*!< USART guard time and divider register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CMD; /*!< WDT Command register, Address offset: 0x00 */ + __IO uint32_t DIV; /*!< WDT Divider register, Address offset: 0x04 */ + __IO uint32_t RLD; /*!< WDT Reload register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< WDT Status register, Address offset: 0x0C */ +} WDT_TypeDef; + +/** + * @brief Window WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< WWDT Control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< WWDT Configuration register, Address offset: 0x04 */ + __IO uint32_t STS; /*!< WWDT Status register, Address offset: 0x08 */ +} WWDT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH end address of bank 1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE /*!< APB1 base address */ +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) /*!< APB2 base address */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< AHB base address */ + +#define TMR2_BASE (APB1PERIPH_BASE + 0x00000000U) /*!< TMR2 base address */ +#define TMR3_BASE (APB1PERIPH_BASE + 0x00000400U) /*!< TMR3 base address */ +#define TMR4_BASE (APB1PERIPH_BASE + 0x00000800U) /*!< TMR4 base address */ +#define TMR5_BASE (APB1PERIPH_BASE + 0x00000C00U) /*!< TMR5 base address */ +#define CMP_BASE (APB1PERIPH_BASE + 0x00002400U) /*!< CMP base address */ +#define ERTC_BASE (APB1PERIPH_BASE + 0x00002800U) /*!< ERTC base address */ +#define WWDT_BASE (APB1PERIPH_BASE + 0x00002C00U) /*!< WWDT base address */ +#define WDT_BASE (APB1PERIPH_BASE + 0x00003000U) /*!< WDT base address */ +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) /*!< SPI2 base address */ +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) /*!< USART2 base address */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) /*!< I2C1 base address */ +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ +#define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ +#define IOMUX_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< IOMUX base address */ +#define EXINT_BASE (APB2PERIPH_BASE + 0x00000400U) /*!< EXINT base address */ +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) /*!< GPIOA base address */ +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) /*!< GPIOB base address */ +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) /*!< GPIOC base address */ +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) /*!< GPIOD base address */ +#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U) /*!< GPIOF base address */ +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) /*!< ADC1 base address */ +#define TMR1_BASE (APB2PERIPH_BASE + 0x00002C00U) /*!< TMR1 base address */ +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) /*!< SPI1 base address */ +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< USART1 base address */ +#define TMR9_BASE (APB2PERIPH_BASE + 0x00004C00U) /*!< TMR9 base address */ +#define TMR10_BASE (APB2PERIPH_BASE + 0x00005000U) /*!< TMR10 base address */ +#define TMR11_BASE (APB2PERIPH_BASE + 0x00005400U) /*!< TMR11 base address */ + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) /*!< SDIO base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) /*!< DMA1 base address */ +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) /*!< DMA1 Channel 1 base address */ +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) /*!< DMA1 Channel 2 base address */ +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) /*!< DMA1 Channel 3 base address */ +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) /*!< DMA1 Channel 4 base address */ +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) /*!< DMA1 Channel 5 base address */ +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) /*!< DMA1 Channel 6 base address */ +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) /*!< DMA1 Channel 7 base address */ +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U) /*!< DMA2 base address */ +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U) /*!< DMA2 Channel 1 base address */ +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU) /*!< DMA2 Channel 2 base address */ +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U) /*!< DMA2 Channel 3 base address */ +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U) /*!< DMA2 Channel 4 base address */ +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U) /*!< DMA2 Channel 5 base address */ +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x0000046CU) /*!< DMA2 Channel 6 base address */ +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x00000480U) /*!< DMA2 Channel 7 base address */ +#define CRM_BASE (AHBPERIPH_BASE + 0x00001000U) /*!< CRM base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) /*!< CRC base address */ + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */ +#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */ +#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */ +#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ + +#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB OTG device FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG Peripheral Registers base address */ + +#define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ +#define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U /*!< USB OTG IN Endpoint Registers base address */ +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U /*!< USB OTG OUT Endpoint Registers base address */ +#define USB_OTG_EP_REG_SIZE 0x00000020U /*!< USB OTG All Endpoint Registers size address */ +#define USB_OTG_HOST_BASE 0x00000400U /*!< USB OTG Host Mode Registers base address */ +#define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ +#define USB_OTG_DEP3RMPEN_BASE 0x00000D0CU /*!< USB OTG DEP3RMPEN Registers base address */ +#define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ +#define USB_OTG_USBDIVRST_BASE 0x00000E10U /*!< USB OTG USBDIVRST Registers base address */ +#define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ +#define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CMP ((CMP_TypeDef *)CMP_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR5 ((TMR_TypeDef *)TMR5_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral registers bits definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Power Control (PWC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for PWC_CTRL register *******************/ +#define PWC_CTRL_VRSEL_Pos (0U) +#define PWC_CTRL_VRSEL_Msk (0x1U << PWC_CTRL_VRSEL_Pos) /*!< 0x00000001 */ +#define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ +#define PWC_CTRL_LPSEL_Pos (1U) +#define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep */ +#define PWC_CTRL_CLSWEF_Pos (2U) +#define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ +#define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ +#define PWC_CTRL_CLSEF_Pos (3U) +#define PWC_CTRL_CLSEF_Msk (0x1U << PWC_CTRL_CLSEF_Pos) /*!< 0x00000008 */ +#define PWC_CTRL_CLSEF PWC_CTRL_CLSEF_Msk /*!< Clear SEF flag */ +#define PWC_CTRL_PVMEN_Pos (4U) +#define PWC_CTRL_PVMEN_Msk (0x1U << PWC_CTRL_PVMEN_Pos) /*!< 0x00000010 */ +#define PWC_CTRL_PVMEN PWC_CTRL_PVMEN_Msk /*!< Power voltage monitoring enable */ + +/*!< PVM level configuration */ +#define PWC_CTRL_PVMSEL_Pos (5U) +#define PWC_CTRL_PVMSEL_Msk (0x7U << PWC_CTRL_PVMSEL_Pos) /*!< 0x000000E0 */ +#define PWC_CTRL_PVMSEL PWC_CTRL_PVMSEL_Msk /*!< PVMSEL[2:0] bits (Power voltage monitoring boundary select) */ +#define PWC_CTRL_PVMSEL_0 (0x1U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000020 */ +#define PWC_CTRL_PVMSEL_1 (0x2U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000040 */ +#define PWC_CTRL_PVMSEL_2 (0x4U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000080 */ + +#define PWC_CTRL_PVMSEL_LEV1 0x00000020U /*!< PVM level 2.3V */ +#define PWC_CTRL_PVMSEL_LEV2 0x00000040U /*!< PVM level 2.4V */ +#define PWC_CTRL_PVMSEL_LEV3 0x00000060U /*!< PVM level 2.5V */ +#define PWC_CTRL_PVMSEL_LEV4 0x00000080U /*!< PVM level 2.6V */ +#define PWC_CTRL_PVMSEL_LEV5 0x000000A0U /*!< PVM level 2.7V */ +#define PWC_CTRL_PVMSEL_LEV6 0x000000C0U /*!< PVM level 2.8V */ +#define PWC_CTRL_PVMSEL_LEV7 0x000000E0U /*!< PVM level 2.9V */ + +/* Legacy defines */ +#define PWC_CTRL_PVMSEL_2V3 PWC_CTRL_PVMSEL_LEV1 +#define PWC_CTRL_PVMSEL_2V4 PWC_CTRL_PVMSEL_LEV2 +#define PWC_CTRL_PVMSEL_2V5 PWC_CTRL_PVMSEL_LEV3 +#define PWC_CTRL_PVMSEL_2V6 PWC_CTRL_PVMSEL_LEV4 +#define PWC_CTRL_PVMSEL_2V7 PWC_CTRL_PVMSEL_LEV5 +#define PWC_CTRL_PVMSEL_2V8 PWC_CTRL_PVMSEL_LEV6 +#define PWC_CTRL_PVMSEL_2V9 PWC_CTRL_PVMSEL_LEV7 + +#define PWC_CTRL_BPWEN_Pos (8U) +#define PWC_CTRL_BPWEN_Msk (0x1U << PWC_CTRL_BPWEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRL_BPWEN PWC_CTRL_BPWEN_Msk /*!< Battery powered domain write enable */ + +/***************** Bit definition for PWC_CTRLSTS register ******************/ +#define PWC_CTRLSTS_SWEF_Pos (0U) +#define PWC_CTRLSTS_SWEF_Msk (0x1U << PWC_CTRLSTS_SWEF_Pos) /*!< 0x00000001 */ +#define PWC_CTRLSTS_SWEF PWC_CTRLSTS_SWEF_Msk /*!< Standby wake-up event flag */ +#define PWC_CTRLSTS_SEF_Pos (1U) +#define PWC_CTRLSTS_SEF_Msk (0x1U << PWC_CTRLSTS_SEF_Pos) /*!< 0x00000002 */ +#define PWC_CTRLSTS_SEF PWC_CTRLSTS_SEF_Msk /*!< Standby mode entry flag */ +#define PWC_CTRLSTS_PVMOF_Pos (2U) +#define PWC_CTRLSTS_PVMOF_Msk (0x1U << PWC_CTRLSTS_PVMOF_Pos) /*!< 0x00000004 */ +#define PWC_CTRLSTS_PVMOF PWC_CTRLSTS_PVMOF_Msk /*!< Power voltage monitoring output flag */ +#define PWC_CTRLSTS_SWPEN_Pos (8U) +#define PWC_CTRLSTS_SWPEN_Msk (0x1U << PWC_CTRLSTS_SWPEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRLSTS_SWPEN PWC_CTRLSTS_SWPEN_Msk /*!< Standby wake-up pin enable */ + +/******************************************************************************/ +/* */ +/* Clock and reset manage (CRM) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRM_CTRL register *******************/ +#define CRM_CTRL_HICKEN_Pos (0U) +#define CRM_CTRL_HICKEN_Msk (0x1U << CRM_CTRL_HICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRL_HICKEN CRM_CTRL_HICKEN_Msk /*!< High speed internal clock enable */ +#define CRM_CTRL_HICKSTBL_Pos (1U) +#define CRM_CTRL_HICKSTBL_Msk (0x1U << CRM_CTRL_HICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRL_HICKSTBL CRM_CTRL_HICKSTBL_Msk /*!< High speed internal clock stable */ +#define CRM_CTRL_HICKTRIM_Pos (2U) +#define CRM_CTRL_HICKTRIM_Msk (0x3FU << CRM_CTRL_HICKTRIM_Pos) /*!< 0x000000FC */ +#define CRM_CTRL_HICKTRIM CRM_CTRL_HICKTRIM_Msk /*!< High speed internal clock trimming */ +#define CRM_CTRL_HICKCAL_Pos (8U) +#define CRM_CTRL_HICKCAL_Msk (0xFFU << CRM_CTRL_HICKCAL_Pos) /*!< 0x0000FF00 */ +#define CRM_CTRL_HICKCAL CRM_CTRL_HICKCAL_Msk /*!< High speed internal clock calibration */ +#define CRM_CTRL_HEXTEN_Pos (16U) +#define CRM_CTRL_HEXTEN_Msk (0x1U << CRM_CTRL_HEXTEN_Pos) /*!< 0x00010000 */ +#define CRM_CTRL_HEXTEN CRM_CTRL_HEXTEN_Msk /*!< High speed external crystal enable */ +#define CRM_CTRL_HEXTSTBL_Pos (17U) +#define CRM_CTRL_HEXTSTBL_Msk (0x1U << CRM_CTRL_HEXTSTBL_Pos) /*!< 0x00020000 */ +#define CRM_CTRL_HEXTSTBL CRM_CTRL_HEXTSTBL_Msk /*!< High speed external crystal stable */ +#define CRM_CTRL_HEXTBYPS_Pos (18U) +#define CRM_CTRL_HEXTBYPS_Msk (0x1U << CRM_CTRL_HEXTBYPS_Pos) /*!< 0x00040000 */ +#define CRM_CTRL_HEXTBYPS CRM_CTRL_HEXTBYPS_Msk /*!< High speed external crystal bypass */ +#define CRM_CTRL_CFDEN_Pos (19U) +#define CRM_CTRL_CFDEN_Msk (0x1U << CRM_CTRL_CFDEN_Pos) /*!< 0x00080000 */ +#define CRM_CTRL_CFDEN CRM_CTRL_CFDEN_Msk /*!< Clock failure detector enable */ +#define CRM_CTRL_PLLEN_Pos (24U) +#define CRM_CTRL_PLLEN_Msk (0x1U << CRM_CTRL_PLLEN_Pos) /*!< 0x01000000 */ +#define CRM_CTRL_PLLEN CRM_CTRL_PLLEN_Msk /*!< PLL enable */ +#define CRM_CTRL_PLLSTBL_Pos (25U) +#define CRM_CTRL_PLLSTBL_Msk (0x1U << CRM_CTRL_PLLSTBL_Pos) /*!< 0x02000000 */ +#define CRM_CTRL_PLLSTBL CRM_CTRL_PLLSTBL_Msk /*!< PLL clock stable */ + +/******************* Bit definition for CRM_CFG register ********************/ +/*!< SCLKSEL configuration */ +#define CRM_CFG_SCLKSEL_Pos (0U) +#define CRM_CFG_SCLKSEL_Msk (0x3U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000003 */ +#define CRM_CFG_SCLKSEL CRM_CFG_SCLKSEL_Msk /*!< SCLKSEL[1:0] bits (System clock select) */ +#define CRM_CFG_SCLKSEL_0 (0x1U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000001 */ +#define CRM_CFG_SCLKSEL_1 (0x2U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000002 */ + +#define CRM_CFG_SCLKSEL_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSEL_HEXT 0x00000001U /*!< HEXT */ +#define CRM_CFG_SCLKSEL_PLL 0x00000002U /*!< PLL */ + +/*!< SCLKSTS configuration */ +#define CRM_CFG_SCLKSTS_Pos (2U) +#define CRM_CFG_SCLKSTS_Msk (0x3U << CRM_CFG_SCLKSTS_Pos) /*!< 0x0000000C */ +#define CRM_CFG_SCLKSTS CRM_CFG_SCLKSTS_Msk /*!< SCLKSTS[1:0] bits (System clock select status) */ +#define CRM_CFG_SCLKSTS_0 (0x1U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000004 */ +#define CRM_CFG_SCLKSTS_1 (0x2U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000008 */ + +#define CRM_CFG_SCLKSTS_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSTS_HEXT 0x00000004U /*!< HEXT */ +#define CRM_CFG_SCLKSTS_PLL 0x00000008U /*!< PLL */ + +/*!< AHBDIV configuration */ +#define CRM_CFG_AHBDIV_Pos (4U) +#define CRM_CFG_AHBDIV_Msk (0xFU << CRM_CFG_AHBDIV_Pos) /*!< 0x000000F0 */ +#define CRM_CFG_AHBDIV CRM_CFG_AHBDIV_Msk /*!< AHBDIV[3:0] bits (AHB division) */ +#define CRM_CFG_AHBDIV_0 (0x1U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000010 */ +#define CRM_CFG_AHBDIV_1 (0x2U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000020 */ +#define CRM_CFG_AHBDIV_2 (0x4U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000040 */ +#define CRM_CFG_AHBDIV_3 (0x8U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000080 */ + +#define CRM_CFG_AHBDIV_DIV1 0x00000000U /*!< SCLK is not divided */ +#define CRM_CFG_AHBDIV_DIV2 0x00000080U /*!< SCLK is divided by 2 */ +#define CRM_CFG_AHBDIV_DIV4 0x00000090U /*!< SCLK is divided by 4 */ +#define CRM_CFG_AHBDIV_DIV8 0x000000A0U /*!< SCLK is divided by 8 */ +#define CRM_CFG_AHBDIV_DIV16 0x000000B0U /*!< SCLK is divided by 16 */ +#define CRM_CFG_AHBDIV_DIV64 0x000000C0U /*!< SCLK is divided by 64 */ +#define CRM_CFG_AHBDIV_DIV128 0x000000D0U /*!< SCLK is divided by 128 */ +#define CRM_CFG_AHBDIV_DIV256 0x000000E0U /*!< SCLK is divided by 256 */ +#define CRM_CFG_AHBDIV_DIV512 0x000000F0U /*!< SCLK is divided by 512 */ + +/*!< APB1DIV configuration */ +#define CRM_CFG_APB1DIV_Pos (8U) +#define CRM_CFG_APB1DIV_Msk (0x7U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000700 */ +#define CRM_CFG_APB1DIV CRM_CFG_APB1DIV_Msk /*!< APB1DIV[2:0] bits (APB1 division) */ +#define CRM_CFG_APB1DIV_0 (0x1U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000100 */ +#define CRM_CFG_APB1DIV_1 (0x2U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000200 */ +#define CRM_CFG_APB1DIV_2 (0x4U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000400 */ + +#define CRM_CFG_APB1DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB1DIV_DIV2 0x00000400U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB1DIV_DIV4 0x00000500U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB1DIV_DIV8 0x00000600U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB1DIV_DIV16 0x00000700U /*!< HCLK is divided by 16 */ + +/*!< APB2DIV configuration */ +#define CRM_CFG_APB2DIV_Pos (11U) +#define CRM_CFG_APB2DIV_Msk (0x7U << CRM_CFG_APB2DIV_Pos) /*!< 0x00003800 */ +#define CRM_CFG_APB2DIV CRM_CFG_APB2DIV_Msk /*!< APB2DIV[2:0] bits (APB2 division) */ +#define CRM_CFG_APB2DIV_0 (0x1U << CRM_CFG_APB2DIV_Pos) /*!< 0x00000800 */ +#define CRM_CFG_APB2DIV_1 (0x2U << CRM_CFG_APB2DIV_Pos) /*!< 0x00001000 */ +#define CRM_CFG_APB2DIV_2 (0x4U << CRM_CFG_APB2DIV_Pos) /*!< 0x00002000 */ + +#define CRM_CFG_APB2DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB2DIV_DIV2 0x00002000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB2DIV_DIV4 0x00002800U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB2DIV_DIV8 0x00003000U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB2DIV_DIV16 0x00003800U /*!< HCLK is divided by 16 */ + +/*!< ADCDIV configuration */ +#define CRM_CFG_ADCDIV_Msk ((0x3U << 14) | (0x1U << 28)) /*!< 0x0100C000 */ +#define CRM_CFG_ADCDIV CRM_CFG_ADCDIV_Msk /*!< ADCDIV[2:0] bits (ADC division) */ +#define CRM_CFG_ADCDIV_0 (0x1U << 14) /*!< 0x00004000 */ +#define CRM_CFG_ADCDIV_1 (0x2U << 14) /*!< 0x00008000 */ +#define CRM_CFG_ADCDIV_2 (0x1U << 28) /*!< 0x10000000 */ + +#define CRM_CFG_ADCDIV_DIV2 0x00000000U /*!< PCLK/2 */ +#define CRM_CFG_ADCDIV_DIV4 0x00004000U /*!< PCLK/4 */ +#define CRM_CFG_ADCDIV_DIV6 0x00008000U /*!< PCLK/6 */ +#define CRM_CFG_ADCDIV_DIV8 0x0000C000U /*!< PCLK/8 */ +#define CRM_CFG_ADCDIV_DIV12 0x10004000U /*!< PCLK2/12 */ +#define CRM_CFG_ADCDIV_DIV16 0x1000C000U /*!< PCLK2/16 */ + +#define CRM_CFG_PLLRCS_Pos (16U) +#define CRM_CFG_PLLRCS_Msk (0x1U << CRM_CFG_PLLRCS_Pos) /*!< 0x00010000 */ +#define CRM_CFG_PLLRCS CRM_CFG_PLLRCS_Msk /*!< PLL entry clock select */ + +#define CRM_CFG_PLLHEXTDIV_Pos (17U) +#define CRM_CFG_PLLHEXTDIV_Msk (0x1U << CRM_CFG_PLLHEXTDIV_Pos) /*!< 0x00020000 */ +#define CRM_CFG_PLLHEXTDIV CRM_CFG_PLLHEXTDIV_Msk /*!< HEXT division selection for PLL entry clock */ + +/*!< PLLMULT configuration */ +#define CRM_CFG_PLLMULT_Msk ((0xFU << 18) | (0x3U << 29)) /*!< 0x603C0000 */ +#define CRM_CFG_PLLMULT CRM_CFG_PLLMULT_Msk /*!< PLLMULT[5:0] bits (PLL multiplication factor) */ +#define CRM_CFG_PLLMULT_0 (0x1U << 18) /*!< 0x00040000 */ +#define CRM_CFG_PLLMULT_1 (0x2U << 18) /*!< 0x00080000 */ +#define CRM_CFG_PLLMULT_2 (0x4U << 18) /*!< 0x00100000 */ +#define CRM_CFG_PLLMULT_3 (0x8U << 18) /*!< 0x00200000 */ +#define CRM_CFG_PLLMULT_4 (0x1U << 29) /*!< 0x20000000 */ +#define CRM_CFG_PLLMULT_5 (0x2U << 29) /*!< 0x40000000 */ + +#define CRM_CFG_PLLMULT_MULT2 0x00000000U /*!< PLL input clock * 2 */ +#define CRM_CFG_PLLMULT_MULT3_Pos (18U) +#define CRM_CFG_PLLMULT_MULT3_Msk (0x1U << CRM_CFG_PLLMULT_MULT3_Pos) /*!< 0x00040000 */ +#define CRM_CFG_PLLMULT_MULT3 CRM_CFG_PLLMULT_MULT3_Msk /*!< PLL input clock * 3 */ +#define CRM_CFG_PLLMULT_MULT4_Pos (19U) +#define CRM_CFG_PLLMULT_MULT4_Msk (0x1U << CRM_CFG_PLLMULT_MULT4_Pos) /*!< 0x00080000 */ +#define CRM_CFG_PLLMULT_MULT4 CRM_CFG_PLLMULT_MULT4_Msk /*!< PLL input clock * 4 */ +#define CRM_CFG_PLLMULT_MULT5_Pos (18U) +#define CRM_CFG_PLLMULT_MULT5_Msk (0x3U << CRM_CFG_PLLMULT_MULT5_Pos) /*!< 0x000C0000 */ +#define CRM_CFG_PLLMULT_MULT5 CRM_CFG_PLLMULT_MULT5_Msk /*!< PLL input clock * 5 */ +#define CRM_CFG_PLLMULT_MULT6_Pos (20U) +#define CRM_CFG_PLLMULT_MULT6_Msk (0x1U << CRM_CFG_PLLMULT_MULT6_Pos) /*!< 0x00100000 */ +#define CRM_CFG_PLLMULT_MULT6 CRM_CFG_PLLMULT_MULT6_Msk /*!< PLL input clock * 6 */ +#define CRM_CFG_PLLMULT_MULT7_Pos (18U) +#define CRM_CFG_PLLMULT_MULT7_Msk (0x5U << CRM_CFG_PLLMULT_MULT7_Pos) /*!< 0x00140000 */ +#define CRM_CFG_PLLMULT_MULT7 CRM_CFG_PLLMULT_MULT7_Msk /*!< PLL input clock * 7 */ +#define CRM_CFG_PLLMULT_MULT8_Pos (19U) +#define CRM_CFG_PLLMULT_MULT8_Msk (0x3U << CRM_CFG_PLLMULT_MULT8_Pos) /*!< 0x00180000 */ +#define CRM_CFG_PLLMULT_MULT8 CRM_CFG_PLLMULT_MULT8_Msk /*!< PLL input clock * 8 */ +#define CRM_CFG_PLLMULT_MULT9_Pos (18U) +#define CRM_CFG_PLLMULT_MULT9_Msk (0x7U << CRM_CFG_PLLMULT_MULT9_Pos) /*!< 0x001C0000 */ +#define CRM_CFG_PLLMULT_MULT9 CRM_CFG_PLLMULT_MULT9_Msk /*!< PLL input clock * 9 */ +#define CRM_CFG_PLLMULT_MULT10_Pos (21U) +#define CRM_CFG_PLLMULT_MULT10_Msk (0x1U << CRM_CFG_PLLMULT_MULT10_Pos) /*!< 0x00200000 */ +#define CRM_CFG_PLLMULT_MULT10 CRM_CFG_PLLMULT_MULT10_Msk /*!< PLL input clock * 10 */ +#define CRM_CFG_PLLMULT_MULT11_Pos (18U) +#define CRM_CFG_PLLMULT_MULT11_Msk (0x9U << CRM_CFG_PLLMULT_MULT11_Pos) /*!< 0x00240000 */ +#define CRM_CFG_PLLMULT_MULT11 CRM_CFG_PLLMULT_MULT11_Msk /*!< PLL input clock * 11 */ +#define CRM_CFG_PLLMULT_MULT12_Pos (19U) +#define CRM_CFG_PLLMULT_MULT12_Msk (0x5U << CRM_CFG_PLLMULT_MULT12_Pos) /*!< 0x00280000 */ +#define CRM_CFG_PLLMULT_MULT12 CRM_CFG_PLLMULT_MULT12_Msk /*!< PLL input clock * 12 */ +#define CRM_CFG_PLLMULT_MULT13_Pos (18U) +#define CRM_CFG_PLLMULT_MULT13_Msk (0xBU << CRM_CFG_PLLMULT_MULT13_Pos) /*!< 0x002C0000 */ +#define CRM_CFG_PLLMULT_MULT13 CRM_CFG_PLLMULT_MULT13_Msk /*!< PLL input clock * 13 */ +#define CRM_CFG_PLLMULT_MULT14_Pos (20U) +#define CRM_CFG_PLLMULT_MULT14_Msk (0x3U << CRM_CFG_PLLMULT_MULT14_Pos) /*!< 0x00300000 */ +#define CRM_CFG_PLLMULT_MULT14 CRM_CFG_PLLMULT_MULT14_Msk /*!< PLL input clock * 14 */ +#define CRM_CFG_PLLMULT_MULT15_Pos (18U) +#define CRM_CFG_PLLMULT_MULT15_Msk (0xDU << CRM_CFG_PLLMULT_MULT15_Pos) /*!< 0x00340000 */ +#define CRM_CFG_PLLMULT_MULT15 CRM_CFG_PLLMULT_MULT15_Msk /*!< PLL input clock * 15 */ +#define CRM_CFG_PLLMULT_MULT16_Pos (19U) +#define CRM_CFG_PLLMULT_MULT16_Msk (0x7U << CRM_CFG_PLLMULT_MULT16_Pos) /*!< 0x00380000 */ +#define CRM_CFG_PLLMULT_MULT16 CRM_CFG_PLLMULT_MULT16_Msk /*!< PLL input clock * 16 */ +#define CRM_CFG_PLLMULT_MULT17 0x20000000U /*!< PLL input clock * 17 */ +#define CRM_CFG_PLLMULT_MULT18 0x20040000U /*!< PLL input clock * 18 */ +#define CRM_CFG_PLLMULT_MULT19 0x20080000U /*!< PLL input clock * 19 */ +#define CRM_CFG_PLLMULT_MULT20 0x200C0000U /*!< PLL input clock * 20 */ +#define CRM_CFG_PLLMULT_MULT21 0x20100000U /*!< PLL input clock * 21 */ +#define CRM_CFG_PLLMULT_MULT22 0x20140000U /*!< PLL input clock * 22 */ +#define CRM_CFG_PLLMULT_MULT23 0x20180000U /*!< PLL input clock * 23 */ +#define CRM_CFG_PLLMULT_MULT24 0x201C0000U /*!< PLL input clock * 24 */ +#define CRM_CFG_PLLMULT_MULT25 0x20200000U /*!< PLL input clock * 25 */ +#define CRM_CFG_PLLMULT_MULT26 0x20240000U /*!< PLL input clock * 26 */ +#define CRM_CFG_PLLMULT_MULT27 0x20280000U /*!< PLL input clock * 27 */ +#define CRM_CFG_PLLMULT_MULT28 0x202C0000U /*!< PLL input clock * 28 */ +#define CRM_CFG_PLLMULT_MULT29 0x20300000U /*!< PLL input clock * 29 */ +#define CRM_CFG_PLLMULT_MULT30 0x20340000U /*!< PLL input clock * 30 */ +#define CRM_CFG_PLLMULT_MULT31 0x20380000U /*!< PLL input clock * 31 */ +#define CRM_CFG_PLLMULT_MULT32 0x203C0000U /*!< PLL input clock * 32 */ +#define CRM_CFG_PLLMULT_MULT33 0x40000000U /*!< PLL input clock * 33 */ +#define CRM_CFG_PLLMULT_MULT34 0x40040000U /*!< PLL input clock * 34 */ +#define CRM_CFG_PLLMULT_MULT35 0x40080000U /*!< PLL input clock * 35 */ +#define CRM_CFG_PLLMULT_MULT36 0x400C0000U /*!< PLL input clock * 36 */ +#define CRM_CFG_PLLMULT_MULT37 0x40100000U /*!< PLL input clock * 37 */ +#define CRM_CFG_PLLMULT_MULT38 0x40140000U /*!< PLL input clock * 38 */ +#define CRM_CFG_PLLMULT_MULT39 0x40180000U /*!< PLL input clock * 39 */ +#define CRM_CFG_PLLMULT_MULT40 0x401C0000U /*!< PLL input clock * 40 */ +#define CRM_CFG_PLLMULT_MULT41 0x40200000U /*!< PLL input clock * 41 */ +#define CRM_CFG_PLLMULT_MULT42 0x40240000U /*!< PLL input clock * 42 */ +#define CRM_CFG_PLLMULT_MULT43 0x40280000U /*!< PLL input clock * 43 */ +#define CRM_CFG_PLLMULT_MULT44 0x402C0000U /*!< PLL input clock * 44 */ +#define CRM_CFG_PLLMULT_MULT45 0x40300000U /*!< PLL input clock * 45 */ +#define CRM_CFG_PLLMULT_MULT46 0x40340000U /*!< PLL input clock * 46 */ +#define CRM_CFG_PLLMULT_MULT47 0x40380000U /*!< PLL input clock * 47 */ +#define CRM_CFG_PLLMULT_MULT48 0x403C0000U /*!< PLL input clock * 48 */ +#define CRM_CFG_PLLMULT_MULT49 0x60000000U /*!< PLL input clock * 49 */ +#define CRM_CFG_PLLMULT_MULT50 0x60040000U /*!< PLL input clock * 50 */ +#define CRM_CFG_PLLMULT_MULT51 0x60080000U /*!< PLL input clock * 51 */ +#define CRM_CFG_PLLMULT_MULT52 0x600C0000U /*!< PLL input clock * 52 */ +#define CRM_CFG_PLLMULT_MULT53 0x60100000U /*!< PLL input clock * 53 */ +#define CRM_CFG_PLLMULT_MULT54 0x60140000U /*!< PLL input clock * 54 */ +#define CRM_CFG_PLLMULT_MULT55 0x60180000U /*!< PLL input clock * 55 */ +#define CRM_CFG_PLLMULT_MULT56 0x601C0000U /*!< PLL input clock * 56 */ +#define CRM_CFG_PLLMULT_MULT57 0x60200000U /*!< PLL input clock * 57 */ +#define CRM_CFG_PLLMULT_MULT58 0x60240000U /*!< PLL input clock * 58 */ +#define CRM_CFG_PLLMULT_MULT59 0x60280000U /*!< PLL input clock * 59 */ +#define CRM_CFG_PLLMULT_MULT60 0x602C0000U /*!< PLL input clock * 60 */ +#define CRM_CFG_PLLMULT_MULT61 0x60300000U /*!< PLL input clock * 61 */ +#define CRM_CFG_PLLMULT_MULT62 0x60340000U /*!< PLL input clock * 62 */ +#define CRM_CFG_PLLMULT_MULT63 0x60380000U /*!< PLL input clock * 63 */ +#define CRM_CFG_PLLMULT_MULT64 0x603C0000U /*!< PLL input clock * 64 */ + +/*!< USBDIV configuration */ +#define CRM_CFG_USBDIV_Msk ((0x3U << 22) | (0x1U << 27)) /*!< 0x08C00000 */ +#define CRM_CFG_USBDIV CRM_CFG_USBDIV_Msk /*!< USBDIV[2:0] bits (USB division factor) */ +#define CRM_CFG_USBDIV_0 (0x1U << 22) /*!< 0x00400000 */ +#define CRM_CFG_USBDIV_1 (0x2U << 22) /*!< 0x00800000 */ +#define CRM_CFG_USBDIV_2 (0x1U << 27) /*!< 0x08000000 */ + +#define CRM_CFG_USBDIV_DIV1_5 0x00000000U /*!< PLL/1.5 */ +#define CRM_CFG_USBDIV_DIV1 0x00400000U /*!< PLL/1 */ +#define CRM_CFG_USBDIV_DIV2_5 0x00800000U /*!< PLL/2.5 */ +#define CRM_CFG_USBDIV_DIV2 0x00C00000U /*!< PLL/2 */ +#define CRM_CFG_USBDIV_DIV3_5 0x08000000U /*!< PLL/3.5 */ +#define CRM_CFG_USBDIV_DIV3 0x08400000U /*!< PLL/3 */ +#define CRM_CFG_USBDIV_DIV4 0x08800000U /*!< PLL/4 */ + +/*!< CLKOUT_SEL configuration */ +#define CRM_CFG_CLKOUT_SEL_Msk ((CRM_MISC1_CLKOUT_SEL) | (0x7U << 24)) /*!< 0x07010000 */ +#define CRM_CFG_CLKOUT_SEL CRM_CFG_CLKOUT_SEL_Msk /*!< CLKOUT_SEL[3:0] bits (Clock output selection) */ +#define CRM_CFG_CLKOUT_SEL_0 (0x1U << 24) /*!< 0x01000000 */ +#define CRM_CFG_CLKOUT_SEL_1 (0x2U << 24) /*!< 0x02000000 */ +#define CRM_CFG_CLKOUT_SEL_2 (0x4U << 24) /*!< 0x04000000 */ +#define CRM_CFG_CLKOUT_SEL_3 CRM_MISC1_CLKOUT_SEL /*!< 0x00010000 */ + +#define CRM_CFG_CLKOUT_SEL_NOCLOCK 0x00000000U /*!< Not clock output */ +#define CRM_CFG_CLKOUT_SEL_LICK 0x02000000U /*!< LICK */ +#define CRM_CFG_CLKOUT_SEL_LEXT 0x03000000U /*!< LEXT */ +#define CRM_CFG_CLKOUT_SEL_SCLK 0x04000000U /*!< SCLK */ +#define CRM_CFG_CLKOUT_SEL_HICK 0x05000000U /*!< HICK */ +#define CRM_CFG_CLKOUT_SEL_HEXT 0x06000000U /*!< HEXT */ +#define CRM_CFG_CLKOUT_SEL_PLL_DIV2 0x07000000U /*!< PLL/2 */ +#define CRM_MISC1_CLKOUT_SEL_PLL_DIV4 0x04010000U /*!< PLL/4 */ +#define CRM_MISC1_CLKOUT_SEL_USB 0x05010000U /*!< USB */ +#define CRM_MISC1_CLKOUT_SEL_ADC 0x06010000U /*!< ADC */ + +/* Reference defines */ +#define CRM_CFG_CLKSEL CRM_CFG_CLKOUT_SEL +#define CRM_CFG_CLKSEL_0 CRM_CFG_CLKOUT_SEL_0 +#define CRM_CFG_CLKSEL_1 CRM_CFG_CLKOUT_SEL_1 +#define CRM_CFG_CLKSEL_2 CRM_CFG_CLKOUT_SEL_2 +#define CRM_CFG_CLKSEL_NOCLOCK CRM_CFG_CLKOUT_SEL_NOCLOCK +#define CRM_CFG_CLKSEL_LICK CRM_CFG_CLKOUT_SEL_LICK +#define CRM_CFG_CLKSEL_LEXT CRM_CFG_CLKOUT_SEL_LEXT +#define CRM_CFG_CLKSEL_SCLK CRM_CFG_CLKOUT_SEL_SCLK +#define CRM_CFG_CLKSEL_HICK CRM_CFG_CLKOUT_SEL_HICK +#define CRM_CFG_CLKSEL_HEXT CRM_CFG_CLKOUT_SEL_HEXT +#define CRM_CFG_CLKSEL_PLL_DIV2 CRM_CFG_CLKOUT_SEL_PLL_DIV2 +#define CRM_MISC1_CLKSEL_PLL_DIV4 CRM_MISC1_CLKOUT_SEL_PLL_DIV4 +#define CRM_MISC1_CLKSEL_USB CRM_MISC1_CLKOUT_SEL_USB +#define CRM_MISC1_CLKSEL_ADC CRM_MISC1_CLKOUT_SEL_ADC + +/*!<*************** Bit definition for CRM_CLKINT register ******************/ +#define CRM_CLKINT_LICKSTBLF_Pos (0U) +#define CRM_CLKINT_LICKSTBLF_Msk (0x1U << CRM_CLKINT_LICKSTBLF_Pos) /*!< 0x00000001 */ +#define CRM_CLKINT_LICKSTBLF CRM_CLKINT_LICKSTBLF_Msk /*!< LICK stable interrupt flag */ +#define CRM_CLKINT_LEXTSTBLF_Pos (1U) +#define CRM_CLKINT_LEXTSTBLF_Msk (0x1U << CRM_CLKINT_LEXTSTBLF_Pos) /*!< 0x00000002 */ +#define CRM_CLKINT_LEXTSTBLF CRM_CLKINT_LEXTSTBLF_Msk /*!< LEXT stable flag */ +#define CRM_CLKINT_HICKSTBLF_Pos (2U) +#define CRM_CLKINT_HICKSTBLF_Msk (0x1U << CRM_CLKINT_HICKSTBLF_Pos) /*!< 0x00000004 */ +#define CRM_CLKINT_HICKSTBLF CRM_CLKINT_HICKSTBLF_Msk /*!< HICK stable flag */ +#define CRM_CLKINT_HEXTSTBLF_Pos (3U) +#define CRM_CLKINT_HEXTSTBLF_Msk (0x1U << CRM_CLKINT_HEXTSTBLF_Pos) /*!< 0x00000008 */ +#define CRM_CLKINT_HEXTSTBLF CRM_CLKINT_HEXTSTBLF_Msk /*!< HEXT stable flag */ +#define CRM_CLKINT_PLLSTBLF_Pos (4U) +#define CRM_CLKINT_PLLSTBLF_Msk (0x1U << CRM_CLKINT_PLLSTBLF_Pos) /*!< 0x00000010 */ +#define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ +#define CRM_CLKINT_CFDF_Pos (7U) +#define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock Failure Detection flag */ +#define CRM_CLKINT_LICKSTBLIEN_Pos (8U) +#define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ +#define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ +#define CRM_CLKINT_LEXTSTBLIEN_Pos (9U) +#define CRM_CLKINT_LEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_LEXTSTBLIEN_Pos) /*!< 0x00000200 */ +#define CRM_CLKINT_LEXTSTBLIEN CRM_CLKINT_LEXTSTBLIEN_Msk /*!< LEXT stable interrupt enable */ +#define CRM_CLKINT_HICKSTBLIEN_Pos (10U) +#define CRM_CLKINT_HICKSTBLIEN_Msk (0x1U << CRM_CLKINT_HICKSTBLIEN_Pos) /*!< 0x00000400 */ +#define CRM_CLKINT_HICKSTBLIEN CRM_CLKINT_HICKSTBLIEN_Msk /*!< HICK stable interrupt enable */ +#define CRM_CLKINT_HEXTSTBLIEN_Pos (11U) +#define CRM_CLKINT_HEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_HEXTSTBLIEN_Pos) /*!< 0x00000800 */ +#define CRM_CLKINT_HEXTSTBLIEN CRM_CLKINT_HEXTSTBLIEN_Msk /*!< HEXT stable interrupt enable */ +#define CRM_CLKINT_PLLSTBLIEN_Pos (12U) +#define CRM_CLKINT_PLLSTBLIEN_Msk (0x1U << CRM_CLKINT_PLLSTBLIEN_Pos) /*!< 0x00001000 */ +#define CRM_CLKINT_PLLSTBLIEN CRM_CLKINT_PLLSTBLIEN_Msk /*!< PLL stable interrupt enable */ +#define CRM_CLKINT_LICKSTBLFC_Pos (16U) +#define CRM_CLKINT_LICKSTBLFC_Msk (0x1U << CRM_CLKINT_LICKSTBLFC_Pos) /*!< 0x00010000 */ +#define CRM_CLKINT_LICKSTBLFC CRM_CLKINT_LICKSTBLFC_Msk /*!< LICK stable flag clear */ +#define CRM_CLKINT_LEXTSTBLFC_Pos (17U) +#define CRM_CLKINT_LEXTSTBLFC_Msk (0x1U << CRM_CLKINT_LEXTSTBLFC_Pos) /*!< 0x00020000 */ +#define CRM_CLKINT_LEXTSTBLFC CRM_CLKINT_LEXTSTBLFC_Msk /*!< LEXT stable flag clear */ +#define CRM_CLKINT_HICKSTBLFC_Pos (18U) +#define CRM_CLKINT_HICKSTBLFC_Msk (0x1U << CRM_CLKINT_HICKSTBLFC_Pos) /*!< 0x00040000 */ +#define CRM_CLKINT_HICKSTBLFC CRM_CLKINT_HICKSTBLFC_Msk /*!< HICK stable flag clear */ +#define CRM_CLKINT_HEXTSTBLFC_Pos (19U) +#define CRM_CLKINT_HEXTSTBLFC_Msk (0x1U << CRM_CLKINT_HEXTSTBLFC_Pos) /*!< 0x00080000 */ +#define CRM_CLKINT_HEXTSTBLFC CRM_CLKINT_HEXTSTBLFC_Msk /*!< HEXT stable flag clear */ +#define CRM_CLKINT_PLLSTBLFC_Pos (20U) +#define CRM_CLKINT_PLLSTBLFC_Msk (0x1U << CRM_CLKINT_PLLSTBLFC_Pos) /*!< 0x00100000 */ +#define CRM_CLKINT_PLLSTBLFC CRM_CLKINT_PLLSTBLFC_Msk /*!< PLL stable flag clear */ +#define CRM_CLKINT_CFDFC_Pos (23U) +#define CRM_CLKINT_CFDFC_Msk (0x1U << CRM_CLKINT_CFDFC_Pos) /*!< 0x00800000 */ +#define CRM_CLKINT_CFDFC CRM_CLKINT_CFDFC_Msk /*!< Clock failure detection flag clear */ + +/***************** Bit definition for CRM_APB2RST register ******************/ +#define CRM_APB2RST_IOMUXRST_Pos (0U) +#define CRM_APB2RST_IOMUXRST_Msk (0x1U << CRM_APB2RST_IOMUXRST_Pos) /*!< 0x00000001 */ +#define CRM_APB2RST_IOMUXRST CRM_APB2RST_IOMUXRST_Msk /*!< IOMUX reset */ +#define CRM_APB2RST_EXINTRST_Pos (1U) +#define CRM_APB2RST_EXINTRST_Msk (0x1U << CRM_APB2RST_EXINTRST_Pos) /*!< 0x00000002 */ +#define CRM_APB2RST_EXINTRST CRM_APB2RST_EXINTRST_Msk /*!< EXINT reset */ +#define CRM_APB2RST_GPIOARST_Pos (2U) +#define CRM_APB2RST_GPIOARST_Msk (0x1U << CRM_APB2RST_GPIOARST_Pos) /*!< 0x00000004 */ +#define CRM_APB2RST_GPIOARST CRM_APB2RST_GPIOARST_Msk /*!< GPIOA reset */ +#define CRM_APB2RST_GPIOBRST_Pos (3U) +#define CRM_APB2RST_GPIOBRST_Msk (0x1U << CRM_APB2RST_GPIOBRST_Pos) /*!< 0x00000008 */ +#define CRM_APB2RST_GPIOBRST CRM_APB2RST_GPIOBRST_Msk /*!< GPIOB reset */ +#define CRM_APB2RST_GPIOCRST_Pos (4U) +#define CRM_APB2RST_GPIOCRST_Msk (0x1U << CRM_APB2RST_GPIOCRST_Pos) /*!< 0x00000010 */ +#define CRM_APB2RST_GPIOCRST CRM_APB2RST_GPIOCRST_Msk /*!< GPIOC reset */ +#define CRM_APB2RST_GPIODRST_Pos (5U) +#define CRM_APB2RST_GPIODRST_Msk (0x1U << CRM_APB2RST_GPIODRST_Pos) /*!< 0x00000020 */ +#define CRM_APB2RST_GPIODRST CRM_APB2RST_GPIODRST_Msk /*!< GPIOD reset */ +#define CRM_APB2RST_GPIOFRST_Pos (7U) +#define CRM_APB2RST_GPIOFRST_Msk (0x1U << CRM_APB2RST_GPIOFRST_Pos) /*!< 0x00000080 */ +#define CRM_APB2RST_GPIOFRST CRM_APB2RST_GPIOFRST_Msk /*!< GPIOF reset */ +#define CRM_APB2RST_ADC1RST_Pos (9U) +#define CRM_APB2RST_ADC1RST_Msk (0x1U << CRM_APB2RST_ADC1RST_Pos) /*!< 0x00000200 */ +#define CRM_APB2RST_ADC1RST CRM_APB2RST_ADC1RST_Msk /*!< ADC1 reset */ +#define CRM_APB2RST_TMR1RST_Pos (11U) +#define CRM_APB2RST_TMR1RST_Msk (0x1U << CRM_APB2RST_TMR1RST_Pos) /*!< 0x00000800 */ +#define CRM_APB2RST_TMR1RST CRM_APB2RST_TMR1RST_Msk /*!< TMR1 reset */ +#define CRM_APB2RST_SPI1RST_Pos (12U) +#define CRM_APB2RST_SPI1RST_Msk (0x1U << CRM_APB2RST_SPI1RST_Pos) /*!< 0x00001000 */ +#define CRM_APB2RST_SPI1RST CRM_APB2RST_SPI1RST_Msk /*!< SPI1 reset */ +#define CRM_APB2RST_USART1RST_Pos (14U) +#define CRM_APB2RST_USART1RST_Msk (0x1U << CRM_APB2RST_USART1RST_Pos) /*!< 0x00004000 */ +#define CRM_APB2RST_USART1RST CRM_APB2RST_USART1RST_Msk /*!< USART1 reset */ +#define CRM_APB2RST_TMR9RST_Pos (19U) +#define CRM_APB2RST_TMR9RST_Msk (0x1U << CRM_APB2RST_TMR9RST_Pos) /*!< 0x00080000 */ +#define CRM_APB2RST_TMR9RST CRM_APB2RST_TMR9RST_Msk /*!< TMR9 reset */ +#define CRM_APB2RST_TMR10RST_Pos (20U) +#define CRM_APB2RST_TMR10RST_Msk (0x1U << CRM_APB2RST_TMR10RST_Pos) /*!< 0x00100000 */ +#define CRM_APB2RST_TMR10RST CRM_APB2RST_TMR10RST_Msk /*!< TMR10 reset */ +#define CRM_APB2RST_TMR11RST_Pos (21U) +#define CRM_APB2RST_TMR11RST_Msk (0x1U << CRM_APB2RST_TMR11RST_Pos) /*!< 0x00200000 */ +#define CRM_APB2RST_TMR11RST CRM_APB2RST_TMR11RST_Msk /*!< TMR11 reset */ + +/***************** Bit definition for CRM_APB1RST register ******************/ +#define CRM_APB1RST_TMR2RST_Pos (0U) +#define CRM_APB1RST_TMR2RST_Msk (0x1U << CRM_APB1RST_TMR2RST_Pos) /*!< 0x00000001 */ +#define CRM_APB1RST_TMR2RST CRM_APB1RST_TMR2RST_Msk /*!< TMR2 reset */ +#define CRM_APB1RST_TMR3RST_Pos (1U) +#define CRM_APB1RST_TMR3RST_Msk (0x1U << CRM_APB1RST_TMR3RST_Pos) /*!< 0x00000002 */ +#define CRM_APB1RST_TMR3RST CRM_APB1RST_TMR3RST_Msk /*!< TMR3 reset */ +#define CRM_APB1RST_TMR4RST_Pos (2U) +#define CRM_APB1RST_TMR4RST_Msk (0x1U << CRM_APB1RST_TMR4RST_Pos) /*!< 0x00000004 */ +#define CRM_APB1RST_TMR4RST CRM_APB1RST_TMR4RST_Msk /*!< TMR4 reset */ +#define CRM_APB1RST_TMR5RST_Pos (3U) +#define CRM_APB1RST_TMR5RST_Msk (0x1U << CRM_APB1RST_TMR5RST_Pos) /*!< 0x00000008 */ +#define CRM_APB1RST_TMR5RST CRM_APB1RST_TMR5RST_Msk /*!< TMR5 reset */ +#define CRM_APB1RST_CMPRST_Pos (9U) +#define CRM_APB1RST_CMPRST_Msk (0x1U << CRM_APB1RST_CMPRST_Pos) /*!< 0x00000200 */ +#define CRM_APB1RST_CMPRST CRM_APB1RST_CMPRST_Msk /*!< CMP reset */ +#define CRM_APB1RST_WWDTRST_Pos (11U) +#define CRM_APB1RST_WWDTRST_Msk (0x1U << CRM_APB1RST_WWDTRST_Pos) /*!< 0x00000800 */ +#define CRM_APB1RST_WWDTRST CRM_APB1RST_WWDTRST_Msk /*!< WWDT reset */ +#define CRM_APB1RST_SPI2RST_Pos (14U) +#define CRM_APB1RST_SPI2RST_Msk (0x1U << CRM_APB1RST_SPI2RST_Pos) /*!< 0x00004000 */ +#define CRM_APB1RST_SPI2RST CRM_APB1RST_SPI2RST_Msk /*!< SPI2 reset */ +#define CRM_APB1RST_USART2RST_Pos (17U) +#define CRM_APB1RST_USART2RST_Msk (0x1U << CRM_APB1RST_USART2RST_Pos) /*!< 0x00020000 */ +#define CRM_APB1RST_USART2RST CRM_APB1RST_USART2RST_Msk /*!< USART2 reset */ +#define CRM_APB1RST_I2C1RST_Pos (21U) +#define CRM_APB1RST_I2C1RST_Msk (0x1U << CRM_APB1RST_I2C1RST_Pos) /*!< 0x00200000 */ +#define CRM_APB1RST_I2C1RST CRM_APB1RST_I2C1RST_Msk /*!< I2C1 reset */ +#define CRM_APB1RST_I2C2RST_Pos (22U) +#define CRM_APB1RST_I2C2RST_Msk (0x1U << CRM_APB1RST_I2C2RST_Pos) /*!< 0x00400000 */ +#define CRM_APB1RST_I2C2RST CRM_APB1RST_I2C2RST_Msk /*!< I2C2 reset */ +#define CRM_APB1RST_CAN1RST_Pos (25U) +#define CRM_APB1RST_CAN1RST_Msk (0x1U << CRM_APB1RST_CAN1RST_Pos) /*!< 0x02000000 */ +#define CRM_APB1RST_CAN1RST CRM_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ +#define CRM_APB1RST_PWCRST_Pos (28U) +#define CRM_APB1RST_PWCRST_Msk (0x1U << CRM_APB1RST_PWCRST_Pos) /*!< 0x10000000 */ +#define CRM_APB1RST_PWCRST CRM_APB1RST_PWCRST_Msk /*!< PWC reset */ + +/****************** Bit definition for CRM_AHBEN register *******************/ +#define CRM_AHBEN_DMA1EN_Pos (0U) +#define CRM_AHBEN_DMA1EN_Msk (0x1U << CRM_AHBEN_DMA1EN_Pos) /*!< 0x00000001 */ +#define CRM_AHBEN_DMA1EN CRM_AHBEN_DMA1EN_Msk /*!< DMA1 clock enable */ +#define CRM_AHBEN_DMA2EN_Pos (1U) +#define CRM_AHBEN_DMA2EN_Msk (0x1U << CRM_AHBEN_DMA2EN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN_DMA2EN CRM_AHBEN_DMA2EN_Msk /*!< DMA2 clock enable */ +#define CRM_AHBEN_SRAMEN_Pos (2U) +#define CRM_AHBEN_SRAMEN_Msk (0x1U << CRM_AHBEN_SRAMEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBEN_SRAMEN CRM_AHBEN_SRAMEN_Msk /*!< SRAM clock enable */ +#define CRM_AHBEN_FLASHEN_Pos (4U) +#define CRM_AHBEN_FLASHEN_Msk (0x1U << CRM_AHBEN_FLASHEN_Pos) /*!< 0x00000010 */ +#define CRM_AHBEN_FLASHEN CRM_AHBEN_FLASHEN_Msk /*!< Flash clock enable */ +#define CRM_AHBEN_CRCEN_Pos (6U) +#define CRM_AHBEN_CRCEN_Msk (0x1U << CRM_AHBEN_CRCEN_Pos) /*!< 0x00000040 */ +#define CRM_AHBEN_CRCEN CRM_AHBEN_CRCEN_Msk /*!< CRC clock enable */ +#define CRM_AHBEN_SDIOEN_Pos (10U) +#define CRM_AHBEN_SDIOEN_Msk (0x1U << CRM_AHBEN_SDIOEN_Pos) /*!< 0x00000400 */ +#define CRM_AHBEN_SDIOEN CRM_AHBEN_SDIOEN_Msk /*!< SDIO clock enable */ +#define CRM_AHBEN_OTGFSEN_Pos (12U) +#define CRM_AHBEN_OTGFSEN_Msk (0x1U << CRM_AHBEN_OTGFSEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBEN_OTGFSEN CRM_AHBEN_OTGFSEN_Msk /*!< OTGFS clock enable */ + +/****************** Bit definition for CRM_APB2EN register ******************/ +#define CRM_APB2EN_IOMUXEN_Pos (0U) +#define CRM_APB2EN_IOMUXEN_Msk (0x1U << CRM_APB2EN_IOMUXEN_Pos) /*!< 0x00000001 */ +#define CRM_APB2EN_IOMUXEN CRM_APB2EN_IOMUXEN_Msk /*!< IOMUX clock enable */ +#define CRM_APB2EN_GPIOAEN_Pos (2U) +#define CRM_APB2EN_GPIOAEN_Msk (0x1U << CRM_APB2EN_GPIOAEN_Pos) /*!< 0x00000004 */ +#define CRM_APB2EN_GPIOAEN CRM_APB2EN_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define CRM_APB2EN_GPIOBEN_Pos (3U) +#define CRM_APB2EN_GPIOBEN_Msk (0x1U << CRM_APB2EN_GPIOBEN_Pos) /*!< 0x00000008 */ +#define CRM_APB2EN_GPIOBEN CRM_APB2EN_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define CRM_APB2EN_GPIOCEN_Pos (4U) +#define CRM_APB2EN_GPIOCEN_Msk (0x1U << CRM_APB2EN_GPIOCEN_Pos) /*!< 0x00000010 */ +#define CRM_APB2EN_GPIOCEN CRM_APB2EN_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define CRM_APB2EN_GPIODEN_Pos (5U) +#define CRM_APB2EN_GPIODEN_Msk (0x1U << CRM_APB2EN_GPIODEN_Pos) /*!< 0x00000020 */ +#define CRM_APB2EN_GPIODEN CRM_APB2EN_GPIODEN_Msk /*!< GPIOD clock enable */ +#define CRM_APB2EN_GPIOFEN_Pos (7U) +#define CRM_APB2EN_GPIOFEN_Msk (0x1U << CRM_APB2EN_GPIOFEN_Pos) /*!< 0x00000080 */ +#define CRM_APB2EN_GPIOFEN CRM_APB2EN_GPIOFEN_Msk /*!< GPIOF clock enable */ +#define CRM_APB2EN_ADC1EN_Pos (9U) +#define CRM_APB2EN_ADC1EN_Msk (0x1U << CRM_APB2EN_ADC1EN_Pos) /*!< 0x00000200 */ +#define CRM_APB2EN_ADC1EN CRM_APB2EN_ADC1EN_Msk /*!< ADC1 clock enable */ +#define CRM_APB2EN_TMR1EN_Pos (11U) +#define CRM_APB2EN_TMR1EN_Msk (0x1U << CRM_APB2EN_TMR1EN_Pos) /*!< 0x00000800 */ +#define CRM_APB2EN_TMR1EN CRM_APB2EN_TMR1EN_Msk /*!< TMR1 clock enable */ +#define CRM_APB2EN_SPI1EN_Pos (12U) +#define CRM_APB2EN_SPI1EN_Msk (0x1U << CRM_APB2EN_SPI1EN_Pos) /*!< 0x00001000 */ +#define CRM_APB2EN_SPI1EN CRM_APB2EN_SPI1EN_Msk /*!< SPI1 clock enable */ +#define CRM_APB2EN_USART1EN_Pos (14U) +#define CRM_APB2EN_USART1EN_Msk (0x1U << CRM_APB2EN_USART1EN_Pos) /*!< 0x00004000 */ +#define CRM_APB2EN_USART1EN CRM_APB2EN_USART1EN_Msk /*!< USART1 clock enable */ +#define CRM_APB2EN_TMR9EN_Pos (19U) +#define CRM_APB2EN_TMR9EN_Msk (0x1U << CRM_APB2EN_TMR9EN_Pos) /*!< 0x00080000 */ +#define CRM_APB2EN_TMR9EN CRM_APB2EN_TMR9EN_Msk /*!< TMR9 clock enable */ +#define CRM_APB2EN_TMR10EN_Pos (20U) +#define CRM_APB2EN_TMR10EN_Msk (0x1U << CRM_APB2EN_TMR10EN_Pos) /*!< 0x00100000 */ +#define CRM_APB2EN_TMR10EN CRM_APB2EN_TMR10EN_Msk /*!< TMR10 clock enable */ +#define CRM_APB2EN_TMR11EN_Pos (21U) +#define CRM_APB2EN_TMR11EN_Msk (0x1U << CRM_APB2EN_TMR11EN_Pos) /*!< 0x00200000 */ +#define CRM_APB2EN_TMR11EN CRM_APB2EN_TMR11EN_Msk /*!< TMR11 clock enable */ + +/****************** Bit definition for CRM_APB1EN register ******************/ +#define CRM_APB1EN_TMR2EN_Pos (0U) +#define CRM_APB1EN_TMR2EN_Msk (0x1U << CRM_APB1EN_TMR2EN_Pos) /*!< 0x00000001 */ +#define CRM_APB1EN_TMR2EN CRM_APB1EN_TMR2EN_Msk /*!< TMR2 clock enable */ +#define CRM_APB1EN_TMR3EN_Pos (1U) +#define CRM_APB1EN_TMR3EN_Msk (0x1U << CRM_APB1EN_TMR3EN_Pos) /*!< 0x00000002 */ +#define CRM_APB1EN_TMR3EN CRM_APB1EN_TMR3EN_Msk /*!< TMR3 clock enable */ +#define CRM_APB1EN_TMR4EN_Pos (2U) +#define CRM_APB1EN_TMR4EN_Msk (0x1U << CRM_APB1EN_TMR4EN_Pos) /*!< 0x00000004 */ +#define CRM_APB1EN_TMR4EN CRM_APB1EN_TMR4EN_Msk /*!< TMR4 clock enable */ +#define CRM_APB1EN_TMR5EN_Pos (3U) +#define CRM_APB1EN_TMR5EN_Msk (0x1U << CRM_APB1EN_TMR5EN_Pos) /*!< 0x00000008 */ +#define CRM_APB1EN_TMR5EN CRM_APB1EN_TMR5EN_Msk /*!< TMR5 clock enable */ +#define CRM_APB1EN_CMPEN_Pos (9U) +#define CRM_APB1EN_CMPEN_Msk (0x1U << CRM_APB1EN_CMPEN_Pos) /*!< 0x00000200 */ +#define CRM_APB1EN_CMPEN CRM_APB1EN_CMPEN_Msk /*!< CMP clock enable */ +#define CRM_APB1EN_WWDTEN_Pos (11U) +#define CRM_APB1EN_WWDTEN_Msk (0x1U << CRM_APB1EN_WWDTEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1EN_WWDTEN CRM_APB1EN_WWDTEN_Msk /*!< WWDT clock enable */ +#define CRM_APB1EN_SPI2EN_Pos (14U) +#define CRM_APB1EN_SPI2EN_Msk (0x1U << CRM_APB1EN_SPI2EN_Pos) /*!< 0x00004000 */ +#define CRM_APB1EN_SPI2EN CRM_APB1EN_SPI2EN_Msk /*!< SPI2 clock enable */ +#define CRM_APB1EN_USART2EN_Pos (17U) +#define CRM_APB1EN_USART2EN_Msk (0x1U << CRM_APB1EN_USART2EN_Pos) /*!< 0x00020000 */ +#define CRM_APB1EN_USART2EN CRM_APB1EN_USART2EN_Msk /*!< USART2 clock enable */ +#define CRM_APB1EN_I2C1EN_Pos (21U) +#define CRM_APB1EN_I2C1EN_Msk (0x1U << CRM_APB1EN_I2C1EN_Pos) /*!< 0x00200000 */ +#define CRM_APB1EN_I2C1EN CRM_APB1EN_I2C1EN_Msk /*!< I2C1 clock enable */ +#define CRM_APB1EN_I2C2EN_Pos (22U) +#define CRM_APB1EN_I2C2EN_Msk (0x1U << CRM_APB1EN_I2C2EN_Pos) /*!< 0x00400000 */ +#define CRM_APB1EN_I2C2EN CRM_APB1EN_I2C2EN_Msk /*!< I2C2 clock enable */ +#define CRM_APB1EN_CAN1EN_Pos (25U) +#define CRM_APB1EN_CAN1EN_Msk (0x1U << CRM_APB1EN_CAN1EN_Pos) /*!< 0x02000000 */ +#define CRM_APB1EN_CAN1EN CRM_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ +#define CRM_APB1EN_PWCEN_Pos (28U) +#define CRM_APB1EN_PWCEN_Msk (0x1U << CRM_APB1EN_PWCEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1EN_PWCEN CRM_APB1EN_PWCEN_Msk /*!< Power control clock enable */ + +/******************* Bit definition for CRM_BPDC register *******************/ +#define CRM_BPDC_LEXTEN_Pos (0U) +#define CRM_BPDC_LEXTEN_Msk (0x1U << CRM_BPDC_LEXTEN_Pos) /*!< 0x00000001 */ +#define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ +#define CRM_BPDC_LEXTSTBL_Pos (1U) +#define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< Low speed external oscillator stable */ +#define CRM_BPDC_LEXTBYPS_Pos (2U) +#define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< Low speed external crystal bypass */ + +/*!< ERTCSEL congiguration */ +#define CRM_BPDC_ERTCSEL_Pos (8U) +#define CRM_BPDC_ERTCSEL_Msk (0x3U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000300 */ +#define CRM_BPDC_ERTCSEL CRM_BPDC_ERTCSEL_Msk /*!< ERTCSEL[1:0] bits (ERTC clock selection) */ +#define CRM_BPDC_ERTCSEL_0 (0x1U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000100 */ +#define CRM_BPDC_ERTCSEL_1 (0x2U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000200 */ + +#define CRM_BPDC_ERTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define CRM_BPDC_ERTCSEL_LEXT 0x00000100U /*!< LEXT */ +#define CRM_BPDC_ERTCSEL_LICK 0x00000200U /*!< LICK */ +#define CRM_BPDC_ERTCSEL_HEXT 0x00000300U /*!< HEXT/128 */ + +#define CRM_BPDC_ERTCEN_Pos (15U) +#define CRM_BPDC_ERTCEN_Msk (0x1U << CRM_BPDC_ERTCEN_Pos) /*!< 0x00008000 */ +#define CRM_BPDC_ERTCEN CRM_BPDC_ERTCEN_Msk /*!< ERTC clock enable */ +#define CRM_BPDC_BPDRST_Pos (16U) +#define CRM_BPDC_BPDRST_Msk (0x1U << CRM_BPDC_BPDRST_Pos) /*!< 0x00010000 */ +#define CRM_BPDC_BPDRST CRM_BPDC_BPDRST_Msk /*!< Battery powered domain software reset */ + +/***************** Bit definition for CRM_CTRLSTS register ******************/ +#define CRM_CTRLSTS_LICKEN_Pos (0U) +#define CRM_CTRLSTS_LICKEN_Msk (0x1U << CRM_CTRLSTS_LICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRLSTS_LICKEN CRM_CTRLSTS_LICKEN_Msk /*!< LICK enable */ +#define CRM_CTRLSTS_LICKSTBL_Pos (1U) +#define CRM_CTRLSTS_LICKSTBL_Msk (0x1U << CRM_CTRLSTS_LICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRLSTS_LICKSTBL CRM_CTRLSTS_LICKSTBL_Msk /*!< LICK stable */ +#define CRM_CTRLSTS_RSTFC_Pos (24U) +#define CRM_CTRLSTS_RSTFC_Msk (0x1U << CRM_CTRLSTS_RSTFC_Pos) /*!< 0x01000000 */ +#define CRM_CTRLSTS_RSTFC CRM_CTRLSTS_RSTFC_Msk /*!< Reset flag clear */ +#define CRM_CTRLSTS_NRSTF_Pos (26U) +#define CRM_CTRLSTS_NRSTF_Msk (0x1U << CRM_CTRLSTS_NRSTF_Pos) /*!< 0x04000000 */ +#define CRM_CTRLSTS_NRSTF CRM_CTRLSTS_NRSTF_Msk /*!< NRST pin reset flag */ +#define CRM_CTRLSTS_PORRSTF_Pos (27U) +#define CRM_CTRLSTS_PORRSTF_Msk (0x1U << CRM_CTRLSTS_PORRSTF_Pos) /*!< 0x08000000 */ +#define CRM_CTRLSTS_PORRSTF CRM_CTRLSTS_PORRSTF_Msk /*!< POR/LVR reset flag */ +#define CRM_CTRLSTS_SWRSTF_Pos (28U) +#define CRM_CTRLSTS_SWRSTF_Msk (0x1U << CRM_CTRLSTS_SWRSTF_Pos) /*!< 0x10000000 */ +#define CRM_CTRLSTS_SWRSTF CRM_CTRLSTS_SWRSTF_Msk /*!< Software reset flag */ +#define CRM_CTRLSTS_WDTRSTF_Pos (29U) +#define CRM_CTRLSTS_WDTRSTF_Msk (0x1U << CRM_CTRLSTS_WDTRSTF_Pos) /*!< 0x20000000 */ +#define CRM_CTRLSTS_WDTRSTF CRM_CTRLSTS_WDTRSTF_Msk /*!< Watchdog timer reset flag */ +#define CRM_CTRLSTS_WWDTRSTF_Pos (30U) +#define CRM_CTRLSTS_WWDTRSTF_Msk (0x1U << CRM_CTRLSTS_WWDTRSTF_Pos) /*!< 0x40000000 */ +#define CRM_CTRLSTS_WWDTRSTF CRM_CTRLSTS_WWDTRSTF_Msk /*!< Window watchdog timer reset flag */ +#define CRM_CTRLSTS_LPRSTF_Pos (31U) +#define CRM_CTRLSTS_LPRSTF_Msk (0x1U << CRM_CTRLSTS_LPRSTF_Pos) /*!< 0x80000000 */ +#define CRM_CTRLSTS_LPRSTF CRM_CTRLSTS_LPRSTF_Msk /*!< Low-power reset flag */ + +/****************** Bit definition for CRM_AHBRST register ******************/ +#define CRM_AHBRST_OTGFSRST_Pos (12U) +#define CRM_AHBRST_OTGFSRST_Msk (0x1U << CRM_AHBRST_OTGFSRST_Pos) /*!< 0x00001000 */ +#define CRM_AHBRST_OTGFSRST CRM_AHBRST_OTGFSRST_Msk /*!< OTGFS reset */ + +/******************* Bit definition for CRM_PLL register ********************/ +/*!< PLL_FR congiguration */ +#define CRM_PLL_PLL_FR_Pos (0U) +#define CRM_PLL_PLL_FR_Msk (0x7U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000007 */ +#define CRM_PLL_PLL_FR CRM_PLL_PLL_FR_Msk /*!< PLL_FR[2:0] bits (PLL post-division factor) */ +#define CRM_PLL_PLL_FR_0 (0x1U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000001 */ +#define CRM_PLL_PLL_FR_1 (0x2U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000002 */ +#define CRM_PLL_PLL_FR_2 (0x4U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000004 */ + +/*!< PLL_MS congiguration */ +#define CRM_PLL_PLL_MS_Pos (4U) +#define CRM_PLL_PLL_MS_Msk (0xFU << CRM_PLL_PLL_MS_Pos) /*!< 0x000000F0 */ +#define CRM_PLL_PLL_MS CRM_PLL_PLL_MS_Msk /*!< PLL_MS[3:0] bits (PLL pre-division) */ +#define CRM_PLL_PLL_MS_0 (0x1U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000010 */ +#define CRM_PLL_PLL_MS_1 (0x2U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000020 */ +#define CRM_PLL_PLL_MS_2 (0x4U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000040 */ +#define CRM_PLL_PLL_MS_3 (0x8U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000080 */ + +/*!< PLL_NS congiguration */ +#define CRM_PLL_PLL_NS_Pos (8U) +#define CRM_PLL_PLL_NS_Msk (0x1FFU << CRM_PLL_PLL_NS_Pos) /*!< 0x0001FF00 */ +#define CRM_PLL_PLL_NS CRM_PLL_PLL_NS_Msk /*!< PLL_NS[8:0] bits (PLL multiplication factor) */ +#define CRM_PLL_PLL_NS_0 (0x001U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000100 */ +#define CRM_PLL_PLL_NS_1 (0x002U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000200 */ +#define CRM_PLL_PLL_NS_2 (0x004U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000400 */ +#define CRM_PLL_PLL_NS_3 (0x008U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000800 */ +#define CRM_PLL_PLL_NS_4 (0x010U << CRM_PLL_PLL_NS_Pos) /*!< 0x00001000 */ +#define CRM_PLL_PLL_NS_5 (0x020U << CRM_PLL_PLL_NS_Pos) /*!< 0x00002000 */ +#define CRM_PLL_PLL_NS_6 (0x040U << CRM_PLL_PLL_NS_Pos) /*!< 0x00004000 */ +#define CRM_PLL_PLL_NS_7 (0x080U << CRM_PLL_PLL_NS_Pos) /*!< 0x00008000 */ +#define CRM_PLL_PLL_NS_8 (0x100U << CRM_PLL_PLL_NS_Pos) /*!< 0x00010000 */ + +/*!< PLL_FREF congiguration */ +#define CRM_PLL_PLL_FREF_Pos (24U) +#define CRM_PLL_PLL_FREF_Msk (0x7U << CRM_PLL_PLL_FREF_Pos) /*!< 0x07000000 */ +#define CRM_PLL_PLL_FREF CRM_PLL_PLL_FREF_Msk /*!< PLL_FREF[2:0] bits (PLL input clock selection) */ +#define CRM_PLL_PLL_FREF_0 (0x1U << CRM_PLL_PLL_FREF_Pos) /*!< 0x01000000 */ +#define CRM_PLL_PLL_FREF_1 (0x2U << CRM_PLL_PLL_FREF_Pos) /*!< 0x02000000 */ +#define CRM_PLL_PLL_FREF_2 (0x4U << CRM_PLL_PLL_FREF_Pos) /*!< 0x04000000 */ + +#define CRM_PLL_PLL_FREF_4M 0x00000000U /*!< 3.9 ~ 5 MHz */ +#define CRM_PLL_PLL_FREF_6M 0x01000000U /*!< 5.2 ~ 6.25 MHz */ +#define CRM_PLL_PLL_FREF_8M 0x02000000U /*!< 7.8125 ~ 8.33 MHz */ +#define CRM_PLL_PLL_FREF_12M 0x03000000U /*!< 8.33 ~ 12.5 MHz */ +#define CRM_PLL_PLL_FREF_16M 0x04000000U /*!< 15.625 ~ 20.83 MHz */ +#define CRM_PLL_PLL_FREF_25M 0x05000000U /*!< 20.83 ~ 31.255 MHz */ + +#define CRM_PLL_PLLCFGEN_Pos (31U) +#define CRM_PLL_PLLCFGEN_Msk (0x1U << CRM_PLL_PLLCFGEN_Pos) /*!< 0x80000000 */ +#define CRM_PLL_PLLCFGEN CRM_PLL_PLLCFGEN_Msk /*!< PLL configuration enable */ + +/****************** Bit definition for CRM_MISC1 register *******************/ +#define CRM_MISC1_HICKCAL_KEY_Pos (0U) +#define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ +#define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ +#define CRM_MISC1_CLKOUT_SEL_Pos (16U) +#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRN_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL CRM_MISC1_CLKOUT_SEL_Msk /*!< Clock output selection */ +#define CRM_MISC1_CLKFMC_SRC_Pos (20U) +#define CRM_MISC1_CLKFMC_SRC_Msk (0x1U << CRM_MISC1_CLKFMC_SRC_Pos) /*!< 0x00100000 */ +#define CRM_MISC1_CLKFMC_SRC CRM_MISC1_CLKFMC_SRC_Msk /*!< FMC clock source */ +#define CRM_MISC1_HICKDIV_Pos (25U) +#define CRM_MISC1_HICKDIV_Msk (0x1U << CRM_MISC1_HICKDIV_Pos) /*!< 0x02000000 */ +#define CRM_MISC1_HICKDIV CRM_MISC1_HICKDIV_Msk /*!< HICK 6 divider selection */ + +/*!< CLKOUTDIV congiguration */ +#define CRM_MISC1_CLKOUTDIV_Pos (28U) +#define CRM_MISC1_CLKOUTDIV_Msk (0xFU << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0xF0000000 */ +#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division */ +#define CRM_MISC1_CLKOUTDIV_0 (0x1U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x10000000 */ +#define CRM_MISC1_CLKOUTDIV_1 (0x2U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x20000000 */ +#define CRM_MISC1_CLKOUTDIV_2 (0x4U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x40000000 */ +#define CRM_MISC1_CLKOUTDIV_3 (0x8U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x80000000 */ + +#define CRM_MISC1_CLKOUTDIV_DIV1 0x00000000U /*!< No clock output */ +#define CRM_MISC1_CLKOUTDIV_DIV2 0x80000000U /*!< Clock output divided by 2 */ +#define CRM_MISC1_CLKOUTDIV_DIV4 0x90000000U /*!< Clock output divided by 4 */ +#define CRM_MISC1_CLKOUTDIV_DIV8 0xA0000000U /*!< Clock output divided by 8 */ +#define CRM_MISC1_CLKOUTDIV_DIV16 0xB0000000U /*!< Clock output divided by 16 */ +#define CRM_MISC1_CLKOUTDIV_DIV64 0xC0000000U /*!< Clock output divided by 64 */ +#define CRM_MISC1_CLKOUTDIV_DIV128 0xD0000000U /*!< Clock output divided by 128 */ +#define CRM_MISC1_CLKOUTDIV_DIV256 0xE0000000U /*!< Clock output divided by 256 */ +#define CRM_MISC1_CLKOUTDIV_DIV512 0xF0000000U /*!< Clock output divided by 512 */ + +/*************** Bit definition for CRM_OTG_EXTCTRL register ****************/ +#define CRM_OTG_EXTCTRL_USBDIV_RST_Pos (30U) /*!< 0x40000000 */ +#define CRM_OTG_EXTCTRL_USBDIV_RST_Msk (0x1U << CRM_OTG_EXTCTRL_USBDIV_RST_Pos) +#define CRM_OTG_EXTCTRL_USBDIV_RST CRM_OTG_EXTCTRL_USBDIV_RST_Msk /*!< USB divider reset */ +#define CRM_OTG_EXTCTRL_EP3_RMPEN_Pos (31U) +#define CRM_OTG_EXTCTRL_EP3_RMPEN_Msk (0x1U << CRM_OTG_EXTCTRL_EP3_RMPEN_Pos) /*!< 0x80000000 */ +#define CRM_OTG_EXTCTRL_EP3_RMPEN CRM_OTG_EXTCTRL_EP3_RMPEN_Msk /*!< Endpoint 3 remap enable */ + +/****************** Bit definition for CRM_MISC2 register *******************/ +/*!< AUTO_STEP_EN congiguration */ +#define CRM_MISC2_AUTO_STEP_EN_Pos (4U) +#define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] Auto step-by-step SCLK switch enable */ +#define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ +#define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ + +#define CRM_MISC2_HICK_TO_SCLK_Pos (9U) +#define CRM_MISC2_HICK_TO_SCLK_Msk (0x1U << CRM_MISC2_HICK_TO_SCLK_Pos) /*!< 0x00000200 */ +#define CRM_MISC2_HICK_TO_SCLK CRM_MISC2_HICK_TO_SCLK_Msk /*!< HICK as system clock frequency select */ + +/******************************************************************************/ +/* */ +/* Flash and User System Data Registers (FLASH) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_PSR register ******************/ +/*!< WTCYC congiguration */ +#define FLASH_PSR_WTCYC_Pos (0U) +#define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] Wait states */ +#define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ +#define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ +#define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ + +#define FLASH_PSR_HFCYC_EN_Pos (3U) +#define FLASH_PSR_HFCYC_EN_Msk (0x1U << FLASH_PSR_HFCYC_EN_Pos) /*!< 0x00000008 */ +#define FLASH_PSR_HFCYC_EN FLASH_PSR_HFCYC_EN_Msk /*!< Half cycle acceleration access enable */ +#define FLASH_PSR_PFT_EN_Pos (4U) +#define FLASH_PSR_PFT_EN_Msk (0x1U << FLASH_PSR_PFT_EN_Pos) /*!< 0x00000010 */ +#define FLASH_PSR_PFT_EN FLASH_PSR_PFT_EN_Msk /*!< Prefetch enable */ +#define FLASH_PSR_PFT_ENF_Pos (5U) +#define FLASH_PSR_PFT_ENF_Msk (0x1U << FLASH_PSR_PFT_ENF_Pos) /*!< 0x00000020 */ +#define FLASH_PSR_PFT_ENF FLASH_PSR_PFT_ENF_Msk /*!< Prefetch enable flag */ + +/***************** Bit definition for FLASH_UNLOCK register *****************/ +#define FLASH_UNLOCK_UKVAL_Pos (0U) +#define FLASH_UNLOCK_UKVAL_Msk (0xFFFFFFFFU << FLASH_UNLOCK_UKVAL_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_UNLOCK_UKVAL FLASH_UNLOCK_UKVAL_Msk /*!< Unlock key value */ + +#define FAP_KEY_Pos (0U) +#define FAP_KEY_Msk (0xA5U << FAP_KEY_Pos) /*!< 0x000000A5 */ +#define FAP_KEY FAP_KEY_Msk /*!< Flash access protection key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash key 1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash key 2 */ + +/*************** Bit definition for FLASH_USD_UNLOCK register ***************/ +#define FLASH_USD_UNLOCK_USD_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_USD_UNLOCK_USD_UKVAL_Msk (0xFFFFFFFFU << FLASH_USD_UNLOCK_USD_UKVAL_Pos) +#define FLASH_USD_UNLOCK_USD_UKVAL FLASH_USD_UNLOCK_USD_UKVAL_Msk /*!< User system data unlock key value */ + +#define FLASH_USDKEY1 FLASH_KEY1 /*!< User system data key 1 */ +#define FLASH_USDKEY2 FLASH_KEY2 /*!< User system data key 2 */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_OBF_Pos (0U) +#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation done flag */ +#define FLASH_STS_PRGMERR_Pos (2U) +#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ +#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ +#define FLASH_STS_EPPERR_Pos (4U) +#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */ +#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk /*!< Erase/program protection error */ +#define FLASH_STS_ODF_Pos (5U) +#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */ +#define FLASH_STS_ODF FLASH_STS_ODF_Msk /*!< Operation done flag */ + +/****************** Bit definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_FPRGM_Pos (0U) +#define FLASH_CTRL_FPRGM_Msk (0x1U << FLASH_CTRL_FPRGM_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_FPRGM FLASH_CTRL_FPRGM_Msk /*!< Flash program */ +#define FLASH_CTRL_SECERS_Pos (1U) +#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk /*!< Page erase */ +#define FLASH_CTRL_BANKERS_Pos (2U) +#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk /*!< Bank erase */ +#define FLASH_CTRL_USDPRGM_Pos (4U) +#define FLASH_CTRL_USDPRGM_Msk (0x1U << FLASH_CTRL_USDPRGM_Pos) /*!< 0x00000010 */ +#define FLASH_CTRL_USDPRGM FLASH_CTRL_USDPRGM_Msk /*!< User system data program */ +#define FLASH_CTRL_USDERS_Pos (5U) +#define FLASH_CTRL_USDERS_Msk (0x1U << FLASH_CTRL_USDERS_Pos) /*!< 0x00000020 */ +#define FLASH_CTRL_USDERS FLASH_CTRL_USDERS_Msk /*!< User system data erase */ +#define FLASH_CTRL_ERSTR_Pos (6U) +#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x00000040 */ +#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk /*!< Erase start */ +#define FLASH_CTRL_OPLK_Pos (7U) +#define FLASH_CTRL_OPLK_Msk (0x1U << FLASH_CTRL_OPLK_Pos) /*!< 0x00000080 */ +#define FLASH_CTRL_OPLK FLASH_CTRL_OPLK_Msk /*!< Operation lock */ +#define FLASH_CTRL_USDULKS_Pos (9U) +#define FLASH_CTRL_USDULKS_Msk (0x1U << FLASH_CTRL_USDULKS_Pos) /*!< 0x00000200 */ +#define FLASH_CTRL_USDULKS FLASH_CTRL_USDULKS_Msk /*!< User system data unlock success */ +#define FLASH_CTRL_ERRIE_Pos (10U) +#define FLASH_CTRL_ERRIE_Msk (0x1U << FLASH_CTRL_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CTRL_ERRIE FLASH_CTRL_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CTRL_ODFIE_Pos (12U) +#define FLASH_CTRL_ODFIE_Msk (0x1U << FLASH_CTRL_ODFIE_Pos) /*!< 0x00001000 */ +#define FLASH_CTRL_ODFIE FLASH_CTRL_ODFIE_Msk /*!< Operation done flag interrupt enable */ +#define FLASH_CTRL_FAP_HL_DIS_Pos (16U) +#define FLASH_CTRL_FAP_HL_DIS_Msk (0x1U << FLASH_CTRL_FAP_HL_DIS_Pos) /*!< 0x00010000 */ +#define FLASH_CTRL_FAP_HL_DIS FLASH_CTRL_FAP_HL_DIS_Msk /*!< High level Flash access protection disable */ + +/****************** Bit definition for FLASH_ADDR register ******************/ +#define FLASH_ADDR_FA_Pos (0U) +#define FLASH_ADDR_FA_Msk (0xFFFFFFFFU << FLASH_ADDR_FA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_ADDR_FA FLASH_ADDR_FA_Msk /*!< Flash address */ + +/****************** Bit definition for FLASH_USD register *******************/ +#define FLASH_USD_USDERR_Pos (0U) +#define FLASH_USD_USDERR_Msk (0x1U << FLASH_USD_USDERR_Pos) /*!< 0x00000001 */ +#define FLASH_USD_USDERR FLASH_USD_USDERR_Msk /*!< User system data error */ +#define FLASH_USD_FAP_Pos (1U) +#define FLASH_USD_FAP_Msk (0x1U << FLASH_USD_FAP_Pos) /*!< 0x00000002 */ +#define FLASH_USD_FAP FLASH_USD_FAP_Msk /*!< Flash access protection */ + +/*!< SSB congiguration */ +#define FLASH_USD_WDT_ATO_EN_Pos (2U) +#define FLASH_USD_WDT_ATO_EN_Msk (0x1U << FLASH_USD_WDT_ATO_EN_Pos) /*!< 0x00000004 */ +#define FLASH_USD_WDT_ATO_EN FLASH_USD_WDT_ATO_EN_Msk /*!< nWDT_ATO_EN */ +#define FLASH_USD_DEPSLP_RST_Pos (3U) +#define FLASH_USD_DEPSLP_RST_Msk (0x1U << FLASH_USD_DEPSLP_RST_Pos) /*!< 0x00000008 */ +#define FLASH_USD_DEPSLP_RST FLASH_USD_DEPSLP_RST_Msk /*!< nDEPSLP_RST */ +#define FLASH_USD_STDBY_RST_Pos (4U) +#define FLASH_USD_STDBY_RST_Msk (0x1U << FLASH_USD_STDBY_RST_Pos) /*!< 0x00000010 */ +#define FLASH_USD_STDBY_RST FLASH_USD_STDBY_RST_Msk /*!< nSTDBY_RST */ +#define FLASH_USD_SSB_Pos (2U) +#define FLASH_USD_SSB_Msk (0x7U << FLASH_USD_SSB_Pos) /*!< 0x0000001C */ +#define FLASH_USD_SSB FLASH_USD_SSB_Msk /*!< System setting byte */ + +#define FLASH_USD_USER_D0_Pos (10U) +#define FLASH_USD_USER_D0_Msk (0xFFU << FLASH_USD_USER_D0_Pos) /*!< 0x0003FC00 */ +#define FLASH_USD_USER_D0 FLASH_USD_USER_D0_Msk /*!< User data 0 */ +#define FLASH_USD_USER_D1_Pos (18U) +#define FLASH_USD_USER_D1_Msk (0xFFU << FLASH_USD_USER_D1_Pos) /*!< 0x03FC0000 */ +#define FLASH_USD_USER_D1 FLASH_USD_USER_D1_Msk /*!< User data 1 */ +#define FLASH_USD_FAP_HL_Pos (26U) +#define FLASH_USD_FAP_HL_Msk (0x1U << FLASH_USD_FAP_HL_Pos) /*!< 0x04000000 */ +#define FLASH_USD_FAP_HL FLASH_USD_FAP_HL_Msk /*!< Flash access protection high level */ + +/****************** Bit definition for FLASH_EPPS register ******************/ +#define FLASH_EPPS_EPPS_Pos (0U) +#define FLASH_EPPS_EPPS_Msk (0xFFFFFFFFU << FLASH_EPPS_EPPS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_EPPS_EPPS FLASH_EPPS_EPPS_Msk /*!< Erase/Program protection status */ + +/******************* Bit definition for SLIB_STS0 register *******************/ +#define SLIB_STS0_BTM_AP_ENF_Pos (0U) +#define SLIB_STS0_BTM_AP_ENF_Msk (0x1U << SLIB_STS0_BTM_AP_ENF_Pos) /*!< 0x00000001 */ +#define SLIB_STS0_BTM_AP_ENF SLIB_STS0_BTM_AP_ENF_Msk /*!< Boot memory store application code enabled flag */ +#define SLIB_STS0_EM_SLIB_ENF_Pos (2U) +#define SLIB_STS0_EM_SLIB_ENF_Msk (0x1U << SLIB_STS0_EM_SLIB_ENF_Pos) /*!< 0x00000004 */ +#define SLIB_STS0_EM_SLIB_ENF SLIB_STS0_EM_SLIB_ENF_Msk /*!< Extension memory sLib enable flag */ +#define SLIB_STS0_SLIB_ENF_Pos (3U) +#define SLIB_STS0_SLIB_ENF_Msk (0x1U << SLIB_STS0_SLIB_ENF_Pos) /*!< 0x00000008 */ +#define SLIB_STS0_SLIB_ENF SLIB_STS0_SLIB_ENF_Msk /*!< Security library enable flag */ +#define SLIB_STS0_EM_SLIB_DAT_SS_Pos (16U) +#define SLIB_STS0_EM_SLIB_DAT_SS_Msk (0xFFU << SLIB_STS0_EM_SLIB_DAT_SS_Pos) /*!< 0x00FF0000 */ +#define SLIB_STS0_EM_SLIB_DAT_SS SLIB_STS0_EM_SLIB_DAT_SS_Msk /*!< Extension memory sLib data start page */ + +/******************* Bit definition for SLIB_STS1 register *******************/ +#define SLIB_STS1_SLIB_SS_Pos (0U) +#define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ +#define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ +#define SLIB_STS1_SLIB_DAT_SS_Pos (11U) +#define SLIB_STS1_SLIB_DAT_SS_Msk (0x3FF8U << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_DAT_SS SLIB_STS1_SLIB_DAT_SS_Msk /*!< Security library data start page */ +#define SLIB_STS1_SLIB_ES_Pos (22U) +#define SLIB_STS1_SLIB_ES_Msk (0xFFCU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ + +/***************** Bit definition for SLIB_PWD_CLR register ******************/ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk (0xFFFFFFFFU << SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos) +#define SLIB_PWD_CLR_SLIB_PCLR_VAL SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk /*!< Security library password clear value */ + +/***************** Bit definition for SLIB_MISC_STS register *****************/ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Pos (0U) /*!< 0x00000001 */ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_ERR_Pos) +#define SLIB_MISC_STS_SLIB_PWD_ERR SLIB_MISC_STS_SLIB_PWD_ERR_Msk /*!< Security library password error */ +#define SLIB_MISC_STS_SLIB_PWD_OK_Pos (1U) +#define SLIB_MISC_STS_SLIB_PWD_OK_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_OK_Pos) /*!< 0x00000002 */ +#define SLIB_MISC_STS_SLIB_PWD_OK SLIB_MISC_STS_SLIB_PWD_OK_Msk /*!< Security library password ok */ +#define SLIB_MISC_STS_SLIB_ULKF_Pos (2U) +#define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ +#define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ + +/***************** Bit definition for FLASH_CRC_ARR register *****************/ +#define FLASH_CRC_ARR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ARR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ARR_CRC_ADDR_Pos) +#define FLASH_CRC_ARR_CRC_ADDR FLASH_CRC_ARR_CRC_ADDR_Msk /*!< CRC address */ + +/**************** Bit definition for FLASH_CRC_CTRL register *****************/ +#define FLASH_CRC_CTRL_CRC_SN_Pos (0U) +#define FLASH_CRC_CTRL_CRC_SN_Msk (0xFFFFU << FLASH_CRC_CTRL_CRC_SN_Pos) /*!< 0x0000FFFF */ +#define FLASH_CRC_CTRL_CRC_SN FLASH_CRC_CTRL_CRC_SN_Msk /*!< CRC page number */ +#define FLASH_CRC_CTRL_CRC_STRT_Pos (16U) +#define FLASH_CRC_CTRL_CRC_STRT_Msk (0x1U << FLASH_CRC_CTRL_CRC_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CRC_CTRL_CRC_STRT FLASH_CRC_CTRL_CRC_STRT_Msk /*!< CRC start */ + +/**************** Bit definition for FLASH_CRC_CHKR register *****************/ +#define FLASH_CRC_CHKR_CRC_CHKR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_CHKR_CRC_CHKR_Msk (0xFFFFFFFFU << FLASH_CRC_CHKR_CRC_CHKR_Pos) +#define FLASH_CRC_CHKR_CRC_CHKR FLASH_CRC_CHKR_CRC_CHKR_Msk /*!< CRC check result */ + +/***************** Bit definition for SLIB_SET_PWD register ******************/ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< sLib password setting value */ + +/**************** Bit definition for SLIB_SET_RANGE register *****************/ +#define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ +#define SLIB_SET_RANGE_SLIB_SS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_SS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_SS_SET SLIB_SET_RANGE_SLIB_SS_SET_Msk /*!< Security library start page setting */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Pos (11U) /*!< 0x003FF800 */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Msk (0x3FF8U << SLIB_SET_RANGE_SLIB_ISS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ISS_SET SLIB_SET_RANGE_SLIB_ISS_SET_Msk /*!< Security library instruction start page setting */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Pos (22U) /*!< 0xFFC00000 */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Msk (0xFFCU << SLIB_SET_RANGE_SLIB_ES_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ES_SET SLIB_SET_RANGE_SLIB_ES_SET_Msk /*!< Security library end page setting */ + +/****************** Bit definition for EM_SLIB_SET register ******************/ +#define EM_SLIB_SET_EM_SLIB_SET_Pos (0U) /*!< 0x0000FFFF */ +#define EM_SLIB_SET_EM_SLIB_SET_Msk (0xFFFFU << EM_SLIB_SET_EM_SLIB_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page */ + +/***************** Bit definition for BTM_MODE_SET register ******************/ +#define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ +#define BTM_MODE_SET_BTM_MODE_SET_Msk (0xFFU << BTM_MODE_SET_BTM_MODE_SET_Pos) +#define BTM_MODE_SET_BTM_MODE_SET BTM_MODE_SET_BTM_MODE_SET_Msk /*!< Boot memory mode setting */ + +/***************** Bit definition for SLIB_UNLOCK register ******************/ +#define SLIB_UNLOCK_SLIB_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) +#define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ + +#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ +#define SLIB_KEY SLIB_KEY_Msk + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_FAP register *******************/ +#define FLASH_FAP_FAP_Pos (0U) +#define FLASH_FAP_FAP_Msk (0xFFU << FLASH_FAP_FAP_Pos) /*!< 0x000000FF */ +#define FLASH_FAP_FAP FLASH_FAP_FAP_Msk /*!< Flash memory access protection */ +#define FLASH_FAP_nFAP_Pos (8U) +#define FLASH_FAP_nFAP_Msk (0xFFU << FLASH_FAP_nFAP_Pos) /*!< 0x0000FF00 */ +#define FLASH_FAP_nFAP FLASH_FAP_nFAP_Msk /*!< Inverse code of flash memory access protection */ + +/****************** Bit definition for FLASH_SSB register *******************/ +#define FLASH_SSB_SSB_Pos (16U) +#define FLASH_SSB_SSB_Msk (0xFFU << FLASH_SSB_SSB_Pos) /*!< 0x00FF0000 */ +#define FLASH_SSB_SSB FLASH_SSB_SSB_Msk /*!< System configuration byte */ +#define FLASH_SSB_nSSB_Pos (24U) +#define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ +#define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ + +/****************** Bit definition for FLASH_DATA0 register *****************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ + +/****************** Bit definition for FLASH_DATA1 register *****************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< Inverse code of user data 1 */ + +/****************** Bit definition for FLASH_EPP0 register ******************/ +#define FLASH_EPP0_EPP0_Pos (0U) +#define FLASH_EPP0_EPP0_Msk (0xFFU << FLASH_EPP0_EPP0_Pos) /*!< 0x000000FF */ +#define FLASH_EPP0_EPP0 FLASH_EPP0_EPP0_Msk /*!< Flash erase/write protection byte 0 */ +#define FLASH_EPP0_nEPP0_Pos (8U) +#define FLASH_EPP0_nEPP0_Msk (0xFFU << FLASH_EPP0_nEPP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP0_nEPP0 FLASH_EPP0_nEPP0_Msk /*!< Inverse code of flash erase/write protection byte 0 */ + +/****************** Bit definition for FLASH_EPP1 register ******************/ +#define FLASH_EPP1_EPP1_Pos (16U) +#define FLASH_EPP1_EPP1_Msk (0xFFU << FLASH_EPP1_EPP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP1_EPP1 FLASH_EPP1_EPP1_Msk /*!< Flash erase/write protection byte 1 */ +#define FLASH_EPP1_nEPP1_Pos (24U) +#define FLASH_EPP1_nEPP1_Msk (0xFFU << FLASH_EPP1_nEPP1_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP1_nEPP1 FLASH_EPP1_nEPP1_Msk /*!< Inverse code of flash erase/write protection byte 1 */ + +/****************** Bit definition for FLASH_EPP2 register ******************/ +#define FLASH_EPP2_EPP2_Pos (0U) +#define FLASH_EPP2_EPP2_Msk (0xFFU << FLASH_EPP2_EPP2_Pos) /*!< 0x000000FF */ +#define FLASH_EPP2_EPP2 FLASH_EPP2_EPP2_Msk /*!< Flash erase/write protection byte 2 */ +#define FLASH_EPP2_nEPP2_Pos (8U) +#define FLASH_EPP2_nEPP2_Msk (0xFFU << FLASH_EPP2_nEPP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP2_nEPP2 FLASH_EPP2_nEPP2_Msk /*!< Inverse code of flash erase/write protection byte 2 */ + +/****************** Bit definition for FLASH_EPP3 register ******************/ +#define FLASH_EPP3_EPP3_Pos (16U) +#define FLASH_EPP3_EPP3_Msk (0xFFU << FLASH_EPP3_EPP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP3_EPP3 FLASH_EPP3_EPP3_Msk /*!< Flash erase/write protection byte 3 */ +#define FLASH_EPP3_nEPP3_Pos (24U) +#define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ + +/***************** Bit definition for FLASH_EOPB0 register ******************/ +#define FLASH_EOPB0_EOPB0_Pos (0U) +#define FLASH_EOPB0_EOPB0_Msk (0xFFU << FLASH_EOPB0_EOPB0_Pos) /*!< 0x000000FF */ +#define FLASH_EOPB0_EOPB0 FLASH_EOPB0_EOPB0_Msk /*!< Extended system options */ +#define FLASH_EOPB0_nEOPB0_Pos (8U) +#define FLASH_EOPB0_nEOPB0_Msk (0xFFU << FLASH_EOPB0_nEOPB0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EOPB0_nEOPB0 FLASH_EOPB0_nEOPB0_Msk /*!< Inverse code of extended system options */ + +/****************** Bit definition for FLASH_DATA2 register *****************/ +#define FLASH_DATA2_DATA2_Pos (0U) +#define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ +#define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ +#define FLASH_DATA2_nDATA2_Pos (8U) +#define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ + +/****************** Bit definition for FLASH_DATA3 register *****************/ +#define FLASH_DATA3_DATA3_Pos (16U) +#define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ +#define FLASH_DATA3_nDATA3_Pos (24U) +#define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ + +/****************** Bit definition for FLASH_DATA4 register *****************/ +#define FLASH_DATA4_DATA4_Pos (0U) +#define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ +#define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ +#define FLASH_DATA4_nDATA4_Pos (8U) +#define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ + +/****************** Bit definition for FLASH_DATA5 register *****************/ +#define FLASH_DATA5_DATA5_Pos (16U) +#define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ +#define FLASH_DATA5_nDATA5_Pos (24U) +#define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ + +/****************** Bit definition for FLASH_DATA6 register *****************/ +#define FLASH_DATA6_DATA6_Pos (0U) +#define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ +#define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ +#define FLASH_DATA6_nDATA6_Pos (8U) +#define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ + +/****************** Bit definition for FLASH_DATA7 register *****************/ +#define FLASH_DATA7_DATA7_Pos (16U) +#define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ +#define FLASH_DATA7_nDATA7_Pos (24U) +#define FLASH_DATA7_nDATA7_Msk (0xFFU << FLASH_DATA7_nDATA7_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA7_nDATA7 FLASH_DATA7_nDATA7_Msk /*!< Inverse code of user data 7 */ + +/*!< Noted: The FLASH_DATA go up to 505, it too long for added in here */ + +/******************************************************************************/ +/* */ +/* General-purpose I/Os (GPIO) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for GPIO_CFGLR register ******************/ +#define GPIO_CFGLR_IOMC_Pos (0U) +#define GPIO_CFGLR_IOMC_Msk (0x33333333U << GPIO_CFGLR_IOMC_Pos) /*!< 0x33333333 */ +#define GPIO_CFGLR_IOMC GPIO_CFGLR_IOMC_Msk /*!< GPIO x mode configuration */ + +#define GPIO_CFGLR_IOMC0_Pos (0U) +#define GPIO_CFGLR_IOMC0_Msk (0x3U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000003 */ +#define GPIO_CFGLR_IOMC0 GPIO_CFGLR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ +#define GPIO_CFGLR_IOMC0_0 (0x1U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000001 */ +#define GPIO_CFGLR_IOMC0_1 (0x2U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000002 */ + +#define GPIO_CFGLR_IOMC1_Pos (4U) +#define GPIO_CFGLR_IOMC1_Msk (0x3U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000030 */ +#define GPIO_CFGLR_IOMC1 GPIO_CFGLR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ +#define GPIO_CFGLR_IOMC1_0 (0x1U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000010 */ +#define GPIO_CFGLR_IOMC1_1 (0x2U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000020 */ + +#define GPIO_CFGLR_IOMC2_Pos (8U) +#define GPIO_CFGLR_IOMC2_Msk (0x3U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000300 */ +#define GPIO_CFGLR_IOMC2 GPIO_CFGLR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ +#define GPIO_CFGLR_IOMC2_0 (0x1U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000100 */ +#define GPIO_CFGLR_IOMC2_1 (0x2U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000200 */ + +#define GPIO_CFGLR_IOMC3_Pos (12U) +#define GPIO_CFGLR_IOMC3_Msk (0x3U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00003000 */ +#define GPIO_CFGLR_IOMC3 GPIO_CFGLR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ +#define GPIO_CFGLR_IOMC3_0 (0x1U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00001000 */ +#define GPIO_CFGLR_IOMC3_1 (0x2U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00002000 */ + +#define GPIO_CFGLR_IOMC4_Pos (16U) +#define GPIO_CFGLR_IOMC4_Msk (0x3U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00030000 */ +#define GPIO_CFGLR_IOMC4 GPIO_CFGLR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ +#define GPIO_CFGLR_IOMC4_0 (0x1U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00010000 */ +#define GPIO_CFGLR_IOMC4_1 (0x2U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00020000 */ + +#define GPIO_CFGLR_IOMC5_Pos (20U) +#define GPIO_CFGLR_IOMC5_Msk (0x3U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00300000 */ +#define GPIO_CFGLR_IOMC5 GPIO_CFGLR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ +#define GPIO_CFGLR_IOMC5_0 (0x1U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00100000 */ +#define GPIO_CFGLR_IOMC5_1 (0x2U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00200000 */ + +#define GPIO_CFGLR_IOMC6_Pos (24U) +#define GPIO_CFGLR_IOMC6_Msk (0x3U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x03000000 */ +#define GPIO_CFGLR_IOMC6 GPIO_CFGLR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ +#define GPIO_CFGLR_IOMC6_0 (0x1U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x01000000 */ +#define GPIO_CFGLR_IOMC6_1 (0x2U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x02000000 */ + +#define GPIO_CFGLR_IOMC7_Pos (28U) +#define GPIO_CFGLR_IOMC7_Msk (0x3U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x30000000 */ +#define GPIO_CFGLR_IOMC7 GPIO_CFGLR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ +#define GPIO_CFGLR_IOMC7_0 (0x1U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x10000000 */ +#define GPIO_CFGLR_IOMC7_1 (0x2U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x20000000 */ + +#define GPIO_CFGLR_IOFC_Pos (2U) +#define GPIO_CFGLR_IOFC_Msk (0x33333333U << GPIO_CFGLR_IOFC_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CFGLR_IOFC GPIO_CFGLR_IOFC_Msk /*!< GPIO x function configuration */ + +#define GPIO_CFGLR_IOFC0_Pos (2U) +#define GPIO_CFGLR_IOFC0_Msk (0x3U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x0000000C */ +#define GPIO_CFGLR_IOFC0 GPIO_CFGLR_IOFC0_Msk /*!< IOFC0[1:0] bits (GPIO x function configuration, pin 0) */ +#define GPIO_CFGLR_IOFC0_0 (0x1U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000004 */ +#define GPIO_CFGLR_IOFC0_1 (0x2U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000008 */ + +#define GPIO_CFGLR_IOFC1_Pos (6U) +#define GPIO_CFGLR_IOFC1_Msk (0x3U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGLR_IOFC1 GPIO_CFGLR_IOFC1_Msk /*!< IOFC1[1:0] bits (GPIO x function configuration, pin 1) */ +#define GPIO_CFGLR_IOFC1_0 (0x1U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000040 */ +#define GPIO_CFGLR_IOFC1_1 (0x2U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000080 */ + +#define GPIO_CFGLR_IOFC2_Pos (10U) +#define GPIO_CFGLR_IOFC2_Msk (0x3U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGLR_IOFC2 GPIO_CFGLR_IOFC2_Msk /*!< IOFC2[1:0] bits (GPIO x function configuration, pin 2) */ +#define GPIO_CFGLR_IOFC2_0 (0x1U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000400 */ +#define GPIO_CFGLR_IOFC2_1 (0x2U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000800 */ + +#define GPIO_CFGLR_IOFC3_Pos (14U) +#define GPIO_CFGLR_IOFC3_Msk (0x3U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGLR_IOFC3 GPIO_CFGLR_IOFC3_Msk /*!< IOFC3[1:0] bits (GPIO x function configuration, pin 3) */ +#define GPIO_CFGLR_IOFC3_0 (0x1U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00004000 */ +#define GPIO_CFGLR_IOFC3_1 (0x2U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00008000 */ + +#define GPIO_CFGLR_IOFC4_Pos (18U) +#define GPIO_CFGLR_IOFC4_Msk (0x3U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGLR_IOFC4 GPIO_CFGLR_IOFC4_Msk /*!< IOFC4[1:0] bits (GPIO x function configuration, pin 4) */ +#define GPIO_CFGLR_IOFC4_0 (0x1U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00040000 */ +#define GPIO_CFGLR_IOFC4_1 (0x2U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00080000 */ + +#define GPIO_CFGLR_IOFC5_Pos (22U) +#define GPIO_CFGLR_IOFC5_Msk (0x3U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGLR_IOFC5 GPIO_CFGLR_IOFC5_Msk /*!< IOFC5[1:0] bits (GPIO x function configuration, pin 5) */ +#define GPIO_CFGLR_IOFC5_0 (0x1U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00400000 */ +#define GPIO_CFGLR_IOFC5_1 (0x2U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00800000 */ + +#define GPIO_CFGLR_IOFC6_Pos (26U) +#define GPIO_CFGLR_IOFC6_Msk (0x3U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGLR_IOFC6 GPIO_CFGLR_IOFC6_Msk /*!< IOFC6[1:0] bits (GPIO x function configuration, pin 6) */ +#define GPIO_CFGLR_IOFC6_0 (0x1U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x04000000 */ +#define GPIO_CFGLR_IOFC6_1 (0x2U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x08000000 */ + +#define GPIO_CFGLR_IOFC7_Pos (30U) +#define GPIO_CFGLR_IOFC7_Msk (0x3U << GPIO_CFGLR_IOFC7_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGLR_IOFC7 GPIO_CFGLR_IOFC7_Msk /*!< IOFC7[1:0] bits (GPIO x function configuration, pin 7) */ +#define GPIO_CFGLR_IOFC7_0 (0x1U << GPIO_CFGLR_IOFC7_Pos) /*!< 0x40000000 */ +#define GPIO_CFGLR_IOFC7_1 (0x2U << GPIO_CFGLR_IOFC7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_CFGHR register ******************/ +#define GPIO_CFGHR_IOMC_Pos (0U) +#define GPIO_CFGHR_IOMC_Msk (0x33333333U << GPIO_CFGHR_IOMC_Pos) /*!< 0x33333333 */ +#define GPIO_CFGHR_IOMC GPIO_CFGHR_IOMC_Msk /*!< GPIO x mode configuration */ + +#define GPIO_CFGHR_IOMC8_Pos (0U) +#define GPIO_CFGHR_IOMC8_Msk (0x3U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000003 */ +#define GPIO_CFGHR_IOMC8 GPIO_CFGHR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ +#define GPIO_CFGHR_IOMC8_0 (0x1U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000001 */ +#define GPIO_CFGHR_IOMC8_1 (0x2U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000002 */ + +#define GPIO_CFGHR_IOMC9_Pos (4U) +#define GPIO_CFGHR_IOMC9_Msk (0x3U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000030 */ +#define GPIO_CFGHR_IOMC9 GPIO_CFGHR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ +#define GPIO_CFGHR_IOMC9_0 (0x1U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000010 */ +#define GPIO_CFGHR_IOMC9_1 (0x2U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000020 */ + +#define GPIO_CFGHR_IOMC10_Pos (8U) +#define GPIO_CFGHR_IOMC10_Msk (0x3U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000300 */ +#define GPIO_CFGHR_IOMC10 GPIO_CFGHR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ +#define GPIO_CFGHR_IOMC10_0 (0x1U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000100 */ +#define GPIO_CFGHR_IOMC10_1 (0x2U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000200 */ + +#define GPIO_CFGHR_IOMC11_Pos (12U) +#define GPIO_CFGHR_IOMC11_Msk (0x3U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00003000 */ +#define GPIO_CFGHR_IOMC11 GPIO_CFGHR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ +#define GPIO_CFGHR_IOMC11_0 (0x1U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00001000 */ +#define GPIO_CFGHR_IOMC11_1 (0x2U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00002000 */ + +#define GPIO_CFGHR_IOMC12_Pos (16U) +#define GPIO_CFGHR_IOMC12_Msk (0x3U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00030000 */ +#define GPIO_CFGHR_IOMC12 GPIO_CFGHR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ +#define GPIO_CFGHR_IOMC12_0 (0x1U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00010000 */ +#define GPIO_CFGHR_IOMC12_1 (0x2U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00020000 */ + +#define GPIO_CFGHR_IOMC13_Pos (20U) +#define GPIO_CFGHR_IOMC13_Msk (0x3U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00300000 */ +#define GPIO_CFGHR_IOMC13 GPIO_CFGHR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ +#define GPIO_CFGHR_IOMC13_0 (0x1U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00100000 */ +#define GPIO_CFGHR_IOMC13_1 (0x2U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00200000 */ + +#define GPIO_CFGHR_IOMC14_Pos (24U) +#define GPIO_CFGHR_IOMC14_Msk (0x3U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x03000000 */ +#define GPIO_CFGHR_IOMC14 GPIO_CFGHR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ +#define GPIO_CFGHR_IOMC14_0 (0x1U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x01000000 */ +#define GPIO_CFGHR_IOMC14_1 (0x2U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x02000000 */ + +#define GPIO_CFGHR_IOMC15_Pos (28U) +#define GPIO_CFGHR_IOMC15_Msk (0x3U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x30000000 */ +#define GPIO_CFGHR_IOMC15 GPIO_CFGHR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ +#define GPIO_CFGHR_IOMC15_0 (0x1U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x10000000 */ +#define GPIO_CFGHR_IOMC15_1 (0x2U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x20000000 */ + +#define GPIO_CFGHR_IOFC_Pos (2U) +#define GPIO_CFGHR_IOFC_Msk (0x33333333U << GPIO_CFGHR_IOFC_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CFGHR_IOFC GPIO_CFGHR_IOFC_Msk /*!< GPIO x function configuration */ + +#define GPIO_CFGHR_IOFC8_Pos (2U) +#define GPIO_CFGHR_IOFC8_Msk (0x3U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x0000000C */ +#define GPIO_CFGHR_IOFC8 GPIO_CFGHR_IOFC8_Msk /*!< IOFC8[1:0] bits (GPIO x function configuration, pin 8) */ +#define GPIO_CFGHR_IOFC8_0 (0x1U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000004 */ +#define GPIO_CFGHR_IOFC8_1 (0x2U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000008 */ + +#define GPIO_CFGHR_IOFC9_Pos (6U) +#define GPIO_CFGHR_IOFC9_Msk (0x3U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGHR_IOFC9 GPIO_CFGHR_IOFC9_Msk /*!< IOFC9[1:0] bits (GPIO x function configuration, pin 9) */ +#define GPIO_CFGHR_IOFC9_0 (0x1U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000040 */ +#define GPIO_CFGHR_IOFC9_1 (0x2U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000080 */ + +#define GPIO_CFGHR_IOFC10_Pos (10U) +#define GPIO_CFGHR_IOFC10_Msk (0x3U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGHR_IOFC10 GPIO_CFGHR_IOFC10_Msk /*!< IOFC10[1:0] bits (GPIO x function configuration, pin 10) */ +#define GPIO_CFGHR_IOFC10_0 (0x1U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000400 */ +#define GPIO_CFGHR_IOFC10_1 (0x2U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000800 */ + +#define GPIO_CFGHR_IOFC11_Pos (14U) +#define GPIO_CFGHR_IOFC11_Msk (0x3U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGHR_IOFC11 GPIO_CFGHR_IOFC11_Msk /*!< IOFC11[1:0] bits (GPIO x function configuration, pin 11) */ +#define GPIO_CFGHR_IOFC11_0 (0x1U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00004000 */ +#define GPIO_CFGHR_IOFC11_1 (0x2U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00008000 */ + +#define GPIO_CFGHR_IOFC12_Pos (18U) +#define GPIO_CFGHR_IOFC12_Msk (0x3U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGHR_IOFC12 GPIO_CFGHR_IOFC12_Msk /*!< IOFC12[1:0] bits (GPIO x function configuration, pin 12) */ +#define GPIO_CFGHR_IOFC12_0 (0x1U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00040000 */ +#define GPIO_CFGHR_IOFC12_1 (0x2U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00080000 */ + +#define GPIO_CFGHR_IOFC13_Pos (22U) +#define GPIO_CFGHR_IOFC13_Msk (0x3U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGHR_IOFC13 GPIO_CFGHR_IOFC13_Msk /*!< IOFC13[1:0] bits (GPIO x function configuration, pin 13) */ +#define GPIO_CFGHR_IOFC13_0 (0x1U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00400000 */ +#define GPIO_CFGHR_IOFC13_1 (0x2U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00800000 */ + +#define GPIO_CFGHR_IOFC14_Pos (26U) +#define GPIO_CFGHR_IOFC14_Msk (0x3U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGHR_IOFC14 GPIO_CFGHR_IOFC14_Msk /*!< IOFC14[1:0] bits (GPIO x function configuration, pin 14) */ +#define GPIO_CFGHR_IOFC14_0 (0x1U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x04000000 */ +#define GPIO_CFGHR_IOFC14_1 (0x2U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x08000000 */ + +#define GPIO_CFGHR_IOFC15_Pos (30U) +#define GPIO_CFGHR_IOFC15_Msk (0x3U << GPIO_CFGHR_IOFC15_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGHR_IOFC15 GPIO_CFGHR_IOFC15_Msk /*!< IOFC15[1:0] bits (GPIO x function configuration, pin 15) */ +#define GPIO_CFGHR_IOFC15_0 (0x1U << GPIO_CFGHR_IOFC15_Pos) /*!< 0x40000000 */ +#define GPIO_CFGHR_IOFC15_1 (0x2U << GPIO_CFGHR_IOFC15_Pos) /*!< 0x80000000 */ + +/*!<**************** Bit definition for GPIO_IDT register *******************/ +#define GPIO_IDT_IDT0_Pos (0U) +#define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, bit 0 */ +#define GPIO_IDT_IDT1_Pos (1U) +#define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, bit 1 */ +#define GPIO_IDT_IDT2_Pos (2U) +#define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, bit 2 */ +#define GPIO_IDT_IDT3_Pos (3U) +#define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, bit 3 */ +#define GPIO_IDT_IDT4_Pos (4U) +#define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, bit 4 */ +#define GPIO_IDT_IDT5_Pos (5U) +#define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, bit 5 */ +#define GPIO_IDT_IDT6_Pos (6U) +#define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, bit 6 */ +#define GPIO_IDT_IDT7_Pos (7U) +#define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, bit 7 */ +#define GPIO_IDT_IDT8_Pos (8U) +#define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, bit 8 */ +#define GPIO_IDT_IDT9_Pos (9U) +#define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, bit 9 */ +#define GPIO_IDT_IDT10_Pos (10U) +#define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, bit 10 */ +#define GPIO_IDT_IDT11_Pos (11U) +#define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, bit 11 */ +#define GPIO_IDT_IDT12_Pos (12U) +#define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, bit 12 */ +#define GPIO_IDT_IDT13_Pos (13U) +#define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, bit 13 */ +#define GPIO_IDT_IDT14_Pos (14U) +#define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, bit 14 */ +#define GPIO_IDT_IDT15_Pos (15U) +#define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, bit 15 */ + +/******************* Bit definition for GPIO_ODT register *******************/ +#define GPIO_ODT_ODT0_Pos (0U) +#define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, bit 0 */ +#define GPIO_ODT_ODT1_Pos (1U) +#define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, bit 1 */ +#define GPIO_ODT_ODT2_Pos (2U) +#define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, bit 2 */ +#define GPIO_ODT_ODT3_Pos (3U) +#define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, bit 3 */ +#define GPIO_ODT_ODT4_Pos (4U) +#define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, bit 4 */ +#define GPIO_ODT_ODT5_Pos (5U) +#define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, bit 5 */ +#define GPIO_ODT_ODT6_Pos (6U) +#define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, bit 6 */ +#define GPIO_ODT_ODT7_Pos (7U) +#define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, bit 7 */ +#define GPIO_ODT_ODT8_Pos (8U) +#define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, bit 8 */ +#define GPIO_ODT_ODT9_Pos (9U) +#define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, bit 9 */ +#define GPIO_ODT_ODT10_Pos (10U) +#define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, bit 10 */ +#define GPIO_ODT_ODT11_Pos (11U) +#define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, bit 11 */ +#define GPIO_ODT_ODT12_Pos (12U) +#define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, bit 12 */ +#define GPIO_ODT_ODT13_Pos (13U) +#define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, bit 13 */ +#define GPIO_ODT_ODT14_Pos (14U) +#define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, bit 14 */ +#define GPIO_ODT_ODT15_Pos (15U) +#define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, bit 15 */ + +/******************* Bit definition for GPIO_SCR register *******************/ +#define GPIO_SCR_IOSB0_Pos (0U) +#define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit 0 */ +#define GPIO_SCR_IOSB1_Pos (1U) +#define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit 1 */ +#define GPIO_SCR_IOSB2_Pos (2U) +#define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit 2 */ +#define GPIO_SCR_IOSB3_Pos (3U) +#define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit 3 */ +#define GPIO_SCR_IOSB4_Pos (4U) +#define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit 4 */ +#define GPIO_SCR_IOSB5_Pos (5U) +#define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit 5 */ +#define GPIO_SCR_IOSB6_Pos (6U) +#define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit 6 */ +#define GPIO_SCR_IOSB7_Pos (7U) +#define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit 7 */ +#define GPIO_SCR_IOSB8_Pos (8U) +#define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit 8 */ +#define GPIO_SCR_IOSB9_Pos (9U) +#define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit 9 */ +#define GPIO_SCR_IOSB10_Pos (10U) +#define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit 10 */ +#define GPIO_SCR_IOSB11_Pos (11U) +#define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit 11 */ +#define GPIO_SCR_IOSB12_Pos (12U) +#define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit 12 */ +#define GPIO_SCR_IOSB13_Pos (13U) +#define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit 13 */ +#define GPIO_SCR_IOSB14_Pos (14U) +#define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit 14 */ +#define GPIO_SCR_IOSB15_Pos (15U) +#define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit 15 */ +#define GPIO_SCR_IOCB0_Pos (16U) +#define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_SCR_IOCB1_Pos (17U) +#define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_SCR_IOCB2_Pos (18U) +#define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_SCR_IOCB3_Pos (19U) +#define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_SCR_IOCB4_Pos (20U) +#define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_SCR_IOCB5_Pos (21U) +#define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_SCR_IOCB6_Pos (22U) +#define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_SCR_IOCB7_Pos (23U) +#define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_SCR_IOCB8_Pos (24U) +#define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_SCR_IOCB9_Pos (25U) +#define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_SCR_IOCB10_Pos (26U) +#define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_SCR_IOCB11_Pos (27U) +#define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_SCR_IOCB12_Pos (28U) +#define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_SCR_IOCB13_Pos (29U) +#define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_SCR_IOCB14_Pos (30U) +#define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_SCR_IOCB15_Pos (31U) +#define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit 15 */ + +/******************* Bit definition for GPIO_CLR register *******************/ +#define GPIO_CLR_IOCB0_Pos (0U) +#define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_CLR_IOCB1_Pos (1U) +#define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_CLR_IOCB2_Pos (2U) +#define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_CLR_IOCB3_Pos (3U) +#define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_CLR_IOCB4_Pos (4U) +#define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_CLR_IOCB5_Pos (5U) +#define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_CLR_IOCB6_Pos (6U) +#define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_CLR_IOCB7_Pos (7U) +#define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_CLR_IOCB8_Pos (8U) +#define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_CLR_IOCB9_Pos (9U) +#define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_CLR_IOCB10_Pos (10U) +#define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_CLR_IOCB11_Pos (11U) +#define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_CLR_IOCB12_Pos (12U) +#define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_CLR_IOCB13_Pos (13U) +#define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_CLR_IOCB14_Pos (14U) +#define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_CLR_IOCB15_Pos (15U) +#define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit 15 */ + +/******************* Bit definition for GPIO_WPR register *******************/ +#define GPIO_WPR_WPEN0_Pos (0U) +#define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable bit 0 */ +#define GPIO_WPR_WPEN1_Pos (1U) +#define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable bit 1 */ +#define GPIO_WPR_WPEN2_Pos (2U) +#define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable bit 2 */ +#define GPIO_WPR_WPEN3_Pos (3U) +#define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable bit 3 */ +#define GPIO_WPR_WPEN4_Pos (4U) +#define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable bit 4 */ +#define GPIO_WPR_WPEN5_Pos (5U) +#define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable bit 5 */ +#define GPIO_WPR_WPEN6_Pos (6U) +#define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable bit 6 */ +#define GPIO_WPR_WPEN7_Pos (7U) +#define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable bit 7 */ +#define GPIO_WPR_WPEN8_Pos (8U) +#define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable bit 8 */ +#define GPIO_WPR_WPEN9_Pos (9U) +#define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable bit 9 */ +#define GPIO_WPR_WPEN10_Pos (10U) +#define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable bit 10 */ +#define GPIO_WPR_WPEN11_Pos (11U) +#define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable bit 11 */ +#define GPIO_WPR_WPEN12_Pos (12U) +#define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable bit 12 */ +#define GPIO_WPR_WPEN13_Pos (13U) +#define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable bit 13 */ +#define GPIO_WPR_WPEN14_Pos (14U) +#define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable bit 14 */ +#define GPIO_WPR_WPEN15_Pos (15U) +#define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable bit 15 */ +#define GPIO_WPR_WPSEQ_Pos (16U) +#define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ +#define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ + +/******************************************************************************/ +/* */ +/* Multiplex function I/Os (IOMUX) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for IOMUX_EVTOUT register *****************/ +/*!< SELPIN configuration */ +#define IOMUX_EVTOUT_SELPIN_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_Msk (0xFU << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x0000000F */ +#define IOMUX_EVTOUT_SELPIN IOMUX_EVTOUT_SELPIN_Msk /*!< SELPIN[3:0] bits (Selection IO pin) */ +#define IOMUX_EVTOUT_SELPIN_0 (0x1U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000001 */ +#define IOMUX_EVTOUT_SELPIN_1 (0x2U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000002 */ +#define IOMUX_EVTOUT_SELPIN_2 (0x4U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000004 */ +#define IOMUX_EVTOUT_SELPIN_3 (0x8U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000008 */ + +#define IOMUX_EVTOUT_SELPIN_PIN0 0x00000000U /*!< Pin 0 */ +#define IOMUX_EVTOUT_SELPIN_PIN1_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN1_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN1_Pos) /*!< 0x00000001 */ +#define IOMUX_EVTOUT_SELPIN_PIN1 IOMUX_EVTOUT_SELPIN_PIN1_Msk /*!< Pin 1 */ +#define IOMUX_EVTOUT_SELPIN_PIN2_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN2_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN2_Pos) /*!< 0x00000002 */ +#define IOMUX_EVTOUT_SELPIN_PIN2 IOMUX_EVTOUT_SELPIN_PIN2_Msk /*!< Pin 2 */ +#define IOMUX_EVTOUT_SELPIN_PIN3_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN3_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN3_Pos) /*!< 0x00000003 */ +#define IOMUX_EVTOUT_SELPIN_PIN3 IOMUX_EVTOUT_SELPIN_PIN3_Msk /*!< Pin 3 */ +#define IOMUX_EVTOUT_SELPIN_PIN4_Pos (2U) +#define IOMUX_EVTOUT_SELPIN_PIN4_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN4_Pos) /*!< 0x00000004 */ +#define IOMUX_EVTOUT_SELPIN_PIN4 IOMUX_EVTOUT_SELPIN_PIN4_Msk /*!< Pin 4 */ +#define IOMUX_EVTOUT_SELPIN_PIN5_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN5_Msk (0x5U << IOMUX_EVTOUT_SELPIN_PIN5_Pos) /*!< 0x00000005 */ +#define IOMUX_EVTOUT_SELPIN_PIN5 IOMUX_EVTOUT_SELPIN_PIN5_Msk /*!< Pin 5 */ +#define IOMUX_EVTOUT_SELPIN_PIN6_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN6_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN6_Pos) /*!< 0x00000006 */ +#define IOMUX_EVTOUT_SELPIN_PIN6 IOMUX_EVTOUT_SELPIN_PIN6_Msk /*!< Pin 6 */ +#define IOMUX_EVTOUT_SELPIN_PIN7_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN7_Msk (0x7U << IOMUX_EVTOUT_SELPIN_PIN7_Pos) /*!< 0x00000007 */ +#define IOMUX_EVTOUT_SELPIN_PIN7 IOMUX_EVTOUT_SELPIN_PIN7_Msk /*!< Pin 7 */ +#define IOMUX_EVTOUT_SELPIN_PIN8_Pos (3U) +#define IOMUX_EVTOUT_SELPIN_PIN8_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN8_Pos) /*!< 0x00000008 */ +#define IOMUX_EVTOUT_SELPIN_PIN8 IOMUX_EVTOUT_SELPIN_PIN8_Msk /*!< Pin 8 */ +#define IOMUX_EVTOUT_SELPIN_PIN9_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN9_Msk (0x9U << IOMUX_EVTOUT_SELPIN_PIN9_Pos) /*!< 0x00000009 */ +#define IOMUX_EVTOUT_SELPIN_PIN9 IOMUX_EVTOUT_SELPIN_PIN9_Msk /*!< Pin 9 */ +#define IOMUX_EVTOUT_SELPIN_PIN10_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN10_Msk (0x5U << IOMUX_EVTOUT_SELPIN_PIN10_Pos) /*!< 0x0000000A */ +#define IOMUX_EVTOUT_SELPIN_PIN10 IOMUX_EVTOUT_SELPIN_PIN10_Msk /*!< Pin 10 */ +#define IOMUX_EVTOUT_SELPIN_PIN11_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN11_Msk (0xBU << IOMUX_EVTOUT_SELPIN_PIN11_Pos) /*!< 0x0000000B */ +#define IOMUX_EVTOUT_SELPIN_PIN11 IOMUX_EVTOUT_SELPIN_PIN11_Msk /*!< Pin 11 */ +#define IOMUX_EVTOUT_SELPIN_PIN12_Pos (2U) +#define IOMUX_EVTOUT_SELPIN_PIN12_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN12_Pos) /*!< 0x0000000C */ +#define IOMUX_EVTOUT_SELPIN_PIN12 IOMUX_EVTOUT_SELPIN_PIN12_Msk /*!< Pin 12 */ +#define IOMUX_EVTOUT_SELPIN_PIN13_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN13_Msk (0xDU << IOMUX_EVTOUT_SELPIN_PIN13_Pos) /*!< 0x0000000D */ +#define IOMUX_EVTOUT_SELPIN_PIN13 IOMUX_EVTOUT_SELPIN_PIN13_Msk /*!< Pin 13 */ +#define IOMUX_EVTOUT_SELPIN_PIN14_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN14_Msk (0x7U << IOMUX_EVTOUT_SELPIN_PIN14_Pos) /*!< 0x0000000E */ +#define IOMUX_EVTOUT_SELPIN_PIN14 IOMUX_EVTOUT_SELPIN_PIN14_Msk /*!< Pin 14 */ +#define IOMUX_EVTOUT_SELPIN_PIN15_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN15_Msk (0xFU << IOMUX_EVTOUT_SELPIN_PIN15_Pos) /*!< 0x0000000F */ +#define IOMUX_EVTOUT_SELPIN_PIN15 IOMUX_EVTOUT_SELPIN_PIN15_Msk /*!< Pin 15 */ + +/*!< SELPORT configuration */ +#define IOMUX_EVTOUT_SELPORT_Pos (4U) +#define IOMUX_EVTOUT_SELPORT_Msk (0x7U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000070 */ +#define IOMUX_EVTOUT_SELPORT IOMUX_EVTOUT_SELPORT_Msk /*!< SELPORT[2:0] bits (Selection IO port) */ +#define IOMUX_EVTOUT_SELPORT_0 (0x1U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000010 */ +#define IOMUX_EVTOUT_SELPORT_1 (0x2U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000020 */ +#define IOMUX_EVTOUT_SELPORT_2 (0x4U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000040 */ + +#define IOMUX_EVTOUT_SELPORT_GPIOA 0x00000000 /*!< GPIOA */ +#define IOMUX_EVTOUT_SELPORT_GPIOB_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_EVTOUT_SELPORT_GPIOB_Msk (0x1U << IOMUX_EVTOUT_SELPORT_GPIOB_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOB IOMUX_EVTOUT_SELPORT_GPIOB_Msk /*!< GPIOB */ +#define IOMUX_EVTOUT_SELPORT_GPIOC_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_EVTOUT_SELPORT_GPIOC_Msk (0x1U << IOMUX_EVTOUT_SELPORT_GPIOC_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOC IOMUX_EVTOUT_SELPORT_GPIOC_Msk /*!< GPIOC */ +#define IOMUX_EVTOUT_SELPORT_GPIOD_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_EVTOUT_SELPORT_GPIOD_Msk (0x3U << IOMUX_EVTOUT_SELPORT_GPIOD_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOD IOMUX_EVTOUT_SELPORT_GPIOD_Msk /*!< GPIOD */ +#define IOMUX_EVTOUT_SELPORT_GPIOF_Pos (4U) /*!< 0x00000050 */ +#define IOMUX_EVTOUT_SELPORT_GPIOF_Msk (0x5U << IOMUX_EVTOUT_SELPORT_GPIOF_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOF IOMUX_EVTOUT_SELPORT_GPIOF_Msk /*!< GPIOF */ + +#define IOMUX_EVTOUT_EVOEN_Pos (7U) +#define IOMUX_EVTOUT_EVOEN_Msk (0x1U << IOMUX_EVTOUT_EVOEN_Pos) /*!< 0x00000080 */ +#define IOMUX_EVTOUT_EVOEN IOMUX_EVTOUT_EVOEN_Msk /*!< Event output enable */ + +/***************** Bit definition for IOMUX_REMAP register ******************/ +/*!< SPI1_MUX configuration */ +#define IOMUX_REMAP_SPI1_MUX_Pos (0U) +#define IOMUX_REMAP_SPI1_MUX_Msk (0x1U << IOMUX_REMAP_SPI1_MUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP_SPI1_MUX IOMUX_REMAP_SPI1_MUX_Msk /*!< SPI1 IO multiplexing */ +#define IOMUX_REMAP_I2C1_MUX_Pos (1U) +#define IOMUX_REMAP_I2C1_MUX_Msk (0x1U << IOMUX_REMAP_I2C1_MUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP_I2C1_MUX IOMUX_REMAP_I2C1_MUX_Msk /*!< I2C1 IO multiplexing */ +#define IOMUX_REMAP_USART1_MUX_Pos (2U) +#define IOMUX_REMAP_USART1_MUX_Msk (0x1U << IOMUX_REMAP_USART1_MUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP_USART1_MUX IOMUX_REMAP_USART1_MUX_Msk /*!< USART1 IO multiplexing */ + +/*!< TMR1_MUX configuration */ +#define IOMUX_REMAP_TMR1_MUX_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_Msk (0x3U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x000000C0 */ +#define IOMUX_REMAP_TMR1_MUX IOMUX_REMAP_TMR1_MUX_Msk /*!< TMR1_MUX[1:0] bits (TMR1 IO multiplexing) */ +#define IOMUX_REMAP_TMR1_MUX_0 (0x1U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_1 (0x2U << IOMUX_REMAP_TMR1_MUX_Pos /*!< 0x00000080 */ + +#define IOMUX_REMAP_TMR1_MUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX1_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1 IOMUX_REMAP_TMR1_MUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ + +/*!< TMR2_MUX configuration */ +#define IOMUX_REMAP_TMR2_MUX_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX IOMUX_REMAP_TMR2_MUX_Msk /*!< TMR2_MUX[1:0] bits (TMR2 IO multiplexing) */ +#define IOMUX_REMAP_TMR2_MUX_0 (0x1U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_1 (0x2U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000200 */ + +#define IOMUX_REMAP_TMR2_MUX_MUX0 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX1_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1 IOMUX_REMAP_TMR2_MUX_MUX1_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (9U) +#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ + +/*!< TMR3_MUX configuration */ +#define IOMUX_REMAP_TMR3_MUX_Pos (10U) +#define IOMUX_REMAP_TMR3_MUX_Msk (0x3U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000C00 */ +#define IOMUX_REMAP_TMR3_MUX IOMUX_REMAP_TMR3_MUX_Msk /*!< TMR3_MUX[1:0] bits (TMR3 IO multiplexing) */ +#define IOMUX_REMAP_TMR3_MUX_0 (0x1U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP_TMR3_MUX_1 (0x2U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP_TMR3_MUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX2_Pos (11U) +#define IOMUX_REMAP_TMR3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR3_MUX_MUX2_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP_TMR3_MUX_MUX2 IOMUX_REMAP_TMR3_MUX_MUX2_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX3_Pos (10U) +#define IOMUX_REMAP_TMR3_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR3_MUX_MUX3_Pos) /*!< 0x00000C00 */ +#define IOMUX_REMAP_TMR3_MUX_MUX3 IOMUX_REMAP_TMR3_MUX_MUX3_Msk /*!< CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9 */ + +/*!< CAN1_MUX configuration */ +#define IOMUX_REMAP_CAN1_MUX_Pos (13U) +#define IOMUX_REMAP_CAN1_MUX_Msk (0x3U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00006000 */ +#define IOMUX_REMAP_CAN1_MUX IOMUX_REMAP_CAN1_MUX_Msk /*!< CAN1_MUX[1:0] bits (CAN1 IO multiplexing) */ +#define IOMUX_REMAP_CAN1_MUX_0 (0x1U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00002000 */ +#define IOMUX_REMAP_CAN1_MUX_1 (0x2U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00004000 */ + +#define IOMUX_REMAP_CAN1_MUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP_CAN1_MUX_MUX2_Pos (14U) +#define IOMUX_REMAP_CAN1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_CAN1_MUX_MUX2_Pos) /*!< 0x00004000 */ +#define IOMUX_REMAP_CAN1_MUX_MUX2 IOMUX_REMAP_CAN1_MUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + +#define IOMUX_REMAP_PD01_MUX_Pos (15U) +#define IOMUX_REMAP_PD01_MUX_Msk (0x1U << IOMUX_REMAP_PD01_MUX_Pos) /*!< 0x00008000 */ +#define IOMUX_REMAP_PD01_MUX IOMUX_REMAP_PD01_MUX_Msk /*!< PD0/PD1 mapped on HEXT_IN/HEXT_OUT */ +#define IOMUX_REMAP_TMR5CH4_MUX_Pos (16U) +#define IOMUX_REMAP_TMR5CH4_MUX_Msk (0x1U << IOMUX_REMAP_TMR5CH4_MUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP_TMR5CH4_MUX IOMUX_REMAP_TMR5CH4_MUX_Msk /*!< TMR5 channel 4 multiplexing */ +#define IOMUX_REMAP_ADC1_ETP_MUX_Pos (17U) +#define IOMUX_REMAP_ADC1_ETP_MUX_Msk (0x1U << IOMUX_REMAP_ADC1_ETP_MUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP_ADC1_ETP_MUX IOMUX_REMAP_ADC1_ETP_MUX_Msk /*!< ADC1 external trigger preempted conversion multiplexing */ +#define IOMUX_REMAP_ADC1_ETO_MUX_Pos (18U) +#define IOMUX_REMAP_ADC1_ETO_MUX_Msk (0x1U << IOMUX_REMAP_ADC1_ETO_MUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP_ADC1_ETO_MUX IOMUX_REMAP_ADC1_ETO_MUX_Msk /*!< ADC1 external trigger regular conversion mutiplexing */ + +/*!< SWJTAG_MUX configuration */ +#define IOMUX_REMAP_SWJTAG_MUX_Pos (24U) +#define IOMUX_REMAP_SWJTAG_MUX_Msk (0x7U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x07000000 */ +#define IOMUX_REMAP_SWJTAG_MUX IOMUX_REMAP_SWJTAG_MUX_Msk /*!< SWJTAG_MUX[2:0] bits (SWD JTAG mutiplexing) */ +#define IOMUX_REMAP_SWJTAG_MUX_0 (0x1U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x01000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_1 (0x2U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x02000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_2 (0x4U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x04000000 */ + +#define IOMUX_REMAP_SWJTAG_MUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIOs */ +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Pos (25U) /*!< 0x02000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Msk /*!< Supports SWD but JTAG is disabled. PA15/PB3/PB4 can be used as GPIOs */ +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE_Pos (26U) /*!< 0x04000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_DISABLE_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE IOMUX_REMAP_SWJTAG_MUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIOs */ + +/**************** Bit definition for IOMUX_EXINTC1 register *****************/ +/*!< EXINT0 configuration */ +#define IOMUX_EXINTC1_EXINT0_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_Msk (0xFU << IOMUX_EXINTC1_EXINT0_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC1_EXINT0 IOMUX_EXINTC1_EXINT0_Msk /*!< EXINT0[3:0] bits (EXINT0 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT0_GPA 0x00000000U /*!< GPIOA pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPB_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC1_EXINT0_GPB IOMUX_EXINTC1_EXINT0_GPB_Msk /*!< GPIOB pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPC_Pos (1U) +#define IOMUX_EXINTC1_EXINT0_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC1_EXINT0_GPC IOMUX_EXINTC1_EXINT0_GPC_Msk /*!< GPIOC pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPD_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT0_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC1_EXINT0_GPD IOMUX_EXINTC1_EXINT0_GPD_Msk /*!< GPIOD pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPF_Pos (2U) +#define IOMUX_EXINTC1_EXINT0_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC1_EXINT0_GPF IOMUX_EXINTC1_EXINT0_GPF_Msk /*!< GPIOF pin 0 */ + +/*!< EXINT1 configuration */ +#define IOMUX_EXINTC1_EXINT1_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_Msk (0xFU << IOMUX_EXINTC1_EXINT1_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC1_EXINT1 IOMUX_EXINTC1_EXINT1_Msk /*!< EXINT1[3:0] bits (EXINT1 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT1_GPA 0x00000000U /*!< GPIOA pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPB_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC1_EXINT1_GPB IOMUX_EXINTC1_EXINT1_GPB_Msk /*!< GPIOB pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPC_Pos (5U) +#define IOMUX_EXINTC1_EXINT1_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC1_EXINT1_GPC IOMUX_EXINTC1_EXINT1_GPC_Msk /*!< GPIOC pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPD_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT1_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC1_EXINT1_GPD IOMUX_EXINTC1_EXINT1_GPD_Msk /*!< GPIOD pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPF_Pos (6U) +#define IOMUX_EXINTC1_EXINT1_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC1_EXINT1_GPF IOMUX_EXINTC1_EXINT1_GPF_Msk /*!< GPIOF pin 1 */ + +/*!< EXINT2 configuration */ +#define IOMUX_EXINTC1_EXINT2_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_Msk (0xFU << IOMUX_EXINTC1_EXINT2_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC1_EXINT2 IOMUX_EXINTC1_EXINT2_Msk /*!< EXINT2[3:0] bits (EXINT2 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT2_GPA 0x00000000U /*!< GPIOA pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPB_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC1_EXINT2_GPB IOMUX_EXINTC1_EXINT2_GPB_Msk /*!< GPIOB pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPC_Pos (9U) +#define IOMUX_EXINTC1_EXINT2_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC1_EXINT2_GPC IOMUX_EXINTC1_EXINT2_GPC_Msk /*!< GPIOC pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPD_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT2_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC1_EXINT2_GPD IOMUX_EXINTC1_EXINT2_GPD_Msk /*!< GPIOD pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPF_Pos (10U) +#define IOMUX_EXINTC1_EXINT2_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC1_EXINT2_GPF IOMUX_EXINTC1_EXINT2_GPF_Msk /*!< GPIOF pin 2 */ + +/*!< EXINT3 configuration */ +#define IOMUX_EXINTC1_EXINT3_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_Msk (0xFU << IOMUX_EXINTC1_EXINT3_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC1_EXINT3 IOMUX_EXINTC1_EXINT3_Msk /*!< EXINT3[3:0] bits (EXINT3 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT3_GPA 0x00000000U /*!< GPIOA pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPB_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC1_EXINT3_GPB IOMUX_EXINTC1_EXINT3_GPB_Msk /*!< GPIOB pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPC_Pos (13U) +#define IOMUX_EXINTC1_EXINT3_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC1_EXINT3_GPC IOMUX_EXINTC1_EXINT3_GPC_Msk /*!< GPIOC pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPD_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT3_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC1_EXINT3_GPD IOMUX_EXINTC1_EXINT3_GPD_Msk /*!< GPIOD pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPF_Pos (14U) +#define IOMUX_EXINTC1_EXINT3_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC1_EXINT3_GPF IOMUX_EXINTC1_EXINT3_GPF_Msk /*!< GPIOF pin 3 */ + +/**************** Bit definition for IOMUX_EXINTC2 register *****************/ +/*!< EXINT4 configuration */ +#define IOMUX_EXINTC2_EXINT4_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_Msk (0xFU << IOMUX_EXINTC2_EXINT4_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC2_EXINT4 IOMUX_EXINTC2_EXINT4_Msk /*!< EXINT4[3:0] bits (EXINT4 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT4_GPA 0x00000000U /*!< GPIOA pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPB_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC2_EXINT4_GPB IOMUX_EXINTC2_EXINT4_GPB_Msk /*!< GPIOB pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPC_Pos (1U) +#define IOMUX_EXINTC2_EXINT4_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC2_EXINT4_GPC IOMUX_EXINTC2_EXINT4_GPC_Msk /*!< GPIOC pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPD_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT4_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC2_EXINT4_GPD IOMUX_EXINTC2_EXINT4_GPD_Msk /*!< GPIOD pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPF_Pos (2U) +#define IOMUX_EXINTC2_EXINT4_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC2_EXINT4_GPF IOMUX_EXINTC2_EXINT4_GPF_Msk /*!< GPIOF pin 4 */ + +/* EXINT5 configuration */ +#define IOMUX_EXINTC2_EXINT5_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_Msk (0xFU << IOMUX_EXINTC2_EXINT5_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC2_EXINT5 IOMUX_EXINTC2_EXINT5_Msk /*!< EXINT5[3:0] bits (EXINT5 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT5_GPA 0x00000000U /*!< GPIOA pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPB_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC2_EXINT5_GPB IOMUX_EXINTC2_EXINT5_GPB_Msk /*!< GPIOB pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPC_Pos (5U) +#define IOMUX_EXINTC2_EXINT5_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC2_EXINT5_GPC IOMUX_EXINTC2_EXINT5_GPC_Msk /*!< GPIOC pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPD_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT5_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC2_EXINT5_GPD IOMUX_EXINTC2_EXINT5_GPD_Msk /*!< GPIOD pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPF_Pos (6U) +#define IOMUX_EXINTC2_EXINT5_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC2_EXINT5_GPF IOMUX_EXINTC2_EXINT5_GPF_Msk /*!< GPIOF pin 5 */ + +/*!< EXINT6 configuration */ +#define IOMUX_EXINTC2_EXINT6_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_Msk (0xFU << IOMUX_EXINTC2_EXINT6_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC2_EXINT6 IOMUX_EXINTC2_EXINT6_Msk /*!< EXINT6[3:0] bits (EXINT6 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT6_GPA 0x00000000U /*!< GPIOA pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPB_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC2_EXINT6_GPB IOMUX_EXINTC2_EXINT6_GPB_Msk /*!< GPIOB pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPC_Pos (9U) +#define IOMUX_EXINTC2_EXINT6_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC2_EXINT6_GPC IOMUX_EXINTC2_EXINT6_GPC_Msk /*!< GPIOC pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPD_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT6_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC2_EXINT6_GPD IOMUX_EXINTC2_EXINT6_GPD_Msk /*!< GPIOD pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPF_Pos (10U) +#define IOMUX_EXINTC2_EXINT6_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC2_EXINT6_GPF IOMUX_EXINTC2_EXINT6_GPF_Msk /*!< GPIOF pin 6 */ + +/*!< EXINT7 configuration */ +#define IOMUX_EXINTC2_EXINT7_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_Msk (0xFU << IOMUX_EXINTC2_EXINT7_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC2_EXINT7 IOMUX_EXINTC2_EXINT7_Msk /*!< EXINT7[3:0] bits (EXINT7 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT7_GPA 0x00000000U /*!< GPIOA pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPB_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC2_EXINT7_GPB IOMUX_EXINTC2_EXINT7_GPB_Msk /*!< GPIOB pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPC_Pos (13U) +#define IOMUX_EXINTC2_EXINT7_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC2_EXINT7_GPC IOMUX_EXINTC2_EXINT7_GPC_Msk /*!< GPIOC pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPD_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT7_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC2_EXINT7_GPD IOMUX_EXINTC2_EXINT7_GPD_Msk /*!< GPIOD pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPF_Pos (14U) +#define IOMUX_EXINTC2_EXINT7_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC2_EXINT7_GPF IOMUX_EXINTC2_EXINT7_GPF_Msk /*!< GPIOF pin 7 */ + +/**************** Bit definition for IOMUX_EXINTC3 register *****************/ +/*!< EXINT8 configuration */ +#define IOMUX_EXINTC3_EXINT8_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_Msk (0xFU << IOMUX_EXINTC3_EXINT8_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC3_EXINT8 IOMUX_EXINTC3_EXINT8_Msk /*!< EXINT8[3:0] bits (EXINT8 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT8_GPA 0x00000000U /*!< GPIOA pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPB_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC3_EXINT8_GPB IOMUX_EXINTC3_EXINT8_GPB_Msk /*!< GPIOB pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPC_Pos (1U) +#define IOMUX_EXINTC3_EXINT8_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC3_EXINT8_GPC IOMUX_EXINTC3_EXINT8_GPC_Msk /*!< GPIOC pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPD_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT8_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC3_EXINT8_GPD IOMUX_EXINTC3_EXINT8_GPD_Msk /*!< GPIOD pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPF_Pos (2U) +#define IOMUX_EXINTC3_EXINT8_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC3_EXINT8_GPF IOMUX_EXINTC3_EXINT8_GPF_Msk /*!< GPIOF pin 8 */ + +/*!< EXINT9 configuration */ +#define IOMUX_EXINTC3_EXINT9_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_Msk (0xFU << IOMUX_EXINTC3_EXINT9_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC3_EXINT9 IOMUX_EXINTC3_EXINT9_Msk /*!< EXINT9[3:0] bits (EXINT9 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT9_GPA 0x00000000U /*!< GPIOA pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPB_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC3_EXINT9_GPB IOMUX_EXINTC3_EXINT9_GPB_Msk /*!< GPIOB pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPC_Pos (5U) +#define IOMUX_EXINTC3_EXINT9_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC3_EXINT9_GPC IOMUX_EXINTC3_EXINT9_GPC_Msk /*!< GPIOC pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPD_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT9_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC3_EXINT9_GPD IOMUX_EXINTC3_EXINT9_GPD_Msk /*!< GPIOD pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPF_Pos (6U) +#define IOMUX_EXINTC3_EXINT9_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC3_EXINT9_GPF IOMUX_EXINTC3_EXINT9_GPF_Msk /*!< GPIOF pin 9 */ + +/*!< EXINT10 configuration */ +#define IOMUX_EXINTC3_EXINT10_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_Msk (0xFU << IOMUX_EXINTC3_EXINT10_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC3_EXINT10 IOMUX_EXINTC3_EXINT10_Msk /*!< EXINT10[3:0] bits (EXINT10 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT10_GPA 0x00000000U /*!< GPIOA pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPB_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC3_EXINT10_GPB IOMUX_EXINTC3_EXINT10_GPB_Msk /*!< GPIOB pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPC_Pos (9U) +#define IOMUX_EXINTC3_EXINT10_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC3_EXINT10_GPC IOMUX_EXINTC3_EXINT10_GPC_Msk /*!< GPIOC pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPD_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT10_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC3_EXINT10_GPD IOMUX_EXINTC3_EXINT10_GPD_Msk /*!< GPIOD pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPF_Pos (10U) +#define IOMUX_EXINTC3_EXINT10_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC3_EXINT10_GPF IOMUX_EXINTC3_EXINT10_GPF_Msk /*!< GPIOF pin 10 */ + +/*!< EXINT11 configuration */ +#define IOMUX_EXINTC3_EXINT11_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_Msk (0xFU << IOMUX_EXINTC3_EXINT11_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC3_EXINT11 IOMUX_EXINTC3_EXINT11_Msk /*!< EXINT11[3:0] bits (EXINT11 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT11_GPA 0x00000000U /*!< GPIOA pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPB_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC3_EXINT11_GPB IOMUX_EXINTC3_EXINT11_GPB_Msk /*!< GPIOB pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPC_Pos (13U) +#define IOMUX_EXINTC3_EXINT11_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC3_EXINT11_GPC IOMUX_EXINTC3_EXINT11_GPC_Msk /*!< GPIOC pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPD_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT11_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC3_EXINT11_GPD IOMUX_EXINTC3_EXINT11_GPD_Msk /*!< GPIOD pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPF_Pos (14U) +#define IOMUX_EXINTC3_EXINT11_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC3_EXINT11_GPF IOMUX_EXINTC3_EXINT11_GPF_Msk /*!< GPIOF pin 11 */ + +/**************** Bit definition for IOMUX_EXINTC4 register *****************/ +/* EXINT12 configuration */ +#define IOMUX_EXINTC4_EXINT12_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_Msk (0xFU << IOMUX_EXINTC4_EXINT12_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC4_EXINT12 IOMUX_EXINTC4_EXINT12_Msk /*!< EXINT12[3:0] bits (EXINT12 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT12_GPA 0x00000000U /*!< GPIOA pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPB_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC4_EXINT12_GPB IOMUX_EXINTC4_EXINT12_GPB_Msk /*!< GPIOB pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPC_Pos (1U) +#define IOMUX_EXINTC4_EXINT12_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC4_EXINT12_GPC IOMUX_EXINTC4_EXINT12_GPC_Msk /*!< GPIOC pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPD_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT12_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC4_EXINT12_GPD IOMUX_EXINTC4_EXINT12_GPD_Msk /*!< GPIOD pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPF_Pos (2U) +#define IOMUX_EXINTC4_EXINT12_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC4_EXINT12_GPF IOMUX_EXINTC4_EXINT12_GPF_Msk /*!< GPIOF pin 12 */ + +/* EXINT13 configuration */ +#define IOMUX_EXINTC4_EXINT13_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_Msk (0xFU << IOMUX_EXINTC4_EXINT13_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC4_EXINT13 IOMUX_EXINTC4_EXINT13_Msk /*!< EXINT13[3:0] bits (EXINT13 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT13_GPA 0x00000000U /*!< GPIOA pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPB_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC4_EXINT13_GPB IOMUX_EXINTC4_EXINT13_GPB_Msk /*!< GPIOB pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPC_Pos (5U) +#define IOMUX_EXINTC4_EXINT13_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC4_EXINT13_GPC IOMUX_EXINTC4_EXINT13_GPC_Msk /*!< GPIOC pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPD_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT13_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC4_EXINT13_GPD IOMUX_EXINTC4_EXINT13_GPD_Msk /*!< GPIOD pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPF_Pos (6U) +#define IOMUX_EXINTC4_EXINT13_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC4_EXINT13_GPF IOMUX_EXINTC4_EXINT13_GPF_Msk /*!< GPIOF pin 13 */ + +/*!< EXINT14 configuration */ +#define IOMUX_EXINTC4_EXINT14_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_Msk (0xFU << IOMUX_EXINTC4_EXINT14_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC4_EXINT14 IOMUX_EXINTC4_EXINT14_Msk /*!< EXINT14[3:0] bits (EXINT14 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT14_GPA 0x00000000U /*!< GPIOA pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPB_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC4_EXINT14_GPB IOMUX_EXINTC4_EXINT14_GPB_Msk /*!< GPIOB pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPC_Pos (9U) +#define IOMUX_EXINTC4_EXINT14_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC4_EXINT14_GPC IOMUX_EXINTC4_EXINT14_GPC_Msk /*!< GPIOC pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPD_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT14_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC4_EXINT14_GPD IOMUX_EXINTC4_EXINT14_GPD_Msk /*!< GPIOD pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPF_Pos (10U) +#define IOMUX_EXINTC4_EXINT14_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC4_EXINT14_GPF IOMUX_EXINTC4_EXINT14_GPF_Msk /*!< GPIOF pin 14 */ + +/*!< EXINT15 configuration */ +#define IOMUX_EXINTC4_EXINT15_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_Msk (0xFU << IOMUX_EXINTC4_EXINT15_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC4_EXINT15 IOMUX_EXINTC4_EXINT15_Msk /*!< EXINT15[3:0] bits (EXINT15 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT15_GPA 0x00000000U /*!< GPIOA pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPB_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC4_EXINT15_GPB IOMUX_EXINTC4_EXINT15_GPB_Msk /*!< GPIOB pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPC_Pos (13U) +#define IOMUX_EXINTC4_EXINT15_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC4_EXINT15_GPC IOMUX_EXINTC4_EXINT15_GPC_Msk /*!< GPIOC pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPD_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT15_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC4_EXINT15_GPD IOMUX_EXINTC4_EXINT15_GPD_Msk /*!< GPIOD pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPF_Pos (14U) +#define IOMUX_EXINTC4_EXINT15_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC4_EXINT15_GPF IOMUX_EXINTC4_EXINT15_GPF_Msk /*!< GPIOF pin 15 */ + +/***************** Bit definition for IOMUX_REMAP2 register *****************/ +/*!< CMP_MUX configuration */ +#define IOMUX_REMAP2_CMP_MUX_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ +#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ +#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP2_CMP_MUX_MUX0 0x00000000U /*!< CMP1_OUT is connected to PA0, CMP2_OUT is connected to PA2 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_MUX1_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX1_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1 IOMUX_REMAP2_CMP_MUX_MUX1_Msk /*!< CMP1_OUT is connected to PA6, CMP2_OUT is connected to PA7 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2_Pos (27U) +#define IOMUX_REMAP2_CMP_MUX_MUX2_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX2_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2 IOMUX_REMAP2_CMP_MUX_MUX2_Msk /*!< CMP1_OUT is connected to PA11, CMP2_OUT is connected to PA12 */ + +/***************** Bit definition for IOMUX_REMAP3 register *****************/ +/*!< TMR9_GMUX configuration */ +#define IOMUX_REMAP3_TMR9_GMUX_Pos (0U) +#define IOMUX_REMAP3_TMR9_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP3_TMR9_GMUX IOMUX_REMAP3_TMR9_GMUX_Msk /*!< TMR9_GMUX[3:0] bits (TMR9 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR9_GMUX_0 (0x1U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP3_TMR9_GMUX_1 (0x2U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_2 (0x4U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP3_TMR9_GMUX_3 (0x8U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP3_TMR9_GMUX_MUX0 0x00000000U /*!< CH1/PA2, CH2/PA3 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR9_GMUX_MUX2 IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk /*!< CH1/PB14, CH2/PB15 */ + +/*!< TMR10_GMUX configuration */ +#define IOMUX_REMAP3_TMR10_GMUX_Pos (4U) +#define IOMUX_REMAP3_TMR10_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x000000F0 */ +#define IOMUX_REMAP3_TMR10_GMUX IOMUX_REMAP3_TMR10_GMUX_Msk /*!< TMR10_GMUX[3:0] bits (TMR10 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR10_GMUX_0 (0x1U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP3_TMR10_GMUX_1 (0x2U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_2 (0x4U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP3_TMR10_GMUX_3 (0x8U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP3_TMR10_GMUX_MUX0 0x00000000U /*!< CH1/PB8 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR10_GMUX_MUX2 IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk /*!< CH1/PA6 */ + +/*!< TMR11_GMUX configuration */ +#define IOMUX_REMAP3_TMR11_GMUX_Pos (8U) +#define IOMUX_REMAP3_TMR11_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP3_TMR11_GMUX IOMUX_REMAP3_TMR11_GMUX_Msk /*!< TMR11_GMUX[3:0] bits (TMR11 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR11_GMUX_0 (0x1U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP3_TMR11_GMUX_1 (0x2U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP3_TMR11_GMUX_2 (0x4U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */ + +/***************** Bit definition for IOMUX_REMAP4 register *****************/ +/*!< TMR1_GMUX configuration */ +#define IOMUX_REMAP4_TMR1_GMUX_Pos (0U) +#define IOMUX_REMAP4_TMR1_GMUX_Msk (0xFU << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP4_TMR1_GMUX IOMUX_REMAP4_TMR1_GMUX_Msk /*!< TMR1_GMUX[3:0] bits (TMR1 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR1_GMUX_0 (0x1U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_1 (0x2U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP4_TMR1_GMUX_2 (0x4U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP4_TMR1_GMUX_3 (0x8U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP4_TMR1_GMUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX1 IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ + +/*!< TMR2_GMUX configuration */ +#define IOMUX_REMAP4_TMR2_GMUX_Pos (4U) +#define IOMUX_REMAP4_TMR2_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000070 */ +#define IOMUX_REMAP4_TMR2_GMUX IOMUX_REMAP4_TMR2_GMUX_Msk /*!< TMR2_GMUX[2:0] bits (TMR2 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR2_GMUX_0 (0x1U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_1 (0x2U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP4_TMR2_GMUX_2 (0x4U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000040 */ + +#define IOMUX_REMAP4_TMR2_GMUX_MUX0 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX1 IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ + +/*!< TMR3_GMUX configuration */ +#define IOMUX_REMAP4_TMR3_GMUX_Pos (8U) +#define IOMUX_REMAP4_TMR3_GMUX_Msk (0xFU << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP4_TMR3_GMUX IOMUX_REMAP4_TMR3_GMUX_Msk /*!< TMR3_GMUX[3:0] bits (TMR3 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR3_GMUX_0 (0x1U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_1 (0x2U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP4_TMR3_GMUX_2 (0x4U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP4_TMR3_GMUX_3 (0x8U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP4_TMR3_GMUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR3_GMUX_MUX1 IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ + +/*!< TMR5_GMUX configuration */ +#define IOMUX_REMAP4_TMR5_GMUX_Pos (16U) +#define IOMUX_REMAP4_TMR5_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00070000 */ +#define IOMUX_REMAP4_TMR5_GMUX IOMUX_REMAP4_TMR5_GMUX_Msk /*!< TMR5_GMUX[2:0] bits (TMR5 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR5_GMUX_0 (0x1U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_1 (0x2U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP4_TMR5_GMUX_2 (0x4U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00040000 */ + +#define IOMUX_REMAP4_TMR5_GMUX_MUX0 0x00000000U /*!< CH1/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR5_GMUX_MUX1 IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk /*!< CH1/PF4, CH2/PF5, CH3/PA2, CH4/PA3 */ + +#define IOMUX_REMAP4_TMR5CH4_GMUX_Pos (19U) +#define IOMUX_REMAP4_TMR5CH4_GMUX_Msk (0x1U << IOMUX_REMAP4_TMR5CH4_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP4_TMR5CH4_GMUX IOMUX_REMAP4_TMR5CH4_GMUX_Msk /*!< TMR5 channel 4 general multiplexing */ + +/***************** Bit definition for IOMUX_REMAP5 register *****************/ +/*!< I2C1_GMUX configuration */ +#define IOMUX_REMAP5_I2C1_GMUX_Pos (4U) +#define IOMUX_REMAP5_I2C1_GMUX_Msk (0xFU << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x000000F0 */ +#define IOMUX_REMAP5_I2C1_GMUX IOMUX_REMAP5_I2C1_GMUX_Msk /*!< I2C1_GMUX[3:0] bits (I2C1 IO general multiplexing) */ +#define IOMUX_REMAP5_I2C1_GMUX_0 (0x1U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_1 (0x2U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP5_I2C1_GMUX_2 (0x4U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP5_I2C1_GMUX_3 (0x8U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP5_I2C1_GMUX_MUX0 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX1 IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ + +/*!< I2C2_GMUX configuration */ +#define IOMUX_REMAP5_I2C2_GMUX_Pos (8U) +#define IOMUX_REMAP5_I2C2_GMUX_Msk (0xFU << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP5_I2C2_GMUX IOMUX_REMAP5_I2C2_GMUX_Msk /*!< I2C2_GMUX[3:0] bits (I2C2 IO general multiplexing) */ +#define IOMUX_REMAP5_I2C2_GMUX_0 (0x1U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_1 (0x2U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP5_I2C2_GMUX_2 (0x4U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP5_I2C2_GMUX_3 (0x8U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP5_I2C2_GMUX_MUX0 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX1 IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (8U) /*!< 0x00000300 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ + +/*!< SPI1_GMUX configuration */ +#define IOMUX_REMAP5_SPI1_GMUX_Pos (16U) +#define IOMUX_REMAP5_SPI1_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x000F0000 */ +#define IOMUX_REMAP5_SPI1_GMUX IOMUX_REMAP5_SPI1_GMUX_Msk /*!< SPI1_GMUX[3:0] bits (SPI1 IO general multiplexing) */ +#define IOMUX_REMAP5_SPI1_GMUX_0 (0x1U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_1 (0x2U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP5_SPI1_GMUX_2 (0x4U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP5_SPI1_GMUX_3 (0x8U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00080000 */ + +#define IOMUX_REMAP5_SPI1_GMUX_MUX0 0x00000000U /*!< CS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7, MCK/PB0 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI1_GMUX_MUX1 IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PB6 */ + +/*!< SPI2_GMUX configuration */ +#define IOMUX_REMAP5_SPI2_GMUX_Pos (20U) +#define IOMUX_REMAP5_SPI2_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00F00000 */ +#define IOMUX_REMAP5_SPI2_GMUX IOMUX_REMAP5_SPI2_GMUX_Msk /*!< SPI2_GMUX[3:0] bits (SPI2 IO general multiplexing) */ +#define IOMUX_REMAP5_SPI2_GMUX_0 (0x1U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_1 (0x2U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00200000 */ +#define IOMUX_REMAP5_SPI2_GMUX_2 (0x4U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00400000 */ +#define IOMUX_REMAP5_SPI2_GMUX_3 (0x8U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00800000 */ + +#define IOMUX_REMAP5_SPI2_GMUX_MUX0 0x00000000U /*!< CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15, MCK/PC6 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos (20U) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI2_GMUX_MUX1 IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PC7 */ + +/***************** Bit definition for IOMUX_REMAP6 register *****************/ +/*!< CAN1_GMUX configuration */ +#define IOMUX_REMAP6_CAN1_GMUX_Pos (0U) +#define IOMUX_REMAP6_CAN1_GMUX_Msk (0xFU << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP6_CAN1_GMUX IOMUX_REMAP6_CAN1_GMUX_Msk /*!< CAN1_GMUX[3:0] bits (CAN1 IO general multiplexing) */ +#define IOMUX_REMAP6_CAN1_GMUX_0 (0x1U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP6_CAN1_GMUX_1 (0x2U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_2 (0x4U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP6_CAN1_GMUX_3 (0x8U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP6_CAN1_GMUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_CAN1_GMUX_MUX2 IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + +/*!< SDIO_GMUX configuration */ +#define IOMUX_REMAP6_SDIO_GMUX_Pos (8U) +#define IOMUX_REMAP6_SDIO_GMUX_Msk (0xFU << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP6_SDIO_GMUX IOMUX_REMAP6_SDIO_GMUX_Msk /*!< SDIO_GMUX[3:0] bits (SDIO IO general multiplexing) */ +#define IOMUX_REMAP6_SDIO_GMUX_0 (0x1U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP6_SDIO_GMUX_1 (0x2U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP6_SDIO_GMUX_2 (0x4U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_3 (0x8U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP6_SDIO_GMUX_MUX0 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (10U) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000500 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos (9U) /*!< 0x00000600 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX6 IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos (8U) /*!< 0x00000700 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX7 IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ + +/*!< USART1_GMUX configuration */ +#define IOMUX_REMAP6_USART1_GMUX_Pos (16U) +#define IOMUX_REMAP6_USART1_GMUX_Msk (0xFU << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x000F0000 */ +#define IOMUX_REMAP6_USART1_GMUX IOMUX_REMAP6_USART1_GMUX_Msk /*!< USART1_GMUX[3:0] bits (USART1 IO general multiplexing) */ +#define IOMUX_REMAP6_USART1_GMUX_0 (0x1U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_1 (0x2U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP6_USART1_GMUX_2 (0x4U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP6_USART1_GMUX_3 (0x8U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00080000 */ + +#define IOMUX_REMAP6_USART1_GMUX_MUX0 0x00000000U /*!< TX/PA9, RX/PA10 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART1_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART1_GMUX_MUX1 IOMUX_REMAP6_USART1_GMUX_MUX1_Msk /*!< TX/PB6, RX/PB7 */ + +/***************** Bit definition for IOMUX_REMAP7 register *****************/ +#define IOMUX_REMAP7_ADC1_ETP_GMUX_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP7_ADC1_ETP_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETP_GMUX_Pos) +#define IOMUX_REMAP7_ADC1_ETP_GMUX IOMUX_REMAP7_ADC1_ETP_GMUX_Msk /*!< ADC1 External trigger preempted conversion general multiplexing */ +#define IOMUX_REMAP7_ADC1_ETO_GMUX_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP7_ADC1_ETO_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETO_GMUX_Pos) +#define IOMUX_REMAP7_ADC1_ETO_GMUX IOMUX_REMAP7_ADC1_ETO_GMUX_Msk /*!< ADC1 external trigger regular conversion general multiplexing */ + +/*!< SWJTAG_GMUX configuration */ +#define IOMUX_REMAP7_SWJTAG_GMUX_Pos (16U) +#define IOMUX_REMAP7_SWJTAG_GMUX_Msk (0x7U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00070000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX IOMUX_REMAP7_SWJTAG_GMUX_Msk /*!< SWJTAG_GMUX[2:0] bits (SWD JTAG IO general mutiplexing) */ +#define IOMUX_REMAP7_SWJTAG_GMUX_0 (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_1 (0x2U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_2 (0x4U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00040000 */ + +#define IOMUX_REMAP7_SWJTAG_GMUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos (17U) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos (18U) /*!< 0x00040000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ + +#define IOMUX_REMAP7_PD01_GMUX_Pos (20U) +#define IOMUX_REMAP7_PD01_GMUX_Msk (0x1U << IOMUX_REMAP7_PD01_GMUX_Pos) /*!< 0x00100000 */ +#define IOMUX_REMAP7_PD01_GMUX IOMUX_REMAP7_PD01_GMUX_Msk /*!< PD0/PD1 mapped onto HEXT_IN / HEXT_OUT */ + +/***************** Bit definition for IOMUX_REMAP8 register *****************/ +/*!< TMR1_BK1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Msk /*!< TMR1_BK1_CMP_GMUX[1:0] bits (TMR1 break channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */ + +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ + +/*!< TMR1_CH1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk /*!< TMR1_CH1_CMP_GMUX[1:0] bits (TMR1 channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 channel 1 */ + +/*!< TMR2_CH4_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk /*!< TMR2_CH4_CMP_GMUX[1:0] bits (TMR2 channel 4 internal mapping) */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */ + +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 */ + +/*!< TMR3_CH1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk /*!< TMR3_CH1_CMP_GMUX[1:0] bits (TMR3 channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR3_GMUX IO signal is connected to TMR3 channel 1 */ + +/******************************************************************************/ +/* */ +/* External interrupt/Event controller (EXINT) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for EXINT_INTEN register ******************/ +#define EXINT_INTEN_INTEN0_Pos (0U) +#define EXINT_INTEN_INTEN0_Msk (0x1U << EXINT_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_INTEN_INTEN0 EXINT_INTEN_INTEN0_Msk /*!< Interrupt enable or disable on line 0 */ +#define EXINT_INTEN_INTEN1_Pos (1U) +#define EXINT_INTEN_INTEN1_Msk (0x1U << EXINT_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_INTEN_INTEN1 EXINT_INTEN_INTEN1_Msk /*!< Interrupt enable or disable on line 1 */ +#define EXINT_INTEN_INTEN2_Pos (2U) +#define EXINT_INTEN_INTEN2_Msk (0x1U << EXINT_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_INTEN_INTEN2 EXINT_INTEN_INTEN2_Msk /*!< Interrupt enable or disable on line 2 */ +#define EXINT_INTEN_INTEN3_Pos (3U) +#define EXINT_INTEN_INTEN3_Msk (0x1U << EXINT_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_INTEN_INTEN3 EXINT_INTEN_INTEN3_Msk /*!< Interrupt enable or disable on line 3 */ +#define EXINT_INTEN_INTEN4_Pos (4U) +#define EXINT_INTEN_INTEN4_Msk (0x1U << EXINT_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_INTEN_INTEN4 EXINT_INTEN_INTEN4_Msk /*!< Interrupt enable or disable on line 4 */ +#define EXINT_INTEN_INTEN5_Pos (5U) +#define EXINT_INTEN_INTEN5_Msk (0x1U << EXINT_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_INTEN_INTEN5 EXINT_INTEN_INTEN5_Msk /*!< Interrupt enable or disable on line 5 */ +#define EXINT_INTEN_INTEN6_Pos (6U) +#define EXINT_INTEN_INTEN6_Msk (0x1U << EXINT_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_INTEN_INTEN6 EXINT_INTEN_INTEN6_Msk /*!< Interrupt enable or disable on line 6 */ +#define EXINT_INTEN_INTEN7_Pos (7U) +#define EXINT_INTEN_INTEN7_Msk (0x1U << EXINT_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_INTEN_INTEN7 EXINT_INTEN_INTEN7_Msk /*!< Interrupt enable or disable on line 7 */ +#define EXINT_INTEN_INTEN8_Pos (8U) +#define EXINT_INTEN_INTEN8_Msk (0x1U << EXINT_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_INTEN_INTEN8 EXINT_INTEN_INTEN8_Msk /*!< Interrupt enable or disable on line 8 */ +#define EXINT_INTEN_INTEN9_Pos (9U) +#define EXINT_INTEN_INTEN9_Msk (0x1U << EXINT_INTEN_INTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_INTEN_INTEN9 EXINT_INTEN_INTEN9_Msk /*!< Interrupt enable or disable on line 9 */ +#define EXINT_INTEN_INTEN10_Pos (10U) +#define EXINT_INTEN_INTEN10_Msk (0x1U << EXINT_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_INTEN_INTEN10 EXINT_INTEN_INTEN10_Msk /*!< Interrupt enable or disable on line 10 */ +#define EXINT_INTEN_INTEN11_Pos (11U) +#define EXINT_INTEN_INTEN11_Msk (0x1U << EXINT_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_INTEN_INTEN11 EXINT_INTEN_INTEN11_Msk /*!< Interrupt enable or disable on line 11 */ +#define EXINT_INTEN_INTEN12_Pos (12U) +#define EXINT_INTEN_INTEN12_Msk (0x1U << EXINT_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_INTEN_INTEN12 EXINT_INTEN_INTEN12_Msk /*!< Interrupt enable or disable on line 12 */ +#define EXINT_INTEN_INTEN13_Pos (13U) +#define EXINT_INTEN_INTEN13_Msk (0x1U << EXINT_INTEN_INTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_INTEN_INTEN13 EXINT_INTEN_INTEN13_Msk /*!< Interrupt enable or disable on line 13 */ +#define EXINT_INTEN_INTEN14_Pos (14U) +#define EXINT_INTEN_INTEN14_Msk (0x1U << EXINT_INTEN_INTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_INTEN_INTEN14 EXINT_INTEN_INTEN14_Msk /*!< Interrupt enable or disable on line 14 */ +#define EXINT_INTEN_INTEN15_Pos (15U) +#define EXINT_INTEN_INTEN15_Msk (0x1U << EXINT_INTEN_INTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_INTEN_INTEN15 EXINT_INTEN_INTEN15_Msk /*!< Interrupt enable or disable on line 15 */ +#define EXINT_INTEN_INTEN16_Pos (16U) +#define EXINT_INTEN_INTEN16_Msk (0x1U << EXINT_INTEN_INTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_INTEN_INTEN16 EXINT_INTEN_INTEN16_Msk /*!< Interrupt enable or disable on line 16 */ +#define EXINT_INTEN_INTEN17_Pos (17U) +#define EXINT_INTEN_INTEN17_Msk (0x1U << EXINT_INTEN_INTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_INTEN_INTEN17 EXINT_INTEN_INTEN17_Msk /*!< Interrupt enable or disable on line 17 */ +#define EXINT_INTEN_INTEN18_Pos (18U) +#define EXINT_INTEN_INTEN18_Msk (0x1U << EXINT_INTEN_INTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_INTEN_INTEN18 EXINT_INTEN_INTEN18_Msk /*!< Interrupt enable or disable on line 18 */ +#define EXINT_INTEN_INTEN19_Pos (19U) +#define EXINT_INTEN_INTEN19_Msk (0x1U << EXINT_INTEN_INTEN19_Pos) /*!< 0x00080000 */ +#define EXINT_INTEN_INTEN19 EXINT_INTEN_INTEN19_Msk /*!< Interrupt enable or disable on line 19 */ +#define EXINT_INTEN_INTEN20_Pos (20U) +#define EXINT_INTEN_INTEN20_Msk (0x1U << EXINT_INTEN_INTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_INTEN_INTEN20 EXINT_INTEN_INTEN20_Msk /*!< Interrupt enable or disable on line 20 */ +#define EXINT_INTEN_INTEN21_Pos (21U) +#define EXINT_INTEN_INTEN21_Msk (0x1U << EXINT_INTEN_INTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_INTEN_INTEN21 EXINT_INTEN_INTEN21_Msk /*!< Interrupt enable or disable on line 21 */ +#define EXINT_INTEN_INTEN22_Pos (22U) +#define EXINT_INTEN_INTEN22_Msk (0x1U << EXINT_INTEN_INTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_INTEN_INTEN22 EXINT_INTEN_INTEN22_Msk /*!< Interrupt enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_INTEN_INT0 EXINT_INTEN_INTEN0 +#define EXINT_INTEN_INT1 EXINT_INTEN_INTEN1 +#define EXINT_INTEN_INT2 EXINT_INTEN_INTEN2 +#define EXINT_INTEN_INT3 EXINT_INTEN_INTEN3 +#define EXINT_INTEN_INT4 EXINT_INTEN_INTEN4 +#define EXINT_INTEN_INT5 EXINT_INTEN_INTEN5 +#define EXINT_INTEN_INT6 EXINT_INTEN_INTEN6 +#define EXINT_INTEN_INT7 EXINT_INTEN_INTEN7 +#define EXINT_INTEN_INT8 EXINT_INTEN_INTEN8 +#define EXINT_INTEN_INT9 EXINT_INTEN_INTEN9 +#define EXINT_INTEN_INT10 EXINT_INTEN_INTEN10 +#define EXINT_INTEN_INT11 EXINT_INTEN_INTEN11 +#define EXINT_INTEN_INT12 EXINT_INTEN_INTEN12 +#define EXINT_INTEN_INT13 EXINT_INTEN_INTEN13 +#define EXINT_INTEN_INT14 EXINT_INTEN_INTEN14 +#define EXINT_INTEN_INT15 EXINT_INTEN_INTEN15 +#define EXINT_INTEN_INT16 EXINT_INTEN_INTEN16 +#define EXINT_INTEN_INT17 EXINT_INTEN_INTEN17 +#define EXINT_INTEN_INT18 EXINT_INTEN_INTEN18 +#define EXINT_INTEN_INT19 EXINT_INTEN_INTEN19 +#define EXINT_INTEN_INT20 EXINT_INTEN_INTEN20 +#define EXINT_INTEN_INT21 EXINT_INTEN_INTEN21 +#define EXINT_INTEN_INT22 EXINT_INTEN_INTEN22 +#define EXINT_INTEN_INT 0x007FFFFFU /*!< Interrupt enable or disable all */ + +/***************** Bit definition for EXINT_EVTEN register ******************/ +#define EXINT_EVTEN_EVTEN0_Pos (0U) +#define EXINT_EVTEN_EVTEN0_Msk (0x1U << EXINT_EVTEN_EVTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_EVTEN_EVTEN0 EXINT_EVTEN_EVTEN0_Msk /*!< Event enable or disable on line 0 */ +#define EXINT_EVTEN_EVTEN1_Pos (1U) +#define EXINT_EVTEN_EVTEN1_Msk (0x1U << EXINT_EVTEN_EVTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_EVTEN_EVTEN1 EXINT_EVTEN_EVTEN1_Msk /*!< Event enable or disable on line 1 */ +#define EXINT_EVTEN_EVTEN2_Pos (2U) +#define EXINT_EVTEN_EVTEN2_Msk (0x1U << EXINT_EVTEN_EVTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_EVTEN_EVTEN2 EXINT_EVTEN_EVTEN2_Msk /*!< Event enable or disable on line 2 */ +#define EXINT_EVTEN_EVTEN3_Pos (3U) +#define EXINT_EVTEN_EVTEN3_Msk (0x1U << EXINT_EVTEN_EVTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_EVTEN_EVTEN3 EXINT_EVTEN_EVTEN3_Msk /*!< Event enable or disable on line 3 */ +#define EXINT_EVTEN_EVTEN4_Pos (4U) +#define EXINT_EVTEN_EVTEN4_Msk (0x1U << EXINT_EVTEN_EVTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_EVTEN_EVTEN4 EXINT_EVTEN_EVTEN4_Msk /*!< Event enable or disable on line 4 */ +#define EXINT_EVTEN_EVTEN5_Pos (5U) +#define EXINT_EVTEN_EVTEN5_Msk (0x1U << EXINT_EVTEN_EVTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_EVTEN_EVTEN5 EXINT_EVTEN_EVTEN5_Msk /*!< Event enable or disable on line 5 */ +#define EXINT_EVTEN_EVTEN6_Pos (6U) +#define EXINT_EVTEN_EVTEN6_Msk (0x1U << EXINT_EVTEN_EVTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_EVTEN_EVTEN6 EXINT_EVTEN_EVTEN6_Msk /*!< Event enable or disable on line 6 */ +#define EXINT_EVTEN_EVTEN7_Pos (7U) +#define EXINT_EVTEN_EVTEN7_Msk (0x1U << EXINT_EVTEN_EVTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_EVTEN_EVTEN7 EXINT_EVTEN_EVTEN7_Msk /*!< Event enable or disable on line 7 */ +#define EXINT_EVTEN_EVTEN8_Pos (8U) +#define EXINT_EVTEN_EVTEN8_Msk (0x1U << EXINT_EVTEN_EVTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_EVTEN_EVTEN8 EXINT_EVTEN_EVTEN8_Msk /*!< Event enable or disable on line 8 */ +#define EXINT_EVTEN_EVTEN9_Pos (9U) +#define EXINT_EVTEN_EVTEN9_Msk (0x1U << EXINT_EVTEN_EVTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_EVTEN_EVTEN9 EXINT_EVTEN_EVTEN9_Msk /*!< Event enable or disable on line 9 */ +#define EXINT_EVTEN_EVTEN10_Pos (10U) +#define EXINT_EVTEN_EVTEN10_Msk (0x1U << EXINT_EVTEN_EVTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_EVTEN_EVTEN10 EXINT_EVTEN_EVTEN10_Msk /*!< Event enable or disable on line 10 */ +#define EXINT_EVTEN_EVTEN11_Pos (11U) +#define EXINT_EVTEN_EVTEN11_Msk (0x1U << EXINT_EVTEN_EVTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_EVTEN_EVTEN11 EXINT_EVTEN_EVTEN11_Msk /*!< Event enable or disable on line 11 */ +#define EXINT_EVTEN_EVTEN12_Pos (12U) +#define EXINT_EVTEN_EVTEN12_Msk (0x1U << EXINT_EVTEN_EVTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_EVTEN_EVTEN12 EXINT_EVTEN_EVTEN12_Msk /*!< Event enable or disable on line 12 */ +#define EXINT_EVTEN_EVTEN13_Pos (13U) +#define EXINT_EVTEN_EVTEN13_Msk (0x1U << EXINT_EVTEN_EVTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_EVTEN_EVTEN13 EXINT_EVTEN_EVTEN13_Msk /*!< Event enable or disable on line 13 */ +#define EXINT_EVTEN_EVTEN14_Pos (14U) +#define EXINT_EVTEN_EVTEN14_Msk (0x1U << EXINT_EVTEN_EVTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_EVTEN_EVTEN14 EXINT_EVTEN_EVTEN14_Msk /*!< Event enable or disable on line 14 */ +#define EXINT_EVTEN_EVTEN15_Pos (15U) +#define EXINT_EVTEN_EVTEN15_Msk (0x1U << EXINT_EVTEN_EVTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_EVTEN_EVTEN15 EXINT_EVTEN_EVTEN15_Msk /*!< Event enable or disable on line 15 */ +#define EXINT_EVTEN_EVTEN16_Pos (16U) +#define EXINT_EVTEN_EVTEN16_Msk (0x1U << EXINT_EVTEN_EVTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_EVTEN_EVTEN16 EXINT_EVTEN_EVTEN16_Msk /*!< Event enable or disable on line 16 */ +#define EXINT_EVTEN_EVTEN17_Pos (17U) +#define EXINT_EVTEN_EVTEN17_Msk (0x1U << EXINT_EVTEN_EVTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_EVTEN_EVTEN17 EXINT_EVTEN_EVTEN17_Msk /*!< Event enable or disable on line 17 */ +#define EXINT_EVTEN_EVTEN18_Pos (18U) +#define EXINT_EVTEN_EVTEN18_Msk (0x1U << EXINT_EVTEN_EVTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_EVTEN_EVTEN18 EXINT_EVTEN_EVTEN18_Msk /*!< Event enable or disable on line 18 */ +#define EXINT_EVTEN_EVTEN19_Pos (19U) +#define EXINT_EVTEN_EVTEN19_Msk (0x1U << EXINT_EVTEN_EVTEN19_Pos) /*!< 0x00080000 */ +#define EXINT_EVTEN_EVTEN19 EXINT_EVTEN_EVTEN19_Msk /*!< Event enable or disable on line 19 */ +#define EXINT_EVTEN_EVTEN20_Pos (20U) +#define EXINT_EVTEN_EVTEN20_Msk (0x1U << EXINT_EVTEN_EVTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_EVTEN_EVTEN20 EXINT_EVTEN_EVTEN20_Msk /*!< Event enable or disable on line 20 */ +#define EXINT_EVTEN_EVTEN21_Pos (21U) +#define EXINT_EVTEN_EVTEN21_Msk (0x1U << EXINT_EVTEN_EVTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_EVTEN_EVTEN21 EXINT_EVTEN_EVTEN21_Msk /*!< Event enable or disable on line 21 */ +#define EXINT_EVTEN_EVTEN22_Pos (22U) +#define EXINT_EVTEN_EVTEN22_Msk (0x1U << EXINT_EVTEN_EVTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_EVTEN_EVTEN22 EXINT_EVTEN_EVTEN22_Msk /*!< Event enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_EVTEN_EVT0 EXINT_EVTEN_EVTEN0 +#define EXINT_EVTEN_EVT1 EXINT_EVTEN_EVTEN1 +#define EXINT_EVTEN_EVT2 EXINT_EVTEN_EVTEN2 +#define EXINT_EVTEN_EVT3 EXINT_EVTEN_EVTEN3 +#define EXINT_EVTEN_EVT4 EXINT_EVTEN_EVTEN4 +#define EXINT_EVTEN_EVT5 EXINT_EVTEN_EVTEN5 +#define EXINT_EVTEN_EVT6 EXINT_EVTEN_EVTEN6 +#define EXINT_EVTEN_EVT7 EXINT_EVTEN_EVTEN7 +#define EXINT_EVTEN_EVT8 EXINT_EVTEN_EVTEN8 +#define EXINT_EVTEN_EVT9 EXINT_EVTEN_EVTEN9 +#define EXINT_EVTEN_EVT10 EXINT_EVTEN_EVTEN10 +#define EXINT_EVTEN_EVT11 EXINT_EVTEN_EVTEN11 +#define EXINT_EVTEN_EVT12 EXINT_EVTEN_EVTEN12 +#define EXINT_EVTEN_EVT13 EXINT_EVTEN_EVTEN13 +#define EXINT_EVTEN_EVT14 EXINT_EVTEN_EVTEN14 +#define EXINT_EVTEN_EVT15 EXINT_EVTEN_EVTEN15 +#define EXINT_EVTEN_EVT16 EXINT_EVTEN_EVTEN16 +#define EXINT_EVTEN_EVT17 EXINT_EVTEN_EVTEN17 +#define EXINT_EVTEN_EVT18 EXINT_EVTEN_EVTEN18 +#define EXINT_EVTEN_EVT19 EXINT_EVTEN_EVTEN19 +#define EXINT_EVTEN_EVT20 EXINT_EVTEN_EVTEN20 +#define EXINT_EVTEN_EVT21 EXINT_EVTEN_EVTEN21 +#define EXINT_EVTEN_EVT22 EXINT_EVTEN_EVTEN22 + +/**************** Bit definition for EXINT_POLCFG1 register *****************/ +#define EXINT_POLCFG1_RP0_Pos (0U) +#define EXINT_POLCFG1_RP0_Msk (0x1U << EXINT_POLCFG1_RP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG1_RP0 EXINT_POLCFG1_RP0_Msk /*!< Rising edge event configuration bit on line 0 */ +#define EXINT_POLCFG1_RP1_Pos (1U) +#define EXINT_POLCFG1_RP1_Msk (0x1U << EXINT_POLCFG1_RP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG1_RP1 EXINT_POLCFG1_RP1_Msk /*!< Rising edge event configuration bit on line 1 */ +#define EXINT_POLCFG1_RP2_Pos (2U) +#define EXINT_POLCFG1_RP2_Msk (0x1U << EXINT_POLCFG1_RP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG1_RP2 EXINT_POLCFG1_RP2_Msk /*!< Rising edge event configuration bit on line 2 */ +#define EXINT_POLCFG1_RP3_Pos (3U) +#define EXINT_POLCFG1_RP3_Msk (0x1U << EXINT_POLCFG1_RP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG1_RP3 EXINT_POLCFG1_RP3_Msk /*!< Rising edge event configuration bit on line 3 */ +#define EXINT_POLCFG1_RP4_Pos (4U) +#define EXINT_POLCFG1_RP4_Msk (0x1U << EXINT_POLCFG1_RP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG1_RP4 EXINT_POLCFG1_RP4_Msk /*!< Rising edge event configuration bit on line 4 */ +#define EXINT_POLCFG1_RP5_Pos (5U) +#define EXINT_POLCFG1_RP5_Msk (0x1U << EXINT_POLCFG1_RP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG1_RP5 EXINT_POLCFG1_RP5_Msk /*!< Rising edge event configuration bit on line 5 */ +#define EXINT_POLCFG1_RP6_Pos (6U) +#define EXINT_POLCFG1_RP6_Msk (0x1U << EXINT_POLCFG1_RP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG1_RP6 EXINT_POLCFG1_RP6_Msk /*!< Rising edge event configuration bit on line 6 */ +#define EXINT_POLCFG1_RP7_Pos (7U) +#define EXINT_POLCFG1_RP7_Msk (0x1U << EXINT_POLCFG1_RP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG1_RP7 EXINT_POLCFG1_RP7_Msk /*!< Rising edge event configuration bit on line 7 */ +#define EXINT_POLCFG1_RP8_Pos (8U) +#define EXINT_POLCFG1_RP8_Msk (0x1U << EXINT_POLCFG1_RP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG1_RP8 EXINT_POLCFG1_RP8_Msk /*!< Rising edge event configuration bit on line 8 */ +#define EXINT_POLCFG1_RP9_Pos (9U) +#define EXINT_POLCFG1_RP9_Msk (0x1U << EXINT_POLCFG1_RP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG1_RP9 EXINT_POLCFG1_RP9_Msk /*!< Rising edge event configuration bit on line 9 */ +#define EXINT_POLCFG1_RP10_Pos (10U) +#define EXINT_POLCFG1_RP10_Msk (0x1U << EXINT_POLCFG1_RP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG1_RP10 EXINT_POLCFG1_RP10_Msk /*!< Rising edge event configuration bit on line 10 */ +#define EXINT_POLCFG1_RP11_Pos (11U) +#define EXINT_POLCFG1_RP11_Msk (0x1U << EXINT_POLCFG1_RP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG1_RP11 EXINT_POLCFG1_RP11_Msk /*!< Rising edge event configuration bit on line 11 */ +#define EXINT_POLCFG1_RP12_Pos (12U) +#define EXINT_POLCFG1_RP12_Msk (0x1U << EXINT_POLCFG1_RP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG1_RP12 EXINT_POLCFG1_RP12_Msk /*!< Rising edge event configuration bit on line 12 */ +#define EXINT_POLCFG1_RP13_Pos (13U) +#define EXINT_POLCFG1_RP13_Msk (0x1U << EXINT_POLCFG1_RP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG1_RP13 EXINT_POLCFG1_RP13_Msk /*!< Rising edge event configuration bit on line 13 */ +#define EXINT_POLCFG1_RP14_Pos (14U) +#define EXINT_POLCFG1_RP14_Msk (0x1U << EXINT_POLCFG1_RP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG1_RP14 EXINT_POLCFG1_RP14_Msk /*!< Rising edge event configuration bit on line 14 */ +#define EXINT_POLCFG1_RP15_Pos (15U) +#define EXINT_POLCFG1_RP15_Msk (0x1U << EXINT_POLCFG1_RP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG1_RP15 EXINT_POLCFG1_RP15_Msk /*!< Rising edge event configuration bit on line 15 */ +#define EXINT_POLCFG1_RP16_Pos (16U) +#define EXINT_POLCFG1_RP16_Msk (0x1U << EXINT_POLCFG1_RP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG1_RP16 EXINT_POLCFG1_RP16_Msk /*!< Rising edge event configuration bit on line 16 */ +#define EXINT_POLCFG1_RP17_Pos (17U) +#define EXINT_POLCFG1_RP17_Msk (0x1U << EXINT_POLCFG1_RP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG1_RP17 EXINT_POLCFG1_RP17_Msk /*!< Rising edge event configuration bit on line 17 */ +#define EXINT_POLCFG1_RP18_Pos (18U) +#define EXINT_POLCFG1_RP18_Msk (0x1U << EXINT_POLCFG1_RP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG1_RP18 EXINT_POLCFG1_RP18_Msk /*!< Rising edge event configuration bit on line 18 */ +#define EXINT_POLCFG1_RP19_Pos (19U) +#define EXINT_POLCFG1_RP19_Msk (0x1U << EXINT_POLCFG1_RP19_Pos) /*!< 0x00080000 */ +#define EXINT_POLCFG1_RP19 EXINT_POLCFG1_RP19_Msk /*!< Rising edge event configuration bit on line 19 */ +#define EXINT_POLCFG1_RP20_Pos (20U) +#define EXINT_POLCFG1_RP20_Msk (0x1U << EXINT_POLCFG1_RP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG1_RP20 EXINT_POLCFG1_RP20_Msk /*!< Rising edge event configuration bit on line 20 */ +#define EXINT_POLCFG1_RP21_Pos (21U) +#define EXINT_POLCFG1_RP21_Msk (0x1U << EXINT_POLCFG1_RP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG1_RP21 EXINT_POLCFG1_RP21_Msk /*!< Rising edge event configuration bit on line 21 */ +#define EXINT_POLCFG1_RP22_Pos (22U) +#define EXINT_POLCFG1_RP22_Msk (0x1U << EXINT_POLCFG1_RP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG1_RP22 EXINT_POLCFG1_RP22_Msk /*!< Rising edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG1_POL0 EXINT_POLCFG1_RP0 +#define EXINT_POLCFG1_POL1 EXINT_POLCFG1_RP1 +#define EXINT_POLCFG1_POL2 EXINT_POLCFG1_RP2 +#define EXINT_POLCFG1_POL3 EXINT_POLCFG1_RP3 +#define EXINT_POLCFG1_POL4 EXINT_POLCFG1_RP4 +#define EXINT_POLCFG1_POL5 EXINT_POLCFG1_RP5 +#define EXINT_POLCFG1_POL6 EXINT_POLCFG1_RP6 +#define EXINT_POLCFG1_POL7 EXINT_POLCFG1_RP7 +#define EXINT_POLCFG1_POL8 EXINT_POLCFG1_RP8 +#define EXINT_POLCFG1_POL9 EXINT_POLCFG1_RP9 +#define EXINT_POLCFG1_POL10 EXINT_POLCFG1_RP10 +#define EXINT_POLCFG1_POL11 EXINT_POLCFG1_RP11 +#define EXINT_POLCFG1_POL12 EXINT_POLCFG1_RP12 +#define EXINT_POLCFG1_POL13 EXINT_POLCFG1_RP13 +#define EXINT_POLCFG1_POL14 EXINT_POLCFG1_RP14 +#define EXINT_POLCFG1_POL15 EXINT_POLCFG1_RP15 +#define EXINT_POLCFG1_POL16 EXINT_POLCFG1_RP16 +#define EXINT_POLCFG1_POL17 EXINT_POLCFG1_RP17 +#define EXINT_POLCFG1_POL18 EXINT_POLCFG1_RP18 +#define EXINT_POLCFG1_POL19 EXINT_POLCFG1_RP19 +#define EXINT_POLCFG1_POL20 EXINT_POLCFG1_RP20 +#define EXINT_POLCFG1_POL21 EXINT_POLCFG1_RP21 +#define EXINT_POLCFG1_POL22 EXINT_POLCFG1_RP22 + +/**************** Bit definition for EXINT_POLCFG2 register *****************/ +#define EXINT_POLCFG2_FP0_Pos (0U) +#define EXINT_POLCFG2_FP0_Msk (0x1U << EXINT_POLCFG2_FP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG2_FP0 EXINT_POLCFG2_FP0_Msk /*!< Falling edge event configuration bit on line 0 */ +#define EXINT_POLCFG2_FP1_Pos (1U) +#define EXINT_POLCFG2_FP1_Msk (0x1U << EXINT_POLCFG2_FP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG2_FP1 EXINT_POLCFG2_FP1_Msk /*!< Falling edge event configuration bit on line 1 */ +#define EXINT_POLCFG2_FP2_Pos (2U) +#define EXINT_POLCFG2_FP2_Msk (0x1U << EXINT_POLCFG2_FP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG2_FP2 EXINT_POLCFG2_FP2_Msk /*!< Falling edge event configuration bit on line 2 */ +#define EXINT_POLCFG2_FP3_Pos (3U) +#define EXINT_POLCFG2_FP3_Msk (0x1U << EXINT_POLCFG2_FP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG2_FP3 EXINT_POLCFG2_FP3_Msk /*!< Falling edge event configuration bit on line 3 */ +#define EXINT_POLCFG2_FP4_Pos (4U) +#define EXINT_POLCFG2_FP4_Msk (0x1U << EXINT_POLCFG2_FP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG2_FP4 EXINT_POLCFG2_FP4_Msk /*!< Falling edge event configuration bit on line 4 */ +#define EXINT_POLCFG2_FP5_Pos (5U) +#define EXINT_POLCFG2_FP5_Msk (0x1U << EXINT_POLCFG2_FP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG2_FP5 EXINT_POLCFG2_FP5_Msk /*!< Falling edge event configuration bit on line 5 */ +#define EXINT_POLCFG2_FP6_Pos (6U) +#define EXINT_POLCFG2_FP6_Msk (0x1U << EXINT_POLCFG2_FP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG2_FP6 EXINT_POLCFG2_FP6_Msk /*!< Falling edge event configuration bit on line 6 */ +#define EXINT_POLCFG2_FP7_Pos (7U) +#define EXINT_POLCFG2_FP7_Msk (0x1U << EXINT_POLCFG2_FP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG2_FP7 EXINT_POLCFG2_FP7_Msk /*!< Falling edge event configuration bit on line 7 */ +#define EXINT_POLCFG2_FP8_Pos (8U) +#define EXINT_POLCFG2_FP8_Msk (0x1U << EXINT_POLCFG2_FP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG2_FP8 EXINT_POLCFG2_FP8_Msk /*!< Falling edge event configuration bit on line 8 */ +#define EXINT_POLCFG2_FP9_Pos (9U) +#define EXINT_POLCFG2_FP9_Msk (0x1U << EXINT_POLCFG2_FP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG2_FP9 EXINT_POLCFG2_FP9_Msk /*!< Falling edge event configuration bit on line 9 */ +#define EXINT_POLCFG2_FP10_Pos (10U) +#define EXINT_POLCFG2_FP10_Msk (0x1U << EXINT_POLCFG2_FP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG2_FP10 EXINT_POLCFG2_FP10_Msk /*!< Falling edge event configuration bit on line 10 */ +#define EXINT_POLCFG2_FP11_Pos (11U) +#define EXINT_POLCFG2_FP11_Msk (0x1U << EXINT_POLCFG2_FP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG2_FP11 EXINT_POLCFG2_FP11_Msk /*!< Falling edge event configuration bit on line 11 */ +#define EXINT_POLCFG2_FP12_Pos (12U) +#define EXINT_POLCFG2_FP12_Msk (0x1U << EXINT_POLCFG2_FP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG2_FP12 EXINT_POLCFG2_FP12_Msk /*!< Falling edge event configuration bit on line 12 */ +#define EXINT_POLCFG2_FP13_Pos (13U) +#define EXINT_POLCFG2_FP13_Msk (0x1U << EXINT_POLCFG2_FP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG2_FP13 EXINT_POLCFG2_FP13_Msk /*!< Falling edge event configuration bit on line 13 */ +#define EXINT_POLCFG2_FP14_Pos (14U) +#define EXINT_POLCFG2_FP14_Msk (0x1U << EXINT_POLCFG2_FP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG2_FP14 EXINT_POLCFG2_FP14_Msk /*!< Falling edge event configuration bit on line 14 */ +#define EXINT_POLCFG2_FP15_Pos (15U) +#define EXINT_POLCFG2_FP15_Msk (0x1U << EXINT_POLCFG2_FP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG2_FP15 EXINT_POLCFG2_FP15_Msk /*!< Falling edge event configuration bit on line 15 */ +#define EXINT_POLCFG2_FP16_Pos (16U) +#define EXINT_POLCFG2_FP16_Msk (0x1U << EXINT_POLCFG2_FP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG2_FP16 EXINT_POLCFG2_FP16_Msk /*!< Falling edge event configuration bit on line 16 */ +#define EXINT_POLCFG2_FP17_Pos (17U) +#define EXINT_POLCFG2_FP17_Msk (0x1U << EXINT_POLCFG2_FP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG2_FP17 EXINT_POLCFG2_FP17_Msk /*!< Falling edge event configuration bit on line 17 */ +#define EXINT_POLCFG2_FP18_Pos (18U) +#define EXINT_POLCFG2_FP18_Msk (0x1U << EXINT_POLCFG2_FP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG2_FP18 EXINT_POLCFG2_FP18_Msk /*!< Falling edge event configuration bit on line 18 */ +#define EXINT_POLCFG2_FP19_Pos (19U) +#define EXINT_POLCFG2_FP19_Msk (0x1U << EXINT_POLCFG2_FP19_Pos) /*!< 0x00080000 */ +#define EXINT_POLCFG2_FP19 EXINT_POLCFG2_FP19_Msk /*!< Falling edge event configuration bit on line 19 */ +#define EXINT_POLCFG2_FP20_Pos (20U) +#define EXINT_POLCFG2_FP20_Msk (0x1U << EXINT_POLCFG2_FP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG2_FP20 EXINT_POLCFG2_FP20_Msk /*!< Falling edge event configuration bit on line 20 */ +#define EXINT_POLCFG2_FP21_Pos (21U) +#define EXINT_POLCFG2_FP21_Msk (0x1U << EXINT_POLCFG2_FP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG2_FP21 EXINT_POLCFG2_FP21_Msk /*!< Falling edge event configuration bit on line 21 */ +#define EXINT_POLCFG2_FP22_Pos (22U) +#define EXINT_POLCFG2_FP22_Msk (0x1U << EXINT_POLCFG2_FP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG2_FP22 EXINT_POLCFG2_FP22_Msk /*!< Falling edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG2_POL0 EXINT_POLCFG2_FP0 +#define EXINT_POLCFG2_POL1 EXINT_POLCFG2_FP1 +#define EXINT_POLCFG2_POL2 EXINT_POLCFG2_FP2 +#define EXINT_POLCFG2_POL3 EXINT_POLCFG2_FP3 +#define EXINT_POLCFG2_POL4 EXINT_POLCFG2_FP4 +#define EXINT_POLCFG2_POL5 EXINT_POLCFG2_FP5 +#define EXINT_POLCFG2_POL6 EXINT_POLCFG2_FP6 +#define EXINT_POLCFG2_POL7 EXINT_POLCFG2_FP7 +#define EXINT_POLCFG2_POL8 EXINT_POLCFG2_FP8 +#define EXINT_POLCFG2_POL9 EXINT_POLCFG2_FP9 +#define EXINT_POLCFG2_POL10 EXINT_POLCFG2_FP10 +#define EXINT_POLCFG2_POL11 EXINT_POLCFG2_FP11 +#define EXINT_POLCFG2_POL12 EXINT_POLCFG2_FP12 +#define EXINT_POLCFG2_POL13 EXINT_POLCFG2_FP13 +#define EXINT_POLCFG2_POL14 EXINT_POLCFG2_FP14 +#define EXINT_POLCFG2_POL15 EXINT_POLCFG2_FP15 +#define EXINT_POLCFG2_POL16 EXINT_POLCFG2_FP16 +#define EXINT_POLCFG2_POL17 EXINT_POLCFG2_FP17 +#define EXINT_POLCFG2_POL18 EXINT_POLCFG2_FP18 +#define EXINT_POLCFG2_POL19 EXINT_POLCFG2_FP19 +#define EXINT_POLCFG2_POL20 EXINT_POLCFG2_FP20 +#define EXINT_POLCFG2_POL21 EXINT_POLCFG2_FP21 +#define EXINT_POLCFG2_POL22 EXINT_POLCFG2_FP22 + +/***************** Bit definition for EXINT_SWTRG register ******************/ +#define EXINT_SWTRG_SWT0_Pos (0U) +#define EXINT_SWTRG_SWT0_Msk (0x1U << EXINT_SWTRG_SWT0_Pos) /*!< 0x00000001 */ +#define EXINT_SWTRG_SWT0 EXINT_SWTRG_SWT0_Msk /*!< Software trigger on line 0 */ +#define EXINT_SWTRG_SWT1_Pos (1U) +#define EXINT_SWTRG_SWT1_Msk (0x1U << EXINT_SWTRG_SWT1_Pos) /*!< 0x00000002 */ +#define EXINT_SWTRG_SWT1 EXINT_SWTRG_SWT1_Msk /*!< Software trigger on line 1 */ +#define EXINT_SWTRG_SWT2_Pos (2U) +#define EXINT_SWTRG_SWT2_Msk (0x1U << EXINT_SWTRG_SWT2_Pos) /*!< 0x00000004 */ +#define EXINT_SWTRG_SWT2 EXINT_SWTRG_SWT2_Msk /*!< Software trigger on line 2 */ +#define EXINT_SWTRG_SWT3_Pos (3U) +#define EXINT_SWTRG_SWT3_Msk (0x1U << EXINT_SWTRG_SWT3_Pos) /*!< 0x00000008 */ +#define EXINT_SWTRG_SWT3 EXINT_SWTRG_SWT3_Msk /*!< Software trigger on line 3 */ +#define EXINT_SWTRG_SWT4_Pos (4U) +#define EXINT_SWTRG_SWT4_Msk (0x1U << EXINT_SWTRG_SWT4_Pos) /*!< 0x00000010 */ +#define EXINT_SWTRG_SWT4 EXINT_SWTRG_SWT4_Msk /*!< Software trigger on line 4 */ +#define EXINT_SWTRG_SWT5_Pos (5U) +#define EXINT_SWTRG_SWT5_Msk (0x1U << EXINT_SWTRG_SWT5_Pos) /*!< 0x00000020 */ +#define EXINT_SWTRG_SWT5 EXINT_SWTRG_SWT5_Msk /*!< Software trigger on line 5 */ +#define EXINT_SWTRG_SWT6_Pos (6U) +#define EXINT_SWTRG_SWT6_Msk (0x1U << EXINT_SWTRG_SWT6_Pos) /*!< 0x00000040 */ +#define EXINT_SWTRG_SWT6 EXINT_SWTRG_SWT6_Msk /*!< Software trigger on line 6 */ +#define EXINT_SWTRG_SWT7_Pos (7U) +#define EXINT_SWTRG_SWT7_Msk (0x1U << EXINT_SWTRG_SWT7_Pos) /*!< 0x00000080 */ +#define EXINT_SWTRG_SWT7 EXINT_SWTRG_SWT7_Msk /*!< Software trigger on line 7 */ +#define EXINT_SWTRG_SWT8_Pos (8U) +#define EXINT_SWTRG_SWT8_Msk (0x1U << EXINT_SWTRG_SWT8_Pos) /*!< 0x00000100 */ +#define EXINT_SWTRG_SWT8 EXINT_SWTRG_SWT8_Msk /*!< Software trigger on line 8 */ +#define EXINT_SWTRG_SWT9_Pos (9U) +#define EXINT_SWTRG_SWT9_Msk (0x1U << EXINT_SWTRG_SWT9_Pos) /*!< 0x00000200 */ +#define EXINT_SWTRG_SWT9 EXINT_SWTRG_SWT9_Msk /*!< Software trigger on line 9 */ +#define EXINT_SWTRG_SWT10_Pos (10U) +#define EXINT_SWTRG_SWT10_Msk (0x1U << EXINT_SWTRG_SWT10_Pos) /*!< 0x00000400 */ +#define EXINT_SWTRG_SWT10 EXINT_SWTRG_SWT10_Msk /*!< Software trigger on line 10 */ +#define EXINT_SWTRG_SWT11_Pos (11U) +#define EXINT_SWTRG_SWT11_Msk (0x1U << EXINT_SWTRG_SWT11_Pos) /*!< 0x00000800 */ +#define EXINT_SWTRG_SWT11 EXINT_SWTRG_SWT11_Msk /*!< Software trigger on line 11 */ +#define EXINT_SWTRG_SWT12_Pos (12U) +#define EXINT_SWTRG_SWT12_Msk (0x1U << EXINT_SWTRG_SWT12_Pos) /*!< 0x00001000 */ +#define EXINT_SWTRG_SWT12 EXINT_SWTRG_SWT12_Msk /*!< Software trigger on line 12 */ +#define EXINT_SWTRG_SWT13_Pos (13U) +#define EXINT_SWTRG_SWT13_Msk (0x1U << EXINT_SWTRG_SWT13_Pos) /*!< 0x00002000 */ +#define EXINT_SWTRG_SWT13 EXINT_SWTRG_SWT13_Msk /*!< Software trigger on line 13 */ +#define EXINT_SWTRG_SWT14_Pos (14U) +#define EXINT_SWTRG_SWT14_Msk (0x1U << EXINT_SWTRG_SWT14_Pos) /*!< 0x00004000 */ +#define EXINT_SWTRG_SWT14 EXINT_SWTRG_SWT14_Msk /*!< Software trigger on line 14 */ +#define EXINT_SWTRG_SWT15_Pos (15U) +#define EXINT_SWTRG_SWT15_Msk (0x1U << EXINT_SWTRG_SWT15_Pos) /*!< 0x00008000 */ +#define EXINT_SWTRG_SWT15 EXINT_SWTRG_SWT15_Msk /*!< Software trigger on line 15 */ +#define EXINT_SWTRG_SWT16_Pos (16U) +#define EXINT_SWTRG_SWT16_Msk (0x1U << EXINT_SWTRG_SWT16_Pos) /*!< 0x00010000 */ +#define EXINT_SWTRG_SWT16 EXINT_SWTRG_SWT16_Msk /*!< Software trigger on line 16 */ +#define EXINT_SWTRG_SWT17_Pos (17U) +#define EXINT_SWTRG_SWT17_Msk (0x1U << EXINT_SWTRG_SWT17_Pos) /*!< 0x00020000 */ +#define EXINT_SWTRG_SWT17 EXINT_SWTRG_SWT17_Msk /*!< Software trigger on line 17 */ +#define EXINT_SWTRG_SWT18_Pos (18U) +#define EXINT_SWTRG_SWT18_Msk (0x1U << EXINT_SWTRG_SWT18_Pos) /*!< 0x00040000 */ +#define EXINT_SWTRG_SWT18 EXINT_SWTRG_SWT18_Msk /*!< Software trigger on line 18 */ +#define EXINT_SWTRG_SWT19_Pos (19U) +#define EXINT_SWTRG_SWT19_Msk (0x1U << EXINT_SWTRG_SWT19_Pos) /*!< 0x00080000 */ +#define EXINT_SWTRG_SWT19 EXINT_SWTRG_SWT19_Msk /*!< Software trigger on line 19 */ +#define EXINT_SWTRG_SWT20_Pos (20U) +#define EXINT_SWTRG_SWT20_Msk (0x1U << EXINT_SWTRG_SWT20_Pos) /*!< 0x00100000 */ +#define EXINT_SWTRG_SWT20 EXINT_SWTRG_SWT20_Msk /*!< Software trigger on line 20 */ +#define EXINT_SWTRG_SWT21_Pos (21U) +#define EXINT_SWTRG_SWT21_Msk (0x1U << EXINT_SWTRG_SWT21_Pos) /*!< 0x00200000 */ +#define EXINT_SWTRG_SWT21 EXINT_SWTRG_SWT21_Msk /*!< Software trigger on line 21 */ +#define EXINT_SWTRG_SWT22_Pos (22U) +#define EXINT_SWTRG_SWT22_Msk (0x1U << EXINT_SWTRG_SWT22_Pos) /*!< 0x00400000 */ +#define EXINT_SWTRG_SWT22 EXINT_SWTRG_SWT22_Msk /*!< Software trigger on line 22 */ + +/* References Defines */ +#define EXINT_SWTRG_SW0 EXINT_SWTRG_SWT0 +#define EXINT_SWTRG_SW1 EXINT_SWTRG_SWT1 +#define EXINT_SWTRG_SW2 EXINT_SWTRG_SWT2 +#define EXINT_SWTRG_SW3 EXINT_SWTRG_SWT3 +#define EXINT_SWTRG_SW4 EXINT_SWTRG_SWT4 +#define EXINT_SWTRG_SW5 EXINT_SWTRG_SWT5 +#define EXINT_SWTRG_SW6 EXINT_SWTRG_SWT6 +#define EXINT_SWTRG_SW7 EXINT_SWTRG_SWT7 +#define EXINT_SWTRG_SW8 EXINT_SWTRG_SWT8 +#define EXINT_SWTRG_SW9 EXINT_SWTRG_SWT9 +#define EXINT_SWTRG_SW10 EXINT_SWTRG_SWT10 +#define EXINT_SWTRG_SW11 EXINT_SWTRG_SWT11 +#define EXINT_SWTRG_SW12 EXINT_SWTRG_SWT12 +#define EXINT_SWTRG_SW13 EXINT_SWTRG_SWT13 +#define EXINT_SWTRG_SW14 EXINT_SWTRG_SWT14 +#define EXINT_SWTRG_SW15 EXINT_SWTRG_SWT15 +#define EXINT_SWTRG_SW16 EXINT_SWTRG_SWT16 +#define EXINT_SWTRG_SW17 EXINT_SWTRG_SWT17 +#define EXINT_SWTRG_SW18 EXINT_SWTRG_SWT18 +#define EXINT_SWTRG_SW19 EXINT_SWTRG_SWT19 +#define EXINT_SWTRG_SW20 EXINT_SWTRG_SWT20 +#define EXINT_SWTRG_SW21 EXINT_SWTRG_SWT21 +#define EXINT_SWTRG_SW22 EXINT_SWTRG_SWT22 + +/***************** Bit definition for EXINT_INTSTS register *****************/ +#define EXINT_INTSTS_LINE0_Pos (0U) +#define EXINT_INTSTS_LINE0_Msk (0x1U << EXINT_INTSTS_LINE0_Pos) /*!< 0x00000001 */ +#define EXINT_INTSTS_LINE0 EXINT_INTSTS_LINE0_Msk /*!< Status bit for line 0 */ +#define EXINT_INTSTS_LINE1_Pos (1U) +#define EXINT_INTSTS_LINE1_Msk (0x1U << EXINT_INTSTS_LINE1_Pos) /*!< 0x00000002 */ +#define EXINT_INTSTS_LINE1 EXINT_INTSTS_LINE1_Msk /*!< Status bit for line 1 */ +#define EXINT_INTSTS_LINE2_Pos (2U) +#define EXINT_INTSTS_LINE2_Msk (0x1U << EXINT_INTSTS_LINE2_Pos) /*!< 0x00000004 */ +#define EXINT_INTSTS_LINE2 EXINT_INTSTS_LINE2_Msk /*!< Status bit for line 2 */ +#define EXINT_INTSTS_LINE3_Pos (3U) +#define EXINT_INTSTS_LINE3_Msk (0x1U << EXINT_INTSTS_LINE3_Pos) /*!< 0x00000008 */ +#define EXINT_INTSTS_LINE3 EXINT_INTSTS_LINE3_Msk /*!< Status bit for line 3 */ +#define EXINT_INTSTS_LINE4_Pos (4U) +#define EXINT_INTSTS_LINE4_Msk (0x1U << EXINT_INTSTS_LINE4_Pos) /*!< 0x00000010 */ +#define EXINT_INTSTS_LINE4 EXINT_INTSTS_LINE4_Msk /*!< Status bit for line 4 */ +#define EXINT_INTSTS_LINE5_Pos (5U) +#define EXINT_INTSTS_LINE5_Msk (0x1U << EXINT_INTSTS_LINE5_Pos) /*!< 0x00000020 */ +#define EXINT_INTSTS_LINE5 EXINT_INTSTS_LINE5_Msk /*!< Status bit for line 5 */ +#define EXINT_INTSTS_LINE6_Pos (6U) +#define EXINT_INTSTS_LINE6_Msk (0x1U << EXINT_INTSTS_LINE6_Pos) /*!< 0x00000040 */ +#define EXINT_INTSTS_LINE6 EXINT_INTSTS_LINE6_Msk /*!< Status bit for line 6 */ +#define EXINT_INTSTS_LINE7_Pos (7U) +#define EXINT_INTSTS_LINE7_Msk (0x1U << EXINT_INTSTS_LINE7_Pos) /*!< 0x00000080 */ +#define EXINT_INTSTS_LINE7 EXINT_INTSTS_LINE7_Msk /*!< Status bit for line 7 */ +#define EXINT_INTSTS_LINE8_Pos (8U) +#define EXINT_INTSTS_LINE8_Msk (0x1U << EXINT_INTSTS_LINE8_Pos) /*!< 0x00000100 */ +#define EXINT_INTSTS_LINE8 EXINT_INTSTS_LINE8_Msk /*!< Status bit for line 8 */ +#define EXINT_INTSTS_LINE9_Pos (9U) +#define EXINT_INTSTS_LINE9_Msk (0x1U << EXINT_INTSTS_LINE9_Pos) /*!< 0x00000200 */ +#define EXINT_INTSTS_LINE9 EXINT_INTSTS_LINE9_Msk /*!< Status bit for line 9 */ +#define EXINT_INTSTS_LINE10_Pos (10U) +#define EXINT_INTSTS_LINE10_Msk (0x1U << EXINT_INTSTS_LINE10_Pos) /*!< 0x00000400 */ +#define EXINT_INTSTS_LINE10 EXINT_INTSTS_LINE10_Msk /*!< Status bit for line 10 */ +#define EXINT_INTSTS_LINE11_Pos (11U) +#define EXINT_INTSTS_LINE11_Msk (0x1U << EXINT_INTSTS_LINE11_Pos) /*!< 0x00000800 */ +#define EXINT_INTSTS_LINE11 EXINT_INTSTS_LINE11_Msk /*!< Status bit for line 11 */ +#define EXINT_INTSTS_LINE12_Pos (12U) +#define EXINT_INTSTS_LINE12_Msk (0x1U << EXINT_INTSTS_LINE12_Pos) /*!< 0x00001000 */ +#define EXINT_INTSTS_LINE12 EXINT_INTSTS_LINE12_Msk /*!< Status bit for line 12 */ +#define EXINT_INTSTS_LINE13_Pos (13U) +#define EXINT_INTSTS_LINE13_Msk (0x1U << EXINT_INTSTS_LINE13_Pos) /*!< 0x00002000 */ +#define EXINT_INTSTS_LINE13 EXINT_INTSTS_LINE13_Msk /*!< Status bit for line 13 */ +#define EXINT_INTSTS_LINE14_Pos (14U) +#define EXINT_INTSTS_LINE14_Msk (0x1U << EXINT_INTSTS_LINE14_Pos) /*!< 0x00004000 */ +#define EXINT_INTSTS_LINE14 EXINT_INTSTS_LINE14_Msk /*!< Status bit for line 14 */ +#define EXINT_INTSTS_LINE15_Pos (15U) +#define EXINT_INTSTS_LINE15_Msk (0x1U << EXINT_INTSTS_LINE15_Pos) /*!< 0x00008000 */ +#define EXINT_INTSTS_LINE15 EXINT_INTSTS_LINE15_Msk /*!< Status bit for line 15 */ +#define EXINT_INTSTS_LINE16_Pos (16U) +#define EXINT_INTSTS_LINE16_Msk (0x1U << EXINT_INTSTS_LINE16_Pos) /*!< 0x00010000 */ +#define EXINT_INTSTS_LINE16 EXINT_INTSTS_LINE16_Msk /*!< Status bit for line 16 */ +#define EXINT_INTSTS_LINE17_Pos (17U) +#define EXINT_INTSTS_LINE17_Msk (0x1U << EXINT_INTSTS_LINE17_Pos) /*!< 0x00020000 */ +#define EXINT_INTSTS_LINE17 EXINT_INTSTS_LINE17_Msk /*!< Status bit for line 17 */ +#define EXINT_INTSTS_LINE18_Pos (18U) +#define EXINT_INTSTS_LINE18_Msk (0x1U << EXINT_INTSTS_LINE18_Pos) /*!< 0x00040000 */ +#define EXINT_INTSTS_LINE18 EXINT_INTSTS_LINE18_Msk /*!< Status bit for line 18 */ +#define EXINT_INTSTS_LINE19_Pos (19U) +#define EXINT_INTSTS_LINE19_Msk (0x1U << EXINT_INTSTS_LINE19_Pos) /*!< 0x00080000 */ +#define EXINT_INTSTS_LINE19 EXINT_INTSTS_LINE19_Msk /*!< Status bit for line 19 */ +#define EXINT_INTSTS_LINE20_Pos (20U) +#define EXINT_INTSTS_LINE20_Msk (0x1U << EXINT_INTSTS_LINE20_Pos) /*!< 0x00100000 */ +#define EXINT_INTSTS_LINE20 EXINT_INTSTS_LINE20_Msk /*!< Status bit for line 20 */ +#define EXINT_INTSTS_LINE21_Pos (21U) +#define EXINT_INTSTS_LINE21_Msk (0x1U << EXINT_INTSTS_LINE21_Pos) /*!< 0x00200000 */ +#define EXINT_INTSTS_LINE21 EXINT_INTSTS_LINE21_Msk /*!< Status bit for line 21 */ +#define EXINT_INTSTS_LINE22_Pos (22U) +#define EXINT_INTSTS_LINE22_Msk (0x1U << EXINT_INTSTS_LINE22_Pos) /*!< 0x00400000 */ +#define EXINT_INTSTS_LINE22 EXINT_INTSTS_LINE22_Msk /*!< Status bit for line 22 */ + +/* References Defines */ +#define EXINT_INTSTS_INT0 EXINT_INTSTS_LINE0 +#define EXINT_INTSTS_INT1 EXINT_INTSTS_LINE1 +#define EXINT_INTSTS_INT2 EXINT_INTSTS_LINE2 +#define EXINT_INTSTS_INT3 EXINT_INTSTS_LINE3 +#define EXINT_INTSTS_INT4 EXINT_INTSTS_LINE4 +#define EXINT_INTSTS_INT5 EXINT_INTSTS_LINE5 +#define EXINT_INTSTS_INT6 EXINT_INTSTS_LINE6 +#define EXINT_INTSTS_INT7 EXINT_INTSTS_LINE7 +#define EXINT_INTSTS_INT8 EXINT_INTSTS_LINE8 +#define EXINT_INTSTS_INT9 EXINT_INTSTS_LINE9 +#define EXINT_INTSTS_INT10 EXINT_INTSTS_LINE10 +#define EXINT_INTSTS_INT11 EXINT_INTSTS_LINE11 +#define EXINT_INTSTS_INT12 EXINT_INTSTS_LINE12 +#define EXINT_INTSTS_INT13 EXINT_INTSTS_LINE13 +#define EXINT_INTSTS_INT14 EXINT_INTSTS_LINE14 +#define EXINT_INTSTS_INT15 EXINT_INTSTS_LINE15 +#define EXINT_INTSTS_INT16 EXINT_INTSTS_LINE16 +#define EXINT_INTSTS_INT17 EXINT_INTSTS_LINE17 +#define EXINT_INTSTS_INT18 EXINT_INTSTS_LINE18 +#define EXINT_INTSTS_INT19 EXINT_INTSTS_LINE19 +#define EXINT_INTSTS_INT20 EXINT_INTSTS_LINE20 +#define EXINT_INTSTS_INT21 EXINT_INTSTS_LINE21 +#define EXINT_INTSTS_INT22 EXINT_INTSTS_LINE22 + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_STS register ********************/ +#define DMA_STS_GF1_Pos (0U) +#define DMA_STS_GF1_Msk (0x1U << DMA_STS_GF1_Pos) /*!< 0x00000001 */ +#define DMA_STS_GF1 DMA_STS_GF1_Msk /*!< Channel 1 global event flag */ +#define DMA_STS_FDTF1_Pos (1U) +#define DMA_STS_FDTF1_Msk (0x1U << DMA_STS_FDTF1_Pos) /*!< 0x00000002 */ +#define DMA_STS_FDTF1 DMA_STS_FDTF1_Msk /*!< Channel 1 transfer complete event flag */ +#define DMA_STS_HDTF1_Pos (2U) +#define DMA_STS_HDTF1_Msk (0x1U << DMA_STS_HDTF1_Pos) /*!< 0x00000004 */ +#define DMA_STS_HDTF1 DMA_STS_HDTF1_Msk /*!< Channel 1 half transfer event flag */ +#define DMA_STS_DTERRF1_Pos (3U) +#define DMA_STS_DTERRF1_Msk (0x1U << DMA_STS_DTERRF1_Pos) /*!< 0x00000008 */ +#define DMA_STS_DTERRF1 DMA_STS_DTERRF1_Msk /*!< Channel 1 transfer error event flag */ +#define DMA_STS_GF2_Pos (4U) +#define DMA_STS_GF2_Msk (0x1U << DMA_STS_GF2_Pos) /*!< 0x00000010 */ +#define DMA_STS_GF2 DMA_STS_GF2_Msk /*!< Channel 2 global event flag */ +#define DMA_STS_FDTF2_Pos (5U) +#define DMA_STS_FDTF2_Msk (0x1U << DMA_STS_FDTF2_Pos) /*!< 0x00000020 */ +#define DMA_STS_FDTF2 DMA_STS_FDTF2_Msk /*!< Channel 2 transfer complete event flag */ +#define DMA_STS_HDTF2_Pos (6U) +#define DMA_STS_HDTF2_Msk (0x1U << DMA_STS_HDTF2_Pos) /*!< 0x00000040 */ +#define DMA_STS_HDTF2 DMA_STS_HDTF2_Msk /*!< Channel 2 half transfer event flag */ +#define DMA_STS_DTERRF2_Pos (7U) +#define DMA_STS_DTERRF2_Msk (0x1U << DMA_STS_DTERRF2_Pos) /*!< 0x00000080 */ +#define DMA_STS_DTERRF2 DMA_STS_DTERRF2_Msk /*!< Channel 2 transfer error event flag */ +#define DMA_STS_GF3_Pos (8U) +#define DMA_STS_GF3_Msk (0x1U << DMA_STS_GF3_Pos) /*!< 0x00000100 */ +#define DMA_STS_GF3 DMA_STS_GF3_Msk /*!< Channel 3 global event flag */ +#define DMA_STS_FDTF3_Pos (9U) +#define DMA_STS_FDTF3_Msk (0x1U << DMA_STS_FDTF3_Pos) /*!< 0x00000200 */ +#define DMA_STS_FDTF3 DMA_STS_FDTF3_Msk /*!< Channel 3 transfer complete event flag */ +#define DMA_STS_HDTF3_Pos (10U) +#define DMA_STS_HDTF3_Msk (0x1U << DMA_STS_HDTF3_Pos) /*!< 0x00000400 */ +#define DMA_STS_HDTF3 DMA_STS_HDTF3_Msk /*!< Channel 3 half transfer event flag */ +#define DMA_STS_DTERRF3_Pos (11U) +#define DMA_STS_DTERRF3_Msk (0x1U << DMA_STS_DTERRF3_Pos) /*!< 0x00000800 */ +#define DMA_STS_DTERRF3 DMA_STS_DTERRF3_Msk /*!< Channel 3 transfer error event flag */ +#define DMA_STS_GF4_Pos (12U) +#define DMA_STS_GF4_Msk (0x1U << DMA_STS_GF4_Pos) /*!< 0x00001000 */ +#define DMA_STS_GF4 DMA_STS_GF4_Msk /*!< Channel 4 global event flag */ +#define DMA_STS_FDTF4_Pos (13U) +#define DMA_STS_FDTF4_Msk (0x1U << DMA_STS_FDTF4_Pos) /*!< 0x00002000 */ +#define DMA_STS_FDTF4 DMA_STS_FDTF4_Msk /*!< Channel 4 transfer complete event flag */ +#define DMA_STS_HDTF4_Pos (14U) +#define DMA_STS_HDTF4_Msk (0x1U << DMA_STS_HDTF4_Pos) /*!< 0x00004000 */ +#define DMA_STS_HDTF4 DMA_STS_HDTF4_Msk /*!< Channel 4 half transfer event flag */ +#define DMA_STS_DTERRF4_Pos (15U) +#define DMA_STS_DTERRF4_Msk (0x1U << DMA_STS_DTERRF4_Pos) /*!< 0x00008000 */ +#define DMA_STS_DTERRF4 DMA_STS_DTERRF4_Msk /*!< Channel 4 transfer error event flag */ +#define DMA_STS_GF5_Pos (16U) +#define DMA_STS_GF5_Msk (0x1U << DMA_STS_GF5_Pos) /*!< 0x00010000 */ +#define DMA_STS_GF5 DMA_STS_GF5_Msk /*!< Channel 5 global event flag */ +#define DMA_STS_FDTF5_Pos (17U) +#define DMA_STS_FDTF5_Msk (0x1U << DMA_STS_FDTF5_Pos) /*!< 0x00020000 */ +#define DMA_STS_FDTF5 DMA_STS_FDTF5_Msk /*!< Channel 5 transfer complete event flag */ +#define DMA_STS_HDTF5_Pos (18U) +#define DMA_STS_HDTF5_Msk (0x1U << DMA_STS_HDTF5_Pos) /*!< 0x00040000 */ +#define DMA_STS_HDTF5 DMA_STS_HDTF5_Msk /*!< Channel 5 half transfer event flag */ +#define DMA_STS_DTERRF5_Pos (19U) +#define DMA_STS_DTERRF5_Msk (0x1U << DMA_STS_DTERRF5_Pos) /*!< 0x00080000 */ +#define DMA_STS_DTERRF5 DMA_STS_DTERRF5_Msk /*!< Channel 5 transfer error event flag */ +#define DMA_STS_GF6_Pos (20U) +#define DMA_STS_GF6_Msk (0x1U << DMA_STS_GF6_Pos) /*!< 0x00100000 */ +#define DMA_STS_GF6 DMA_STS_GF6_Msk /*!< Channel 6 global event flag */ +#define DMA_STS_FDTF6_Pos (21U) +#define DMA_STS_FDTF6_Msk (0x1U << DMA_STS_FDTF6_Pos) /*!< 0x00200000 */ +#define DMA_STS_FDTF6 DMA_STS_FDTF6_Msk /*!< Channel 6 transfer complete event flag */ +#define DMA_STS_HDTF6_Pos (22U) +#define DMA_STS_HDTF6_Msk (0x1U << DMA_STS_HDTF6_Pos) /*!< 0x00400000 */ +#define DMA_STS_HDTF6 DMA_STS_HDTF6_Msk /*!< Channel 6 half transfer event flag */ +#define DMA_STS_DTERRF6_Pos (23U) +#define DMA_STS_DTERRF6_Msk (0x1U << DMA_STS_DTERRF6_Pos) /*!< 0x00800000 */ +#define DMA_STS_DTERRF6 DMA_STS_DTERRF6_Msk /*!< Channel 6 transfer error event flag */ +#define DMA_STS_GF7_Pos (24U) +#define DMA_STS_GF7_Msk (0x1U << DMA_STS_GF7_Pos) /*!< 0x01000000 */ +#define DMA_STS_GF7 DMA_STS_GF7_Msk /*!< Channel 7 global event flag */ +#define DMA_STS_FDTF7_Pos (25U) +#define DMA_STS_FDTF7_Msk (0x1U << DMA_STS_FDTF7_Pos) /*!< 0x02000000 */ +#define DMA_STS_FDTF7 DMA_STS_FDTF7_Msk /*!< Channel 7 transfer complete event flag */ +#define DMA_STS_HDTF7_Pos (26U) +#define DMA_STS_HDTF7_Msk (0x1U << DMA_STS_HDTF7_Pos) /*!< 0x04000000 */ +#define DMA_STS_HDTF7 DMA_STS_HDTF7_Msk /*!< Channel 7 half transfer event flag */ +#define DMA_STS_DTERRF7_Pos (27U) +#define DMA_STS_DTERRF7_Msk (0x1U << DMA_STS_DTERRF7_Pos) /*!< 0x08000000 */ +#define DMA_STS_DTERRF7 DMA_STS_DTERRF7_Msk /*!< Channel 7 transfer error event flag */ + +/******************* Bit definition for DMA_CLR register ********************/ +#define DMA_CLR_GFC1_Pos (0U) +#define DMA_CLR_GFC1_Msk (0x1U << DMA_CLR_GFC1_Pos) /*!< 0x00000001 */ +#define DMA_CLR_GFC1 DMA_CLR_GFC1_Msk /*!< Channel 1 global interrupt flag clear */ +#define DMA_CLR_FDTFC1_Pos (1U) +#define DMA_CLR_FDTFC1_Msk (0x1U << DMA_CLR_FDTFC1_Pos) /*!< 0x00000002 */ +#define DMA_CLR_FDTFC1 DMA_CLR_FDTFC1_Msk /*!< Channel 1 transfer complete flag clear */ +#define DMA_CLR_HDTFC1_Pos (2U) +#define DMA_CLR_HDTFC1_Msk (0x1U << DMA_CLR_HDTFC1_Pos) /*!< 0x00000004 */ +#define DMA_CLR_HDTFC1 DMA_CLR_HDTFC1_Msk /*!< Channel 1 half transfer flag clear */ +#define DMA_CLR_DTERRFC1_Pos (3U) +#define DMA_CLR_DTERRFC1_Msk (0x1U << DMA_CLR_DTERRFC1_Pos) /*!< 0x00000008 */ +#define DMA_CLR_DTERRFC1 DMA_CLR_DTERRFC1_Msk /*!< Channel 1 data transfer error flag clear */ +#define DMA_CLR_GFC2_Pos (4U) +#define DMA_CLR_GFC2_Msk (0x1U << DMA_CLR_GFC2_Pos) /*!< 0x00000010 */ +#define DMA_CLR_GFC2 DMA_CLR_GFC2_Msk /*!< Channel 2 global interrupt flag clear */ +#define DMA_CLR_FDTFC2_Pos (5U) +#define DMA_CLR_FDTFC2_Msk (0x1U << DMA_CLR_FDTFC2_Pos) /*!< 0x00000020 */ +#define DMA_CLR_FDTFC2 DMA_CLR_FDTFC2_Msk /*!< Channel 2 transfer complete flag clear */ +#define DMA_CLR_HDTFC2_Pos (6U) +#define DMA_CLR_HDTFC2_Msk (0x1U << DMA_CLR_HDTFC2_Pos) /*!< 0x00000040 */ +#define DMA_CLR_HDTFC2 DMA_CLR_HDTFC2_Msk /*!< Channel 2 half transfer flag clear */ +#define DMA_CLR_DTERRFC2_Pos (7U) +#define DMA_CLR_DTERRFC2_Msk (0x1U << DMA_CLR_DTERRFC2_Pos) /*!< 0x00000080 */ +#define DMA_CLR_DTERRFC2 DMA_CLR_DTERRFC2_Msk /*!< Channel 2 data transfer error flag clear */ +#define DMA_CLR_GFC3_Pos (8U) +#define DMA_CLR_GFC3_Msk (0x1U << DMA_CLR_GFC3_Pos) /*!< 0x00000100 */ +#define DMA_CLR_GFC3 DMA_CLR_GFC3_Msk /*!< Channel 3 global interrupt flag clear */ +#define DMA_CLR_FDTFC3_Pos (9U) +#define DMA_CLR_FDTFC3_Msk (0x1U << DMA_CLR_FDTFC3_Pos) /*!< 0x00000200 */ +#define DMA_CLR_FDTFC3 DMA_CLR_FDTFC3_Msk /*!< Channel 3 transfer complete flag clear */ +#define DMA_CLR_HDTFC3_Pos (10U) +#define DMA_CLR_HDTFC3_Msk (0x1U << DMA_CLR_HDTFC3_Pos) /*!< 0x00000400 */ +#define DMA_CLR_HDTFC3 DMA_CLR_HDTFC3_Msk /*!< Channel 3 half transfer flag clear */ +#define DMA_CLR_DTERRFC3_Pos (11U) +#define DMA_CLR_DTERRFC3_Msk (0x1U << DMA_CLR_DTERRFC3_Pos) /*!< 0x00000800 */ +#define DMA_CLR_DTERRFC3 DMA_CLR_DTERRFC3_Msk /*!< Channel 3 data transfer error flag clear */ +#define DMA_CLR_GFC4_Pos (12U) +#define DMA_CLR_GFC4_Msk (0x1U << DMA_CLR_GFC4_Pos) /*!< 0x00001000 */ +#define DMA_CLR_GFC4 DMA_CLR_GFC4_Msk /*!< Channel 4 global interrupt flag clear */ +#define DMA_CLR_FDTFC4_Pos (13U) +#define DMA_CLR_FDTFC4_Msk (0x1U << DMA_CLR_FDTFC4_Pos) /*!< 0x00002000 */ +#define DMA_CLR_FDTFC4 DMA_CLR_FDTFC4_Msk /*!< Channel 4 transfer complete flag clear */ +#define DMA_CLR_HDTFC4_Pos (14U) +#define DMA_CLR_HDTFC4_Msk (0x1U << DMA_CLR_HDTFC4_Pos) /*!< 0x00004000 */ +#define DMA_CLR_HDTFC4 DMA_CLR_HDTFC4_Msk /*!< Channel 4 half transfer flag clear */ +#define DMA_CLR_DTERRFC4_Pos (15U) +#define DMA_CLR_DTERRFC4_Msk (0x1U << DMA_CLR_DTERRFC4_Pos) /*!< 0x00008000 */ +#define DMA_CLR_DTERRFC4 DMA_CLR_DTERRFC4_Msk /*!< Channel 4 data transfer error flag clear */ +#define DMA_CLR_GFC5_Pos (16U) +#define DMA_CLR_GFC5_Msk (0x1U << DMA_CLR_GFC5_Pos) /*!< 0x00010000 */ +#define DMA_CLR_GFC5 DMA_CLR_GFC5_Msk /*!< Channel 5 global interrupt flag clear */ +#define DMA_CLR_FDTFC5_Pos (17U) +#define DMA_CLR_FDTFC5_Msk (0x1U << DMA_CLR_FDTFC5_Pos) /*!< 0x00020000 */ +#define DMA_CLR_FDTFC5 DMA_CLR_FDTFC5_Msk /*!< Channel 5 transfer complete flag clear */ +#define DMA_CLR_HDTFC5_Pos (18U) +#define DMA_CLR_HDTFC5_Msk (0x1U << DMA_CLR_HDTFC5_Pos) /*!< 0x00040000 */ +#define DMA_CLR_HDTFC5 DMA_CLR_HDTFC5_Msk /*!< Channel 5 half transfer flag clear */ +#define DMA_CLR_DTERRFC5_Pos (19U) +#define DMA_CLR_DTERRFC5_Msk (0x1U << DMA_CLR_DTERRFC5_Pos) /*!< 0x00080000 */ +#define DMA_CLR_DTERRFC5 DMA_CLR_DTERRFC5_Msk /*!< Channel 5 data transfer error flag clear */ +#define DMA_CLR_GFC6_Pos (20U) +#define DMA_CLR_GFC6_Msk (0x1U << DMA_CLR_GFC6_Pos) /*!< 0x00100000 */ +#define DMA_CLR_GFC6 DMA_CLR_GFC6_Msk /*!< Channel 6 global interrupt flag clear */ +#define DMA_CLR_FDTFC6_Pos (21U) +#define DMA_CLR_FDTFC6_Msk (0x1U << DMA_CLR_FDTFC6_Pos) /*!< 0x00200000 */ +#define DMA_CLR_FDTFC6 DMA_CLR_FDTFC6_Msk /*!< Channel 6 transfer complete flag clear */ +#define DMA_CLR_HDTFC6_Pos (22U) +#define DMA_CLR_HDTFC6_Msk (0x1U << DMA_CLR_HDTFC6_Pos) /*!< 0x00400000 */ +#define DMA_CLR_HDTFC6 DMA_CLR_HDTFC6_Msk /*!< Channel 6 half transfer flag clear */ +#define DMA_CLR_DTERRFC6_Pos (23U) +#define DMA_CLR_DTERRFC6_Msk (0x1U << DMA_CLR_DTERRFC6_Pos) /*!< 0x00800000 */ +#define DMA_CLR_DTERRFC6 DMA_CLR_DTERRFC6_Msk /*!< Channel 6 data transfer error flag clear */ +#define DMA_CLR_GFC7_Pos (24U) +#define DMA_CLR_GFC7_Msk (0x1U << DMA_CLR_GFC7_Pos) /*!< 0x01000000 */ +#define DMA_CLR_GFC7 DMA_CLR_GFC7_Msk /*!< Channel 7 global interrupt flag clear */ +#define DMA_CLR_FDTFC7_Pos (25U) +#define DMA_CLR_FDTFC7_Msk (0x1U << DMA_CLR_FDTFC7_Pos) /*!< 0x02000000 */ +#define DMA_CLR_FDTFC7 DMA_CLR_FDTFC7_Msk /*!< Channel 7 transfer complete flag clear */ +#define DMA_CLR_HDTFC7_Pos (26U) +#define DMA_CLR_HDTFC7_Msk (0x1U << DMA_CLR_HDTFC7_Pos) /*!< 0x04000000 */ +#define DMA_CLR_HDTFC7 DMA_CLR_HDTFC7_Msk /*!< Channel 7 half transfer flag clear */ +#define DMA_CLR_DTERRFC7_Pos (27U) +#define DMA_CLR_DTERRFC7_Msk (0x1U << DMA_CLR_DTERRFC7_Pos) /*!< 0x08000000 */ +#define DMA_CLR_DTERRFC7 DMA_CLR_DTERRFC7_Msk /*!< Channel 7 data transfer error flag clear */ + +/****************** Bit definition for DMA_CCTRL register *******************/ +#define DMA_CCTRL_CHEN_Pos (0U) +#define DMA_CCTRL_CHEN_Msk (0x1U << DMA_CCTRL_CHEN_Pos) /*!< 0x00000001 */ +#define DMA_CCTRL_CHEN DMA_CCTRL_CHEN_Msk /*!< Channel enable */ +#define DMA_CCTRL_FDTIEN_Pos (1U) +#define DMA_CCTRL_FDTIEN_Msk (0x1U << DMA_CCTRL_FDTIEN_Pos) /*!< 0x00000002 */ +#define DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCTRL_HDTIEN_Pos (2U) +#define DMA_CCTRL_HDTIEN_Msk (0x1U << DMA_CCTRL_HDTIEN_Pos) /*!< 0x00000004 */ +#define DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN_Msk /*!< Half-transfer interrupt enable */ +#define DMA_CCTRL_DTERRIEN_Pos (3U) +#define DMA_CCTRL_DTERRIEN_Msk (0x1U << DMA_CCTRL_DTERRIEN_Pos) /*!< 0x00000008 */ +#define DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCTRL_DTD_Pos (4U) +#define DMA_CCTRL_DTD_Msk (0x1U << DMA_CCTRL_DTD_Pos) /*!< 0x00000010 */ +#define DMA_CCTRL_DTD DMA_CCTRL_DTD_Msk /*!< Data transfer direction */ +#define DMA_CCTRL_LM_Pos (5U) +#define DMA_CCTRL_LM_Msk (0x1U << DMA_CCTRL_LM_Pos) /*!< 0x00000020 */ +#define DMA_CCTRL_LM DMA_CCTRL_LM_Msk /*!< Circular mode */ +#define DMA_CCTRL_PINCM_Pos (6U) +#define DMA_CCTRL_PINCM_Msk (0x1U << DMA_CCTRL_PINCM_Pos) /*!< 0x00000040 */ +#define DMA_CCTRL_PINCM DMA_CCTRL_PINCM_Msk /*!< Peripheral address increment mode */ +#define DMA_CCTRL_MINCM_Pos (7U) +#define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ +#define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ + +#define DMA_CCTRL_PWIDTH_Pos (8U) +#define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ +#define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ +#define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ +#define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ + +#define DMA_CCTRL_MWIDTH_Pos (10U) +#define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ +#define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ +#define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ +#define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ + +#define DMA_CCTRL_CHPL_Pos (12U) +#define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ +#define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ +#define DMA_CCTRL_CHPL_0 (0x1U << DMA_CCTRL_CHPL_Pos) /*!< 0x00001000 */ +#define DMA_CCTRL_CHPL_1 (0x2U << DMA_CCTRL_CHPL_Pos) /*!< 0x00002000 */ + +#define DMA_CCTRL_M2M_Pos (14U) +#define DMA_CCTRL_M2M_Msk (0x1U << DMA_CCTRL_M2M_Pos) /*!< 0x00004000 */ +#define DMA_CCTRL_M2M DMA_CCTRL_M2M_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CDTCNT register ******************/ +#define DMA_CDTCNT_CNT_Pos (0U) +#define DMA_CDTCNT_CNT_Msk (0xFFFFU << DMA_CDTCNT_CNT_Pos) /*!< 0x0000FFFF */ +#define DMA_CDTCNT_CNT DMA_CDTCNT_CNT_Msk /*!< Number of data to transfer */ + +/****************** Bit definition for DMA_CPADDR register ******************/ +#define DMA_CPADDR_PADDR_Pos (0U) +#define DMA_CPADDR_PADDR_Msk (0xFFFFFFFFU << DMA_CPADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPADDR_PADDR DMA_CPADDR_PADDR_Msk /*!< Peripheral base address */ + +/****************** Bit definition for DMA_CMADDR register ******************/ +#define DMA_CMADDR_MADDR_Pos (0U) +#define DMA_CMADDR_MADDR_Msk (0xFFFFFFFFU << DMA_CMADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMADDR_MADDR DMA_CMADDR_MADDR_Msk /*!< Memory base address */ + +/***************** Bit definition for DMA_SRC_SEL0 register *****************/ +#define DMA_SRC_SEL0_CH1_SRC_Pos (0U) +#define DMA_SRC_SEL0_CH1_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH1_SRC_Pos) /*!< 0x000000FF */ +#define DMA_SRC_SEL0_CH1_SRC DMA_SRC_SEL0_CH1_SRC_Msk /*!< CH1 source select */ +#define DMA_SRC_SEL0_CH2_SRC_Pos (8U) +#define DMA_SRC_SEL0_CH2_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH2_SRC_Pos) /*!< 0x0000FF00 */ +#define DMA_SRC_SEL0_CH2_SRC DMA_SRC_SEL0_CH2_SRC_Msk /*!< CH2 source select */ +#define DMA_SRC_SEL0_CH3_SRC_Pos (16U) +#define DMA_SRC_SEL0_CH3_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH3_SRC_Pos) /*!< 0x00FF0000 */ +#define DMA_SRC_SEL0_CH3_SRC DMA_SRC_SEL0_CH3_SRC_Msk /*!< CH3 source select */ +#define DMA_SRC_SEL0_CH4_SRC_Pos (24U) +#define DMA_SRC_SEL0_CH4_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH4_SRC_Pos) /*!< 0xFF000000 */ +#define DMA_SRC_SEL0_CH4_SRC DMA_SRC_SEL0_CH4_SRC_Msk /*!< CH4 source select */ + +/***************** Bit definition for DMA_SRC_SEL1 register *****************/ +#define DMA_SRC_SEL1_CH5_SRC_Pos (0U) +#define DMA_SRC_SEL1_CH5_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH5_SRC_Pos) /*!< 0x000000FF */ +#define DMA_SRC_SEL1_CH5_SRC DMA_SRC_SEL1_CH5_SRC_Msk /*!< CH5 source select */ +#define DMA_SRC_SEL1_CH6_SRC_Pos (8U) +#define DMA_SRC_SEL1_CH6_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH6_SRC_Pos) /*!< 0x0000FF00 */ +#define DMA_SRC_SEL1_CH6_SRC DMA_SRC_SEL1_CH6_SRC_Msk /*!< CH6 source select */ +#define DMA_SRC_SEL1_CH7_SRC_Pos (16U) +#define DMA_SRC_SEL1_CH7_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH7_SRC_Pos) /*!< 0x00FF0000 */ +#define DMA_SRC_SEL1_CH7_SRC DMA_SRC_SEL1_CH7_SRC_Msk /*!< CH7 source select */ +#define DMA_SRC_SEL1_DMA_FLEX_EN_Pos (24U) +#define DMA_SRC_SEL1_DMA_FLEX_EN_Msk (0x1U << DMA_SRC_SEL1_DMA_FLEX_EN_Pos) /*!< 0x01000000 */ +#define DMA_SRC_SEL1_DMA_FLEX_EN DMA_SRC_SEL1_DMA_FLEX_EN_Msk /*!< DMA flexible request mapping enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for CRC_DT register ********************/ +#define CRC_DT_DT_Pos (0U) +#define CRC_DT_DT_Msk (0xFFFFFFFFU << CRC_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DT_DT CRC_DT_DT_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_CDT register ********************/ +#define CRC_CDT_CDT_Pos (0U) +#define CRC_CDT_CDT_Msk (0xFFU << CRC_CDT_CDT_Pos) /*!< 0x000000FF */ +#define CRC_CDT_CDT CRC_CDT_CDT_Msk /*!< General-purpose 8-bit data register bits */ + +/******************* Bit definition for CRC_CTRL register *******************/ +#define CRC_CTRL_RST_Pos (0U) +#define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ +#define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ + +/*!< REVID configuration */ +#define CRC_CTRL_REVID_Pos (5U) +#define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID CRC_CTRL_REVID_Msk /*!< REVID[1:0] bits (Reverse input data) */ +#define CRC_CTRL_REVID_0 (0x1U << CRC_CTRL_REVID_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_1 (0x2U << CRC_CTRL_REVID_Pos) /*!< 0x00000040 */ + +#define CRC_CTRL_REVID_NOREV 0x00000000U /*!< No effect */ +#define CRC_CTRL_REVID_BYTEREV_Pos (5U) +#define CRC_CTRL_REVID_BYTEREV_Msk (0x1U << CRC_CTRL_REVID_BYTEREV_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_BYTEREV CRC_CTRL_REVID_BYTEREV_Msk /*!< Byte reverse */ +#define CRC_CTRL_REVID_HALFREV_Pos (6U) +#define CRC_CTRL_REVID_HALFREV_Msk (0x1U << CRC_CTRL_REVID_HALFREV_Pos) /*!< 0x00000040 */ +#define CRC_CTRL_REVID_HALFREV CRC_CTRL_REVID_HALFREV_Msk /*!< Half-word reverse */ +#define CRC_CTRL_REVID_WORDREV_Pos (5U) +#define CRC_CTRL_REVID_WORDREV_Msk (0x3U << CRC_CTRL_REVID_WORDREV_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID_WORDREV CRC_CTRL_REVID_WORDREV_Msk /*!< Word reverse */ + +#define CRC_CTRL_REVOD_Pos (7U) +#define CRC_CTRL_REVOD_Msk (0x1U << CRC_CTRL_REVOD_Pos) /*!< 0x00000080 */ +#define CRC_CTRL_REVOD CRC_CTRL_REVOD_Msk /*!< Reverse output data */ + +/******************* Bit definition for CRC_IDT register ********************/ +#define CRC_IDT_IDT_Pos (0U) +#define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ + +/******************************************************************************/ +/* */ +/* Inter-integrated circuit interface (I2C) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2C_CTRL1 register *******************/ +#define I2C_CTRL1_I2CEN_Pos (0U) +#define I2C_CTRL1_I2CEN_Msk (0x1U << I2C_CTRL1_I2CEN_Pos) /*!< 0x00000001 */ +#define I2C_CTRL1_I2CEN I2C_CTRL1_I2CEN_Msk /*!< I2C peripheral enable */ +#define I2C_CTRL1_PERMODE_Pos (1U) +#define I2C_CTRL1_PERMODE_Msk (0x1U << I2C_CTRL1_PERMODE_Pos) /*!< 0x00000002 */ +#define I2C_CTRL1_PERMODE I2C_CTRL1_PERMODE_Msk /*!< I2C peripheral mode */ +#define I2C_CTRL1_SMBMODE_Pos (3U) +#define I2C_CTRL1_SMBMODE_Msk (0x1U << I2C_CTRL1_SMBMODE_Pos) /*!< 0x00000008 */ +#define I2C_CTRL1_SMBMODE I2C_CTRL1_SMBMODE_Msk /*!< SMBus device mode */ +#define I2C_CTRL1_ARPEN_Pos (4U) +#define I2C_CTRL1_ARPEN_Msk (0x1U << I2C_CTRL1_ARPEN_Pos) /*!< 0x00000010 */ +#define I2C_CTRL1_ARPEN I2C_CTRL1_ARPEN_Msk /*!< SMBus address resolution protocol enable */ +#define I2C_CTRL1_PECEN_Pos (5U) +#define I2C_CTRL1_PECEN_Msk (0x1U << I2C_CTRL1_PECEN_Pos) /*!< 0x00000020 */ +#define I2C_CTRL1_PECEN I2C_CTRL1_PECEN_Msk /*!< PEC calculation enable */ +#define I2C_CTRL1_GCAEN_Pos (6U) +#define I2C_CTRL1_GCAEN_Msk (0x1U << I2C_CTRL1_GCAEN_Pos) /*!< 0x00000040 */ +#define I2C_CTRL1_GCAEN I2C_CTRL1_GCAEN_Msk /*!< General call address enable */ +#define I2C_CTRL1_STRETCH_Pos (7U) +#define I2C_CTRL1_STRETCH_Msk (0x1U << I2C_CTRL1_STRETCH_Pos) /*!< 0x00000080 */ +#define I2C_CTRL1_STRETCH I2C_CTRL1_STRETCH_Msk /*!< Clock stretching mode */ +#define I2C_CTRL1_GENSTART_Pos (8U) +#define I2C_CTRL1_GENSTART_Msk (0x1U << I2C_CTRL1_GENSTART_Pos) /*!< 0x00000100 */ +#define I2C_CTRL1_GENSTART I2C_CTRL1_GENSTART_Msk /*!< Generate start condition */ +#define I2C_CTRL1_GENSTOP_Pos (9U) +#define I2C_CTRL1_GENSTOP_Msk (0x1U << I2C_CTRL1_GENSTOP_Pos) /*!< 0x00000200 */ +#define I2C_CTRL1_GENSTOP I2C_CTRL1_GENSTOP_Msk /*!< Generate stop condition */ +#define I2C_CTRL1_ACKEN_Pos (10U) +#define I2C_CTRL1_ACKEN_Msk (0x1U << I2C_CTRL1_ACKEN_Pos) /*!< 0x00000400 */ +#define I2C_CTRL1_ACKEN I2C_CTRL1_ACKEN_Msk /*!< Acknowledge enable */ +#define I2C_CTRL1_MACKCTRL_Pos (11U) +#define I2C_CTRL1_MACKCTRL_Msk (0x1U << I2C_CTRL1_MACKCTRL_Pos) /*!< 0x00000800 */ +#define I2C_CTRL1_MACKCTRL I2C_CTRL1_MACKCTRL_Msk /*!< Master receive mode acknowledge control */ +#define I2C_CTRL1_PECTEN_Pos (12U) +#define I2C_CTRL1_PECTEN_Msk (0x1U << I2C_CTRL1_PECTEN_Pos) /*!< 0x00001000 */ +#define I2C_CTRL1_PECTEN I2C_CTRL1_PECTEN_Msk /*!< Request PEC transfer enable */ +#define I2C_CTRL1_SMBALERT_Pos (13U) +#define I2C_CTRL1_SMBALERT_Msk (0x1U << I2C_CTRL1_SMBALERT_Pos) /*!< 0x00002000 */ +#define I2C_CTRL1_SMBALERT I2C_CTRL1_SMBALERT_Msk /*!< SMBus alert pin set */ +#define I2C_CTRL1_RESET_Pos (15U) +#define I2C_CTRL1_RESET_Msk (0x1U << I2C_CTRL1_RESET_Pos) /*!< 0x00008000 */ +#define I2C_CTRL1_RESET I2C_CTRL1_RESET_Msk /*!< I2C peripheral reset */ + +/****************** Bit definition for I2C_CTRL2 register *******************/ +/*!< CLKFREQ configuration */ +#define I2C_CTRL2_CLKFREQ_Pos (0U) +#define I2C_CTRL2_CLKFREQ_Msk (0xFFU << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x000000FF */ +#define I2C_CTRL2_CLKFREQ I2C_CTRL2_CLKFREQ_Msk /*!< CLKFREQ[7:0] bits (I2C input clock frequency) */ +#define I2C_CTRL2_CLKFREQ_0 (0x01U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000001 */ +#define I2C_CTRL2_CLKFREQ_1 (0x02U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000002 */ +#define I2C_CTRL2_CLKFREQ_2 (0x04U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000004 */ +#define I2C_CTRL2_CLKFREQ_3 (0x08U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000008 */ +#define I2C_CTRL2_CLKFREQ_4 (0x10U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000010 */ +#define I2C_CTRL2_CLKFREQ_5 (0x20U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000020 */ +#define I2C_CTRL2_CLKFREQ_6 (0x40U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000040 */ +#define I2C_CTRL2_CLKFREQ_7 (0x80U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000080 */ + +#define I2C_CTRL2_ERRIEN_Pos (8U) +#define I2C_CTRL2_ERRIEN_Msk (0x1U << I2C_CTRL2_ERRIEN_Pos) /*!< 0x00000100 */ +#define I2C_CTRL2_ERRIEN I2C_CTRL2_ERRIEN_Msk /*!< Error interrupt enable */ +#define I2C_CTRL2_EVTIEN_Pos (9U) +#define I2C_CTRL2_EVTIEN_Msk (0x1U << I2C_CTRL2_EVTIEN_Pos) /*!< 0x00000200 */ +#define I2C_CTRL2_EVTIEN I2C_CTRL2_EVTIEN_Msk /*!< Event interrupt enable */ +#define I2C_CTRL2_DATAIEN_Pos (10U) +#define I2C_CTRL2_DATAIEN_Msk (0x1U << I2C_CTRL2_DATAIEN_Pos) /*!< 0x00000400 */ +#define I2C_CTRL2_DATAIEN I2C_CTRL2_DATAIEN_Msk /*!< Data transfer interrupt enable */ +#define I2C_CTRL2_DMAEN_Pos (11U) +#define I2C_CTRL2_DMAEN_Msk (0x1U << I2C_CTRL2_DMAEN_Pos) /*!< 0x00000800 */ +#define I2C_CTRL2_DMAEN I2C_CTRL2_DMAEN_Msk /*!< DMA transfer enable */ +#define I2C_CTRL2_DMAEND_Pos (12U) +#define I2C_CTRL2_DMAEND_Msk (0x1U << I2C_CTRL2_DMAEND_Pos) /*!< 0x00001000 */ +#define I2C_CTRL2_DMAEND I2C_CTRL2_DMAEND_Msk /*!< End of DMA transfer */ + +/****************** Bit definition for I2C_OADDR1 register ******************/ +/*!< ADDR1 configuration */ +#define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ +#define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ +#define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ +#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ +#define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ +#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ +#define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ +#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ +#define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ +#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ +#define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ +#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ +#define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ +#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ +#define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ +#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ +#define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ +#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ +#define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ + +#define I2C_OADDR1_ADDR1MODE_Pos (15U) +#define I2C_OADDR1_ADDR1MODE_Msk (0x1U << I2C_OADDR1_ADDR1MODE_Pos) /*!< 0x00008000 */ +#define I2C_OADDR1_ADDR1MODE I2C_OADDR1_ADDR1MODE_Msk /*!< Address mode */ + +/****************** Bit definition for I2C_OADDR2 register ******************/ +#define I2C_OADDR2_ADDR2EN_Pos (0U) +#define I2C_OADDR2_ADDR2EN_Msk (0x1U << I2C_OADDR2_ADDR2EN_Pos) /*!< 0x00000001 */ +#define I2C_OADDR2_ADDR2EN I2C_OADDR2_ADDR2EN_Msk /*!< Own address 2 enable */ +#define I2C_OADDR2_ADDR2_Pos (1U) +#define I2C_OADDR2_ADDR2_Msk (0x7FU << I2C_OADDR2_ADDR2_Pos) /*!< 0x000000FE */ +#define I2C_OADDR2_ADDR2 I2C_OADDR2_ADDR2_Msk /*!< Own address 2 */ + +/******************** Bit definition for I2C_DT register ********************/ +#define I2C_DT_DT_Pos (0U) +#define I2C_DT_DT_Msk (0xFFU << I2C_DT_DT_Pos) /*!< 0x000000FF */ +#define I2C_DT_DT I2C_DT_DT_Msk /*!< This field is used to store data received or to be transferred */ + +/******************* Bit definition for I2C_STS1 register *******************/ +#define I2C_STS1_STARTF_Pos (0U) +#define I2C_STS1_STARTF_Msk (0x1U << I2C_STS1_STARTF_Pos) /*!< 0x00000001 */ +#define I2C_STS1_STARTF I2C_STS1_STARTF_Msk /*!< Start condition generation complete flag */ +#define I2C_STS1_ADDR7F_Pos (1U) +#define I2C_STS1_ADDR7F_Msk (0x1U << I2C_STS1_ADDR7F_Pos) /*!< 0x00000002 */ +#define I2C_STS1_ADDR7F I2C_STS1_ADDR7F_Msk /*!< 0 ~ 7 bit address match flag */ +#define I2C_STS1_TDC_Pos (2U) +#define I2C_STS1_TDC_Msk (0x1U << I2C_STS1_TDC_Pos) /*!< 0x00000004 */ +#define I2C_STS1_TDC I2C_STS1_TDC_Msk /*!< Data transfer complete flag */ +#define I2C_STS1_ADDRHF_Pos (3U) +#define I2C_STS1_ADDRHF_Msk (0x1U << I2C_STS1_ADDRHF_Pos) /*!< 0x00000008 */ +#define I2C_STS1_ADDRHF I2C_STS1_ADDRHF_Msk /*!< Master 9 ~ 8 bit address head match flag */ +#define I2C_STS1_STOPF_Pos (4U) +#define I2C_STS1_STOPF_Msk (0x1U << I2C_STS1_STOPF_Pos) /*!< 0x00000010 */ +#define I2C_STS1_STOPF I2C_STS1_STOPF_Msk /*!< Stop condition generation complete flag */ +#define I2C_STS1_RDBF_Pos (6U) +#define I2C_STS1_RDBF_Msk (0x1U << I2C_STS1_RDBF_Pos) /*!< 0x00000040 */ +#define I2C_STS1_RDBF I2C_STS1_RDBF_Msk /*!< Receive data buffer full flag */ +#define I2C_STS1_TDBE_Pos (7U) +#define I2C_STS1_TDBE_Msk (0x1U << I2C_STS1_TDBE_Pos) /*!< 0x00000080 */ +#define I2C_STS1_TDBE I2C_STS1_TDBE_Msk /*!< Transmit data buffer empty flag */ +#define I2C_STS1_BUSERR_Pos (8U) +#define I2C_STS1_BUSERR_Msk (0x1U << I2C_STS1_BUSERR_Pos) /*!< 0x00000100 */ +#define I2C_STS1_BUSERR I2C_STS1_BUSERR_Msk /*!< Bus error flag */ +#define I2C_STS1_ARLOST_Pos (9U) +#define I2C_STS1_ARLOST_Msk (0x1U << I2C_STS1_ARLOST_Pos) /*!< 0x00000200 */ +#define I2C_STS1_ARLOST I2C_STS1_ARLOST_Msk /*!< Arbitration lost flag */ +#define I2C_STS1_ACKFAIL_Pos (10U) +#define I2C_STS1_ACKFAIL_Msk (0x1U << I2C_STS1_ACKFAIL_Pos) /*!< 0x00000400 */ +#define I2C_STS1_ACKFAIL I2C_STS1_ACKFAIL_Msk /*!< Acknowledge failure flag */ +#define I2C_STS1_OUF_Pos (11U) +#define I2C_STS1_OUF_Msk (0x1U << I2C_STS1_OUF_Pos) /*!< 0x00000800 */ +#define I2C_STS1_OUF I2C_STS1_OUF_Msk /*!< Overload / underload flag */ +#define I2C_STS1_PECERR_Pos (12U) +#define I2C_STS1_PECERR_Msk (0x1U << I2C_STS1_PECERR_Pos) /*!< 0x00001000 */ +#define I2C_STS1_PECERR I2C_STS1_PECERR_Msk /*!< PEC receive error flag */ +#define I2C_STS1_TMOUT_Pos (14U) +#define I2C_STS1_TMOUT_Msk (0x1U << I2C_STS1_TMOUT_Pos) /*!< 0x00004000 */ +#define I2C_STS1_TMOUT I2C_STS1_TMOUT_Msk /*!< SMBus timeout flag */ +#define I2C_STS1_ALERTF_Pos (15U) +#define I2C_STS1_ALERTF_Msk (0x1U << I2C_STS1_ALERTF_Pos) /*!< 0x00008000 */ +#define I2C_STS1_ALERTF I2C_STS1_ALERTF_Msk /*!< SMBus alert flag */ + +/******************* Bit definition for I2C_STS2 register *******************/ +#define I2C_STS2_TRMODE_Pos (0U) +#define I2C_STS2_TRMODE_Msk (0x1U << I2C_STS2_TRMODE_Pos) /*!< 0x00000001 */ +#define I2C_STS2_TRMODE I2C_STS2_TRMODE_Msk /*!< Transmission mode */ +#define I2C_STS2_BUSYF_Pos (1U) +#define I2C_STS2_BUSYF_Msk (0x1U << I2C_STS2_BUSYF_Pos) /*!< 0x00000002 */ +#define I2C_STS2_BUSYF I2C_STS2_BUSYF_Msk /*!< Bus busy flag transmission mode */ +#define I2C_STS2_DIRF_Pos (2U) +#define I2C_STS2_DIRF_Msk (0x1U << I2C_STS2_DIRF_Pos) /*!< 0x00000004 */ +#define I2C_STS2_DIRF I2C_STS2_DIRF_Msk /*!< Transmission direction flag */ +#define I2C_STS2_GCADDRF_Pos (4U) +#define I2C_STS2_GCADDRF_Msk (0x1U << I2C_STS2_GCADDRF_Pos) /*!< 0x00000010 */ +#define I2C_STS2_GCADDRF I2C_STS2_GCADDRF_Msk /*!< General call address reception flag */ +#define I2C_STS2_DEVADDRF_Pos (5U) +#define I2C_STS2_DEVADDRF_Msk (0x1U << I2C_STS2_DEVADDRF_Pos) /*!< 0x00000020 */ +#define I2C_STS2_DEVADDRF I2C_STS2_DEVADDRF_Msk /*!< SMBus device address reception flag */ +#define I2C_STS2_HOSTADDRF_Pos (6U) +#define I2C_STS2_HOSTADDRF_Msk (0x1U << I2C_STS2_HOSTADDRF_Pos) /*!< 0x00000040 */ +#define I2C_STS2_HOSTADDRF I2C_STS2_HOSTADDRF_Msk /*!< SMBus host address reception flag */ +#define I2C_STS2_ADDR2F_Pos (7U) +#define I2C_STS2_ADDR2F_Msk (0x1U << I2C_STS2_ADDR2F_Pos) /*!< 0x00000080 */ +#define I2C_STS2_ADDR2F I2C_STS2_ADDR2F_Msk /*!< Received address 2 flag */ +#define I2C_STS2_PECVAL_Pos (8U) +#define I2C_STS2_PECVAL_Msk (0xFFU << I2C_STS2_PECVAL_Pos) /*!< 0x0000FF00 */ +#define I2C_STS2_PECVAL I2C_STS2_PECVAL_Msk /*!< PEC value */ + +/***************** Bit definition for I2C_CLKCTRL register ******************/ +#define I2C_CLKCTRL_SPEED_Pos (0U) +#define I2C_CLKCTRL_SPEED_Msk (0xFFFU << I2C_CLKCTRL_SPEED_Pos) /*!< 0x00000FFF */ +#define I2C_CLKCTRL_SPEED I2C_CLKCTRL_SPEED_Msk /*!< I2C bus speed config */ +#define I2C_CLKCTRL_DUTYMODE_Pos (14U) +#define I2C_CLKCTRL_DUTYMODE_Msk (0x1U << I2C_CLKCTRL_DUTYMODE_Pos) /*!< 0x00004000 */ +#define I2C_CLKCTRL_DUTYMODE I2C_CLKCTRL_DUTYMODE_Msk /*!< Fast mode duty cycle */ +#define I2C_CLKCTRL_SPEEDMODE_Pos (15U) +#define I2C_CLKCTRL_SPEEDMODE_Msk (0x1U << I2C_CLKCTRL_SPEEDMODE_Pos) /*!< 0x00008000 */ +#define I2C_CLKCTRL_SPEEDMODE I2C_CLKCTRL_SPEEDMODE_Msk /*!< Speed mode selection */ + +/****************** Bit definition for I2C_TMRISE register ******************/ +#define I2C_TMRISE_RISETIME_Pos (0U) +#define I2C_TMRISE_RISETIME_Msk (0x3FU << I2C_TMRISE_RISETIME_Pos) /*!< 0x0000003F */ +#define I2C_TMRISE_RISETIME I2C_TMRISE_RISETIME_Msk /*!< I2C bus rise time */ + +/******************************************************************************/ +/* */ +/* Universal synchronous/asynchronous receiver/transmitter (USART) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for USART_STS register *******************/ +#define USART_STS_PERR_Pos (0U) +#define USART_STS_PERR_Msk (0x1U << USART_STS_PERR_Pos) /*!< 0x00000001 */ +#define USART_STS_PERR USART_STS_PERR_Msk /*!< Parity error */ +#define USART_STS_FERR_Pos (1U) +#define USART_STS_FERR_Msk (0x1U << USART_STS_FERR_Pos) /*!< 0x00000002 */ +#define USART_STS_FERR USART_STS_FERR_Msk /*!< Framing error */ +#define USART_STS_NERR_Pos (2U) +#define USART_STS_NERR_Msk (0x1U << USART_STS_NERR_Pos) /*!< 0x00000004 */ +#define USART_STS_NERR USART_STS_NERR_Msk /*!< Noise error */ +#define USART_STS_ROERR_Pos (3U) +#define USART_STS_ROERR_Msk (0x1U << USART_STS_ROERR_Pos) /*!< 0x00000008 */ +#define USART_STS_ROERR USART_STS_ROERR_Msk /*!< Receiver overflow error */ +#define USART_STS_IDLEF_Pos (4U) +#define USART_STS_IDLEF_Msk (0x1U << USART_STS_IDLEF_Pos) /*!< 0x00000010 */ +#define USART_STS_IDLEF USART_STS_IDLEF_Msk /*!< Idle flag */ +#define USART_STS_RDBF_Pos (5U) +#define USART_STS_RDBF_Msk (0x1U << USART_STS_RDBF_Pos) /*!< 0x00000020 */ +#define USART_STS_RDBF USART_STS_RDBF_Msk /*!< Receive data buffer full */ +#define USART_STS_TDC_Pos (6U) +#define USART_STS_TDC_Msk (0x1U << USART_STS_TDC_Pos) /*!< 0x00000040 */ +#define USART_STS_TDC USART_STS_TDC_Msk /*!< Transmit data complete */ +#define USART_STS_TDBE_Pos (7U) +#define USART_STS_TDBE_Msk (0x1U << USART_STS_TDBE_Pos) /*!< 0x00000080 */ +#define USART_STS_TDBE USART_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define USART_STS_BFF_Pos (8U) +#define USART_STS_BFF_Msk (0x1U << USART_STS_BFF_Pos) /*!< 0x00000100 */ +#define USART_STS_BFF USART_STS_BFF_Msk /*!< Break frame flag */ +#define USART_STS_CTSCF_Pos (9U) +#define USART_STS_CTSCF_Msk (0x1U << USART_STS_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_STS_CTSCF USART_STS_CTSCF_Msk /*!< CTS change flag */ + +/******************* Bit definition for USART_DT register *******************/ +#define USART_DT_DT_Pos (0U) +#define USART_DT_DT_Msk (0x1FFU << USART_DT_DT_Pos) /*!< 0x000001FF */ +#define USART_DT_DT USART_DT_DT_Msk /*!< Data value */ + +/***************** Bit definition for USART_BAUDR register ******************/ +#define USART_BAUDR_DIV_Pos (0U) +#define USART_BAUDR_DIV_Msk (0xFFFFU << USART_BAUDR_DIV_Pos) /*!< 0x0000FFFF */ +#define USART_BAUDR_DIV USART_BAUDR_DIV_Msk /*!< Divider */ + +/***************** Bit definition for USART_CTRL1 register ******************/ +#define USART_CTRL1_SBF_Pos (0U) +#define USART_CTRL1_SBF_Msk (0x1U << USART_CTRL1_SBF_Pos) /*!< 0x00000001 */ +#define USART_CTRL1_SBF USART_CTRL1_SBF_Msk /*!< Send break frame */ +#define USART_CTRL1_RM_Pos (1U) +#define USART_CTRL1_RM_Msk (0x1U << USART_CTRL1_RM_Pos) /*!< 0x00000002 */ +#define USART_CTRL1_RM USART_CTRL1_RM_Msk /*!< Receiver mute */ +#define USART_CTRL1_REN_Pos (2U) +#define USART_CTRL1_REN_Msk (0x1U << USART_CTRL1_REN_Pos) /*!< 0x00000004 */ +#define USART_CTRL1_REN USART_CTRL1_REN_Msk /*!< Receiver enable */ +#define USART_CTRL1_TEN_Pos (3U) +#define USART_CTRL1_TEN_Msk (0x1U << USART_CTRL1_TEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL1_TEN USART_CTRL1_TEN_Msk /*!< Transmitter enable */ +#define USART_CTRL1_IDLEIEN_Pos (4U) +#define USART_CTRL1_IDLEIEN_Msk (0x1U << USART_CTRL1_IDLEIEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL1_IDLEIEN USART_CTRL1_IDLEIEN_Msk /*!< IDLE interrupt enable */ +#define USART_CTRL1_RDBFIEN_Pos (5U) +#define USART_CTRL1_RDBFIEN_Msk (0x1U << USART_CTRL1_RDBFIEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL1_RDBFIEN USART_CTRL1_RDBFIEN_Msk /*!< RDBF interrupt enable */ +#define USART_CTRL1_TDCIEN_Pos (6U) +#define USART_CTRL1_TDCIEN_Msk (0x1U << USART_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL1_TDCIEN USART_CTRL1_TDCIEN_Msk /*!< TDC interrupt enable */ +#define USART_CTRL1_TDBEIEN_Pos (7U) +#define USART_CTRL1_TDBEIEN_Msk (0x1U << USART_CTRL1_TDBEIEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL1_TDBEIEN USART_CTRL1_TDBEIEN_Msk /*!< TDBE interrupt enable */ +#define USART_CTRL1_PERRIEN_Pos (8U) +#define USART_CTRL1_PERRIEN_Msk (0x1U << USART_CTRL1_PERRIEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL1_PERRIEN USART_CTRL1_PERRIEN_Msk /*!< PERR interrupt enable */ +#define USART_CTRL1_PSEL_Pos (9U) +#define USART_CTRL1_PSEL_Msk (0x1U << USART_CTRL1_PSEL_Pos) /*!< 0x00000200 */ +#define USART_CTRL1_PSEL USART_CTRL1_PSEL_Msk /*!< Parity selection */ +#define USART_CTRL1_PEN_Pos (10U) +#define USART_CTRL1_PEN_Msk (0x1U << USART_CTRL1_PEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL1_PEN USART_CTRL1_PEN_Msk /*!< Parity enable */ +#define USART_CTRL1_WUM_Pos (11U) +#define USART_CTRL1_WUM_Msk (0x1U << USART_CTRL1_WUM_Pos) /*!< 0x00000800 */ +#define USART_CTRL1_WUM USART_CTRL1_WUM_Msk /*!< Wakeup mode */ +#define USART_CTRL1_DBN_Pos (12U) +#define USART_CTRL1_DBN_Msk (0x1U << USART_CTRL1_DBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL1_DBN USART_CTRL1_DBN_Msk /*!< Data bit num */ +#define USART_CTRL1_UEN_Pos (13U) +#define USART_CTRL1_UEN_Msk (0x1U << USART_CTRL1_UEN_Pos) /*!< 0x00002000 */ +#define USART_CTRL1_UEN USART_CTRL1_UEN_Msk /*!< USART enable */ + +/***************** Bit definition for USART_CTRL2 register ******************/ +#define USART_CTRL2_ID_Pos (0U) +#define USART_CTRL2_ID_Msk (0xFU << USART_CTRL2_ID_Pos) /*!< 0x0000000F */ +#define USART_CTRL2_ID USART_CTRL2_ID_Msk /*!< USART identification */ +#define USART_CTRL2_BFBN_Pos (5U) +#define USART_CTRL2_BFBN_Msk (0x1U << USART_CTRL2_BFBN_Pos) /*!< 0x00000020 */ +#define USART_CTRL2_BFBN USART_CTRL2_BFBN_Msk /*!< Break frame bit num */ +#define USART_CTRL2_BFIEN_Pos (6U) +#define USART_CTRL2_BFIEN_Msk (0x1U << USART_CTRL2_BFIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL2_BFIEN USART_CTRL2_BFIEN_Msk /*!< Break frame interrupt enable */ +#define USART_CTRL2_LBCP_Pos (8U) +#define USART_CTRL2_LBCP_Msk (0x1U << USART_CTRL2_LBCP_Pos) /*!< 0x00000100 */ +#define USART_CTRL2_LBCP USART_CTRL2_LBCP_Msk /*!< Last bit clock pulse */ +#define USART_CTRL2_CLKPHA_Pos (9U) +#define USART_CTRL2_CLKPHA_Msk (0x1U << USART_CTRL2_CLKPHA_Pos) /*!< 0x00000200 */ +#define USART_CTRL2_CLKPHA USART_CTRL2_CLKPHA_Msk /*!< Clock phase */ +#define USART_CTRL2_CLKPOL_Pos (10U) +#define USART_CTRL2_CLKPOL_Msk (0x1U << USART_CTRL2_CLKPOL_Pos) /*!< 0x00000400 */ +#define USART_CTRL2_CLKPOL USART_CTRL2_CLKPOL_Msk /*!< Clock polarity */ +#define USART_CTRL2_CLKEN_Pos (11U) +#define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ + +#define USART_CTRL2_STOPBN_Pos (12U) +#define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ +#define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ +#define USART_CTRL2_STOPBN_0 (0x1U << USART_CTRL2_STOPBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL2_STOPBN_1 (0x2U << USART_CTRL2_STOPBN_Pos) /*!< 0x00002000 */ + +#define USART_CTRL2_LINEN_Pos (14U) +#define USART_CTRL2_LINEN_Msk (0x1U << USART_CTRL2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CTRL2_LINEN USART_CTRL2_LINEN_Msk /*!< LIN mode enable */ + +/***************** Bit definition for USART_CTRL3 register ******************/ +#define USART_CTRL3_ERRIEN_Pos (0U) +#define USART_CTRL3_ERRIEN_Msk (0x1U << USART_CTRL3_ERRIEN_Pos) /*!< 0x00000001 */ +#define USART_CTRL3_ERRIEN USART_CTRL3_ERRIEN_Msk /*!< Error interrupt enable */ +#define USART_CTRL3_IRDAEN_Pos (1U) +#define USART_CTRL3_IRDAEN_Msk (0x1U << USART_CTRL3_IRDAEN_Pos) /*!< 0x00000002 */ +#define USART_CTRL3_IRDAEN USART_CTRL3_IRDAEN_Msk /*!< IrDA enable */ +#define USART_CTRL3_IRDALP_Pos (2U) +#define USART_CTRL3_IRDALP_Msk (0x1U << USART_CTRL3_IRDALP_Pos) /*!< 0x00000004 */ +#define USART_CTRL3_IRDALP USART_CTRL3_IRDALP_Msk /*!< IrDA low-power mode */ +#define USART_CTRL3_SLBEN_Pos (3U) +#define USART_CTRL3_SLBEN_Msk (0x1U << USART_CTRL3_SLBEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL3_SLBEN USART_CTRL3_SLBEN_Msk /*!< Single-wire bidirectional half-duplex enable */ +#define USART_CTRL3_SCNACKEN_Pos (4U) +#define USART_CTRL3_SCNACKEN_Msk (0x1U << USART_CTRL3_SCNACKEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL3_SCNACKEN USART_CTRL3_SCNACKEN_Msk /*!< Smart Card NACK enable */ +#define USART_CTRL3_SCMEN_Pos (5U) +#define USART_CTRL3_SCMEN_Msk (0x1U << USART_CTRL3_SCMEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL3_SCMEN USART_CTRL3_SCMEN_Msk /*!< Smart Card mode enable */ +#define USART_CTRL3_DMAREN_Pos (6U) +#define USART_CTRL3_DMAREN_Msk (0x1U << USART_CTRL3_DMAREN_Pos) /*!< 0x00000040 */ +#define USART_CTRL3_DMAREN USART_CTRL3_DMAREN_Msk /*!< DMA receiver enable */ +#define USART_CTRL3_DMATEN_Pos (7U) +#define USART_CTRL3_DMATEN_Msk (0x1U << USART_CTRL3_DMATEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL3_DMATEN USART_CTRL3_DMATEN_Msk /*!< DMA transmitter enable */ +#define USART_CTRL3_RTSEN_Pos (8U) +#define USART_CTRL3_RTSEN_Msk (0x1U << USART_CTRL3_RTSEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL3_RTSEN USART_CTRL3_RTSEN_Msk /*!< RTS enable */ +#define USART_CTRL3_CTSEN_Pos (9U) +#define USART_CTRL3_CTSEN_Msk (0x1U << USART_CTRL3_CTSEN_Pos) /*!< 0x00000200 */ +#define USART_CTRL3_CTSEN USART_CTRL3_CTSEN_Msk /*!< CTS enable */ +#define USART_CTRL3_CTSCFIEN_Pos (10U) +#define USART_CTRL3_CTSCFIEN_Msk (0x1U << USART_CTRL3_CTSCFIEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ + +/****************** Bit definition for USART_GDIV register ******************/ +#define USART_GDIV_ISDIV_Pos (0U) +#define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ +#define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ +#define USART_GDIV_ISDIV_0 (0x01U << USART_GDIV_ISDIV_Pos) /*!< 0x00000001 */ +#define USART_GDIV_ISDIV_1 (0x02U << USART_GDIV_ISDIV_Pos) /*!< 0x00000002 */ +#define USART_GDIV_ISDIV_2 (0x04U << USART_GDIV_ISDIV_Pos) /*!< 0x00000004 */ +#define USART_GDIV_ISDIV_3 (0x08U << USART_GDIV_ISDIV_Pos) /*!< 0x00000008 */ +#define USART_GDIV_ISDIV_4 (0x10U << USART_GDIV_ISDIV_Pos) /*!< 0x00000010 */ +#define USART_GDIV_ISDIV_5 (0x20U << USART_GDIV_ISDIV_Pos) /*!< 0x00000020 */ +#define USART_GDIV_ISDIV_6 (0x40U << USART_GDIV_ISDIV_Pos) /*!< 0x00000040 */ +#define USART_GDIV_ISDIV_7 (0x80U << USART_GDIV_ISDIV_Pos) /*!< 0x00000080 */ + +#define USART_GDIV_SCGT_Pos (8U) +#define USART_GDIV_SCGT_Msk (0xFFU << USART_GDIV_SCGT_Pos) /*!< 0x0000FF00 */ +#define USART_GDIV_SCGT USART_GDIV_SCGT_Msk /*!< Smart Card guard time value */ + +/******************************************************************************/ +/* */ +/* Serial peripheral interface (SPI) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SPI_CTRL1 register *******************/ +#define SPI_CTRL1_CLKPHA_Pos (0U) +#define SPI_CTRL1_CLKPHA_Msk (0x1U << SPI_CTRL1_CLKPHA_Pos) /*!< 0x00000001 */ +#define SPI_CTRL1_CLKPHA SPI_CTRL1_CLKPHA_Msk /*!< Clock phase */ +#define SPI_CTRL1_CLKPOL_Pos (1U) +#define SPI_CTRL1_CLKPOL_Msk (0x1U << SPI_CTRL1_CLKPOL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL1_CLKPOL SPI_CTRL1_CLKPOL_Msk /*!< Clock polarity */ +#define SPI_CTRL1_MSTEN_Pos (2U) +#define SPI_CTRL1_MSTEN_Msk (0x1U << SPI_CTRL1_MSTEN_Pos) /*!< 0x00000004 */ +#define SPI_CTRL1_MSTEN SPI_CTRL1_MSTEN_Msk /*!< Master enable */ + +/*!< MDIV configuration */ +#define SPI_CTRL1_MDIV_Msk ((SPI_CTRL2_MDIV) | (0x7U << 3) /*!< 0x00000138 */ +#define SPI_CTRL1_MDIV SPI_CTRL1_MDIV_Msk /*!< MDIV[3:0] bits (Master clock frequency division) */ +#define SPI_CTRL1_MDIV_0 (0x1U << 3) /*!< 0x00000008 */ +#define SPI_CTRL1_MDIV_1 (0x2U << 3) /*!< 0x00000010 */ +#define SPI_CTRL1_MDIV_2 (0x4U << 3) /*!< 0x00000020 */ +#define SPI_CTRL1_MDIV_3 SPI_CTRL2_MDIV /*!< 0x00000100 */ + +#define SPI_CTRL1_SPIEN_Pos (6U) +#define SPI_CTRL1_SPIEN_Msk (0x1U << SPI_CTRL1_SPIEN_Pos) /*!< 0x00000040 */ +#define SPI_CTRL1_SPIEN SPI_CTRL1_SPIEN_Msk /*!< SPI enable */ +#define SPI_CTRL1_LTF_Pos (7U) +#define SPI_CTRL1_LTF_Msk (0x1U << SPI_CTRL1_LTF_Pos) /*!< 0x00000080 */ +#define SPI_CTRL1_LTF SPI_CTRL1_LTF_Msk /*!< LSB transmit first */ +#define SPI_CTRL1_SWCSIL_Pos (8U) +#define SPI_CTRL1_SWCSIL_Msk (0x1U << SPI_CTRL1_SWCSIL_Pos) /*!< 0x00000100 */ +#define SPI_CTRL1_SWCSIL SPI_CTRL1_SWCSIL_Msk /*!< Software CS internal level */ +#define SPI_CTRL1_SWCSEN_Pos (9U) +#define SPI_CTRL1_SWCSEN_Msk (0x1U << SPI_CTRL1_SWCSEN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL1_SWCSEN SPI_CTRL1_SWCSEN_Msk /*!< Software CS enable */ +#define SPI_CTRL1_ORA_Pos (10U) +#define SPI_CTRL1_ORA_Msk (0x1U << SPI_CTRL1_ORA_Pos) /*!< 0x00000400 */ +#define SPI_CTRL1_ORA SPI_CTRL1_ORA_Msk /*!< Receive-only active */ +#define SPI_CTRL1_FBN_Pos (11U) +#define SPI_CTRL1_FBN_Msk (0x1U << SPI_CTRL1_FBN_Pos) /*!< 0x00000800 */ +#define SPI_CTRL1_FBN SPI_CTRL1_FBN_Msk /*!< Frame bit num */ +#define SPI_CTRL1_NTC_Pos (12U) +#define SPI_CTRL1_NTC_Msk (0x1U << SPI_CTRL1_NTC_Pos) /*!< 0x00001000 */ +#define SPI_CTRL1_NTC SPI_CTRL1_NTC_Msk /*!< Transmit CRC next */ +#define SPI_CTRL1_CCEN_Pos (13U) +#define SPI_CTRL1_CCEN_Msk (0x1U << SPI_CTRL1_CCEN_Pos) /*!< 0x00002000 */ +#define SPI_CTRL1_CCEN SPI_CTRL1_CCEN_Msk /*!< RC calculation enable */ +#define SPI_CTRL1_SLBTD_Pos (14U) +#define SPI_CTRL1_SLBTD_Msk (0x1U << SPI_CTRL1_SLBTD_Pos) /*!< 0x00004000 */ +#define SPI_CTRL1_SLBTD SPI_CTRL1_SLBTD_Msk /*!< Single line bidirectional half-duplex transmission direction */ +#define SPI_CTRL1_SLBEN_Pos (15U) +#define SPI_CTRL1_SLBEN_Msk (0x1U << SPI_CTRL1_SLBEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL1_SLBEN SPI_CTRL1_SLBEN_Msk /*!< Single line bidirectional half-duplex enable */ + +/****************** Bit definition for SPI_CTRL2 register *******************/ +#define SPI_CTRL2_DMAREN_Pos (0U) +#define SPI_CTRL2_DMAREN_Msk (0x1U << SPI_CTRL2_DMAREN_Pos) /*!< 0x00000001 */ +#define SPI_CTRL2_DMAREN SPI_CTRL2_DMAREN_Msk /*!< DMA receive enable */ +#define SPI_CTRL2_DMATEN_Pos (1U) +#define SPI_CTRL2_DMATEN_Msk (0x1U << SPI_CTRL2_DMATEN_Pos) /*!< 0x00000002 */ +#define SPI_CTRL2_DMATEN SPI_CTRL2_DMATEN_Msk /*!< DMA transmit enable */ +#define SPI_CTRL2_HWCSOE_Pos (2U) +#define SPI_CTRL2_HWCSOE_Msk (0x1U << SPI_CTRL2_HWCSOE_Pos) /*!< 0x00000004 */ +#define SPI_CTRL2_HWCSOE SPI_CTRL2_HWCSOE_Msk /*!< Hardware CS output enable */ +#define SPI_CTRL2_ERRIE_Pos (5U) +#define SPI_CTRL2_ERRIE_Msk (0x1U << SPI_CTRL2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CTRL2_ERRIE SPI_CTRL2_ERRIE_Msk /*!< Error interrupt enable */ +#define SPI_CTRL2_RDBFIE_Pos (6U) +#define SPI_CTRL2_RDBFIE_Msk (0x1U << SPI_CTRL2_RDBFIE_Pos) /*!< 0x00000040 */ +#define SPI_CTRL2_RDBFIE SPI_CTRL2_RDBFIE_Msk /*!< Receive data buffer full interrupt enable */ +#define SPI_CTRL2_TDBEIE_Pos (7U) +#define SPI_CTRL2_TDBEIE_Msk (0x1U << SPI_CTRL2_TDBEIE_Pos) /*!< 0x00000080 */ +#define SPI_CTRL2_TDBEIE SPI_CTRL2_TDBEIE_Msk /*!< Transmit data buffer empty interrupt enable */ +#define SPI_CTRL2_MDIV_Pos (8U) +#define SPI_CTRL2_MDIV_Msk (0x1U << SPI_CTRL2_MDIV_Pos) /*!< 0x00000100 */ +#define SPI_CTRL2_MDIV SPI_CTRL2_MDIV_Msk /*!< Master clock frequency division */ + +/******************* Bit definition for SPI_STS register ********************/ +#define SPI_STS_RDBF_Pos (0U) +#define SPI_STS_RDBF_Msk (0x1U << SPI_STS_RDBF_Pos) /*!< 0x00000001 */ +#define SPI_STS_RDBF SPI_STS_RDBF_Msk /*!< Receive data buffer full */ +#define SPI_STS_TDBE_Pos (1U) +#define SPI_STS_TDBE_Msk (0x1U << SPI_STS_TDBE_Pos) /*!< 0x00000002 */ +#define SPI_STS_TDBE SPI_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define SPI_STS_ACS_Pos (2U) +#define SPI_STS_ACS_Msk (0x1U << SPI_STS_ACS_Pos) /*!< 0x00000004 */ +#define SPI_STS_ACS SPI_STS_ACS_Msk /*!< Audio channel state */ +#define SPI_STS_TUERR_Pos (3U) +#define SPI_STS_TUERR_Msk (0x1U << SPI_STS_TUERR_Pos) /*!< 0x00000008 */ +#define SPI_STS_TUERR SPI_STS_TUERR_Msk /*!< Transmitter underload error */ +#define SPI_STS_CCERR_Pos (4U) +#define SPI_STS_CCERR_Msk (0x1U << SPI_STS_CCERR_Pos) /*!< 0x00000010 */ +#define SPI_STS_CCERR SPI_STS_CCERR_Msk /*!< CRC error */ +#define SPI_STS_MMERR_Pos (5U) +#define SPI_STS_MMERR_Msk (0x1U << SPI_STS_MMERR_Pos) /*!< 0x00000020 */ +#define SPI_STS_MMERR SPI_STS_MMERR_Msk /*!< Master mode error */ +#define SPI_STS_ROERR_Pos (6U) +#define SPI_STS_ROERR_Msk (0x1U << SPI_STS_ROERR_Pos) /*!< 0x00000040 */ +#define SPI_STS_ROERR SPI_STS_ROERR_Msk /*!< Receiver overflow error */ +#define SPI_STS_BF_Pos (7U) +#define SPI_STS_BF_Msk (0x1U << SPI_STS_BF_Pos) /*!< 0x00000080 */ +#define SPI_STS_BF SPI_STS_BF_Msk /*!< Busy flag */ + +/******************** Bit definition for SPI_DT register ********************/ +#define SPI_DT_DT_Pos (0U) +#define SPI_DT_DT_Msk (0xFFFFU << SPI_DT_DT_Pos) /*!< 0x0000FFFF */ +#define SPI_DT_DT SPI_DT_DT_Msk /*!< Data value */ + +/******************* Bit definition for SPI_CPOLY register ******************/ +#define SPI_CPOLY_CPOLY_Pos (0U) +#define SPI_CPOLY_CPOLY_Msk (0xFFFFU << SPI_CPOLY_CPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CPOLY_CPOLY SPI_CPOLY_CPOLY_Msk /*!< CRC polynomial */ + +/******************* Bit definition for SPI_RCRC register *******************/ +#define SPI_RCRC_RCRC_Pos (0U) +#define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Receive CRC */ + +/******************* Bit definition for SPI_TCRC register *******************/ +#define SPI_TCRC_TCRC_Pos (0U) +#define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Transmit CRC */ + +/***************** Bit definition for SPI_I2SCTRL register ******************/ +#define SPI_I2SCTRL_I2SCBN_Pos (0U) +#define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ + +#define SPI_I2SCTRL_I2SDBN_Pos (1U) +#define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ +#define SPI_I2SCTRL_I2SDBN_0 (0x1U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCTRL_I2SDBN_1 (0x2U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCTRL_I2SCLKPOL_Pos (3U) +#define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ + +#define SPI_I2SCTRL_STDSEL_Pos (4U) +#define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ +#define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ +#define SPI_I2SCTRL_STDSEL_0 (0x1U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000010 */ +#define SPI_I2SCTRL_STDSEL_1 (0x2U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCTRL_PCMFSSEL_Pos (7U) +#define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ +#define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ + +#define SPI_I2SCTRL_OPERSEL_Pos (8U) +#define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ +#define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ +#define SPI_I2SCTRL_OPERSEL_0 (0x1U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000100 */ +#define SPI_I2SCTRL_OPERSEL_1 (0x2U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCTRL_I2SEN_Pos (10U) +#define SPI_I2SCTRL_I2SEN_Msk (0x1U << SPI_I2SCTRL_I2SEN_Pos) /*!< 0x00000400 */ +#define SPI_I2SCTRL_I2SEN SPI_I2SCTRL_I2SEN_Msk /*!< I2S enable */ +#define SPI_I2SCTRL_I2SMSEL_Pos (11U) +#define SPI_I2SCTRL_I2SMSEL_Msk (0x1U << SPI_I2SCTRL_I2SMSEL_Pos) /*!< 0x00000800 */ +#define SPI_I2SCTRL_I2SMSEL SPI_I2SCTRL_I2SMSEL_Msk /*!< I2S mode select */ + +/***************** Bit definition for SPI_I2SCLKP register ******************/ +#define SPI_I2SCLKP_I2SDIV_Msk ((0xFFU << 0) | (0x3U << 10)) /*!< 0x00000CFF */ +#define SPI_I2SCLKP_I2SDIV SPI_I2SCLKP_I2SDIV_Msk /*!< I2SDIV[9:0] bits (I2S division) */ +#define SPI_I2SCLKP_I2SODD_Pos (8U) +#define SPI_I2SCLKP_I2SODD_Msk (0x1U << SPI_I2SCLKP_I2SODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SCLKP_I2SODD SPI_I2SCLKP_I2SODD_Msk /*!< Odd factor for I2S division */ +#define SPI_I2SCLKP_I2SMCLKOE_Pos (9U) +#define SPI_I2SCLKP_I2SMCLKOE_Msk (0x1U << SPI_I2SCLKP_I2SMCLKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SCLKP_I2SMCLKOE SPI_I2SCLKP_I2SMCLKOE_Msk /*!< I2S Master clock output enable */ + +/******************************************************************************/ +/* */ +/* Window watchdog timer (WWDT) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for WWDT_CTRL register *******************/ +#define WWDT_CTRL_CNT_Pos (0U) +#define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ +#define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ +#define WWDT_CTRL_CNT_0 (0x01U << WWDT_CTRL_CNT_Pos) /*!< 0x00000001 */ +#define WWDT_CTRL_CNT_1 (0x02U << WWDT_CTRL_CNT_Pos) /*!< 0x00000002 */ +#define WWDT_CTRL_CNT_2 (0x04U << WWDT_CTRL_CNT_Pos) /*!< 0x00000004 */ +#define WWDT_CTRL_CNT_3 (0x08U << WWDT_CTRL_CNT_Pos) /*!< 0x00000008 */ +#define WWDT_CTRL_CNT_4 (0x10U << WWDT_CTRL_CNT_Pos) /*!< 0x00000010 */ +#define WWDT_CTRL_CNT_5 (0x20U << WWDT_CTRL_CNT_Pos) /*!< 0x00000020 */ +#define WWDT_CTRL_CNT_6 (0x40U << WWDT_CTRL_CNT_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CTRL_CNT0 WWDT_CTRL_CNT_0 +#define WWDT_CTRL_CNT1 WWDT_CTRL_CNT_1 +#define WWDT_CTRL_CNT2 WWDT_CTRL_CNT_2 +#define WWDT_CTRL_CNT3 WWDT_CTRL_CNT_3 +#define WWDT_CTRL_CNT4 WWDT_CTRL_CNT_4 +#define WWDT_CTRL_CNT5 WWDT_CTRL_CNT_5 +#define WWDT_CTRL_CNT6 WWDT_CTRL_CNT_6 + +#define WWDT_CTRL_WWDTEN_Pos (7U) +#define WWDT_CTRL_WWDTEN_Msk (0x1U << WWDT_CTRL_WWDTEN_Pos) /*!< 0x00000080 */ +#define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ + +/******************* Bit definition for WWDT_CFG register *******************/ +#define WWDT_CFG_WIN_Pos (0U) +#define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ +#define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ +#define WWDT_CFG_WIN_0 (0x01U << WWDT_CFG_WIN_Pos) /*!< 0x00000001 */ +#define WWDT_CFG_WIN_1 (0x02U << WWDT_CFG_WIN_Pos) /*!< 0x00000002 */ +#define WWDT_CFG_WIN_2 (0x04U << WWDT_CFG_WIN_Pos) /*!< 0x00000004 */ +#define WWDT_CFG_WIN_3 (0x08U << WWDT_CFG_WIN_Pos) /*!< 0x00000008 */ +#define WWDT_CFG_WIN_4 (0x10U << WWDT_CFG_WIN_Pos) /*!< 0x00000010 */ +#define WWDT_CFG_WIN_5 (0x20U << WWDT_CFG_WIN_Pos) /*!< 0x00000020 */ +#define WWDT_CFG_WIN_6 (0x40U << WWDT_CFG_WIN_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CFG_WIN0 WWDT_CFG_WIN_0 +#define WWDT_CFG_WIN1 WWDT_CFG_WIN_1 +#define WWDT_CFG_WIN2 WWDT_CFG_WIN_2 +#define WWDT_CFG_WIN3 WWDT_CFG_WIN_3 +#define WWDT_CFG_WIN4 WWDT_CFG_WIN_4 +#define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 +#define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 + +#define WWDT_CFG_DIV_Pos (7U) +#define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ +#define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ +#define WWDT_CFG_DIV_0 (0x1U << WWDT_CFG_DIV_Pos) /*!< 0x00000080 */ +#define WWDT_CFG_DIV_1 (0x2U << WWDT_CFG_DIV_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDT_CFG_DIV0 WWDT_CFG_DIV_0 +#define WWDT_CFG_DIV1 WWDT_CFG_DIV_1 + +#define WWDT_CFG_RLDIEN_Pos (9U) +#define WWDT_CFG_RLDIEN_Msk (0x1U << WWDT_CFG_RLDIEN_Pos) /*!< 0x00000200 */ +#define WWDT_CFG_RLDIEN WWDT_CFG_RLDIEN_Msk /*!< Reload counter interrupt */ + +/******************* Bit definition for WWDT_STS register *******************/ +#define WWDT_STS_RLDF_Pos (0U) +#define WWDT_STS_RLDF_Msk (0x1U << WWDT_STS_RLDF_Pos) /*!< 0x00000001 */ +#define WWDT_STS_RLDF WWDT_STS_RLDF_Msk /*!< Reload counter interrupt flag */ + +/******************************************************************************/ +/* */ +/* Watchdog timer (WDT) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WDT_CMD register ********************/ +#define WDT_CMD_CMD_Pos (0U) +#define WDT_CMD_CMD_Msk (0xFFFFU << WDT_CMD_CMD_Pos) /*!< 0x0000FFFF */ +#define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ + +/******************* Bit definition for WDT_DIV register ********************/ +#define WDT_DIV_DIV_Pos (0U) +#define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ +#define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ +#define WDT_DIV_DIV_0 (0x1U << WDT_DIV_DIV_Pos) /*!< 0x00000001 */ +#define WDT_DIV_DIV_1 (0x2U << WDT_DIV_DIV_Pos) /*!< 0x00000002 */ +#define WDT_DIV_DIV_2 (0x4U << WDT_DIV_DIV_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for WDT_RLD register ********************/ +#define WDT_RLD_RLD_Pos (0U) +#define WDT_RLD_RLD_Msk (0xFFFU << WDT_RLD_RLD_Pos) /*!< 0x00000FFF */ +#define WDT_RLD_RLD WDT_RLD_RLD_Msk /*!< Reload value */ + +/******************* Bit definition for WDT_STS register ********************/ +#define WDT_STS_DIVF_Pos (0U) +#define WDT_STS_DIVF_Msk (0x1U << WDT_STS_DIVF_Pos) /*!< 0x00000001 */ +#define WDT_STS_DIVF WDT_STS_DIVF_Msk /*!< Division value update complete flag */ +#define WDT_STS_RLDF_Pos (1U) +#define WDT_STS_RLDF_Msk (0x1U << WDT_STS_RLDF_Pos) /*!< 0x00000002 */ +#define WDT_STS_RLDF WDT_STS_RLDF_Msk /*!< Reload value update complete flag */ + +/******************************************************************************/ +/* */ +/* Enhanced real-time clock (ERTC) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for ERTC_TIME register *******************/ +#define ERTC_TIME_SU_Pos (0U) +#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_TIME_ST_Pos (4U) +#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_TIME_MU_Pos (8U) +#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TIME_MT_Pos (12U) +#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_TIME_HU_Pos (16U) +#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_TIME_HT_Pos (20U) +#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TIME_AMPM_Pos (22U) +#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_DATE register *******************/ +#define ERTC_DATE_DU_Pos (0U) +#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ +#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ +#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ +#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ +#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ + +#define ERTC_DATE_DT_Pos (4U) +#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ +#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ +#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ + +#define ERTC_DATE_MU_Pos (8U) +#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ +#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ +#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ +#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_DATE_MT_Pos (12U) +#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ +#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ + +#define ERTC_DATE_WK_Pos (13U) +#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ +#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ +#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ + +#define ERTC_DATE_YU_Pos (16U) +#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ +#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ +#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ +#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ +#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ +#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ + +#define ERTC_DATE_YT_Pos (20U) +#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ +#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ +#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ +#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ +#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ +#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ERTC_CTRL register *******************/ +#define ERTC_CTRL_WATCLK_Pos (0U) +#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ +#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ +#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ +#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ +#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ + +#define ERTC_CTRL_TSEDG_Pos (3U) +#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ +#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ +#define ERTC_CTRL_RCDEN_Pos (4U) +#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ +#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ +#define ERTC_CTRL_DREN_Pos (5U) +#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ +#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ +#define ERTC_CTRL_HM_Pos (6U) +#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ +#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ +#define ERTC_CTRL_CCALEN_Pos (7U) +#define ERTC_CTRL_CCALEN_Msk (0x1U << ERTC_CTRL_CCALEN_Pos) /*!< 0x00000080 */ +#define ERTC_CTRL_CCALEN ERTC_CTRL_CCALEN_Msk /*!< Coarse calibration enable */ +#define ERTC_CTRL_ALAEN_Pos (8U) +#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ +#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ +#define ERTC_CTRL_ALBEN_Pos (9U) +#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ +#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ +#define ERTC_CTRL_WATEN_Pos (10U) +#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ +#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ +#define ERTC_CTRL_TSEN_Pos (11U) +#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ +#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ +#define ERTC_CTRL_ALAIEN_Pos (12U) +#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ +#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ +#define ERTC_CTRL_ALBIEN_Pos (13U) +#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ +#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ +#define ERTC_CTRL_WATIEN_Pos (14U) +#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ +#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ +#define ERTC_CTRL_TSIEN_Pos (15U) +#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ +#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ +#define ERTC_CTRL_ADD1H_Pos (16U) +#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ +#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ +#define ERTC_CTRL_DEC1H_Pos (17U) +#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ +#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ +#define ERTC_CTRL_BPR_Pos (18U) +#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ +#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ +#define ERTC_CTRL_CALOSEL_Pos (19U) +#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ +#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ +#define ERTC_CTRL_OUTP_Pos (20U) +#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ +#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ + +#define ERTC_CTRL_OUTSEL_Pos (21U) +#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< WATCLK[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ +#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ + +#define ERTC_CTRL_CALOEN_Pos (23U) +#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ +#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ + +/******************* Bit definition for ERTC_STS register *******************/ +#define ERTC_STS_ALAWF_Pos (0U) +#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ +#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ +#define ERTC_STS_ALBWF_Pos (1U) +#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ +#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ +#define ERTC_STS_WATWF_Pos (2U) +#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ +#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ +#define ERTC_STS_TADJF_Pos (3U) +#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ +#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ +#define ERTC_STS_INITF_Pos (4U) +#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ +#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ +#define ERTC_STS_UPDF_Pos (5U) +#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ +#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ +#define ERTC_STS_IMF_Pos (6U) +#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ +#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ +#define ERTC_STS_IMEN_Pos (7U) +#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ +#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ +#define ERTC_STS_ALAF_Pos (8U) +#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ +#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ +#define ERTC_STS_ALBF_Pos (9U) +#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ +#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ +#define ERTC_STS_WATF_Pos (10U) +#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ +#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ +#define ERTC_STS_TSF_Pos (11U) +#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ +#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ +#define ERTC_STS_TSOF_Pos (12U) +#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ +#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ +#define ERTC_STS_TP1F_Pos (13U) +#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ +#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ +#define ERTC_STS_CALUPDF_Pos (16U) +#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ +#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ + +/******************* Bit definition for ERTC_DIV register *******************/ +#define ERTC_DIV_DIVB_Pos (0U) +#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ +#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ +#define ERTC_DIV_DIVA_Pos (16U) +#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ +#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ + +/******************* Bit definition for ERTC_WAT register *******************/ +#define ERTC_WAT_VAL_Pos (0U) +#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ +#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ + +/****************** Bit definition for ERTC_CCAL register *******************/ +#define ERTC_CCAL_CALVAL_Pos (0U) +#define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ +#define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ +#define ERTC_CCAL_CALVAL_0 (0x1U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000001 */ +#define ERTC_CCAL_CALVAL_1 (0x2U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000002 */ +#define ERTC_CCAL_CALVAL_2 (0x4U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000004 */ +#define ERTC_CCAL_CALVAL_3 (0x8U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000008 */ +#define ERTC_CCAL_CALVAL_4 (0x10U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000010 */ + +#define ERTC_CCAL_CALDIR_Pos (7U) +#define ERTC_CCAL_CALDIR_Msk (0x1U << ERTC_CCAL_CALDIR_Pos) /*!< 0x00000080 */ +#define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ + +/******************* Bit definition for ERTC_ALA register *******************/ +#define ERTC_ALA_SU_Pos (0U) +#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_ALA_ST_Pos (4U) +#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALA_MASK1_Pos (7U) +#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ + +#define ERTC_ALA_MU_Pos (8U) +#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_ALA_MT_Pos (12U) +#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALA_MASK2_Pos (15U) +#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ + +#define ERTC_ALA_HU_Pos (16U) +#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_ALA_HT_Pos (20U) +#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALA_AMPM_Pos (22U) +#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALA_MASK3_Pos (23U) +#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ + +#define ERTC_ALA_DU_Pos (24U) +#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ + +#define ERTC_ALA_DT_Pos (28U) +#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALA_WKSEL_Pos (30U) +#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALA_MASK4_Pos (31U) +#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_ALB register *******************/ +#define ERTC_ALB_SU_Pos (0U) +#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_ALB_ST_Pos (4U) +#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALB_MASK1_Pos (7U) +#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ + +#define ERTC_ALB_MU_Pos (8U) +#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_ALB_MT_Pos (12U) +#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALB_MASK2_Pos (15U) +#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ + +#define ERTC_ALB_HU_Pos (16U) +#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_ALB_HT_Pos (20U) +#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALB_AMPM_Pos (22U) +#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALB_MASK3_Pos (23U) +#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ + +#define ERTC_ALB_DU_Pos (24U) +#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ + +#define ERTC_ALB_DT_Pos (28U) +#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALB_WKSEL_Pos (30U) +#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALB_MASK4_Pos (31U) +#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_WP register ********************/ +#define ERTC_WP_CMD_Pos (0U) +#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ +#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ + +/******************* Bit definition for ERTC_SBS register *******************/ +#define ERTC_SBS_SBS_Pos (0U) +#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_TADJ register *******************/ +#define ERTC_TADJ_DECSBS_Pos (0U) +#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ +#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ +#define ERTC_TADJ_ADD1S_Pos (31U) +#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ +#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ + +/****************** Bit definition for ERTC_TSTM register *******************/ +#define ERTC_TSTM_SU_Pos (0U) +#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_TSTM_ST_Pos (4U) +#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_TSTM_MU_Pos (8U) +#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSTM_MT_Pos (12U) +#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_TSTM_HU_Pos (16U) +#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_TSTM_HT_Pos (20U) +#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TSTM_AMPM_Pos (22U) +#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_TSDT register *******************/ +#define ERTC_TSDT_DU_Pos (0U) +#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ +#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ +#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ +#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ +#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ + +#define ERTC_TSDT_DT_Pos (4U) +#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ +#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ +#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ + +#define ERTC_TSDT_MU_Pos (8U) +#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSDT_MT_Pos (12U) +#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ + +#define ERTC_TSDT_WK_Pos (13U) +#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ +#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ +#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for ERTC_TSSBS register ******************/ +#define ERTC_TSSBS_SBS_Pos (0U) +#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_SCAL register *******************/ +#define ERTC_SCAL_DEC_Pos (0U) +#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ +#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ +#define ERTC_SCAL_CAL16_Pos (13U) +#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ +#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ +#define ERTC_SCAL_CAL8_Pos (14U) +#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ +#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ +#define ERTC_SCAL_ADD_Pos (15U) +#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ +#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ + +/****************** Bit definition for ERTC_TAMP register *******************/ +#define ERTC_TAMP_TP1EN_Pos (0U) +#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ +#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ +#define ERTC_TAMP_TP1EDG_Pos (1U) +#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ +#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ +#define ERTC_TAMP_TPIEN_Pos (2U) +#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ +#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ +#define ERTC_TAMP_TPTSEN_Pos (7U) +#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ +#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ + +#define ERTC_TAMP_TPFREQ_Pos (8U) +#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ +#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ +#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ +#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ +#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ + +#define ERTC_TAMP_TPFLT_Pos (11U) +#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ +#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ +#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ +#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ + +#define ERTC_TAMP_TPPR_Pos (13U) +#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ +#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ +#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ +#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ + +#define ERTC_TAMP_TPPU_Pos (15U) +#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ +#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ +#define ERTC_TAMP_OUTTYPE_Pos (18U) +#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ +#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ + +/***************** Bit definition for ERTC_ALASBS register ******************/ +#define ERTC_ALASBS_SBS_Pos (0U) +#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ + +#define ERTC_ALASBS_SBSMSK_Pos (24U) +#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for ERTC_ALBSBS register ******************/ +#define ERTC_ALBSBS_SBS_Pos (0U) +#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ + +#define ERTC_ALBSBS_SBSMSK_Pos (24U) +#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ERTC_BPR1 register *******************/ +#define ERTC_BPR1_DT_Pos (0U) +#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ + +/****************** Bit definition for ERTC_BPR2 register *******************/ +#define ERTC_BPR2_DT_Pos (0U) +#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ + +/****************** Bit definition for ERTC_BPR3 register *******************/ +#define ERTC_BPR3_DT_Pos (0U) +#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ + +/****************** Bit definition for ERTC_BPR4 register *******************/ +#define ERTC_BPR4_DT_Pos (0U) +#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ + +/****************** Bit definition for ERTC_BPR5 register *******************/ +#define ERTC_BPR5_DT_Pos (0U) +#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ + +/****************** Bit definition for ERTC_BPR6 register *******************/ +#define ERTC_BPR6_DT_Pos (0U) +#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ + +/****************** Bit definition for ERTC_BPR7 register *******************/ +#define ERTC_BPR7_DT_Pos (0U) +#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ + +/****************** Bit definition for ERTC_BPR8 register *******************/ +#define ERTC_BPR8_DT_Pos (0U) +#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ + +/****************** Bit definition for ERTC_BPR9 register *******************/ +#define ERTC_BPR9_DT_Pos (0U) +#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ + +/****************** Bit definition for ERTC_BPR10 register ******************/ +#define ERTC_BPR10_DT_Pos (0U) +#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ + +/****************** Bit definition for ERTC_BPR11 register ******************/ +#define ERTC_BPR11_DT_Pos (0U) +#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ + +/****************** Bit definition for ERTC_BPR12 register ******************/ +#define ERTC_BPR12_DT_Pos (0U) +#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ + +/****************** Bit definition for ERTC_BPR13 register ******************/ +#define ERTC_BPR13_DT_Pos (0U) +#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ + +/****************** Bit definition for ERTC_BPR14 register ******************/ +#define ERTC_BPR14_DT_Pos (0U) +#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ + +/****************** Bit definition for ERTC_BPR15 register ******************/ +#define ERTC_BPR15_DT_Pos (0U) +#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ + +/****************** Bit definition for ERTC_BPR16 register ******************/ +#define ERTC_BPR16_DT_Pos (0U) +#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ + +/****************** Bit definition for ERTC_BPR17 register ******************/ +#define ERTC_BPR17_DT_Pos (0U) +#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ + +/****************** Bit definition for ERTC_BPR18 register ******************/ +#define ERTC_BPR18_DT_Pos (0U) +#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ + +/****************** Bit definition for ERTC_BPR19 register ******************/ +#define ERTC_BPR19_DT_Pos (0U) +#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ + +/****************** Bit definition for ERTC_BPR20 register ******************/ +#define ERTC_BPR20_DT_Pos (0U) +#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ + +/************************* Number of backup registers *************************/ +#define ERTC_BPR_NUMBER 0x000000014U + +/******************************************************************************/ +/* */ +/* Analog-to-digital converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ADC_STS register ********************/ +#define ADC_STS_VMOR_Pos (0U) +#define ADC_STS_VMOR_Msk (0x1U << ADC_STS_VMOR_Pos) /*!< 0x00000001 */ +#define ADC_STS_VMOR ADC_STS_VMOR_Msk /*!< Voltage monitoring out of range flag */ +#define ADC_STS_OCCC_Pos (1U) +#define ADC_STS_OCCC_Msk (0x1U << ADC_STS_OCCC_Pos) /*!< 0x00000002 */ +#define ADC_STS_OCCC ADC_STS_OCCC_Msk /*!< End of conversion flag */ +#define ADC_STS_PCCC_Pos (2U) +#define ADC_STS_PCCC_Msk (0x1U << ADC_STS_PCCC_Pos) /*!< 0x00000004 */ +#define ADC_STS_PCCC ADC_STS_PCCC_Msk /*!< Preempted channel end of conversion flag */ +#define ADC_STS_PCCS_Pos (3U) +#define ADC_STS_PCCS_Msk (0x1U << ADC_STS_PCCS_Pos) /*!< 0x00000008 */ +#define ADC_STS_PCCS ADC_STS_PCCS_Msk /*!< Preempted channel conversion start flag */ +#define ADC_STS_OCCS_Pos (4U) +#define ADC_STS_OCCS_Msk (0x1U << ADC_STS_OCCS_Pos) /*!< 0x00000010 */ +#define ADC_STS_OCCS ADC_STS_OCCS_Msk /*!< Ordinary channel conversion start flag */ + +/* Legacy defines */ +#define ADC_STS_OCCE (ADC_STS_OCCC) +#define ADC_STS_PCCE (ADC_STS_PCCC) + +/****************** Bit definition for ADC_CTRL1 register *******************/ +#define ADC_CTRL1_VMCSEL_Pos (0U) +#define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ +#define ADC_CTRL1_VMCSEL_0 (0x01U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTRL1_VMCSEL_1 (0x02U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTRL1_VMCSEL_2 (0x04U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL1_VMCSEL_3 (0x08U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTRL1_VMCSEL_4 (0x10U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000010 */ + +#define ADC_CTRL1_CCCIEN_Pos (5U) +#define ADC_CTRL1_CCCIEN_Msk (0x1U << ADC_CTRL1_CCCIEN_Pos) /*!< 0x00000020 */ +#define ADC_CTRL1_CCCIEN ADC_CTRL1_CCCIEN_Msk /*!< Channel conversion end interrupt enable */ +#define ADC_CTRL1_VMORIEN_Pos (6U) +#define ADC_CTRL1_VMORIEN_Msk (0x1U << ADC_CTRL1_VMORIEN_Pos) /*!< 0x00000040 */ +#define ADC_CTRL1_VMORIEN ADC_CTRL1_VMORIEN_Msk /*!< Voltage monitoring out of range interrupt enable */ +#define ADC_CTRL1_PCCCIEN_Pos (7U) +#define ADC_CTRL1_PCCCIEN_Msk (0x1U << ADC_CTRL1_PCCCIEN_Pos) /*!< 0x00000080 */ +#define ADC_CTRL1_PCCCIEN ADC_CTRL1_PCCCIEN_Msk /*!< Conversion end interrupt enable on Preempted channels */ +#define ADC_CTRL1_SQEN_Pos (8U) +#define ADC_CTRL1_SQEN_Msk (0x1U << ADC_CTRL1_SQEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL1_SQEN ADC_CTRL1_SQEN_Msk /*!< Sequence mode enable */ +#define ADC_CTRL1_VMSGEN_Pos (9U) +#define ADC_CTRL1_VMSGEN_Msk (0x1U << ADC_CTRL1_VMSGEN_Pos) /*!< 0x00000200 */ +#define ADC_CTRL1_VMSGEN ADC_CTRL1_VMSGEN_Msk /*!< Voltage monitoring enable on a single channel */ +#define ADC_CTRL1_PCAUTOEN_Pos (10U) +#define ADC_CTRL1_PCAUTOEN_Msk (0x1U << ADC_CTRL1_PCAUTOEN_Pos) /*!< 0x00000400 */ +#define ADC_CTRL1_PCAUTOEN ADC_CTRL1_PCAUTOEN_Msk /*!< Preempted group automatic conversion enable after ordinary group */ +#define ADC_CTRL1_OCPEN_Pos (11U) +#define ADC_CTRL1_OCPEN_Msk (0x1U << ADC_CTRL1_OCPEN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL1_OCPEN ADC_CTRL1_OCPEN_Msk /*!< Partitioned mode enable on ordinary channels */ +#define ADC_CTRL1_PCPEN_Pos (12U) +#define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ +#define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ + +#define ADC_CTRL1_OCPCNT_Pos (13U) +#define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ +#define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ +#define ADC_CTRL1_OCPCNT_0 (0x1U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00002000 */ +#define ADC_CTRL1_OCPCNT_1 (0x2U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00004000 */ +#define ADC_CTRL1_OCPCNT_2 (0x4U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00008000 */ + +#define ADC_CTRL1_PCVMEN_Pos (22U) +#define ADC_CTRL1_PCVMEN_Msk (0x1U << ADC_CTRL1_PCVMEN_Pos) /*!< 0x00400000 */ +#define ADC_CTRL1_PCVMEN ADC_CTRL1_PCVMEN_Msk /*!< Voltage monitoring enable on preempted channels */ +#define ADC_CTRL1_OCVMEN_Pos (23U) +#define ADC_CTRL1_OCVMEN_Msk (0x1U << ADC_CTRL1_OCVMEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL1_OCVMEN ADC_CTRL1_OCVMEN_Msk /*!< Voltage monitoring enable on ordinary channels */ + +/* Legacy defines */ +#define ADC_CTRL1_CCEIEN (ADC_CTRL1_CCCIEN) +#define ADC_CTRL1_PCCEIEN (ADC_CTRL1_PCCCIEN) + +/****************** Bit definition for ADC_CTRL2 register *******************/ +#define ADC_CTRL2_ADCEN_Pos (0U) +#define ADC_CTRL2_ADCEN_Msk (0x1U << ADC_CTRL2_ADCEN_Pos) /*!< 0x00000001 */ +#define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ +#define ADC_CTRL2_RPEN_Pos (1U) +#define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repition mode enable */ +#define ADC_CTRL2_ADCAL_Pos (2U) +#define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ +#define ADC_CTRL2_ADCALINIT_Pos (3U) +#define ADC_CTRL2_ADCALINIT_Msk (0x1U << ADC_CTRL2_ADCALINIT_Pos) /*!< 0x00000008 */ +#define ADC_CTRL2_ADCALINIT ADC_CTRL2_ADCALINIT_Msk /*!< Initialize A/D calibration */ +#define ADC_CTRL2_OCDMAEN_Pos (8U) +#define ADC_CTRL2_OCDMAEN_Msk (0x1U << ADC_CTRL2_OCDMAEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL2_OCDMAEN ADC_CTRL2_OCDMAEN_Msk /*!< DMA transfer enable of ordinary channels */ +#define ADC_CTRL2_DTALIGN_Pos (11U) +#define ADC_CTRL2_DTALIGN_Msk (0x1U << ADC_CTRL2_DTALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL2_DTALIGN ADC_CTRL2_DTALIGN_Msk /*!< Data alignment */ + +/*!< PCTESEL configuration */ +#define ADC_CTRL2_PCTESEL_Msk ((0x7U << 12) | (0x1U << 24)) /*!< 0x01007000 */ +#define ADC_CTRL2_PCTESEL ADC_CTRL2_PCTESEL_Msk /*!< PCTESEL[3:0] bits (Trigger event select for preempted channels conversion) */ +#define ADC_CTRL2_PCTESEL_0 (0x1U << 12) /*!< 0x00001000 */ +#define ADC_CTRL2_PCTESEL_1 (0x2U << 12) /*!< 0x00002000 */ +#define ADC_CTRL2_PCTESEL_2 (0x4U << 12) /*!< 0x00004000 */ +#define ADC_CTRL2_PCTESEL_3 (0x1U << 24) /*!< 0x01000000 */ + +#define ADC_CTRL2_PCTEN_Pos (15U) +#define ADC_CTRL2_PCTEN_Msk (0x1U << ADC_CTRL2_PCTEN_Pos) /*!< 0x00008000 */ +#define ADC_CTRL2_PCTEN ADC_CTRL2_PCTEN_Msk /*!< Trigger mode enable for preempted channels conversion */ + +/*!< OCTESEL configuration */ +#define ADC_CTRL2_OCTESEL_Msk ((0x7U << 17) | (0x1U << 25)) /*!< 0x020E0000 */ +#define ADC_CTRL2_OCTESEL ADC_CTRL2_OCTESEL_Msk /*!< OCTESEL[3:0] bits (Trigger event select for ordinary channels conversion) */ +#define ADC_CTRL2_OCTESEL_0 (0x1U << 17) /*!< 0x00020000 */ +#define ADC_CTRL2_OCTESEL_1 (0x2U << 17) /*!< 0x00040000 */ +#define ADC_CTRL2_OCTESEL_2 (0x4U << 17) /*!< 0x00080000 */ +#define ADC_CTRL2_OCTESEL_3 (0x1U << 25) /*!< 0x02000000 */ + +#define ADC_CTRL2_OCTEN_Pos (20U) +#define ADC_CTRL2_OCTEN_Msk (0x1U << ADC_CTRL2_OCTEN_Pos) /*!< 0x00100000 */ +#define ADC_CTRL2_OCTEN ADC_CTRL2_OCTEN_Msk /*!< Trigger mode enable for ordinary channels conversion */ +#define ADC_CTRL2_PCSWTRG_Pos (21U) +#define ADC_CTRL2_PCSWTRG_Msk (0x1U << ADC_CTRL2_PCSWTRG_Pos) /*!< 0x00200000 */ +#define ADC_CTRL2_PCSWTRG ADC_CTRL2_PCSWTRG_Msk /*!< Conversion of preempted channels triggered by software */ +#define ADC_CTRL2_OCSWTRG_Pos (22U) +#define ADC_CTRL2_OCSWTRG_Msk (0x1U << ADC_CTRL2_OCSWTRG_Pos) /*!< 0x00400000 */ +#define ADC_CTRL2_OCSWTRG ADC_CTRL2_OCSWTRG_Msk /*!< Conversion of ordinary channels triggered by software */ +#define ADC_CTRL2_ITSRVEN_Pos (23U) +#define ADC_CTRL2_ITSRVEN_Msk (0x1U << ADC_CTRL2_ITSRVEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ + +/******************* Bit definition for ADC_SPT1 register *******************/ +#define ADC_SPT1_CSPT10_Pos (0U) +#define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ +#define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ +#define ADC_SPT1_CSPT10_0 (0x1U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000001 */ +#define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ +#define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ + +#define ADC_SPT1_CSPT11_Pos (3U) +#define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ +#define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ +#define ADC_SPT1_CSPT11_0 (0x1U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000008 */ +#define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ +#define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ + +#define ADC_SPT1_CSPT12_Pos (6U) +#define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ +#define ADC_SPT1_CSPT12_0 (0x1U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000040 */ +#define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ +#define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ + +#define ADC_SPT1_CSPT13_Pos (9U) +#define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ +#define ADC_SPT1_CSPT13_0 (0x1U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000200 */ +#define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ +#define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ + +#define ADC_SPT1_CSPT14_Pos (12U) +#define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ +#define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ +#define ADC_SPT1_CSPT14_0 (0x1U << ADC_SPT1_CSPT14_Pos) /*!< 0x00001000 */ +#define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ +#define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ + +#define ADC_SPT1_CSPT15_Pos (15U) +#define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ +#define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ +#define ADC_SPT1_CSPT15_0 (0x1U << ADC_SPT1_CSPT15_Pos) /*!< 0x00008000 */ +#define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ +#define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ + +#define ADC_SPT1_CSPT16_Pos (18U) +#define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ +#define ADC_SPT1_CSPT16_0 (0x1U << ADC_SPT1_CSPT16_Pos) /*!< 0x00040000 */ +#define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ +#define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ + +#define ADC_SPT1_CSPT17_Pos (21U) +#define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ +#define ADC_SPT1_CSPT17_0 (0x1U << ADC_SPT1_CSPT17_Pos) /*!< 0x00200000 */ +#define ADC_SPT1_CSPT17_1 (0x2U << ADC_SPT1_CSPT17_Pos) /*!< 0x00400000 */ +#define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SPT2 register *******************/ +#define ADC_SPT2_CSPT0_Pos (0U) +#define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ +#define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ +#define ADC_SPT2_CSPT0_0 (0x1U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000001 */ +#define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ +#define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ + +#define ADC_SPT2_CSPT1_Pos (3U) +#define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ +#define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ +#define ADC_SPT2_CSPT1_0 (0x1U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000008 */ +#define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ +#define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ + +#define ADC_SPT2_CSPT2_Pos (6U) +#define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ +#define ADC_SPT2_CSPT2_0 (0x1U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000040 */ +#define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ +#define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ + +#define ADC_SPT2_CSPT3_Pos (9U) +#define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ +#define ADC_SPT2_CSPT3_0 (0x1U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000200 */ +#define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ +#define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ + +#define ADC_SPT2_CSPT4_Pos (12U) +#define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ +#define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ +#define ADC_SPT2_CSPT4_0 (0x1U << ADC_SPT2_CSPT4_Pos) /*!< 0x00001000 */ +#define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ +#define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ + +#define ADC_SPT2_CSPT5_Pos (15U) +#define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ +#define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ +#define ADC_SPT2_CSPT5_0 (0x1U << ADC_SPT2_CSPT5_Pos) /*!< 0x00008000 */ +#define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ +#define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ + +#define ADC_SPT2_CSPT6_Pos (18U) +#define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ +#define ADC_SPT2_CSPT6_0 (0x1U << ADC_SPT2_CSPT6_Pos) /*!< 0x00040000 */ +#define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ +#define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ + +#define ADC_SPT2_CSPT7_Pos (21U) +#define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ +#define ADC_SPT2_CSPT7_0 (0x1U << ADC_SPT2_CSPT7_Pos) /*!< 0x00200000 */ +#define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ +#define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ + +#define ADC_SPT2_CSPT8_Pos (24U) +#define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ +#define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ +#define ADC_SPT2_CSPT8_0 (0x1U << ADC_SPT2_CSPT8_Pos) /*!< 0x01000000 */ +#define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ +#define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ + +#define ADC_SPT2_CSPT9_Pos (27U) +#define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ +#define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ +#define ADC_SPT2_CSPT9_0 (0x1U << ADC_SPT2_CSPT9_Pos) /*!< 0x08000000 */ +#define ADC_SPT2_CSPT9_1 (0x2U << ADC_SPT2_CSPT9_Pos) /*!< 0x10000000 */ +#define ADC_SPT2_CSPT9_2 (0x4U << ADC_SPT2_CSPT9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_PCDTO1 register ******************/ +#define ADC_PCDTO1_PCDTO1_Pos (0U) +#define ADC_PCDTO1_PCDTO1_Msk (0xFFFU << ADC_PCDTO1_PCDTO1_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO1_PCDTO1 ADC_PCDTO1_PCDTO1_Msk /*!< Data offset for Preempted channel 1 */ + +/****************** Bit definition for ADC_PCDTO2 register ******************/ +#define ADC_PCDTO2_PCDTO2_Pos (0U) +#define ADC_PCDTO2_PCDTO2_Msk (0xFFFU << ADC_PCDTO2_PCDTO2_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO2_PCDTO2 ADC_PCDTO2_PCDTO2_Msk /*!< Data offset for Preempted channel 2 */ + +/****************** Bit definition for ADC_PCDTO3 register ******************/ +#define ADC_PCDTO3_PCDTO3_Pos (0U) +#define ADC_PCDTO3_PCDTO3_Msk (0xFFFU << ADC_PCDTO3_PCDTO3_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO3_PCDTO3 ADC_PCDTO3_PCDTO3_Msk /*!< Data offset for Preempted channel 3 */ + +/****************** Bit definition for ADC_PCDTO4 register ******************/ +#define ADC_PCDTO4_PCDTO4_Pos (0U) +#define ADC_PCDTO4_PCDTO4_Msk (0xFFFU << ADC_PCDTO4_PCDTO4_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO4_PCDTO4 ADC_PCDTO4_PCDTO4_Msk /*!< Data offset for Preempted channel 4 */ + +/******************* Bit definition for ADC_VMHB register ********************/ +#define ADC_VMHB_VMHB_Pos (0U) +#define ADC_VMHB_VMHB_Msk (0xFFFU << ADC_VMHB_VMHB_Pos) /*!< 0x00000FFF */ +#define ADC_VMHB_VMHB ADC_VMHB_VMHB_Msk /*!< Voltage monitoring high boundary */ + +/******************* Bit definition for ADC_VMLB register ********************/ +#define ADC_VMLB_VMLB_Pos (0U) +#define ADC_VMLB_VMLB_Msk (0xFFFU << ADC_VMLB_VMLB_Pos) /*!< 0x00000FFF */ +#define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ + +/******************* Bit definition for ADC_OSQ1 register *******************/ +#define ADC_OSQ1_OSN13_Pos (0U) +#define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ +#define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN13_0 (0x01U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000001 */ +#define ADC_OSQ1_OSN13_1 (0x02U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000002 */ +#define ADC_OSQ1_OSN13_2 (0x04U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000004 */ +#define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ +#define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ1_OSN14_Pos (5U) +#define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN14_0 (0x01U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000020 */ +#define ADC_OSQ1_OSN14_1 (0x02U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000040 */ +#define ADC_OSQ1_OSN14_2 (0x04U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000080 */ +#define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ +#define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ1_OSN15_Pos (10U) +#define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN15_0 (0x01U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000400 */ +#define ADC_OSQ1_OSN15_1 (0x02U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000800 */ +#define ADC_OSQ1_OSN15_2 (0x04U << ADC_OSQ1_OSN15_Pos) /*!< 0x00001000 */ +#define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ +#define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ1_OSN16_Pos (15U) +#define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN16_0 (0x01U << ADC_OSQ1_OSN16_Pos) /*!< 0x00008000 */ +#define ADC_OSQ1_OSN16_1 (0x02U << ADC_OSQ1_OSN16_Pos) /*!< 0x00010000 */ +#define ADC_OSQ1_OSN16_2 (0x04U << ADC_OSQ1_OSN16_Pos) /*!< 0x00020000 */ +#define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ +#define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ1_OCLEN_Pos (20U) +#define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ +#define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ +#define ADC_OSQ1_OCLEN_0 (0x1U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00100000 */ +#define ADC_OSQ1_OCLEN_1 (0x2U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00200000 */ +#define ADC_OSQ1_OCLEN_2 (0x4U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00400000 */ +#define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_OSQ2 register *******************/ +#define ADC_OSQ2_OSN7_Pos (0U) +#define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ +#define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN7_0 (0x01U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000001 */ +#define ADC_OSQ2_OSN7_1 (0x02U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000002 */ +#define ADC_OSQ2_OSN7_2 (0x04U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000004 */ +#define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ +#define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ2_OSN8_Pos (5U) +#define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN8_0 (0x01U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000020 */ +#define ADC_OSQ2_OSN8_1 (0x02U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000040 */ +#define ADC_OSQ2_OSN8_2 (0x04U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000080 */ +#define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ +#define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ2_OSN9_Pos (10U) +#define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN9_0 (0x01U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000400 */ +#define ADC_OSQ2_OSN9_1 (0x02U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000800 */ +#define ADC_OSQ2_OSN9_2 (0x04U << ADC_OSQ2_OSN9_Pos) /*!< 0x00001000 */ +#define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ +#define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ2_OSN10_Pos (15U) +#define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN10_0 (0x01U << ADC_OSQ2_OSN10_Pos) /*!< 0x00008000 */ +#define ADC_OSQ2_OSN10_1 (0x02U << ADC_OSQ2_OSN10_Pos) /*!< 0x00010000 */ +#define ADC_OSQ2_OSN10_2 (0x04U << ADC_OSQ2_OSN10_Pos) /*!< 0x00020000 */ +#define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ +#define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ2_OSN11_Pos (20U) +#define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN11_0 (0x01U << ADC_OSQ2_OSN11_Pos) /*!< 0x00100000 */ +#define ADC_OSQ2_OSN11_1 (0x02U << ADC_OSQ2_OSN11_Pos) /*!< 0x00200000 */ +#define ADC_OSQ2_OSN11_2 (0x04U << ADC_OSQ2_OSN11_Pos) /*!< 0x00400000 */ +#define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ +#define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ + +#define ADC_OSQ2_OSN12_Pos (25U) +#define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN12_0 (0x01U << ADC_OSQ2_OSN12_Pos) /*!< 0x02000000 */ +#define ADC_OSQ2_OSN12_1 (0x02U << ADC_OSQ2_OSN12_Pos) /*!< 0x04000000 */ +#define ADC_OSQ2_OSN12_2 (0x04U << ADC_OSQ2_OSN12_Pos) /*!< 0x08000000 */ +#define ADC_OSQ2_OSN12_3 (0x08U << ADC_OSQ2_OSN12_Pos) /*!< 0x10000000 */ +#define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_OSQ3 register *******************/ +#define ADC_OSQ3_OSN1_Pos (0U) +#define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ +#define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN1_0 (0x01U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000001 */ +#define ADC_OSQ3_OSN1_1 (0x02U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000002 */ +#define ADC_OSQ3_OSN1_2 (0x04U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000004 */ +#define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ +#define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ3_OSN2_Pos (5U) +#define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN2_0 (0x01U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000020 */ +#define ADC_OSQ3_OSN2_1 (0x02U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000040 */ +#define ADC_OSQ3_OSN2_2 (0x04U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000080 */ +#define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ +#define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ3_OSN3_Pos (10U) +#define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN3_0 (0x01U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000400 */ +#define ADC_OSQ3_OSN3_1 (0x02U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000800 */ +#define ADC_OSQ3_OSN3_2 (0x04U << ADC_OSQ3_OSN3_Pos) /*!< 0x00001000 */ +#define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ +#define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ3_OSN4_Pos (15U) +#define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN4_0 (0x01U << ADC_OSQ3_OSN4_Pos) /*!< 0x00008000 */ +#define ADC_OSQ3_OSN4_1 (0x02U << ADC_OSQ3_OSN4_Pos) /*!< 0x00010000 */ +#define ADC_OSQ3_OSN4_2 (0x04U << ADC_OSQ3_OSN4_Pos) /*!< 0x00020000 */ +#define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ +#define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ3_OSN5_Pos (20U) +#define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN5_0 (0x01U << ADC_OSQ3_OSN5_Pos) /*!< 0x00100000 */ +#define ADC_OSQ3_OSN5_1 (0x02U << ADC_OSQ3_OSN5_Pos) /*!< 0x00200000 */ +#define ADC_OSQ3_OSN5_2 (0x04U << ADC_OSQ3_OSN5_Pos) /*!< 0x00400000 */ +#define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ +#define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ + +#define ADC_OSQ3_OSN6_Pos (25U) +#define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN6_0 (0x01U << ADC_OSQ3_OSN6_Pos) /*!< 0x02000000 */ +#define ADC_OSQ3_OSN6_1 (0x02U << ADC_OSQ3_OSN6_Pos) /*!< 0x04000000 */ +#define ADC_OSQ3_OSN6_2 (0x04U << ADC_OSQ3_OSN6_Pos) /*!< 0x08000000 */ +#define ADC_OSQ3_OSN6_3 (0x08U << ADC_OSQ3_OSN6_Pos) /*!< 0x10000000 */ +#define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_PSQ register ********************/ +#define ADC_PSQ_PSN1_Pos (0U) +#define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ +#define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ +#define ADC_PSQ_PSN1_0 (0x01U << ADC_PSQ_PSN1_Pos) /*!< 0x00000001 */ +#define ADC_PSQ_PSN1_1 (0x02U << ADC_PSQ_PSN1_Pos) /*!< 0x00000002 */ +#define ADC_PSQ_PSN1_2 (0x04U << ADC_PSQ_PSN1_Pos) /*!< 0x00000004 */ +#define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ +#define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ + +#define ADC_PSQ_PSN2_Pos (5U) +#define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ +#define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ +#define ADC_PSQ_PSN2_0 (0x01U << ADC_PSQ_PSN2_Pos) /*!< 0x00000020 */ +#define ADC_PSQ_PSN2_1 (0x02U << ADC_PSQ_PSN2_Pos) /*!< 0x00000040 */ +#define ADC_PSQ_PSN2_2 (0x04U << ADC_PSQ_PSN2_Pos) /*!< 0x00000080 */ +#define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ +#define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ + +#define ADC_PSQ_PSN3_Pos (10U) +#define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ +#define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ +#define ADC_PSQ_PSN3_0 (0x01U << ADC_PSQ_PSN3_Pos) /*!< 0x00000400 */ +#define ADC_PSQ_PSN3_1 (0x02U << ADC_PSQ_PSN3_Pos) /*!< 0x00000800 */ +#define ADC_PSQ_PSN3_2 (0x04U << ADC_PSQ_PSN3_Pos) /*!< 0x00001000 */ +#define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ +#define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ + +#define ADC_PSQ_PSN4_Pos (15U) +#define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ +#define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ +#define ADC_PSQ_PSN4_0 (0x01U << ADC_PSQ_PSN4_Pos) /*!< 0x00008000 */ +#define ADC_PSQ_PSN4_1 (0x02U << ADC_PSQ_PSN4_Pos) /*!< 0x00010000 */ +#define ADC_PSQ_PSN4_2 (0x04U << ADC_PSQ_PSN4_Pos) /*!< 0x00020000 */ +#define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ +#define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ + +#define ADC_PSQ_PCLEN_Pos (20U) +#define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ +#define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ +#define ADC_PSQ_PCLEN_0 (0x1U << ADC_PSQ_PCLEN_Pos) /*!< 0x00100000 */ +#define ADC_PSQ_PCLEN_1 (0x2U << ADC_PSQ_PCLEN_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_PDT1 register *******************/ +#define ADC_PDT1_PDT1_Pos (0U) +#define ADC_PDT1_PDT1_Msk (0xFFFFU << ADC_PDT1_PDT1_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT1_PDT1 ADC_PDT1_PDT1_Msk /*!< Conversion data from preempted channel 1 */ + +/******************* Bit definition for ADC_PDT2 register *******************/ +#define ADC_PDT2_PDT2_Pos (0U) +#define ADC_PDT2_PDT2_Msk (0xFFFFU << ADC_PDT2_PDT2_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT2_PDT2 ADC_PDT2_PDT2_Msk /*!< Conversion data from preempted channel 2 */ + +/******************* Bit definition for ADC_PDT3 register *******************/ +#define ADC_PDT3_PDT3_Pos (0U) +#define ADC_PDT3_PDT3_Msk (0xFFFFU << ADC_PDT3_PDT3_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT3_PDT3 ADC_PDT3_PDT3_Msk /*!< Conversion data from preempted channel 3 */ + +/******************* Bit definition for ADC_PDT4 register *******************/ +#define ADC_PDT4_PDT4_Pos (0U) +#define ADC_PDT4_PDT4_Msk (0xFFFFU << ADC_PDT4_PDT4_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT4_PDT4 ADC_PDT4_PDT4_Msk /*!< Conversion data from preempted channel 4 */ + +/******************* Bit definition for ADC_ODT register ********************/ +#define ADC_ODT_ODT_Pos (0U) +#define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ +#define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ +#define ADC_ODT_ADC2ODT_Pos (16U) +#define ADC_ODT_ADC2ODT_Msk (0xFFFFU << ADC_ODT_ADC2ODT_Pos) /*!< 0xFFFF0000 */ +#define ADC_ODT_ADC2ODT ADC_ODT_ADC2ODT_Msk /*!< ADC2 conversion data of ordinary channel */ + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN) */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/****************** Bit definition for CAN_MCTRL register *******************/ +#define CAN_MCTRL_FZEN_Pos (0U) +#define CAN_MCTRL_FZEN_Msk (0x1U << CAN_MCTRL_FZEN_Pos) /*!< 0x00000001 */ +#define CAN_MCTRL_FZEN CAN_MCTRL_FZEN_Msk /*!< Freeze mode enable */ +#define CAN_MCTRL_DZEN_Pos (1U) +#define CAN_MCTRL_DZEN_Msk (0x1U << CAN_MCTRL_DZEN_Pos) /*!< 0x00000002 */ +#define CAN_MCTRL_DZEN CAN_MCTRL_DZEN_Msk /*!< Doze mode enable */ +#define CAN_MCTRL_MMSSR_Pos (2U) +#define CAN_MCTRL_MMSSR_Msk (0x1U << CAN_MCTRL_MMSSR_Pos) /*!< 0x00000004 */ +#define CAN_MCTRL_MMSSR CAN_MCTRL_MMSSR_Msk /*!< Multiple message transmit sequence rule */ +#define CAN_MCTRL_MDRSEL_Pos (3U) +#define CAN_MCTRL_MDRSEL_Msk (0x1U << CAN_MCTRL_MDRSEL_Pos) /*!< 0x00000008 */ +#define CAN_MCTRL_MDRSEL CAN_MCTRL_MDRSEL_Msk /*!< Message discard rule select when overflow */ +#define CAN_MCTRL_PRSFEN_Pos (4U) +#define CAN_MCTRL_PRSFEN_Msk (0x1U << CAN_MCTRL_PRSFEN_Pos) /*!< 0x00000010 */ +#define CAN_MCTRL_PRSFEN CAN_MCTRL_PRSFEN_Msk /*!< Prohibit retransmission enable when sending fails enable */ +#define CAN_MCTRL_AEDEN_Pos (5U) +#define CAN_MCTRL_AEDEN_Msk (0x1U << CAN_MCTRL_AEDEN_Pos) /*!< 0x00000020 */ +#define CAN_MCTRL_AEDEN CAN_MCTRL_AEDEN_Msk /*!< Automatic exit doze mode enable */ +#define CAN_MCTRL_AEBOEN_Pos (6U) +#define CAN_MCTRL_AEBOEN_Msk (0x1U << CAN_MCTRL_AEBOEN_Pos) /*!< 0x00000040 */ +#define CAN_MCTRL_AEBOEN CAN_MCTRL_AEBOEN_Msk /*!< Automatic exit bus-off enable */ +#define CAN_MCTRL_TTCEN_Pos (7U) +#define CAN_MCTRL_TTCEN_Msk (0x1U << CAN_MCTRL_TTCEN_Pos) /*!< 0x00000080 */ +#define CAN_MCTRL_TTCEN CAN_MCTRL_TTCEN_Msk /*!< Time triggered communication mode enable */ +#define CAN_MCTRL_SPRST_Pos (15U) +#define CAN_MCTRL_SPRST_Msk (0x1U << CAN_MCTRL_SPRST_Pos) /*!< 0x00008000 */ +#define CAN_MCTRL_SPRST CAN_MCTRL_SPRST_Msk /*!< Software partial reset */ +#define CAN_MCTRL_PTD_Pos (16U) +#define CAN_MCTRL_PTD_Msk (0x1U << CAN_MCTRL_PTD_Pos) /*!< 0x00010000 */ +#define CAN_MCTRL_PTD CAN_MCTRL_PTD_Msk /*!< Prohibit trans when debug */ + +/******************* Bit definition for CAN_MSTS register *******************/ +#define CAN_MSTS_FZC_Pos (0U) +#define CAN_MSTS_FZC_Msk (0x1U << CAN_MSTS_FZC_Pos) /*!< 0x00000001 */ +#define CAN_MSTS_FZC CAN_MSTS_FZC_Msk /*!< Freeze mode confirm */ +#define CAN_MSTS_DZC_Pos (1U) +#define CAN_MSTS_DZC_Msk (0x1U << CAN_MSTS_DZC_Pos) /*!< 0x00000002 */ +#define CAN_MSTS_DZC CAN_MSTS_DZC_Msk /*!< Doze mode acknowledge */ +#define CAN_MSTS_EOIF_Pos (2U) +#define CAN_MSTS_EOIF_Msk (0x1U << CAN_MSTS_EOIF_Pos) /*!< 0x00000004 */ +#define CAN_MSTS_EOIF CAN_MSTS_EOIF_Msk /*!< Error occur interrupt flag */ +#define CAN_MSTS_QDZIF_Pos (3U) +#define CAN_MSTS_QDZIF_Msk (0x1U << CAN_MSTS_QDZIF_Pos) /*!< 0x00000008 */ +#define CAN_MSTS_QDZIF CAN_MSTS_QDZIF_Msk /*!< Exit doze mode interrupt flag */ +#define CAN_MSTS_EDZIF_Pos (4U) +#define CAN_MSTS_EDZIF_Msk (0x1U << CAN_MSTS_EDZIF_Pos) /*!< 0x00000010 */ +#define CAN_MSTS_EDZIF CAN_MSTS_EDZIF_Msk /*!< Enter doze mode interrupt flag */ +#define CAN_MSTS_CUSS_Pos (8U) +#define CAN_MSTS_CUSS_Msk (0x1U << CAN_MSTS_CUSS_Pos) /*!< 0x00000100 */ +#define CAN_MSTS_CUSS CAN_MSTS_CUSS_Msk /*!< Current transmit status */ +#define CAN_MSTS_CURS_Pos (9U) +#define CAN_MSTS_CURS_Msk (0x1U << CAN_MSTS_CURS_Pos) /*!< 0x00000200 */ +#define CAN_MSTS_CURS CAN_MSTS_CURS_Msk /*!< Current receive status */ +#define CAN_MSTS_LSAMPRX_Pos (10U) +#define CAN_MSTS_LSAMPRX_Msk (0x1U << CAN_MSTS_LSAMPRX_Pos) /*!< 0x00000400 */ +#define CAN_MSTS_LSAMPRX CAN_MSTS_LSAMPRX_Msk /*!< Last sample level on RX pin */ +#define CAN_MSTS_REALRX_Pos (11U) +#define CAN_MSTS_REALRX_Msk (0x1U << CAN_MSTS_REALRX_Pos) /*!< 0x00000800 */ +#define CAN_MSTS_REALRX CAN_MSTS_REALRX_Msk /*!< Real time level on RX pin */ + +/******************* Bit definition for CAN_TSTS register *******************/ +#define CAN_TSTS_TM0TCF_Pos (0U) +#define CAN_TSTS_TM0TCF_Msk (0x1U << CAN_TSTS_TM0TCF_Pos) /*!< 0x00000001 */ +#define CAN_TSTS_TM0TCF CAN_TSTS_TM0TCF_Msk /*!< Transmit mailbox 0 transmission completed flag */ +#define CAN_TSTS_TM0TSF_Pos (1U) +#define CAN_TSTS_TM0TSF_Msk (0x1U << CAN_TSTS_TM0TSF_Pos) /*!< 0x00000002 */ +#define CAN_TSTS_TM0TSF CAN_TSTS_TM0TSF_Msk /*!< Transmit mailbox 0 transmission success flag */ +#define CAN_TSTS_TM0ALF_Pos (2U) +#define CAN_TSTS_TM0ALF_Msk (0x1U << CAN_TSTS_TM0ALF_Pos) /*!< 0x00000004 */ +#define CAN_TSTS_TM0ALF CAN_TSTS_TM0ALF_Msk /*!< Transmit mailbox 0 arbitration lost flag */ +#define CAN_TSTS_TM0TEF_Pos (3U) +#define CAN_TSTS_TM0TEF_Msk (0x1U << CAN_TSTS_TM0TEF_Pos) /*!< 0x00000008 */ +#define CAN_TSTS_TM0TEF CAN_TSTS_TM0TEF_Msk /*!< Transmit mailbox 0 transmission error flag */ +#define CAN_TSTS_TM0CT_Pos (7U) +#define CAN_TSTS_TM0CT_Msk (0x1U << CAN_TSTS_TM0CT_Pos) /*!< 0x00000080 */ +#define CAN_TSTS_TM0CT CAN_TSTS_TM0CT_Msk /*!< Transmit mailbox 0 cancel transmit */ +#define CAN_TSTS_TM1TCF_Pos (8U) +#define CAN_TSTS_TM1TCF_Msk (0x1U << CAN_TSTS_TM1TCF_Pos) /*!< 0x00000100 */ +#define CAN_TSTS_TM1TCF CAN_TSTS_TM1TCF_Msk /*!< Transmit mailbox 1 transmission completed flag */ +#define CAN_TSTS_TM1TSF_Pos (9U) +#define CAN_TSTS_TM1TSF_Msk (0x1U << CAN_TSTS_TM1TSF_Pos) /*!< 0x00000200 */ +#define CAN_TSTS_TM1TSF CAN_TSTS_TM1TSF_Msk /*!< Transmit mailbox 1 transmission success flag */ +#define CAN_TSTS_TM1ALF_Pos (10U) +#define CAN_TSTS_TM1ALF_Msk (0x1U << CAN_TSTS_TM1ALF_Pos) /*!< 0x00000400 */ +#define CAN_TSTS_TM1ALF CAN_TSTS_TM1ALF_Msk /*!< Transmit mailbox 1 arbitration lost flag */ +#define CAN_TSTS_TM1TEF_Pos (11U) +#define CAN_TSTS_TM1TEF_Msk (0x1U << CAN_TSTS_TM1TEF_Pos) /*!< 0x00000800 */ +#define CAN_TSTS_TM1TEF CAN_TSTS_TM1TEF_Msk /*!< Transmit mailbox 1 transmission error flag */ +#define CAN_TSTS_TM1CT_Pos (15U) +#define CAN_TSTS_TM1CT_Msk (0x1U << CAN_TSTS_TM1CT_Pos) /*!< 0x00008000 */ +#define CAN_TSTS_TM1CT CAN_TSTS_TM1CT_Msk /*!< Transmit mailbox 1 cancel transmit */ +#define CAN_TSTS_TM2TCF_Pos (16U) +#define CAN_TSTS_TM2TCF_Msk (0x1U << CAN_TSTS_TM2TCF_Pos) /*!< 0x00010000 */ +#define CAN_TSTS_TM2TCF CAN_TSTS_TM2TCF_Msk /*!< Transmit mailbox 2 transmission completed flag */ +#define CAN_TSTS_TM2TSF_Pos (17U) +#define CAN_TSTS_TM2TSF_Msk (0x1U << CAN_TSTS_TM2TSF_Pos) /*!< 0x00020000 */ +#define CAN_TSTS_TM2TSF CAN_TSTS_TM2TSF_Msk /*!< Transmit mailbox 2 transmission success flag */ +#define CAN_TSTS_TM2ALF_Pos (18U) +#define CAN_TSTS_TM2ALF_Msk (0x1U << CAN_TSTS_TM2ALF_Pos) /*!< 0x00040000 */ +#define CAN_TSTS_TM2ALF CAN_TSTS_TM2ALF_Msk /*!< Transmit mailbox 2 arbitration lost flag */ +#define CAN_TSTS_TM2TEF_Pos (19U) +#define CAN_TSTS_TM2TEF_Msk (0x1U << CAN_TSTS_TM2TEF_Pos) /*!< 0x00080000 */ +#define CAN_TSTS_TM2TEF CAN_TSTS_TM2TEF_Msk /*!< Transmit mailbox 2 transmission error flag */ +#define CAN_TSTS_TM2CT_Pos (23U) +#define CAN_TSTS_TM2CT_Msk (0x1U << CAN_TSTS_TM2CT_Pos) /*!< 0x00800000 */ +#define CAN_TSTS_TM2CT CAN_TSTS_TM2CT_Msk /*!< Transmit mailbox 2 cancel transmit */ +#define CAN_TSTS_TMNR_Pos (24U) +#define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ +#define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ + +#define CAN_TSTS_TMEF_Pos (26U) +#define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ +#define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ +#define CAN_TSTS_TM0EF_Pos (26U) +#define CAN_TSTS_TM0EF_Msk (0x1U << CAN_TSTS_TM0EF_Pos) /*!< 0x04000000 */ +#define CAN_TSTS_TM0EF CAN_TSTS_TM0EF_Msk /*!< Transmit mailbox 0 empty flag */ +#define CAN_TSTS_TM1EF_Pos (27U) +#define CAN_TSTS_TM1EF_Msk (0x1U << CAN_TSTS_TM1EF_Pos) /*!< 0x08000000 */ +#define CAN_TSTS_TM1EF CAN_TSTS_TM1EF_Msk /*!< Transmit mailbox 1 empty flag */ +#define CAN_TSTS_TM2EF_Pos (28U) +#define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ +#define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ + +#define CAN_TSTS_TMLPF_Pos (29U) +#define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ +#define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ +#define CAN_TSTS_TM0LPF_Pos (29U) +#define CAN_TSTS_TM0LPF_Msk (0x1U << CAN_TSTS_TM0LPF_Pos) /*!< 0x20000000 */ +#define CAN_TSTS_TM0LPF CAN_TSTS_TM0LPF_Msk /*!< Transmit mailbox 0 lowest priority flag */ +#define CAN_TSTS_TM1LPF_Pos (30U) +#define CAN_TSTS_TM1LPF_Msk (0x1U << CAN_TSTS_TM1LPF_Pos) /*!< 0x40000000 */ +#define CAN_TSTS_TM1LPF CAN_TSTS_TM1LPF_Msk /*!< Transmit mailbox 1 lowest priority flag */ +#define CAN_TSTS_TM2LPF_Pos (31U) +#define CAN_TSTS_TM2LPF_Msk (0x1U << CAN_TSTS_TM2LPF_Pos) /*!< 0x80000000 */ +#define CAN_TSTS_TM2LPF CAN_TSTS_TM2LPF_Msk /*!< Transmit mailbox 2 lowest priority flag */ + +/******************* Bit definition for CAN_RF0 register ********************/ +#define CAN_RF0_RF0MN_Pos (0U) +#define CAN_RF0_RF0MN_Msk (0x3U << CAN_RF0_RF0MN_Pos) /*!< 0x00000003 */ +#define CAN_RF0_RF0MN CAN_RF0_RF0MN_Msk /*!< Receive FIFO 0 message num */ +#define CAN_RF0_RF0FF_Pos (3U) +#define CAN_RF0_RF0FF_Msk (0x1U << CAN_RF0_RF0FF_Pos) /*!< 0x00000008 */ +#define CAN_RF0_RF0FF CAN_RF0_RF0FF_Msk /*!< Receive FIFO 0 full flag */ +#define CAN_RF0_RF0OF_Pos (4U) +#define CAN_RF0_RF0OF_Msk (0x1U << CAN_RF0_RF0OF_Pos) /*!< 0x00000010 */ +#define CAN_RF0_RF0OF CAN_RF0_RF0OF_Msk /*!< Receive FIFO 0 overflow flag */ +#define CAN_RF0_RF0R_Pos (5U) +#define CAN_RF0_RF0R_Msk (0x1U << CAN_RF0_RF0R_Pos) /*!< 0x00000020 */ +#define CAN_RF0_RF0R CAN_RF0_RF0R_Msk /*!< Receive FIFO 0 release */ + +/******************* Bit definition for CAN_RF1 register ********************/ +#define CAN_RF1_RF1MN_Pos (0U) +#define CAN_RF1_RF1MN_Msk (0x3U << CAN_RF1_RF1MN_Pos) /*!< 0x00000003 */ +#define CAN_RF1_RF1MN CAN_RF1_RF1MN_Msk /*!< Receive FIFO 1 message num */ +#define CAN_RF1_RF1FF_Pos (3U) +#define CAN_RF1_RF1FF_Msk (0x1U << CAN_RF1_RF1FF_Pos) /*!< 0x00000008 */ +#define CAN_RF1_RF1FF CAN_RF1_RF1FF_Msk /*!< Receive FIFO 1 full flag */ +#define CAN_RF1_RF1OF_Pos (4U) +#define CAN_RF1_RF1OF_Msk (0x1U << CAN_RF1_RF1OF_Pos) /*!< 0x00000010 */ +#define CAN_RF1_RF1OF CAN_RF1_RF1OF_Msk /*!< Receive FIFO 1 overflow flag */ +#define CAN_RF1_RF1R_Pos (5U) +#define CAN_RF1_RF1R_Msk (0x1U << CAN_RF1_RF1R_Pos) /*!< 0x00000020 */ +#define CAN_RF1_RF1R CAN_RF1_RF1R_Msk /*!< Receive FIFO 1 release */ + +/****************** Bit definition for CAN_INTEN register *******************/ +#define CAN_INTEN_TCIEN_Pos (0U) +#define CAN_INTEN_TCIEN_Msk (0x1U << CAN_INTEN_TCIEN_Pos) /*!< 0x00000001 */ +#define CAN_INTEN_TCIEN CAN_INTEN_TCIEN_Msk /*!< Transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RF0MIEN_Pos (1U) +#define CAN_INTEN_RF0MIEN_Msk (0x1U << CAN_INTEN_RF0MIEN_Pos) /*!< 0x00000002 */ +#define CAN_INTEN_RF0MIEN CAN_INTEN_RF0MIEN_Msk /*!< FIFO 0 receive message interrupt enable */ +#define CAN_INTEN_RF0FIEN_Pos (2U) +#define CAN_INTEN_RF0FIEN_Msk (0x1U << CAN_INTEN_RF0FIEN_Pos) /*!< 0x00000004 */ +#define CAN_INTEN_RF0FIEN CAN_INTEN_RF0FIEN_Msk /*!< Receive FIFO 0 full interrupt enable */ +#define CAN_INTEN_RF0OIEN_Pos (3U) +#define CAN_INTEN_RF0OIEN_Msk (0x1U << CAN_INTEN_RF0OIEN_Pos) /*!< 0x00000008 */ +#define CAN_INTEN_RF0OIEN CAN_INTEN_RF0OIEN_Msk /*!< Receive FIFO 0 overflow interrupt enable */ +#define CAN_INTEN_RF1MIEN_Pos (4U) +#define CAN_INTEN_RF1MIEN_Msk (0x1U << CAN_INTEN_RF1MIEN_Pos) /*!< 0x00000010 */ +#define CAN_INTEN_RF1MIEN CAN_INTEN_RF1MIEN_Msk /*!< FIFO 1 receive message interrupt enable */ +#define CAN_INTEN_RF1FIEN_Pos (5U) +#define CAN_INTEN_RF1FIEN_Msk (0x1U << CAN_INTEN_RF1FIEN_Pos) /*!< 0x00000020 */ +#define CAN_INTEN_RF1FIEN CAN_INTEN_RF1FIEN_Msk /*!< Receive FIFO 1 full interrupt enable */ +#define CAN_INTEN_RF1OIEN_Pos (6U) +#define CAN_INTEN_RF1OIEN_Msk (0x1U << CAN_INTEN_RF1OIEN_Pos) /*!< 0x00000040 */ +#define CAN_INTEN_RF1OIEN CAN_INTEN_RF1OIEN_Msk /*!< Receive FIFO 1 overflow interrupt enable */ +#define CAN_INTEN_EAIEN_Pos (8U) +#define CAN_INTEN_EAIEN_Msk (0x1U << CAN_INTEN_EAIEN_Pos) /*!< 0x00000100 */ +#define CAN_INTEN_EAIEN CAN_INTEN_EAIEN_Msk /*!< Error active interrupt enable */ +#define CAN_INTEN_EPIEN_Pos (9U) +#define CAN_INTEN_EPIEN_Msk (0x1U << CAN_INTEN_EPIEN_Pos) /*!< 0x00000200 */ +#define CAN_INTEN_EPIEN CAN_INTEN_EPIEN_Msk /*!< Error passive interrupt enable */ +#define CAN_INTEN_BOIEN_Pos (10U) +#define CAN_INTEN_BOIEN_Msk (0x1U << CAN_INTEN_BOIEN_Pos) /*!< 0x00000400 */ +#define CAN_INTEN_BOIEN CAN_INTEN_BOIEN_Msk /*!< Bus-off interrupt enable */ +#define CAN_INTEN_ETRIEN_Pos (11U) +#define CAN_INTEN_ETRIEN_Msk (0x1U << CAN_INTEN_ETRIEN_Pos) /*!< 0x00000800 */ +#define CAN_INTEN_ETRIEN CAN_INTEN_ETRIEN_Msk /*!< Error type record interrupt enable */ +#define CAN_INTEN_EOIEN_Pos (15U) +#define CAN_INTEN_EOIEN_Msk (0x1U << CAN_INTEN_EOIEN_Pos) /*!< 0x00008000 */ +#define CAN_INTEN_EOIEN CAN_INTEN_EOIEN_Msk /*!< Error occur interrupt enable */ +#define CAN_INTEN_QDZIEN_Pos (16U) +#define CAN_INTEN_QDZIEN_Msk (0x1U << CAN_INTEN_QDZIEN_Pos) /*!< 0x00010000 */ +#define CAN_INTEN_QDZIEN CAN_INTEN_QDZIEN_Msk /*!< Quit doze mode interrupt enable */ +#define CAN_INTEN_EDZIEN_Pos (17U) +#define CAN_INTEN_EDZIEN_Msk (0x1U << CAN_INTEN_EDZIEN_Pos) /*!< 0x00020000 */ +#define CAN_INTEN_EDZIEN CAN_INTEN_EDZIEN_Msk /*!< Enter doze mode interrupt enable */ + +/******************* Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EAF_Pos (0U) +#define CAN_ESTS_EAF_Msk (0x1U << CAN_ESTS_EAF_Pos) /*!< 0x00000001 */ +#define CAN_ESTS_EAF CAN_ESTS_EAF_Msk /*!< Error active flag */ +#define CAN_ESTS_EPF_Pos (1U) +#define CAN_ESTS_EPF_Msk (0x1U << CAN_ESTS_EPF_Pos) /*!< 0x00000002 */ +#define CAN_ESTS_EPF CAN_ESTS_EPF_Msk /*!< Error passive flag */ +#define CAN_ESTS_BOF_Pos (2U) +#define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ +#define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ + +#define CAN_ESTS_ETR_Pos (4U) +#define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ +#define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ +#define CAN_ESTS_ETR_0 (0x1U << CAN_ESTS_ETR_Pos) /*!< 0x00000010 */ +#define CAN_ESTS_ETR_1 (0x2U << CAN_ESTS_ETR_Pos) /*!< 0x00000020 */ +#define CAN_ESTS_ETR_2 (0x4U << CAN_ESTS_ETR_Pos) /*!< 0x00000040 */ + +#define CAN_ESTS_TEC_Pos (16U) +#define CAN_ESTS_TEC_Msk (0xFFU << CAN_ESTS_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESTS_TEC CAN_ESTS_TEC_Msk /*!< Transmit error counter */ +#define CAN_ESTS_REC_Pos (24U) +#define CAN_ESTS_REC_Msk (0xFFU << CAN_ESTS_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESTS_REC CAN_ESTS_REC_Msk /*!< Receive error counter */ + +/******************* Bit definition for CAN_BTMG register ********************/ +#define CAN_BTMG_BRDIV_Pos (0U) +#define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ +#define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ + +#define CAN_BTMG_BTS1_Pos (16U) +#define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ +#define CAN_BTMG_BTS1_0 (0x1U << CAN_BTMG_BTS1_Pos) /*!< 0x00010000 */ +#define CAN_BTMG_BTS1_1 (0x2U << CAN_BTMG_BTS1_Pos) /*!< 0x00020000 */ +#define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ +#define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ + +#define CAN_BTMG_BTS2_Pos (20U) +#define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ +#define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ +#define CAN_BTMG_BTS2_0 (0x1U << CAN_BTMG_BTS2_Pos) /*!< 0x00100000 */ +#define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ +#define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ + +#define CAN_BTMG_RSAW_Pos (24U) +#define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ +#define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ +#define CAN_BTMG_RSAW_0 (0x1U << CAN_BTMG_RSAW_Pos) /*!< 0x01000000 */ +#define CAN_BTMG_RSAW_1 (0x2U << CAN_BTMG_RSAW_Pos) /*!< 0x02000000 */ + +#define CAN_BTMG_LBEN_Pos (30U) +#define CAN_BTMG_LBEN_Msk (0x1U << CAN_BTMG_LBEN_Pos) /*!< 0x40000000 */ +#define CAN_BTMG_LBEN CAN_BTMG_LBEN_Msk /*!< Loop back mode */ +#define CAN_BTMG_LOEN_Pos (31U) +#define CAN_BTMG_LOEN_Msk (0x1U << CAN_BTMG_LOEN_Pos) /*!< 0x80000000 */ +#define CAN_BTMG_LOEN CAN_BTMG_LOEN_Msk /*!< Listen-Only mode */ + +/*!< Mailbox registers */ +/******************* Bit definition for CAN_TMI0 register *******************/ +#define CAN_TMI0_TMSR_Pos (0U) +#define CAN_TMI0_TMSR_Msk (0x1U << CAN_TMI0_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI0_TMSR CAN_TMI0_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI0_TMFRSEL_Pos (1U) +#define CAN_TMI0_TMFRSEL_Msk (0x1U << CAN_TMI0_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI0_TMFRSEL CAN_TMI0_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI0_TMIDSEL_Pos (2U) +#define CAN_TMI0_TMIDSEL_Msk (0x1U << CAN_TMI0_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI0_TMIDSEL CAN_TMI0_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI0_TMEID_Pos (3U) +#define CAN_TMI0_TMEID_Msk (0x3FFFFU << CAN_TMI0_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI0_TMEID CAN_TMI0_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI0_TMSID_Pos (21U) +#define CAN_TMI0_TMSID_Msk (0x7FFU << CAN_TMI0_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI0_TMSID CAN_TMI0_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC0 register *******************/ +#define CAN_TMC0_TMDTBL_Pos (0U) +#define CAN_TMC0_TMDTBL_Msk (0xFU << CAN_TMC0_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC0_TMDTBL CAN_TMC0_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC0_TMTSTEN_Pos (8U) +#define CAN_TMC0_TMTSTEN_Msk (0x1U << CAN_TMC0_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC0_TMTSTEN CAN_TMC0_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC0_TMTS_Pos (16U) +#define CAN_TMC0_TMTS_Msk (0xFFFFU << CAN_TMC0_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC0_TMTS CAN_TMC0_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL0 register ******************/ +#define CAN_TMDTL0_TMDT0_Pos (0U) +#define CAN_TMDTL0_TMDT0_Msk (0xFFU << CAN_TMDTL0_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL0_TMDT0 CAN_TMDTL0_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL0_TMDT1_Pos (8U) +#define CAN_TMDTL0_TMDT1_Msk (0xFFU << CAN_TMDTL0_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL0_TMDT1 CAN_TMDTL0_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL0_TMDT2_Pos (16U) +#define CAN_TMDTL0_TMDT2_Msk (0xFFU << CAN_TMDTL0_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL0_TMDT2 CAN_TMDTL0_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL0_TMDT3_Pos (24U) +#define CAN_TMDTL0_TMDT3_Msk (0xFFU << CAN_TMDTL0_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL0_TMDT3 CAN_TMDTL0_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH0 register ******************/ +#define CAN_TMDTH0_TMDT4_Pos (0U) +#define CAN_TMDTH0_TMDT4_Msk (0xFFU << CAN_TMDTH0_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH0_TMDT4 CAN_TMDTH0_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH0_TMDT5_Pos (8U) +#define CAN_TMDTH0_TMDT5_Msk (0xFFU << CAN_TMDTH0_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH0_TMDT5 CAN_TMDTH0_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH0_TMDT6_Pos (16U) +#define CAN_TMDTH0_TMDT6_Msk (0xFFU << CAN_TMDTH0_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH0_TMDT6 CAN_TMDTH0_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH0_TMDT7_Pos (24U) +#define CAN_TMDTH0_TMDT7_Msk (0xFFU << CAN_TMDTH0_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH0_TMDT7 CAN_TMDTH0_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI1 register *******************/ +#define CAN_TMI1_TMSR_Pos (0U) +#define CAN_TMI1_TMSR_Msk (0x1U << CAN_TMI1_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI1_TMSR CAN_TMI1_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI1_TMFRSEL_Pos (1U) +#define CAN_TMI1_TMFRSEL_Msk (0x1U << CAN_TMI1_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI1_TMFRSEL CAN_TMI1_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI1_TMIDSEL_Pos (2U) +#define CAN_TMI1_TMIDSEL_Msk (0x1U << CAN_TMI1_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI1_TMIDSEL CAN_TMI1_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI1_TMEID_Pos (3U) +#define CAN_TMI1_TMEID_Msk (0x3FFFFU << CAN_TMI1_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI1_TMEID CAN_TMI1_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI1_TMSID_Pos (21U) +#define CAN_TMI1_TMSID_Msk (0x7FFU << CAN_TMI1_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI1_TMSID CAN_TMI1_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC1 register *******************/ +#define CAN_TMC1_TMDTBL_Pos (0U) +#define CAN_TMC1_TMDTBL_Msk (0xFU << CAN_TMC1_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC1_TMDTBL CAN_TMC1_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC1_TMTSTEN_Pos (8U) +#define CAN_TMC1_TMTSTEN_Msk (0x1U << CAN_TMC1_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC1_TMTSTEN CAN_TMC1_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC1_TMTS_Pos (16U) +#define CAN_TMC1_TMTS_Msk (0xFFFFU << CAN_TMC1_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC1_TMTS CAN_TMC1_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL1 register ******************/ +#define CAN_TMDTL1_TMDT0_Pos (0U) +#define CAN_TMDTL1_TMDT0_Msk (0xFFU << CAN_TMDTL1_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL1_TMDT0 CAN_TMDTL1_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL1_TMDT1_Pos (8U) +#define CAN_TMDTL1_TMDT1_Msk (0xFFU << CAN_TMDTL1_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL1_TMDT1 CAN_TMDTL1_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL1_TMDT2_Pos (16U) +#define CAN_TMDTL1_TMDT2_Msk (0xFFU << CAN_TMDTL1_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL1_TMDT2 CAN_TMDTL1_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL1_TMDT3_Pos (24U) +#define CAN_TMDTL1_TMDT3_Msk (0xFFU << CAN_TMDTL1_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL1_TMDT3 CAN_TMDTL1_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH1 register ******************/ +#define CAN_TMDTH1_TMDT4_Pos (0U) +#define CAN_TMDTH1_TMDT4_Msk (0xFFU << CAN_TMDTH1_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH1_TMDT4 CAN_TMDTH1_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH1_TMDT5_Pos (8U) +#define CAN_TMDTH1_TMDT5_Msk (0xFFU << CAN_TMDTH1_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH1_TMDT5 CAN_TMDTH1_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH1_TMDT6_Pos (16U) +#define CAN_TMDTH1_TMDT6_Msk (0xFFU << CAN_TMDTH1_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH1_TMDT6 CAN_TMDTH1_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH1_TMDT7_Pos (24U) +#define CAN_TMDTH1_TMDT7_Msk (0xFFU << CAN_TMDTH1_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH1_TMDT7 CAN_TMDTH1_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI2 register *******************/ +#define CAN_TMI2_TMSR_Pos (0U) +#define CAN_TMI2_TMSR_Msk (0x1U << CAN_TMI2_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI2_TMSR CAN_TMI2_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI2_TMFRSEL_Pos (1U) +#define CAN_TMI2_TMFRSEL_Msk (0x1U << CAN_TMI2_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI2_TMFRSEL CAN_TMI2_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI2_TMIDSEL_Pos (2U) +#define CAN_TMI2_TMIDSEL_Msk (0x1U << CAN_TMI2_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI2_TMIDSEL CAN_TMI2_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI2_TMEID_Pos (3U) +#define CAN_TMI2_TMEID_Msk (0x3FFFFU << CAN_TMI2_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI2_TMEID CAN_TMI2_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI2_TMSID_Pos (21U) +#define CAN_TMI2_TMSID_Msk (0x7FFU << CAN_TMI2_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI2_TMSID CAN_TMI2_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC2 register *******************/ +#define CAN_TMC2_TMDTBL_Pos (0U) +#define CAN_TMC2_TMDTBL_Msk (0xFU << CAN_TMC2_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC2_TMDTBL CAN_TMC2_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC2_TMTSTEN_Pos (8U) +#define CAN_TMC2_TMTSTEN_Msk (0x1U << CAN_TMC2_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC2_TMTSTEN CAN_TMC2_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC2_TMTS_Pos (16U) +#define CAN_TMC2_TMTS_Msk (0xFFFFU << CAN_TMC2_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC2_TMTS CAN_TMC2_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL2 register ******************/ +#define CAN_TMDTL2_TMDT0_Pos (0U) +#define CAN_TMDTL2_TMDT0_Msk (0xFFU << CAN_TMDTL2_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL2_TMDT0 CAN_TMDTL2_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL2_TMDT1_Pos (8U) +#define CAN_TMDTL2_TMDT1_Msk (0xFFU << CAN_TMDTL2_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL2_TMDT1 CAN_TMDTL2_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL2_TMDT2_Pos (16U) +#define CAN_TMDTL2_TMDT2_Msk (0xFFU << CAN_TMDTL2_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL2_TMDT2 CAN_TMDTL2_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL2_TMDT3_Pos (24U) +#define CAN_TMDTL2_TMDT3_Msk (0xFFU << CAN_TMDTL2_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL2_TMDT3 CAN_TMDTL2_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH2 register ******************/ +#define CAN_TMDTH2_TMDT4_Pos (0U) +#define CAN_TMDTH2_TMDT4_Msk (0xFFU << CAN_TMDTH2_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH2_TMDT4 CAN_TMDTH2_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH2_TMDT5_Pos (8U) +#define CAN_TMDTH2_TMDT5_Msk (0xFFU << CAN_TMDTH2_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH2_TMDT5 CAN_TMDTH2_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH2_TMDT6_Pos (16U) +#define CAN_TMDTH2_TMDT6_Msk (0xFFU << CAN_TMDTH2_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH2_TMDT6 CAN_TMDTH2_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH2_TMDT7_Pos (24U) +#define CAN_TMDTH2_TMDT7_Msk (0xFFU << CAN_TMDTH2_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH2_TMDT7 CAN_TMDTH2_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_RFI0 register *******************/ +#define CAN_RFI0_RFFRI_Pos (1U) +#define CAN_RFI0_RFFRI_Msk (0x1U << CAN_RFI0_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI0_RFFRI CAN_RFI0_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI0_RFIDI_Pos (2U) +#define CAN_RFI0_RFIDI_Msk (0x1U << CAN_RFI0_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI0_RFIDI CAN_RFI0_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI0_RFEID_Pos (3U) +#define CAN_RFI0_RFEID_Msk (0x3FFFFU << CAN_RFI0_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI0_RFEID CAN_RFI0_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI0_RFSID_Pos (21U) +#define CAN_RFI0_RFSID_Msk (0x7FFU << CAN_RFI0_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI0_RFSID CAN_RFI0_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC0 register *******************/ +#define CAN_RFC0_RFDTL_Pos (0U) +#define CAN_RFC0_RFDTL_Msk (0xFU << CAN_RFC0_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC0_RFDTL CAN_RFC0_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC0_RFFMN_Pos (8U) +#define CAN_RFC0_RFFMN_Msk (0xFFU << CAN_RFC0_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC0_RFFMN CAN_RFC0_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC0_RFTS_Pos (16U) +#define CAN_RFC0_RFTS_Msk (0xFFFFU << CAN_RFC0_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC0_RFTS CAN_RFC0_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL0 register ******************/ +#define CAN_RFDTL0_RFDT0_Pos (0U) +#define CAN_RFDTL0_RFDT0_Msk (0xFFU << CAN_RFDTL0_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL0_RFDT0 CAN_RFDTL0_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL0_RFDT1_Pos (8U) +#define CAN_RFDTL0_RFDT1_Msk (0xFFU << CAN_RFDTL0_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL0_RFDT1 CAN_RFDTL0_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL0_RFDT2_Pos (16U) +#define CAN_RFDTL0_RFDT2_Msk (0xFFU << CAN_RFDTL0_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL0_RFDT2 CAN_RFDTL0_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL0_RFDT3_Pos (24U) +#define CAN_RFDTL0_RFDT3_Msk (0xFFU << CAN_RFDTL0_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL0_RFDT3 CAN_RFDTL0_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH0 register ******************/ +#define CAN_RFDTH0_RFDT4_Pos (0U) +#define CAN_RFDTH0_RFDT4_Msk (0xFFU << CAN_RFDTH0_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH0_RFDT4 CAN_RFDTH0_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH0_RFDT5_Pos (8U) +#define CAN_RFDTH0_RFDT5_Msk (0xFFU << CAN_RFDTH0_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH0_RFDT5 CAN_RFDTH0_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH0_RFDT6_Pos (16U) +#define CAN_RFDTH0_RFDT6_Msk (0xFFU << CAN_RFDTH0_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH0_RFDT6 CAN_RFDTH0_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH0_RFDT7_Pos (24U) +#define CAN_RFDTH0_RFDT7_Msk (0xFFU << CAN_RFDTH0_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH0_RFDT7 CAN_RFDTH0_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/******************* Bit definition for CAN_RFI1 register *******************/ +#define CAN_RFI1_RFFRI_Pos (1U) +#define CAN_RFI1_RFFRI_Msk (0x1U << CAN_RFI1_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI1_RFFRI CAN_RFI1_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI1_RFIDI_Pos (2U) +#define CAN_RFI1_RFIDI_Msk (0x1U << CAN_RFI1_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI1_RFIDI CAN_RFI1_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI1_RFEID_Pos (3U) +#define CAN_RFI1_RFEID_Msk (0x3FFFFU << CAN_RFI1_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI1_RFEID CAN_RFI1_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI1_RFSID_Pos (21U) +#define CAN_RFI1_RFSID_Msk (0x7FFU << CAN_RFI1_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI1_RFSID CAN_RFI1_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC1 register *******************/ +#define CAN_RFC1_RFDTL_Pos (0U) +#define CAN_RFC1_RFDTL_Msk (0xFU << CAN_RFC1_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC1_RFDTL CAN_RFC1_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC1_RFFMN_Pos (8U) +#define CAN_RFC1_RFFMN_Msk (0xFFU << CAN_RFC1_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC1_RFFMN CAN_RFC1_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC1_RFTS_Pos (16U) +#define CAN_RFC1_RFTS_Msk (0xFFFFU << CAN_RFC1_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC1_RFTS CAN_RFC1_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL1 register ******************/ +#define CAN_RFDTL1_RFDT0_Pos (0U) +#define CAN_RFDTL1_RFDT0_Msk (0xFFU << CAN_RFDTL1_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL1_RFDT0 CAN_RFDTL1_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL1_RFDT1_Pos (8U) +#define CAN_RFDTL1_RFDT1_Msk (0xFFU << CAN_RFDTL1_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL1_RFDT1 CAN_RFDTL1_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL1_RFDT2_Pos (16U) +#define CAN_RFDTL1_RFDT2_Msk (0xFFU << CAN_RFDTL1_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL1_RFDT2 CAN_RFDTL1_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL1_RFDT3_Pos (24U) +#define CAN_RFDTL1_RFDT3_Msk (0xFFU << CAN_RFDTL1_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL1_RFDT3 CAN_RFDTL1_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH1 register ******************/ +#define CAN_RFDTH1_RFDT4_Pos (0U) +#define CAN_RFDTH1_RFDT4_Msk (0xFFU << CAN_RFDTH1_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH1_RFDT4 CAN_RFDTH1_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH1_RFDT5_Pos (8U) +#define CAN_RFDTH1_RFDT5_Msk (0xFFU << CAN_RFDTH1_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH1_RFDT5 CAN_RFDTH1_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH1_RFDT6_Pos (16U) +#define CAN_RFDTH1_RFDT6_Msk (0xFFU << CAN_RFDTH1_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH1_RFDT6 CAN_RFDTH1_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH1_RFDT7_Pos (24U) +#define CAN_RFDTH1_RFDT7_Msk (0xFFU << CAN_RFDTH1_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH1_RFDT7 CAN_RFDTH1_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/*!< CAN filter registers */ +/****************** Bit definition for CAN_FCTRL register *******************/ +#define CAN_FCTRL_FCS_Pos (0U) +#define CAN_FCTRL_FCS_Msk (0x1U << CAN_FCTRL_FCS_Pos) /*!< 0x00000001 */ +#define CAN_FCTRL_FCS CAN_FCTRL_FCS_Msk /*!< Filter configuration switch */ + +/****************** Bit definition for CAN_FMCFG register *******************/ +#define CAN_FMCFG_FMSEL_Pos (0U) +#define CAN_FMCFG_FMSEL_Msk (0x3FFFU << CAN_FMCFG_FMSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FMCFG_FMSEL CAN_FMCFG_FMSEL_Msk /*!< Filter mode select */ +#define CAN_FMCFG_FMSEL0_Pos (0U) +#define CAN_FMCFG_FMSEL0_Msk (0x1U << CAN_FMCFG_FMSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FMCFG_FMSEL0 CAN_FMCFG_FMSEL0_Msk /*!< Filter mode select for filter 0 */ +#define CAN_FMCFG_FMSEL1_Pos (1U) +#define CAN_FMCFG_FMSEL1_Msk (0x1U << CAN_FMCFG_FMSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FMCFG_FMSEL1 CAN_FMCFG_FMSEL1_Msk /*!< Filter mode select for filter 1 */ +#define CAN_FMCFG_FMSEL2_Pos (2U) +#define CAN_FMCFG_FMSEL2_Msk (0x1U << CAN_FMCFG_FMSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FMCFG_FMSEL2 CAN_FMCFG_FMSEL2_Msk /*!< Filter mode select for filter 2 */ +#define CAN_FMCFG_FMSEL3_Pos (3U) +#define CAN_FMCFG_FMSEL3_Msk (0x1U << CAN_FMCFG_FMSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FMCFG_FMSEL3 CAN_FMCFG_FMSEL3_Msk /*!< Filter mode select for filter 3 */ +#define CAN_FMCFG_FMSEL4_Pos (4U) +#define CAN_FMCFG_FMSEL4_Msk (0x1U << CAN_FMCFG_FMSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FMCFG_FMSEL4 CAN_FMCFG_FMSEL4_Msk /*!< Filter mode select for filter 4 */ +#define CAN_FMCFG_FMSEL5_Pos (5U) +#define CAN_FMCFG_FMSEL5_Msk (0x1U << CAN_FMCFG_FMSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FMCFG_FMSEL5 CAN_FMCFG_FMSEL5_Msk /*!< Filter mode select for filter 5 */ +#define CAN_FMCFG_FMSEL6_Pos (6U) +#define CAN_FMCFG_FMSEL6_Msk (0x1U << CAN_FMCFG_FMSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FMCFG_FMSEL6 CAN_FMCFG_FMSEL6_Msk /*!< Filter mode select for filter 6 */ +#define CAN_FMCFG_FMSEL7_Pos (7U) +#define CAN_FMCFG_FMSEL7_Msk (0x1U << CAN_FMCFG_FMSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FMCFG_FMSEL7 CAN_FMCFG_FMSEL7_Msk /*!< Filter mode select for filter 7 */ +#define CAN_FMCFG_FMSEL8_Pos (8U) +#define CAN_FMCFG_FMSEL8_Msk (0x1U << CAN_FMCFG_FMSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FMCFG_FMSEL8 CAN_FMCFG_FMSEL8_Msk /*!< Filter mode select for filter 8 */ +#define CAN_FMCFG_FMSEL9_Pos (9U) +#define CAN_FMCFG_FMSEL9_Msk (0x1U << CAN_FMCFG_FMSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FMCFG_FMSEL9 CAN_FMCFG_FMSEL9_Msk /*!< Filter mode select for filter 9 */ +#define CAN_FMCFG_FMSEL10_Pos (10U) +#define CAN_FMCFG_FMSEL10_Msk (0x1U << CAN_FMCFG_FMSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FMCFG_FMSEL10 CAN_FMCFG_FMSEL10_Msk /*!< Filter mode select for filter 10 */ +#define CAN_FMCFG_FMSEL11_Pos (11U) +#define CAN_FMCFG_FMSEL11_Msk (0x1U << CAN_FMCFG_FMSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FMCFG_FMSEL11 CAN_FMCFG_FMSEL11_Msk /*!< Filter mode select for filter 11 */ +#define CAN_FMCFG_FMSEL12_Pos (12U) +#define CAN_FMCFG_FMSEL12_Msk (0x1U << CAN_FMCFG_FMSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FMCFG_FMSEL12 CAN_FMCFG_FMSEL12_Msk /*!< Filter mode select for filter 12 */ +#define CAN_FMCFG_FMSEL13_Pos (13U) +#define CAN_FMCFG_FMSEL13_Msk (0x1U << CAN_FMCFG_FMSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FMCFG_FMSEL13 CAN_FMCFG_FMSEL13_Msk /*!< Filter mode select for filter 13 */ + +/****************** Bit definition for CAN_FBWCFG register ******************/ +#define CAN_FBWCFG_FBWSEL_Pos (0U) +#define CAN_FBWCFG_FBWSEL_Msk (0x3FFFU << CAN_FBWCFG_FBWSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FBWCFG_FBWSEL CAN_FBWCFG_FBWSEL_Msk /*!< Filter bit width select */ +#define CAN_FBWCFG_FBWSEL0_Pos (0U) +#define CAN_FBWCFG_FBWSEL0_Msk (0x1U << CAN_FBWCFG_FBWSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FBWCFG_FBWSEL0 CAN_FBWCFG_FBWSEL0_Msk /*!< Filter bit width select for filter 0 */ +#define CAN_FBWCFG_FBWSEL1_Pos (1U) +#define CAN_FBWCFG_FBWSEL1_Msk (0x1U << CAN_FBWCFG_FBWSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FBWCFG_FBWSEL1 CAN_FBWCFG_FBWSEL1_Msk /*!< Filter bit width select for filter 1 */ +#define CAN_FBWCFG_FBWSEL2_Pos (2U) +#define CAN_FBWCFG_FBWSEL2_Msk (0x1U << CAN_FBWCFG_FBWSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FBWCFG_FBWSEL2 CAN_FBWCFG_FBWSEL2_Msk /*!< Filter bit width select for filter 2 */ +#define CAN_FBWCFG_FBWSEL3_Pos (3U) +#define CAN_FBWCFG_FBWSEL3_Msk (0x1U << CAN_FBWCFG_FBWSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FBWCFG_FBWSEL3 CAN_FBWCFG_FBWSEL3_Msk /*!< Filter bit width select for filter 3 */ +#define CAN_FBWCFG_FBWSEL4_Pos (4U) +#define CAN_FBWCFG_FBWSEL4_Msk (0x1U << CAN_FBWCFG_FBWSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FBWCFG_FBWSEL4 CAN_FBWCFG_FBWSEL4_Msk /*!< Filter bit width select for filter 4 */ +#define CAN_FBWCFG_FBWSEL5_Pos (5U) +#define CAN_FBWCFG_FBWSEL5_Msk (0x1U << CAN_FBWCFG_FBWSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FBWCFG_FBWSEL5 CAN_FBWCFG_FBWSEL5_Msk /*!< Filter bit width select for filter 5 */ +#define CAN_FBWCFG_FBWSEL6_Pos (6U) +#define CAN_FBWCFG_FBWSEL6_Msk (0x1U << CAN_FBWCFG_FBWSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FBWCFG_FBWSEL6 CAN_FBWCFG_FBWSEL6_Msk /*!< Filter bit width select for filter 6 */ +#define CAN_FBWCFG_FBWSEL7_Pos (7U) +#define CAN_FBWCFG_FBWSEL7_Msk (0x1U << CAN_FBWCFG_FBWSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FBWCFG_FBWSEL7 CAN_FBWCFG_FBWSEL7_Msk /*!< Filter bit width select for filter 7 */ +#define CAN_FBWCFG_FBWSEL8_Pos (8U) +#define CAN_FBWCFG_FBWSEL8_Msk (0x1U << CAN_FBWCFG_FBWSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FBWCFG_FBWSEL8 CAN_FBWCFG_FBWSEL8_Msk /*!< Filter bit width select for filter 8 */ +#define CAN_FBWCFG_FBWSEL9_Pos (9U) +#define CAN_FBWCFG_FBWSEL9_Msk (0x1U << CAN_FBWCFG_FBWSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FBWCFG_FBWSEL9 CAN_FBWCFG_FBWSEL9_Msk /*!< Filter bit width select for filter 9 */ +#define CAN_FBWCFG_FBWSEL10_Pos (10U) +#define CAN_FBWCFG_FBWSEL10_Msk (0x1U << CAN_FBWCFG_FBWSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FBWCFG_FBWSEL10 CAN_FBWCFG_FBWSEL10_Msk /*!< Filter bit width select for filter 10 */ +#define CAN_FBWCFG_FBWSEL11_Pos (11U) +#define CAN_FBWCFG_FBWSEL11_Msk (0x1U << CAN_FBWCFG_FBWSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FBWCFG_FBWSEL11 CAN_FBWCFG_FBWSEL11_Msk /*!< Filter bit width select for filter 11 */ +#define CAN_FBWCFG_FBWSEL12_Pos (12U) +#define CAN_FBWCFG_FBWSEL12_Msk (0x1U << CAN_FBWCFG_FBWSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FBWCFG_FBWSEL12 CAN_FBWCFG_FBWSEL12_Msk /*!< Filter bit width select for filter 12 */ +#define CAN_FBWCFG_FBWSEL13_Pos (13U) +#define CAN_FBWCFG_FBWSEL13_Msk (0x1U << CAN_FBWCFG_FBWSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FBWCFG_FBWSEL13 CAN_FBWCFG_FBWSEL13_Msk /*!< Filter bit width select for filter 13 */ + +/******************* Bit definition for CAN_FRF register ********************/ +#define CAN_FRF_FRFSEL_Pos (0U) +#define CAN_FRF_FRFSEL_Msk (0x3FFFU << CAN_FRF_FRFSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FRF_FRFSEL CAN_FRF_FRFSEL_Msk /*!< Filter relation FIFO select */ +#define CAN_FRF_FRFSEL0_Pos (0U) +#define CAN_FRF_FRFSEL0_Msk (0x1U << CAN_FRF_FRFSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FRF_FRFSEL0 CAN_FRF_FRFSEL0_Msk /*!< Filter relation FIFO select for filter 0 */ +#define CAN_FRF_FRFSEL1_Pos (1U) +#define CAN_FRF_FRFSEL1_Msk (0x1U << CAN_FRF_FRFSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FRF_FRFSEL1 CAN_FRF_FRFSEL1_Msk /*!< Filter relation FIFO select for filter 1 */ +#define CAN_FRF_FRFSEL2_Pos (2U) +#define CAN_FRF_FRFSEL2_Msk (0x1U << CAN_FRF_FRFSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FRF_FRFSEL2 CAN_FRF_FRFSEL2_Msk /*!< Filter relation FIFO select for filter 2 */ +#define CAN_FRF_FRFSEL3_Pos (3U) +#define CAN_FRF_FRFSEL3_Msk (0x1U << CAN_FRF_FRFSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FRF_FRFSEL3 CAN_FRF_FRFSEL3_Msk /*!< Filter relation FIFO select for filter 3 */ +#define CAN_FRF_FRFSEL4_Pos (4U) +#define CAN_FRF_FRFSEL4_Msk (0x1U << CAN_FRF_FRFSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FRF_FRFSEL4 CAN_FRF_FRFSEL4_Msk /*!< Filter relation FIFO select for filter 4 */ +#define CAN_FRF_FRFSEL5_Pos (5U) +#define CAN_FRF_FRFSEL5_Msk (0x1U << CAN_FRF_FRFSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FRF_FRFSEL5 CAN_FRF_FRFSEL5_Msk /*!< Filter relation FIFO select for filter 5 */ +#define CAN_FRF_FRFSEL6_Pos (6U) +#define CAN_FRF_FRFSEL6_Msk (0x1U << CAN_FRF_FRFSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FRF_FRFSEL6 CAN_FRF_FRFSEL6_Msk /*!< Filter relation FIFO select for filter 6 */ +#define CAN_FRF_FRFSEL7_Pos (7U) +#define CAN_FRF_FRFSEL7_Msk (0x1U << CAN_FRF_FRFSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FRF_FRFSEL7 CAN_FRF_FRFSEL7_Msk /*!< Filter relation FIFO select for filter 7 */ +#define CAN_FRF_FRFSEL8_Pos (8U) +#define CAN_FRF_FRFSEL8_Msk (0x1U << CAN_FRF_FRFSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FRF_FRFSEL8 CAN_FRF_FRFSEL8_Msk /*!< Filter relation FIFO select for filter 8 */ +#define CAN_FRF_FRFSEL9_Pos (9U) +#define CAN_FRF_FRFSEL9_Msk (0x1U << CAN_FRF_FRFSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FRF_FRFSEL9 CAN_FRF_FRFSEL9_Msk /*!< Filter relation FIFO select for filter 9 */ +#define CAN_FRF_FRFSEL10_Pos (10U) +#define CAN_FRF_FRFSEL10_Msk (0x1U << CAN_FRF_FRFSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FRF_FRFSEL10 CAN_FRF_FRFSEL10_Msk /*!< Filter relation FIFO select for filter 10 */ +#define CAN_FRF_FRFSEL11_Pos (11U) +#define CAN_FRF_FRFSEL11_Msk (0x1U << CAN_FRF_FRFSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FRF_FRFSEL11 CAN_FRF_FRFSEL11_Msk /*!< Filter relation FIFO select for filter 11 */ +#define CAN_FRF_FRFSEL12_Pos (12U) +#define CAN_FRF_FRFSEL12_Msk (0x1U << CAN_FRF_FRFSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FRF_FRFSEL12 CAN_FRF_FRFSEL12_Msk /*!< Filter relation FIFO select for filter 12 */ +#define CAN_FRF_FRFSEL13_Pos (13U) +#define CAN_FRF_FRFSEL13_Msk (0x1U << CAN_FRF_FRFSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FRF_FRFSEL13 CAN_FRF_FRFSEL13_Msk /*!< Filter relation FIFO select for filter 13 */ + +/****************** Bit definition for CAN_FACFG register *******************/ +#define CAN_FACFG_FAEN_Pos (0U) +#define CAN_FACFG_FAEN_Msk (0x3FFFU << CAN_FACFG_FAEN_Pos) /*!< 0x00003FFF */ +#define CAN_FACFG_FAEN CAN_FACFG_FAEN_Msk /*!< Filter active enable */ +#define CAN_FACFG_FAEN0_Pos (0U) +#define CAN_FACFG_FAEN0_Msk (0x1U << CAN_FACFG_FAEN0_Pos) /*!< 0x00000001 */ +#define CAN_FACFG_FAEN0 CAN_FACFG_FAEN0_Msk /*!< Filter 0 active enable */ +#define CAN_FACFG_FAEN1_Pos (1U) +#define CAN_FACFG_FAEN1_Msk (0x1U << CAN_FACFG_FAEN1_Pos) /*!< 0x00000002 */ +#define CAN_FACFG_FAEN1 CAN_FACFG_FAEN1_Msk /*!< Filter 1 active enable */ +#define CAN_FACFG_FAEN2_Pos (2U) +#define CAN_FACFG_FAEN2_Msk (0x1U << CAN_FACFG_FAEN2_Pos) /*!< 0x00000004 */ +#define CAN_FACFG_FAEN2 CAN_FACFG_FAEN2_Msk /*!< Filter 2 active enable */ +#define CAN_FACFG_FAEN3_Pos (3U) +#define CAN_FACFG_FAEN3_Msk (0x1U << CAN_FACFG_FAEN3_Pos) /*!< 0x00000008 */ +#define CAN_FACFG_FAEN3 CAN_FACFG_FAEN3_Msk /*!< Filter 3 active enable */ +#define CAN_FACFG_FAEN4_Pos (4U) +#define CAN_FACFG_FAEN4_Msk (0x1U << CAN_FACFG_FAEN4_Pos) /*!< 0x00000010 */ +#define CAN_FACFG_FAEN4 CAN_FACFG_FAEN4_Msk /*!< Filter 4 active enable */ +#define CAN_FACFG_FAEN5_Pos (5U) +#define CAN_FACFG_FAEN5_Msk (0x1U << CAN_FACFG_FAEN5_Pos) /*!< 0x00000020 */ +#define CAN_FACFG_FAEN5 CAN_FACFG_FAEN5_Msk /*!< Filter 5 active enable */ +#define CAN_FACFG_FAEN6_Pos (6U) +#define CAN_FACFG_FAEN6_Msk (0x1U << CAN_FACFG_FAEN6_Pos) /*!< 0x00000040 */ +#define CAN_FACFG_FAEN6 CAN_FACFG_FAEN6_Msk /*!< Filter 6 active enable */ +#define CAN_FACFG_FAEN7_Pos (7U) +#define CAN_FACFG_FAEN7_Msk (0x1U << CAN_FACFG_FAEN7_Pos) /*!< 0x00000080 */ +#define CAN_FACFG_FAEN7 CAN_FACFG_FAEN7_Msk /*!< Filter 7 active enable */ +#define CAN_FACFG_FAEN8_Pos (8U) +#define CAN_FACFG_FAEN8_Msk (0x1U << CAN_FACFG_FAEN8_Pos) /*!< 0x00000100 */ +#define CAN_FACFG_FAEN8 CAN_FACFG_FAEN8_Msk /*!< Filter 8 active enable */ +#define CAN_FACFG_FAEN9_Pos (9U) +#define CAN_FACFG_FAEN9_Msk (0x1U << CAN_FACFG_FAEN9_Pos) /*!< 0x00000200 */ +#define CAN_FACFG_FAEN9 CAN_FACFG_FAEN9_Msk /*!< Filter 9 active enable */ +#define CAN_FACFG_FAEN10_Pos (10U) +#define CAN_FACFG_FAEN10_Msk (0x1U << CAN_FACFG_FAEN10_Pos) /*!< 0x00000400 */ +#define CAN_FACFG_FAEN10 CAN_FACFG_FAEN10_Msk /*!< Filter 10 active enable */ +#define CAN_FACFG_FAEN11_Pos (11U) +#define CAN_FACFG_FAEN11_Msk (0x1U << CAN_FACFG_FAEN11_Pos) /*!< 0x00000800 */ +#define CAN_FACFG_FAEN11 CAN_FACFG_FAEN11_Msk /*!< Filter 11 active enable */ +#define CAN_FACFG_FAEN12_Pos (12U) +#define CAN_FACFG_FAEN12_Msk (0x1U << CAN_FACFG_FAEN12_Pos) /*!< 0x00001000 */ +#define CAN_FACFG_FAEN12 CAN_FACFG_FAEN12_Msk /*!< Filter 12 active enable */ +#define CAN_FACFG_FAEN13_Pos (13U) +#define CAN_FACFG_FAEN13_Msk (0x1U << CAN_FACFG_FAEN13_Pos) /*!< 0x00002000 */ +#define CAN_FACFG_FAEN13 CAN_FACFG_FAEN13_Msk /*!< Filter 13 active enable */ + +/****************** Bit definition for CAN_F0FB1 register *******************/ +#define CAN_F0FB1_FFDB0_Pos (0U) +#define CAN_F0FB1_FFDB0_Msk (0x1U << CAN_F0FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB1_FFDB0 CAN_F0FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB1_FFDB1_Pos (1U) +#define CAN_F0FB1_FFDB1_Msk (0x1U << CAN_F0FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB1_FFDB1 CAN_F0FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB1_FFDB2_Pos (2U) +#define CAN_F0FB1_FFDB2_Msk (0x1U << CAN_F0FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB1_FFDB2 CAN_F0FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB1_FFDB3_Pos (3U) +#define CAN_F0FB1_FFDB3_Msk (0x1U << CAN_F0FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB1_FFDB3 CAN_F0FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB1_FFDB4_Pos (4U) +#define CAN_F0FB1_FFDB4_Msk (0x1U << CAN_F0FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB1_FFDB4 CAN_F0FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB1_FFDB5_Pos (5U) +#define CAN_F0FB1_FFDB5_Msk (0x1U << CAN_F0FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB1_FFDB5 CAN_F0FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB1_FFDB6_Pos (6U) +#define CAN_F0FB1_FFDB6_Msk (0x1U << CAN_F0FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB1_FFDB6 CAN_F0FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB1_FFDB7_Pos (7U) +#define CAN_F0FB1_FFDB7_Msk (0x1U << CAN_F0FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB1_FFDB7 CAN_F0FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB1_FFDB8_Pos (8U) +#define CAN_F0FB1_FFDB8_Msk (0x1U << CAN_F0FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB1_FFDB8 CAN_F0FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB1_FFDB9_Pos (9U) +#define CAN_F0FB1_FFDB9_Msk (0x1U << CAN_F0FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB1_FFDB9 CAN_F0FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB1_FFDB10_Pos (10U) +#define CAN_F0FB1_FFDB10_Msk (0x1U << CAN_F0FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB1_FFDB10 CAN_F0FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB1_FFDB11_Pos (11U) +#define CAN_F0FB1_FFDB11_Msk (0x1U << CAN_F0FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB1_FFDB11 CAN_F0FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB1_FFDB12_Pos (12U) +#define CAN_F0FB1_FFDB12_Msk (0x1U << CAN_F0FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB1_FFDB12 CAN_F0FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB1_FFDB13_Pos (13U) +#define CAN_F0FB1_FFDB13_Msk (0x1U << CAN_F0FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB1_FFDB13 CAN_F0FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB1_FFDB14_Pos (14U) +#define CAN_F0FB1_FFDB14_Msk (0x1U << CAN_F0FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB1_FFDB14 CAN_F0FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB1_FFDB15_Pos (15U) +#define CAN_F0FB1_FFDB15_Msk (0x1U << CAN_F0FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB1_FFDB15 CAN_F0FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB1_FFDB16_Pos (16U) +#define CAN_F0FB1_FFDB16_Msk (0x1U << CAN_F0FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB1_FFDB16 CAN_F0FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB1_FFDB17_Pos (17U) +#define CAN_F0FB1_FFDB17_Msk (0x1U << CAN_F0FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB1_FFDB17 CAN_F0FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB1_FFDB18_Pos (18U) +#define CAN_F0FB1_FFDB18_Msk (0x1U << CAN_F0FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB1_FFDB18 CAN_F0FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB1_FFDB19_Pos (19U) +#define CAN_F0FB1_FFDB19_Msk (0x1U << CAN_F0FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB1_FFDB19 CAN_F0FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB1_FFDB20_Pos (20U) +#define CAN_F0FB1_FFDB20_Msk (0x1U << CAN_F0FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB1_FFDB20 CAN_F0FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB1_FFDB21_Pos (21U) +#define CAN_F0FB1_FFDB21_Msk (0x1U << CAN_F0FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB1_FFDB21 CAN_F0FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB1_FFDB22_Pos (22U) +#define CAN_F0FB1_FFDB22_Msk (0x1U << CAN_F0FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB1_FFDB22 CAN_F0FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB1_FFDB23_Pos (23U) +#define CAN_F0FB1_FFDB23_Msk (0x1U << CAN_F0FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB1_FFDB23 CAN_F0FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB1_FFDB24_Pos (24U) +#define CAN_F0FB1_FFDB24_Msk (0x1U << CAN_F0FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB1_FFDB24 CAN_F0FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB1_FFDB25_Pos (25U) +#define CAN_F0FB1_FFDB25_Msk (0x1U << CAN_F0FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB1_FFDB25 CAN_F0FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB1_FFDB26_Pos (26U) +#define CAN_F0FB1_FFDB26_Msk (0x1U << CAN_F0FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB1_FFDB26 CAN_F0FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB1_FFDB27_Pos (27U) +#define CAN_F0FB1_FFDB27_Msk (0x1U << CAN_F0FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB1_FFDB27 CAN_F0FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB1_FFDB28_Pos (28U) +#define CAN_F0FB1_FFDB28_Msk (0x1U << CAN_F0FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB1_FFDB28 CAN_F0FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB1_FFDB29_Pos (29U) +#define CAN_F0FB1_FFDB29_Msk (0x1U << CAN_F0FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB1_FFDB29 CAN_F0FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB1_FFDB30_Pos (30U) +#define CAN_F0FB1_FFDB30_Msk (0x1U << CAN_F0FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB1_FFDB30 CAN_F0FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB1_FFDB31_Pos (31U) +#define CAN_F0FB1_FFDB31_Msk (0x1U << CAN_F0FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB1_FFDB31 CAN_F0FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB1 register *******************/ +#define CAN_F1FB1_FFDB0_Pos (0U) +#define CAN_F1FB1_FFDB0_Msk (0x1U << CAN_F1FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB1_FFDB0 CAN_F1FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB1_FFDB1_Pos (1U) +#define CAN_F1FB1_FFDB1_Msk (0x1U << CAN_F1FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB1_FFDB1 CAN_F1FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB1_FFDB2_Pos (2U) +#define CAN_F1FB1_FFDB2_Msk (0x1U << CAN_F1FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB1_FFDB2 CAN_F1FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB1_FFDB3_Pos (3U) +#define CAN_F1FB1_FFDB3_Msk (0x1U << CAN_F1FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB1_FFDB3 CAN_F1FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB1_FFDB4_Pos (4U) +#define CAN_F1FB1_FFDB4_Msk (0x1U << CAN_F1FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB1_FFDB4 CAN_F1FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB1_FFDB5_Pos (5U) +#define CAN_F1FB1_FFDB5_Msk (0x1U << CAN_F1FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB1_FFDB5 CAN_F1FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB1_FFDB6_Pos (6U) +#define CAN_F1FB1_FFDB6_Msk (0x1U << CAN_F1FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB1_FFDB6 CAN_F1FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB1_FFDB7_Pos (7U) +#define CAN_F1FB1_FFDB7_Msk (0x1U << CAN_F1FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB1_FFDB7 CAN_F1FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB1_FFDB8_Pos (8U) +#define CAN_F1FB1_FFDB8_Msk (0x1U << CAN_F1FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB1_FFDB8 CAN_F1FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB1_FFDB9_Pos (9U) +#define CAN_F1FB1_FFDB9_Msk (0x1U << CAN_F1FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB1_FFDB9 CAN_F1FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB1_FFDB10_Pos (10U) +#define CAN_F1FB1_FFDB10_Msk (0x1U << CAN_F1FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB1_FFDB10 CAN_F1FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB1_FFDB11_Pos (11U) +#define CAN_F1FB1_FFDB11_Msk (0x1U << CAN_F1FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB1_FFDB11 CAN_F1FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB1_FFDB12_Pos (12U) +#define CAN_F1FB1_FFDB12_Msk (0x1U << CAN_F1FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB1_FFDB12 CAN_F1FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB1_FFDB13_Pos (13U) +#define CAN_F1FB1_FFDB13_Msk (0x1U << CAN_F1FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB1_FFDB13 CAN_F1FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB1_FFDB14_Pos (14U) +#define CAN_F1FB1_FFDB14_Msk (0x1U << CAN_F1FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB1_FFDB14 CAN_F1FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB1_FFDB15_Pos (15U) +#define CAN_F1FB1_FFDB15_Msk (0x1U << CAN_F1FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB1_FFDB15 CAN_F1FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB1_FFDB16_Pos (16U) +#define CAN_F1FB1_FFDB16_Msk (0x1U << CAN_F1FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB1_FFDB16 CAN_F1FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB1_FFDB17_Pos (17U) +#define CAN_F1FB1_FFDB17_Msk (0x1U << CAN_F1FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB1_FFDB17 CAN_F1FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB1_FFDB18_Pos (18U) +#define CAN_F1FB1_FFDB18_Msk (0x1U << CAN_F1FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB1_FFDB18 CAN_F1FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB1_FFDB19_Pos (19U) +#define CAN_F1FB1_FFDB19_Msk (0x1U << CAN_F1FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB1_FFDB19 CAN_F1FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB1_FFDB20_Pos (20U) +#define CAN_F1FB1_FFDB20_Msk (0x1U << CAN_F1FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB1_FFDB20 CAN_F1FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB1_FFDB21_Pos (21U) +#define CAN_F1FB1_FFDB21_Msk (0x1U << CAN_F1FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB1_FFDB21 CAN_F1FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB1_FFDB22_Pos (22U) +#define CAN_F1FB1_FFDB22_Msk (0x1U << CAN_F1FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB1_FFDB22 CAN_F1FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB1_FFDB23_Pos (23U) +#define CAN_F1FB1_FFDB23_Msk (0x1U << CAN_F1FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB1_FFDB23 CAN_F1FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB1_FFDB24_Pos (24U) +#define CAN_F1FB1_FFDB24_Msk (0x1U << CAN_F1FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB1_FFDB24 CAN_F1FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB1_FFDB25_Pos (25U) +#define CAN_F1FB1_FFDB25_Msk (0x1U << CAN_F1FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB1_FFDB25 CAN_F1FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB1_FFDB26_Pos (26U) +#define CAN_F1FB1_FFDB26_Msk (0x1U << CAN_F1FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB1_FFDB26 CAN_F1FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB1_FFDB27_Pos (27U) +#define CAN_F1FB1_FFDB27_Msk (0x1U << CAN_F1FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB1_FFDB27 CAN_F1FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB1_FFDB28_Pos (28U) +#define CAN_F1FB1_FFDB28_Msk (0x1U << CAN_F1FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB1_FFDB28 CAN_F1FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB1_FFDB29_Pos (29U) +#define CAN_F1FB1_FFDB29_Msk (0x1U << CAN_F1FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB1_FFDB29 CAN_F1FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB1_FFDB30_Pos (30U) +#define CAN_F1FB1_FFDB30_Msk (0x1U << CAN_F1FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB1_FFDB30 CAN_F1FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB1_FFDB31_Pos (31U) +#define CAN_F1FB1_FFDB31_Msk (0x1U << CAN_F1FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB1_FFDB31 CAN_F1FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB1 register *******************/ +#define CAN_F2FB1_FFDB0_Pos (0U) +#define CAN_F2FB1_FFDB0_Msk (0x1U << CAN_F2FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB1_FFDB0 CAN_F2FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB1_FFDB1_Pos (1U) +#define CAN_F2FB1_FFDB1_Msk (0x1U << CAN_F2FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB1_FFDB1 CAN_F2FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB1_FFDB2_Pos (2U) +#define CAN_F2FB1_FFDB2_Msk (0x1U << CAN_F2FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB1_FFDB2 CAN_F2FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB1_FFDB3_Pos (3U) +#define CAN_F2FB1_FFDB3_Msk (0x1U << CAN_F2FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB1_FFDB3 CAN_F2FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB1_FFDB4_Pos (4U) +#define CAN_F2FB1_FFDB4_Msk (0x1U << CAN_F2FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB1_FFDB4 CAN_F2FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB1_FFDB5_Pos (5U) +#define CAN_F2FB1_FFDB5_Msk (0x1U << CAN_F2FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB1_FFDB5 CAN_F2FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB1_FFDB6_Pos (6U) +#define CAN_F2FB1_FFDB6_Msk (0x1U << CAN_F2FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB1_FFDB6 CAN_F2FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB1_FFDB7_Pos (7U) +#define CAN_F2FB1_FFDB7_Msk (0x1U << CAN_F2FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB1_FFDB7 CAN_F2FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB1_FFDB8_Pos (8U) +#define CAN_F2FB1_FFDB8_Msk (0x1U << CAN_F2FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB1_FFDB8 CAN_F2FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB1_FFDB9_Pos (9U) +#define CAN_F2FB1_FFDB9_Msk (0x1U << CAN_F2FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB1_FFDB9 CAN_F2FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB1_FFDB10_Pos (10U) +#define CAN_F2FB1_FFDB10_Msk (0x1U << CAN_F2FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB1_FFDB10 CAN_F2FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB1_FFDB11_Pos (11U) +#define CAN_F2FB1_FFDB11_Msk (0x1U << CAN_F2FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB1_FFDB11 CAN_F2FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB1_FFDB12_Pos (12U) +#define CAN_F2FB1_FFDB12_Msk (0x1U << CAN_F2FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB1_FFDB12 CAN_F2FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB1_FFDB13_Pos (13U) +#define CAN_F2FB1_FFDB13_Msk (0x1U << CAN_F2FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB1_FFDB13 CAN_F2FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB1_FFDB14_Pos (14U) +#define CAN_F2FB1_FFDB14_Msk (0x1U << CAN_F2FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB1_FFDB14 CAN_F2FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB1_FFDB15_Pos (15U) +#define CAN_F2FB1_FFDB15_Msk (0x1U << CAN_F2FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB1_FFDB15 CAN_F2FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB1_FFDB16_Pos (16U) +#define CAN_F2FB1_FFDB16_Msk (0x1U << CAN_F2FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB1_FFDB16 CAN_F2FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB1_FFDB17_Pos (17U) +#define CAN_F2FB1_FFDB17_Msk (0x1U << CAN_F2FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB1_FFDB17 CAN_F2FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB1_FFDB18_Pos (18U) +#define CAN_F2FB1_FFDB18_Msk (0x1U << CAN_F2FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB1_FFDB18 CAN_F2FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB1_FFDB19_Pos (19U) +#define CAN_F2FB1_FFDB19_Msk (0x1U << CAN_F2FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB1_FFDB19 CAN_F2FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB1_FFDB20_Pos (20U) +#define CAN_F2FB1_FFDB20_Msk (0x1U << CAN_F2FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB1_FFDB20 CAN_F2FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB1_FFDB21_Pos (21U) +#define CAN_F2FB1_FFDB21_Msk (0x1U << CAN_F2FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB1_FFDB21 CAN_F2FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB1_FFDB22_Pos (22U) +#define CAN_F2FB1_FFDB22_Msk (0x1U << CAN_F2FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB1_FFDB22 CAN_F2FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB1_FFDB23_Pos (23U) +#define CAN_F2FB1_FFDB23_Msk (0x1U << CAN_F2FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB1_FFDB23 CAN_F2FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB1_FFDB24_Pos (24U) +#define CAN_F2FB1_FFDB24_Msk (0x1U << CAN_F2FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB1_FFDB24 CAN_F2FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB1_FFDB25_Pos (25U) +#define CAN_F2FB1_FFDB25_Msk (0x1U << CAN_F2FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB1_FFDB25 CAN_F2FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB1_FFDB26_Pos (26U) +#define CAN_F2FB1_FFDB26_Msk (0x1U << CAN_F2FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB1_FFDB26 CAN_F2FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB1_FFDB27_Pos (27U) +#define CAN_F2FB1_FFDB27_Msk (0x1U << CAN_F2FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB1_FFDB27 CAN_F2FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB1_FFDB28_Pos (28U) +#define CAN_F2FB1_FFDB28_Msk (0x1U << CAN_F2FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB1_FFDB28 CAN_F2FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB1_FFDB29_Pos (29U) +#define CAN_F2FB1_FFDB29_Msk (0x1U << CAN_F2FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB1_FFDB29 CAN_F2FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB1_FFDB30_Pos (30U) +#define CAN_F2FB1_FFDB30_Msk (0x1U << CAN_F2FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB1_FFDB30 CAN_F2FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB1_FFDB31_Pos (31U) +#define CAN_F2FB1_FFDB31_Msk (0x1U << CAN_F2FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB1_FFDB31 CAN_F2FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB1 register *******************/ +#define CAN_F3FB1_FFDB0_Pos (0U) +#define CAN_F3FB1_FFDB0_Msk (0x1U << CAN_F3FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB1_FFDB0 CAN_F3FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB1_FFDB1_Pos (1U) +#define CAN_F3FB1_FFDB1_Msk (0x1U << CAN_F3FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB1_FFDB1 CAN_F3FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB1_FFDB2_Pos (2U) +#define CAN_F3FB1_FFDB2_Msk (0x1U << CAN_F3FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB1_FFDB2 CAN_F3FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB1_FFDB3_Pos (3U) +#define CAN_F3FB1_FFDB3_Msk (0x1U << CAN_F3FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB1_FFDB3 CAN_F3FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB1_FFDB4_Pos (4U) +#define CAN_F3FB1_FFDB4_Msk (0x1U << CAN_F3FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB1_FFDB4 CAN_F3FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB1_FFDB5_Pos (5U) +#define CAN_F3FB1_FFDB5_Msk (0x1U << CAN_F3FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB1_FFDB5 CAN_F3FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB1_FFDB6_Pos (6U) +#define CAN_F3FB1_FFDB6_Msk (0x1U << CAN_F3FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB1_FFDB6 CAN_F3FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB1_FFDB7_Pos (7U) +#define CAN_F3FB1_FFDB7_Msk (0x1U << CAN_F3FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB1_FFDB7 CAN_F3FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB1_FFDB8_Pos (8U) +#define CAN_F3FB1_FFDB8_Msk (0x1U << CAN_F3FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB1_FFDB8 CAN_F3FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB1_FFDB9_Pos (9U) +#define CAN_F3FB1_FFDB9_Msk (0x1U << CAN_F3FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB1_FFDB9 CAN_F3FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB1_FFDB10_Pos (10U) +#define CAN_F3FB1_FFDB10_Msk (0x1U << CAN_F3FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB1_FFDB10 CAN_F3FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB1_FFDB11_Pos (11U) +#define CAN_F3FB1_FFDB11_Msk (0x1U << CAN_F3FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB1_FFDB11 CAN_F3FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB1_FFDB12_Pos (12U) +#define CAN_F3FB1_FFDB12_Msk (0x1U << CAN_F3FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB1_FFDB12 CAN_F3FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB1_FFDB13_Pos (13U) +#define CAN_F3FB1_FFDB13_Msk (0x1U << CAN_F3FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB1_FFDB13 CAN_F3FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB1_FFDB14_Pos (14U) +#define CAN_F3FB1_FFDB14_Msk (0x1U << CAN_F3FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB1_FFDB14 CAN_F3FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB1_FFDB15_Pos (15U) +#define CAN_F3FB1_FFDB15_Msk (0x1U << CAN_F3FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB1_FFDB15 CAN_F3FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB1_FFDB16_Pos (16U) +#define CAN_F3FB1_FFDB16_Msk (0x1U << CAN_F3FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB1_FFDB16 CAN_F3FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB1_FFDB17_Pos (17U) +#define CAN_F3FB1_FFDB17_Msk (0x1U << CAN_F3FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB1_FFDB17 CAN_F3FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB1_FFDB18_Pos (18U) +#define CAN_F3FB1_FFDB18_Msk (0x1U << CAN_F3FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB1_FFDB18 CAN_F3FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB1_FFDB19_Pos (19U) +#define CAN_F3FB1_FFDB19_Msk (0x1U << CAN_F3FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB1_FFDB19 CAN_F3FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB1_FFDB20_Pos (20U) +#define CAN_F3FB1_FFDB20_Msk (0x1U << CAN_F3FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB1_FFDB20 CAN_F3FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB1_FFDB21_Pos (21U) +#define CAN_F3FB1_FFDB21_Msk (0x1U << CAN_F3FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB1_FFDB21 CAN_F3FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB1_FFDB22_Pos (22U) +#define CAN_F3FB1_FFDB22_Msk (0x1U << CAN_F3FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB1_FFDB22 CAN_F3FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB1_FFDB23_Pos (23U) +#define CAN_F3FB1_FFDB23_Msk (0x1U << CAN_F3FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB1_FFDB23 CAN_F3FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB1_FFDB24_Pos (24U) +#define CAN_F3FB1_FFDB24_Msk (0x1U << CAN_F3FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB1_FFDB24 CAN_F3FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB1_FFDB25_Pos (25U) +#define CAN_F3FB1_FFDB25_Msk (0x1U << CAN_F3FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB1_FFDB25 CAN_F3FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB1_FFDB26_Pos (26U) +#define CAN_F3FB1_FFDB26_Msk (0x1U << CAN_F3FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB1_FFDB26 CAN_F3FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB1_FFDB27_Pos (27U) +#define CAN_F3FB1_FFDB27_Msk (0x1U << CAN_F3FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB1_FFDB27 CAN_F3FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB1_FFDB28_Pos (28U) +#define CAN_F3FB1_FFDB28_Msk (0x1U << CAN_F3FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB1_FFDB28 CAN_F3FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB1_FFDB29_Pos (29U) +#define CAN_F3FB1_FFDB29_Msk (0x1U << CAN_F3FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB1_FFDB29 CAN_F3FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB1_FFDB30_Pos (30U) +#define CAN_F3FB1_FFDB30_Msk (0x1U << CAN_F3FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB1_FFDB30 CAN_F3FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB1_FFDB31_Pos (31U) +#define CAN_F3FB1_FFDB31_Msk (0x1U << CAN_F3FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB1_FFDB31 CAN_F3FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB1 register *******************/ +#define CAN_F4FB1_FFDB0_Pos (0U) +#define CAN_F4FB1_FFDB0_Msk (0x1U << CAN_F4FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB1_FFDB0 CAN_F4FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB1_FFDB1_Pos (1U) +#define CAN_F4FB1_FFDB1_Msk (0x1U << CAN_F4FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB1_FFDB1 CAN_F4FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB1_FFDB2_Pos (2U) +#define CAN_F4FB1_FFDB2_Msk (0x1U << CAN_F4FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB1_FFDB2 CAN_F4FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB1_FFDB3_Pos (3U) +#define CAN_F4FB1_FFDB3_Msk (0x1U << CAN_F4FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB1_FFDB3 CAN_F4FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB1_FFDB4_Pos (4U) +#define CAN_F4FB1_FFDB4_Msk (0x1U << CAN_F4FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB1_FFDB4 CAN_F4FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB1_FFDB5_Pos (5U) +#define CAN_F4FB1_FFDB5_Msk (0x1U << CAN_F4FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB1_FFDB5 CAN_F4FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB1_FFDB6_Pos (6U) +#define CAN_F4FB1_FFDB6_Msk (0x1U << CAN_F4FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB1_FFDB6 CAN_F4FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB1_FFDB7_Pos (7U) +#define CAN_F4FB1_FFDB7_Msk (0x1U << CAN_F4FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB1_FFDB7 CAN_F4FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB1_FFDB8_Pos (8U) +#define CAN_F4FB1_FFDB8_Msk (0x1U << CAN_F4FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB1_FFDB8 CAN_F4FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB1_FFDB9_Pos (9U) +#define CAN_F4FB1_FFDB9_Msk (0x1U << CAN_F4FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB1_FFDB9 CAN_F4FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB1_FFDB10_Pos (10U) +#define CAN_F4FB1_FFDB10_Msk (0x1U << CAN_F4FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB1_FFDB10 CAN_F4FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB1_FFDB11_Pos (11U) +#define CAN_F4FB1_FFDB11_Msk (0x1U << CAN_F4FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB1_FFDB11 CAN_F4FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB1_FFDB12_Pos (12U) +#define CAN_F4FB1_FFDB12_Msk (0x1U << CAN_F4FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB1_FFDB12 CAN_F4FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB1_FFDB13_Pos (13U) +#define CAN_F4FB1_FFDB13_Msk (0x1U << CAN_F4FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB1_FFDB13 CAN_F4FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB1_FFDB14_Pos (14U) +#define CAN_F4FB1_FFDB14_Msk (0x1U << CAN_F4FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB1_FFDB14 CAN_F4FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB1_FFDB15_Pos (15U) +#define CAN_F4FB1_FFDB15_Msk (0x1U << CAN_F4FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB1_FFDB15 CAN_F4FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB1_FFDB16_Pos (16U) +#define CAN_F4FB1_FFDB16_Msk (0x1U << CAN_F4FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB1_FFDB16 CAN_F4FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB1_FFDB17_Pos (17U) +#define CAN_F4FB1_FFDB17_Msk (0x1U << CAN_F4FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB1_FFDB17 CAN_F4FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB1_FFDB18_Pos (18U) +#define CAN_F4FB1_FFDB18_Msk (0x1U << CAN_F4FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB1_FFDB18 CAN_F4FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB1_FFDB19_Pos (19U) +#define CAN_F4FB1_FFDB19_Msk (0x1U << CAN_F4FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB1_FFDB19 CAN_F4FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB1_FFDB20_Pos (20U) +#define CAN_F4FB1_FFDB20_Msk (0x1U << CAN_F4FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB1_FFDB20 CAN_F4FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB1_FFDB21_Pos (21U) +#define CAN_F4FB1_FFDB21_Msk (0x1U << CAN_F4FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB1_FFDB21 CAN_F4FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB1_FFDB22_Pos (22U) +#define CAN_F4FB1_FFDB22_Msk (0x1U << CAN_F4FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB1_FFDB22 CAN_F4FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB1_FFDB23_Pos (23U) +#define CAN_F4FB1_FFDB23_Msk (0x1U << CAN_F4FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB1_FFDB23 CAN_F4FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB1_FFDB24_Pos (24U) +#define CAN_F4FB1_FFDB24_Msk (0x1U << CAN_F4FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB1_FFDB24 CAN_F4FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB1_FFDB25_Pos (25U) +#define CAN_F4FB1_FFDB25_Msk (0x1U << CAN_F4FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB1_FFDB25 CAN_F4FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB1_FFDB26_Pos (26U) +#define CAN_F4FB1_FFDB26_Msk (0x1U << CAN_F4FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB1_FFDB26 CAN_F4FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB1_FFDB27_Pos (27U) +#define CAN_F4FB1_FFDB27_Msk (0x1U << CAN_F4FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB1_FFDB27 CAN_F4FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB1_FFDB28_Pos (28U) +#define CAN_F4FB1_FFDB28_Msk (0x1U << CAN_F4FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB1_FFDB28 CAN_F4FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB1_FFDB29_Pos (29U) +#define CAN_F4FB1_FFDB29_Msk (0x1U << CAN_F4FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB1_FFDB29 CAN_F4FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB1_FFDB30_Pos (30U) +#define CAN_F4FB1_FFDB30_Msk (0x1U << CAN_F4FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB1_FFDB30 CAN_F4FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB1_FFDB31_Pos (31U) +#define CAN_F4FB1_FFDB31_Msk (0x1U << CAN_F4FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB1_FFDB31 CAN_F4FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB1 register *******************/ +#define CAN_F5FB1_FFDB0_Pos (0U) +#define CAN_F5FB1_FFDB0_Msk (0x1U << CAN_F5FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB1_FFDB0 CAN_F5FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB1_FFDB1_Pos (1U) +#define CAN_F5FB1_FFDB1_Msk (0x1U << CAN_F5FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB1_FFDB1 CAN_F5FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB1_FFDB2_Pos (2U) +#define CAN_F5FB1_FFDB2_Msk (0x1U << CAN_F5FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB1_FFDB2 CAN_F5FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB1_FFDB3_Pos (3U) +#define CAN_F5FB1_FFDB3_Msk (0x1U << CAN_F5FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB1_FFDB3 CAN_F5FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB1_FFDB4_Pos (4U) +#define CAN_F5FB1_FFDB4_Msk (0x1U << CAN_F5FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB1_FFDB4 CAN_F5FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB1_FFDB5_Pos (5U) +#define CAN_F5FB1_FFDB5_Msk (0x1U << CAN_F5FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB1_FFDB5 CAN_F5FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB1_FFDB6_Pos (6U) +#define CAN_F5FB1_FFDB6_Msk (0x1U << CAN_F5FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB1_FFDB6 CAN_F5FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB1_FFDB7_Pos (7U) +#define CAN_F5FB1_FFDB7_Msk (0x1U << CAN_F5FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB1_FFDB7 CAN_F5FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB1_FFDB8_Pos (8U) +#define CAN_F5FB1_FFDB8_Msk (0x1U << CAN_F5FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB1_FFDB8 CAN_F5FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB1_FFDB9_Pos (9U) +#define CAN_F5FB1_FFDB9_Msk (0x1U << CAN_F5FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB1_FFDB9 CAN_F5FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB1_FFDB10_Pos (10U) +#define CAN_F5FB1_FFDB10_Msk (0x1U << CAN_F5FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB1_FFDB10 CAN_F5FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB1_FFDB11_Pos (11U) +#define CAN_F5FB1_FFDB11_Msk (0x1U << CAN_F5FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB1_FFDB11 CAN_F5FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB1_FFDB12_Pos (12U) +#define CAN_F5FB1_FFDB12_Msk (0x1U << CAN_F5FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB1_FFDB12 CAN_F5FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB1_FFDB13_Pos (13U) +#define CAN_F5FB1_FFDB13_Msk (0x1U << CAN_F5FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB1_FFDB13 CAN_F5FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB1_FFDB14_Pos (14U) +#define CAN_F5FB1_FFDB14_Msk (0x1U << CAN_F5FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB1_FFDB14 CAN_F5FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB1_FFDB15_Pos (15U) +#define CAN_F5FB1_FFDB15_Msk (0x1U << CAN_F5FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB1_FFDB15 CAN_F5FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB1_FFDB16_Pos (16U) +#define CAN_F5FB1_FFDB16_Msk (0x1U << CAN_F5FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB1_FFDB16 CAN_F5FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB1_FFDB17_Pos (17U) +#define CAN_F5FB1_FFDB17_Msk (0x1U << CAN_F5FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB1_FFDB17 CAN_F5FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB1_FFDB18_Pos (18U) +#define CAN_F5FB1_FFDB18_Msk (0x1U << CAN_F5FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB1_FFDB18 CAN_F5FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB1_FFDB19_Pos (19U) +#define CAN_F5FB1_FFDB19_Msk (0x1U << CAN_F5FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB1_FFDB19 CAN_F5FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB1_FFDB20_Pos (20U) +#define CAN_F5FB1_FFDB20_Msk (0x1U << CAN_F5FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB1_FFDB20 CAN_F5FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB1_FFDB21_Pos (21U) +#define CAN_F5FB1_FFDB21_Msk (0x1U << CAN_F5FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB1_FFDB21 CAN_F5FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB1_FFDB22_Pos (22U) +#define CAN_F5FB1_FFDB22_Msk (0x1U << CAN_F5FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB1_FFDB22 CAN_F5FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB1_FFDB23_Pos (23U) +#define CAN_F5FB1_FFDB23_Msk (0x1U << CAN_F5FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB1_FFDB23 CAN_F5FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB1_FFDB24_Pos (24U) +#define CAN_F5FB1_FFDB24_Msk (0x1U << CAN_F5FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB1_FFDB24 CAN_F5FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB1_FFDB25_Pos (25U) +#define CAN_F5FB1_FFDB25_Msk (0x1U << CAN_F5FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB1_FFDB25 CAN_F5FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB1_FFDB26_Pos (26U) +#define CAN_F5FB1_FFDB26_Msk (0x1U << CAN_F5FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB1_FFDB26 CAN_F5FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB1_FFDB27_Pos (27U) +#define CAN_F5FB1_FFDB27_Msk (0x1U << CAN_F5FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB1_FFDB27 CAN_F5FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB1_FFDB28_Pos (28U) +#define CAN_F5FB1_FFDB28_Msk (0x1U << CAN_F5FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB1_FFDB28 CAN_F5FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB1_FFDB29_Pos (29U) +#define CAN_F5FB1_FFDB29_Msk (0x1U << CAN_F5FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB1_FFDB29 CAN_F5FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB1_FFDB30_Pos (30U) +#define CAN_F5FB1_FFDB30_Msk (0x1U << CAN_F5FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB1_FFDB30 CAN_F5FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB1_FFDB31_Pos (31U) +#define CAN_F5FB1_FFDB31_Msk (0x1U << CAN_F5FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB1_FFDB31 CAN_F5FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB1 register *******************/ +#define CAN_F6FB1_FFDB0_Pos (0U) +#define CAN_F6FB1_FFDB0_Msk (0x1U << CAN_F6FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB1_FFDB0 CAN_F6FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB1_FFDB1_Pos (1U) +#define CAN_F6FB1_FFDB1_Msk (0x1U << CAN_F6FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB1_FFDB1 CAN_F6FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB1_FFDB2_Pos (2U) +#define CAN_F6FB1_FFDB2_Msk (0x1U << CAN_F6FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB1_FFDB2 CAN_F6FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB1_FFDB3_Pos (3U) +#define CAN_F6FB1_FFDB3_Msk (0x1U << CAN_F6FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB1_FFDB3 CAN_F6FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB1_FFDB4_Pos (4U) +#define CAN_F6FB1_FFDB4_Msk (0x1U << CAN_F6FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB1_FFDB4 CAN_F6FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB1_FFDB5_Pos (5U) +#define CAN_F6FB1_FFDB5_Msk (0x1U << CAN_F6FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB1_FFDB5 CAN_F6FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB1_FFDB6_Pos (6U) +#define CAN_F6FB1_FFDB6_Msk (0x1U << CAN_F6FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB1_FFDB6 CAN_F6FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB1_FFDB7_Pos (7U) +#define CAN_F6FB1_FFDB7_Msk (0x1U << CAN_F6FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB1_FFDB7 CAN_F6FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB1_FFDB8_Pos (8U) +#define CAN_F6FB1_FFDB8_Msk (0x1U << CAN_F6FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB1_FFDB8 CAN_F6FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB1_FFDB9_Pos (9U) +#define CAN_F6FB1_FFDB9_Msk (0x1U << CAN_F6FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB1_FFDB9 CAN_F6FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB1_FFDB10_Pos (10U) +#define CAN_F6FB1_FFDB10_Msk (0x1U << CAN_F6FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB1_FFDB10 CAN_F6FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB1_FFDB11_Pos (11U) +#define CAN_F6FB1_FFDB11_Msk (0x1U << CAN_F6FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB1_FFDB11 CAN_F6FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB1_FFDB12_Pos (12U) +#define CAN_F6FB1_FFDB12_Msk (0x1U << CAN_F6FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB1_FFDB12 CAN_F6FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB1_FFDB13_Pos (13U) +#define CAN_F6FB1_FFDB13_Msk (0x1U << CAN_F6FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB1_FFDB13 CAN_F6FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB1_FFDB14_Pos (14U) +#define CAN_F6FB1_FFDB14_Msk (0x1U << CAN_F6FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB1_FFDB14 CAN_F6FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB1_FFDB15_Pos (15U) +#define CAN_F6FB1_FFDB15_Msk (0x1U << CAN_F6FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB1_FFDB15 CAN_F6FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB1_FFDB16_Pos (16U) +#define CAN_F6FB1_FFDB16_Msk (0x1U << CAN_F6FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB1_FFDB16 CAN_F6FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB1_FFDB17_Pos (17U) +#define CAN_F6FB1_FFDB17_Msk (0x1U << CAN_F6FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB1_FFDB17 CAN_F6FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB1_FFDB18_Pos (18U) +#define CAN_F6FB1_FFDB18_Msk (0x1U << CAN_F6FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB1_FFDB18 CAN_F6FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB1_FFDB19_Pos (19U) +#define CAN_F6FB1_FFDB19_Msk (0x1U << CAN_F6FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB1_FFDB19 CAN_F6FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB1_FFDB20_Pos (20U) +#define CAN_F6FB1_FFDB20_Msk (0x1U << CAN_F6FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB1_FFDB20 CAN_F6FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB1_FFDB21_Pos (21U) +#define CAN_F6FB1_FFDB21_Msk (0x1U << CAN_F6FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB1_FFDB21 CAN_F6FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB1_FFDB22_Pos (22U) +#define CAN_F6FB1_FFDB22_Msk (0x1U << CAN_F6FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB1_FFDB22 CAN_F6FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB1_FFDB23_Pos (23U) +#define CAN_F6FB1_FFDB23_Msk (0x1U << CAN_F6FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB1_FFDB23 CAN_F6FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB1_FFDB24_Pos (24U) +#define CAN_F6FB1_FFDB24_Msk (0x1U << CAN_F6FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB1_FFDB24 CAN_F6FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB1_FFDB25_Pos (25U) +#define CAN_F6FB1_FFDB25_Msk (0x1U << CAN_F6FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB1_FFDB25 CAN_F6FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB1_FFDB26_Pos (26U) +#define CAN_F6FB1_FFDB26_Msk (0x1U << CAN_F6FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB1_FFDB26 CAN_F6FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB1_FFDB27_Pos (27U) +#define CAN_F6FB1_FFDB27_Msk (0x1U << CAN_F6FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB1_FFDB27 CAN_F6FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB1_FFDB28_Pos (28U) +#define CAN_F6FB1_FFDB28_Msk (0x1U << CAN_F6FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB1_FFDB28 CAN_F6FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB1_FFDB29_Pos (29U) +#define CAN_F6FB1_FFDB29_Msk (0x1U << CAN_F6FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB1_FFDB29 CAN_F6FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB1_FFDB30_Pos (30U) +#define CAN_F6FB1_FFDB30_Msk (0x1U << CAN_F6FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB1_FFDB30 CAN_F6FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB1_FFDB31_Pos (31U) +#define CAN_F6FB1_FFDB31_Msk (0x1U << CAN_F6FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB1_FFDB31 CAN_F6FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB1 register *******************/ +#define CAN_F7FB1_FFDB0_Pos (0U) +#define CAN_F7FB1_FFDB0_Msk (0x1U << CAN_F7FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB1_FFDB0 CAN_F7FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB1_FFDB1_Pos (1U) +#define CAN_F7FB1_FFDB1_Msk (0x1U << CAN_F7FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB1_FFDB1 CAN_F7FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB1_FFDB2_Pos (2U) +#define CAN_F7FB1_FFDB2_Msk (0x1U << CAN_F7FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB1_FFDB2 CAN_F7FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB1_FFDB3_Pos (3U) +#define CAN_F7FB1_FFDB3_Msk (0x1U << CAN_F7FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB1_FFDB3 CAN_F7FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB1_FFDB4_Pos (4U) +#define CAN_F7FB1_FFDB4_Msk (0x1U << CAN_F7FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB1_FFDB4 CAN_F7FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB1_FFDB5_Pos (5U) +#define CAN_F7FB1_FFDB5_Msk (0x1U << CAN_F7FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB1_FFDB5 CAN_F7FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB1_FFDB6_Pos (6U) +#define CAN_F7FB1_FFDB6_Msk (0x1U << CAN_F7FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB1_FFDB6 CAN_F7FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB1_FFDB7_Pos (7U) +#define CAN_F7FB1_FFDB7_Msk (0x1U << CAN_F7FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB1_FFDB7 CAN_F7FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB1_FFDB8_Pos (8U) +#define CAN_F7FB1_FFDB8_Msk (0x1U << CAN_F7FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB1_FFDB8 CAN_F7FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB1_FFDB9_Pos (9U) +#define CAN_F7FB1_FFDB9_Msk (0x1U << CAN_F7FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB1_FFDB9 CAN_F7FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB1_FFDB10_Pos (10U) +#define CAN_F7FB1_FFDB10_Msk (0x1U << CAN_F7FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB1_FFDB10 CAN_F7FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB1_FFDB11_Pos (11U) +#define CAN_F7FB1_FFDB11_Msk (0x1U << CAN_F7FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB1_FFDB11 CAN_F7FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB1_FFDB12_Pos (12U) +#define CAN_F7FB1_FFDB12_Msk (0x1U << CAN_F7FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB1_FFDB12 CAN_F7FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB1_FFDB13_Pos (13U) +#define CAN_F7FB1_FFDB13_Msk (0x1U << CAN_F7FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB1_FFDB13 CAN_F7FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB1_FFDB14_Pos (14U) +#define CAN_F7FB1_FFDB14_Msk (0x1U << CAN_F7FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB1_FFDB14 CAN_F7FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB1_FFDB15_Pos (15U) +#define CAN_F7FB1_FFDB15_Msk (0x1U << CAN_F7FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB1_FFDB15 CAN_F7FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB1_FFDB16_Pos (16U) +#define CAN_F7FB1_FFDB16_Msk (0x1U << CAN_F7FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB1_FFDB16 CAN_F7FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB1_FFDB17_Pos (17U) +#define CAN_F7FB1_FFDB17_Msk (0x1U << CAN_F7FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB1_FFDB17 CAN_F7FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB1_FFDB18_Pos (18U) +#define CAN_F7FB1_FFDB18_Msk (0x1U << CAN_F7FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB1_FFDB18 CAN_F7FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB1_FFDB19_Pos (19U) +#define CAN_F7FB1_FFDB19_Msk (0x1U << CAN_F7FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB1_FFDB19 CAN_F7FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB1_FFDB20_Pos (20U) +#define CAN_F7FB1_FFDB20_Msk (0x1U << CAN_F7FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB1_FFDB20 CAN_F7FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB1_FFDB21_Pos (21U) +#define CAN_F7FB1_FFDB21_Msk (0x1U << CAN_F7FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB1_FFDB21 CAN_F7FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB1_FFDB22_Pos (22U) +#define CAN_F7FB1_FFDB22_Msk (0x1U << CAN_F7FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB1_FFDB22 CAN_F7FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB1_FFDB23_Pos (23U) +#define CAN_F7FB1_FFDB23_Msk (0x1U << CAN_F7FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB1_FFDB23 CAN_F7FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB1_FFDB24_Pos (24U) +#define CAN_F7FB1_FFDB24_Msk (0x1U << CAN_F7FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB1_FFDB24 CAN_F7FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB1_FFDB25_Pos (25U) +#define CAN_F7FB1_FFDB25_Msk (0x1U << CAN_F7FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB1_FFDB25 CAN_F7FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB1_FFDB26_Pos (26U) +#define CAN_F7FB1_FFDB26_Msk (0x1U << CAN_F7FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB1_FFDB26 CAN_F7FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB1_FFDB27_Pos (27U) +#define CAN_F7FB1_FFDB27_Msk (0x1U << CAN_F7FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB1_FFDB27 CAN_F7FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB1_FFDB28_Pos (28U) +#define CAN_F7FB1_FFDB28_Msk (0x1U << CAN_F7FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB1_FFDB28 CAN_F7FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB1_FFDB29_Pos (29U) +#define CAN_F7FB1_FFDB29_Msk (0x1U << CAN_F7FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB1_FFDB29 CAN_F7FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB1_FFDB30_Pos (30U) +#define CAN_F7FB1_FFDB30_Msk (0x1U << CAN_F7FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB1_FFDB30 CAN_F7FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB1_FFDB31_Pos (31U) +#define CAN_F7FB1_FFDB31_Msk (0x1U << CAN_F7FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB1_FFDB31 CAN_F7FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB1 register *******************/ +#define CAN_F8FB1_FFDB0_Pos (0U) +#define CAN_F8FB1_FFDB0_Msk (0x1U << CAN_F8FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB1_FFDB0 CAN_F8FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB1_FFDB1_Pos (1U) +#define CAN_F8FB1_FFDB1_Msk (0x1U << CAN_F8FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB1_FFDB1 CAN_F8FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB1_FFDB2_Pos (2U) +#define CAN_F8FB1_FFDB2_Msk (0x1U << CAN_F8FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB1_FFDB2 CAN_F8FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB1_FFDB3_Pos (3U) +#define CAN_F8FB1_FFDB3_Msk (0x1U << CAN_F8FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB1_FFDB3 CAN_F8FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB1_FFDB4_Pos (4U) +#define CAN_F8FB1_FFDB4_Msk (0x1U << CAN_F8FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB1_FFDB4 CAN_F8FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB1_FFDB5_Pos (5U) +#define CAN_F8FB1_FFDB5_Msk (0x1U << CAN_F8FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB1_FFDB5 CAN_F8FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB1_FFDB6_Pos (6U) +#define CAN_F8FB1_FFDB6_Msk (0x1U << CAN_F8FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB1_FFDB6 CAN_F8FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB1_FFDB7_Pos (7U) +#define CAN_F8FB1_FFDB7_Msk (0x1U << CAN_F8FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB1_FFDB7 CAN_F8FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB1_FFDB8_Pos (8U) +#define CAN_F8FB1_FFDB8_Msk (0x1U << CAN_F8FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB1_FFDB8 CAN_F8FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB1_FFDB9_Pos (9U) +#define CAN_F8FB1_FFDB9_Msk (0x1U << CAN_F8FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB1_FFDB9 CAN_F8FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB1_FFDB10_Pos (10U) +#define CAN_F8FB1_FFDB10_Msk (0x1U << CAN_F8FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB1_FFDB10 CAN_F8FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB1_FFDB11_Pos (11U) +#define CAN_F8FB1_FFDB11_Msk (0x1U << CAN_F8FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB1_FFDB11 CAN_F8FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB1_FFDB12_Pos (12U) +#define CAN_F8FB1_FFDB12_Msk (0x1U << CAN_F8FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB1_FFDB12 CAN_F8FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB1_FFDB13_Pos (13U) +#define CAN_F8FB1_FFDB13_Msk (0x1U << CAN_F8FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB1_FFDB13 CAN_F8FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB1_FFDB14_Pos (14U) +#define CAN_F8FB1_FFDB14_Msk (0x1U << CAN_F8FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB1_FFDB14 CAN_F8FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB1_FFDB15_Pos (15U) +#define CAN_F8FB1_FFDB15_Msk (0x1U << CAN_F8FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB1_FFDB15 CAN_F8FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB1_FFDB16_Pos (16U) +#define CAN_F8FB1_FFDB16_Msk (0x1U << CAN_F8FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB1_FFDB16 CAN_F8FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB1_FFDB17_Pos (17U) +#define CAN_F8FB1_FFDB17_Msk (0x1U << CAN_F8FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB1_FFDB17 CAN_F8FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB1_FFDB18_Pos (18U) +#define CAN_F8FB1_FFDB18_Msk (0x1U << CAN_F8FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB1_FFDB18 CAN_F8FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB1_FFDB19_Pos (19U) +#define CAN_F8FB1_FFDB19_Msk (0x1U << CAN_F8FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB1_FFDB19 CAN_F8FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB1_FFDB20_Pos (20U) +#define CAN_F8FB1_FFDB20_Msk (0x1U << CAN_F8FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB1_FFDB20 CAN_F8FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB1_FFDB21_Pos (21U) +#define CAN_F8FB1_FFDB21_Msk (0x1U << CAN_F8FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB1_FFDB21 CAN_F8FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB1_FFDB22_Pos (22U) +#define CAN_F8FB1_FFDB22_Msk (0x1U << CAN_F8FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB1_FFDB22 CAN_F8FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB1_FFDB23_Pos (23U) +#define CAN_F8FB1_FFDB23_Msk (0x1U << CAN_F8FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB1_FFDB23 CAN_F8FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB1_FFDB24_Pos (24U) +#define CAN_F8FB1_FFDB24_Msk (0x1U << CAN_F8FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB1_FFDB24 CAN_F8FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB1_FFDB25_Pos (25U) +#define CAN_F8FB1_FFDB25_Msk (0x1U << CAN_F8FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB1_FFDB25 CAN_F8FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB1_FFDB26_Pos (26U) +#define CAN_F8FB1_FFDB26_Msk (0x1U << CAN_F8FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB1_FFDB26 CAN_F8FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB1_FFDB27_Pos (27U) +#define CAN_F8FB1_FFDB27_Msk (0x1U << CAN_F8FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB1_FFDB27 CAN_F8FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB1_FFDB28_Pos (28U) +#define CAN_F8FB1_FFDB28_Msk (0x1U << CAN_F8FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB1_FFDB28 CAN_F8FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB1_FFDB29_Pos (29U) +#define CAN_F8FB1_FFDB29_Msk (0x1U << CAN_F8FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB1_FFDB29 CAN_F8FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB1_FFDB30_Pos (30U) +#define CAN_F8FB1_FFDB30_Msk (0x1U << CAN_F8FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB1_FFDB30 CAN_F8FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB1_FFDB31_Pos (31U) +#define CAN_F8FB1_FFDB31_Msk (0x1U << CAN_F8FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB1_FFDB31 CAN_F8FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB1 register *******************/ +#define CAN_F9FB1_FFDB0_Pos (0U) +#define CAN_F9FB1_FFDB0_Msk (0x1U << CAN_F9FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB1_FFDB0 CAN_F9FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB1_FFDB1_Pos (1U) +#define CAN_F9FB1_FFDB1_Msk (0x1U << CAN_F9FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB1_FFDB1 CAN_F9FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB1_FFDB2_Pos (2U) +#define CAN_F9FB1_FFDB2_Msk (0x1U << CAN_F9FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB1_FFDB2 CAN_F9FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB1_FFDB3_Pos (3U) +#define CAN_F9FB1_FFDB3_Msk (0x1U << CAN_F9FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB1_FFDB3 CAN_F9FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB1_FFDB4_Pos (4U) +#define CAN_F9FB1_FFDB4_Msk (0x1U << CAN_F9FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB1_FFDB4 CAN_F9FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB1_FFDB5_Pos (5U) +#define CAN_F9FB1_FFDB5_Msk (0x1U << CAN_F9FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB1_FFDB5 CAN_F9FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB1_FFDB6_Pos (6U) +#define CAN_F9FB1_FFDB6_Msk (0x1U << CAN_F9FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB1_FFDB6 CAN_F9FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB1_FFDB7_Pos (7U) +#define CAN_F9FB1_FFDB7_Msk (0x1U << CAN_F9FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB1_FFDB7 CAN_F9FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB1_FFDB8_Pos (8U) +#define CAN_F9FB1_FFDB8_Msk (0x1U << CAN_F9FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB1_FFDB8 CAN_F9FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB1_FFDB9_Pos (9U) +#define CAN_F9FB1_FFDB9_Msk (0x1U << CAN_F9FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB1_FFDB9 CAN_F9FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB1_FFDB10_Pos (10U) +#define CAN_F9FB1_FFDB10_Msk (0x1U << CAN_F9FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB1_FFDB10 CAN_F9FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB1_FFDB11_Pos (11U) +#define CAN_F9FB1_FFDB11_Msk (0x1U << CAN_F9FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB1_FFDB11 CAN_F9FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB1_FFDB12_Pos (12U) +#define CAN_F9FB1_FFDB12_Msk (0x1U << CAN_F9FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB1_FFDB12 CAN_F9FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB1_FFDB13_Pos (13U) +#define CAN_F9FB1_FFDB13_Msk (0x1U << CAN_F9FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB1_FFDB13 CAN_F9FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB1_FFDB14_Pos (14U) +#define CAN_F9FB1_FFDB14_Msk (0x1U << CAN_F9FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB1_FFDB14 CAN_F9FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB1_FFDB15_Pos (15U) +#define CAN_F9FB1_FFDB15_Msk (0x1U << CAN_F9FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB1_FFDB15 CAN_F9FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB1_FFDB16_Pos (16U) +#define CAN_F9FB1_FFDB16_Msk (0x1U << CAN_F9FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB1_FFDB16 CAN_F9FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB1_FFDB17_Pos (17U) +#define CAN_F9FB1_FFDB17_Msk (0x1U << CAN_F9FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB1_FFDB17 CAN_F9FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB1_FFDB18_Pos (18U) +#define CAN_F9FB1_FFDB18_Msk (0x1U << CAN_F9FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB1_FFDB18 CAN_F9FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB1_FFDB19_Pos (19U) +#define CAN_F9FB1_FFDB19_Msk (0x1U << CAN_F9FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB1_FFDB19 CAN_F9FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB1_FFDB20_Pos (20U) +#define CAN_F9FB1_FFDB20_Msk (0x1U << CAN_F9FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB1_FFDB20 CAN_F9FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB1_FFDB21_Pos (21U) +#define CAN_F9FB1_FFDB21_Msk (0x1U << CAN_F9FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB1_FFDB21 CAN_F9FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB1_FFDB22_Pos (22U) +#define CAN_F9FB1_FFDB22_Msk (0x1U << CAN_F9FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB1_FFDB22 CAN_F9FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB1_FFDB23_Pos (23U) +#define CAN_F9FB1_FFDB23_Msk (0x1U << CAN_F9FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB1_FFDB23 CAN_F9FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB1_FFDB24_Pos (24U) +#define CAN_F9FB1_FFDB24_Msk (0x1U << CAN_F9FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB1_FFDB24 CAN_F9FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB1_FFDB25_Pos (25U) +#define CAN_F9FB1_FFDB25_Msk (0x1U << CAN_F9FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB1_FFDB25 CAN_F9FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB1_FFDB26_Pos (26U) +#define CAN_F9FB1_FFDB26_Msk (0x1U << CAN_F9FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB1_FFDB26 CAN_F9FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB1_FFDB27_Pos (27U) +#define CAN_F9FB1_FFDB27_Msk (0x1U << CAN_F9FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB1_FFDB27 CAN_F9FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB1_FFDB28_Pos (28U) +#define CAN_F9FB1_FFDB28_Msk (0x1U << CAN_F9FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB1_FFDB28 CAN_F9FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB1_FFDB29_Pos (29U) +#define CAN_F9FB1_FFDB29_Msk (0x1U << CAN_F9FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB1_FFDB29 CAN_F9FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB1_FFDB30_Pos (30U) +#define CAN_F9FB1_FFDB30_Msk (0x1U << CAN_F9FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB1_FFDB30 CAN_F9FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB1_FFDB31_Pos (31U) +#define CAN_F9FB1_FFDB31_Msk (0x1U << CAN_F9FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB1_FFDB31 CAN_F9FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB1 register ******************/ +#define CAN_F10FB1_FFDB0_Pos (0U) +#define CAN_F10FB1_FFDB0_Msk (0x1U << CAN_F10FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB1_FFDB0 CAN_F10FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB1_FFDB1_Pos (1U) +#define CAN_F10FB1_FFDB1_Msk (0x1U << CAN_F10FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB1_FFDB1 CAN_F10FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB1_FFDB2_Pos (2U) +#define CAN_F10FB1_FFDB2_Msk (0x1U << CAN_F10FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB1_FFDB2 CAN_F10FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB1_FFDB3_Pos (3U) +#define CAN_F10FB1_FFDB3_Msk (0x1U << CAN_F10FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB1_FFDB3 CAN_F10FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB1_FFDB4_Pos (4U) +#define CAN_F10FB1_FFDB4_Msk (0x1U << CAN_F10FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB1_FFDB4 CAN_F10FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB1_FFDB5_Pos (5U) +#define CAN_F10FB1_FFDB5_Msk (0x1U << CAN_F10FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB1_FFDB5 CAN_F10FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB1_FFDB6_Pos (6U) +#define CAN_F10FB1_FFDB6_Msk (0x1U << CAN_F10FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB1_FFDB6 CAN_F10FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB1_FFDB7_Pos (7U) +#define CAN_F10FB1_FFDB7_Msk (0x1U << CAN_F10FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB1_FFDB7 CAN_F10FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB1_FFDB8_Pos (8U) +#define CAN_F10FB1_FFDB8_Msk (0x1U << CAN_F10FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB1_FFDB8 CAN_F10FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB1_FFDB9_Pos (9U) +#define CAN_F10FB1_FFDB9_Msk (0x1U << CAN_F10FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB1_FFDB9 CAN_F10FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB1_FFDB10_Pos (10U) +#define CAN_F10FB1_FFDB10_Msk (0x1U << CAN_F10FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB1_FFDB10 CAN_F10FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB1_FFDB11_Pos (11U) +#define CAN_F10FB1_FFDB11_Msk (0x1U << CAN_F10FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB1_FFDB11 CAN_F10FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB1_FFDB12_Pos (12U) +#define CAN_F10FB1_FFDB12_Msk (0x1U << CAN_F10FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB1_FFDB12 CAN_F10FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB1_FFDB13_Pos (13U) +#define CAN_F10FB1_FFDB13_Msk (0x1U << CAN_F10FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB1_FFDB13 CAN_F10FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB1_FFDB14_Pos (14U) +#define CAN_F10FB1_FFDB14_Msk (0x1U << CAN_F10FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB1_FFDB14 CAN_F10FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB1_FFDB15_Pos (15U) +#define CAN_F10FB1_FFDB15_Msk (0x1U << CAN_F10FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB1_FFDB15 CAN_F10FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB1_FFDB16_Pos (16U) +#define CAN_F10FB1_FFDB16_Msk (0x1U << CAN_F10FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB1_FFDB16 CAN_F10FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB1_FFDB17_Pos (17U) +#define CAN_F10FB1_FFDB17_Msk (0x1U << CAN_F10FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB1_FFDB17 CAN_F10FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB1_FFDB18_Pos (18U) +#define CAN_F10FB1_FFDB18_Msk (0x1U << CAN_F10FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB1_FFDB18 CAN_F10FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB1_FFDB19_Pos (19U) +#define CAN_F10FB1_FFDB19_Msk (0x1U << CAN_F10FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB1_FFDB19 CAN_F10FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB1_FFDB20_Pos (20U) +#define CAN_F10FB1_FFDB20_Msk (0x1U << CAN_F10FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB1_FFDB20 CAN_F10FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB1_FFDB21_Pos (21U) +#define CAN_F10FB1_FFDB21_Msk (0x1U << CAN_F10FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB1_FFDB21 CAN_F10FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB1_FFDB22_Pos (22U) +#define CAN_F10FB1_FFDB22_Msk (0x1U << CAN_F10FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB1_FFDB22 CAN_F10FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB1_FFDB23_Pos (23U) +#define CAN_F10FB1_FFDB23_Msk (0x1U << CAN_F10FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB1_FFDB23 CAN_F10FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB1_FFDB24_Pos (24U) +#define CAN_F10FB1_FFDB24_Msk (0x1U << CAN_F10FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB1_FFDB24 CAN_F10FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB1_FFDB25_Pos (25U) +#define CAN_F10FB1_FFDB25_Msk (0x1U << CAN_F10FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB1_FFDB25 CAN_F10FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB1_FFDB26_Pos (26U) +#define CAN_F10FB1_FFDB26_Msk (0x1U << CAN_F10FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB1_FFDB26 CAN_F10FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB1_FFDB27_Pos (27U) +#define CAN_F10FB1_FFDB27_Msk (0x1U << CAN_F10FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB1_FFDB27 CAN_F10FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB1_FFDB28_Pos (28U) +#define CAN_F10FB1_FFDB28_Msk (0x1U << CAN_F10FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB1_FFDB28 CAN_F10FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB1_FFDB29_Pos (29U) +#define CAN_F10FB1_FFDB29_Msk (0x1U << CAN_F10FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB1_FFDB29 CAN_F10FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB1_FFDB30_Pos (30U) +#define CAN_F10FB1_FFDB30_Msk (0x1U << CAN_F10FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB1_FFDB30 CAN_F10FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB1_FFDB31_Pos (31U) +#define CAN_F10FB1_FFDB31_Msk (0x1U << CAN_F10FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB1_FFDB31 CAN_F10FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB1 register ******************/ +#define CAN_F11FB1_FFDB0_Pos (0U) +#define CAN_F11FB1_FFDB0_Msk (0x1U << CAN_F11FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB1_FFDB0 CAN_F11FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB1_FFDB1_Pos (1U) +#define CAN_F11FB1_FFDB1_Msk (0x1U << CAN_F11FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB1_FFDB1 CAN_F11FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB1_FFDB2_Pos (2U) +#define CAN_F11FB1_FFDB2_Msk (0x1U << CAN_F11FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB1_FFDB2 CAN_F11FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB1_FFDB3_Pos (3U) +#define CAN_F11FB1_FFDB3_Msk (0x1U << CAN_F11FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB1_FFDB3 CAN_F11FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB1_FFDB4_Pos (4U) +#define CAN_F11FB1_FFDB4_Msk (0x1U << CAN_F11FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB1_FFDB4 CAN_F11FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB1_FFDB5_Pos (5U) +#define CAN_F11FB1_FFDB5_Msk (0x1U << CAN_F11FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB1_FFDB5 CAN_F11FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB1_FFDB6_Pos (6U) +#define CAN_F11FB1_FFDB6_Msk (0x1U << CAN_F11FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB1_FFDB6 CAN_F11FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB1_FFDB7_Pos (7U) +#define CAN_F11FB1_FFDB7_Msk (0x1U << CAN_F11FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB1_FFDB7 CAN_F11FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB1_FFDB8_Pos (8U) +#define CAN_F11FB1_FFDB8_Msk (0x1U << CAN_F11FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB1_FFDB8 CAN_F11FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB1_FFDB9_Pos (9U) +#define CAN_F11FB1_FFDB9_Msk (0x1U << CAN_F11FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB1_FFDB9 CAN_F11FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB1_FFDB10_Pos (10U) +#define CAN_F11FB1_FFDB10_Msk (0x1U << CAN_F11FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB1_FFDB10 CAN_F11FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB1_FFDB11_Pos (11U) +#define CAN_F11FB1_FFDB11_Msk (0x1U << CAN_F11FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB1_FFDB11 CAN_F11FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB1_FFDB12_Pos (12U) +#define CAN_F11FB1_FFDB12_Msk (0x1U << CAN_F11FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB1_FFDB12 CAN_F11FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB1_FFDB13_Pos (13U) +#define CAN_F11FB1_FFDB13_Msk (0x1U << CAN_F11FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB1_FFDB13 CAN_F11FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB1_FFDB14_Pos (14U) +#define CAN_F11FB1_FFDB14_Msk (0x1U << CAN_F11FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB1_FFDB14 CAN_F11FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB1_FFDB15_Pos (15U) +#define CAN_F11FB1_FFDB15_Msk (0x1U << CAN_F11FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB1_FFDB15 CAN_F11FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB1_FFDB16_Pos (16U) +#define CAN_F11FB1_FFDB16_Msk (0x1U << CAN_F11FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB1_FFDB16 CAN_F11FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB1_FFDB17_Pos (17U) +#define CAN_F11FB1_FFDB17_Msk (0x1U << CAN_F11FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB1_FFDB17 CAN_F11FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB1_FFDB18_Pos (18U) +#define CAN_F11FB1_FFDB18_Msk (0x1U << CAN_F11FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB1_FFDB18 CAN_F11FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB1_FFDB19_Pos (19U) +#define CAN_F11FB1_FFDB19_Msk (0x1U << CAN_F11FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB1_FFDB19 CAN_F11FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB1_FFDB20_Pos (20U) +#define CAN_F11FB1_FFDB20_Msk (0x1U << CAN_F11FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB1_FFDB20 CAN_F11FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB1_FFDB21_Pos (21U) +#define CAN_F11FB1_FFDB21_Msk (0x1U << CAN_F11FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB1_FFDB21 CAN_F11FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB1_FFDB22_Pos (22U) +#define CAN_F11FB1_FFDB22_Msk (0x1U << CAN_F11FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB1_FFDB22 CAN_F11FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB1_FFDB23_Pos (23U) +#define CAN_F11FB1_FFDB23_Msk (0x1U << CAN_F11FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB1_FFDB23 CAN_F11FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB1_FFDB24_Pos (24U) +#define CAN_F11FB1_FFDB24_Msk (0x1U << CAN_F11FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB1_FFDB24 CAN_F11FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB1_FFDB25_Pos (25U) +#define CAN_F11FB1_FFDB25_Msk (0x1U << CAN_F11FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB1_FFDB25 CAN_F11FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB1_FFDB26_Pos (26U) +#define CAN_F11FB1_FFDB26_Msk (0x1U << CAN_F11FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB1_FFDB26 CAN_F11FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB1_FFDB27_Pos (27U) +#define CAN_F11FB1_FFDB27_Msk (0x1U << CAN_F11FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB1_FFDB27 CAN_F11FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB1_FFDB28_Pos (28U) +#define CAN_F11FB1_FFDB28_Msk (0x1U << CAN_F11FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB1_FFDB28 CAN_F11FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB1_FFDB29_Pos (29U) +#define CAN_F11FB1_FFDB29_Msk (0x1U << CAN_F11FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB1_FFDB29 CAN_F11FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB1_FFDB30_Pos (30U) +#define CAN_F11FB1_FFDB30_Msk (0x1U << CAN_F11FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB1_FFDB30 CAN_F11FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB1_FFDB31_Pos (31U) +#define CAN_F11FB1_FFDB31_Msk (0x1U << CAN_F11FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB1_FFDB31 CAN_F11FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB1 register ******************/ +#define CAN_F12FB1_FFDB0_Pos (0U) +#define CAN_F12FB1_FFDB0_Msk (0x1U << CAN_F12FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB1_FFDB0 CAN_F12FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB1_FFDB1_Pos (1U) +#define CAN_F12FB1_FFDB1_Msk (0x1U << CAN_F12FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB1_FFDB1 CAN_F12FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB1_FFDB2_Pos (2U) +#define CAN_F12FB1_FFDB2_Msk (0x1U << CAN_F12FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB1_FFDB2 CAN_F12FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB1_FFDB3_Pos (3U) +#define CAN_F12FB1_FFDB3_Msk (0x1U << CAN_F12FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB1_FFDB3 CAN_F12FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB1_FFDB4_Pos (4U) +#define CAN_F12FB1_FFDB4_Msk (0x1U << CAN_F12FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB1_FFDB4 CAN_F12FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB1_FFDB5_Pos (5U) +#define CAN_F12FB1_FFDB5_Msk (0x1U << CAN_F12FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB1_FFDB5 CAN_F12FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB1_FFDB6_Pos (6U) +#define CAN_F12FB1_FFDB6_Msk (0x1U << CAN_F12FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB1_FFDB6 CAN_F12FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB1_FFDB7_Pos (7U) +#define CAN_F12FB1_FFDB7_Msk (0x1U << CAN_F12FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB1_FFDB7 CAN_F12FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB1_FFDB8_Pos (8U) +#define CAN_F12FB1_FFDB8_Msk (0x1U << CAN_F12FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB1_FFDB8 CAN_F12FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB1_FFDB9_Pos (9U) +#define CAN_F12FB1_FFDB9_Msk (0x1U << CAN_F12FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB1_FFDB9 CAN_F12FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB1_FFDB10_Pos (10U) +#define CAN_F12FB1_FFDB10_Msk (0x1U << CAN_F12FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB1_FFDB10 CAN_F12FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB1_FFDB11_Pos (11U) +#define CAN_F12FB1_FFDB11_Msk (0x1U << CAN_F12FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB1_FFDB11 CAN_F12FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB1_FFDB12_Pos (12U) +#define CAN_F12FB1_FFDB12_Msk (0x1U << CAN_F12FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB1_FFDB12 CAN_F12FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB1_FFDB13_Pos (13U) +#define CAN_F12FB1_FFDB13_Msk (0x1U << CAN_F12FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB1_FFDB13 CAN_F12FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB1_FFDB14_Pos (14U) +#define CAN_F12FB1_FFDB14_Msk (0x1U << CAN_F12FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB1_FFDB14 CAN_F12FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB1_FFDB15_Pos (15U) +#define CAN_F12FB1_FFDB15_Msk (0x1U << CAN_F12FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB1_FFDB15 CAN_F12FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB1_FFDB16_Pos (16U) +#define CAN_F12FB1_FFDB16_Msk (0x1U << CAN_F12FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB1_FFDB16 CAN_F12FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB1_FFDB17_Pos (17U) +#define CAN_F12FB1_FFDB17_Msk (0x1U << CAN_F12FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB1_FFDB17 CAN_F12FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB1_FFDB18_Pos (18U) +#define CAN_F12FB1_FFDB18_Msk (0x1U << CAN_F12FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB1_FFDB18 CAN_F12FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB1_FFDB19_Pos (19U) +#define CAN_F12FB1_FFDB19_Msk (0x1U << CAN_F12FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB1_FFDB19 CAN_F12FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB1_FFDB20_Pos (20U) +#define CAN_F12FB1_FFDB20_Msk (0x1U << CAN_F12FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB1_FFDB20 CAN_F12FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB1_FFDB21_Pos (21U) +#define CAN_F12FB1_FFDB21_Msk (0x1U << CAN_F12FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB1_FFDB21 CAN_F12FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB1_FFDB22_Pos (22U) +#define CAN_F12FB1_FFDB22_Msk (0x1U << CAN_F12FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB1_FFDB22 CAN_F12FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB1_FFDB23_Pos (23U) +#define CAN_F12FB1_FFDB23_Msk (0x1U << CAN_F12FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB1_FFDB23 CAN_F12FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB1_FFDB24_Pos (24U) +#define CAN_F12FB1_FFDB24_Msk (0x1U << CAN_F12FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB1_FFDB24 CAN_F12FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB1_FFDB25_Pos (25U) +#define CAN_F12FB1_FFDB25_Msk (0x1U << CAN_F12FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB1_FFDB25 CAN_F12FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB1_FFDB26_Pos (26U) +#define CAN_F12FB1_FFDB26_Msk (0x1U << CAN_F12FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB1_FFDB26 CAN_F12FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB1_FFDB27_Pos (27U) +#define CAN_F12FB1_FFDB27_Msk (0x1U << CAN_F12FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB1_FFDB27 CAN_F12FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB1_FFDB28_Pos (28U) +#define CAN_F12FB1_FFDB28_Msk (0x1U << CAN_F12FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB1_FFDB28 CAN_F12FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB1_FFDB29_Pos (29U) +#define CAN_F12FB1_FFDB29_Msk (0x1U << CAN_F12FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB1_FFDB29 CAN_F12FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB1_FFDB30_Pos (30U) +#define CAN_F12FB1_FFDB30_Msk (0x1U << CAN_F12FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB1_FFDB30 CAN_F12FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB1_FFDB31_Pos (31U) +#define CAN_F12FB1_FFDB31_Msk (0x1U << CAN_F12FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB1_FFDB31 CAN_F12FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB1 register ******************/ +#define CAN_F13FB1_FFDB0_Pos (0U) +#define CAN_F13FB1_FFDB0_Msk (0x1U << CAN_F13FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB1_FFDB0 CAN_F13FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB1_FFDB1_Pos (1U) +#define CAN_F13FB1_FFDB1_Msk (0x1U << CAN_F13FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB1_FFDB1 CAN_F13FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB1_FFDB2_Pos (2U) +#define CAN_F13FB1_FFDB2_Msk (0x1U << CAN_F13FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB1_FFDB2 CAN_F13FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB1_FFDB3_Pos (3U) +#define CAN_F13FB1_FFDB3_Msk (0x1U << CAN_F13FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB1_FFDB3 CAN_F13FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB1_FFDB4_Pos (4U) +#define CAN_F13FB1_FFDB4_Msk (0x1U << CAN_F13FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB1_FFDB4 CAN_F13FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB1_FFDB5_Pos (5U) +#define CAN_F13FB1_FFDB5_Msk (0x1U << CAN_F13FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB1_FFDB5 CAN_F13FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB1_FFDB6_Pos (6U) +#define CAN_F13FB1_FFDB6_Msk (0x1U << CAN_F13FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB1_FFDB6 CAN_F13FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB1_FFDB7_Pos (7U) +#define CAN_F13FB1_FFDB7_Msk (0x1U << CAN_F13FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB1_FFDB7 CAN_F13FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB1_FFDB8_Pos (8U) +#define CAN_F13FB1_FFDB8_Msk (0x1U << CAN_F13FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB1_FFDB8 CAN_F13FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB1_FFDB9_Pos (9U) +#define CAN_F13FB1_FFDB9_Msk (0x1U << CAN_F13FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB1_FFDB9 CAN_F13FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB1_FFDB10_Pos (10U) +#define CAN_F13FB1_FFDB10_Msk (0x1U << CAN_F13FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB1_FFDB10 CAN_F13FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB1_FFDB11_Pos (11U) +#define CAN_F13FB1_FFDB11_Msk (0x1U << CAN_F13FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB1_FFDB11 CAN_F13FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB1_FFDB12_Pos (12U) +#define CAN_F13FB1_FFDB12_Msk (0x1U << CAN_F13FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB1_FFDB12 CAN_F13FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB1_FFDB13_Pos (13U) +#define CAN_F13FB1_FFDB13_Msk (0x1U << CAN_F13FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB1_FFDB13 CAN_F13FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB1_FFDB14_Pos (14U) +#define CAN_F13FB1_FFDB14_Msk (0x1U << CAN_F13FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB1_FFDB14 CAN_F13FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB1_FFDB15_Pos (15U) +#define CAN_F13FB1_FFDB15_Msk (0x1U << CAN_F13FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB1_FFDB15 CAN_F13FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB1_FFDB16_Pos (16U) +#define CAN_F13FB1_FFDB16_Msk (0x1U << CAN_F13FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB1_FFDB16 CAN_F13FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB1_FFDB17_Pos (17U) +#define CAN_F13FB1_FFDB17_Msk (0x1U << CAN_F13FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB1_FFDB17 CAN_F13FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB1_FFDB18_Pos (18U) +#define CAN_F13FB1_FFDB18_Msk (0x1U << CAN_F13FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB1_FFDB18 CAN_F13FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB1_FFDB19_Pos (19U) +#define CAN_F13FB1_FFDB19_Msk (0x1U << CAN_F13FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB1_FFDB19 CAN_F13FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB1_FFDB20_Pos (20U) +#define CAN_F13FB1_FFDB20_Msk (0x1U << CAN_F13FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB1_FFDB20 CAN_F13FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB1_FFDB21_Pos (21U) +#define CAN_F13FB1_FFDB21_Msk (0x1U << CAN_F13FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB1_FFDB21 CAN_F13FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB1_FFDB22_Pos (22U) +#define CAN_F13FB1_FFDB22_Msk (0x1U << CAN_F13FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB1_FFDB22 CAN_F13FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB1_FFDB23_Pos (23U) +#define CAN_F13FB1_FFDB23_Msk (0x1U << CAN_F13FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB1_FFDB23 CAN_F13FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB1_FFDB24_Pos (24U) +#define CAN_F13FB1_FFDB24_Msk (0x1U << CAN_F13FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB1_FFDB24 CAN_F13FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB1_FFDB25_Pos (25U) +#define CAN_F13FB1_FFDB25_Msk (0x1U << CAN_F13FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB1_FFDB25 CAN_F13FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB1_FFDB26_Pos (26U) +#define CAN_F13FB1_FFDB26_Msk (0x1U << CAN_F13FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB1_FFDB26 CAN_F13FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB1_FFDB27_Pos (27U) +#define CAN_F13FB1_FFDB27_Msk (0x1U << CAN_F13FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB1_FFDB27 CAN_F13FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB1_FFDB28_Pos (28U) +#define CAN_F13FB1_FFDB28_Msk (0x1U << CAN_F13FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB1_FFDB28 CAN_F13FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB1_FFDB29_Pos (29U) +#define CAN_F13FB1_FFDB29_Msk (0x1U << CAN_F13FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB1_FFDB29 CAN_F13FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB1_FFDB30_Pos (30U) +#define CAN_F13FB1_FFDB30_Msk (0x1U << CAN_F13FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB1_FFDB30 CAN_F13FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB1_FFDB31_Pos (31U) +#define CAN_F13FB1_FFDB31_Msk (0x1U << CAN_F13FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB1_FFDB31 CAN_F13FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F0FB2 register *******************/ +#define CAN_F0FB2_FFDB0_Pos (0U) +#define CAN_F0FB2_FFDB0_Msk (0x1U << CAN_F0FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB2_FFDB0 CAN_F0FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB2_FFDB1_Pos (1U) +#define CAN_F0FB2_FFDB1_Msk (0x1U << CAN_F0FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB2_FFDB1 CAN_F0FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB2_FFDB2_Pos (2U) +#define CAN_F0FB2_FFDB2_Msk (0x1U << CAN_F0FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB2_FFDB2 CAN_F0FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB2_FFDB3_Pos (3U) +#define CAN_F0FB2_FFDB3_Msk (0x1U << CAN_F0FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB2_FFDB3 CAN_F0FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB2_FFDB4_Pos (4U) +#define CAN_F0FB2_FFDB4_Msk (0x1U << CAN_F0FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB2_FFDB4 CAN_F0FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB2_FFDB5_Pos (5U) +#define CAN_F0FB2_FFDB5_Msk (0x1U << CAN_F0FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB2_FFDB5 CAN_F0FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB2_FFDB6_Pos (6U) +#define CAN_F0FB2_FFDB6_Msk (0x1U << CAN_F0FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB2_FFDB6 CAN_F0FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB2_FFDB7_Pos (7U) +#define CAN_F0FB2_FFDB7_Msk (0x1U << CAN_F0FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB2_FFDB7 CAN_F0FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB2_FFDB8_Pos (8U) +#define CAN_F0FB2_FFDB8_Msk (0x1U << CAN_F0FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB2_FFDB8 CAN_F0FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB2_FFDB9_Pos (9U) +#define CAN_F0FB2_FFDB9_Msk (0x1U << CAN_F0FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB2_FFDB9 CAN_F0FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB2_FFDB10_Pos (10U) +#define CAN_F0FB2_FFDB10_Msk (0x1U << CAN_F0FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB2_FFDB10 CAN_F0FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB2_FFDB11_Pos (11U) +#define CAN_F0FB2_FFDB11_Msk (0x1U << CAN_F0FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB2_FFDB11 CAN_F0FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB2_FFDB12_Pos (12U) +#define CAN_F0FB2_FFDB12_Msk (0x1U << CAN_F0FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB2_FFDB12 CAN_F0FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB2_FFDB13_Pos (13U) +#define CAN_F0FB2_FFDB13_Msk (0x1U << CAN_F0FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB2_FFDB13 CAN_F0FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB2_FFDB14_Pos (14U) +#define CAN_F0FB2_FFDB14_Msk (0x1U << CAN_F0FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB2_FFDB14 CAN_F0FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB2_FFDB15_Pos (15U) +#define CAN_F0FB2_FFDB15_Msk (0x1U << CAN_F0FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB2_FFDB15 CAN_F0FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB2_FFDB16_Pos (16U) +#define CAN_F0FB2_FFDB16_Msk (0x1U << CAN_F0FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB2_FFDB16 CAN_F0FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB2_FFDB17_Pos (17U) +#define CAN_F0FB2_FFDB17_Msk (0x1U << CAN_F0FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB2_FFDB17 CAN_F0FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB2_FFDB18_Pos (18U) +#define CAN_F0FB2_FFDB18_Msk (0x1U << CAN_F0FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB2_FFDB18 CAN_F0FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB2_FFDB19_Pos (19U) +#define CAN_F0FB2_FFDB19_Msk (0x1U << CAN_F0FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB2_FFDB19 CAN_F0FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB2_FFDB20_Pos (20U) +#define CAN_F0FB2_FFDB20_Msk (0x1U << CAN_F0FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB2_FFDB20 CAN_F0FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB2_FFDB21_Pos (21U) +#define CAN_F0FB2_FFDB21_Msk (0x1U << CAN_F0FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB2_FFDB21 CAN_F0FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB2_FFDB22_Pos (22U) +#define CAN_F0FB2_FFDB22_Msk (0x1U << CAN_F0FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB2_FFDB22 CAN_F0FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB2_FFDB23_Pos (23U) +#define CAN_F0FB2_FFDB23_Msk (0x1U << CAN_F0FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB2_FFDB23 CAN_F0FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB2_FFDB24_Pos (24U) +#define CAN_F0FB2_FFDB24_Msk (0x1U << CAN_F0FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB2_FFDB24 CAN_F0FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB2_FFDB25_Pos (25U) +#define CAN_F0FB2_FFDB25_Msk (0x1U << CAN_F0FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB2_FFDB25 CAN_F0FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB2_FFDB26_Pos (26U) +#define CAN_F0FB2_FFDB26_Msk (0x1U << CAN_F0FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB2_FFDB26 CAN_F0FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB2_FFDB27_Pos (27U) +#define CAN_F0FB2_FFDB27_Msk (0x1U << CAN_F0FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB2_FFDB27 CAN_F0FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB2_FFDB28_Pos (28U) +#define CAN_F0FB2_FFDB28_Msk (0x1U << CAN_F0FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB2_FFDB28 CAN_F0FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB2_FFDB29_Pos (29U) +#define CAN_F0FB2_FFDB29_Msk (0x1U << CAN_F0FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB2_FFDB29 CAN_F0FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB2_FFDB30_Pos (30U) +#define CAN_F0FB2_FFDB30_Msk (0x1U << CAN_F0FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB2_FFDB30 CAN_F0FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB2_FFDB31_Pos (31U) +#define CAN_F0FB2_FFDB31_Msk (0x1U << CAN_F0FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB2_FFDB31 CAN_F0FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB2 register *******************/ +#define CAN_F1FB2_FFDB0_Pos (0U) +#define CAN_F1FB2_FFDB0_Msk (0x1U << CAN_F1FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB2_FFDB0 CAN_F1FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB2_FFDB1_Pos (1U) +#define CAN_F1FB2_FFDB1_Msk (0x1U << CAN_F1FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB2_FFDB1 CAN_F1FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB2_FFDB2_Pos (2U) +#define CAN_F1FB2_FFDB2_Msk (0x1U << CAN_F1FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB2_FFDB2 CAN_F1FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB2_FFDB3_Pos (3U) +#define CAN_F1FB2_FFDB3_Msk (0x1U << CAN_F1FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB2_FFDB3 CAN_F1FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB2_FFDB4_Pos (4U) +#define CAN_F1FB2_FFDB4_Msk (0x1U << CAN_F1FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB2_FFDB4 CAN_F1FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB2_FFDB5_Pos (5U) +#define CAN_F1FB2_FFDB5_Msk (0x1U << CAN_F1FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB2_FFDB5 CAN_F1FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB2_FFDB6_Pos (6U) +#define CAN_F1FB2_FFDB6_Msk (0x1U << CAN_F1FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB2_FFDB6 CAN_F1FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB2_FFDB7_Pos (7U) +#define CAN_F1FB2_FFDB7_Msk (0x1U << CAN_F1FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB2_FFDB7 CAN_F1FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB2_FFDB8_Pos (8U) +#define CAN_F1FB2_FFDB8_Msk (0x1U << CAN_F1FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB2_FFDB8 CAN_F1FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB2_FFDB9_Pos (9U) +#define CAN_F1FB2_FFDB9_Msk (0x1U << CAN_F1FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB2_FFDB9 CAN_F1FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB2_FFDB10_Pos (10U) +#define CAN_F1FB2_FFDB10_Msk (0x1U << CAN_F1FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB2_FFDB10 CAN_F1FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB2_FFDB11_Pos (11U) +#define CAN_F1FB2_FFDB11_Msk (0x1U << CAN_F1FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB2_FFDB11 CAN_F1FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB2_FFDB12_Pos (12U) +#define CAN_F1FB2_FFDB12_Msk (0x1U << CAN_F1FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB2_FFDB12 CAN_F1FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB2_FFDB13_Pos (13U) +#define CAN_F1FB2_FFDB13_Msk (0x1U << CAN_F1FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB2_FFDB13 CAN_F1FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB2_FFDB14_Pos (14U) +#define CAN_F1FB2_FFDB14_Msk (0x1U << CAN_F1FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB2_FFDB14 CAN_F1FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB2_FFDB15_Pos (15U) +#define CAN_F1FB2_FFDB15_Msk (0x1U << CAN_F1FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB2_FFDB15 CAN_F1FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB2_FFDB16_Pos (16U) +#define CAN_F1FB2_FFDB16_Msk (0x1U << CAN_F1FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB2_FFDB16 CAN_F1FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB2_FFDB17_Pos (17U) +#define CAN_F1FB2_FFDB17_Msk (0x1U << CAN_F1FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB2_FFDB17 CAN_F1FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB2_FFDB18_Pos (18U) +#define CAN_F1FB2_FFDB18_Msk (0x1U << CAN_F1FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB2_FFDB18 CAN_F1FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB2_FFDB19_Pos (19U) +#define CAN_F1FB2_FFDB19_Msk (0x1U << CAN_F1FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB2_FFDB19 CAN_F1FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB2_FFDB20_Pos (20U) +#define CAN_F1FB2_FFDB20_Msk (0x1U << CAN_F1FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB2_FFDB20 CAN_F1FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB2_FFDB21_Pos (21U) +#define CAN_F1FB2_FFDB21_Msk (0x1U << CAN_F1FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB2_FFDB21 CAN_F1FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB2_FFDB22_Pos (22U) +#define CAN_F1FB2_FFDB22_Msk (0x1U << CAN_F1FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB2_FFDB22 CAN_F1FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB2_FFDB23_Pos (23U) +#define CAN_F1FB2_FFDB23_Msk (0x1U << CAN_F1FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB2_FFDB23 CAN_F1FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB2_FFDB24_Pos (24U) +#define CAN_F1FB2_FFDB24_Msk (0x1U << CAN_F1FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB2_FFDB24 CAN_F1FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB2_FFDB25_Pos (25U) +#define CAN_F1FB2_FFDB25_Msk (0x1U << CAN_F1FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB2_FFDB25 CAN_F1FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB2_FFDB26_Pos (26U) +#define CAN_F1FB2_FFDB26_Msk (0x1U << CAN_F1FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB2_FFDB26 CAN_F1FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB2_FFDB27_Pos (27U) +#define CAN_F1FB2_FFDB27_Msk (0x1U << CAN_F1FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB2_FFDB27 CAN_F1FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB2_FFDB28_Pos (28U) +#define CAN_F1FB2_FFDB28_Msk (0x1U << CAN_F1FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB2_FFDB28 CAN_F1FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB2_FFDB29_Pos (29U) +#define CAN_F1FB2_FFDB29_Msk (0x1U << CAN_F1FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB2_FFDB29 CAN_F1FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB2_FFDB30_Pos (30U) +#define CAN_F1FB2_FFDB30_Msk (0x1U << CAN_F1FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB2_FFDB30 CAN_F1FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB2_FFDB31_Pos (31U) +#define CAN_F1FB2_FFDB31_Msk (0x1U << CAN_F1FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB2_FFDB31 CAN_F1FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB2 register *******************/ +#define CAN_F2FB2_FFDB0_Pos (0U) +#define CAN_F2FB2_FFDB0_Msk (0x1U << CAN_F2FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB2_FFDB0 CAN_F2FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB2_FFDB1_Pos (1U) +#define CAN_F2FB2_FFDB1_Msk (0x1U << CAN_F2FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB2_FFDB1 CAN_F2FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB2_FFDB2_Pos (2U) +#define CAN_F2FB2_FFDB2_Msk (0x1U << CAN_F2FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB2_FFDB2 CAN_F2FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB2_FFDB3_Pos (3U) +#define CAN_F2FB2_FFDB3_Msk (0x1U << CAN_F2FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB2_FFDB3 CAN_F2FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB2_FFDB4_Pos (4U) +#define CAN_F2FB2_FFDB4_Msk (0x1U << CAN_F2FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB2_FFDB4 CAN_F2FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB2_FFDB5_Pos (5U) +#define CAN_F2FB2_FFDB5_Msk (0x1U << CAN_F2FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB2_FFDB5 CAN_F2FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB2_FFDB6_Pos (6U) +#define CAN_F2FB2_FFDB6_Msk (0x1U << CAN_F2FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB2_FFDB6 CAN_F2FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB2_FFDB7_Pos (7U) +#define CAN_F2FB2_FFDB7_Msk (0x1U << CAN_F2FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB2_FFDB7 CAN_F2FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB2_FFDB8_Pos (8U) +#define CAN_F2FB2_FFDB8_Msk (0x1U << CAN_F2FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB2_FFDB8 CAN_F2FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB2_FFDB9_Pos (9U) +#define CAN_F2FB2_FFDB9_Msk (0x1U << CAN_F2FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB2_FFDB9 CAN_F2FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB2_FFDB10_Pos (10U) +#define CAN_F2FB2_FFDB10_Msk (0x1U << CAN_F2FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB2_FFDB10 CAN_F2FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB2_FFDB11_Pos (11U) +#define CAN_F2FB2_FFDB11_Msk (0x1U << CAN_F2FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB2_FFDB11 CAN_F2FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB2_FFDB12_Pos (12U) +#define CAN_F2FB2_FFDB12_Msk (0x1U << CAN_F2FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB2_FFDB12 CAN_F2FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB2_FFDB13_Pos (13U) +#define CAN_F2FB2_FFDB13_Msk (0x1U << CAN_F2FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB2_FFDB13 CAN_F2FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB2_FFDB14_Pos (14U) +#define CAN_F2FB2_FFDB14_Msk (0x1U << CAN_F2FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB2_FFDB14 CAN_F2FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB2_FFDB15_Pos (15U) +#define CAN_F2FB2_FFDB15_Msk (0x1U << CAN_F2FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB2_FFDB15 CAN_F2FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB2_FFDB16_Pos (16U) +#define CAN_F2FB2_FFDB16_Msk (0x1U << CAN_F2FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB2_FFDB16 CAN_F2FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB2_FFDB17_Pos (17U) +#define CAN_F2FB2_FFDB17_Msk (0x1U << CAN_F2FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB2_FFDB17 CAN_F2FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB2_FFDB18_Pos (18U) +#define CAN_F2FB2_FFDB18_Msk (0x1U << CAN_F2FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB2_FFDB18 CAN_F2FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB2_FFDB19_Pos (19U) +#define CAN_F2FB2_FFDB19_Msk (0x1U << CAN_F2FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB2_FFDB19 CAN_F2FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB2_FFDB20_Pos (20U) +#define CAN_F2FB2_FFDB20_Msk (0x1U << CAN_F2FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB2_FFDB20 CAN_F2FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB2_FFDB21_Pos (21U) +#define CAN_F2FB2_FFDB21_Msk (0x1U << CAN_F2FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB2_FFDB21 CAN_F2FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB2_FFDB22_Pos (22U) +#define CAN_F2FB2_FFDB22_Msk (0x1U << CAN_F2FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB2_FFDB22 CAN_F2FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB2_FFDB23_Pos (23U) +#define CAN_F2FB2_FFDB23_Msk (0x1U << CAN_F2FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB2_FFDB23 CAN_F2FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB2_FFDB24_Pos (24U) +#define CAN_F2FB2_FFDB24_Msk (0x1U << CAN_F2FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB2_FFDB24 CAN_F2FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB2_FFDB25_Pos (25U) +#define CAN_F2FB2_FFDB25_Msk (0x1U << CAN_F2FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB2_FFDB25 CAN_F2FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB2_FFDB26_Pos (26U) +#define CAN_F2FB2_FFDB26_Msk (0x1U << CAN_F2FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB2_FFDB26 CAN_F2FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB2_FFDB27_Pos (27U) +#define CAN_F2FB2_FFDB27_Msk (0x1U << CAN_F2FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB2_FFDB27 CAN_F2FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB2_FFDB28_Pos (28U) +#define CAN_F2FB2_FFDB28_Msk (0x1U << CAN_F2FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB2_FFDB28 CAN_F2FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB2_FFDB29_Pos (29U) +#define CAN_F2FB2_FFDB29_Msk (0x1U << CAN_F2FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB2_FFDB29 CAN_F2FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB2_FFDB30_Pos (30U) +#define CAN_F2FB2_FFDB30_Msk (0x1U << CAN_F2FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB2_FFDB30 CAN_F2FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB2_FFDB31_Pos (31U) +#define CAN_F2FB2_FFDB31_Msk (0x1U << CAN_F2FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB2_FFDB31 CAN_F2FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB2 register *******************/ +#define CAN_F3FB2_FFDB0_Pos (0U) +#define CAN_F3FB2_FFDB0_Msk (0x1U << CAN_F3FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB2_FFDB0 CAN_F3FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB2_FFDB1_Pos (1U) +#define CAN_F3FB2_FFDB1_Msk (0x1U << CAN_F3FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB2_FFDB1 CAN_F3FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB2_FFDB2_Pos (2U) +#define CAN_F3FB2_FFDB2_Msk (0x1U << CAN_F3FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB2_FFDB2 CAN_F3FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB2_FFDB3_Pos (3U) +#define CAN_F3FB2_FFDB3_Msk (0x1U << CAN_F3FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB2_FFDB3 CAN_F3FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB2_FFDB4_Pos (4U) +#define CAN_F3FB2_FFDB4_Msk (0x1U << CAN_F3FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB2_FFDB4 CAN_F3FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB2_FFDB5_Pos (5U) +#define CAN_F3FB2_FFDB5_Msk (0x1U << CAN_F3FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB2_FFDB5 CAN_F3FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB2_FFDB6_Pos (6U) +#define CAN_F3FB2_FFDB6_Msk (0x1U << CAN_F3FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB2_FFDB6 CAN_F3FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB2_FFDB7_Pos (7U) +#define CAN_F3FB2_FFDB7_Msk (0x1U << CAN_F3FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB2_FFDB7 CAN_F3FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB2_FFDB8_Pos (8U) +#define CAN_F3FB2_FFDB8_Msk (0x1U << CAN_F3FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB2_FFDB8 CAN_F3FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB2_FFDB9_Pos (9U) +#define CAN_F3FB2_FFDB9_Msk (0x1U << CAN_F3FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB2_FFDB9 CAN_F3FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB2_FFDB10_Pos (10U) +#define CAN_F3FB2_FFDB10_Msk (0x1U << CAN_F3FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB2_FFDB10 CAN_F3FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB2_FFDB11_Pos (11U) +#define CAN_F3FB2_FFDB11_Msk (0x1U << CAN_F3FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB2_FFDB11 CAN_F3FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB2_FFDB12_Pos (12U) +#define CAN_F3FB2_FFDB12_Msk (0x1U << CAN_F3FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB2_FFDB12 CAN_F3FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB2_FFDB13_Pos (13U) +#define CAN_F3FB2_FFDB13_Msk (0x1U << CAN_F3FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB2_FFDB13 CAN_F3FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB2_FFDB14_Pos (14U) +#define CAN_F3FB2_FFDB14_Msk (0x1U << CAN_F3FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB2_FFDB14 CAN_F3FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB2_FFDB15_Pos (15U) +#define CAN_F3FB2_FFDB15_Msk (0x1U << CAN_F3FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB2_FFDB15 CAN_F3FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB2_FFDB16_Pos (16U) +#define CAN_F3FB2_FFDB16_Msk (0x1U << CAN_F3FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB2_FFDB16 CAN_F3FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB2_FFDB17_Pos (17U) +#define CAN_F3FB2_FFDB17_Msk (0x1U << CAN_F3FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB2_FFDB17 CAN_F3FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB2_FFDB18_Pos (18U) +#define CAN_F3FB2_FFDB18_Msk (0x1U << CAN_F3FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB2_FFDB18 CAN_F3FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB2_FFDB19_Pos (19U) +#define CAN_F3FB2_FFDB19_Msk (0x1U << CAN_F3FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB2_FFDB19 CAN_F3FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB2_FFDB20_Pos (20U) +#define CAN_F3FB2_FFDB20_Msk (0x1U << CAN_F3FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB2_FFDB20 CAN_F3FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB2_FFDB21_Pos (21U) +#define CAN_F3FB2_FFDB21_Msk (0x1U << CAN_F3FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB2_FFDB21 CAN_F3FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB2_FFDB22_Pos (22U) +#define CAN_F3FB2_FFDB22_Msk (0x1U << CAN_F3FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB2_FFDB22 CAN_F3FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB2_FFDB23_Pos (23U) +#define CAN_F3FB2_FFDB23_Msk (0x1U << CAN_F3FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB2_FFDB23 CAN_F3FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB2_FFDB24_Pos (24U) +#define CAN_F3FB2_FFDB24_Msk (0x1U << CAN_F3FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB2_FFDB24 CAN_F3FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB2_FFDB25_Pos (25U) +#define CAN_F3FB2_FFDB25_Msk (0x1U << CAN_F3FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB2_FFDB25 CAN_F3FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB2_FFDB26_Pos (26U) +#define CAN_F3FB2_FFDB26_Msk (0x1U << CAN_F3FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB2_FFDB26 CAN_F3FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB2_FFDB27_Pos (27U) +#define CAN_F3FB2_FFDB27_Msk (0x1U << CAN_F3FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB2_FFDB27 CAN_F3FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB2_FFDB28_Pos (28U) +#define CAN_F3FB2_FFDB28_Msk (0x1U << CAN_F3FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB2_FFDB28 CAN_F3FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB2_FFDB29_Pos (29U) +#define CAN_F3FB2_FFDB29_Msk (0x1U << CAN_F3FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB2_FFDB29 CAN_F3FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB2_FFDB30_Pos (30U) +#define CAN_F3FB2_FFDB30_Msk (0x1U << CAN_F3FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB2_FFDB30 CAN_F3FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB2_FFDB31_Pos (31U) +#define CAN_F3FB2_FFDB31_Msk (0x1U << CAN_F3FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB2_FFDB31 CAN_F3FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB2 register *******************/ +#define CAN_F4FB2_FFDB0_Pos (0U) +#define CAN_F4FB2_FFDB0_Msk (0x1U << CAN_F4FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB2_FFDB0 CAN_F4FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB2_FFDB1_Pos (1U) +#define CAN_F4FB2_FFDB1_Msk (0x1U << CAN_F4FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB2_FFDB1 CAN_F4FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB2_FFDB2_Pos (2U) +#define CAN_F4FB2_FFDB2_Msk (0x1U << CAN_F4FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB2_FFDB2 CAN_F4FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB2_FFDB3_Pos (3U) +#define CAN_F4FB2_FFDB3_Msk (0x1U << CAN_F4FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB2_FFDB3 CAN_F4FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB2_FFDB4_Pos (4U) +#define CAN_F4FB2_FFDB4_Msk (0x1U << CAN_F4FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB2_FFDB4 CAN_F4FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB2_FFDB5_Pos (5U) +#define CAN_F4FB2_FFDB5_Msk (0x1U << CAN_F4FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB2_FFDB5 CAN_F4FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB2_FFDB6_Pos (6U) +#define CAN_F4FB2_FFDB6_Msk (0x1U << CAN_F4FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB2_FFDB6 CAN_F4FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB2_FFDB7_Pos (7U) +#define CAN_F4FB2_FFDB7_Msk (0x1U << CAN_F4FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB2_FFDB7 CAN_F4FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB2_FFDB8_Pos (8U) +#define CAN_F4FB2_FFDB8_Msk (0x1U << CAN_F4FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB2_FFDB8 CAN_F4FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB2_FFDB9_Pos (9U) +#define CAN_F4FB2_FFDB9_Msk (0x1U << CAN_F4FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB2_FFDB9 CAN_F4FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB2_FFDB10_Pos (10U) +#define CAN_F4FB2_FFDB10_Msk (0x1U << CAN_F4FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB2_FFDB10 CAN_F4FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB2_FFDB11_Pos (11U) +#define CAN_F4FB2_FFDB11_Msk (0x1U << CAN_F4FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB2_FFDB11 CAN_F4FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB2_FFDB12_Pos (12U) +#define CAN_F4FB2_FFDB12_Msk (0x1U << CAN_F4FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB2_FFDB12 CAN_F4FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB2_FFDB13_Pos (13U) +#define CAN_F4FB2_FFDB13_Msk (0x1U << CAN_F4FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB2_FFDB13 CAN_F4FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB2_FFDB14_Pos (14U) +#define CAN_F4FB2_FFDB14_Msk (0x1U << CAN_F4FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB2_FFDB14 CAN_F4FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB2_FFDB15_Pos (15U) +#define CAN_F4FB2_FFDB15_Msk (0x1U << CAN_F4FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB2_FFDB15 CAN_F4FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB2_FFDB16_Pos (16U) +#define CAN_F4FB2_FFDB16_Msk (0x1U << CAN_F4FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB2_FFDB16 CAN_F4FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB2_FFDB17_Pos (17U) +#define CAN_F4FB2_FFDB17_Msk (0x1U << CAN_F4FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB2_FFDB17 CAN_F4FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB2_FFDB18_Pos (18U) +#define CAN_F4FB2_FFDB18_Msk (0x1U << CAN_F4FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB2_FFDB18 CAN_F4FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB2_FFDB19_Pos (19U) +#define CAN_F4FB2_FFDB19_Msk (0x1U << CAN_F4FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB2_FFDB19 CAN_F4FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB2_FFDB20_Pos (20U) +#define CAN_F4FB2_FFDB20_Msk (0x1U << CAN_F4FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB2_FFDB20 CAN_F4FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB2_FFDB21_Pos (21U) +#define CAN_F4FB2_FFDB21_Msk (0x1U << CAN_F4FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB2_FFDB21 CAN_F4FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB2_FFDB22_Pos (22U) +#define CAN_F4FB2_FFDB22_Msk (0x1U << CAN_F4FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB2_FFDB22 CAN_F4FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB2_FFDB23_Pos (23U) +#define CAN_F4FB2_FFDB23_Msk (0x1U << CAN_F4FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB2_FFDB23 CAN_F4FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB2_FFDB24_Pos (24U) +#define CAN_F4FB2_FFDB24_Msk (0x1U << CAN_F4FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB2_FFDB24 CAN_F4FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB2_FFDB25_Pos (25U) +#define CAN_F4FB2_FFDB25_Msk (0x1U << CAN_F4FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB2_FFDB25 CAN_F4FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB2_FFDB26_Pos (26U) +#define CAN_F4FB2_FFDB26_Msk (0x1U << CAN_F4FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB2_FFDB26 CAN_F4FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB2_FFDB27_Pos (27U) +#define CAN_F4FB2_FFDB27_Msk (0x1U << CAN_F4FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB2_FFDB27 CAN_F4FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB2_FFDB28_Pos (28U) +#define CAN_F4FB2_FFDB28_Msk (0x1U << CAN_F4FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB2_FFDB28 CAN_F4FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB2_FFDB29_Pos (29U) +#define CAN_F4FB2_FFDB29_Msk (0x1U << CAN_F4FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB2_FFDB29 CAN_F4FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB2_FFDB30_Pos (30U) +#define CAN_F4FB2_FFDB30_Msk (0x1U << CAN_F4FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB2_FFDB30 CAN_F4FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB2_FFDB31_Pos (31U) +#define CAN_F4FB2_FFDB31_Msk (0x1U << CAN_F4FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB2_FFDB31 CAN_F4FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB2 register *******************/ +#define CAN_F5FB2_FFDB0_Pos (0U) +#define CAN_F5FB2_FFDB0_Msk (0x1U << CAN_F5FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB2_FFDB0 CAN_F5FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB2_FFDB1_Pos (1U) +#define CAN_F5FB2_FFDB1_Msk (0x1U << CAN_F5FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB2_FFDB1 CAN_F5FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB2_FFDB2_Pos (2U) +#define CAN_F5FB2_FFDB2_Msk (0x1U << CAN_F5FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB2_FFDB2 CAN_F5FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB2_FFDB3_Pos (3U) +#define CAN_F5FB2_FFDB3_Msk (0x1U << CAN_F5FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB2_FFDB3 CAN_F5FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB2_FFDB4_Pos (4U) +#define CAN_F5FB2_FFDB4_Msk (0x1U << CAN_F5FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB2_FFDB4 CAN_F5FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB2_FFDB5_Pos (5U) +#define CAN_F5FB2_FFDB5_Msk (0x1U << CAN_F5FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB2_FFDB5 CAN_F5FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB2_FFDB6_Pos (6U) +#define CAN_F5FB2_FFDB6_Msk (0x1U << CAN_F5FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB2_FFDB6 CAN_F5FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB2_FFDB7_Pos (7U) +#define CAN_F5FB2_FFDB7_Msk (0x1U << CAN_F5FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB2_FFDB7 CAN_F5FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB2_FFDB8_Pos (8U) +#define CAN_F5FB2_FFDB8_Msk (0x1U << CAN_F5FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB2_FFDB8 CAN_F5FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB2_FFDB9_Pos (9U) +#define CAN_F5FB2_FFDB9_Msk (0x1U << CAN_F5FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB2_FFDB9 CAN_F5FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB2_FFDB10_Pos (10U) +#define CAN_F5FB2_FFDB10_Msk (0x1U << CAN_F5FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB2_FFDB10 CAN_F5FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB2_FFDB11_Pos (11U) +#define CAN_F5FB2_FFDB11_Msk (0x1U << CAN_F5FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB2_FFDB11 CAN_F5FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB2_FFDB12_Pos (12U) +#define CAN_F5FB2_FFDB12_Msk (0x1U << CAN_F5FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB2_FFDB12 CAN_F5FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB2_FFDB13_Pos (13U) +#define CAN_F5FB2_FFDB13_Msk (0x1U << CAN_F5FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB2_FFDB13 CAN_F5FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB2_FFDB14_Pos (14U) +#define CAN_F5FB2_FFDB14_Msk (0x1U << CAN_F5FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB2_FFDB14 CAN_F5FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB2_FFDB15_Pos (15U) +#define CAN_F5FB2_FFDB15_Msk (0x1U << CAN_F5FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB2_FFDB15 CAN_F5FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB2_FFDB16_Pos (16U) +#define CAN_F5FB2_FFDB16_Msk (0x1U << CAN_F5FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB2_FFDB16 CAN_F5FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB2_FFDB17_Pos (17U) +#define CAN_F5FB2_FFDB17_Msk (0x1U << CAN_F5FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB2_FFDB17 CAN_F5FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB2_FFDB18_Pos (18U) +#define CAN_F5FB2_FFDB18_Msk (0x1U << CAN_F5FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB2_FFDB18 CAN_F5FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB2_FFDB19_Pos (19U) +#define CAN_F5FB2_FFDB19_Msk (0x1U << CAN_F5FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB2_FFDB19 CAN_F5FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB2_FFDB20_Pos (20U) +#define CAN_F5FB2_FFDB20_Msk (0x1U << CAN_F5FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB2_FFDB20 CAN_F5FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB2_FFDB21_Pos (21U) +#define CAN_F5FB2_FFDB21_Msk (0x1U << CAN_F5FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB2_FFDB21 CAN_F5FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB2_FFDB22_Pos (22U) +#define CAN_F5FB2_FFDB22_Msk (0x1U << CAN_F5FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB2_FFDB22 CAN_F5FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB2_FFDB23_Pos (23U) +#define CAN_F5FB2_FFDB23_Msk (0x1U << CAN_F5FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB2_FFDB23 CAN_F5FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB2_FFDB24_Pos (24U) +#define CAN_F5FB2_FFDB24_Msk (0x1U << CAN_F5FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB2_FFDB24 CAN_F5FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB2_FFDB25_Pos (25U) +#define CAN_F5FB2_FFDB25_Msk (0x1U << CAN_F5FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB2_FFDB25 CAN_F5FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB2_FFDB26_Pos (26U) +#define CAN_F5FB2_FFDB26_Msk (0x1U << CAN_F5FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB2_FFDB26 CAN_F5FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB2_FFDB27_Pos (27U) +#define CAN_F5FB2_FFDB27_Msk (0x1U << CAN_F5FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB2_FFDB27 CAN_F5FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB2_FFDB28_Pos (28U) +#define CAN_F5FB2_FFDB28_Msk (0x1U << CAN_F5FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB2_FFDB28 CAN_F5FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB2_FFDB29_Pos (29U) +#define CAN_F5FB2_FFDB29_Msk (0x1U << CAN_F5FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB2_FFDB29 CAN_F5FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB2_FFDB30_Pos (30U) +#define CAN_F5FB2_FFDB30_Msk (0x1U << CAN_F5FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB2_FFDB30 CAN_F5FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB2_FFDB31_Pos (31U) +#define CAN_F5FB2_FFDB31_Msk (0x1U << CAN_F5FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB2_FFDB31 CAN_F5FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB2 register *******************/ +#define CAN_F6FB2_FFDB0_Pos (0U) +#define CAN_F6FB2_FFDB0_Msk (0x1U << CAN_F6FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB2_FFDB0 CAN_F6FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB2_FFDB1_Pos (1U) +#define CAN_F6FB2_FFDB1_Msk (0x1U << CAN_F6FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB2_FFDB1 CAN_F6FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB2_FFDB2_Pos (2U) +#define CAN_F6FB2_FFDB2_Msk (0x1U << CAN_F6FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB2_FFDB2 CAN_F6FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB2_FFDB3_Pos (3U) +#define CAN_F6FB2_FFDB3_Msk (0x1U << CAN_F6FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB2_FFDB3 CAN_F6FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB2_FFDB4_Pos (4U) +#define CAN_F6FB2_FFDB4_Msk (0x1U << CAN_F6FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB2_FFDB4 CAN_F6FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB2_FFDB5_Pos (5U) +#define CAN_F6FB2_FFDB5_Msk (0x1U << CAN_F6FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB2_FFDB5 CAN_F6FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB2_FFDB6_Pos (6U) +#define CAN_F6FB2_FFDB6_Msk (0x1U << CAN_F6FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB2_FFDB6 CAN_F6FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB2_FFDB7_Pos (7U) +#define CAN_F6FB2_FFDB7_Msk (0x1U << CAN_F6FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB2_FFDB7 CAN_F6FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB2_FFDB8_Pos (8U) +#define CAN_F6FB2_FFDB8_Msk (0x1U << CAN_F6FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB2_FFDB8 CAN_F6FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB2_FFDB9_Pos (9U) +#define CAN_F6FB2_FFDB9_Msk (0x1U << CAN_F6FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB2_FFDB9 CAN_F6FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB2_FFDB10_Pos (10U) +#define CAN_F6FB2_FFDB10_Msk (0x1U << CAN_F6FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB2_FFDB10 CAN_F6FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB2_FFDB11_Pos (11U) +#define CAN_F6FB2_FFDB11_Msk (0x1U << CAN_F6FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB2_FFDB11 CAN_F6FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB2_FFDB12_Pos (12U) +#define CAN_F6FB2_FFDB12_Msk (0x1U << CAN_F6FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB2_FFDB12 CAN_F6FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB2_FFDB13_Pos (13U) +#define CAN_F6FB2_FFDB13_Msk (0x1U << CAN_F6FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB2_FFDB13 CAN_F6FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB2_FFDB14_Pos (14U) +#define CAN_F6FB2_FFDB14_Msk (0x1U << CAN_F6FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB2_FFDB14 CAN_F6FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB2_FFDB15_Pos (15U) +#define CAN_F6FB2_FFDB15_Msk (0x1U << CAN_F6FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB2_FFDB15 CAN_F6FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB2_FFDB16_Pos (16U) +#define CAN_F6FB2_FFDB16_Msk (0x1U << CAN_F6FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB2_FFDB16 CAN_F6FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB2_FFDB17_Pos (17U) +#define CAN_F6FB2_FFDB17_Msk (0x1U << CAN_F6FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB2_FFDB17 CAN_F6FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB2_FFDB18_Pos (18U) +#define CAN_F6FB2_FFDB18_Msk (0x1U << CAN_F6FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB2_FFDB18 CAN_F6FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB2_FFDB19_Pos (19U) +#define CAN_F6FB2_FFDB19_Msk (0x1U << CAN_F6FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB2_FFDB19 CAN_F6FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB2_FFDB20_Pos (20U) +#define CAN_F6FB2_FFDB20_Msk (0x1U << CAN_F6FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB2_FFDB20 CAN_F6FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB2_FFDB21_Pos (21U) +#define CAN_F6FB2_FFDB21_Msk (0x1U << CAN_F6FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB2_FFDB21 CAN_F6FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB2_FFDB22_Pos (22U) +#define CAN_F6FB2_FFDB22_Msk (0x1U << CAN_F6FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB2_FFDB22 CAN_F6FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB2_FFDB23_Pos (23U) +#define CAN_F6FB2_FFDB23_Msk (0x1U << CAN_F6FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB2_FFDB23 CAN_F6FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB2_FFDB24_Pos (24U) +#define CAN_F6FB2_FFDB24_Msk (0x1U << CAN_F6FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB2_FFDB24 CAN_F6FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB2_FFDB25_Pos (25U) +#define CAN_F6FB2_FFDB25_Msk (0x1U << CAN_F6FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB2_FFDB25 CAN_F6FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB2_FFDB26_Pos (26U) +#define CAN_F6FB2_FFDB26_Msk (0x1U << CAN_F6FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB2_FFDB26 CAN_F6FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB2_FFDB27_Pos (27U) +#define CAN_F6FB2_FFDB27_Msk (0x1U << CAN_F6FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB2_FFDB27 CAN_F6FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB2_FFDB28_Pos (28U) +#define CAN_F6FB2_FFDB28_Msk (0x1U << CAN_F6FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB2_FFDB28 CAN_F6FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB2_FFDB29_Pos (29U) +#define CAN_F6FB2_FFDB29_Msk (0x1U << CAN_F6FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB2_FFDB29 CAN_F6FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB2_FFDB30_Pos (30U) +#define CAN_F6FB2_FFDB30_Msk (0x1U << CAN_F6FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB2_FFDB30 CAN_F6FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB2_FFDB31_Pos (31U) +#define CAN_F6FB2_FFDB31_Msk (0x1U << CAN_F6FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB2_FFDB31 CAN_F6FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB2 register *******************/ +#define CAN_F7FB2_FFDB0_Pos (0U) +#define CAN_F7FB2_FFDB0_Msk (0x1U << CAN_F7FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB2_FFDB0 CAN_F7FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB2_FFDB1_Pos (1U) +#define CAN_F7FB2_FFDB1_Msk (0x1U << CAN_F7FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB2_FFDB1 CAN_F7FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB2_FFDB2_Pos (2U) +#define CAN_F7FB2_FFDB2_Msk (0x1U << CAN_F7FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB2_FFDB2 CAN_F7FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB2_FFDB3_Pos (3U) +#define CAN_F7FB2_FFDB3_Msk (0x1U << CAN_F7FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB2_FFDB3 CAN_F7FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB2_FFDB4_Pos (4U) +#define CAN_F7FB2_FFDB4_Msk (0x1U << CAN_F7FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB2_FFDB4 CAN_F7FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB2_FFDB5_Pos (5U) +#define CAN_F7FB2_FFDB5_Msk (0x1U << CAN_F7FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB2_FFDB5 CAN_F7FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB2_FFDB6_Pos (6U) +#define CAN_F7FB2_FFDB6_Msk (0x1U << CAN_F7FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB2_FFDB6 CAN_F7FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB2_FFDB7_Pos (7U) +#define CAN_F7FB2_FFDB7_Msk (0x1U << CAN_F7FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB2_FFDB7 CAN_F7FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB2_FFDB8_Pos (8U) +#define CAN_F7FB2_FFDB8_Msk (0x1U << CAN_F7FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB2_FFDB8 CAN_F7FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB2_FFDB9_Pos (9U) +#define CAN_F7FB2_FFDB9_Msk (0x1U << CAN_F7FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB2_FFDB9 CAN_F7FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB2_FFDB10_Pos (10U) +#define CAN_F7FB2_FFDB10_Msk (0x1U << CAN_F7FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB2_FFDB10 CAN_F7FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB2_FFDB11_Pos (11U) +#define CAN_F7FB2_FFDB11_Msk (0x1U << CAN_F7FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB2_FFDB11 CAN_F7FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB2_FFDB12_Pos (12U) +#define CAN_F7FB2_FFDB12_Msk (0x1U << CAN_F7FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB2_FFDB12 CAN_F7FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB2_FFDB13_Pos (13U) +#define CAN_F7FB2_FFDB13_Msk (0x1U << CAN_F7FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB2_FFDB13 CAN_F7FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB2_FFDB14_Pos (14U) +#define CAN_F7FB2_FFDB14_Msk (0x1U << CAN_F7FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB2_FFDB14 CAN_F7FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB2_FFDB15_Pos (15U) +#define CAN_F7FB2_FFDB15_Msk (0x1U << CAN_F7FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB2_FFDB15 CAN_F7FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB2_FFDB16_Pos (16U) +#define CAN_F7FB2_FFDB16_Msk (0x1U << CAN_F7FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB2_FFDB16 CAN_F7FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB2_FFDB17_Pos (17U) +#define CAN_F7FB2_FFDB17_Msk (0x1U << CAN_F7FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB2_FFDB17 CAN_F7FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB2_FFDB18_Pos (18U) +#define CAN_F7FB2_FFDB18_Msk (0x1U << CAN_F7FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB2_FFDB18 CAN_F7FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB2_FFDB19_Pos (19U) +#define CAN_F7FB2_FFDB19_Msk (0x1U << CAN_F7FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB2_FFDB19 CAN_F7FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB2_FFDB20_Pos (20U) +#define CAN_F7FB2_FFDB20_Msk (0x1U << CAN_F7FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB2_FFDB20 CAN_F7FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB2_FFDB21_Pos (21U) +#define CAN_F7FB2_FFDB21_Msk (0x1U << CAN_F7FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB2_FFDB21 CAN_F7FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB2_FFDB22_Pos (22U) +#define CAN_F7FB2_FFDB22_Msk (0x1U << CAN_F7FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB2_FFDB22 CAN_F7FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB2_FFDB23_Pos (23U) +#define CAN_F7FB2_FFDB23_Msk (0x1U << CAN_F7FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB2_FFDB23 CAN_F7FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB2_FFDB24_Pos (24U) +#define CAN_F7FB2_FFDB24_Msk (0x1U << CAN_F7FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB2_FFDB24 CAN_F7FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB2_FFDB25_Pos (25U) +#define CAN_F7FB2_FFDB25_Msk (0x1U << CAN_F7FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB2_FFDB25 CAN_F7FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB2_FFDB26_Pos (26U) +#define CAN_F7FB2_FFDB26_Msk (0x1U << CAN_F7FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB2_FFDB26 CAN_F7FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB2_FFDB27_Pos (27U) +#define CAN_F7FB2_FFDB27_Msk (0x1U << CAN_F7FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB2_FFDB27 CAN_F7FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB2_FFDB28_Pos (28U) +#define CAN_F7FB2_FFDB28_Msk (0x1U << CAN_F7FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB2_FFDB28 CAN_F7FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB2_FFDB29_Pos (29U) +#define CAN_F7FB2_FFDB29_Msk (0x1U << CAN_F7FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB2_FFDB29 CAN_F7FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB2_FFDB30_Pos (30U) +#define CAN_F7FB2_FFDB30_Msk (0x1U << CAN_F7FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB2_FFDB30 CAN_F7FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB2_FFDB31_Pos (31U) +#define CAN_F7FB2_FFDB31_Msk (0x1U << CAN_F7FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB2_FFDB31 CAN_F7FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB2 register *******************/ +#define CAN_F8FB2_FFDB0_Pos (0U) +#define CAN_F8FB2_FFDB0_Msk (0x1U << CAN_F8FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB2_FFDB0 CAN_F8FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB2_FFDB1_Pos (1U) +#define CAN_F8FB2_FFDB1_Msk (0x1U << CAN_F8FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB2_FFDB1 CAN_F8FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB2_FFDB2_Pos (2U) +#define CAN_F8FB2_FFDB2_Msk (0x1U << CAN_F8FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB2_FFDB2 CAN_F8FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB2_FFDB3_Pos (3U) +#define CAN_F8FB2_FFDB3_Msk (0x1U << CAN_F8FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB2_FFDB3 CAN_F8FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB2_FFDB4_Pos (4U) +#define CAN_F8FB2_FFDB4_Msk (0x1U << CAN_F8FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB2_FFDB4 CAN_F8FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB2_FFDB5_Pos (5U) +#define CAN_F8FB2_FFDB5_Msk (0x1U << CAN_F8FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB2_FFDB5 CAN_F8FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB2_FFDB6_Pos (6U) +#define CAN_F8FB2_FFDB6_Msk (0x1U << CAN_F8FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB2_FFDB6 CAN_F8FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB2_FFDB7_Pos (7U) +#define CAN_F8FB2_FFDB7_Msk (0x1U << CAN_F8FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB2_FFDB7 CAN_F8FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB2_FFDB8_Pos (8U) +#define CAN_F8FB2_FFDB8_Msk (0x1U << CAN_F8FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB2_FFDB8 CAN_F8FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB2_FFDB9_Pos (9U) +#define CAN_F8FB2_FFDB9_Msk (0x1U << CAN_F8FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB2_FFDB9 CAN_F8FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB2_FFDB10_Pos (10U) +#define CAN_F8FB2_FFDB10_Msk (0x1U << CAN_F8FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB2_FFDB10 CAN_F8FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB2_FFDB11_Pos (11U) +#define CAN_F8FB2_FFDB11_Msk (0x1U << CAN_F8FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB2_FFDB11 CAN_F8FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB2_FFDB12_Pos (12U) +#define CAN_F8FB2_FFDB12_Msk (0x1U << CAN_F8FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB2_FFDB12 CAN_F8FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB2_FFDB13_Pos (13U) +#define CAN_F8FB2_FFDB13_Msk (0x1U << CAN_F8FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB2_FFDB13 CAN_F8FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB2_FFDB14_Pos (14U) +#define CAN_F8FB2_FFDB14_Msk (0x1U << CAN_F8FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB2_FFDB14 CAN_F8FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB2_FFDB15_Pos (15U) +#define CAN_F8FB2_FFDB15_Msk (0x1U << CAN_F8FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB2_FFDB15 CAN_F8FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB2_FFDB16_Pos (16U) +#define CAN_F8FB2_FFDB16_Msk (0x1U << CAN_F8FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB2_FFDB16 CAN_F8FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB2_FFDB17_Pos (17U) +#define CAN_F8FB2_FFDB17_Msk (0x1U << CAN_F8FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB2_FFDB17 CAN_F8FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB2_FFDB18_Pos (18U) +#define CAN_F8FB2_FFDB18_Msk (0x1U << CAN_F8FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB2_FFDB18 CAN_F8FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB2_FFDB19_Pos (19U) +#define CAN_F8FB2_FFDB19_Msk (0x1U << CAN_F8FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB2_FFDB19 CAN_F8FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB2_FFDB20_Pos (20U) +#define CAN_F8FB2_FFDB20_Msk (0x1U << CAN_F8FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB2_FFDB20 CAN_F8FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB2_FFDB21_Pos (21U) +#define CAN_F8FB2_FFDB21_Msk (0x1U << CAN_F8FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB2_FFDB21 CAN_F8FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB2_FFDB22_Pos (22U) +#define CAN_F8FB2_FFDB22_Msk (0x1U << CAN_F8FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB2_FFDB22 CAN_F8FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB2_FFDB23_Pos (23U) +#define CAN_F8FB2_FFDB23_Msk (0x1U << CAN_F8FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB2_FFDB23 CAN_F8FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB2_FFDB24_Pos (24U) +#define CAN_F8FB2_FFDB24_Msk (0x1U << CAN_F8FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB2_FFDB24 CAN_F8FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB2_FFDB25_Pos (25U) +#define CAN_F8FB2_FFDB25_Msk (0x1U << CAN_F8FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB2_FFDB25 CAN_F8FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB2_FFDB26_Pos (26U) +#define CAN_F8FB2_FFDB26_Msk (0x1U << CAN_F8FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB2_FFDB26 CAN_F8FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB2_FFDB27_Pos (27U) +#define CAN_F8FB2_FFDB27_Msk (0x1U << CAN_F8FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB2_FFDB27 CAN_F8FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB2_FFDB28_Pos (28U) +#define CAN_F8FB2_FFDB28_Msk (0x1U << CAN_F8FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB2_FFDB28 CAN_F8FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB2_FFDB29_Pos (29U) +#define CAN_F8FB2_FFDB29_Msk (0x1U << CAN_F8FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB2_FFDB29 CAN_F8FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB2_FFDB30_Pos (30U) +#define CAN_F8FB2_FFDB30_Msk (0x1U << CAN_F8FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB2_FFDB30 CAN_F8FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB2_FFDB31_Pos (31U) +#define CAN_F8FB2_FFDB31_Msk (0x1U << CAN_F8FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB2_FFDB31 CAN_F8FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB2 register *******************/ +#define CAN_F9FB2_FFDB0_Pos (0U) +#define CAN_F9FB2_FFDB0_Msk (0x1U << CAN_F9FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB2_FFDB0 CAN_F9FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB2_FFDB1_Pos (1U) +#define CAN_F9FB2_FFDB1_Msk (0x1U << CAN_F9FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB2_FFDB1 CAN_F9FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB2_FFDB2_Pos (2U) +#define CAN_F9FB2_FFDB2_Msk (0x1U << CAN_F9FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB2_FFDB2 CAN_F9FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB2_FFDB3_Pos (3U) +#define CAN_F9FB2_FFDB3_Msk (0x1U << CAN_F9FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB2_FFDB3 CAN_F9FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB2_FFDB4_Pos (4U) +#define CAN_F9FB2_FFDB4_Msk (0x1U << CAN_F9FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB2_FFDB4 CAN_F9FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB2_FFDB5_Pos (5U) +#define CAN_F9FB2_FFDB5_Msk (0x1U << CAN_F9FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB2_FFDB5 CAN_F9FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB2_FFDB6_Pos (6U) +#define CAN_F9FB2_FFDB6_Msk (0x1U << CAN_F9FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB2_FFDB6 CAN_F9FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB2_FFDB7_Pos (7U) +#define CAN_F9FB2_FFDB7_Msk (0x1U << CAN_F9FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB2_FFDB7 CAN_F9FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB2_FFDB8_Pos (8U) +#define CAN_F9FB2_FFDB8_Msk (0x1U << CAN_F9FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB2_FFDB8 CAN_F9FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB2_FFDB9_Pos (9U) +#define CAN_F9FB2_FFDB9_Msk (0x1U << CAN_F9FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB2_FFDB9 CAN_F9FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB2_FFDB10_Pos (10U) +#define CAN_F9FB2_FFDB10_Msk (0x1U << CAN_F9FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB2_FFDB10 CAN_F9FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB2_FFDB11_Pos (11U) +#define CAN_F9FB2_FFDB11_Msk (0x1U << CAN_F9FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB2_FFDB11 CAN_F9FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB2_FFDB12_Pos (12U) +#define CAN_F9FB2_FFDB12_Msk (0x1U << CAN_F9FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB2_FFDB12 CAN_F9FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB2_FFDB13_Pos (13U) +#define CAN_F9FB2_FFDB13_Msk (0x1U << CAN_F9FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB2_FFDB13 CAN_F9FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB2_FFDB14_Pos (14U) +#define CAN_F9FB2_FFDB14_Msk (0x1U << CAN_F9FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB2_FFDB14 CAN_F9FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB2_FFDB15_Pos (15U) +#define CAN_F9FB2_FFDB15_Msk (0x1U << CAN_F9FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB2_FFDB15 CAN_F9FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB2_FFDB16_Pos (16U) +#define CAN_F9FB2_FFDB16_Msk (0x1U << CAN_F9FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB2_FFDB16 CAN_F9FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB2_FFDB17_Pos (17U) +#define CAN_F9FB2_FFDB17_Msk (0x1U << CAN_F9FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB2_FFDB17 CAN_F9FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB2_FFDB18_Pos (18U) +#define CAN_F9FB2_FFDB18_Msk (0x1U << CAN_F9FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB2_FFDB18 CAN_F9FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB2_FFDB19_Pos (19U) +#define CAN_F9FB2_FFDB19_Msk (0x1U << CAN_F9FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB2_FFDB19 CAN_F9FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB2_FFDB20_Pos (20U) +#define CAN_F9FB2_FFDB20_Msk (0x1U << CAN_F9FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB2_FFDB20 CAN_F9FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB2_FFDB21_Pos (21U) +#define CAN_F9FB2_FFDB21_Msk (0x1U << CAN_F9FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB2_FFDB21 CAN_F9FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB2_FFDB22_Pos (22U) +#define CAN_F9FB2_FFDB22_Msk (0x1U << CAN_F9FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB2_FFDB22 CAN_F9FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB2_FFDB23_Pos (23U) +#define CAN_F9FB2_FFDB23_Msk (0x1U << CAN_F9FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB2_FFDB23 CAN_F9FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB2_FFDB24_Pos (24U) +#define CAN_F9FB2_FFDB24_Msk (0x1U << CAN_F9FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB2_FFDB24 CAN_F9FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB2_FFDB25_Pos (25U) +#define CAN_F9FB2_FFDB25_Msk (0x1U << CAN_F9FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB2_FFDB25 CAN_F9FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB2_FFDB26_Pos (26U) +#define CAN_F9FB2_FFDB26_Msk (0x1U << CAN_F9FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB2_FFDB26 CAN_F9FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB2_FFDB27_Pos (27U) +#define CAN_F9FB2_FFDB27_Msk (0x1U << CAN_F9FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB2_FFDB27 CAN_F9FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB2_FFDB28_Pos (28U) +#define CAN_F9FB2_FFDB28_Msk (0x1U << CAN_F9FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB2_FFDB28 CAN_F9FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB2_FFDB29_Pos (29U) +#define CAN_F9FB2_FFDB29_Msk (0x1U << CAN_F9FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB2_FFDB29 CAN_F9FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB2_FFDB30_Pos (30U) +#define CAN_F9FB2_FFDB30_Msk (0x1U << CAN_F9FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB2_FFDB30 CAN_F9FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB2_FFDB31_Pos (31U) +#define CAN_F9FB2_FFDB31_Msk (0x1U << CAN_F9FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB2_FFDB31 CAN_F9FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB2 register ******************/ +#define CAN_F10FB2_FFDB0_Pos (0U) +#define CAN_F10FB2_FFDB0_Msk (0x1U << CAN_F10FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB2_FFDB0 CAN_F10FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB2_FFDB1_Pos (1U) +#define CAN_F10FB2_FFDB1_Msk (0x1U << CAN_F10FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB2_FFDB1 CAN_F10FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB2_FFDB2_Pos (2U) +#define CAN_F10FB2_FFDB2_Msk (0x1U << CAN_F10FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB2_FFDB2 CAN_F10FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB2_FFDB3_Pos (3U) +#define CAN_F10FB2_FFDB3_Msk (0x1U << CAN_F10FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB2_FFDB3 CAN_F10FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB2_FFDB4_Pos (4U) +#define CAN_F10FB2_FFDB4_Msk (0x1U << CAN_F10FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB2_FFDB4 CAN_F10FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB2_FFDB5_Pos (5U) +#define CAN_F10FB2_FFDB5_Msk (0x1U << CAN_F10FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB2_FFDB5 CAN_F10FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB2_FFDB6_Pos (6U) +#define CAN_F10FB2_FFDB6_Msk (0x1U << CAN_F10FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB2_FFDB6 CAN_F10FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB2_FFDB7_Pos (7U) +#define CAN_F10FB2_FFDB7_Msk (0x1U << CAN_F10FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB2_FFDB7 CAN_F10FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB2_FFDB8_Pos (8U) +#define CAN_F10FB2_FFDB8_Msk (0x1U << CAN_F10FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB2_FFDB8 CAN_F10FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB2_FFDB9_Pos (9U) +#define CAN_F10FB2_FFDB9_Msk (0x1U << CAN_F10FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB2_FFDB9 CAN_F10FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB2_FFDB10_Pos (10U) +#define CAN_F10FB2_FFDB10_Msk (0x1U << CAN_F10FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB2_FFDB10 CAN_F10FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB2_FFDB11_Pos (11U) +#define CAN_F10FB2_FFDB11_Msk (0x1U << CAN_F10FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB2_FFDB11 CAN_F10FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB2_FFDB12_Pos (12U) +#define CAN_F10FB2_FFDB12_Msk (0x1U << CAN_F10FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB2_FFDB12 CAN_F10FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB2_FFDB13_Pos (13U) +#define CAN_F10FB2_FFDB13_Msk (0x1U << CAN_F10FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB2_FFDB13 CAN_F10FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB2_FFDB14_Pos (14U) +#define CAN_F10FB2_FFDB14_Msk (0x1U << CAN_F10FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB2_FFDB14 CAN_F10FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB2_FFDB15_Pos (15U) +#define CAN_F10FB2_FFDB15_Msk (0x1U << CAN_F10FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB2_FFDB15 CAN_F10FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB2_FFDB16_Pos (16U) +#define CAN_F10FB2_FFDB16_Msk (0x1U << CAN_F10FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB2_FFDB16 CAN_F10FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB2_FFDB17_Pos (17U) +#define CAN_F10FB2_FFDB17_Msk (0x1U << CAN_F10FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB2_FFDB17 CAN_F10FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB2_FFDB18_Pos (18U) +#define CAN_F10FB2_FFDB18_Msk (0x1U << CAN_F10FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB2_FFDB18 CAN_F10FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB2_FFDB19_Pos (19U) +#define CAN_F10FB2_FFDB19_Msk (0x1U << CAN_F10FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB2_FFDB19 CAN_F10FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB2_FFDB20_Pos (20U) +#define CAN_F10FB2_FFDB20_Msk (0x1U << CAN_F10FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB2_FFDB20 CAN_F10FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB2_FFDB21_Pos (21U) +#define CAN_F10FB2_FFDB21_Msk (0x1U << CAN_F10FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB2_FFDB21 CAN_F10FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB2_FFDB22_Pos (22U) +#define CAN_F10FB2_FFDB22_Msk (0x1U << CAN_F10FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB2_FFDB22 CAN_F10FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB2_FFDB23_Pos (23U) +#define CAN_F10FB2_FFDB23_Msk (0x1U << CAN_F10FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB2_FFDB23 CAN_F10FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB2_FFDB24_Pos (24U) +#define CAN_F10FB2_FFDB24_Msk (0x1U << CAN_F10FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB2_FFDB24 CAN_F10FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB2_FFDB25_Pos (25U) +#define CAN_F10FB2_FFDB25_Msk (0x1U << CAN_F10FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB2_FFDB25 CAN_F10FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB2_FFDB26_Pos (26U) +#define CAN_F10FB2_FFDB26_Msk (0x1U << CAN_F10FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB2_FFDB26 CAN_F10FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB2_FFDB27_Pos (27U) +#define CAN_F10FB2_FFDB27_Msk (0x1U << CAN_F10FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB2_FFDB27 CAN_F10FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB2_FFDB28_Pos (28U) +#define CAN_F10FB2_FFDB28_Msk (0x1U << CAN_F10FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB2_FFDB28 CAN_F10FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB2_FFDB29_Pos (29U) +#define CAN_F10FB2_FFDB29_Msk (0x1U << CAN_F10FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB2_FFDB29 CAN_F10FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB2_FFDB30_Pos (30U) +#define CAN_F10FB2_FFDB30_Msk (0x1U << CAN_F10FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB2_FFDB30 CAN_F10FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB2_FFDB31_Pos (31U) +#define CAN_F10FB2_FFDB31_Msk (0x1U << CAN_F10FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB2_FFDB31 CAN_F10FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB2 register ******************/ +#define CAN_F11FB2_FFDB0_Pos (0U) +#define CAN_F11FB2_FFDB0_Msk (0x1U << CAN_F11FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB2_FFDB0 CAN_F11FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB2_FFDB1_Pos (1U) +#define CAN_F11FB2_FFDB1_Msk (0x1U << CAN_F11FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB2_FFDB1 CAN_F11FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB2_FFDB2_Pos (2U) +#define CAN_F11FB2_FFDB2_Msk (0x1U << CAN_F11FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB2_FFDB2 CAN_F11FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB2_FFDB3_Pos (3U) +#define CAN_F11FB2_FFDB3_Msk (0x1U << CAN_F11FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB2_FFDB3 CAN_F11FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB2_FFDB4_Pos (4U) +#define CAN_F11FB2_FFDB4_Msk (0x1U << CAN_F11FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB2_FFDB4 CAN_F11FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB2_FFDB5_Pos (5U) +#define CAN_F11FB2_FFDB5_Msk (0x1U << CAN_F11FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB2_FFDB5 CAN_F11FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB2_FFDB6_Pos (6U) +#define CAN_F11FB2_FFDB6_Msk (0x1U << CAN_F11FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB2_FFDB6 CAN_F11FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB2_FFDB7_Pos (7U) +#define CAN_F11FB2_FFDB7_Msk (0x1U << CAN_F11FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB2_FFDB7 CAN_F11FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB2_FFDB8_Pos (8U) +#define CAN_F11FB2_FFDB8_Msk (0x1U << CAN_F11FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB2_FFDB8 CAN_F11FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB2_FFDB9_Pos (9U) +#define CAN_F11FB2_FFDB9_Msk (0x1U << CAN_F11FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB2_FFDB9 CAN_F11FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB2_FFDB10_Pos (10U) +#define CAN_F11FB2_FFDB10_Msk (0x1U << CAN_F11FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB2_FFDB10 CAN_F11FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB2_FFDB11_Pos (11U) +#define CAN_F11FB2_FFDB11_Msk (0x1U << CAN_F11FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB2_FFDB11 CAN_F11FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB2_FFDB12_Pos (12U) +#define CAN_F11FB2_FFDB12_Msk (0x1U << CAN_F11FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB2_FFDB12 CAN_F11FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB2_FFDB13_Pos (13U) +#define CAN_F11FB2_FFDB13_Msk (0x1U << CAN_F11FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB2_FFDB13 CAN_F11FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB2_FFDB14_Pos (14U) +#define CAN_F11FB2_FFDB14_Msk (0x1U << CAN_F11FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB2_FFDB14 CAN_F11FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB2_FFDB15_Pos (15U) +#define CAN_F11FB2_FFDB15_Msk (0x1U << CAN_F11FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB2_FFDB15 CAN_F11FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB2_FFDB16_Pos (16U) +#define CAN_F11FB2_FFDB16_Msk (0x1U << CAN_F11FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB2_FFDB16 CAN_F11FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB2_FFDB17_Pos (17U) +#define CAN_F11FB2_FFDB17_Msk (0x1U << CAN_F11FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB2_FFDB17 CAN_F11FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB2_FFDB18_Pos (18U) +#define CAN_F11FB2_FFDB18_Msk (0x1U << CAN_F11FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB2_FFDB18 CAN_F11FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB2_FFDB19_Pos (19U) +#define CAN_F11FB2_FFDB19_Msk (0x1U << CAN_F11FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB2_FFDB19 CAN_F11FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB2_FFDB20_Pos (20U) +#define CAN_F11FB2_FFDB20_Msk (0x1U << CAN_F11FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB2_FFDB20 CAN_F11FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB2_FFDB21_Pos (21U) +#define CAN_F11FB2_FFDB21_Msk (0x1U << CAN_F11FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB2_FFDB21 CAN_F11FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB2_FFDB22_Pos (22U) +#define CAN_F11FB2_FFDB22_Msk (0x1U << CAN_F11FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB2_FFDB22 CAN_F11FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB2_FFDB23_Pos (23U) +#define CAN_F11FB2_FFDB23_Msk (0x1U << CAN_F11FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB2_FFDB23 CAN_F11FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB2_FFDB24_Pos (24U) +#define CAN_F11FB2_FFDB24_Msk (0x1U << CAN_F11FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB2_FFDB24 CAN_F11FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB2_FFDB25_Pos (25U) +#define CAN_F11FB2_FFDB25_Msk (0x1U << CAN_F11FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB2_FFDB25 CAN_F11FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB2_FFDB26_Pos (26U) +#define CAN_F11FB2_FFDB26_Msk (0x1U << CAN_F11FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB2_FFDB26 CAN_F11FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB2_FFDB27_Pos (27U) +#define CAN_F11FB2_FFDB27_Msk (0x1U << CAN_F11FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB2_FFDB27 CAN_F11FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB2_FFDB28_Pos (28U) +#define CAN_F11FB2_FFDB28_Msk (0x1U << CAN_F11FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB2_FFDB28 CAN_F11FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB2_FFDB29_Pos (29U) +#define CAN_F11FB2_FFDB29_Msk (0x1U << CAN_F11FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB2_FFDB29 CAN_F11FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB2_FFDB30_Pos (30U) +#define CAN_F11FB2_FFDB30_Msk (0x1U << CAN_F11FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB2_FFDB30 CAN_F11FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB2_FFDB31_Pos (31U) +#define CAN_F11FB2_FFDB31_Msk (0x1U << CAN_F11FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB2_FFDB31 CAN_F11FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB2 register ******************/ +#define CAN_F12FB2_FFDB0_Pos (0U) +#define CAN_F12FB2_FFDB0_Msk (0x1U << CAN_F12FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB2_FFDB0 CAN_F12FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB2_FFDB1_Pos (1U) +#define CAN_F12FB2_FFDB1_Msk (0x1U << CAN_F12FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB2_FFDB1 CAN_F12FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB2_FFDB2_Pos (2U) +#define CAN_F12FB2_FFDB2_Msk (0x1U << CAN_F12FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB2_FFDB2 CAN_F12FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB2_FFDB3_Pos (3U) +#define CAN_F12FB2_FFDB3_Msk (0x1U << CAN_F12FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB2_FFDB3 CAN_F12FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB2_FFDB4_Pos (4U) +#define CAN_F12FB2_FFDB4_Msk (0x1U << CAN_F12FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB2_FFDB4 CAN_F12FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB2_FFDB5_Pos (5U) +#define CAN_F12FB2_FFDB5_Msk (0x1U << CAN_F12FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB2_FFDB5 CAN_F12FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB2_FFDB6_Pos (6U) +#define CAN_F12FB2_FFDB6_Msk (0x1U << CAN_F12FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB2_FFDB6 CAN_F12FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB2_FFDB7_Pos (7U) +#define CAN_F12FB2_FFDB7_Msk (0x1U << CAN_F12FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB2_FFDB7 CAN_F12FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB2_FFDB8_Pos (8U) +#define CAN_F12FB2_FFDB8_Msk (0x1U << CAN_F12FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB2_FFDB8 CAN_F12FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB2_FFDB9_Pos (9U) +#define CAN_F12FB2_FFDB9_Msk (0x1U << CAN_F12FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB2_FFDB9 CAN_F12FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB2_FFDB10_Pos (10U) +#define CAN_F12FB2_FFDB10_Msk (0x1U << CAN_F12FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB2_FFDB10 CAN_F12FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB2_FFDB11_Pos (11U) +#define CAN_F12FB2_FFDB11_Msk (0x1U << CAN_F12FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB2_FFDB11 CAN_F12FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB2_FFDB12_Pos (12U) +#define CAN_F12FB2_FFDB12_Msk (0x1U << CAN_F12FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB2_FFDB12 CAN_F12FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB2_FFDB13_Pos (13U) +#define CAN_F12FB2_FFDB13_Msk (0x1U << CAN_F12FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB2_FFDB13 CAN_F12FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB2_FFDB14_Pos (14U) +#define CAN_F12FB2_FFDB14_Msk (0x1U << CAN_F12FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB2_FFDB14 CAN_F12FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB2_FFDB15_Pos (15U) +#define CAN_F12FB2_FFDB15_Msk (0x1U << CAN_F12FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB2_FFDB15 CAN_F12FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB2_FFDB16_Pos (16U) +#define CAN_F12FB2_FFDB16_Msk (0x1U << CAN_F12FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB2_FFDB16 CAN_F12FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB2_FFDB17_Pos (17U) +#define CAN_F12FB2_FFDB17_Msk (0x1U << CAN_F12FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB2_FFDB17 CAN_F12FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB2_FFDB18_Pos (18U) +#define CAN_F12FB2_FFDB18_Msk (0x1U << CAN_F12FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB2_FFDB18 CAN_F12FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB2_FFDB19_Pos (19U) +#define CAN_F12FB2_FFDB19_Msk (0x1U << CAN_F12FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB2_FFDB19 CAN_F12FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB2_FFDB20_Pos (20U) +#define CAN_F12FB2_FFDB20_Msk (0x1U << CAN_F12FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB2_FFDB20 CAN_F12FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB2_FFDB21_Pos (21U) +#define CAN_F12FB2_FFDB21_Msk (0x1U << CAN_F12FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB2_FFDB21 CAN_F12FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB2_FFDB22_Pos (22U) +#define CAN_F12FB2_FFDB22_Msk (0x1U << CAN_F12FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB2_FFDB22 CAN_F12FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB2_FFDB23_Pos (23U) +#define CAN_F12FB2_FFDB23_Msk (0x1U << CAN_F12FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB2_FFDB23 CAN_F12FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB2_FFDB24_Pos (24U) +#define CAN_F12FB2_FFDB24_Msk (0x1U << CAN_F12FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB2_FFDB24 CAN_F12FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB2_FFDB25_Pos (25U) +#define CAN_F12FB2_FFDB25_Msk (0x1U << CAN_F12FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB2_FFDB25 CAN_F12FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB2_FFDB26_Pos (26U) +#define CAN_F12FB2_FFDB26_Msk (0x1U << CAN_F12FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB2_FFDB26 CAN_F12FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB2_FFDB27_Pos (27U) +#define CAN_F12FB2_FFDB27_Msk (0x1U << CAN_F12FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB2_FFDB27 CAN_F12FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB2_FFDB28_Pos (28U) +#define CAN_F12FB2_FFDB28_Msk (0x1U << CAN_F12FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB2_FFDB28 CAN_F12FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB2_FFDB29_Pos (29U) +#define CAN_F12FB2_FFDB29_Msk (0x1U << CAN_F12FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB2_FFDB29 CAN_F12FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB2_FFDB30_Pos (30U) +#define CAN_F12FB2_FFDB30_Msk (0x1U << CAN_F12FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB2_FFDB30 CAN_F12FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB2_FFDB31_Pos (31U) +#define CAN_F12FB2_FFDB31_Msk (0x1U << CAN_F12FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB2_FFDB31 CAN_F12FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB2 register ******************/ +#define CAN_F13FB2_FFDB0_Pos (0U) +#define CAN_F13FB2_FFDB0_Msk (0x1U << CAN_F13FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB2_FFDB0 CAN_F13FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB2_FFDB1_Pos (1U) +#define CAN_F13FB2_FFDB1_Msk (0x1U << CAN_F13FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB2_FFDB1 CAN_F13FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB2_FFDB2_Pos (2U) +#define CAN_F13FB2_FFDB2_Msk (0x1U << CAN_F13FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB2_FFDB2 CAN_F13FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB2_FFDB3_Pos (3U) +#define CAN_F13FB2_FFDB3_Msk (0x1U << CAN_F13FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB2_FFDB3 CAN_F13FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB2_FFDB4_Pos (4U) +#define CAN_F13FB2_FFDB4_Msk (0x1U << CAN_F13FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB2_FFDB4 CAN_F13FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB2_FFDB5_Pos (5U) +#define CAN_F13FB2_FFDB5_Msk (0x1U << CAN_F13FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB2_FFDB5 CAN_F13FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB2_FFDB6_Pos (6U) +#define CAN_F13FB2_FFDB6_Msk (0x1U << CAN_F13FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB2_FFDB6 CAN_F13FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB2_FFDB7_Pos (7U) +#define CAN_F13FB2_FFDB7_Msk (0x1U << CAN_F13FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB2_FFDB7 CAN_F13FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB2_FFDB8_Pos (8U) +#define CAN_F13FB2_FFDB8_Msk (0x1U << CAN_F13FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB2_FFDB8 CAN_F13FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB2_FFDB9_Pos (9U) +#define CAN_F13FB2_FFDB9_Msk (0x1U << CAN_F13FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB2_FFDB9 CAN_F13FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB2_FFDB10_Pos (10U) +#define CAN_F13FB2_FFDB10_Msk (0x1U << CAN_F13FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB2_FFDB10 CAN_F13FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB2_FFDB11_Pos (11U) +#define CAN_F13FB2_FFDB11_Msk (0x1U << CAN_F13FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB2_FFDB11 CAN_F13FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB2_FFDB12_Pos (12U) +#define CAN_F13FB2_FFDB12_Msk (0x1U << CAN_F13FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB2_FFDB12 CAN_F13FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB2_FFDB13_Pos (13U) +#define CAN_F13FB2_FFDB13_Msk (0x1U << CAN_F13FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB2_FFDB13 CAN_F13FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB2_FFDB14_Pos (14U) +#define CAN_F13FB2_FFDB14_Msk (0x1U << CAN_F13FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB2_FFDB14 CAN_F13FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB2_FFDB15_Pos (15U) +#define CAN_F13FB2_FFDB15_Msk (0x1U << CAN_F13FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB2_FFDB15 CAN_F13FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB2_FFDB16_Pos (16U) +#define CAN_F13FB2_FFDB16_Msk (0x1U << CAN_F13FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB2_FFDB16 CAN_F13FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB2_FFDB17_Pos (17U) +#define CAN_F13FB2_FFDB17_Msk (0x1U << CAN_F13FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB2_FFDB17 CAN_F13FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB2_FFDB18_Pos (18U) +#define CAN_F13FB2_FFDB18_Msk (0x1U << CAN_F13FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB2_FFDB18 CAN_F13FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB2_FFDB19_Pos (19U) +#define CAN_F13FB2_FFDB19_Msk (0x1U << CAN_F13FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB2_FFDB19 CAN_F13FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB2_FFDB20_Pos (20U) +#define CAN_F13FB2_FFDB20_Msk (0x1U << CAN_F13FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB2_FFDB20 CAN_F13FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB2_FFDB21_Pos (21U) +#define CAN_F13FB2_FFDB21_Msk (0x1U << CAN_F13FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB2_FFDB21 CAN_F13FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB2_FFDB22_Pos (22U) +#define CAN_F13FB2_FFDB22_Msk (0x1U << CAN_F13FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB2_FFDB22 CAN_F13FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB2_FFDB23_Pos (23U) +#define CAN_F13FB2_FFDB23_Msk (0x1U << CAN_F13FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB2_FFDB23 CAN_F13FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB2_FFDB24_Pos (24U) +#define CAN_F13FB2_FFDB24_Msk (0x1U << CAN_F13FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB2_FFDB24 CAN_F13FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB2_FFDB25_Pos (25U) +#define CAN_F13FB2_FFDB25_Msk (0x1U << CAN_F13FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB2_FFDB25 CAN_F13FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB2_FFDB26_Pos (26U) +#define CAN_F13FB2_FFDB26_Msk (0x1U << CAN_F13FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB2_FFDB26 CAN_F13FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB2_FFDB27_Pos (27U) +#define CAN_F13FB2_FFDB27_Msk (0x1U << CAN_F13FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB2_FFDB27 CAN_F13FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB2_FFDB28_Pos (28U) +#define CAN_F13FB2_FFDB28_Msk (0x1U << CAN_F13FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB2_FFDB28 CAN_F13FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB2_FFDB29_Pos (29U) +#define CAN_F13FB2_FFDB29_Msk (0x1U << CAN_F13FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB2_FFDB29 CAN_F13FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB2_FFDB30_Pos (30U) +#define CAN_F13FB2_FFDB30_Msk (0x1U << CAN_F13FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB2_FFDB30 CAN_F13FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB2_FFDB31_Pos (31U) +#define CAN_F13FB2_FFDB31_Msk (0x1U << CAN_F13FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB2_FFDB31 CAN_F13FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/******************************************************************************/ +/* */ +/* SD/SDIO MMC card host interface (SDIO) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SDIO_PWRCTRL register *****************/ +#define SDIO_PWRCTRL_PS_Pos (0U) +#define SDIO_PWRCTRL_PS_Msk (0x3U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000003 */ +#define SDIO_PWRCTRL_PS SDIO_PWRCTRL_PS_Msk /*!< PS[1:0] bits (Power switch) */ +#define SDIO_PWRCTRL_PS_0 (0x1U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000001 */ +#define SDIO_PWRCTRL_PS_1 (0x2U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for SDIO_CLKCTRL register *****************/ +#define SDIO_CLKCTRL_CLKDIV_Msk ((0xFFU << 0) | (0x3U << 15)) /*!< 0x000180FF */ +#define SDIO_CLKCTRL_CLKDIV SDIO_CLKCTRL_CLKDIV_Msk /*!< CLKDIV[9:0] bits (Clock division) */ +#define SDIO_CLKCTRL_CLKOEN_Pos (8U) +#define SDIO_CLKCTRL_CLKOEN_Msk (0x1U << SDIO_CLKCTRL_CLKOEN_Pos) /*!< 0x00000100 */ +#define SDIO_CLKCTRL_CLKOEN SDIO_CLKCTRL_CLKOEN_Msk /*!< Clock output enable */ +#define SDIO_CLKCTRL_PWRSVEN_Pos (9U) +#define SDIO_CLKCTRL_PWRSVEN_Msk (0x1U << SDIO_CLKCTRL_PWRSVEN_Pos) /*!< 0x00000200 */ +#define SDIO_CLKCTRL_PWRSVEN SDIO_CLKCTRL_PWRSVEN_Msk /*!< Power saving mode enable */ +#define SDIO_CLKCTRL_BYPSEN_Pos (10U) +#define SDIO_CLKCTRL_BYPSEN_Msk (0x1U << SDIO_CLKCTRL_BYPSEN_Pos) /*!< 0x00000400 */ +#define SDIO_CLKCTRL_BYPSEN SDIO_CLKCTRL_BYPSEN_Msk /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCTRL_BUSWS_Pos (11U) +#define SDIO_CLKCTRL_BUSWS_Msk (0x3U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001800 */ +#define SDIO_CLKCTRL_BUSWS SDIO_CLKCTRL_BUSWS_Msk /*!< BUSWS[1:0] bits (Bus width selection) */ +#define SDIO_CLKCTRL_BUSWS_0 (0x1U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00000800 */ +#define SDIO_CLKCTRL_BUSWS_1 (0x2U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001000 */ + +#define SDIO_CLKCTRL_CLKEGS_Pos (13U) +#define SDIO_CLKCTRL_CLKEGS_Msk (0x1U << SDIO_CLKCTRL_CLKEGS_Pos) /*!< 0x00002000 */ +#define SDIO_CLKCTRL_CLKEGS SDIO_CLKCTRL_CLKEGS_Msk /*!< SDIO_CK edge selection */ +#define SDIO_CLKCTRL_HFCEN_Pos (14U) +#define SDIO_CLKCTRL_HFCEN_Msk (0x1U << SDIO_CLKCTRL_HFCEN_Pos) /*!< 0x00004000 */ +#define SDIO_CLKCTRL_HFCEN SDIO_CLKCTRL_HFCEN_Msk /*!< Hardware flow control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_ARGU_Pos (0U) +#define SDIO_ARG_ARGU_Msk (0xFFFFFFFFU << SDIO_ARG_ARGU_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_ARG_ARGU SDIO_ARG_ARGU_Msk /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDIDX_Pos (0U) +#define SDIO_CMD_CMDIDX_Msk (0x3FU << SDIO_CMD_CMDIDX_Pos) /*!< 0x0000003F */ +#define SDIO_CMD_CMDIDX SDIO_CMD_CMDIDX_Msk /*!< Command index */ + +#define SDIO_CMD_RSPWT_Pos (6U) +#define SDIO_CMD_RSPWT_Msk (0x3U << SDIO_CMD_RSPWT_Pos) /*!< 0x000000C0 */ +#define SDIO_CMD_RSPWT SDIO_CMD_RSPWT_Msk /*!< RSPWT[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_RSPWT_0 (0x1U << SDIO_CMD_RSPWT_Pos) /*!< 0x00000040 */ +#define SDIO_CMD_RSPWT_1 (0x2U << SDIO_CMD_RSPWT_Pos) /*!< 0x00000080 */ + +#define SDIO_CMD_INTWT_Pos (8U) +#define SDIO_CMD_INTWT_Msk (0x1U << SDIO_CMD_INTWT_Pos) /*!< 0x00000100 */ +#define SDIO_CMD_INTWT SDIO_CMD_INTWT_Msk /*!< CCSM waits for interrupt request */ +#define SDIO_CMD_PNDWT_Pos (9U) +#define SDIO_CMD_PNDWT_Msk (0x1U << SDIO_CMD_PNDWT_Pos) /*!< 0x00000200 */ +#define SDIO_CMD_PNDWT SDIO_CMD_PNDWT_Msk /*!< CCSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CCSMEN_Pos (10U) +#define SDIO_CMD_CCSMEN_Msk (0x1U << SDIO_CMD_CCSMEN_Pos) /*!< 0x00000400 */ +#define SDIO_CMD_CCSMEN SDIO_CMD_CCSMEN_Msk /*!< Command channel state machine (CCSM) enable bit */ +#define SDIO_CMD_IOSUSP_Pos (11U) +#define SDIO_CMD_IOSUSP_Msk (0x1U << SDIO_CMD_IOSUSP_Pos) /*!< 0x00000800 */ +#define SDIO_CMD_IOSUSP SDIO_CMD_IOSUSP_Msk /*!< SD I/O suspend command */ + +/***************** Bit definition for SDIO_RSPCMD register ******************/ +#define SDIO_RSPCMD_RSPCMD_Pos (0U) +#define SDIO_RSPCMD_RSPCMD_Msk (0x3FU << SDIO_RSPCMD_RSPCMD_Pos) /*!< 0x0000003F */ +#define SDIO_RSPCMD_RSPCMD SDIO_RSPCMD_RSPCMD_Msk /*!< Response command index */ + +/****************** Bit definition for SDIO_RSP1 register *******************/ +#define SDIO_RSP1_CARDSTS1_Pos (0U) +#define SDIO_RSP1_CARDSTS1_Msk (0xFFFFFFFFU << SDIO_RSP1_CARDSTS1_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP1_CARDSTS1 SDIO_RSP1_CARDSTS1_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP2 register *******************/ +#define SDIO_RSP2_CARDSTS2_Pos (0U) +#define SDIO_RSP2_CARDSTS2_Msk (0xFFFFFFFFU << SDIO_RSP2_CARDSTS2_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP2_CARDSTS2 SDIO_RSP2_CARDSTS2_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP3 register *******************/ +#define SDIO_RSP3_CARDSTS3_Pos (0U) +#define SDIO_RSP3_CARDSTS3_Msk (0xFFFFFFFFU << SDIO_RSP3_CARDSTS3_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP3_CARDSTS3 SDIO_RSP3_CARDSTS3_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP4 register *******************/ +#define SDIO_RSP4_CARDSTS4_Pos (0U) +#define SDIO_RSP4_CARDSTS4_Msk (0xFFFFFFFFU << SDIO_RSP4_CARDSTS4_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP4_CARDSTS4 SDIO_RSP4_CARDSTS4_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_DTTMR register ******************/ +#define SDIO_DTTMR_TIMEOUT_Pos (0U) +#define SDIO_DTTMR_TIMEOUT_Msk (0xFFFFFFFFU << SDIO_DTTMR_TIMEOUT_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_DTTMR_TIMEOUT SDIO_DTTMR_TIMEOUT_Msk /*!< Data timeout period */ + +/****************** Bit definition for SDIO_DTLEN register ******************/ +#define SDIO_DTLEN_DTLEN_Pos (0U) +#define SDIO_DTLEN_DTLEN_Msk (0x1FFFFFFU << SDIO_DTLEN_DTLEN_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DTLEN_DTLEN SDIO_DTLEN_DTLEN_Msk /*!< Data length value */ + +/***************** Bit definition for SDIO_DTCTRL register ******************/ +#define SDIO_DTCTRL_TFREN_Pos (0U) +#define SDIO_DTCTRL_TFREN_Msk (0x1U << SDIO_DTCTRL_TFREN_Pos) /*!< 0x00000001 */ +#define SDIO_DTCTRL_TFREN SDIO_DTCTRL_TFREN_Msk /*!< Data transfer enabled bit */ +#define SDIO_DTCTRL_TFRDIR_Pos (1U) +#define SDIO_DTCTRL_TFRDIR_Msk (0x1U << SDIO_DTCTRL_TFRDIR_Pos) /*!< 0x00000002 */ +#define SDIO_DTCTRL_TFRDIR SDIO_DTCTRL_TFRDIR_Msk /*!< Data transfer direction selection */ +#define SDIO_DTCTRL_TFRMODE_Pos (2U) +#define SDIO_DTCTRL_TFRMODE_Msk (0x1U << SDIO_DTCTRL_TFRMODE_Pos) /*!< 0x00000004 */ +#define SDIO_DTCTRL_TFRMODE SDIO_DTCTRL_TFRMODE_Msk /*!< Data transfer mode selection */ +#define SDIO_DTCTRL_DMAEN_Pos (3U) +#define SDIO_DTCTRL_DMAEN_Msk (0x1U << SDIO_DTCTRL_DMAEN_Pos) /*!< 0x00000008 */ +#define SDIO_DTCTRL_DMAEN SDIO_DTCTRL_DMAEN_Msk /*!< DMA enable bit */ + +#define SDIO_DTCTRL_BLKSIZE_Pos (4U) +#define SDIO_DTCTRL_BLKSIZE_Msk (0xFU << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x000000F0 */ +#define SDIO_DTCTRL_BLKSIZE SDIO_DTCTRL_BLKSIZE_Msk /*!< BLKSIZE[3:0] bits (Data block size) */ +#define SDIO_DTCTRL_BLKSIZE_0 (0x1U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000010 */ +#define SDIO_DTCTRL_BLKSIZE_1 (0x2U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000020 */ +#define SDIO_DTCTRL_BLKSIZE_2 (0x4U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000040 */ +#define SDIO_DTCTRL_BLKSIZE_3 (0x8U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000080 */ + +#define SDIO_DTCTRL_RDWTSTART_Pos (8U) +#define SDIO_DTCTRL_RDWTSTART_Msk (0x1U << SDIO_DTCTRL_RDWTSTART_Pos) /*!< 0x00000100 */ +#define SDIO_DTCTRL_RDWTSTART SDIO_DTCTRL_RDWTSTART_Msk /*!< Read wait start */ +#define SDIO_DTCTRL_RDWTSTOP_Pos (9U) +#define SDIO_DTCTRL_RDWTSTOP_Msk (0x1U << SDIO_DTCTRL_RDWTSTOP_Pos) /*!< 0x00000200 */ +#define SDIO_DTCTRL_RDWTSTOP SDIO_DTCTRL_RDWTSTOP_Msk /*!< Read wait stop */ +#define SDIO_DTCTRL_RDWTMODE_Pos (10U) +#define SDIO_DTCTRL_RDWTMODE_Msk (0x1U << SDIO_DTCTRL_RDWTMODE_Pos) /*!< 0x00000400 */ +#define SDIO_DTCTRL_RDWTMODE SDIO_DTCTRL_RDWTMODE_Msk /*!< Read wait mode */ +#define SDIO_DTCTRL_IOEN_Pos (11U) +#define SDIO_DTCTRL_IOEN_Msk (0x1U << SDIO_DTCTRL_IOEN_Pos) /*!< 0x00000800 */ +#define SDIO_DTCTRL_IOEN SDIO_DTCTRL_IOEN_Msk /*!< SD I/O enable functions */ + +/***************** Bit definition for SDIO_DTCNTR register ******************/ +#define SDIO_DTCNTR_CNT_Pos (0U) +#define SDIO_DTCNTR_CNT_Msk (0x1FFFFFFU << SDIO_DTCNTR_CNT_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DTCNTR_CNT SDIO_DTCNTR_CNT_Msk /*!< Data count value */ + +/******************* Bit definition for SDIO_STS register *******************/ +#define SDIO_STS_CMDFAIL_Pos (0U) +#define SDIO_STS_CMDFAIL_Msk (0x1U << SDIO_STS_CMDFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_STS_CMDFAIL SDIO_STS_CMDFAIL_Msk /*!< Command response received (CRC check failed) */ +#define SDIO_STS_DTFAIL_Pos (1U) +#define SDIO_STS_DTFAIL_Msk (0x1U << SDIO_STS_DTFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_STS_DTFAIL SDIO_STS_DTFAIL_Msk /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STS_CMDTIMEOUT_Pos (2U) +#define SDIO_STS_CMDTIMEOUT_Msk (0x1U << SDIO_STS_CMDTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_STS_CMDTIMEOUT SDIO_STS_CMDTIMEOUT_Msk /*!< Command response timeout */ +#define SDIO_STS_DTTIMEOUT_Pos (3U) +#define SDIO_STS_DTTIMEOUT_Msk (0x1U << SDIO_STS_DTTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_STS_DTTIMEOUT SDIO_STS_DTTIMEOUT_Msk /*!< Data timeout */ +#define SDIO_STS_TXERRU_Pos (4U) +#define SDIO_STS_TXERRU_Msk (0x1U << SDIO_STS_TXERRU_Pos) /*!< 0x00000010 */ +#define SDIO_STS_TXERRU SDIO_STS_TXERRU_Msk /*!< Transmit BUF underrun error */ +#define SDIO_STS_RXERRO_Pos (5U) +#define SDIO_STS_RXERRO_Msk (0x1U << SDIO_STS_RXERRO_Pos) /*!< 0x00000020 */ +#define SDIO_STS_RXERRO SDIO_STS_RXERRO_Msk /*!< Received BUF overrun error */ +#define SDIO_STS_CMDRSPCMPL_Pos (6U) +#define SDIO_STS_CMDRSPCMPL_Msk (0x1U << SDIO_STS_CMDRSPCMPL_Pos) /*!< 0x00000040 */ +#define SDIO_STS_CMDRSPCMPL SDIO_STS_CMDRSPCMPL_Msk /*!< Command response (CRC check passed) */ +#define SDIO_STS_CMDCMPL_Pos (7U) +#define SDIO_STS_CMDCMPL_Msk (0x1U << SDIO_STS_CMDCMPL_Pos) /*!< 0x00000080 */ +#define SDIO_STS_CMDCMPL SDIO_STS_CMDCMPL_Msk /*!< Command sent (no response required) */ +#define SDIO_STS_DTCMPL_Pos (8U) +#define SDIO_STS_DTCMPL_Msk (0x1U << SDIO_STS_DTCMPL_Pos) /*!< 0x00000100 */ +#define SDIO_STS_DTCMPL SDIO_STS_DTCMPL_Msk /*!< Data end (data counter, SDIO CNT, is zero) */ +#define SDIO_STS_SBITERR_Pos (9U) +#define SDIO_STS_SBITERR_Msk (0x1U << SDIO_STS_SBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_STS_SBITERR SDIO_STS_SBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STS_DTBLKCMPL_Pos (10U) +#define SDIO_STS_DTBLKCMPL_Msk (0x1U << SDIO_STS_DTBLKCMPL_Pos) /*!< 0x00000400 */ +#define SDIO_STS_DTBLKCMPL SDIO_STS_DTBLKCMPL_Msk /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STS_DOCMD_Pos (11U) +#define SDIO_STS_DOCMD_Msk (0x1U << SDIO_STS_DOCMD_Pos) /*!< 0x00000800 */ +#define SDIO_STS_DOCMD SDIO_STS_DOCMD_Msk /*!< Command transfer in progress */ +#define SDIO_STS_DOTX_Pos (12U) +#define SDIO_STS_DOTX_Msk (0x1U << SDIO_STS_DOTX_Pos) /*!< 0x00001000 */ +#define SDIO_STS_DOTX SDIO_STS_DOTX_Msk /*!< Data transmit in progress */ +#define SDIO_STS_DORX_Pos (13U) +#define SDIO_STS_DORX_Msk (0x1U << SDIO_STS_DORX_Pos) /*!< 0x00002000 */ +#define SDIO_STS_DORX SDIO_STS_DORX_Msk /*!< Data receive in progress */ +#define SDIO_STS_TXBUFH_Pos (14U) +#define SDIO_STS_TXBUFH_Msk (0x1U << SDIO_STS_TXBUFH_Pos) /*!< 0x00004000 */ +#define SDIO_STS_TXBUFH SDIO_STS_TXBUFH_Msk /*!< Transmit BUF half empty: At least 8 words can be written to the BUF */ +#define SDIO_STS_RXBUFH_Pos (15U) +#define SDIO_STS_RXBUFH_Msk (0x1U << SDIO_STS_RXBUFH_Pos) /*!< 0x00008000 */ +#define SDIO_STS_RXBUFH SDIO_STS_RXBUFH_Msk /*!< Receive BUF half full: There are at least 8 words in the BUF */ +#define SDIO_STS_TXBUFF_Pos (16U) +#define SDIO_STS_TXBUFF_Msk (0x1U << SDIO_STS_TXBUFF_Pos) /*!< 0x00010000 */ +#define SDIO_STS_TXBUFF SDIO_STS_TXBUFF_Msk /*!< Transmit BUF full */ +#define SDIO_STS_RXBUFF_Pos (17U) +#define SDIO_STS_RXBUFF_Msk (0x1U << SDIO_STS_RXBUFF_Pos) /*!< 0x00020000 */ +#define SDIO_STS_RXBUFF SDIO_STS_RXBUFF_Msk /*!< Receive BUF full */ +#define SDIO_STS_TXBUFE_Pos (18U) +#define SDIO_STS_TXBUFE_Msk (0x1U << SDIO_STS_TXBUFE_Pos) /*!< 0x00040000 */ +#define SDIO_STS_TXBUFE SDIO_STS_TXBUFE_Msk /*!< Transmit BUF empty */ +#define SDIO_STS_RXBUFE_Pos (19U) +#define SDIO_STS_RXBUFE_Msk (0x1U << SDIO_STS_RXBUFE_Pos) /*!< 0x00080000 */ +#define SDIO_STS_RXBUFE SDIO_STS_RXBUFE_Msk /*!< Receive BUF empty */ +#define SDIO_STS_TXBUF_Pos (20U) +#define SDIO_STS_TXBUF_Msk (0x1U << SDIO_STS_TXBUF_Pos) /*!< 0x00100000 */ +#define SDIO_STS_TXBUF SDIO_STS_TXBUF_Msk /*!< Data available in transmit BUF */ +#define SDIO_STS_RXBUF_Pos (21U) +#define SDIO_STS_RXBUF_Msk (0x1U << SDIO_STS_RXBUF_Pos) /*!< 0x00200000 */ +#define SDIO_STS_RXBUF SDIO_STS_RXBUF_Msk /*!< Data available in receive BUF */ +#define SDIO_STS_IOIF_Pos (22U) +#define SDIO_STS_IOIF_Msk (0x1U << SDIO_STS_IOIF_Pos) /*!< 0x00400000 */ +#define SDIO_STS_IOIF SDIO_STS_IOIF_Msk /*!< SD I/O interrupt received */ + +/***************** Bit definition for SDIO_INTCLR register ******************/ +#define SDIO_INTCLR_CMDFAIL_Pos (0U) +#define SDIO_INTCLR_CMDFAIL_Msk (0x1U << SDIO_INTCLR_CMDFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_INTCLR_CMDFAIL SDIO_INTCLR_CMDFAIL_Msk /*!< CMDFAIL flag clear bit */ +#define SDIO_INTCLR_DTFAIL_Pos (1U) +#define SDIO_INTCLR_DTFAIL_Msk (0x1U << SDIO_INTCLR_DTFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_INTCLR_DTFAIL SDIO_INTCLR_DTFAIL_Msk /*!< DTFAIL flag clear bit */ +#define SDIO_INTCLR_CMDTIMEOUT_Pos (2U) +#define SDIO_INTCLR_CMDTIMEOUT_Msk (0x1U << SDIO_INTCLR_CMDTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_INTCLR_CMDTIMEOUT SDIO_INTCLR_CMDTIMEOUT_Msk /*!< CMDTIMEOUT flag clear bit */ +#define SDIO_INTCLR_DTTIMEOUT_Pos (3U) +#define SDIO_INTCLR_DTTIMEOUT_Msk (0x1U << SDIO_INTCLR_DTTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_INTCLR_DTTIMEOUT SDIO_INTCLR_DTTIMEOUT_Msk /*!< DTTIMEOUT flag clear bit */ +#define SDIO_INTCLR_TXERRU_Pos (4U) +#define SDIO_INTCLR_TXERRU_Msk (0x1U << SDIO_INTCLR_TXERRU_Pos) /*!< 0x00000010 */ +#define SDIO_INTCLR_TXERRU SDIO_INTCLR_TXERRU_Msk /*!< TXERRU flag clear bit */ +#define SDIO_INTCLR_RXERRO_Pos (5U) +#define SDIO_INTCLR_RXERRO_Msk (0x1U << SDIO_INTCLR_RXERRO_Pos) /*!< 0x00000020 */ +#define SDIO_INTCLR_RXERRO SDIO_INTCLR_RXERRO_Msk /*!< RXERRO flag clear bit */ +#define SDIO_INTCLR_CMDRSPCMPL_Pos (6U) +#define SDIO_INTCLR_CMDRSPCMPL_Msk (0x1U << SDIO_INTCLR_CMDRSPCMPL_Pos) /*!< 0x00000040 */ +#define SDIO_INTCLR_CMDRSPCMPL SDIO_INTCLR_CMDRSPCMPL_Msk /*!< CMDRSPCMPL flag clear bit */ +#define SDIO_INTCLR_CMDCMPL_Pos (7U) +#define SDIO_INTCLR_CMDCMPL_Msk (0x1U << SDIO_INTCLR_CMDCMPL_Pos) /*!< 0x00000080 */ +#define SDIO_INTCLR_CMDCMPL SDIO_INTCLR_CMDCMPL_Msk /*!< CMDCMPL flag clear bit */ +#define SDIO_INTCLR_DTCMPL_Pos (8U) +#define SDIO_INTCLR_DTCMPL_Msk (0x1U << SDIO_INTCLR_DTCMPL_Pos) /*!< 0x00000100 */ +#define SDIO_INTCLR_DTCMPL SDIO_INTCLR_DTCMPL_Msk /*!< DTCMPL flag clear bit */ +#define SDIO_INTCLR_SBITERR_Pos (9U) +#define SDIO_INTCLR_SBITERR_Msk (0x1U << SDIO_INTCLR_SBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_INTCLR_SBITERR SDIO_INTCLR_SBITERR_Msk /*!< SBITERR flag clear bit */ +#define SDIO_INTCLR_DTBLKCMPL_Pos (10U) +#define SDIO_INTCLR_DTBLKCMPL_Msk (0x1U << SDIO_INTCLR_DTBLKCMPL_Pos) /*!< 0x00000400 */ +#define SDIO_INTCLR_DTBLKCMPL SDIO_INTCLR_DTBLKCMPL_Msk /*!< DTBLKCMPL flag clear bit */ +#define SDIO_INTCLR_IOIF_Pos (22U) +#define SDIO_INTCLR_IOIF_Msk (0x1U << SDIO_INTCLR_IOIF_Pos) /*!< 0x00400000 */ +#define SDIO_INTCLR_IOIF SDIO_INTCLR_IOIF_Msk /*!< SD I/O interface flag clear bit */ + +/****************** Bit definition for SDIO_INTEN register ******************/ +#define SDIO_INTEN_CMDFAILIEN_Pos (0U) +#define SDIO_INTEN_CMDFAILIEN_Msk (0x1U << SDIO_INTEN_CMDFAILIEN_Pos) /*!< 0x00000001 */ +#define SDIO_INTEN_CMDFAILIEN SDIO_INTEN_CMDFAILIEN_Msk /*!< Command CRC fail interrupt enable */ +#define SDIO_INTEN_DTFAILIEN_Pos (1U) +#define SDIO_INTEN_DTFAILIEN_Msk (0x1U << SDIO_INTEN_DTFAILIEN_Pos) /*!< 0x00000002 */ +#define SDIO_INTEN_DTFAILIEN SDIO_INTEN_DTFAILIEN_Msk /*!< Data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTIMEOUTIEN_Pos (2U) +#define SDIO_INTEN_CMDTIMEOUTIEN_Msk (0x1U << SDIO_INTEN_CMDTIMEOUTIEN_Pos) /*!< 0x00000004 */ +#define SDIO_INTEN_CMDTIMEOUTIEN SDIO_INTEN_CMDTIMEOUTIEN_Msk /*!< Command timeout interrupt enable */ +#define SDIO_INTEN_DTTIMEOUTIEN_Pos (3U) +#define SDIO_INTEN_DTTIMEOUTIEN_Msk (0x1U << SDIO_INTEN_DTTIMEOUTIEN_Pos) /*!< 0x00000008 */ +#define SDIO_INTEN_DTTIMEOUTIEN SDIO_INTEN_DTTIMEOUTIEN_Msk /*!< Data timeout interrupt enable */ +#define SDIO_INTEN_TXERRUIEN_Pos (4U) +#define SDIO_INTEN_TXERRUIEN_Msk (0x1U << SDIO_INTEN_TXERRUIEN_Pos) /*!< 0x00000010 */ +#define SDIO_INTEN_TXERRUIEN SDIO_INTEN_TXERRUIEN_Msk /*!< TxBUF underrun error interrupt enable */ +#define SDIO_INTEN_RXERROIEN_Pos (5U) +#define SDIO_INTEN_RXERROIEN_Msk (0x1U << SDIO_INTEN_RXERROIEN_Pos) /*!< 0x00000020 */ +#define SDIO_INTEN_RXERROIEN SDIO_INTEN_RXERROIEN_Msk /*!< RxBUF overrun error interrupt enable */ +#define SDIO_INTEN_CMDRSPCMPLIEN_Pos (6U) +#define SDIO_INTEN_CMDRSPCMPLIEN_Msk (0x1U << SDIO_INTEN_CMDRSPCMPLIEN_Pos) /*!< 0x00000040 */ +#define SDIO_INTEN_CMDRSPCMPLIEN SDIO_INTEN_CMDRSPCMPLIEN_Msk /*!< Command response received interrupt enable */ +#define SDIO_INTEN_CMDCMPLIEN_Pos (7U) +#define SDIO_INTEN_CMDCMPLIEN_Msk (0x1U << SDIO_INTEN_CMDCMPLIEN_Pos) /*!< 0x00000080 */ +#define SDIO_INTEN_CMDCMPLIEN SDIO_INTEN_CMDCMPLIEN_Msk /*!< Command sent interrupt enable */ +#define SDIO_INTEN_DTCMPLIEN_Pos (8U) +#define SDIO_INTEN_DTCMPLIEN_Msk (0x1U << SDIO_INTEN_DTCMPLIEN_Pos) /*!< 0x00000100 */ +#define SDIO_INTEN_DTCMPLIEN SDIO_INTEN_DTCMPLIEN_Msk /*!< Data end interrupt enable */ +#define SDIO_INTEN_SBITERRIEN_Pos (9U) +#define SDIO_INTEN_SBITERRIEN_Msk (0x1U << SDIO_INTEN_SBITERRIEN_Pos) /*!< 0x00000200 */ +#define SDIO_INTEN_SBITERRIEN SDIO_INTEN_SBITERRIEN_Msk /*!< Start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKCMPLIEN_Pos (10U) +#define SDIO_INTEN_DTBLKCMPLIEN_Msk (0x1U << SDIO_INTEN_DTBLKCMPLIEN_Pos) /*!< 0x00000400 */ +#define SDIO_INTEN_DTBLKCMPLIEN SDIO_INTEN_DTBLKCMPLIEN_Msk /*!< Data block end interrupt enable */ +#define SDIO_INTEN_DOCMDIEN_Pos (11U) +#define SDIO_INTEN_DOCMDIEN_Msk (0x1U << SDIO_INTEN_DOCMDIEN_Pos) /*!< 0x00000800 */ +#define SDIO_INTEN_DOCMDIEN SDIO_INTEN_DOCMDIEN_Msk /*!< Command acting interrupt enable */ +#define SDIO_INTEN_DOTXIEN_Pos (12U) +#define SDIO_INTEN_DOTXIEN_Msk (0x1U << SDIO_INTEN_DOTXIEN_Pos) /*!< 0x00001000 */ +#define SDIO_INTEN_DOTXIEN SDIO_INTEN_DOTXIEN_Msk /*!< Data transmit acting interrupt enable */ +#define SDIO_INTEN_DORXIEN_Pos (13U) +#define SDIO_INTEN_DORXIEN_Msk (0x1U << SDIO_INTEN_DORXIEN_Pos) /*!< 0x00002000 */ +#define SDIO_INTEN_DORXIEN SDIO_INTEN_DORXIEN_Msk /*!< Data receive acting interrupt enable */ +#define SDIO_INTEN_TXBUFHIEN_Pos (14U) +#define SDIO_INTEN_TXBUFHIEN_Msk (0x1U << SDIO_INTEN_TXBUFHIEN_Pos) /*!< 0x00004000 */ +#define SDIO_INTEN_TXBUFHIEN SDIO_INTEN_TXBUFHIEN_Msk /*!< TxBUF half empty interrupt enable */ +#define SDIO_INTEN_RXBUFHIEN_Pos (15U) +#define SDIO_INTEN_RXBUFHIEN_Msk (0x1U << SDIO_INTEN_RXBUFHIEN_Pos) /*!< 0x00008000 */ +#define SDIO_INTEN_RXBUFHIEN SDIO_INTEN_RXBUFHIEN_Msk /*!< RxBUF half full interrupt enable */ +#define SDIO_INTEN_TXBUFFIEN_Pos (16U) +#define SDIO_INTEN_TXBUFFIEN_Msk (0x1U << SDIO_INTEN_TXBUFFIEN_Pos) /*!< 0x00010000 */ +#define SDIO_INTEN_TXBUFFIEN SDIO_INTEN_TXBUFFIEN_Msk /*!< TxBUF full interrupt enable */ +#define SDIO_INTEN_RXBUFFIEN_Pos (17U) +#define SDIO_INTEN_RXBUFFIEN_Msk (0x1U << SDIO_INTEN_RXBUFFIEN_Pos) /*!< 0x00020000 */ +#define SDIO_INTEN_RXBUFFIEN SDIO_INTEN_RXBUFFIEN_Msk /*!< RxBUF full interrupt enable */ +#define SDIO_INTEN_TXBUFEIEN_Pos (18U) +#define SDIO_INTEN_TXBUFEIEN_Msk (0x1U << SDIO_INTEN_TXBUFEIEN_Pos) /*!< 0x00040000 */ +#define SDIO_INTEN_TXBUFEIEN SDIO_INTEN_TXBUFEIEN_Msk /*!< TxBUF empty interrupt enable */ +#define SDIO_INTEN_RXBUFEIEN_Pos (19U) +#define SDIO_INTEN_RXBUFEIEN_Msk (0x1U << SDIO_INTEN_RXBUFEIEN_Pos) /*!< 0x00080000 */ +#define SDIO_INTEN_RXBUFEIEN SDIO_INTEN_RXBUFEIEN_Msk /*!< RxBUF empty interrupt enable */ +#define SDIO_INTEN_TXBUFIEN_Pos (20U) +#define SDIO_INTEN_TXBUFIEN_Msk (0x1U << SDIO_INTEN_TXBUFIEN_Pos) /*!< 0x00100000 */ +#define SDIO_INTEN_TXBUFIEN SDIO_INTEN_TXBUFIEN_Msk /*!< Data available in TxBUF interrupt enable */ +#define SDIO_INTEN_RXBUFIEN_Pos (21U) +#define SDIO_INTEN_RXBUFIEN_Msk (0x1U << SDIO_INTEN_RXBUFIEN_Pos) /*!< 0x00200000 */ +#define SDIO_INTEN_RXBUFIEN SDIO_INTEN_RXBUFIEN_Msk /*!< Data available in RxBUF interrupt enable */ +#define SDIO_INTEN_IOIFIEN_Pos (22U) +#define SDIO_INTEN_IOIFIEN_Msk (0x1U << SDIO_INTEN_IOIFIEN_Pos) /*!< 0x00400000 */ +#define SDIO_INTEN_IOIFIEN SDIO_INTEN_IOIFIEN_Msk /*!< SD I/O mode received interrupt enable */ + +/***************** Bit definition for SDIO_BUFCNTR register ******************/ +#define SDIO_BUFCNTR_CNT_Pos (0U) +#define SDIO_BUFCNTR_CNT_Msk (0xFFFFFFU << SDIO_BUFCNTR_CNT_Pos) /*!< 0x00FFFFFF */ +#define SDIO_BUFCNTR_CNT SDIO_BUFCNTR_CNT_Msk /*!< Number of words to be written to or read from the BUF */ + +/******************* Bit definition for SDIO_BUF register *******************/ +#define SDIO_BUF_DT_Pos (0U) +#define SDIO_BUF_DT_Msk (0xFFFFFFFFU << SDIO_BUF_DT_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_BUF_DT SDIO_BUF_DT_Msk /*!< Receive and transmit BUF data */ + +/******************************************************************************/ +/* */ +/* Comparator (COMP) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for CMP_CTRLSTS1 register *****************/ +#define CMP_CTRLSTS1_CMP1EN_Pos (0U) +#define CMP_CTRLSTS1_CMP1EN_Msk (0x1U << CMP_CTRLSTS1_CMP1EN_Pos) /*!< 0x00000001 */ +#define CMP_CTRLSTS1_CMP1EN CMP_CTRLSTS1_CMP1EN_Msk /*!< Comparator 1 enable */ +#define CMP_CTRLSTS1_CMP1IS_Pos (1U) +#define CMP_CTRLSTS1_CMP1IS_Msk (0x1U << CMP_CTRLSTS1_CMP1IS_Pos) /*!< 0x00000002 */ +#define CMP_CTRLSTS1_CMP1IS CMP_CTRLSTS1_CMP1IS_Msk /*!< Comparator 1 input shift */ +#define CMP_CTRLSTS1_CMP1SSEL_Pos (2U) +#define CMP_CTRLSTS1_CMP1SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP1SSEL_Pos) /*!< 0x00000004 */ +#define CMP_CTRLSTS1_CMP1SSEL CMP_CTRLSTS1_CMP1SSEL_Msk /*!< Comparator 1 speed selection */ + +#define CMP_CTRLSTS1_CMP1INVSEL_Pos (4U) +#define CMP_CTRLSTS1_CMP1INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000070 */ +#define CMP_CTRLSTS1_CMP1INVSEL CMP_CTRLSTS1_CMP1INVSEL_Msk /*!< CMP1INVSEL[2:0] bits (Comparator 1 inverting selection) */ +#define CMP_CTRLSTS1_CMP1INVSEL_0 (0x1U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000010 */ +#define CMP_CTRLSTS1_CMP1INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000020 */ +#define CMP_CTRLSTS1_CMP1INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000040 */ + +#define CMP_CTRLSTS1_CMP1TAG_Pos (8U) +#define CMP_CTRLSTS1_CMP1TAG_Msk (0x7U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000700 */ +#define CMP_CTRLSTS1_CMP1TAG CMP_CTRLSTS1_CMP1TAG_Msk /*!< CMP1TAG[2:0] bits (Comparator 1 output target) */ +#define CMP_CTRLSTS1_CMP1TAG_0 (0x1U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000100 */ +#define CMP_CTRLSTS1_CMP1TAG_1 (0x2U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000200 */ +#define CMP_CTRLSTS1_CMP1TAG_2 (0x4U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000400 */ + +#define CMP_CTRLSTS1_CMP1P_Pos (11U) +#define CMP_CTRLSTS1_CMP1P_Msk (0x1U << CMP_CTRLSTS1_CMP1P_Pos) /*!< 0x00000800 */ +#define CMP_CTRLSTS1_CMP1P CMP_CTRLSTS1_CMP1P_Msk /*!< Comparator 1 polarity */ + +#define CMP_CTRLSTS1_CMP1HYST_Pos (12U) +#define CMP_CTRLSTS1_CMP1HYST_Msk (0x3U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00003000 */ +#define CMP_CTRLSTS1_CMP1HYST CMP_CTRLSTS1_CMP1HYST_Msk /*!< CMP1HYST[1:0] bits (Comparator 1 hysteresis) */ +#define CMP_CTRLSTS1_CMP1HYST_0 (0x1U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00001000 */ +#define CMP_CTRLSTS1_CMP1HYST_1 (0x2U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00002000 */ + +#define CMP_CTRLSTS1_CMP1VALUE_Pos (14U) +#define CMP_CTRLSTS1_CMP1VALUE_Msk (0x1U << CMP_CTRLSTS1_CMP1VALUE_Pos) /*!< 0x00004000 */ +#define CMP_CTRLSTS1_CMP1VALUE CMP_CTRLSTS1_CMP1VALUE_Msk /*!< Comparator 1 output value */ +#define CMP_CTRLSTS1_CMP1WP_Pos (15U) +#define CMP_CTRLSTS1_CMP1WP_Msk (0x1U << CMP_CTRLSTS1_CMP1WP_Pos) /*!< 0x00008000 */ +#define CMP_CTRLSTS1_CMP1WP CMP_CTRLSTS1_CMP1WP_Msk /*!< Comparator 1 write protect */ +#define CMP_CTRLSTS1_CMP2EN_Pos (16U) +#define CMP_CTRLSTS1_CMP2EN_Msk (0x1U << CMP_CTRLSTS1_CMP2EN_Pos) /*!< 0x00010000 */ +#define CMP_CTRLSTS1_CMP2EN CMP_CTRLSTS1_CMP2EN_Msk /*!< Comparator 2 enable */ +#define CMP_CTRLSTS1_CMP2SSEL_Pos (18U) +#define CMP_CTRLSTS1_CMP2SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP2SSEL_Pos) /*!< 0x00040000 */ +#define CMP_CTRLSTS1_CMP2SSEL CMP_CTRLSTS1_CMP2SSEL_Msk /*!< Comparator 2 speed selection */ + +#define CMP_CTRLSTS1_CMP2INVSEL_Pos (20U) +#define CMP_CTRLSTS1_CMP2INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00700000 */ +#define CMP_CTRLSTS1_CMP2INVSEL CMP_CTRLSTS1_CMP2INVSEL_Msk /*!< CMP2INVSEL[2:0] bits (Comparator 2 inverting selection) */ +#define CMP_CTRLSTS1_CMP2INVSEL_0 (0x1U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00100000 */ +#define CMP_CTRLSTS1_CMP2INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00200000 */ +#define CMP_CTRLSTS1_CMP2INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00400000 */ + +#define CMP_CTRLSTS1_DCMPEN_Pos (23U) +#define CMP_CTRLSTS1_DCMPEN_Msk (0x1U << CMP_CTRLSTS1_DCMPEN_Pos) /*!< 0x00800000 */ +#define CMP_CTRLSTS1_DCMPEN CMP_CTRLSTS1_DCMPEN_Msk /*!< Double comparator mode enable */ + +#define CMP_CTRLSTS1_CMP2TAG_Pos (24U) +#define CMP_CTRLSTS1_CMP2TAG_Msk (0x7U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x07000000 */ +#define CMP_CTRLSTS1_CMP2TAG CMP_CTRLSTS1_CMP2TAG_Msk /*!< CMP2TAG[2:0] bits (Comparator 2 output target) */ +#define CMP_CTRLSTS1_CMP2TAG_0 (0x1U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x01000000 */ +#define CMP_CTRLSTS1_CMP2TAG_1 (0x2U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x02000000 */ +#define CMP_CTRLSTS1_CMP2TAG_2 (0x4U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x04000000 */ + +#define CMP_CTRLSTS1_CMP2P_Pos (27U) +#define CMP_CTRLSTS1_CMP2P_Msk (0x1U << CMP_CTRLSTS1_CMP2P_Pos) /*!< 0x08000000 */ +#define CMP_CTRLSTS1_CMP2P CMP_CTRLSTS1_CMP2P_Msk /*!< Comparator 2 polarity */ + +#define CMP_CTRLSTS1_CMP2HYST_Pos (28U) +#define CMP_CTRLSTS1_CMP2HYST_Msk (0x3U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x30000000 */ +#define CMP_CTRLSTS1_CMP2HYST CMP_CTRLSTS1_CMP2HYST_Msk /*!< CMP2HYST[1:0] bits (Comparator 2 hysteresis) */ +#define CMP_CTRLSTS1_CMP2HYST_0 (0x1U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x10000000 */ +#define CMP_CTRLSTS1_CMP2HYST_1 (0x2U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x20000000 */ + +#define CMP_CTRLSTS1_CMP2VALUE_Pos (30U) +#define CMP_CTRLSTS1_CMP2VALUE_Msk (0x1U << CMP_CTRLSTS1_CMP2VALUE_Pos) /*!< 0x40000000 */ +#define CMP_CTRLSTS1_CMP2VALUE CMP_CTRLSTS1_CMP2VALUE_Msk /*!< Comparator 2 output value */ +#define CMP_CTRLSTS1_CMP2WP_Pos (31U) +#define CMP_CTRLSTS1_CMP2WP_Msk (0x1U << CMP_CTRLSTS1_CMP2WP_Pos) /*!< 0x80000000 */ +#define CMP_CTRLSTS1_CMP2WP CMP_CTRLSTS1_CMP2WP_Msk /*!< Comparator 2 write protect */ + +/***************** Bit definition for CMP_CTRLSTS2 register *****************/ +#define CMP_CTRLSTS2_CMP1NINVSEL_Pos (0U) +#define CMP_CTRLSTS2_CMP1NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000003 */ +#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< Comparator 1 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP1NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000001 */ +#define CMP_CTRLSTS2_CMP1NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000002 */ + +#define CMP_CTRLSTS2_CMP2NINVSEL_Pos (16U) +#define CMP_CTRLSTS2_CMP2NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00030000 */ +#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< Comparator 2 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP2NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00010000 */ +#define CMP_CTRLSTS2_CMP2NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00020000 */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DEBUG) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DEBUG_IDCODE register *****************/ +#define DEBUG_IDCODE_PID_Pos (0U) +#define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ +#define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ +#define DEBUG_IDCODE_PID_0 (0x00000001U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000001 */ +#define DEBUG_IDCODE_PID_1 (0x00000002U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000002 */ +#define DEBUG_IDCODE_PID_2 (0x00000004U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000004 */ +#define DEBUG_IDCODE_PID_3 (0x00000008U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000008 */ +#define DEBUG_IDCODE_PID_4 (0x00000010U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000010 */ +#define DEBUG_IDCODE_PID_5 (0x00000020U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000020 */ +#define DEBUG_IDCODE_PID_6 (0x00000040U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000040 */ +#define DEBUG_IDCODE_PID_7 (0x00000080U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000080 */ +#define DEBUG_IDCODE_PID_8 (0x00000100U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000100 */ +#define DEBUG_IDCODE_PID_9 (0x00000200U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000200 */ +#define DEBUG_IDCODE_PID_10 (0x00000400U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000400 */ +#define DEBUG_IDCODE_PID_11 (0x00000800U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000800 */ +#define DEBUG_IDCODE_PID_12 (0x00001000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00001000 */ +#define DEBUG_IDCODE_PID_13 (0x00002000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00002000 */ +#define DEBUG_IDCODE_PID_14 (0x00004000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00004000 */ +#define DEBUG_IDCODE_PID_15 (0x00008000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00008000 */ +#define DEBUG_IDCODE_PID_16 (0x00010000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00010000 */ +#define DEBUG_IDCODE_PID_17 (0x00020000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00020000 */ +#define DEBUG_IDCODE_PID_18 (0x00040000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00040000 */ +#define DEBUG_IDCODE_PID_19 (0x00080000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00080000 */ +#define DEBUG_IDCODE_PID_20 (0x00100000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00100000 */ +#define DEBUG_IDCODE_PID_21 (0x00200000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00200000 */ +#define DEBUG_IDCODE_PID_22 (0x00400000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00400000 */ +#define DEBUG_IDCODE_PID_23 (0x00800000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00800000 */ +#define DEBUG_IDCODE_PID_24 (0x01000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x01000000 */ +#define DEBUG_IDCODE_PID_25 (0x02000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x02000000 */ +#define DEBUG_IDCODE_PID_26 (0x04000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x04000000 */ +#define DEBUG_IDCODE_PID_27 (0x08000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x08000000 */ +#define DEBUG_IDCODE_PID_28 (0x10000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x10000000 */ +#define DEBUG_IDCODE_PID_29 (0x20000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x20000000 */ +#define DEBUG_IDCODE_PID_30 (0x40000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x40000000 */ +#define DEBUG_IDCODE_PID_31 (0x80000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DEBUG_CTRL register ******************/ +#define DEBUG_CTRL_SLEEP_DEBUG_Pos (0U) +#define DEBUG_CTRL_SLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_SLEEP_DEBUG_Pos) /*!< 0x00000001 */ +#define DEBUG_CTRL_SLEEP_DEBUG DEBUG_CTRL_SLEEP_DEBUG_Msk /*!< Debug Sleep mode control bit */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos) +#define DEBUG_CTRL_DEEPSLEEP_DEBUG DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk /*!< Debug Deep sleep mode control bit */ +#define DEBUG_CTRL_STANDBY_DEBUG_Pos (2U) +#define DEBUG_CTRL_STANDBY_DEBUG_Msk (0x1U << DEBUG_CTRL_STANDBY_DEBUG_Pos) /*!< 0x00000004 */ +#define DEBUG_CTRL_STANDBY_DEBUG DEBUG_CTRL_STANDBY_DEBUG_Msk /*!< Debug Standby mode control bit */ +#define DEBUG_CTRL_TRACE_IOEN_Pos (5U) +#define DEBUG_CTRL_TRACE_IOEN_Msk (0x1U << DEBUG_CTRL_TRACE_IOEN_Pos) /*!< 0x00000020 */ +#define DEBUG_CTRL_TRACE_IOEN DEBUG_CTRL_TRACE_IOEN_Msk /*!< Trace pin assignment enable */ + +#define DEBUG_CTRL_TRACE_MODE_Pos (6U) +#define DEBUG_CTRL_TRACE_MODE_Msk (0x3U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DEBUG_CTRL_TRACE_MODE DEBUG_CTRL_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace pin assignment control) */ +#define DEBUG_CTRL_TRACE_MODE_0 (0x1U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DEBUG_CTRL_TRACE_MODE_1 (0x2U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x00000080 */ + +#define DEBUG_CTRL_WDT_PAUSE_Pos (8U) +#define DEBUG_CTRL_WDT_PAUSE_Msk (0x1U << DEBUG_CTRL_WDT_PAUSE_Pos) /*!< 0x00000100 */ +#define DEBUG_CTRL_WDT_PAUSE DEBUG_CTRL_WDT_PAUSE_Msk /*!< Watchdog pause control bit */ +#define DEBUG_CTRL_WWDT_PAUSE_Pos (9U) +#define DEBUG_CTRL_WWDT_PAUSE_Msk (0x1U << DEBUG_CTRL_WWDT_PAUSE_Pos) /*!< 0x00000200 */ +#define DEBUG_CTRL_WWDT_PAUSE DEBUG_CTRL_WWDT_PAUSE_Msk /*!< Window watchdog pause control bit */ +#define DEBUG_CTRL_TMR1_PAUSE_Pos (10U) +#define DEBUG_CTRL_TMR1_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR1_PAUSE_Pos) /*!< 0x00000400 */ +#define DEBUG_CTRL_TMR1_PAUSE DEBUG_CTRL_TMR1_PAUSE_Msk /*!< TMR1 pause control bit */ +#define DEBUG_CTRL_TMR2_PAUSE_Pos (11U) +#define DEBUG_CTRL_TMR2_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR2_PAUSE_Pos) /*!< 0x00000800 */ +#define DEBUG_CTRL_TMR2_PAUSE DEBUG_CTRL_TMR2_PAUSE_Msk /*!< TMR2 pause control bit */ +#define DEBUG_CTRL_TMR3_PAUSE_Pos (12U) +#define DEBUG_CTRL_TMR3_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR3_PAUSE_Pos) /*!< 0x00001000 */ +#define DEBUG_CTRL_TMR3_PAUSE DEBUG_CTRL_TMR3_PAUSE_Msk /*!< TMR3 pause control bit */ +#define DEBUG_CTRL_TMR4_PAUSE_Pos (13U) +#define DEBUG_CTRL_TMR4_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR4_PAUSE_Pos) /*!< 0x00002000 */ +#define DEBUG_CTRL_TMR4_PAUSE DEBUG_CTRL_TMR4_PAUSE_Msk /*!< TMR4 pause control bit */ +#define DEBUG_CTRL_CAN1_PAUSE_Pos (14U) +#define DEBUG_CTRL_CAN1_PAUSE_Msk (0x1U << DEBUG_CTRL_CAN1_PAUSE_Pos) /*!< 0x00004000 */ +#define DEBUG_CTRL_CAN1_PAUSE DEBUG_CTRL_CAN1_PAUSE_Msk /*!< CAN1 pause control bit */ +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Pos (15U) /*!< 0x00008000 */ +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Pos) +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 pause control bit */ +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Pos (16U) /*!< 0x00010000 */ +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Pos) +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Msk /*!< I2C2 pause control bit */ +#define DEBUG_CTRL_TMR5_PAUSE_Pos (18U) +#define DEBUG_CTRL_TMR5_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR5_PAUSE_Pos) /*!< 0x00040000 */ +#define DEBUG_CTRL_TMR5_PAUSE DEBUG_CTRL_TMR5_PAUSE_Msk /*!< TMR5 pause control bit */ +#define DEBUG_CTRL_TMR9_PAUSE_Pos (28U) +#define DEBUG_CTRL_TMR9_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR9_PAUSE_Pos) /*!< 0x10000000 */ +#define DEBUG_CTRL_TMR9_PAUSE DEBUG_CTRL_TMR9_PAUSE_Msk /*!< TMR9 pause control bit */ +#define DEBUG_CTRL_TMR10_PAUSE_Pos (29U) +#define DEBUG_CTRL_TMR10_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR10_PAUSE_Pos) /*!< 0x20000000 */ +#define DEBUG_CTRL_TMR10_PAUSE DEBUG_CTRL_TMR10_PAUSE_Msk /*!< TMR10 pause control bit */ +#define DEBUG_CTRL_TMR11_PAUSE_Pos (30U) +#define DEBUG_CTRL_TMR11_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR11_PAUSE_Pos) /*!< 0x40000000 */ +#define DEBUG_CTRL_TMR11_PAUSE DEBUG_CTRL_TMR11_PAUSE_Msk /*!< TMR11 pause control bit */ + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +/******************************* CAN Instances ********************************/ +#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + +/******************************* DMA Instances ********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ + ((INSTANCE) == DMA1_Channel2) || \ + ((INSTANCE) == DMA1_Channel3) || \ + ((INSTANCE) == DMA1_Channel4) || \ + ((INSTANCE) == DMA1_Channel5) || \ + ((INSTANCE) == DMA1_Channel6) || \ + ((INSTANCE) == DMA1_Channel7) || \ + ((INSTANCE) == DMA2_Channel1) || \ + ((INSTANCE) == DMA2_Channel2) || \ + ((INSTANCE) == DMA2_Channel3) || \ + ((INSTANCE) == DMA2_Channel4) || \ + ((INSTANCE) == DMA2_Channel5) || \ + ((INSTANCE) == DMA2_Channel6) || \ + ((INSTANCE) == DMA2_Channel7)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOF)) + +/********************* IOMUX Multiplex Function Instances *********************/ +#define IS_IOMUX_ALL_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************* I2C Instances ********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE + +/******************************* I2S Instances ********************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/******************************* WDT Instances ********************************/ +#define IS_WDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WDT) + +/******************************* SDIO Instances *******************************/ +#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) + +/******************************* SPI Instances ********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/**************************** START TMR Instances *****************************/ +/******************************* TMR Instances ********************************/ +#define IS_TMR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_C1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_C2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_C3_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_C4_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_CLOCKSOURCE_EXTMODE1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_CLOCKSOURCE_EXTMODE2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_CLOCKSOURCE_TRGIN_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_CLOCKSOURCE_ISX_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_XOR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_MASTER_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_SLAVE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_DMABURST_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_BREAK_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_CX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TMR1) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR2) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR3) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR4) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR5) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR9) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2))) \ + || \ + (((INSTANCE) == TMR10) && \ + (((CHANNEL) == TMR_CHANNEL_1))) \ + || \ + (((INSTANCE) == TMR11) && \ + (((CHANNEL) == TMR_CHANNEL_1)))) + +#define IS_TMR_CXN_INSTANCE(INSTANCE, CHANNEL) \ + (((INSTANCE) == TMR1) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3))) + +#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_DMA_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_DMA_CC_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1)) + +#define IS_TMR_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE) 0U + +/***************************** END TMR Instances ******************************/ + +/********************* USART Instances : Synchronous mode *********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/********************* UART Instances : Asynchronous mode *********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/********************* UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/************************* UART Instances : LIN mode **************************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/******************* UART Instances : Hardware Flow control *******************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/********************* UART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/************************* UART Instances : IRDA mode *************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/******************* UART Instances : Multi-Processor mode ********************/ +#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/******************** UART Instances : DMA mode available *********************/ +#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/******************************* ERTC Instances *******************************/ +#define IS_ERTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ERTC) + +/******************************* WWDT Instances *******************************/ +#define IS_WWDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDT) + +#define CRM_HEXT_MIN 4000000U +#define CRM_HEXT_MAX 25000000U + +#define CRM_MAX_FREQUENCY 150000000U + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F415Kx_H */ + +/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h new file mode 100644 index 0000000000..7339296261 --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -0,0 +1,10540 @@ +/** + ****************************************************************************** + * @file at32f415rx.h + * @author Artery Technology & HorrorTroll & Zhaqian + * @version v2.1.1 + * @date 26-October-2023 + * @brief AT32F415Rx header file. + * + ****************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f415rx + * @{ + */ + +#ifndef __AT32F415Rx_H +#define __AT32F415Rx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief CMSIS Device version number V2.1.1 + */ +#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ +#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ + |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ + |(__AT32F415_LIBRARY_VERSION_MINOR << 8 )\ + |(__AT32F415_LIBRARY_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< AT32 devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< AT32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /*!< AT32 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief AT32F415Rx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector Interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** AT32 specific Interrupt Numbers **********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ + PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ + ERTC_IRQn = 3, /*!< ERTC Interrupt linked to EXINT22 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + CRM_IRQn = 5, /*!< CRM global Interrupt */ + EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ + EXINT1_IRQn = 7, /*!< EXINT Line 1 Interrupt */ + EXINT2_IRQn = 8, /*!< EXINT Line 2 Interrupt */ + EXINT3_IRQn = 9, /*!< EXINT Line 3 Interrupt */ + EXINT4_IRQn = 10, /*!< EXINT Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SE_IRQn = 22, /*!< CAN1 SE Interrupt */ + EXINT9_5_IRQn = 23, /*!< EXINT Line[9:5] Interrupts */ + TMR1_BRK_TMR9_IRQn = 24, /*!< TMR1 Break Interrupt and TMR9 global Interrupt */ + TMR1_OVF_TMR10_IRQn = 25, /*!< TMR1 Overflow Interrupt and TMR10 global Interrupt */ + TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< TMR1 Trigger and Hall Interrupt and TMR11 global IRQ */ + TMR1_CH_IRQn = 27, /*!< TMR1 Channel Interrupt */ + TMR2_GLOBAL_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_GLOBAL_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_GLOBAL_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EVT_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ERR_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EVT_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ERR_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXINT15_10_IRQn = 40, /*!< EXINT Line[15:10] Interrupts */ + ERTCAlarm_IRQn = 41, /*!< ERTC Alarm Interrupt linked to EXINT17 */ + OTGFS_WKUP_IRQn = 42, /*!< OTGFS Wake Up Interrupt linked to EXINT18 */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_GLOBAL_IRQn = 50, /*!< TMR5 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + OTGFS_IRQn = 67, /*!< OTGFS global Interrupt */ + CMP1_IRQn = 70, /*!< CMP1 Interrupt linked to EXINT19 */ + CMP2_IRQn = 71, /*!< CMP2 Interrupt linked to EXINT20 */ + DMA2_Channel6_7_IRQn = 75, /*!< DMA2 Channel 6 and Channel 7 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" +#include "system_at32f415.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CTRL2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SPT1; /*!< ADC sampling time register 1, Address offset: 0x0C */ + __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x10 */ + __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x14 */ + __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x18 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3 Address offset: 0x1C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4 Address offset: 0x20 */ + __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x24 */ + __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x28 */ + __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x2C */ + __IO uint32_t OSQ2; /*!< ADC ordinary sequence register 2, Address offset: 0x30 */ + __IO uint32_t OSQ3; /*!< ADC ordinary sequence register 3, Address offset: 0x34 */ + __IO uint32_t PSQ; /*!< ADC preempted sequence register, Address offset: 0x38 */ + __IO uint32_t PDT1; /*!< ADC preempted data register 1, Address offset: 0x3C */ + __IO uint32_t PDT2; /*!< ADC preempted data register 2, Address offset: 0x40 */ + __IO uint32_t PDT3; /*!< ADC preempted data register 3, Address offset: 0x44 */ + __IO uint32_t PDT4; /*!< ADC preempted data register 4, Address offset: 0x48 */ + __IO uint32_t ODT; /*!< ADC ordinary data register, Address offset: 0x4C */ +} ADC_TypeDef; + +/** + * @brief Controller Area Network TX Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMC; + __IO uint32_t TMDTL; + __IO uint32_t TMDTH; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFO Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t RFI; + __IO uint32_t RFC; + __IO uint32_t RFDTL; + __IO uint32_t RFDTH; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network Filter Registers + */ + +typedef struct +{ + __IO uint32_t FFB1; + __IO uint32_t FFB2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; /*!< CAN master control register, Address offset: 0x000 */ + __IO uint32_t MSTS; /*!< CAN master status register, Address offset: 0x004 */ + __IO uint32_t TSTS; /*!< CAN transmit status register, Address offset: 0x008 */ + __IO uint32_t RF0; /*!< CAN receive FIFO 0 register, Address offset: 0x00C */ + __IO uint32_t RF1; /*!< CAN receive FIFO 1 register, Address offset: 0x010 */ + __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ + __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ + __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FF */ + __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ + __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ + __IO uint32_t FBWCFG; /*!< CAN filter bit width configuration register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x210 */ + __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ + __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ +} CAN_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CTRLSTS1; /*!< CMP control and status register 1, Address offset: 0x00 */ + __IO uint32_t CTRLSTS2; /*!< CMP control and status register 2, Address offset: 0x04 */ +} CMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DT; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t CDT; /*!< CRC Common data register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ +} CRC_TypeDef; + +/** + * @brief Clock and Reset Manage + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< CRM Clock control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< CRM Clock configuration register, Address offset: 0x04 */ + __IO uint32_t CLKINT; /*!< CRM Clock interrupt register, Address offset: 0x08 */ + __IO uint32_t APB2RST; /*!< CRM APB2 peripheral reset register, Address offset: 0x0C */ + __IO uint32_t APB1RST; /*!< CRM APB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHBEN; /*!< CRM APB peripheral clock enable register, Address offset: 0x14 */ + __IO uint32_t APB2EN; /*!< CRM APB2 peripheral clock enable register, Address offset: 0x18 */ + __IO uint32_t APB1EN; /*!< CRM APB1 peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t BPDC; /*!< CRM Battery powered domain control register, Address offset: 0x20 */ + __IO uint32_t CTRLSTS; /*!< CRM Control/status register, Address offset: 0x24 */ + __IO uint32_t AHBRST; /*!< CRM APB peripheral reset register, Address offset: 0x28 */ + __IO uint32_t PLL; /*!< CRM PLL configuration register, Address offset: 0x2C */ + __IO uint32_t MISC1; /*!< CRM Additional register 1, Address offset: 0x30 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x34 ~ 0x40 */ + __IO uint32_t OTG_EXTCTRL; /*!< CRM OTG_FS extended control register, Address offset: 0x44 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x48 - 0x50 */ + __IO uint32_t MISC2; /*!< CRM Additional register 2, Address offset: 0x54 */ +} CRM_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< DEBUG device ID, Address offset: 0xE004_2000 */ + __IO uint32_t CTRL; /*!< DEBUG control register, Address offset: 0xE004_2004 */ +} DEBUG_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) x = 1 ... 7 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t CLR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ + uint32_t RESERVED[38]; /*!< Reserved, Address offset: 0x08 ~ 0x9C */ + __IO uint32_t SRC_SEL0; /*!< DMA Channel source register 0, Address offset: 0xA0 */ + __IO uint32_t SRC_SEL1; /*!< DMA Channel source register 1, Address offset: 0xA4 */ +} DMA_TypeDef; + +/** + * @brief Enhanced Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TIME; /*!< ERTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< ERTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< ERTC control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< ERTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t DIV; /*!< ERTC divider register, Address offset: 0x10 */ + __IO uint32_t WAT; /*!< ERTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CCAL; /*!< ERTC coarse calibration register, Address offset: 0x18 */ + __IO uint32_t ALA; /*!< ERTC alarm clock A register, Address offset: 0x1C */ + __IO uint32_t ALB; /*!< ERTC alarm clock B register, Address offset: 0x20 */ + __IO uint32_t WP; /*!< ERTC write protection register, Address offset: 0x24 */ + __IO uint32_t SBS; /*!< ERTC subsecond register, Address offset: 0x28 */ + __IO uint32_t TADJ; /*!< ERTC time adjustment register, Address offset: 0x2C */ + __IO uint32_t TSTM; /*!< ERTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDT; /*!< ERTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSBS; /*!< ERTC time stamp subsecond register, Address offset: 0x38 */ + __IO uint32_t SCAL; /*!< ERTC smooth calibration register, Address offset: 0x3C */ + __IO uint32_t TAMP; /*!< ERTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALASBS; /*!< ERTC alarm clock A subsecond register, Address offset: 0x44 */ + __IO uint32_t ALBSBS; /*!< ERTC alarm clock B subsecond register, Address offset: 0x48 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t BPR1; /*!< ERTC battery powered domain data register 1, Address offset: 0x50 */ + __IO uint32_t BPR2; /*!< ERTC battery powered domain data register 2, Address offset: 0x54 */ + __IO uint32_t BPR3; /*!< ERTC battery powered domain data register 3, Address offset: 0x58 */ + __IO uint32_t BPR4; /*!< ERTC battery powered domain data register 4, Address offset: 0x5C */ + __IO uint32_t BPR5; /*!< ERTC battery powered domain data register 5, Address offset: 0x60 */ + __IO uint32_t BPR6; /*!< ERTC battery powered domain data register 6, Address offset: 0x64 */ + __IO uint32_t BPR7; /*!< ERTC battery powered domain data register 7, Address offset: 0x68 */ + __IO uint32_t BPR8; /*!< ERTC battery powered domain data register 8, Address offset: 0x6C */ + __IO uint32_t BPR9; /*!< ERTC battery powered domain data register 9, Address offset: 0x70 */ + __IO uint32_t BPR10; /*!< ERTC BAT powered domain data register 10, Address offset: 0x74 */ + __IO uint32_t BPR11; /*!< ERTC BAT powered domain data register 11, Address offset: 0x78 */ + __IO uint32_t BPR12; /*!< ERTC BAT powered domain data register 12, Address offset: 0x7C */ + __IO uint32_t BPR13; /*!< ERTC BAT powered domain data register 13, Address offset: 0x80 */ + __IO uint32_t BPR14; /*!< ERTC BAT powered domain data register 14, Address offset: 0x84 */ + __IO uint32_t BPR15; /*!< ERTC BAT powered domain data register 15, Address offset: 0x88 */ + __IO uint32_t BPR16; /*!< ERTC BAT powered domain data register 16, Address offset: 0x8C */ + __IO uint32_t BPR17; /*!< ERTC BAT powered domain data register 17, Address offset: 0x90 */ + __IO uint32_t BPR18; /*!< ERTC BAT powered domain data register 18, Address offset: 0x94 */ + __IO uint32_t BPR19; /*!< ERTC BAT powered domain data register 19, Address offset: 0x98 */ + __IO uint32_t BPR20; /*!< ERTC BAT powered domain data register 20, Address offset: 0x9C */ +} ERTC_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t INTEN; /*!< EXINT Interrupt enable register, Address offset: 0x00 */ + __IO uint32_t EVTEN; /*!< EXINT Event enable register, Address offset: 0x04 */ + __IO uint32_t POLCFG1; /*!< EXINT Polarity configuration register 1, Address offset: 0x08 */ + __IO uint32_t POLCFG2; /*!< EXINT Polarity configuration register 2, Address offset: 0x0C */ + __IO uint32_t SWTRG; /*!< EXINT Software trigger register, Address offset: 0x10 */ + __IO uint32_t INTSTS; /*!< EXINT Interrupt status register, Address offset: 0x14 */ +} EXINT_TypeDef; + +/** + * @brief Flash Memory Registers + */ + +typedef struct +{ + __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register 1, Address offset: 0x04 */ + __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t ADDR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t USD; /*!< FLASH user system data register, Address offset: 0x1C */ + __IO uint32_t EPPS; /*!< FLASH erase/program protection status reg, Address offset: 0x20 */ + uint32_t RESERVED1[20]; /*!< Reserved, Address offset: 0x24 ~ 0x70 */ + __IO uint32_t SLIB_STS0; /*!< FLASH security library status register 0, Address offset: 0x74 */ + __IO uint32_t SLIB_STS1; /*!< FLASH security library status register 1, Address offset: 0x78 */ + __IO uint32_t SLIB_PWD_CLR; /*!< FLASH security library password clear reg, Address offset: 0x7C */ + __IO uint32_t SLIB_MISC_STS; /*!< FLASH security library additional stat reg, Address offset: 0x80 */ + __IO uint32_t CRC_ADDR; /*!< FLASH CRC address register, Address offset: 0x84 */ + __IO uint32_t CRC_CTRL; /*!< FLASH CRC control register, Address offset: 0x88 */ + __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register, Address offset: 0x8C */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x90 ~ 0x15C */ + __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ + __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ + __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot mode setting register, Address offset: 0x16C */ + __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ +} FLASH_TypeDef; + +/** + * @brief User System Data Registers + */ + +typedef struct +{ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ +} USD_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ + __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ + __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ +} GPIO_TypeDef; + +/** + * @brief Multiplex Function I/O + */ + +typedef struct +{ + __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ + __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ + __IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */ + __IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */ + __IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */ + __IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ + __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ + __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ + __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ + __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ + __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ + __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ +} IOMUX_TypeDef; + +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OADDR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OADDR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DT; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t STS1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t STS2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CLKCTRL; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TMRISE; /*!< I2C timer rise time register, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< PWC Power control register, Address offset: 0x00 */ + __IO uint32_t CTRLSTS; /*!< PWC Power control/status register, Address offset: 0x04 */ +} PWC_TypeDef; + +/** + * @brief SD Host Interface + */ + +typedef struct +{ + __IO uint32_t PWRCTRL; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCTRL; /*!< SDIO clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RSPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RSP1; /*!< SDIO response register 1, Address offset: 0x14 */ + __I uint32_t RSP2; /*!< SDIO response register 2, Address offset: 0x18 */ + __I uint32_t RSP3; /*!< SDIO response register 3, Address offset: 0x1C */ + __I uint32_t RSP4; /*!< SDIO response register 4, Address offset: 0x20 */ + __IO uint32_t DTTMR; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DTLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DTCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DTCNTR; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STS; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t INTCLR; /*!< SDIO clear interrupt register, Address offset: 0x38 */ + __IO uint32_t INTEN; /*!< SDIO interrupt mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x40 ~ 0x44 */ + __I uint32_t BUFCNTR; /*!< SDIO BUF counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, Address offset: 0x4C ~ 0x7C */ + __IO uint32_t BUF; /*!< SDIO data BUF register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< SPI control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ + __IO uint32_t RCRC; /*!< SPI RX CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI TX CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S register, Address offset: 0x1C */ + __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TMR Timers + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< TMR control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< TMR control register 2, Address offset: 0x04 */ + __IO uint32_t STCTRL; /*!< TMR slave timer control register, Address offset: 0x08 */ + __IO uint32_t IDEN; /*!< TMR DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t ISTS; /*!< TMR interrupt status register, Address offset: 0x10 */ + __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ + __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ + __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ + __IO uint32_t CCTRL; /*!< TMR Channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value, Address offset: 0x28 */ + __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ + __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ + __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ + __IO uint32_t C2DT; /*!< TMR channel 2 data register, Address offset: 0x38 */ + __IO uint32_t C3DT; /*!< TMR channel 3 data register, Address offset: 0x3C */ + __IO uint32_t C4DT; /*!< TMR channel 4 data register, Address offset: 0x40 */ + __IO uint32_t BRK; /*!< TMR break register, Address offset: 0x44 */ + __IO uint32_t DMACTRL; /*!< TMR DMA control register, Address offset: 0x48 */ + __IO uint32_t DMADT; /*!< TMR DMA data register, Address offset: 0x4C */ +} TMR_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< USART status register, Address offset: 0x00 */ + __IO uint32_t DT; /*!< USART data register, Address offset: 0x04 */ + __IO uint32_t BAUDR; /*!< USART baud rate register, Address offset: 0x08 */ + __IO uint32_t CTRL1; /*!< USART control register 1, Address offset: 0x0C */ + __IO uint32_t CTRL2; /*!< USART control register 2, Address offset: 0x10 */ + __IO uint32_t CTRL3; /*!< USART control register 3, Address offset: 0x14 */ + __IO uint32_t GDIV; /*!< USART guard time and divider register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CMD; /*!< WDT Command register, Address offset: 0x00 */ + __IO uint32_t DIV; /*!< WDT Divider register, Address offset: 0x04 */ + __IO uint32_t RLD; /*!< WDT Reload register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< WDT Status register, Address offset: 0x0C */ +} WDT_TypeDef; + +/** + * @brief Window WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< WWDT Control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< WWDT Configuration register, Address offset: 0x04 */ + __IO uint32_t STS; /*!< WWDT Status register, Address offset: 0x08 */ +} WWDT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH end address of bank 1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE /*!< APB1 base address */ +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) /*!< APB2 base address */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< AHB base address */ + +#define TMR2_BASE (APB1PERIPH_BASE + 0x00000000U) /*!< TMR2 base address */ +#define TMR3_BASE (APB1PERIPH_BASE + 0x00000400U) /*!< TMR3 base address */ +#define TMR4_BASE (APB1PERIPH_BASE + 0x00000800U) /*!< TMR4 base address */ +#define TMR5_BASE (APB1PERIPH_BASE + 0x00000C00U) /*!< TMR5 base address */ +#define CMP_BASE (APB1PERIPH_BASE + 0x00002400U) /*!< CMP base address */ +#define ERTC_BASE (APB1PERIPH_BASE + 0x00002800U) /*!< ERTC base address */ +#define WWDT_BASE (APB1PERIPH_BASE + 0x00002C00U) /*!< WWDT base address */ +#define WDT_BASE (APB1PERIPH_BASE + 0x00003000U) /*!< WDT base address */ +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) /*!< SPI2 base address */ +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) /*!< USART2 base address */ +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) /*!< USART3 base address */ +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) /*!< UART4 base address */ +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) /*!< UART5 base address */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) /*!< I2C1 base address */ +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ +#define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ +#define IOMUX_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< IOMUX base address */ +#define EXINT_BASE (APB2PERIPH_BASE + 0x00000400U) /*!< EXINT base address */ +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) /*!< GPIOA base address */ +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) /*!< GPIOB base address */ +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) /*!< GPIOC base address */ +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) /*!< GPIOD base address */ +#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U) /*!< GPIOF base address */ +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) /*!< ADC1 base address */ +#define TMR1_BASE (APB2PERIPH_BASE + 0x00002C00U) /*!< TMR1 base address */ +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) /*!< SPI1 base address */ +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< USART1 base address */ +#define TMR9_BASE (APB2PERIPH_BASE + 0x00004C00U) /*!< TMR9 base address */ +#define TMR10_BASE (APB2PERIPH_BASE + 0x00005000U) /*!< TMR10 base address */ +#define TMR11_BASE (APB2PERIPH_BASE + 0x00005400U) /*!< TMR11 base address */ + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) /*!< SDIO base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) /*!< DMA1 base address */ +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) /*!< DMA1 Channel 1 base address */ +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) /*!< DMA1 Channel 2 base address */ +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) /*!< DMA1 Channel 3 base address */ +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) /*!< DMA1 Channel 4 base address */ +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) /*!< DMA1 Channel 5 base address */ +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) /*!< DMA1 Channel 6 base address */ +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) /*!< DMA1 Channel 7 base address */ +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U) /*!< DMA2 base address */ +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U) /*!< DMA2 Channel 1 base address */ +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU) /*!< DMA2 Channel 2 base address */ +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U) /*!< DMA2 Channel 3 base address */ +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U) /*!< DMA2 Channel 4 base address */ +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U) /*!< DMA2 Channel 5 base address */ +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x0000046CU) /*!< DMA2 Channel 6 base address */ +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x00000480U) /*!< DMA2 Channel 7 base address */ +#define CRM_BASE (AHBPERIPH_BASE + 0x00001000U) /*!< CRM base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) /*!< CRC base address */ + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */ +#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */ +#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */ +#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ + +#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB OTG device FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG Peripheral Registers base address */ + +#define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ +#define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U /*!< USB OTG IN Endpoint Registers base address */ +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U /*!< USB OTG OUT Endpoint Registers base address */ +#define USB_OTG_EP_REG_SIZE 0x00000020U /*!< USB OTG All Endpoint Registers size address */ +#define USB_OTG_HOST_BASE 0x00000400U /*!< USB OTG Host Mode Registers base address */ +#define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ +#define USB_OTG_DEP3RMPEN_BASE 0x00000D0CU /*!< USB OTG DEP3RMPEN Registers base address */ +#define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ +#define USB_OTG_USBDIVRST_BASE 0x00000E10U /*!< USB OTG USBDIVRST Registers base address */ +#define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ +#define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CMP ((CMP_TypeDef *)CMP_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR5 ((TMR_TypeDef *)TMR5_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral registers bits definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Power Control (PWC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for PWC_CTRL register *******************/ +#define PWC_CTRL_VRSEL_Pos (0U) +#define PWC_CTRL_VRSEL_Msk (0x1U << PWC_CTRL_VRSEL_Pos) /*!< 0x00000001 */ +#define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ +#define PWC_CTRL_LPSEL_Pos (1U) +#define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep */ +#define PWC_CTRL_CLSWEF_Pos (2U) +#define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ +#define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ +#define PWC_CTRL_CLSEF_Pos (3U) +#define PWC_CTRL_CLSEF_Msk (0x1U << PWC_CTRL_CLSEF_Pos) /*!< 0x00000008 */ +#define PWC_CTRL_CLSEF PWC_CTRL_CLSEF_Msk /*!< Clear SEF flag */ +#define PWC_CTRL_PVMEN_Pos (4U) +#define PWC_CTRL_PVMEN_Msk (0x1U << PWC_CTRL_PVMEN_Pos) /*!< 0x00000010 */ +#define PWC_CTRL_PVMEN PWC_CTRL_PVMEN_Msk /*!< Power voltage monitoring enable */ + +/*!< PVM level configuration */ +#define PWC_CTRL_PVMSEL_Pos (5U) +#define PWC_CTRL_PVMSEL_Msk (0x7U << PWC_CTRL_PVMSEL_Pos) /*!< 0x000000E0 */ +#define PWC_CTRL_PVMSEL PWC_CTRL_PVMSEL_Msk /*!< PVMSEL[2:0] bits (Power voltage monitoring boundary select) */ +#define PWC_CTRL_PVMSEL_0 (0x1U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000020 */ +#define PWC_CTRL_PVMSEL_1 (0x2U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000040 */ +#define PWC_CTRL_PVMSEL_2 (0x4U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000080 */ + +#define PWC_CTRL_PVMSEL_LEV1 0x00000020U /*!< PVM level 2.3V */ +#define PWC_CTRL_PVMSEL_LEV2 0x00000040U /*!< PVM level 2.4V */ +#define PWC_CTRL_PVMSEL_LEV3 0x00000060U /*!< PVM level 2.5V */ +#define PWC_CTRL_PVMSEL_LEV4 0x00000080U /*!< PVM level 2.6V */ +#define PWC_CTRL_PVMSEL_LEV5 0x000000A0U /*!< PVM level 2.7V */ +#define PWC_CTRL_PVMSEL_LEV6 0x000000C0U /*!< PVM level 2.8V */ +#define PWC_CTRL_PVMSEL_LEV7 0x000000E0U /*!< PVM level 2.9V */ + +/* Legacy defines */ +#define PWC_CTRL_PVMSEL_2V3 PWC_CTRL_PVMSEL_LEV1 +#define PWC_CTRL_PVMSEL_2V4 PWC_CTRL_PVMSEL_LEV2 +#define PWC_CTRL_PVMSEL_2V5 PWC_CTRL_PVMSEL_LEV3 +#define PWC_CTRL_PVMSEL_2V6 PWC_CTRL_PVMSEL_LEV4 +#define PWC_CTRL_PVMSEL_2V7 PWC_CTRL_PVMSEL_LEV5 +#define PWC_CTRL_PVMSEL_2V8 PWC_CTRL_PVMSEL_LEV6 +#define PWC_CTRL_PVMSEL_2V9 PWC_CTRL_PVMSEL_LEV7 + +#define PWC_CTRL_BPWEN_Pos (8U) +#define PWC_CTRL_BPWEN_Msk (0x1U << PWC_CTRL_BPWEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRL_BPWEN PWC_CTRL_BPWEN_Msk /*!< Battery powered domain write enable */ + +/***************** Bit definition for PWC_CTRLSTS register ******************/ +#define PWC_CTRLSTS_SWEF_Pos (0U) +#define PWC_CTRLSTS_SWEF_Msk (0x1U << PWC_CTRLSTS_SWEF_Pos) /*!< 0x00000001 */ +#define PWC_CTRLSTS_SWEF PWC_CTRLSTS_SWEF_Msk /*!< Standby wake-up event flag */ +#define PWC_CTRLSTS_SEF_Pos (1U) +#define PWC_CTRLSTS_SEF_Msk (0x1U << PWC_CTRLSTS_SEF_Pos) /*!< 0x00000002 */ +#define PWC_CTRLSTS_SEF PWC_CTRLSTS_SEF_Msk /*!< Standby mode entry flag */ +#define PWC_CTRLSTS_PVMOF_Pos (2U) +#define PWC_CTRLSTS_PVMOF_Msk (0x1U << PWC_CTRLSTS_PVMOF_Pos) /*!< 0x00000004 */ +#define PWC_CTRLSTS_PVMOF PWC_CTRLSTS_PVMOF_Msk /*!< Power voltage monitoring output flag */ +#define PWC_CTRLSTS_SWPEN_Pos (8U) +#define PWC_CTRLSTS_SWPEN_Msk (0x1U << PWC_CTRLSTS_SWPEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRLSTS_SWPEN PWC_CTRLSTS_SWPEN_Msk /*!< Standby wake-up pin enable */ + +/******************************************************************************/ +/* */ +/* Clock and reset manage (CRM) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRM_CTRL register *******************/ +#define CRM_CTRL_HICKEN_Pos (0U) +#define CRM_CTRL_HICKEN_Msk (0x1U << CRM_CTRL_HICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRL_HICKEN CRM_CTRL_HICKEN_Msk /*!< High speed internal clock enable */ +#define CRM_CTRL_HICKSTBL_Pos (1U) +#define CRM_CTRL_HICKSTBL_Msk (0x1U << CRM_CTRL_HICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRL_HICKSTBL CRM_CTRL_HICKSTBL_Msk /*!< High speed internal clock stable */ +#define CRM_CTRL_HICKTRIM_Pos (2U) +#define CRM_CTRL_HICKTRIM_Msk (0x3FU << CRM_CTRL_HICKTRIM_Pos) /*!< 0x000000FC */ +#define CRM_CTRL_HICKTRIM CRM_CTRL_HICKTRIM_Msk /*!< High speed internal clock trimming */ +#define CRM_CTRL_HICKCAL_Pos (8U) +#define CRM_CTRL_HICKCAL_Msk (0xFFU << CRM_CTRL_HICKCAL_Pos) /*!< 0x0000FF00 */ +#define CRM_CTRL_HICKCAL CRM_CTRL_HICKCAL_Msk /*!< High speed internal clock calibration */ +#define CRM_CTRL_HEXTEN_Pos (16U) +#define CRM_CTRL_HEXTEN_Msk (0x1U << CRM_CTRL_HEXTEN_Pos) /*!< 0x00010000 */ +#define CRM_CTRL_HEXTEN CRM_CTRL_HEXTEN_Msk /*!< High speed external crystal enable */ +#define CRM_CTRL_HEXTSTBL_Pos (17U) +#define CRM_CTRL_HEXTSTBL_Msk (0x1U << CRM_CTRL_HEXTSTBL_Pos) /*!< 0x00020000 */ +#define CRM_CTRL_HEXTSTBL CRM_CTRL_HEXTSTBL_Msk /*!< High speed external crystal stable */ +#define CRM_CTRL_HEXTBYPS_Pos (18U) +#define CRM_CTRL_HEXTBYPS_Msk (0x1U << CRM_CTRL_HEXTBYPS_Pos) /*!< 0x00040000 */ +#define CRM_CTRL_HEXTBYPS CRM_CTRL_HEXTBYPS_Msk /*!< High speed external crystal bypass */ +#define CRM_CTRL_CFDEN_Pos (19U) +#define CRM_CTRL_CFDEN_Msk (0x1U << CRM_CTRL_CFDEN_Pos) /*!< 0x00080000 */ +#define CRM_CTRL_CFDEN CRM_CTRL_CFDEN_Msk /*!< Clock failure detector enable */ +#define CRM_CTRL_PLLEN_Pos (24U) +#define CRM_CTRL_PLLEN_Msk (0x1U << CRM_CTRL_PLLEN_Pos) /*!< 0x01000000 */ +#define CRM_CTRL_PLLEN CRM_CTRL_PLLEN_Msk /*!< PLL enable */ +#define CRM_CTRL_PLLSTBL_Pos (25U) +#define CRM_CTRL_PLLSTBL_Msk (0x1U << CRM_CTRL_PLLSTBL_Pos) /*!< 0x02000000 */ +#define CRM_CTRL_PLLSTBL CRM_CTRL_PLLSTBL_Msk /*!< PLL clock stable */ + +/******************* Bit definition for CRM_CFG register ********************/ +/*!< SCLKSEL configuration */ +#define CRM_CFG_SCLKSEL_Pos (0U) +#define CRM_CFG_SCLKSEL_Msk (0x3U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000003 */ +#define CRM_CFG_SCLKSEL CRM_CFG_SCLKSEL_Msk /*!< SCLKSEL[1:0] bits (System clock select) */ +#define CRM_CFG_SCLKSEL_0 (0x1U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000001 */ +#define CRM_CFG_SCLKSEL_1 (0x2U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000002 */ + +#define CRM_CFG_SCLKSEL_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSEL_HEXT 0x00000001U /*!< HEXT */ +#define CRM_CFG_SCLKSEL_PLL 0x00000002U /*!< PLL */ + +/*!< SCLKSTS configuration */ +#define CRM_CFG_SCLKSTS_Pos (2U) +#define CRM_CFG_SCLKSTS_Msk (0x3U << CRM_CFG_SCLKSTS_Pos) /*!< 0x0000000C */ +#define CRM_CFG_SCLKSTS CRM_CFG_SCLKSTS_Msk /*!< SCLKSTS[1:0] bits (System clock select status) */ +#define CRM_CFG_SCLKSTS_0 (0x1U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000004 */ +#define CRM_CFG_SCLKSTS_1 (0x2U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000008 */ + +#define CRM_CFG_SCLKSTS_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSTS_HEXT 0x00000004U /*!< HEXT */ +#define CRM_CFG_SCLKSTS_PLL 0x00000008U /*!< PLL */ + +/*!< AHBDIV configuration */ +#define CRM_CFG_AHBDIV_Pos (4U) +#define CRM_CFG_AHBDIV_Msk (0xFU << CRM_CFG_AHBDIV_Pos) /*!< 0x000000F0 */ +#define CRM_CFG_AHBDIV CRM_CFG_AHBDIV_Msk /*!< AHBDIV[3:0] bits (AHB division) */ +#define CRM_CFG_AHBDIV_0 (0x1U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000010 */ +#define CRM_CFG_AHBDIV_1 (0x2U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000020 */ +#define CRM_CFG_AHBDIV_2 (0x4U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000040 */ +#define CRM_CFG_AHBDIV_3 (0x8U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000080 */ + +#define CRM_CFG_AHBDIV_DIV1 0x00000000U /*!< SCLK is not divided */ +#define CRM_CFG_AHBDIV_DIV2 0x00000080U /*!< SCLK is divided by 2 */ +#define CRM_CFG_AHBDIV_DIV4 0x00000090U /*!< SCLK is divided by 4 */ +#define CRM_CFG_AHBDIV_DIV8 0x000000A0U /*!< SCLK is divided by 8 */ +#define CRM_CFG_AHBDIV_DIV16 0x000000B0U /*!< SCLK is divided by 16 */ +#define CRM_CFG_AHBDIV_DIV64 0x000000C0U /*!< SCLK is divided by 64 */ +#define CRM_CFG_AHBDIV_DIV128 0x000000D0U /*!< SCLK is divided by 128 */ +#define CRM_CFG_AHBDIV_DIV256 0x000000E0U /*!< SCLK is divided by 256 */ +#define CRM_CFG_AHBDIV_DIV512 0x000000F0U /*!< SCLK is divided by 512 */ + +/*!< APB1DIV configuration */ +#define CRM_CFG_APB1DIV_Pos (8U) +#define CRM_CFG_APB1DIV_Msk (0x7U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000700 */ +#define CRM_CFG_APB1DIV CRM_CFG_APB1DIV_Msk /*!< APB1DIV[2:0] bits (APB1 division) */ +#define CRM_CFG_APB1DIV_0 (0x1U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000100 */ +#define CRM_CFG_APB1DIV_1 (0x2U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000200 */ +#define CRM_CFG_APB1DIV_2 (0x4U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000400 */ + +#define CRM_CFG_APB1DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB1DIV_DIV2 0x00000400U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB1DIV_DIV4 0x00000500U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB1DIV_DIV8 0x00000600U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB1DIV_DIV16 0x00000700U /*!< HCLK is divided by 16 */ + +/*!< APB2DIV configuration */ +#define CRM_CFG_APB2DIV_Pos (11U) +#define CRM_CFG_APB2DIV_Msk (0x7U << CRM_CFG_APB2DIV_Pos) /*!< 0x00003800 */ +#define CRM_CFG_APB2DIV CRM_CFG_APB2DIV_Msk /*!< APB2DIV[2:0] bits (APB2 division) */ +#define CRM_CFG_APB2DIV_0 (0x1U << CRM_CFG_APB2DIV_Pos) /*!< 0x00000800 */ +#define CRM_CFG_APB2DIV_1 (0x2U << CRM_CFG_APB2DIV_Pos) /*!< 0x00001000 */ +#define CRM_CFG_APB2DIV_2 (0x4U << CRM_CFG_APB2DIV_Pos) /*!< 0x00002000 */ + +#define CRM_CFG_APB2DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB2DIV_DIV2 0x00002000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB2DIV_DIV4 0x00002800U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB2DIV_DIV8 0x00003000U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB2DIV_DIV16 0x00003800U /*!< HCLK is divided by 16 */ + +/*!< ADCDIV configuration */ +#define CRM_CFG_ADCDIV_Msk ((0x3U << 14) | (0x1U << 28)) /*!< 0x0100C000 */ +#define CRM_CFG_ADCDIV CRM_CFG_ADCDIV_Msk /*!< ADCDIV[2:0] bits (ADC division) */ +#define CRM_CFG_ADCDIV_0 (0x1U << 14) /*!< 0x00004000 */ +#define CRM_CFG_ADCDIV_1 (0x2U << 14) /*!< 0x00008000 */ +#define CRM_CFG_ADCDIV_2 (0x1U << 28) /*!< 0x10000000 */ + +#define CRM_CFG_ADCDIV_DIV2 0x00000000U /*!< PCLK/2 */ +#define CRM_CFG_ADCDIV_DIV4 0x00004000U /*!< PCLK/4 */ +#define CRM_CFG_ADCDIV_DIV6 0x00008000U /*!< PCLK/6 */ +#define CRM_CFG_ADCDIV_DIV8 0x0000C000U /*!< PCLK/8 */ +#define CRM_CFG_ADCDIV_DIV12 0x10004000U /*!< PCLK2/12 */ +#define CRM_CFG_ADCDIV_DIV16 0x1000C000U /*!< PCLK2/16 */ + +#define CRM_CFG_PLLRCS_Pos (16U) +#define CRM_CFG_PLLRCS_Msk (0x1U << CRM_CFG_PLLRCS_Pos) /*!< 0x00010000 */ +#define CRM_CFG_PLLRCS CRM_CFG_PLLRCS_Msk /*!< PLL entry clock select */ + +#define CRM_CFG_PLLHEXTDIV_Pos (17U) +#define CRM_CFG_PLLHEXTDIV_Msk (0x1U << CRM_CFG_PLLHEXTDIV_Pos) /*!< 0x00020000 */ +#define CRM_CFG_PLLHEXTDIV CRM_CFG_PLLHEXTDIV_Msk /*!< HEXT division selection for PLL entry clock */ + +/*!< PLLMULT configuration */ +#define CRM_CFG_PLLMULT_Msk ((0xFU << 18) | (0x3U << 29)) /*!< 0x603C0000 */ +#define CRM_CFG_PLLMULT CRM_CFG_PLLMULT_Msk /*!< PLLMULT[5:0] bits (PLL multiplication factor) */ +#define CRM_CFG_PLLMULT_0 (0x1U << 18) /*!< 0x00040000 */ +#define CRM_CFG_PLLMULT_1 (0x2U << 18) /*!< 0x00080000 */ +#define CRM_CFG_PLLMULT_2 (0x4U << 18) /*!< 0x00100000 */ +#define CRM_CFG_PLLMULT_3 (0x8U << 18) /*!< 0x00200000 */ +#define CRM_CFG_PLLMULT_4 (0x1U << 29) /*!< 0x20000000 */ +#define CRM_CFG_PLLMULT_5 (0x2U << 29) /*!< 0x40000000 */ + +#define CRM_CFG_PLLMULT_MULT2 0x00000000U /*!< PLL input clock * 2 */ +#define CRM_CFG_PLLMULT_MULT3_Pos (18U) +#define CRM_CFG_PLLMULT_MULT3_Msk (0x1U << CRM_CFG_PLLMULT_MULT3_Pos) /*!< 0x00040000 */ +#define CRM_CFG_PLLMULT_MULT3 CRM_CFG_PLLMULT_MULT3_Msk /*!< PLL input clock * 3 */ +#define CRM_CFG_PLLMULT_MULT4_Pos (19U) +#define CRM_CFG_PLLMULT_MULT4_Msk (0x1U << CRM_CFG_PLLMULT_MULT4_Pos) /*!< 0x00080000 */ +#define CRM_CFG_PLLMULT_MULT4 CRM_CFG_PLLMULT_MULT4_Msk /*!< PLL input clock * 4 */ +#define CRM_CFG_PLLMULT_MULT5_Pos (18U) +#define CRM_CFG_PLLMULT_MULT5_Msk (0x3U << CRM_CFG_PLLMULT_MULT5_Pos) /*!< 0x000C0000 */ +#define CRM_CFG_PLLMULT_MULT5 CRM_CFG_PLLMULT_MULT5_Msk /*!< PLL input clock * 5 */ +#define CRM_CFG_PLLMULT_MULT6_Pos (20U) +#define CRM_CFG_PLLMULT_MULT6_Msk (0x1U << CRM_CFG_PLLMULT_MULT6_Pos) /*!< 0x00100000 */ +#define CRM_CFG_PLLMULT_MULT6 CRM_CFG_PLLMULT_MULT6_Msk /*!< PLL input clock * 6 */ +#define CRM_CFG_PLLMULT_MULT7_Pos (18U) +#define CRM_CFG_PLLMULT_MULT7_Msk (0x5U << CRM_CFG_PLLMULT_MULT7_Pos) /*!< 0x00140000 */ +#define CRM_CFG_PLLMULT_MULT7 CRM_CFG_PLLMULT_MULT7_Msk /*!< PLL input clock * 7 */ +#define CRM_CFG_PLLMULT_MULT8_Pos (19U) +#define CRM_CFG_PLLMULT_MULT8_Msk (0x3U << CRM_CFG_PLLMULT_MULT8_Pos) /*!< 0x00180000 */ +#define CRM_CFG_PLLMULT_MULT8 CRM_CFG_PLLMULT_MULT8_Msk /*!< PLL input clock * 8 */ +#define CRM_CFG_PLLMULT_MULT9_Pos (18U) +#define CRM_CFG_PLLMULT_MULT9_Msk (0x7U << CRM_CFG_PLLMULT_MULT9_Pos) /*!< 0x001C0000 */ +#define CRM_CFG_PLLMULT_MULT9 CRM_CFG_PLLMULT_MULT9_Msk /*!< PLL input clock * 9 */ +#define CRM_CFG_PLLMULT_MULT10_Pos (21U) +#define CRM_CFG_PLLMULT_MULT10_Msk (0x1U << CRM_CFG_PLLMULT_MULT10_Pos) /*!< 0x00200000 */ +#define CRM_CFG_PLLMULT_MULT10 CRM_CFG_PLLMULT_MULT10_Msk /*!< PLL input clock * 10 */ +#define CRM_CFG_PLLMULT_MULT11_Pos (18U) +#define CRM_CFG_PLLMULT_MULT11_Msk (0x9U << CRM_CFG_PLLMULT_MULT11_Pos) /*!< 0x00240000 */ +#define CRM_CFG_PLLMULT_MULT11 CRM_CFG_PLLMULT_MULT11_Msk /*!< PLL input clock * 11 */ +#define CRM_CFG_PLLMULT_MULT12_Pos (19U) +#define CRM_CFG_PLLMULT_MULT12_Msk (0x5U << CRM_CFG_PLLMULT_MULT12_Pos) /*!< 0x00280000 */ +#define CRM_CFG_PLLMULT_MULT12 CRM_CFG_PLLMULT_MULT12_Msk /*!< PLL input clock * 12 */ +#define CRM_CFG_PLLMULT_MULT13_Pos (18U) +#define CRM_CFG_PLLMULT_MULT13_Msk (0xBU << CRM_CFG_PLLMULT_MULT13_Pos) /*!< 0x002C0000 */ +#define CRM_CFG_PLLMULT_MULT13 CRM_CFG_PLLMULT_MULT13_Msk /*!< PLL input clock * 13 */ +#define CRM_CFG_PLLMULT_MULT14_Pos (20U) +#define CRM_CFG_PLLMULT_MULT14_Msk (0x3U << CRM_CFG_PLLMULT_MULT14_Pos) /*!< 0x00300000 */ +#define CRM_CFG_PLLMULT_MULT14 CRM_CFG_PLLMULT_MULT14_Msk /*!< PLL input clock * 14 */ +#define CRM_CFG_PLLMULT_MULT15_Pos (18U) +#define CRM_CFG_PLLMULT_MULT15_Msk (0xDU << CRM_CFG_PLLMULT_MULT15_Pos) /*!< 0x00340000 */ +#define CRM_CFG_PLLMULT_MULT15 CRM_CFG_PLLMULT_MULT15_Msk /*!< PLL input clock * 15 */ +#define CRM_CFG_PLLMULT_MULT16_Pos (19U) +#define CRM_CFG_PLLMULT_MULT16_Msk (0x7U << CRM_CFG_PLLMULT_MULT16_Pos) /*!< 0x00380000 */ +#define CRM_CFG_PLLMULT_MULT16 CRM_CFG_PLLMULT_MULT16_Msk /*!< PLL input clock * 16 */ +#define CRM_CFG_PLLMULT_MULT17 0x20000000U /*!< PLL input clock * 17 */ +#define CRM_CFG_PLLMULT_MULT18 0x20040000U /*!< PLL input clock * 18 */ +#define CRM_CFG_PLLMULT_MULT19 0x20080000U /*!< PLL input clock * 19 */ +#define CRM_CFG_PLLMULT_MULT20 0x200C0000U /*!< PLL input clock * 20 */ +#define CRM_CFG_PLLMULT_MULT21 0x20100000U /*!< PLL input clock * 21 */ +#define CRM_CFG_PLLMULT_MULT22 0x20140000U /*!< PLL input clock * 22 */ +#define CRM_CFG_PLLMULT_MULT23 0x20180000U /*!< PLL input clock * 23 */ +#define CRM_CFG_PLLMULT_MULT24 0x201C0000U /*!< PLL input clock * 24 */ +#define CRM_CFG_PLLMULT_MULT25 0x20200000U /*!< PLL input clock * 25 */ +#define CRM_CFG_PLLMULT_MULT26 0x20240000U /*!< PLL input clock * 26 */ +#define CRM_CFG_PLLMULT_MULT27 0x20280000U /*!< PLL input clock * 27 */ +#define CRM_CFG_PLLMULT_MULT28 0x202C0000U /*!< PLL input clock * 28 */ +#define CRM_CFG_PLLMULT_MULT29 0x20300000U /*!< PLL input clock * 29 */ +#define CRM_CFG_PLLMULT_MULT30 0x20340000U /*!< PLL input clock * 30 */ +#define CRM_CFG_PLLMULT_MULT31 0x20380000U /*!< PLL input clock * 31 */ +#define CRM_CFG_PLLMULT_MULT32 0x203C0000U /*!< PLL input clock * 32 */ +#define CRM_CFG_PLLMULT_MULT33 0x40000000U /*!< PLL input clock * 33 */ +#define CRM_CFG_PLLMULT_MULT34 0x40040000U /*!< PLL input clock * 34 */ +#define CRM_CFG_PLLMULT_MULT35 0x40080000U /*!< PLL input clock * 35 */ +#define CRM_CFG_PLLMULT_MULT36 0x400C0000U /*!< PLL input clock * 36 */ +#define CRM_CFG_PLLMULT_MULT37 0x40100000U /*!< PLL input clock * 37 */ +#define CRM_CFG_PLLMULT_MULT38 0x40140000U /*!< PLL input clock * 38 */ +#define CRM_CFG_PLLMULT_MULT39 0x40180000U /*!< PLL input clock * 39 */ +#define CRM_CFG_PLLMULT_MULT40 0x401C0000U /*!< PLL input clock * 40 */ +#define CRM_CFG_PLLMULT_MULT41 0x40200000U /*!< PLL input clock * 41 */ +#define CRM_CFG_PLLMULT_MULT42 0x40240000U /*!< PLL input clock * 42 */ +#define CRM_CFG_PLLMULT_MULT43 0x40280000U /*!< PLL input clock * 43 */ +#define CRM_CFG_PLLMULT_MULT44 0x402C0000U /*!< PLL input clock * 44 */ +#define CRM_CFG_PLLMULT_MULT45 0x40300000U /*!< PLL input clock * 45 */ +#define CRM_CFG_PLLMULT_MULT46 0x40340000U /*!< PLL input clock * 46 */ +#define CRM_CFG_PLLMULT_MULT47 0x40380000U /*!< PLL input clock * 47 */ +#define CRM_CFG_PLLMULT_MULT48 0x403C0000U /*!< PLL input clock * 48 */ +#define CRM_CFG_PLLMULT_MULT49 0x60000000U /*!< PLL input clock * 49 */ +#define CRM_CFG_PLLMULT_MULT50 0x60040000U /*!< PLL input clock * 50 */ +#define CRM_CFG_PLLMULT_MULT51 0x60080000U /*!< PLL input clock * 51 */ +#define CRM_CFG_PLLMULT_MULT52 0x600C0000U /*!< PLL input clock * 52 */ +#define CRM_CFG_PLLMULT_MULT53 0x60100000U /*!< PLL input clock * 53 */ +#define CRM_CFG_PLLMULT_MULT54 0x60140000U /*!< PLL input clock * 54 */ +#define CRM_CFG_PLLMULT_MULT55 0x60180000U /*!< PLL input clock * 55 */ +#define CRM_CFG_PLLMULT_MULT56 0x601C0000U /*!< PLL input clock * 56 */ +#define CRM_CFG_PLLMULT_MULT57 0x60200000U /*!< PLL input clock * 57 */ +#define CRM_CFG_PLLMULT_MULT58 0x60240000U /*!< PLL input clock * 58 */ +#define CRM_CFG_PLLMULT_MULT59 0x60280000U /*!< PLL input clock * 59 */ +#define CRM_CFG_PLLMULT_MULT60 0x602C0000U /*!< PLL input clock * 60 */ +#define CRM_CFG_PLLMULT_MULT61 0x60300000U /*!< PLL input clock * 61 */ +#define CRM_CFG_PLLMULT_MULT62 0x60340000U /*!< PLL input clock * 62 */ +#define CRM_CFG_PLLMULT_MULT63 0x60380000U /*!< PLL input clock * 63 */ +#define CRM_CFG_PLLMULT_MULT64 0x603C0000U /*!< PLL input clock * 64 */ + +/*!< USBDIV configuration */ +#define CRM_CFG_USBDIV_Msk ((0x3U << 22) | (0x1U << 27)) /*!< 0x08C00000 */ +#define CRM_CFG_USBDIV CRM_CFG_USBDIV_Msk /*!< USBDIV[2:0] bits (USB division factor) */ +#define CRM_CFG_USBDIV_0 (0x1U << 22) /*!< 0x00400000 */ +#define CRM_CFG_USBDIV_1 (0x2U << 22) /*!< 0x00800000 */ +#define CRM_CFG_USBDIV_2 (0x1U << 27) /*!< 0x08000000 */ + +#define CRM_CFG_USBDIV_DIV1_5 0x00000000U /*!< PLL/1.5 */ +#define CRM_CFG_USBDIV_DIV1 0x00400000U /*!< PLL/1 */ +#define CRM_CFG_USBDIV_DIV2_5 0x00800000U /*!< PLL/2.5 */ +#define CRM_CFG_USBDIV_DIV2 0x00C00000U /*!< PLL/2 */ +#define CRM_CFG_USBDIV_DIV3_5 0x08000000U /*!< PLL/3.5 */ +#define CRM_CFG_USBDIV_DIV3 0x08400000U /*!< PLL/3 */ +#define CRM_CFG_USBDIV_DIV4 0x08800000U /*!< PLL/4 */ + +/*!< CLKOUT_SEL configuration */ +#define CRM_CFG_CLKOUT_SEL_Msk ((CRM_MISC1_CLKOUT_SEL) | (0x7U << 24)) /*!< 0x07010000 */ +#define CRM_CFG_CLKOUT_SEL CRM_CFG_CLKOUT_SEL_Msk /*!< CLKOUT_SEL[3:0] bits (Clock output selection) */ +#define CRM_CFG_CLKOUT_SEL_0 (0x1U << 24) /*!< 0x01000000 */ +#define CRM_CFG_CLKOUT_SEL_1 (0x2U << 24) /*!< 0x02000000 */ +#define CRM_CFG_CLKOUT_SEL_2 (0x4U << 24) /*!< 0x04000000 */ +#define CRM_CFG_CLKOUT_SEL_3 CRM_MISC1_CLKOUT_SEL /*!< 0x00010000 */ + +#define CRM_CFG_CLKOUT_SEL_NOCLOCK 0x00000000U /*!< Not clock output */ +#define CRM_CFG_CLKOUT_SEL_LICK 0x02000000U /*!< LICK */ +#define CRM_CFG_CLKOUT_SEL_LEXT 0x03000000U /*!< LEXT */ +#define CRM_CFG_CLKOUT_SEL_SCLK 0x04000000U /*!< SCLK */ +#define CRM_CFG_CLKOUT_SEL_HICK 0x05000000U /*!< HICK */ +#define CRM_CFG_CLKOUT_SEL_HEXT 0x06000000U /*!< HEXT */ +#define CRM_CFG_CLKOUT_SEL_PLL_DIV2 0x07000000U /*!< PLL/2 */ +#define CRM_MISC1_CLKOUT_SEL_PLL_DIV4 0x04010000U /*!< PLL/4 */ +#define CRM_MISC1_CLKOUT_SEL_USB 0x05010000U /*!< USB */ +#define CRM_MISC1_CLKOUT_SEL_ADC 0x06010000U /*!< ADC */ + +/* Reference defines */ +#define CRM_CFG_CLKSEL CRM_CFG_CLKOUT_SEL +#define CRM_CFG_CLKSEL_0 CRM_CFG_CLKOUT_SEL_0 +#define CRM_CFG_CLKSEL_1 CRM_CFG_CLKOUT_SEL_1 +#define CRM_CFG_CLKSEL_2 CRM_CFG_CLKOUT_SEL_2 +#define CRM_CFG_CLKSEL_NOCLOCK CRM_CFG_CLKOUT_SEL_NOCLOCK +#define CRM_CFG_CLKSEL_LICK CRM_CFG_CLKOUT_SEL_LICK +#define CRM_CFG_CLKSEL_LEXT CRM_CFG_CLKOUT_SEL_LEXT +#define CRM_CFG_CLKSEL_SCLK CRM_CFG_CLKOUT_SEL_SCLK +#define CRM_CFG_CLKSEL_HICK CRM_CFG_CLKOUT_SEL_HICK +#define CRM_CFG_CLKSEL_HEXT CRM_CFG_CLKOUT_SEL_HEXT +#define CRM_CFG_CLKSEL_PLL_DIV2 CRM_CFG_CLKOUT_SEL_PLL_DIV2 +#define CRM_MISC1_CLKSEL_PLL_DIV4 CRM_MISC1_CLKOUT_SEL_PLL_DIV4 +#define CRM_MISC1_CLKSEL_USB CRM_MISC1_CLKOUT_SEL_USB +#define CRM_MISC1_CLKSEL_ADC CRM_MISC1_CLKOUT_SEL_ADC + +/*!<*************** Bit definition for CRM_CLKINT register ******************/ +#define CRM_CLKINT_LICKSTBLF_Pos (0U) +#define CRM_CLKINT_LICKSTBLF_Msk (0x1U << CRM_CLKINT_LICKSTBLF_Pos) /*!< 0x00000001 */ +#define CRM_CLKINT_LICKSTBLF CRM_CLKINT_LICKSTBLF_Msk /*!< LICK stable interrupt flag */ +#define CRM_CLKINT_LEXTSTBLF_Pos (1U) +#define CRM_CLKINT_LEXTSTBLF_Msk (0x1U << CRM_CLKINT_LEXTSTBLF_Pos) /*!< 0x00000002 */ +#define CRM_CLKINT_LEXTSTBLF CRM_CLKINT_LEXTSTBLF_Msk /*!< LEXT stable flag */ +#define CRM_CLKINT_HICKSTBLF_Pos (2U) +#define CRM_CLKINT_HICKSTBLF_Msk (0x1U << CRM_CLKINT_HICKSTBLF_Pos) /*!< 0x00000004 */ +#define CRM_CLKINT_HICKSTBLF CRM_CLKINT_HICKSTBLF_Msk /*!< HICK stable flag */ +#define CRM_CLKINT_HEXTSTBLF_Pos (3U) +#define CRM_CLKINT_HEXTSTBLF_Msk (0x1U << CRM_CLKINT_HEXTSTBLF_Pos) /*!< 0x00000008 */ +#define CRM_CLKINT_HEXTSTBLF CRM_CLKINT_HEXTSTBLF_Msk /*!< HEXT stable flag */ +#define CRM_CLKINT_PLLSTBLF_Pos (4U) +#define CRM_CLKINT_PLLSTBLF_Msk (0x1U << CRM_CLKINT_PLLSTBLF_Pos) /*!< 0x00000010 */ +#define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ +#define CRM_CLKINT_CFDF_Pos (7U) +#define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock Failure Detection flag */ +#define CRM_CLKINT_LICKSTBLIEN_Pos (8U) +#define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ +#define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ +#define CRM_CLKINT_LEXTSTBLIEN_Pos (9U) +#define CRM_CLKINT_LEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_LEXTSTBLIEN_Pos) /*!< 0x00000200 */ +#define CRM_CLKINT_LEXTSTBLIEN CRM_CLKINT_LEXTSTBLIEN_Msk /*!< LEXT stable interrupt enable */ +#define CRM_CLKINT_HICKSTBLIEN_Pos (10U) +#define CRM_CLKINT_HICKSTBLIEN_Msk (0x1U << CRM_CLKINT_HICKSTBLIEN_Pos) /*!< 0x00000400 */ +#define CRM_CLKINT_HICKSTBLIEN CRM_CLKINT_HICKSTBLIEN_Msk /*!< HICK stable interrupt enable */ +#define CRM_CLKINT_HEXTSTBLIEN_Pos (11U) +#define CRM_CLKINT_HEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_HEXTSTBLIEN_Pos) /*!< 0x00000800 */ +#define CRM_CLKINT_HEXTSTBLIEN CRM_CLKINT_HEXTSTBLIEN_Msk /*!< HEXT stable interrupt enable */ +#define CRM_CLKINT_PLLSTBLIEN_Pos (12U) +#define CRM_CLKINT_PLLSTBLIEN_Msk (0x1U << CRM_CLKINT_PLLSTBLIEN_Pos) /*!< 0x00001000 */ +#define CRM_CLKINT_PLLSTBLIEN CRM_CLKINT_PLLSTBLIEN_Msk /*!< PLL stable interrupt enable */ +#define CRM_CLKINT_LICKSTBLFC_Pos (16U) +#define CRM_CLKINT_LICKSTBLFC_Msk (0x1U << CRM_CLKINT_LICKSTBLFC_Pos) /*!< 0x00010000 */ +#define CRM_CLKINT_LICKSTBLFC CRM_CLKINT_LICKSTBLFC_Msk /*!< LICK stable flag clear */ +#define CRM_CLKINT_LEXTSTBLFC_Pos (17U) +#define CRM_CLKINT_LEXTSTBLFC_Msk (0x1U << CRM_CLKINT_LEXTSTBLFC_Pos) /*!< 0x00020000 */ +#define CRM_CLKINT_LEXTSTBLFC CRM_CLKINT_LEXTSTBLFC_Msk /*!< LEXT stable flag clear */ +#define CRM_CLKINT_HICKSTBLFC_Pos (18U) +#define CRM_CLKINT_HICKSTBLFC_Msk (0x1U << CRM_CLKINT_HICKSTBLFC_Pos) /*!< 0x00040000 */ +#define CRM_CLKINT_HICKSTBLFC CRM_CLKINT_HICKSTBLFC_Msk /*!< HICK stable flag clear */ +#define CRM_CLKINT_HEXTSTBLFC_Pos (19U) +#define CRM_CLKINT_HEXTSTBLFC_Msk (0x1U << CRM_CLKINT_HEXTSTBLFC_Pos) /*!< 0x00080000 */ +#define CRM_CLKINT_HEXTSTBLFC CRM_CLKINT_HEXTSTBLFC_Msk /*!< HEXT stable flag clear */ +#define CRM_CLKINT_PLLSTBLFC_Pos (20U) +#define CRM_CLKINT_PLLSTBLFC_Msk (0x1U << CRM_CLKINT_PLLSTBLFC_Pos) /*!< 0x00100000 */ +#define CRM_CLKINT_PLLSTBLFC CRM_CLKINT_PLLSTBLFC_Msk /*!< PLL stable flag clear */ +#define CRM_CLKINT_CFDFC_Pos (23U) +#define CRM_CLKINT_CFDFC_Msk (0x1U << CRM_CLKINT_CFDFC_Pos) /*!< 0x00800000 */ +#define CRM_CLKINT_CFDFC CRM_CLKINT_CFDFC_Msk /*!< Clock failure detection flag clear */ + +/***************** Bit definition for CRM_APB2RST register ******************/ +#define CRM_APB2RST_IOMUXRST_Pos (0U) +#define CRM_APB2RST_IOMUXRST_Msk (0x1U << CRM_APB2RST_IOMUXRST_Pos) /*!< 0x00000001 */ +#define CRM_APB2RST_IOMUXRST CRM_APB2RST_IOMUXRST_Msk /*!< IOMUX reset */ +#define CRM_APB2RST_EXINTRST_Pos (1U) +#define CRM_APB2RST_EXINTRST_Msk (0x1U << CRM_APB2RST_EXINTRST_Pos) /*!< 0x00000002 */ +#define CRM_APB2RST_EXINTRST CRM_APB2RST_EXINTRST_Msk /*!< EXINT reset */ +#define CRM_APB2RST_GPIOARST_Pos (2U) +#define CRM_APB2RST_GPIOARST_Msk (0x1U << CRM_APB2RST_GPIOARST_Pos) /*!< 0x00000004 */ +#define CRM_APB2RST_GPIOARST CRM_APB2RST_GPIOARST_Msk /*!< GPIOA reset */ +#define CRM_APB2RST_GPIOBRST_Pos (3U) +#define CRM_APB2RST_GPIOBRST_Msk (0x1U << CRM_APB2RST_GPIOBRST_Pos) /*!< 0x00000008 */ +#define CRM_APB2RST_GPIOBRST CRM_APB2RST_GPIOBRST_Msk /*!< GPIOB reset */ +#define CRM_APB2RST_GPIOCRST_Pos (4U) +#define CRM_APB2RST_GPIOCRST_Msk (0x1U << CRM_APB2RST_GPIOCRST_Pos) /*!< 0x00000010 */ +#define CRM_APB2RST_GPIOCRST CRM_APB2RST_GPIOCRST_Msk /*!< GPIOC reset */ +#define CRM_APB2RST_GPIODRST_Pos (5U) +#define CRM_APB2RST_GPIODRST_Msk (0x1U << CRM_APB2RST_GPIODRST_Pos) /*!< 0x00000020 */ +#define CRM_APB2RST_GPIODRST CRM_APB2RST_GPIODRST_Msk /*!< GPIOD reset */ +#define CRM_APB2RST_GPIOFRST_Pos (7U) +#define CRM_APB2RST_GPIOFRST_Msk (0x1U << CRM_APB2RST_GPIOFRST_Pos) /*!< 0x00000080 */ +#define CRM_APB2RST_GPIOFRST CRM_APB2RST_GPIOFRST_Msk /*!< GPIOF reset */ +#define CRM_APB2RST_ADC1RST_Pos (9U) +#define CRM_APB2RST_ADC1RST_Msk (0x1U << CRM_APB2RST_ADC1RST_Pos) /*!< 0x00000200 */ +#define CRM_APB2RST_ADC1RST CRM_APB2RST_ADC1RST_Msk /*!< ADC1 reset */ +#define CRM_APB2RST_TMR1RST_Pos (11U) +#define CRM_APB2RST_TMR1RST_Msk (0x1U << CRM_APB2RST_TMR1RST_Pos) /*!< 0x00000800 */ +#define CRM_APB2RST_TMR1RST CRM_APB2RST_TMR1RST_Msk /*!< TMR1 reset */ +#define CRM_APB2RST_SPI1RST_Pos (12U) +#define CRM_APB2RST_SPI1RST_Msk (0x1U << CRM_APB2RST_SPI1RST_Pos) /*!< 0x00001000 */ +#define CRM_APB2RST_SPI1RST CRM_APB2RST_SPI1RST_Msk /*!< SPI1 reset */ +#define CRM_APB2RST_USART1RST_Pos (14U) +#define CRM_APB2RST_USART1RST_Msk (0x1U << CRM_APB2RST_USART1RST_Pos) /*!< 0x00004000 */ +#define CRM_APB2RST_USART1RST CRM_APB2RST_USART1RST_Msk /*!< USART1 reset */ +#define CRM_APB2RST_TMR9RST_Pos (19U) +#define CRM_APB2RST_TMR9RST_Msk (0x1U << CRM_APB2RST_TMR9RST_Pos) /*!< 0x00080000 */ +#define CRM_APB2RST_TMR9RST CRM_APB2RST_TMR9RST_Msk /*!< TMR9 reset */ +#define CRM_APB2RST_TMR10RST_Pos (20U) +#define CRM_APB2RST_TMR10RST_Msk (0x1U << CRM_APB2RST_TMR10RST_Pos) /*!< 0x00100000 */ +#define CRM_APB2RST_TMR10RST CRM_APB2RST_TMR10RST_Msk /*!< TMR10 reset */ +#define CRM_APB2RST_TMR11RST_Pos (21U) +#define CRM_APB2RST_TMR11RST_Msk (0x1U << CRM_APB2RST_TMR11RST_Pos) /*!< 0x00200000 */ +#define CRM_APB2RST_TMR11RST CRM_APB2RST_TMR11RST_Msk /*!< TMR11 reset */ + +/***************** Bit definition for CRM_APB1RST register ******************/ +#define CRM_APB1RST_TMR2RST_Pos (0U) +#define CRM_APB1RST_TMR2RST_Msk (0x1U << CRM_APB1RST_TMR2RST_Pos) /*!< 0x00000001 */ +#define CRM_APB1RST_TMR2RST CRM_APB1RST_TMR2RST_Msk /*!< TMR2 reset */ +#define CRM_APB1RST_TMR3RST_Pos (1U) +#define CRM_APB1RST_TMR3RST_Msk (0x1U << CRM_APB1RST_TMR3RST_Pos) /*!< 0x00000002 */ +#define CRM_APB1RST_TMR3RST CRM_APB1RST_TMR3RST_Msk /*!< TMR3 reset */ +#define CRM_APB1RST_TMR4RST_Pos (2U) +#define CRM_APB1RST_TMR4RST_Msk (0x1U << CRM_APB1RST_TMR4RST_Pos) /*!< 0x00000004 */ +#define CRM_APB1RST_TMR4RST CRM_APB1RST_TMR4RST_Msk /*!< TMR4 reset */ +#define CRM_APB1RST_TMR5RST_Pos (3U) +#define CRM_APB1RST_TMR5RST_Msk (0x1U << CRM_APB1RST_TMR5RST_Pos) /*!< 0x00000008 */ +#define CRM_APB1RST_TMR5RST CRM_APB1RST_TMR5RST_Msk /*!< TMR5 reset */ +#define CRM_APB1RST_CMPRST_Pos (9U) +#define CRM_APB1RST_CMPRST_Msk (0x1U << CRM_APB1RST_CMPRST_Pos) /*!< 0x00000200 */ +#define CRM_APB1RST_CMPRST CRM_APB1RST_CMPRST_Msk /*!< CMP reset */ +#define CRM_APB1RST_WWDTRST_Pos (11U) +#define CRM_APB1RST_WWDTRST_Msk (0x1U << CRM_APB1RST_WWDTRST_Pos) /*!< 0x00000800 */ +#define CRM_APB1RST_WWDTRST CRM_APB1RST_WWDTRST_Msk /*!< WWDT reset */ +#define CRM_APB1RST_SPI2RST_Pos (14U) +#define CRM_APB1RST_SPI2RST_Msk (0x1U << CRM_APB1RST_SPI2RST_Pos) /*!< 0x00004000 */ +#define CRM_APB1RST_SPI2RST CRM_APB1RST_SPI2RST_Msk /*!< SPI2 reset */ +#define CRM_APB1RST_USART2RST_Pos (17U) +#define CRM_APB1RST_USART2RST_Msk (0x1U << CRM_APB1RST_USART2RST_Pos) /*!< 0x00020000 */ +#define CRM_APB1RST_USART2RST CRM_APB1RST_USART2RST_Msk /*!< USART2 reset */ +#define CRM_APB1RST_USART3RST_Pos (18U) +#define CRM_APB1RST_USART3RST_Msk (0x1U << CRM_APB1RST_USART3RST_Pos) /*!< 0x00040000 */ +#define CRM_APB1RST_USART3RST CRM_APB1RST_USART3RST_Msk /*!< USART3 reset */ +#define CRM_APB1RST_UART4RST_Pos (19U) +#define CRM_APB1RST_UART4RST_Msk (0x1U << CRM_APB1RST_UART4RST_Pos) /*!< 0x00080000 */ +#define CRM_APB1RST_UART4RST CRM_APB1RST_UART4RST_Msk /*!< UART4 reset */ +#define CRM_APB1RST_UART5RST_Pos (20U) +#define CRM_APB1RST_UART5RST_Msk (0x1U << CRM_APB1RST_UART5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB1RST_UART5RST CRM_APB1RST_UART5RST_Msk /*!< UART5 reset */ +#define CRM_APB1RST_I2C1RST_Pos (21U) +#define CRM_APB1RST_I2C1RST_Msk (0x1U << CRM_APB1RST_I2C1RST_Pos) /*!< 0x00200000 */ +#define CRM_APB1RST_I2C1RST CRM_APB1RST_I2C1RST_Msk /*!< I2C1 reset */ +#define CRM_APB1RST_I2C2RST_Pos (22U) +#define CRM_APB1RST_I2C2RST_Msk (0x1U << CRM_APB1RST_I2C2RST_Pos) /*!< 0x00400000 */ +#define CRM_APB1RST_I2C2RST CRM_APB1RST_I2C2RST_Msk /*!< I2C2 reset */ +#define CRM_APB1RST_CAN1RST_Pos (25U) +#define CRM_APB1RST_CAN1RST_Msk (0x1U << CRM_APB1RST_CAN1RST_Pos) /*!< 0x02000000 */ +#define CRM_APB1RST_CAN1RST CRM_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ +#define CRM_APB1RST_PWCRST_Pos (28U) +#define CRM_APB1RST_PWCRST_Msk (0x1U << CRM_APB1RST_PWCRST_Pos) /*!< 0x10000000 */ +#define CRM_APB1RST_PWCRST CRM_APB1RST_PWCRST_Msk /*!< PWC reset */ + +/****************** Bit definition for CRM_AHBEN register *******************/ +#define CRM_AHBEN_DMA1EN_Pos (0U) +#define CRM_AHBEN_DMA1EN_Msk (0x1U << CRM_AHBEN_DMA1EN_Pos) /*!< 0x00000001 */ +#define CRM_AHBEN_DMA1EN CRM_AHBEN_DMA1EN_Msk /*!< DMA1 clock enable */ +#define CRM_AHBEN_DMA2EN_Pos (1U) +#define CRM_AHBEN_DMA2EN_Msk (0x1U << CRM_AHBEN_DMA2EN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN_DMA2EN CRM_AHBEN_DMA2EN_Msk /*!< DMA2 clock enable */ +#define CRM_AHBEN_SRAMEN_Pos (2U) +#define CRM_AHBEN_SRAMEN_Msk (0x1U << CRM_AHBEN_SRAMEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBEN_SRAMEN CRM_AHBEN_SRAMEN_Msk /*!< SRAM clock enable */ +#define CRM_AHBEN_FLASHEN_Pos (4U) +#define CRM_AHBEN_FLASHEN_Msk (0x1U << CRM_AHBEN_FLASHEN_Pos) /*!< 0x00000010 */ +#define CRM_AHBEN_FLASHEN CRM_AHBEN_FLASHEN_Msk /*!< Flash clock enable */ +#define CRM_AHBEN_CRCEN_Pos (6U) +#define CRM_AHBEN_CRCEN_Msk (0x1U << CRM_AHBEN_CRCEN_Pos) /*!< 0x00000040 */ +#define CRM_AHBEN_CRCEN CRM_AHBEN_CRCEN_Msk /*!< CRC clock enable */ +#define CRM_AHBEN_SDIOEN_Pos (10U) +#define CRM_AHBEN_SDIOEN_Msk (0x1U << CRM_AHBEN_SDIOEN_Pos) /*!< 0x00000400 */ +#define CRM_AHBEN_SDIOEN CRM_AHBEN_SDIOEN_Msk /*!< SDIO clock enable */ +#define CRM_AHBEN_OTGFSEN_Pos (12U) +#define CRM_AHBEN_OTGFSEN_Msk (0x1U << CRM_AHBEN_OTGFSEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBEN_OTGFSEN CRM_AHBEN_OTGFSEN_Msk /*!< OTGFS clock enable */ + +/****************** Bit definition for CRM_APB2EN register ******************/ +#define CRM_APB2EN_IOMUXEN_Pos (0U) +#define CRM_APB2EN_IOMUXEN_Msk (0x1U << CRM_APB2EN_IOMUXEN_Pos) /*!< 0x00000001 */ +#define CRM_APB2EN_IOMUXEN CRM_APB2EN_IOMUXEN_Msk /*!< IOMUX clock enable */ +#define CRM_APB2EN_GPIOAEN_Pos (2U) +#define CRM_APB2EN_GPIOAEN_Msk (0x1U << CRM_APB2EN_GPIOAEN_Pos) /*!< 0x00000004 */ +#define CRM_APB2EN_GPIOAEN CRM_APB2EN_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define CRM_APB2EN_GPIOBEN_Pos (3U) +#define CRM_APB2EN_GPIOBEN_Msk (0x1U << CRM_APB2EN_GPIOBEN_Pos) /*!< 0x00000008 */ +#define CRM_APB2EN_GPIOBEN CRM_APB2EN_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define CRM_APB2EN_GPIOCEN_Pos (4U) +#define CRM_APB2EN_GPIOCEN_Msk (0x1U << CRM_APB2EN_GPIOCEN_Pos) /*!< 0x00000010 */ +#define CRM_APB2EN_GPIOCEN CRM_APB2EN_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define CRM_APB2EN_GPIODEN_Pos (5U) +#define CRM_APB2EN_GPIODEN_Msk (0x1U << CRM_APB2EN_GPIODEN_Pos) /*!< 0x00000020 */ +#define CRM_APB2EN_GPIODEN CRM_APB2EN_GPIODEN_Msk /*!< GPIOD clock enable */ +#define CRM_APB2EN_GPIOFEN_Pos (7U) +#define CRM_APB2EN_GPIOFEN_Msk (0x1U << CRM_APB2EN_GPIOFEN_Pos) /*!< 0x00000080 */ +#define CRM_APB2EN_GPIOFEN CRM_APB2EN_GPIOFEN_Msk /*!< GPIOF clock enable */ +#define CRM_APB2EN_ADC1EN_Pos (9U) +#define CRM_APB2EN_ADC1EN_Msk (0x1U << CRM_APB2EN_ADC1EN_Pos) /*!< 0x00000200 */ +#define CRM_APB2EN_ADC1EN CRM_APB2EN_ADC1EN_Msk /*!< ADC1 clock enable */ +#define CRM_APB2EN_TMR1EN_Pos (11U) +#define CRM_APB2EN_TMR1EN_Msk (0x1U << CRM_APB2EN_TMR1EN_Pos) /*!< 0x00000800 */ +#define CRM_APB2EN_TMR1EN CRM_APB2EN_TMR1EN_Msk /*!< TMR1 clock enable */ +#define CRM_APB2EN_SPI1EN_Pos (12U) +#define CRM_APB2EN_SPI1EN_Msk (0x1U << CRM_APB2EN_SPI1EN_Pos) /*!< 0x00001000 */ +#define CRM_APB2EN_SPI1EN CRM_APB2EN_SPI1EN_Msk /*!< SPI1 clock enable */ +#define CRM_APB2EN_USART1EN_Pos (14U) +#define CRM_APB2EN_USART1EN_Msk (0x1U << CRM_APB2EN_USART1EN_Pos) /*!< 0x00004000 */ +#define CRM_APB2EN_USART1EN CRM_APB2EN_USART1EN_Msk /*!< USART1 clock enable */ +#define CRM_APB2EN_TMR9EN_Pos (19U) +#define CRM_APB2EN_TMR9EN_Msk (0x1U << CRM_APB2EN_TMR9EN_Pos) /*!< 0x00080000 */ +#define CRM_APB2EN_TMR9EN CRM_APB2EN_TMR9EN_Msk /*!< TMR9 clock enable */ +#define CRM_APB2EN_TMR10EN_Pos (20U) +#define CRM_APB2EN_TMR10EN_Msk (0x1U << CRM_APB2EN_TMR10EN_Pos) /*!< 0x00100000 */ +#define CRM_APB2EN_TMR10EN CRM_APB2EN_TMR10EN_Msk /*!< TMR10 clock enable */ +#define CRM_APB2EN_TMR11EN_Pos (21U) +#define CRM_APB2EN_TMR11EN_Msk (0x1U << CRM_APB2EN_TMR11EN_Pos) /*!< 0x00200000 */ +#define CRM_APB2EN_TMR11EN CRM_APB2EN_TMR11EN_Msk /*!< TMR11 clock enable */ + +/****************** Bit definition for CRM_APB1EN register ******************/ +#define CRM_APB1EN_TMR2EN_Pos (0U) +#define CRM_APB1EN_TMR2EN_Msk (0x1U << CRM_APB1EN_TMR2EN_Pos) /*!< 0x00000001 */ +#define CRM_APB1EN_TMR2EN CRM_APB1EN_TMR2EN_Msk /*!< TMR2 clock enable */ +#define CRM_APB1EN_TMR3EN_Pos (1U) +#define CRM_APB1EN_TMR3EN_Msk (0x1U << CRM_APB1EN_TMR3EN_Pos) /*!< 0x00000002 */ +#define CRM_APB1EN_TMR3EN CRM_APB1EN_TMR3EN_Msk /*!< TMR3 clock enable */ +#define CRM_APB1EN_TMR4EN_Pos (2U) +#define CRM_APB1EN_TMR4EN_Msk (0x1U << CRM_APB1EN_TMR4EN_Pos) /*!< 0x00000004 */ +#define CRM_APB1EN_TMR4EN CRM_APB1EN_TMR4EN_Msk /*!< TMR4 clock enable */ +#define CRM_APB1EN_TMR5EN_Pos (3U) +#define CRM_APB1EN_TMR5EN_Msk (0x1U << CRM_APB1EN_TMR5EN_Pos) /*!< 0x00000008 */ +#define CRM_APB1EN_TMR5EN CRM_APB1EN_TMR5EN_Msk /*!< TMR5 clock enable */ +#define CRM_APB1EN_CMPEN_Pos (9U) +#define CRM_APB1EN_CMPEN_Msk (0x1U << CRM_APB1EN_CMPEN_Pos) /*!< 0x00000200 */ +#define CRM_APB1EN_CMPEN CRM_APB1EN_CMPEN_Msk /*!< CMP clock enable */ +#define CRM_APB1EN_WWDTEN_Pos (11U) +#define CRM_APB1EN_WWDTEN_Msk (0x1U << CRM_APB1EN_WWDTEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1EN_WWDTEN CRM_APB1EN_WWDTEN_Msk /*!< WWDT clock enable */ +#define CRM_APB1EN_SPI2EN_Pos (14U) +#define CRM_APB1EN_SPI2EN_Msk (0x1U << CRM_APB1EN_SPI2EN_Pos) /*!< 0x00004000 */ +#define CRM_APB1EN_SPI2EN CRM_APB1EN_SPI2EN_Msk /*!< SPI2 clock enable */ +#define CRM_APB1EN_USART2EN_Pos (17U) +#define CRM_APB1EN_USART2EN_Msk (0x1U << CRM_APB1EN_USART2EN_Pos) /*!< 0x00020000 */ +#define CRM_APB1EN_USART2EN CRM_APB1EN_USART2EN_Msk /*!< USART2 clock enable */ +#define CRM_APB1EN_USART3EN_Pos (18U) +#define CRM_APB1EN_USART3EN_Msk (0x1U << CRM_APB1EN_USART3EN_Pos) /*!< 0x00040000 */ +#define CRM_APB1EN_USART3EN CRM_APB1EN_USART3EN_Msk /*!< USART3 clock enable */ +#define CRM_APB1EN_UART4EN_Pos (19U) +#define CRM_APB1EN_UART4EN_Msk (0x1U << CRM_APB1EN_UART4EN_Pos) /*!< 0x00080000 */ +#define CRM_APB1EN_UART4EN CRM_APB1EN_UART4EN_Msk /*!< UART4 clock enable */ +#define CRM_APB1EN_UART5EN_Pos (20U) +#define CRM_APB1EN_UART5EN_Msk (0x1U << CRM_APB1EN_UART5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB1EN_UART5EN CRM_APB1EN_UART5EN_Msk /*!< UART5 clock enable */ +#define CRM_APB1EN_I2C1EN_Pos (21U) +#define CRM_APB1EN_I2C1EN_Msk (0x1U << CRM_APB1EN_I2C1EN_Pos) /*!< 0x00200000 */ +#define CRM_APB1EN_I2C1EN CRM_APB1EN_I2C1EN_Msk /*!< I2C1 clock enable */ +#define CRM_APB1EN_I2C2EN_Pos (22U) +#define CRM_APB1EN_I2C2EN_Msk (0x1U << CRM_APB1EN_I2C2EN_Pos) /*!< 0x00400000 */ +#define CRM_APB1EN_I2C2EN CRM_APB1EN_I2C2EN_Msk /*!< I2C2 clock enable */ +#define CRM_APB1EN_CAN1EN_Pos (25U) +#define CRM_APB1EN_CAN1EN_Msk (0x1U << CRM_APB1EN_CAN1EN_Pos) /*!< 0x02000000 */ +#define CRM_APB1EN_CAN1EN CRM_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ +#define CRM_APB1EN_PWCEN_Pos (28U) +#define CRM_APB1EN_PWCEN_Msk (0x1U << CRM_APB1EN_PWCEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1EN_PWCEN CRM_APB1EN_PWCEN_Msk /*!< Power control clock enable */ + +/******************* Bit definition for CRM_BPDC register *******************/ +#define CRM_BPDC_LEXTEN_Pos (0U) +#define CRM_BPDC_LEXTEN_Msk (0x1U << CRM_BPDC_LEXTEN_Pos) /*!< 0x00000001 */ +#define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ +#define CRM_BPDC_LEXTSTBL_Pos (1U) +#define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< Low speed external oscillator stable */ +#define CRM_BPDC_LEXTBYPS_Pos (2U) +#define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< Low speed external crystal bypass */ + +/*!< ERTCSEL congiguration */ +#define CRM_BPDC_ERTCSEL_Pos (8U) +#define CRM_BPDC_ERTCSEL_Msk (0x3U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000300 */ +#define CRM_BPDC_ERTCSEL CRM_BPDC_ERTCSEL_Msk /*!< ERTCSEL[1:0] bits (ERTC clock selection) */ +#define CRM_BPDC_ERTCSEL_0 (0x1U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000100 */ +#define CRM_BPDC_ERTCSEL_1 (0x2U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000200 */ + +#define CRM_BPDC_ERTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define CRM_BPDC_ERTCSEL_LEXT 0x00000100U /*!< LEXT */ +#define CRM_BPDC_ERTCSEL_LICK 0x00000200U /*!< LICK */ +#define CRM_BPDC_ERTCSEL_HEXT 0x00000300U /*!< HEXT/128 */ + +#define CRM_BPDC_ERTCEN_Pos (15U) +#define CRM_BPDC_ERTCEN_Msk (0x1U << CRM_BPDC_ERTCEN_Pos) /*!< 0x00008000 */ +#define CRM_BPDC_ERTCEN CRM_BPDC_ERTCEN_Msk /*!< ERTC clock enable */ +#define CRM_BPDC_BPDRST_Pos (16U) +#define CRM_BPDC_BPDRST_Msk (0x1U << CRM_BPDC_BPDRST_Pos) /*!< 0x00010000 */ +#define CRM_BPDC_BPDRST CRM_BPDC_BPDRST_Msk /*!< Battery powered domain software reset */ + +/***************** Bit definition for CRM_CTRLSTS register ******************/ +#define CRM_CTRLSTS_LICKEN_Pos (0U) +#define CRM_CTRLSTS_LICKEN_Msk (0x1U << CRM_CTRLSTS_LICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRLSTS_LICKEN CRM_CTRLSTS_LICKEN_Msk /*!< LICK enable */ +#define CRM_CTRLSTS_LICKSTBL_Pos (1U) +#define CRM_CTRLSTS_LICKSTBL_Msk (0x1U << CRM_CTRLSTS_LICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRLSTS_LICKSTBL CRM_CTRLSTS_LICKSTBL_Msk /*!< LICK stable */ +#define CRM_CTRLSTS_RSTFC_Pos (24U) +#define CRM_CTRLSTS_RSTFC_Msk (0x1U << CRM_CTRLSTS_RSTFC_Pos) /*!< 0x01000000 */ +#define CRM_CTRLSTS_RSTFC CRM_CTRLSTS_RSTFC_Msk /*!< Reset flag clear */ +#define CRM_CTRLSTS_NRSTF_Pos (26U) +#define CRM_CTRLSTS_NRSTF_Msk (0x1U << CRM_CTRLSTS_NRSTF_Pos) /*!< 0x04000000 */ +#define CRM_CTRLSTS_NRSTF CRM_CTRLSTS_NRSTF_Msk /*!< NRST pin reset flag */ +#define CRM_CTRLSTS_PORRSTF_Pos (27U) +#define CRM_CTRLSTS_PORRSTF_Msk (0x1U << CRM_CTRLSTS_PORRSTF_Pos) /*!< 0x08000000 */ +#define CRM_CTRLSTS_PORRSTF CRM_CTRLSTS_PORRSTF_Msk /*!< POR/LVR reset flag */ +#define CRM_CTRLSTS_SWRSTF_Pos (28U) +#define CRM_CTRLSTS_SWRSTF_Msk (0x1U << CRM_CTRLSTS_SWRSTF_Pos) /*!< 0x10000000 */ +#define CRM_CTRLSTS_SWRSTF CRM_CTRLSTS_SWRSTF_Msk /*!< Software reset flag */ +#define CRM_CTRLSTS_WDTRSTF_Pos (29U) +#define CRM_CTRLSTS_WDTRSTF_Msk (0x1U << CRM_CTRLSTS_WDTRSTF_Pos) /*!< 0x20000000 */ +#define CRM_CTRLSTS_WDTRSTF CRM_CTRLSTS_WDTRSTF_Msk /*!< Watchdog timer reset flag */ +#define CRM_CTRLSTS_WWDTRSTF_Pos (30U) +#define CRM_CTRLSTS_WWDTRSTF_Msk (0x1U << CRM_CTRLSTS_WWDTRSTF_Pos) /*!< 0x40000000 */ +#define CRM_CTRLSTS_WWDTRSTF CRM_CTRLSTS_WWDTRSTF_Msk /*!< Window watchdog timer reset flag */ +#define CRM_CTRLSTS_LPRSTF_Pos (31U) +#define CRM_CTRLSTS_LPRSTF_Msk (0x1U << CRM_CTRLSTS_LPRSTF_Pos) /*!< 0x80000000 */ +#define CRM_CTRLSTS_LPRSTF CRM_CTRLSTS_LPRSTF_Msk /*!< Low-power reset flag */ + +/****************** Bit definition for CRM_AHBRST register ******************/ +#define CRM_AHBRST_OTGFSRST_Pos (12U) +#define CRM_AHBRST_OTGFSRST_Msk (0x1U << CRM_AHBRST_OTGFSRST_Pos) /*!< 0x00001000 */ +#define CRM_AHBRST_OTGFSRST CRM_AHBRST_OTGFSRST_Msk /*!< OTGFS reset */ + +/******************* Bit definition for CRM_PLL register ********************/ +/*!< PLL_FR congiguration */ +#define CRM_PLL_PLL_FR_Pos (0U) +#define CRM_PLL_PLL_FR_Msk (0x7U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000007 */ +#define CRM_PLL_PLL_FR CRM_PLL_PLL_FR_Msk /*!< PLL_FR[2:0] bits (PLL post-division factor) */ +#define CRM_PLL_PLL_FR_0 (0x1U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000001 */ +#define CRM_PLL_PLL_FR_1 (0x2U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000002 */ +#define CRM_PLL_PLL_FR_2 (0x4U << CRM_PLL_PLL_FR_Pos) /*!< 0x00000004 */ + +/*!< PLL_MS congiguration */ +#define CRM_PLL_PLL_MS_Pos (4U) +#define CRM_PLL_PLL_MS_Msk (0xFU << CRM_PLL_PLL_MS_Pos) /*!< 0x000000F0 */ +#define CRM_PLL_PLL_MS CRM_PLL_PLL_MS_Msk /*!< PLL_MS[3:0] bits (PLL pre-division) */ +#define CRM_PLL_PLL_MS_0 (0x1U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000010 */ +#define CRM_PLL_PLL_MS_1 (0x2U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000020 */ +#define CRM_PLL_PLL_MS_2 (0x4U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000040 */ +#define CRM_PLL_PLL_MS_3 (0x8U << CRM_PLL_PLL_MS_Pos) /*!< 0x00000080 */ + +/*!< PLL_NS congiguration */ +#define CRM_PLL_PLL_NS_Pos (8U) +#define CRM_PLL_PLL_NS_Msk (0x1FFU << CRM_PLL_PLL_NS_Pos) /*!< 0x0001FF00 */ +#define CRM_PLL_PLL_NS CRM_PLL_PLL_NS_Msk /*!< PLL_NS[8:0] bits (PLL multiplication factor) */ +#define CRM_PLL_PLL_NS_0 (0x001U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000100 */ +#define CRM_PLL_PLL_NS_1 (0x002U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000200 */ +#define CRM_PLL_PLL_NS_2 (0x004U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000400 */ +#define CRM_PLL_PLL_NS_3 (0x008U << CRM_PLL_PLL_NS_Pos) /*!< 0x00000800 */ +#define CRM_PLL_PLL_NS_4 (0x010U << CRM_PLL_PLL_NS_Pos) /*!< 0x00001000 */ +#define CRM_PLL_PLL_NS_5 (0x020U << CRM_PLL_PLL_NS_Pos) /*!< 0x00002000 */ +#define CRM_PLL_PLL_NS_6 (0x040U << CRM_PLL_PLL_NS_Pos) /*!< 0x00004000 */ +#define CRM_PLL_PLL_NS_7 (0x080U << CRM_PLL_PLL_NS_Pos) /*!< 0x00008000 */ +#define CRM_PLL_PLL_NS_8 (0x100U << CRM_PLL_PLL_NS_Pos) /*!< 0x00010000 */ + +/*!< PLL_FREF congiguration */ +#define CRM_PLL_PLL_FREF_Pos (24U) +#define CRM_PLL_PLL_FREF_Msk (0x7U << CRM_PLL_PLL_FREF_Pos) /*!< 0x07000000 */ +#define CRM_PLL_PLL_FREF CRM_PLL_PLL_FREF_Msk /*!< PLL_FREF[2:0] bits (PLL input clock selection) */ +#define CRM_PLL_PLL_FREF_0 (0x1U << CRM_PLL_PLL_FREF_Pos) /*!< 0x01000000 */ +#define CRM_PLL_PLL_FREF_1 (0x2U << CRM_PLL_PLL_FREF_Pos) /*!< 0x02000000 */ +#define CRM_PLL_PLL_FREF_2 (0x4U << CRM_PLL_PLL_FREF_Pos) /*!< 0x04000000 */ + +#define CRM_PLL_PLL_FREF_4M 0x00000000U /*!< 3.9 ~ 5 MHz */ +#define CRM_PLL_PLL_FREF_6M 0x01000000U /*!< 5.2 ~ 6.25 MHz */ +#define CRM_PLL_PLL_FREF_8M 0x02000000U /*!< 7.8125 ~ 8.33 MHz */ +#define CRM_PLL_PLL_FREF_12M 0x03000000U /*!< 8.33 ~ 12.5 MHz */ +#define CRM_PLL_PLL_FREF_16M 0x04000000U /*!< 15.625 ~ 20.83 MHz */ +#define CRM_PLL_PLL_FREF_25M 0x05000000U /*!< 20.83 ~ 31.255 MHz */ + +#define CRM_PLL_PLLCFGEN_Pos (31U) +#define CRM_PLL_PLLCFGEN_Msk (0x1U << CRM_PLL_PLLCFGEN_Pos) /*!< 0x80000000 */ +#define CRM_PLL_PLLCFGEN CRM_PLL_PLLCFGEN_Msk /*!< PLL configuration enable */ + +/****************** Bit definition for CRM_MISC1 register *******************/ +#define CRM_MISC1_HICKCAL_KEY_Pos (0U) +#define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ +#define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ +#define CRM_MISC1_CLKOUT_SEL_Pos (16U) +#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRN_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL CRM_MISC1_CLKOUT_SEL_Msk /*!< Clock output selection */ +#define CRM_MISC1_CLKFMC_SRC_Pos (20U) +#define CRM_MISC1_CLKFMC_SRC_Msk (0x1U << CRM_MISC1_CLKFMC_SRC_Pos) /*!< 0x00100000 */ +#define CRM_MISC1_CLKFMC_SRC CRM_MISC1_CLKFMC_SRC_Msk /*!< FMC clock source */ +#define CRM_MISC1_HICKDIV_Pos (25U) +#define CRM_MISC1_HICKDIV_Msk (0x1U << CRM_MISC1_HICKDIV_Pos) /*!< 0x02000000 */ +#define CRM_MISC1_HICKDIV CRM_MISC1_HICKDIV_Msk /*!< HICK 6 divider selection */ + +/*!< CLKOUTDIV congiguration */ +#define CRM_MISC1_CLKOUTDIV_Pos (28U) +#define CRM_MISC1_CLKOUTDIV_Msk (0xFU << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0xF0000000 */ +#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division */ +#define CRM_MISC1_CLKOUTDIV_0 (0x1U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x10000000 */ +#define CRM_MISC1_CLKOUTDIV_1 (0x2U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x20000000 */ +#define CRM_MISC1_CLKOUTDIV_2 (0x4U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x40000000 */ +#define CRM_MISC1_CLKOUTDIV_3 (0x8U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x80000000 */ + +#define CRM_MISC1_CLKOUTDIV_DIV1 0x00000000U /*!< No clock output */ +#define CRM_MISC1_CLKOUTDIV_DIV2 0x80000000U /*!< Clock output divided by 2 */ +#define CRM_MISC1_CLKOUTDIV_DIV4 0x90000000U /*!< Clock output divided by 4 */ +#define CRM_MISC1_CLKOUTDIV_DIV8 0xA0000000U /*!< Clock output divided by 8 */ +#define CRM_MISC1_CLKOUTDIV_DIV16 0xB0000000U /*!< Clock output divided by 16 */ +#define CRM_MISC1_CLKOUTDIV_DIV64 0xC0000000U /*!< Clock output divided by 64 */ +#define CRM_MISC1_CLKOUTDIV_DIV128 0xD0000000U /*!< Clock output divided by 128 */ +#define CRM_MISC1_CLKOUTDIV_DIV256 0xE0000000U /*!< Clock output divided by 256 */ +#define CRM_MISC1_CLKOUTDIV_DIV512 0xF0000000U /*!< Clock output divided by 512 */ + +/*************** Bit definition for CRM_OTG_EXTCTRL register ****************/ +#define CRM_OTG_EXTCTRL_USBDIV_RST_Pos (30U) /*!< 0x40000000 */ +#define CRM_OTG_EXTCTRL_USBDIV_RST_Msk (0x1U << CRM_OTG_EXTCTRL_USBDIV_RST_Pos) +#define CRM_OTG_EXTCTRL_USBDIV_RST CRM_OTG_EXTCTRL_USBDIV_RST_Msk /*!< USB divider reset */ +#define CRM_OTG_EXTCTRL_EP3_RMPEN_Pos (31U) +#define CRM_OTG_EXTCTRL_EP3_RMPEN_Msk (0x1U << CRM_OTG_EXTCTRL_EP3_RMPEN_Pos) /*!< 0x80000000 */ +#define CRM_OTG_EXTCTRL_EP3_RMPEN CRM_OTG_EXTCTRL_EP3_RMPEN_Msk /*!< Endpoint 3 remap enable */ + +/****************** Bit definition for CRM_MISC2 register *******************/ +/*!< AUTO_STEP_EN congiguration */ +#define CRM_MISC2_AUTO_STEP_EN_Pos (4U) +#define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] Auto step-by-step SCLK switch enable */ +#define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ +#define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ + +#define CRM_MISC2_HICK_TO_SCLK_Pos (9U) +#define CRM_MISC2_HICK_TO_SCLK_Msk (0x1U << CRM_MISC2_HICK_TO_SCLK_Pos) /*!< 0x00000200 */ +#define CRM_MISC2_HICK_TO_SCLK CRM_MISC2_HICK_TO_SCLK_Msk /*!< HICK as system clock frequency select */ + +/******************************************************************************/ +/* */ +/* Flash and User System Data Registers (FLASH) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_PSR register ******************/ +/*!< WTCYC congiguration */ +#define FLASH_PSR_WTCYC_Pos (0U) +#define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] Wait states */ +#define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ +#define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ +#define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ + +#define FLASH_PSR_HFCYC_EN_Pos (3U) +#define FLASH_PSR_HFCYC_EN_Msk (0x1U << FLASH_PSR_HFCYC_EN_Pos) /*!< 0x00000008 */ +#define FLASH_PSR_HFCYC_EN FLASH_PSR_HFCYC_EN_Msk /*!< Half cycle acceleration access enable */ +#define FLASH_PSR_PFT_EN_Pos (4U) +#define FLASH_PSR_PFT_EN_Msk (0x1U << FLASH_PSR_PFT_EN_Pos) /*!< 0x00000010 */ +#define FLASH_PSR_PFT_EN FLASH_PSR_PFT_EN_Msk /*!< Prefetch enable */ +#define FLASH_PSR_PFT_ENF_Pos (5U) +#define FLASH_PSR_PFT_ENF_Msk (0x1U << FLASH_PSR_PFT_ENF_Pos) /*!< 0x00000020 */ +#define FLASH_PSR_PFT_ENF FLASH_PSR_PFT_ENF_Msk /*!< Prefetch enable flag */ + +/***************** Bit definition for FLASH_UNLOCK register *****************/ +#define FLASH_UNLOCK_UKVAL_Pos (0U) +#define FLASH_UNLOCK_UKVAL_Msk (0xFFFFFFFFU << FLASH_UNLOCK_UKVAL_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_UNLOCK_UKVAL FLASH_UNLOCK_UKVAL_Msk /*!< Unlock key value */ + +#define FAP_KEY_Pos (0U) +#define FAP_KEY_Msk (0xA5U << FAP_KEY_Pos) /*!< 0x000000A5 */ +#define FAP_KEY FAP_KEY_Msk /*!< Flash access protection key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash key 1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash key 2 */ + +/*************** Bit definition for FLASH_USD_UNLOCK register ***************/ +#define FLASH_USD_UNLOCK_USD_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_USD_UNLOCK_USD_UKVAL_Msk (0xFFFFFFFFU << FLASH_USD_UNLOCK_USD_UKVAL_Pos) +#define FLASH_USD_UNLOCK_USD_UKVAL FLASH_USD_UNLOCK_USD_UKVAL_Msk /*!< User system data unlock key value */ + +#define FLASH_USDKEY1 FLASH_KEY1 /*!< User system data key 1 */ +#define FLASH_USDKEY2 FLASH_KEY2 /*!< User system data key 2 */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_OBF_Pos (0U) +#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation done flag */ +#define FLASH_STS_PRGMERR_Pos (2U) +#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ +#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ +#define FLASH_STS_EPPERR_Pos (4U) +#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */ +#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk /*!< Erase/program protection error */ +#define FLASH_STS_ODF_Pos (5U) +#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */ +#define FLASH_STS_ODF FLASH_STS_ODF_Msk /*!< Operation done flag */ + +/****************** Bit definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_FPRGM_Pos (0U) +#define FLASH_CTRL_FPRGM_Msk (0x1U << FLASH_CTRL_FPRGM_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_FPRGM FLASH_CTRL_FPRGM_Msk /*!< Flash program */ +#define FLASH_CTRL_SECERS_Pos (1U) +#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk /*!< Page erase */ +#define FLASH_CTRL_BANKERS_Pos (2U) +#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk /*!< Bank erase */ +#define FLASH_CTRL_USDPRGM_Pos (4U) +#define FLASH_CTRL_USDPRGM_Msk (0x1U << FLASH_CTRL_USDPRGM_Pos) /*!< 0x00000010 */ +#define FLASH_CTRL_USDPRGM FLASH_CTRL_USDPRGM_Msk /*!< User system data program */ +#define FLASH_CTRL_USDERS_Pos (5U) +#define FLASH_CTRL_USDERS_Msk (0x1U << FLASH_CTRL_USDERS_Pos) /*!< 0x00000020 */ +#define FLASH_CTRL_USDERS FLASH_CTRL_USDERS_Msk /*!< User system data erase */ +#define FLASH_CTRL_ERSTR_Pos (6U) +#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x00000040 */ +#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk /*!< Erase start */ +#define FLASH_CTRL_OPLK_Pos (7U) +#define FLASH_CTRL_OPLK_Msk (0x1U << FLASH_CTRL_OPLK_Pos) /*!< 0x00000080 */ +#define FLASH_CTRL_OPLK FLASH_CTRL_OPLK_Msk /*!< Operation lock */ +#define FLASH_CTRL_USDULKS_Pos (9U) +#define FLASH_CTRL_USDULKS_Msk (0x1U << FLASH_CTRL_USDULKS_Pos) /*!< 0x00000200 */ +#define FLASH_CTRL_USDULKS FLASH_CTRL_USDULKS_Msk /*!< User system data unlock success */ +#define FLASH_CTRL_ERRIE_Pos (10U) +#define FLASH_CTRL_ERRIE_Msk (0x1U << FLASH_CTRL_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CTRL_ERRIE FLASH_CTRL_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CTRL_ODFIE_Pos (12U) +#define FLASH_CTRL_ODFIE_Msk (0x1U << FLASH_CTRL_ODFIE_Pos) /*!< 0x00001000 */ +#define FLASH_CTRL_ODFIE FLASH_CTRL_ODFIE_Msk /*!< Operation done flag interrupt enable */ +#define FLASH_CTRL_FAP_HL_DIS_Pos (16U) +#define FLASH_CTRL_FAP_HL_DIS_Msk (0x1U << FLASH_CTRL_FAP_HL_DIS_Pos) /*!< 0x00010000 */ +#define FLASH_CTRL_FAP_HL_DIS FLASH_CTRL_FAP_HL_DIS_Msk /*!< High level Flash access protection disable */ + +/****************** Bit definition for FLASH_ADDR register ******************/ +#define FLASH_ADDR_FA_Pos (0U) +#define FLASH_ADDR_FA_Msk (0xFFFFFFFFU << FLASH_ADDR_FA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_ADDR_FA FLASH_ADDR_FA_Msk /*!< Flash address */ + +/****************** Bit definition for FLASH_USD register *******************/ +#define FLASH_USD_USDERR_Pos (0U) +#define FLASH_USD_USDERR_Msk (0x1U << FLASH_USD_USDERR_Pos) /*!< 0x00000001 */ +#define FLASH_USD_USDERR FLASH_USD_USDERR_Msk /*!< User system data error */ +#define FLASH_USD_FAP_Pos (1U) +#define FLASH_USD_FAP_Msk (0x1U << FLASH_USD_FAP_Pos) /*!< 0x00000002 */ +#define FLASH_USD_FAP FLASH_USD_FAP_Msk /*!< Flash access protection */ + +/*!< SSB congiguration */ +#define FLASH_USD_WDT_ATO_EN_Pos (2U) +#define FLASH_USD_WDT_ATO_EN_Msk (0x1U << FLASH_USD_WDT_ATO_EN_Pos) /*!< 0x00000004 */ +#define FLASH_USD_WDT_ATO_EN FLASH_USD_WDT_ATO_EN_Msk /*!< nWDT_ATO_EN */ +#define FLASH_USD_DEPSLP_RST_Pos (3U) +#define FLASH_USD_DEPSLP_RST_Msk (0x1U << FLASH_USD_DEPSLP_RST_Pos) /*!< 0x00000008 */ +#define FLASH_USD_DEPSLP_RST FLASH_USD_DEPSLP_RST_Msk /*!< nDEPSLP_RST */ +#define FLASH_USD_STDBY_RST_Pos (4U) +#define FLASH_USD_STDBY_RST_Msk (0x1U << FLASH_USD_STDBY_RST_Pos) /*!< 0x00000010 */ +#define FLASH_USD_STDBY_RST FLASH_USD_STDBY_RST_Msk /*!< nSTDBY_RST */ +#define FLASH_USD_SSB_Pos (2U) +#define FLASH_USD_SSB_Msk (0x7U << FLASH_USD_SSB_Pos) /*!< 0x0000001C */ +#define FLASH_USD_SSB FLASH_USD_SSB_Msk /*!< System setting byte */ + +#define FLASH_USD_USER_D0_Pos (10U) +#define FLASH_USD_USER_D0_Msk (0xFFU << FLASH_USD_USER_D0_Pos) /*!< 0x0003FC00 */ +#define FLASH_USD_USER_D0 FLASH_USD_USER_D0_Msk /*!< User data 0 */ +#define FLASH_USD_USER_D1_Pos (18U) +#define FLASH_USD_USER_D1_Msk (0xFFU << FLASH_USD_USER_D1_Pos) /*!< 0x03FC0000 */ +#define FLASH_USD_USER_D1 FLASH_USD_USER_D1_Msk /*!< User data 1 */ +#define FLASH_USD_FAP_HL_Pos (26U) +#define FLASH_USD_FAP_HL_Msk (0x1U << FLASH_USD_FAP_HL_Pos) /*!< 0x04000000 */ +#define FLASH_USD_FAP_HL FLASH_USD_FAP_HL_Msk /*!< Flash access protection high level */ + +/****************** Bit definition for FLASH_EPPS register ******************/ +#define FLASH_EPPS_EPPS_Pos (0U) +#define FLASH_EPPS_EPPS_Msk (0xFFFFFFFFU << FLASH_EPPS_EPPS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_EPPS_EPPS FLASH_EPPS_EPPS_Msk /*!< Erase/Program protection status */ + +/******************* Bit definition for SLIB_STS0 register *******************/ +#define SLIB_STS0_BTM_AP_ENF_Pos (0U) +#define SLIB_STS0_BTM_AP_ENF_Msk (0x1U << SLIB_STS0_BTM_AP_ENF_Pos) /*!< 0x00000001 */ +#define SLIB_STS0_BTM_AP_ENF SLIB_STS0_BTM_AP_ENF_Msk /*!< Boot memory store application code enabled flag */ +#define SLIB_STS0_EM_SLIB_ENF_Pos (2U) +#define SLIB_STS0_EM_SLIB_ENF_Msk (0x1U << SLIB_STS0_EM_SLIB_ENF_Pos) /*!< 0x00000004 */ +#define SLIB_STS0_EM_SLIB_ENF SLIB_STS0_EM_SLIB_ENF_Msk /*!< Extension memory sLib enable flag */ +#define SLIB_STS0_SLIB_ENF_Pos (3U) +#define SLIB_STS0_SLIB_ENF_Msk (0x1U << SLIB_STS0_SLIB_ENF_Pos) /*!< 0x00000008 */ +#define SLIB_STS0_SLIB_ENF SLIB_STS0_SLIB_ENF_Msk /*!< Security library enable flag */ +#define SLIB_STS0_EM_SLIB_DAT_SS_Pos (16U) +#define SLIB_STS0_EM_SLIB_DAT_SS_Msk (0xFFU << SLIB_STS0_EM_SLIB_DAT_SS_Pos) /*!< 0x00FF0000 */ +#define SLIB_STS0_EM_SLIB_DAT_SS SLIB_STS0_EM_SLIB_DAT_SS_Msk /*!< Extension memory sLib data start page */ + +/******************* Bit definition for SLIB_STS1 register *******************/ +#define SLIB_STS1_SLIB_SS_Pos (0U) +#define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ +#define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ +#define SLIB_STS1_SLIB_DAT_SS_Pos (11U) +#define SLIB_STS1_SLIB_DAT_SS_Msk (0x3FF8U << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_DAT_SS SLIB_STS1_SLIB_DAT_SS_Msk /*!< Security library data start page */ +#define SLIB_STS1_SLIB_ES_Pos (22U) +#define SLIB_STS1_SLIB_ES_Msk (0xFFCU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ + +/***************** Bit definition for SLIB_PWD_CLR register ******************/ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk (0xFFFFFFFFU << SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos) +#define SLIB_PWD_CLR_SLIB_PCLR_VAL SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk /*!< Security library password clear value */ + +/***************** Bit definition for SLIB_MISC_STS register *****************/ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Pos (0U) /*!< 0x00000001 */ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_ERR_Pos) +#define SLIB_MISC_STS_SLIB_PWD_ERR SLIB_MISC_STS_SLIB_PWD_ERR_Msk /*!< Security library password error */ +#define SLIB_MISC_STS_SLIB_PWD_OK_Pos (1U) +#define SLIB_MISC_STS_SLIB_PWD_OK_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_OK_Pos) /*!< 0x00000002 */ +#define SLIB_MISC_STS_SLIB_PWD_OK SLIB_MISC_STS_SLIB_PWD_OK_Msk /*!< Security library password ok */ +#define SLIB_MISC_STS_SLIB_ULKF_Pos (2U) +#define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ +#define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ + +/***************** Bit definition for FLASH_CRC_ARR register *****************/ +#define FLASH_CRC_ARR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ARR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ARR_CRC_ADDR_Pos) +#define FLASH_CRC_ARR_CRC_ADDR FLASH_CRC_ARR_CRC_ADDR_Msk /*!< CRC address */ + +/**************** Bit definition for FLASH_CRC_CTRL register *****************/ +#define FLASH_CRC_CTRL_CRC_SN_Pos (0U) +#define FLASH_CRC_CTRL_CRC_SN_Msk (0xFFFFU << FLASH_CRC_CTRL_CRC_SN_Pos) /*!< 0x0000FFFF */ +#define FLASH_CRC_CTRL_CRC_SN FLASH_CRC_CTRL_CRC_SN_Msk /*!< CRC page number */ +#define FLASH_CRC_CTRL_CRC_STRT_Pos (16U) +#define FLASH_CRC_CTRL_CRC_STRT_Msk (0x1U << FLASH_CRC_CTRL_CRC_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CRC_CTRL_CRC_STRT FLASH_CRC_CTRL_CRC_STRT_Msk /*!< CRC start */ + +/**************** Bit definition for FLASH_CRC_CHKR register *****************/ +#define FLASH_CRC_CHKR_CRC_CHKR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_CHKR_CRC_CHKR_Msk (0xFFFFFFFFU << FLASH_CRC_CHKR_CRC_CHKR_Pos) +#define FLASH_CRC_CHKR_CRC_CHKR FLASH_CRC_CHKR_CRC_CHKR_Msk /*!< CRC check result */ + +/***************** Bit definition for SLIB_SET_PWD register ******************/ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< sLib password setting value */ + +/**************** Bit definition for SLIB_SET_RANGE register *****************/ +#define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ +#define SLIB_SET_RANGE_SLIB_SS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_SS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_SS_SET SLIB_SET_RANGE_SLIB_SS_SET_Msk /*!< Security library start page setting */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Pos (11U) /*!< 0x003FF800 */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Msk (0x3FF8U << SLIB_SET_RANGE_SLIB_ISS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ISS_SET SLIB_SET_RANGE_SLIB_ISS_SET_Msk /*!< Security library instruction start page setting */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Pos (22U) /*!< 0xFFC00000 */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Msk (0xFFCU << SLIB_SET_RANGE_SLIB_ES_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ES_SET SLIB_SET_RANGE_SLIB_ES_SET_Msk /*!< Security library end page setting */ + +/****************** Bit definition for EM_SLIB_SET register ******************/ +#define EM_SLIB_SET_EM_SLIB_SET_Pos (0U) /*!< 0x0000FFFF */ +#define EM_SLIB_SET_EM_SLIB_SET_Msk (0xFFFFU << EM_SLIB_SET_EM_SLIB_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page */ + +/***************** Bit definition for BTM_MODE_SET register ******************/ +#define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ +#define BTM_MODE_SET_BTM_MODE_SET_Msk (0xFFU << BTM_MODE_SET_BTM_MODE_SET_Pos) +#define BTM_MODE_SET_BTM_MODE_SET BTM_MODE_SET_BTM_MODE_SET_Msk /*!< Boot memory mode setting */ + +/***************** Bit definition for SLIB_UNLOCK register ******************/ +#define SLIB_UNLOCK_SLIB_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) +#define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ + +#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ +#define SLIB_KEY SLIB_KEY_Msk + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_FAP register *******************/ +#define FLASH_FAP_FAP_Pos (0U) +#define FLASH_FAP_FAP_Msk (0xFFU << FLASH_FAP_FAP_Pos) /*!< 0x000000FF */ +#define FLASH_FAP_FAP FLASH_FAP_FAP_Msk /*!< Flash memory access protection */ +#define FLASH_FAP_nFAP_Pos (8U) +#define FLASH_FAP_nFAP_Msk (0xFFU << FLASH_FAP_nFAP_Pos) /*!< 0x0000FF00 */ +#define FLASH_FAP_nFAP FLASH_FAP_nFAP_Msk /*!< Inverse code of flash memory access protection */ + +/****************** Bit definition for FLASH_SSB register *******************/ +#define FLASH_SSB_SSB_Pos (16U) +#define FLASH_SSB_SSB_Msk (0xFFU << FLASH_SSB_SSB_Pos) /*!< 0x00FF0000 */ +#define FLASH_SSB_SSB FLASH_SSB_SSB_Msk /*!< System configuration byte */ +#define FLASH_SSB_nSSB_Pos (24U) +#define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ +#define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ + +/****************** Bit definition for FLASH_DATA0 register *****************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ + +/****************** Bit definition for FLASH_DATA1 register *****************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< Inverse code of user data 1 */ + +/****************** Bit definition for FLASH_EPP0 register ******************/ +#define FLASH_EPP0_EPP0_Pos (0U) +#define FLASH_EPP0_EPP0_Msk (0xFFU << FLASH_EPP0_EPP0_Pos) /*!< 0x000000FF */ +#define FLASH_EPP0_EPP0 FLASH_EPP0_EPP0_Msk /*!< Flash erase/write protection byte 0 */ +#define FLASH_EPP0_nEPP0_Pos (8U) +#define FLASH_EPP0_nEPP0_Msk (0xFFU << FLASH_EPP0_nEPP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP0_nEPP0 FLASH_EPP0_nEPP0_Msk /*!< Inverse code of flash erase/write protection byte 0 */ + +/****************** Bit definition for FLASH_EPP1 register ******************/ +#define FLASH_EPP1_EPP1_Pos (16U) +#define FLASH_EPP1_EPP1_Msk (0xFFU << FLASH_EPP1_EPP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP1_EPP1 FLASH_EPP1_EPP1_Msk /*!< Flash erase/write protection byte 1 */ +#define FLASH_EPP1_nEPP1_Pos (24U) +#define FLASH_EPP1_nEPP1_Msk (0xFFU << FLASH_EPP1_nEPP1_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP1_nEPP1 FLASH_EPP1_nEPP1_Msk /*!< Inverse code of flash erase/write protection byte 1 */ + +/****************** Bit definition for FLASH_EPP2 register ******************/ +#define FLASH_EPP2_EPP2_Pos (0U) +#define FLASH_EPP2_EPP2_Msk (0xFFU << FLASH_EPP2_EPP2_Pos) /*!< 0x000000FF */ +#define FLASH_EPP2_EPP2 FLASH_EPP2_EPP2_Msk /*!< Flash erase/write protection byte 2 */ +#define FLASH_EPP2_nEPP2_Pos (8U) +#define FLASH_EPP2_nEPP2_Msk (0xFFU << FLASH_EPP2_nEPP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP2_nEPP2 FLASH_EPP2_nEPP2_Msk /*!< Inverse code of flash erase/write protection byte 2 */ + +/****************** Bit definition for FLASH_EPP3 register ******************/ +#define FLASH_EPP3_EPP3_Pos (16U) +#define FLASH_EPP3_EPP3_Msk (0xFFU << FLASH_EPP3_EPP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP3_EPP3 FLASH_EPP3_EPP3_Msk /*!< Flash erase/write protection byte 3 */ +#define FLASH_EPP3_nEPP3_Pos (24U) +#define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ + +/***************** Bit definition for FLASH_EOPB0 register ******************/ +#define FLASH_EOPB0_EOPB0_Pos (0U) +#define FLASH_EOPB0_EOPB0_Msk (0xFFU << FLASH_EOPB0_EOPB0_Pos) /*!< 0x000000FF */ +#define FLASH_EOPB0_EOPB0 FLASH_EOPB0_EOPB0_Msk /*!< Extended system options */ +#define FLASH_EOPB0_nEOPB0_Pos (8U) +#define FLASH_EOPB0_nEOPB0_Msk (0xFFU << FLASH_EOPB0_nEOPB0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EOPB0_nEOPB0 FLASH_EOPB0_nEOPB0_Msk /*!< Inverse code of extended system options */ + +/****************** Bit definition for FLASH_DATA2 register *****************/ +#define FLASH_DATA2_DATA2_Pos (0U) +#define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ +#define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ +#define FLASH_DATA2_nDATA2_Pos (8U) +#define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ + +/****************** Bit definition for FLASH_DATA3 register *****************/ +#define FLASH_DATA3_DATA3_Pos (16U) +#define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ +#define FLASH_DATA3_nDATA3_Pos (24U) +#define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ + +/****************** Bit definition for FLASH_DATA4 register *****************/ +#define FLASH_DATA4_DATA4_Pos (0U) +#define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ +#define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ +#define FLASH_DATA4_nDATA4_Pos (8U) +#define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ + +/****************** Bit definition for FLASH_DATA5 register *****************/ +#define FLASH_DATA5_DATA5_Pos (16U) +#define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ +#define FLASH_DATA5_nDATA5_Pos (24U) +#define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ + +/****************** Bit definition for FLASH_DATA6 register *****************/ +#define FLASH_DATA6_DATA6_Pos (0U) +#define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ +#define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ +#define FLASH_DATA6_nDATA6_Pos (8U) +#define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ + +/****************** Bit definition for FLASH_DATA7 register *****************/ +#define FLASH_DATA7_DATA7_Pos (16U) +#define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ +#define FLASH_DATA7_nDATA7_Pos (24U) +#define FLASH_DATA7_nDATA7_Msk (0xFFU << FLASH_DATA7_nDATA7_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA7_nDATA7 FLASH_DATA7_nDATA7_Msk /*!< Inverse code of user data 7 */ + +/*!< Noted: The FLASH_DATA go up to 505, it too long for added in here */ + +/******************************************************************************/ +/* */ +/* General-purpose I/Os (GPIO) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for GPIO_CFGLR register ******************/ +#define GPIO_CFGLR_IOMC_Pos (0U) +#define GPIO_CFGLR_IOMC_Msk (0x33333333U << GPIO_CFGLR_IOMC_Pos) /*!< 0x33333333 */ +#define GPIO_CFGLR_IOMC GPIO_CFGLR_IOMC_Msk /*!< GPIO x mode configuration */ + +#define GPIO_CFGLR_IOMC0_Pos (0U) +#define GPIO_CFGLR_IOMC0_Msk (0x3U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000003 */ +#define GPIO_CFGLR_IOMC0 GPIO_CFGLR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ +#define GPIO_CFGLR_IOMC0_0 (0x1U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000001 */ +#define GPIO_CFGLR_IOMC0_1 (0x2U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000002 */ + +#define GPIO_CFGLR_IOMC1_Pos (4U) +#define GPIO_CFGLR_IOMC1_Msk (0x3U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000030 */ +#define GPIO_CFGLR_IOMC1 GPIO_CFGLR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ +#define GPIO_CFGLR_IOMC1_0 (0x1U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000010 */ +#define GPIO_CFGLR_IOMC1_1 (0x2U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000020 */ + +#define GPIO_CFGLR_IOMC2_Pos (8U) +#define GPIO_CFGLR_IOMC2_Msk (0x3U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000300 */ +#define GPIO_CFGLR_IOMC2 GPIO_CFGLR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ +#define GPIO_CFGLR_IOMC2_0 (0x1U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000100 */ +#define GPIO_CFGLR_IOMC2_1 (0x2U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000200 */ + +#define GPIO_CFGLR_IOMC3_Pos (12U) +#define GPIO_CFGLR_IOMC3_Msk (0x3U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00003000 */ +#define GPIO_CFGLR_IOMC3 GPIO_CFGLR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ +#define GPIO_CFGLR_IOMC3_0 (0x1U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00001000 */ +#define GPIO_CFGLR_IOMC3_1 (0x2U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00002000 */ + +#define GPIO_CFGLR_IOMC4_Pos (16U) +#define GPIO_CFGLR_IOMC4_Msk (0x3U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00030000 */ +#define GPIO_CFGLR_IOMC4 GPIO_CFGLR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ +#define GPIO_CFGLR_IOMC4_0 (0x1U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00010000 */ +#define GPIO_CFGLR_IOMC4_1 (0x2U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00020000 */ + +#define GPIO_CFGLR_IOMC5_Pos (20U) +#define GPIO_CFGLR_IOMC5_Msk (0x3U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00300000 */ +#define GPIO_CFGLR_IOMC5 GPIO_CFGLR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ +#define GPIO_CFGLR_IOMC5_0 (0x1U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00100000 */ +#define GPIO_CFGLR_IOMC5_1 (0x2U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00200000 */ + +#define GPIO_CFGLR_IOMC6_Pos (24U) +#define GPIO_CFGLR_IOMC6_Msk (0x3U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x03000000 */ +#define GPIO_CFGLR_IOMC6 GPIO_CFGLR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ +#define GPIO_CFGLR_IOMC6_0 (0x1U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x01000000 */ +#define GPIO_CFGLR_IOMC6_1 (0x2U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x02000000 */ + +#define GPIO_CFGLR_IOMC7_Pos (28U) +#define GPIO_CFGLR_IOMC7_Msk (0x3U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x30000000 */ +#define GPIO_CFGLR_IOMC7 GPIO_CFGLR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ +#define GPIO_CFGLR_IOMC7_0 (0x1U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x10000000 */ +#define GPIO_CFGLR_IOMC7_1 (0x2U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x20000000 */ + +#define GPIO_CFGLR_IOFC_Pos (2U) +#define GPIO_CFGLR_IOFC_Msk (0x33333333U << GPIO_CFGLR_IOFC_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CFGLR_IOFC GPIO_CFGLR_IOFC_Msk /*!< GPIO x function configuration */ + +#define GPIO_CFGLR_IOFC0_Pos (2U) +#define GPIO_CFGLR_IOFC0_Msk (0x3U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x0000000C */ +#define GPIO_CFGLR_IOFC0 GPIO_CFGLR_IOFC0_Msk /*!< IOFC0[1:0] bits (GPIO x function configuration, pin 0) */ +#define GPIO_CFGLR_IOFC0_0 (0x1U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000004 */ +#define GPIO_CFGLR_IOFC0_1 (0x2U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000008 */ + +#define GPIO_CFGLR_IOFC1_Pos (6U) +#define GPIO_CFGLR_IOFC1_Msk (0x3U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGLR_IOFC1 GPIO_CFGLR_IOFC1_Msk /*!< IOFC1[1:0] bits (GPIO x function configuration, pin 1) */ +#define GPIO_CFGLR_IOFC1_0 (0x1U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000040 */ +#define GPIO_CFGLR_IOFC1_1 (0x2U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000080 */ + +#define GPIO_CFGLR_IOFC2_Pos (10U) +#define GPIO_CFGLR_IOFC2_Msk (0x3U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGLR_IOFC2 GPIO_CFGLR_IOFC2_Msk /*!< IOFC2[1:0] bits (GPIO x function configuration, pin 2) */ +#define GPIO_CFGLR_IOFC2_0 (0x1U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000400 */ +#define GPIO_CFGLR_IOFC2_1 (0x2U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000800 */ + +#define GPIO_CFGLR_IOFC3_Pos (14U) +#define GPIO_CFGLR_IOFC3_Msk (0x3U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGLR_IOFC3 GPIO_CFGLR_IOFC3_Msk /*!< IOFC3[1:0] bits (GPIO x function configuration, pin 3) */ +#define GPIO_CFGLR_IOFC3_0 (0x1U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00004000 */ +#define GPIO_CFGLR_IOFC3_1 (0x2U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00008000 */ + +#define GPIO_CFGLR_IOFC4_Pos (18U) +#define GPIO_CFGLR_IOFC4_Msk (0x3U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGLR_IOFC4 GPIO_CFGLR_IOFC4_Msk /*!< IOFC4[1:0] bits (GPIO x function configuration, pin 4) */ +#define GPIO_CFGLR_IOFC4_0 (0x1U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00040000 */ +#define GPIO_CFGLR_IOFC4_1 (0x2U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00080000 */ + +#define GPIO_CFGLR_IOFC5_Pos (22U) +#define GPIO_CFGLR_IOFC5_Msk (0x3U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGLR_IOFC5 GPIO_CFGLR_IOFC5_Msk /*!< IOFC5[1:0] bits (GPIO x function configuration, pin 5) */ +#define GPIO_CFGLR_IOFC5_0 (0x1U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00400000 */ +#define GPIO_CFGLR_IOFC5_1 (0x2U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00800000 */ + +#define GPIO_CFGLR_IOFC6_Pos (26U) +#define GPIO_CFGLR_IOFC6_Msk (0x3U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGLR_IOFC6 GPIO_CFGLR_IOFC6_Msk /*!< IOFC6[1:0] bits (GPIO x function configuration, pin 6) */ +#define GPIO_CFGLR_IOFC6_0 (0x1U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x04000000 */ +#define GPIO_CFGLR_IOFC6_1 (0x2U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x08000000 */ + +#define GPIO_CFGLR_IOFC7_Pos (30U) +#define GPIO_CFGLR_IOFC7_Msk (0x3U << GPIO_CFGLR_IOFC7_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGLR_IOFC7 GPIO_CFGLR_IOFC7_Msk /*!< IOFC7[1:0] bits (GPIO x function configuration, pin 7) */ +#define GPIO_CFGLR_IOFC7_0 (0x1U << GPIO_CFGLR_IOFC7_Pos) /*!< 0x40000000 */ +#define GPIO_CFGLR_IOFC7_1 (0x2U << GPIO_CFGLR_IOFC7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_CFGHR register ******************/ +#define GPIO_CFGHR_IOMC_Pos (0U) +#define GPIO_CFGHR_IOMC_Msk (0x33333333U << GPIO_CFGHR_IOMC_Pos) /*!< 0x33333333 */ +#define GPIO_CFGHR_IOMC GPIO_CFGHR_IOMC_Msk /*!< GPIO x mode configuration */ + +#define GPIO_CFGHR_IOMC8_Pos (0U) +#define GPIO_CFGHR_IOMC8_Msk (0x3U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000003 */ +#define GPIO_CFGHR_IOMC8 GPIO_CFGHR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ +#define GPIO_CFGHR_IOMC8_0 (0x1U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000001 */ +#define GPIO_CFGHR_IOMC8_1 (0x2U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000002 */ + +#define GPIO_CFGHR_IOMC9_Pos (4U) +#define GPIO_CFGHR_IOMC9_Msk (0x3U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000030 */ +#define GPIO_CFGHR_IOMC9 GPIO_CFGHR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ +#define GPIO_CFGHR_IOMC9_0 (0x1U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000010 */ +#define GPIO_CFGHR_IOMC9_1 (0x2U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000020 */ + +#define GPIO_CFGHR_IOMC10_Pos (8U) +#define GPIO_CFGHR_IOMC10_Msk (0x3U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000300 */ +#define GPIO_CFGHR_IOMC10 GPIO_CFGHR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ +#define GPIO_CFGHR_IOMC10_0 (0x1U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000100 */ +#define GPIO_CFGHR_IOMC10_1 (0x2U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000200 */ + +#define GPIO_CFGHR_IOMC11_Pos (12U) +#define GPIO_CFGHR_IOMC11_Msk (0x3U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00003000 */ +#define GPIO_CFGHR_IOMC11 GPIO_CFGHR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ +#define GPIO_CFGHR_IOMC11_0 (0x1U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00001000 */ +#define GPIO_CFGHR_IOMC11_1 (0x2U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00002000 */ + +#define GPIO_CFGHR_IOMC12_Pos (16U) +#define GPIO_CFGHR_IOMC12_Msk (0x3U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00030000 */ +#define GPIO_CFGHR_IOMC12 GPIO_CFGHR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ +#define GPIO_CFGHR_IOMC12_0 (0x1U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00010000 */ +#define GPIO_CFGHR_IOMC12_1 (0x2U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00020000 */ + +#define GPIO_CFGHR_IOMC13_Pos (20U) +#define GPIO_CFGHR_IOMC13_Msk (0x3U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00300000 */ +#define GPIO_CFGHR_IOMC13 GPIO_CFGHR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ +#define GPIO_CFGHR_IOMC13_0 (0x1U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00100000 */ +#define GPIO_CFGHR_IOMC13_1 (0x2U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00200000 */ + +#define GPIO_CFGHR_IOMC14_Pos (24U) +#define GPIO_CFGHR_IOMC14_Msk (0x3U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x03000000 */ +#define GPIO_CFGHR_IOMC14 GPIO_CFGHR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ +#define GPIO_CFGHR_IOMC14_0 (0x1U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x01000000 */ +#define GPIO_CFGHR_IOMC14_1 (0x2U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x02000000 */ + +#define GPIO_CFGHR_IOMC15_Pos (28U) +#define GPIO_CFGHR_IOMC15_Msk (0x3U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x30000000 */ +#define GPIO_CFGHR_IOMC15 GPIO_CFGHR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ +#define GPIO_CFGHR_IOMC15_0 (0x1U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x10000000 */ +#define GPIO_CFGHR_IOMC15_1 (0x2U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x20000000 */ + +#define GPIO_CFGHR_IOFC_Pos (2U) +#define GPIO_CFGHR_IOFC_Msk (0x33333333U << GPIO_CFGHR_IOFC_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CFGHR_IOFC GPIO_CFGHR_IOFC_Msk /*!< GPIO x function configuration */ + +#define GPIO_CFGHR_IOFC8_Pos (2U) +#define GPIO_CFGHR_IOFC8_Msk (0x3U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x0000000C */ +#define GPIO_CFGHR_IOFC8 GPIO_CFGHR_IOFC8_Msk /*!< IOFC8[1:0] bits (GPIO x function configuration, pin 8) */ +#define GPIO_CFGHR_IOFC8_0 (0x1U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000004 */ +#define GPIO_CFGHR_IOFC8_1 (0x2U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000008 */ + +#define GPIO_CFGHR_IOFC9_Pos (6U) +#define GPIO_CFGHR_IOFC9_Msk (0x3U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGHR_IOFC9 GPIO_CFGHR_IOFC9_Msk /*!< IOFC9[1:0] bits (GPIO x function configuration, pin 9) */ +#define GPIO_CFGHR_IOFC9_0 (0x1U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000040 */ +#define GPIO_CFGHR_IOFC9_1 (0x2U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000080 */ + +#define GPIO_CFGHR_IOFC10_Pos (10U) +#define GPIO_CFGHR_IOFC10_Msk (0x3U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGHR_IOFC10 GPIO_CFGHR_IOFC10_Msk /*!< IOFC10[1:0] bits (GPIO x function configuration, pin 10) */ +#define GPIO_CFGHR_IOFC10_0 (0x1U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000400 */ +#define GPIO_CFGHR_IOFC10_1 (0x2U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000800 */ + +#define GPIO_CFGHR_IOFC11_Pos (14U) +#define GPIO_CFGHR_IOFC11_Msk (0x3U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGHR_IOFC11 GPIO_CFGHR_IOFC11_Msk /*!< IOFC11[1:0] bits (GPIO x function configuration, pin 11) */ +#define GPIO_CFGHR_IOFC11_0 (0x1U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00004000 */ +#define GPIO_CFGHR_IOFC11_1 (0x2U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00008000 */ + +#define GPIO_CFGHR_IOFC12_Pos (18U) +#define GPIO_CFGHR_IOFC12_Msk (0x3U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGHR_IOFC12 GPIO_CFGHR_IOFC12_Msk /*!< IOFC12[1:0] bits (GPIO x function configuration, pin 12) */ +#define GPIO_CFGHR_IOFC12_0 (0x1U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00040000 */ +#define GPIO_CFGHR_IOFC12_1 (0x2U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00080000 */ + +#define GPIO_CFGHR_IOFC13_Pos (22U) +#define GPIO_CFGHR_IOFC13_Msk (0x3U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGHR_IOFC13 GPIO_CFGHR_IOFC13_Msk /*!< IOFC13[1:0] bits (GPIO x function configuration, pin 13) */ +#define GPIO_CFGHR_IOFC13_0 (0x1U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00400000 */ +#define GPIO_CFGHR_IOFC13_1 (0x2U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00800000 */ + +#define GPIO_CFGHR_IOFC14_Pos (26U) +#define GPIO_CFGHR_IOFC14_Msk (0x3U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGHR_IOFC14 GPIO_CFGHR_IOFC14_Msk /*!< IOFC14[1:0] bits (GPIO x function configuration, pin 14) */ +#define GPIO_CFGHR_IOFC14_0 (0x1U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x04000000 */ +#define GPIO_CFGHR_IOFC14_1 (0x2U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x08000000 */ + +#define GPIO_CFGHR_IOFC15_Pos (30U) +#define GPIO_CFGHR_IOFC15_Msk (0x3U << GPIO_CFGHR_IOFC15_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGHR_IOFC15 GPIO_CFGHR_IOFC15_Msk /*!< IOFC15[1:0] bits (GPIO x function configuration, pin 15) */ +#define GPIO_CFGHR_IOFC15_0 (0x1U << GPIO_CFGHR_IOFC15_Pos) /*!< 0x40000000 */ +#define GPIO_CFGHR_IOFC15_1 (0x2U << GPIO_CFGHR_IOFC15_Pos) /*!< 0x80000000 */ + +/*!<**************** Bit definition for GPIO_IDT register *******************/ +#define GPIO_IDT_IDT0_Pos (0U) +#define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, bit 0 */ +#define GPIO_IDT_IDT1_Pos (1U) +#define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, bit 1 */ +#define GPIO_IDT_IDT2_Pos (2U) +#define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, bit 2 */ +#define GPIO_IDT_IDT3_Pos (3U) +#define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, bit 3 */ +#define GPIO_IDT_IDT4_Pos (4U) +#define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, bit 4 */ +#define GPIO_IDT_IDT5_Pos (5U) +#define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, bit 5 */ +#define GPIO_IDT_IDT6_Pos (6U) +#define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, bit 6 */ +#define GPIO_IDT_IDT7_Pos (7U) +#define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, bit 7 */ +#define GPIO_IDT_IDT8_Pos (8U) +#define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, bit 8 */ +#define GPIO_IDT_IDT9_Pos (9U) +#define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, bit 9 */ +#define GPIO_IDT_IDT10_Pos (10U) +#define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, bit 10 */ +#define GPIO_IDT_IDT11_Pos (11U) +#define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, bit 11 */ +#define GPIO_IDT_IDT12_Pos (12U) +#define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, bit 12 */ +#define GPIO_IDT_IDT13_Pos (13U) +#define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, bit 13 */ +#define GPIO_IDT_IDT14_Pos (14U) +#define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, bit 14 */ +#define GPIO_IDT_IDT15_Pos (15U) +#define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, bit 15 */ + +/******************* Bit definition for GPIO_ODT register *******************/ +#define GPIO_ODT_ODT0_Pos (0U) +#define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, bit 0 */ +#define GPIO_ODT_ODT1_Pos (1U) +#define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, bit 1 */ +#define GPIO_ODT_ODT2_Pos (2U) +#define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, bit 2 */ +#define GPIO_ODT_ODT3_Pos (3U) +#define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, bit 3 */ +#define GPIO_ODT_ODT4_Pos (4U) +#define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, bit 4 */ +#define GPIO_ODT_ODT5_Pos (5U) +#define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, bit 5 */ +#define GPIO_ODT_ODT6_Pos (6U) +#define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, bit 6 */ +#define GPIO_ODT_ODT7_Pos (7U) +#define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, bit 7 */ +#define GPIO_ODT_ODT8_Pos (8U) +#define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, bit 8 */ +#define GPIO_ODT_ODT9_Pos (9U) +#define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, bit 9 */ +#define GPIO_ODT_ODT10_Pos (10U) +#define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, bit 10 */ +#define GPIO_ODT_ODT11_Pos (11U) +#define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, bit 11 */ +#define GPIO_ODT_ODT12_Pos (12U) +#define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, bit 12 */ +#define GPIO_ODT_ODT13_Pos (13U) +#define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, bit 13 */ +#define GPIO_ODT_ODT14_Pos (14U) +#define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, bit 14 */ +#define GPIO_ODT_ODT15_Pos (15U) +#define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, bit 15 */ + +/******************* Bit definition for GPIO_SCR register *******************/ +#define GPIO_SCR_IOSB0_Pos (0U) +#define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit 0 */ +#define GPIO_SCR_IOSB1_Pos (1U) +#define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit 1 */ +#define GPIO_SCR_IOSB2_Pos (2U) +#define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit 2 */ +#define GPIO_SCR_IOSB3_Pos (3U) +#define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit 3 */ +#define GPIO_SCR_IOSB4_Pos (4U) +#define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit 4 */ +#define GPIO_SCR_IOSB5_Pos (5U) +#define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit 5 */ +#define GPIO_SCR_IOSB6_Pos (6U) +#define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit 6 */ +#define GPIO_SCR_IOSB7_Pos (7U) +#define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit 7 */ +#define GPIO_SCR_IOSB8_Pos (8U) +#define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit 8 */ +#define GPIO_SCR_IOSB9_Pos (9U) +#define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit 9 */ +#define GPIO_SCR_IOSB10_Pos (10U) +#define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit 10 */ +#define GPIO_SCR_IOSB11_Pos (11U) +#define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit 11 */ +#define GPIO_SCR_IOSB12_Pos (12U) +#define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit 12 */ +#define GPIO_SCR_IOSB13_Pos (13U) +#define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit 13 */ +#define GPIO_SCR_IOSB14_Pos (14U) +#define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit 14 */ +#define GPIO_SCR_IOSB15_Pos (15U) +#define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit 15 */ +#define GPIO_SCR_IOCB0_Pos (16U) +#define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_SCR_IOCB1_Pos (17U) +#define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_SCR_IOCB2_Pos (18U) +#define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_SCR_IOCB3_Pos (19U) +#define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_SCR_IOCB4_Pos (20U) +#define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_SCR_IOCB5_Pos (21U) +#define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_SCR_IOCB6_Pos (22U) +#define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_SCR_IOCB7_Pos (23U) +#define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_SCR_IOCB8_Pos (24U) +#define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_SCR_IOCB9_Pos (25U) +#define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_SCR_IOCB10_Pos (26U) +#define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_SCR_IOCB11_Pos (27U) +#define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_SCR_IOCB12_Pos (28U) +#define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_SCR_IOCB13_Pos (29U) +#define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_SCR_IOCB14_Pos (30U) +#define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_SCR_IOCB15_Pos (31U) +#define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit 15 */ + +/******************* Bit definition for GPIO_CLR register *******************/ +#define GPIO_CLR_IOCB0_Pos (0U) +#define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_CLR_IOCB1_Pos (1U) +#define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_CLR_IOCB2_Pos (2U) +#define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_CLR_IOCB3_Pos (3U) +#define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_CLR_IOCB4_Pos (4U) +#define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_CLR_IOCB5_Pos (5U) +#define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_CLR_IOCB6_Pos (6U) +#define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_CLR_IOCB7_Pos (7U) +#define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_CLR_IOCB8_Pos (8U) +#define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_CLR_IOCB9_Pos (9U) +#define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_CLR_IOCB10_Pos (10U) +#define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_CLR_IOCB11_Pos (11U) +#define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_CLR_IOCB12_Pos (12U) +#define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_CLR_IOCB13_Pos (13U) +#define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_CLR_IOCB14_Pos (14U) +#define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_CLR_IOCB15_Pos (15U) +#define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit 15 */ + +/******************* Bit definition for GPIO_WPR register *******************/ +#define GPIO_WPR_WPEN0_Pos (0U) +#define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable bit 0 */ +#define GPIO_WPR_WPEN1_Pos (1U) +#define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable bit 1 */ +#define GPIO_WPR_WPEN2_Pos (2U) +#define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable bit 2 */ +#define GPIO_WPR_WPEN3_Pos (3U) +#define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable bit 3 */ +#define GPIO_WPR_WPEN4_Pos (4U) +#define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable bit 4 */ +#define GPIO_WPR_WPEN5_Pos (5U) +#define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable bit 5 */ +#define GPIO_WPR_WPEN6_Pos (6U) +#define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable bit 6 */ +#define GPIO_WPR_WPEN7_Pos (7U) +#define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable bit 7 */ +#define GPIO_WPR_WPEN8_Pos (8U) +#define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable bit 8 */ +#define GPIO_WPR_WPEN9_Pos (9U) +#define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable bit 9 */ +#define GPIO_WPR_WPEN10_Pos (10U) +#define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable bit 10 */ +#define GPIO_WPR_WPEN11_Pos (11U) +#define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable bit 11 */ +#define GPIO_WPR_WPEN12_Pos (12U) +#define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable bit 12 */ +#define GPIO_WPR_WPEN13_Pos (13U) +#define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable bit 13 */ +#define GPIO_WPR_WPEN14_Pos (14U) +#define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable bit 14 */ +#define GPIO_WPR_WPEN15_Pos (15U) +#define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable bit 15 */ +#define GPIO_WPR_WPSEQ_Pos (16U) +#define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ +#define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ + +/******************************************************************************/ +/* */ +/* Multiplex function I/Os (IOMUX) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for IOMUX_EVTOUT register *****************/ +/*!< SELPIN configuration */ +#define IOMUX_EVTOUT_SELPIN_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_Msk (0xFU << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x0000000F */ +#define IOMUX_EVTOUT_SELPIN IOMUX_EVTOUT_SELPIN_Msk /*!< SELPIN[3:0] bits (Selection IO pin) */ +#define IOMUX_EVTOUT_SELPIN_0 (0x1U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000001 */ +#define IOMUX_EVTOUT_SELPIN_1 (0x2U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000002 */ +#define IOMUX_EVTOUT_SELPIN_2 (0x4U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000004 */ +#define IOMUX_EVTOUT_SELPIN_3 (0x8U << IOMUX_EVTOUT_SELPIN_Pos) /*!< 0x00000008 */ + +#define IOMUX_EVTOUT_SELPIN_PIN0 0x00000000U /*!< Pin 0 */ +#define IOMUX_EVTOUT_SELPIN_PIN1_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN1_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN1_Pos) /*!< 0x00000001 */ +#define IOMUX_EVTOUT_SELPIN_PIN1 IOMUX_EVTOUT_SELPIN_PIN1_Msk /*!< Pin 1 */ +#define IOMUX_EVTOUT_SELPIN_PIN2_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN2_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN2_Pos) /*!< 0x00000002 */ +#define IOMUX_EVTOUT_SELPIN_PIN2 IOMUX_EVTOUT_SELPIN_PIN2_Msk /*!< Pin 2 */ +#define IOMUX_EVTOUT_SELPIN_PIN3_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN3_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN3_Pos) /*!< 0x00000003 */ +#define IOMUX_EVTOUT_SELPIN_PIN3 IOMUX_EVTOUT_SELPIN_PIN3_Msk /*!< Pin 3 */ +#define IOMUX_EVTOUT_SELPIN_PIN4_Pos (2U) +#define IOMUX_EVTOUT_SELPIN_PIN4_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN4_Pos) /*!< 0x00000004 */ +#define IOMUX_EVTOUT_SELPIN_PIN4 IOMUX_EVTOUT_SELPIN_PIN4_Msk /*!< Pin 4 */ +#define IOMUX_EVTOUT_SELPIN_PIN5_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN5_Msk (0x5U << IOMUX_EVTOUT_SELPIN_PIN5_Pos) /*!< 0x00000005 */ +#define IOMUX_EVTOUT_SELPIN_PIN5 IOMUX_EVTOUT_SELPIN_PIN5_Msk /*!< Pin 5 */ +#define IOMUX_EVTOUT_SELPIN_PIN6_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN6_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN6_Pos) /*!< 0x00000006 */ +#define IOMUX_EVTOUT_SELPIN_PIN6 IOMUX_EVTOUT_SELPIN_PIN6_Msk /*!< Pin 6 */ +#define IOMUX_EVTOUT_SELPIN_PIN7_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN7_Msk (0x7U << IOMUX_EVTOUT_SELPIN_PIN7_Pos) /*!< 0x00000007 */ +#define IOMUX_EVTOUT_SELPIN_PIN7 IOMUX_EVTOUT_SELPIN_PIN7_Msk /*!< Pin 7 */ +#define IOMUX_EVTOUT_SELPIN_PIN8_Pos (3U) +#define IOMUX_EVTOUT_SELPIN_PIN8_Msk (0x1U << IOMUX_EVTOUT_SELPIN_PIN8_Pos) /*!< 0x00000008 */ +#define IOMUX_EVTOUT_SELPIN_PIN8 IOMUX_EVTOUT_SELPIN_PIN8_Msk /*!< Pin 8 */ +#define IOMUX_EVTOUT_SELPIN_PIN9_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN9_Msk (0x9U << IOMUX_EVTOUT_SELPIN_PIN9_Pos) /*!< 0x00000009 */ +#define IOMUX_EVTOUT_SELPIN_PIN9 IOMUX_EVTOUT_SELPIN_PIN9_Msk /*!< Pin 9 */ +#define IOMUX_EVTOUT_SELPIN_PIN10_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN10_Msk (0x5U << IOMUX_EVTOUT_SELPIN_PIN10_Pos) /*!< 0x0000000A */ +#define IOMUX_EVTOUT_SELPIN_PIN10 IOMUX_EVTOUT_SELPIN_PIN10_Msk /*!< Pin 10 */ +#define IOMUX_EVTOUT_SELPIN_PIN11_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN11_Msk (0xBU << IOMUX_EVTOUT_SELPIN_PIN11_Pos) /*!< 0x0000000B */ +#define IOMUX_EVTOUT_SELPIN_PIN11 IOMUX_EVTOUT_SELPIN_PIN11_Msk /*!< Pin 11 */ +#define IOMUX_EVTOUT_SELPIN_PIN12_Pos (2U) +#define IOMUX_EVTOUT_SELPIN_PIN12_Msk (0x3U << IOMUX_EVTOUT_SELPIN_PIN12_Pos) /*!< 0x0000000C */ +#define IOMUX_EVTOUT_SELPIN_PIN12 IOMUX_EVTOUT_SELPIN_PIN12_Msk /*!< Pin 12 */ +#define IOMUX_EVTOUT_SELPIN_PIN13_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN13_Msk (0xDU << IOMUX_EVTOUT_SELPIN_PIN13_Pos) /*!< 0x0000000D */ +#define IOMUX_EVTOUT_SELPIN_PIN13 IOMUX_EVTOUT_SELPIN_PIN13_Msk /*!< Pin 13 */ +#define IOMUX_EVTOUT_SELPIN_PIN14_Pos (1U) +#define IOMUX_EVTOUT_SELPIN_PIN14_Msk (0x7U << IOMUX_EVTOUT_SELPIN_PIN14_Pos) /*!< 0x0000000E */ +#define IOMUX_EVTOUT_SELPIN_PIN14 IOMUX_EVTOUT_SELPIN_PIN14_Msk /*!< Pin 14 */ +#define IOMUX_EVTOUT_SELPIN_PIN15_Pos (0U) +#define IOMUX_EVTOUT_SELPIN_PIN15_Msk (0xFU << IOMUX_EVTOUT_SELPIN_PIN15_Pos) /*!< 0x0000000F */ +#define IOMUX_EVTOUT_SELPIN_PIN15 IOMUX_EVTOUT_SELPIN_PIN15_Msk /*!< Pin 15 */ + +/*!< SELPORT configuration */ +#define IOMUX_EVTOUT_SELPORT_Pos (4U) +#define IOMUX_EVTOUT_SELPORT_Msk (0x7U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000070 */ +#define IOMUX_EVTOUT_SELPORT IOMUX_EVTOUT_SELPORT_Msk /*!< SELPORT[2:0] bits (Selection IO port) */ +#define IOMUX_EVTOUT_SELPORT_0 (0x1U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000010 */ +#define IOMUX_EVTOUT_SELPORT_1 (0x2U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000020 */ +#define IOMUX_EVTOUT_SELPORT_2 (0x4U << IOMUX_EVTOUT_SELPORT_Pos) /*!< 0x00000040 */ + +#define IOMUX_EVTOUT_SELPORT_GPIOA 0x00000000 /*!< GPIOA */ +#define IOMUX_EVTOUT_SELPORT_GPIOB_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_EVTOUT_SELPORT_GPIOB_Msk (0x1U << IOMUX_EVTOUT_SELPORT_GPIOB_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOB IOMUX_EVTOUT_SELPORT_GPIOB_Msk /*!< GPIOB */ +#define IOMUX_EVTOUT_SELPORT_GPIOC_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_EVTOUT_SELPORT_GPIOC_Msk (0x1U << IOMUX_EVTOUT_SELPORT_GPIOC_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOC IOMUX_EVTOUT_SELPORT_GPIOC_Msk /*!< GPIOC */ +#define IOMUX_EVTOUT_SELPORT_GPIOD_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_EVTOUT_SELPORT_GPIOD_Msk (0x3U << IOMUX_EVTOUT_SELPORT_GPIOD_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOD IOMUX_EVTOUT_SELPORT_GPIOD_Msk /*!< GPIOD */ +#define IOMUX_EVTOUT_SELPORT_GPIOF_Pos (4U) /*!< 0x00000050 */ +#define IOMUX_EVTOUT_SELPORT_GPIOF_Msk (0x5U << IOMUX_EVTOUT_SELPORT_GPIOF_Pos) +#define IOMUX_EVTOUT_SELPORT_GPIOF IOMUX_EVTOUT_SELPORT_GPIOF_Msk /*!< GPIOF */ + +#define IOMUX_EVTOUT_EVOEN_Pos (7U) +#define IOMUX_EVTOUT_EVOEN_Msk (0x1U << IOMUX_EVTOUT_EVOEN_Pos) /*!< 0x00000080 */ +#define IOMUX_EVTOUT_EVOEN IOMUX_EVTOUT_EVOEN_Msk /*!< Event output enable */ + +/***************** Bit definition for IOMUX_REMAP register ******************/ +/*!< SPI1_MUX configuration */ +#define IOMUX_REMAP_SPI1_MUX_Pos (0U) +#define IOMUX_REMAP_SPI1_MUX_Msk (0x1U << IOMUX_REMAP_SPI1_MUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP_SPI1_MUX IOMUX_REMAP_SPI1_MUX_Msk /*!< SPI1 IO multiplexing */ +#define IOMUX_REMAP_I2C1_MUX_Pos (1U) +#define IOMUX_REMAP_I2C1_MUX_Msk (0x1U << IOMUX_REMAP_I2C1_MUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP_I2C1_MUX IOMUX_REMAP_I2C1_MUX_Msk /*!< I2C1 IO multiplexing */ +#define IOMUX_REMAP_USART1_MUX_Pos (2U) +#define IOMUX_REMAP_USART1_MUX_Msk (0x1U << IOMUX_REMAP_USART1_MUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP_USART1_MUX IOMUX_REMAP_USART1_MUX_Msk /*!< USART1 IO multiplexing */ + +/*!< USART3_MUX configuration */ +#define IOMUX_REMAP_USART3_MUX_Pos (4U) +#define IOMUX_REMAP_USART3_MUX_Msk (0x3U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000030 */ +#define IOMUX_REMAP_USART3_MUX IOMUX_REMAP_USART3_MUX_Msk /*!< USART3_MUX[1:0] bits (USART3 IO multiplexing) */ +#define IOMUX_REMAP_USART3_MUX_0 (0x1U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_1 (0x2U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000020 */ + +#define IOMUX_REMAP_USART3_MUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX1_Pos) +#define IOMUX_REMAP_USART3_MUX_MUX1 IOMUX_REMAP_USART3_MUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP_USART3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX2_Pos) +#define IOMUX_REMAP_USART3_MUX_MUX2 IOMUX_REMAP_USART3_MUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ + +/*!< TMR1_MUX configuration */ +#define IOMUX_REMAP_TMR1_MUX_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_Msk (0x3U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x000000C0 */ +#define IOMUX_REMAP_TMR1_MUX IOMUX_REMAP_TMR1_MUX_Msk /*!< TMR1_MUX[1:0] bits (TMR1 IO multiplexing) */ +#define IOMUX_REMAP_TMR1_MUX_0 (0x1U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_1 (0x2U << IOMUX_REMAP_TMR1_MUX_Pos /*!< 0x00000080 */ + +#define IOMUX_REMAP_TMR1_MUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX1_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1 IOMUX_REMAP_TMR1_MUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ + +/*!< TMR2_MUX configuration */ +#define IOMUX_REMAP_TMR2_MUX_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX IOMUX_REMAP_TMR2_MUX_Msk /*!< TMR2_MUX[1:0] bits (TMR2 IO multiplexing) */ +#define IOMUX_REMAP_TMR2_MUX_0 (0x1U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_1 (0x2U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000200 */ + +#define IOMUX_REMAP_TMR2_MUX_MUX0 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX1_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1 IOMUX_REMAP_TMR2_MUX_MUX1_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (9U) +#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ + +/*!< TMR3_MUX configuration */ +#define IOMUX_REMAP_TMR3_MUX_Pos (10U) +#define IOMUX_REMAP_TMR3_MUX_Msk (0x3U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000C00 */ +#define IOMUX_REMAP_TMR3_MUX IOMUX_REMAP_TMR3_MUX_Msk /*!< TMR3_MUX[1:0] bits (TMR3 IO multiplexing) */ +#define IOMUX_REMAP_TMR3_MUX_0 (0x1U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP_TMR3_MUX_1 (0x2U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP_TMR3_MUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX2_Pos (11U) +#define IOMUX_REMAP_TMR3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR3_MUX_MUX2_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP_TMR3_MUX_MUX2 IOMUX_REMAP_TMR3_MUX_MUX2_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX3_Pos (10U) +#define IOMUX_REMAP_TMR3_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR3_MUX_MUX3_Pos) /*!< 0x00000C00 */ +#define IOMUX_REMAP_TMR3_MUX_MUX3 IOMUX_REMAP_TMR3_MUX_MUX3_Msk /*!< CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9 */ + +/*!< CAN1_MUX configuration */ +#define IOMUX_REMAP_CAN1_MUX_Pos (13U) +#define IOMUX_REMAP_CAN1_MUX_Msk (0x3U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00006000 */ +#define IOMUX_REMAP_CAN1_MUX IOMUX_REMAP_CAN1_MUX_Msk /*!< CAN1_MUX[1:0] bits (CAN1 IO multiplexing) */ +#define IOMUX_REMAP_CAN1_MUX_0 (0x1U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00002000 */ +#define IOMUX_REMAP_CAN1_MUX_1 (0x2U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00004000 */ + +#define IOMUX_REMAP_CAN1_MUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP_CAN1_MUX_MUX2_Pos (14U) +#define IOMUX_REMAP_CAN1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_CAN1_MUX_MUX2_Pos) /*!< 0x00004000 */ +#define IOMUX_REMAP_CAN1_MUX_MUX2 IOMUX_REMAP_CAN1_MUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + +#define IOMUX_REMAP_PD01_MUX_Pos (15U) +#define IOMUX_REMAP_PD01_MUX_Msk (0x1U << IOMUX_REMAP_PD01_MUX_Pos) /*!< 0x00008000 */ +#define IOMUX_REMAP_PD01_MUX IOMUX_REMAP_PD01_MUX_Msk /*!< PD0/PD1 mapped on HEXT_IN/HEXT_OUT */ +#define IOMUX_REMAP_TMR5CH4_MUX_Pos (16U) +#define IOMUX_REMAP_TMR5CH4_MUX_Msk (0x1U << IOMUX_REMAP_TMR5CH4_MUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP_TMR5CH4_MUX IOMUX_REMAP_TMR5CH4_MUX_Msk /*!< TMR5 channel 4 multiplexing */ +#define IOMUX_REMAP_ADC1_ETP_MUX_Pos (17U) +#define IOMUX_REMAP_ADC1_ETP_MUX_Msk (0x1U << IOMUX_REMAP_ADC1_ETP_MUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP_ADC1_ETP_MUX IOMUX_REMAP_ADC1_ETP_MUX_Msk /*!< ADC1 external trigger preempted conversion multiplexing */ +#define IOMUX_REMAP_ADC1_ETO_MUX_Pos (18U) +#define IOMUX_REMAP_ADC1_ETO_MUX_Msk (0x1U << IOMUX_REMAP_ADC1_ETO_MUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP_ADC1_ETO_MUX IOMUX_REMAP_ADC1_ETO_MUX_Msk /*!< ADC1 external trigger regular conversion mutiplexing */ + +/*!< SWJTAG_MUX configuration */ +#define IOMUX_REMAP_SWJTAG_MUX_Pos (24U) +#define IOMUX_REMAP_SWJTAG_MUX_Msk (0x7U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x07000000 */ +#define IOMUX_REMAP_SWJTAG_MUX IOMUX_REMAP_SWJTAG_MUX_Msk /*!< SWJTAG_MUX[2:0] bits (SWD JTAG mutiplexing) */ +#define IOMUX_REMAP_SWJTAG_MUX_0 (0x1U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x01000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_1 (0x2U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x02000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_2 (0x4U << IOMUX_REMAP_SWJTAG_MUX_Pos) /*!< 0x04000000 */ + +#define IOMUX_REMAP_SWJTAG_MUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIOs */ +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_NONJTRST IOMUX_REMAP_SWJTAG_MUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Pos (25U) /*!< 0x02000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_JTAGDIS IOMUX_REMAP_SWJTAG_MUX_JTAGDIS_Msk /*!< Supports SWD but JTAG is disabled. PA15/PB3/PB4 can be used as GPIOs */ +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE_Pos (26U) /*!< 0x04000000 */ +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE_Msk (0x1U << IOMUX_REMAP_SWJTAG_MUX_DISABLE_Pos) +#define IOMUX_REMAP_SWJTAG_MUX_DISABLE IOMUX_REMAP_SWJTAG_MUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIOs */ + +/**************** Bit definition for IOMUX_EXINTC1 register *****************/ +/*!< EXINT0 configuration */ +#define IOMUX_EXINTC1_EXINT0_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_Msk (0xFU << IOMUX_EXINTC1_EXINT0_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC1_EXINT0 IOMUX_EXINTC1_EXINT0_Msk /*!< EXINT0[3:0] bits (EXINT0 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT0_GPA 0x00000000U /*!< GPIOA pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPB_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC1_EXINT0_GPB IOMUX_EXINTC1_EXINT0_GPB_Msk /*!< GPIOB pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPC_Pos (1U) +#define IOMUX_EXINTC1_EXINT0_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC1_EXINT0_GPC IOMUX_EXINTC1_EXINT0_GPC_Msk /*!< GPIOC pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPD_Pos (0U) +#define IOMUX_EXINTC1_EXINT0_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT0_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC1_EXINT0_GPD IOMUX_EXINTC1_EXINT0_GPD_Msk /*!< GPIOD pin 0 */ +#define IOMUX_EXINTC1_EXINT0_GPF_Pos (2U) +#define IOMUX_EXINTC1_EXINT0_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT0_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC1_EXINT0_GPF IOMUX_EXINTC1_EXINT0_GPF_Msk /*!< GPIOF pin 0 */ + +/*!< EXINT1 configuration */ +#define IOMUX_EXINTC1_EXINT1_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_Msk (0xFU << IOMUX_EXINTC1_EXINT1_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC1_EXINT1 IOMUX_EXINTC1_EXINT1_Msk /*!< EXINT1[3:0] bits (EXINT1 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT1_GPA 0x00000000U /*!< GPIOA pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPB_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC1_EXINT1_GPB IOMUX_EXINTC1_EXINT1_GPB_Msk /*!< GPIOB pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPC_Pos (5U) +#define IOMUX_EXINTC1_EXINT1_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC1_EXINT1_GPC IOMUX_EXINTC1_EXINT1_GPC_Msk /*!< GPIOC pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPD_Pos (4U) +#define IOMUX_EXINTC1_EXINT1_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT1_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC1_EXINT1_GPD IOMUX_EXINTC1_EXINT1_GPD_Msk /*!< GPIOD pin 1 */ +#define IOMUX_EXINTC1_EXINT1_GPF_Pos (6U) +#define IOMUX_EXINTC1_EXINT1_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT1_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC1_EXINT1_GPF IOMUX_EXINTC1_EXINT1_GPF_Msk /*!< GPIOF pin 1 */ + +/*!< EXINT2 configuration */ +#define IOMUX_EXINTC1_EXINT2_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_Msk (0xFU << IOMUX_EXINTC1_EXINT2_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC1_EXINT2 IOMUX_EXINTC1_EXINT2_Msk /*!< EXINT2[3:0] bits (EXINT2 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT2_GPA 0x00000000U /*!< GPIOA pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPB_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC1_EXINT2_GPB IOMUX_EXINTC1_EXINT2_GPB_Msk /*!< GPIOB pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPC_Pos (9U) +#define IOMUX_EXINTC1_EXINT2_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC1_EXINT2_GPC IOMUX_EXINTC1_EXINT2_GPC_Msk /*!< GPIOC pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPD_Pos (8U) +#define IOMUX_EXINTC1_EXINT2_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT2_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC1_EXINT2_GPD IOMUX_EXINTC1_EXINT2_GPD_Msk /*!< GPIOD pin 2 */ +#define IOMUX_EXINTC1_EXINT2_GPF_Pos (10U) +#define IOMUX_EXINTC1_EXINT2_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT2_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC1_EXINT2_GPF IOMUX_EXINTC1_EXINT2_GPF_Msk /*!< GPIOF pin 2 */ + +/*!< EXINT3 configuration */ +#define IOMUX_EXINTC1_EXINT3_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_Msk (0xFU << IOMUX_EXINTC1_EXINT3_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC1_EXINT3 IOMUX_EXINTC1_EXINT3_Msk /*!< EXINT3[3:0] bits (EXINT3 input source configuration) */ + +#define IOMUX_EXINTC1_EXINT3_GPA 0x00000000U /*!< GPIOA pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPB_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_GPB_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC1_EXINT3_GPB IOMUX_EXINTC1_EXINT3_GPB_Msk /*!< GPIOB pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPC_Pos (13U) +#define IOMUX_EXINTC1_EXINT3_GPC_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC1_EXINT3_GPC IOMUX_EXINTC1_EXINT3_GPC_Msk /*!< GPIOC pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPD_Pos (12U) +#define IOMUX_EXINTC1_EXINT3_GPD_Msk (0x3U << IOMUX_EXINTC1_EXINT3_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC1_EXINT3_GPD IOMUX_EXINTC1_EXINT3_GPD_Msk /*!< GPIOD pin 3 */ +#define IOMUX_EXINTC1_EXINT3_GPF_Pos (14U) +#define IOMUX_EXINTC1_EXINT3_GPF_Msk (0x1U << IOMUX_EXINTC1_EXINT3_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC1_EXINT3_GPF IOMUX_EXINTC1_EXINT3_GPF_Msk /*!< GPIOF pin 3 */ + +/**************** Bit definition for IOMUX_EXINTC2 register *****************/ +/*!< EXINT4 configuration */ +#define IOMUX_EXINTC2_EXINT4_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_Msk (0xFU << IOMUX_EXINTC2_EXINT4_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC2_EXINT4 IOMUX_EXINTC2_EXINT4_Msk /*!< EXINT4[3:0] bits (EXINT4 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT4_GPA 0x00000000U /*!< GPIOA pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPB_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC2_EXINT4_GPB IOMUX_EXINTC2_EXINT4_GPB_Msk /*!< GPIOB pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPC_Pos (1U) +#define IOMUX_EXINTC2_EXINT4_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC2_EXINT4_GPC IOMUX_EXINTC2_EXINT4_GPC_Msk /*!< GPIOC pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPD_Pos (0U) +#define IOMUX_EXINTC2_EXINT4_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT4_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC2_EXINT4_GPD IOMUX_EXINTC2_EXINT4_GPD_Msk /*!< GPIOD pin 4 */ +#define IOMUX_EXINTC2_EXINT4_GPF_Pos (2U) +#define IOMUX_EXINTC2_EXINT4_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT4_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC2_EXINT4_GPF IOMUX_EXINTC2_EXINT4_GPF_Msk /*!< GPIOF pin 4 */ + +/* EXINT5 configuration */ +#define IOMUX_EXINTC2_EXINT5_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_Msk (0xFU << IOMUX_EXINTC2_EXINT5_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC2_EXINT5 IOMUX_EXINTC2_EXINT5_Msk /*!< EXINT5[3:0] bits (EXINT5 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT5_GPA 0x00000000U /*!< GPIOA pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPB_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC2_EXINT5_GPB IOMUX_EXINTC2_EXINT5_GPB_Msk /*!< GPIOB pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPC_Pos (5U) +#define IOMUX_EXINTC2_EXINT5_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC2_EXINT5_GPC IOMUX_EXINTC2_EXINT5_GPC_Msk /*!< GPIOC pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPD_Pos (4U) +#define IOMUX_EXINTC2_EXINT5_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT5_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC2_EXINT5_GPD IOMUX_EXINTC2_EXINT5_GPD_Msk /*!< GPIOD pin 5 */ +#define IOMUX_EXINTC2_EXINT5_GPF_Pos (6U) +#define IOMUX_EXINTC2_EXINT5_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT5_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC2_EXINT5_GPF IOMUX_EXINTC2_EXINT5_GPF_Msk /*!< GPIOF pin 5 */ + +/*!< EXINT6 configuration */ +#define IOMUX_EXINTC2_EXINT6_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_Msk (0xFU << IOMUX_EXINTC2_EXINT6_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC2_EXINT6 IOMUX_EXINTC2_EXINT6_Msk /*!< EXINT6[3:0] bits (EXINT6 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT6_GPA 0x00000000U /*!< GPIOA pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPB_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC2_EXINT6_GPB IOMUX_EXINTC2_EXINT6_GPB_Msk /*!< GPIOB pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPC_Pos (9U) +#define IOMUX_EXINTC2_EXINT6_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC2_EXINT6_GPC IOMUX_EXINTC2_EXINT6_GPC_Msk /*!< GPIOC pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPD_Pos (8U) +#define IOMUX_EXINTC2_EXINT6_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT6_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC2_EXINT6_GPD IOMUX_EXINTC2_EXINT6_GPD_Msk /*!< GPIOD pin 6 */ +#define IOMUX_EXINTC2_EXINT6_GPF_Pos (10U) +#define IOMUX_EXINTC2_EXINT6_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT6_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC2_EXINT6_GPF IOMUX_EXINTC2_EXINT6_GPF_Msk /*!< GPIOF pin 6 */ + +/*!< EXINT7 configuration */ +#define IOMUX_EXINTC2_EXINT7_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_Msk (0xFU << IOMUX_EXINTC2_EXINT7_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC2_EXINT7 IOMUX_EXINTC2_EXINT7_Msk /*!< EXINT7[3:0] bits (EXINT7 input source configuration) */ + +#define IOMUX_EXINTC2_EXINT7_GPA 0x00000000U /*!< GPIOA pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPB_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_GPB_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC2_EXINT7_GPB IOMUX_EXINTC2_EXINT7_GPB_Msk /*!< GPIOB pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPC_Pos (13U) +#define IOMUX_EXINTC2_EXINT7_GPC_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC2_EXINT7_GPC IOMUX_EXINTC2_EXINT7_GPC_Msk /*!< GPIOC pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPD_Pos (12U) +#define IOMUX_EXINTC2_EXINT7_GPD_Msk (0x3U << IOMUX_EXINTC2_EXINT7_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC2_EXINT7_GPD IOMUX_EXINTC2_EXINT7_GPD_Msk /*!< GPIOD pin 7 */ +#define IOMUX_EXINTC2_EXINT7_GPF_Pos (14U) +#define IOMUX_EXINTC2_EXINT7_GPF_Msk (0x1U << IOMUX_EXINTC2_EXINT7_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC2_EXINT7_GPF IOMUX_EXINTC2_EXINT7_GPF_Msk /*!< GPIOF pin 7 */ + +/**************** Bit definition for IOMUX_EXINTC3 register *****************/ +/*!< EXINT8 configuration */ +#define IOMUX_EXINTC3_EXINT8_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_Msk (0xFU << IOMUX_EXINTC3_EXINT8_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC3_EXINT8 IOMUX_EXINTC3_EXINT8_Msk /*!< EXINT8[3:0] bits (EXINT8 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT8_GPA 0x00000000U /*!< GPIOA pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPB_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC3_EXINT8_GPB IOMUX_EXINTC3_EXINT8_GPB_Msk /*!< GPIOB pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPC_Pos (1U) +#define IOMUX_EXINTC3_EXINT8_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC3_EXINT8_GPC IOMUX_EXINTC3_EXINT8_GPC_Msk /*!< GPIOC pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPD_Pos (0U) +#define IOMUX_EXINTC3_EXINT8_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT8_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC3_EXINT8_GPD IOMUX_EXINTC3_EXINT8_GPD_Msk /*!< GPIOD pin 8 */ +#define IOMUX_EXINTC3_EXINT8_GPF_Pos (2U) +#define IOMUX_EXINTC3_EXINT8_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT8_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC3_EXINT8_GPF IOMUX_EXINTC3_EXINT8_GPF_Msk /*!< GPIOF pin 8 */ + +/*!< EXINT9 configuration */ +#define IOMUX_EXINTC3_EXINT9_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_Msk (0xFU << IOMUX_EXINTC3_EXINT9_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC3_EXINT9 IOMUX_EXINTC3_EXINT9_Msk /*!< EXINT9[3:0] bits (EXINT9 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT9_GPA 0x00000000U /*!< GPIOA pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPB_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC3_EXINT9_GPB IOMUX_EXINTC3_EXINT9_GPB_Msk /*!< GPIOB pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPC_Pos (5U) +#define IOMUX_EXINTC3_EXINT9_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC3_EXINT9_GPC IOMUX_EXINTC3_EXINT9_GPC_Msk /*!< GPIOC pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPD_Pos (4U) +#define IOMUX_EXINTC3_EXINT9_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT9_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC3_EXINT9_GPD IOMUX_EXINTC3_EXINT9_GPD_Msk /*!< GPIOD pin 9 */ +#define IOMUX_EXINTC3_EXINT9_GPF_Pos (6U) +#define IOMUX_EXINTC3_EXINT9_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT9_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC3_EXINT9_GPF IOMUX_EXINTC3_EXINT9_GPF_Msk /*!< GPIOF pin 9 */ + +/*!< EXINT10 configuration */ +#define IOMUX_EXINTC3_EXINT10_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_Msk (0xFU << IOMUX_EXINTC3_EXINT10_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC3_EXINT10 IOMUX_EXINTC3_EXINT10_Msk /*!< EXINT10[3:0] bits (EXINT10 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT10_GPA 0x00000000U /*!< GPIOA pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPB_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC3_EXINT10_GPB IOMUX_EXINTC3_EXINT10_GPB_Msk /*!< GPIOB pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPC_Pos (9U) +#define IOMUX_EXINTC3_EXINT10_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC3_EXINT10_GPC IOMUX_EXINTC3_EXINT10_GPC_Msk /*!< GPIOC pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPD_Pos (8U) +#define IOMUX_EXINTC3_EXINT10_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT10_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC3_EXINT10_GPD IOMUX_EXINTC3_EXINT10_GPD_Msk /*!< GPIOD pin 10 */ +#define IOMUX_EXINTC3_EXINT10_GPF_Pos (10U) +#define IOMUX_EXINTC3_EXINT10_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT10_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC3_EXINT10_GPF IOMUX_EXINTC3_EXINT10_GPF_Msk /*!< GPIOF pin 10 */ + +/*!< EXINT11 configuration */ +#define IOMUX_EXINTC3_EXINT11_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_Msk (0xFU << IOMUX_EXINTC3_EXINT11_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC3_EXINT11 IOMUX_EXINTC3_EXINT11_Msk /*!< EXINT11[3:0] bits (EXINT11 input source configuration) */ + +#define IOMUX_EXINTC3_EXINT11_GPA 0x00000000U /*!< GPIOA pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPB_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_GPB_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC3_EXINT11_GPB IOMUX_EXINTC3_EXINT11_GPB_Msk /*!< GPIOB pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPC_Pos (13U) +#define IOMUX_EXINTC3_EXINT11_GPC_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC3_EXINT11_GPC IOMUX_EXINTC3_EXINT11_GPC_Msk /*!< GPIOC pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPD_Pos (12U) +#define IOMUX_EXINTC3_EXINT11_GPD_Msk (0x3U << IOMUX_EXINTC3_EXINT11_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC3_EXINT11_GPD IOMUX_EXINTC3_EXINT11_GPD_Msk /*!< GPIOD pin 11 */ +#define IOMUX_EXINTC3_EXINT11_GPF_Pos (14U) +#define IOMUX_EXINTC3_EXINT11_GPF_Msk (0x1U << IOMUX_EXINTC3_EXINT11_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC3_EXINT11_GPF IOMUX_EXINTC3_EXINT11_GPF_Msk /*!< GPIOF pin 11 */ + +/**************** Bit definition for IOMUX_EXINTC4 register *****************/ +/* EXINT12 configuration */ +#define IOMUX_EXINTC4_EXINT12_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_Msk (0xFU << IOMUX_EXINTC4_EXINT12_Pos) /*!< 0x0000000F */ +#define IOMUX_EXINTC4_EXINT12 IOMUX_EXINTC4_EXINT12_Msk /*!< EXINT12[3:0] bits (EXINT12 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT12_GPA 0x00000000U /*!< GPIOA pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPB_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPB_Pos) /*!< 0x00000001 */ +#define IOMUX_EXINTC4_EXINT12_GPB IOMUX_EXINTC4_EXINT12_GPB_Msk /*!< GPIOB pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPC_Pos (1U) +#define IOMUX_EXINTC4_EXINT12_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPC_Pos) /*!< 0x00000002 */ +#define IOMUX_EXINTC4_EXINT12_GPC IOMUX_EXINTC4_EXINT12_GPC_Msk /*!< GPIOC pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPD_Pos (0U) +#define IOMUX_EXINTC4_EXINT12_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT12_GPD_Pos) /*!< 0x00000003 */ +#define IOMUX_EXINTC4_EXINT12_GPD IOMUX_EXINTC4_EXINT12_GPD_Msk /*!< GPIOD pin 12 */ +#define IOMUX_EXINTC4_EXINT12_GPF_Pos (2U) +#define IOMUX_EXINTC4_EXINT12_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT12_GPF_Pos) /*!< 0x00000004 */ +#define IOMUX_EXINTC4_EXINT12_GPF IOMUX_EXINTC4_EXINT12_GPF_Msk /*!< GPIOF pin 12 */ + +/* EXINT13 configuration */ +#define IOMUX_EXINTC4_EXINT13_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_Msk (0xFU << IOMUX_EXINTC4_EXINT13_Pos) /*!< 0x000000F0 */ +#define IOMUX_EXINTC4_EXINT13 IOMUX_EXINTC4_EXINT13_Msk /*!< EXINT13[3:0] bits (EXINT13 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT13_GPA 0x00000000U /*!< GPIOA pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPB_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPB_Pos) /*!< 0x00000010 */ +#define IOMUX_EXINTC4_EXINT13_GPB IOMUX_EXINTC4_EXINT13_GPB_Msk /*!< GPIOB pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPC_Pos (5U) +#define IOMUX_EXINTC4_EXINT13_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPC_Pos) /*!< 0x00000020 */ +#define IOMUX_EXINTC4_EXINT13_GPC IOMUX_EXINTC4_EXINT13_GPC_Msk /*!< GPIOC pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPD_Pos (4U) +#define IOMUX_EXINTC4_EXINT13_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT13_GPD_Pos) /*!< 0x00000030 */ +#define IOMUX_EXINTC4_EXINT13_GPD IOMUX_EXINTC4_EXINT13_GPD_Msk /*!< GPIOD pin 13 */ +#define IOMUX_EXINTC4_EXINT13_GPF_Pos (6U) +#define IOMUX_EXINTC4_EXINT13_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT13_GPF_Pos) /*!< 0x00000040 */ +#define IOMUX_EXINTC4_EXINT13_GPF IOMUX_EXINTC4_EXINT13_GPF_Msk /*!< GPIOF pin 13 */ + +/*!< EXINT14 configuration */ +#define IOMUX_EXINTC4_EXINT14_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_Msk (0xFU << IOMUX_EXINTC4_EXINT14_Pos) /*!< 0x00000F00 */ +#define IOMUX_EXINTC4_EXINT14 IOMUX_EXINTC4_EXINT14_Msk /*!< EXINT14[3:0] bits (EXINT14 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT14_GPA 0x00000000U /*!< GPIOA pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPB_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPB_Pos) /*!< 0x00000100 */ +#define IOMUX_EXINTC4_EXINT14_GPB IOMUX_EXINTC4_EXINT14_GPB_Msk /*!< GPIOB pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPC_Pos (9U) +#define IOMUX_EXINTC4_EXINT14_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPC_Pos) /*!< 0x00000200 */ +#define IOMUX_EXINTC4_EXINT14_GPC IOMUX_EXINTC4_EXINT14_GPC_Msk /*!< GPIOC pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPD_Pos (8U) +#define IOMUX_EXINTC4_EXINT14_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT14_GPD_Pos) /*!< 0x00000300 */ +#define IOMUX_EXINTC4_EXINT14_GPD IOMUX_EXINTC4_EXINT14_GPD_Msk /*!< GPIOD pin 14 */ +#define IOMUX_EXINTC4_EXINT14_GPF_Pos (10U) +#define IOMUX_EXINTC4_EXINT14_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT14_GPF_Pos) /*!< 0x00000400 */ +#define IOMUX_EXINTC4_EXINT14_GPF IOMUX_EXINTC4_EXINT14_GPF_Msk /*!< GPIOF pin 14 */ + +/*!< EXINT15 configuration */ +#define IOMUX_EXINTC4_EXINT15_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_Msk (0xFU << IOMUX_EXINTC4_EXINT15_Pos) /*!< 0x0000F000 */ +#define IOMUX_EXINTC4_EXINT15 IOMUX_EXINTC4_EXINT15_Msk /*!< EXINT15[3:0] bits (EXINT15 input source configuration) */ + +#define IOMUX_EXINTC4_EXINT15_GPA 0x00000000U /*!< GPIOA pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPB_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_GPB_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPB_Pos) /*!< 0x00001000 */ +#define IOMUX_EXINTC4_EXINT15_GPB IOMUX_EXINTC4_EXINT15_GPB_Msk /*!< GPIOB pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPC_Pos (13U) +#define IOMUX_EXINTC4_EXINT15_GPC_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPC_Pos) /*!< 0x00002000 */ +#define IOMUX_EXINTC4_EXINT15_GPC IOMUX_EXINTC4_EXINT15_GPC_Msk /*!< GPIOC pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPD_Pos (12U) +#define IOMUX_EXINTC4_EXINT15_GPD_Msk (0x3U << IOMUX_EXINTC4_EXINT15_GPD_Pos) /*!< 0x00003000 */ +#define IOMUX_EXINTC4_EXINT15_GPD IOMUX_EXINTC4_EXINT15_GPD_Msk /*!< GPIOD pin 15 */ +#define IOMUX_EXINTC4_EXINT15_GPF_Pos (14U) +#define IOMUX_EXINTC4_EXINT15_GPF_Msk (0x1U << IOMUX_EXINTC4_EXINT15_GPF_Pos) /*!< 0x00004000 */ +#define IOMUX_EXINTC4_EXINT15_GPF IOMUX_EXINTC4_EXINT15_GPF_Msk /*!< GPIOF pin 15 */ + +/***************** Bit definition for IOMUX_REMAP2 register *****************/ +/*!< CMP_MUX configuration */ +#define IOMUX_REMAP2_CMP_MUX_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ +#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ +#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP2_CMP_MUX_MUX0 0x00000000U /*!< CMP1_OUT is connected to PA0, CMP2_OUT is connected to PA2 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_MUX1_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX1_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1 IOMUX_REMAP2_CMP_MUX_MUX1_Msk /*!< CMP1_OUT is connected to PA6, CMP2_OUT is connected to PA7 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2_Pos (27U) +#define IOMUX_REMAP2_CMP_MUX_MUX2_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX2_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2 IOMUX_REMAP2_CMP_MUX_MUX2_Msk /*!< CMP1_OUT is connected to PA11, CMP2_OUT is connected to PA12 */ + +/***************** Bit definition for IOMUX_REMAP3 register *****************/ +/*!< TMR9_GMUX configuration */ +#define IOMUX_REMAP3_TMR9_GMUX_Pos (0U) +#define IOMUX_REMAP3_TMR9_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP3_TMR9_GMUX IOMUX_REMAP3_TMR9_GMUX_Msk /*!< TMR9_GMUX[3:0] bits (TMR9 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR9_GMUX_0 (0x1U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP3_TMR9_GMUX_1 (0x2U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_2 (0x4U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP3_TMR9_GMUX_3 (0x8U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP3_TMR9_GMUX_MUX0 0x00000000U /*!< CH1/PA2, CH2/PA3 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR9_GMUX_MUX2 IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk /*!< CH1/PB14, CH2/PB15 */ + +/*!< TMR10_GMUX configuration */ +#define IOMUX_REMAP3_TMR10_GMUX_Pos (4U) +#define IOMUX_REMAP3_TMR10_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x000000F0 */ +#define IOMUX_REMAP3_TMR10_GMUX IOMUX_REMAP3_TMR10_GMUX_Msk /*!< TMR10_GMUX[3:0] bits (TMR10 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR10_GMUX_0 (0x1U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP3_TMR10_GMUX_1 (0x2U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_2 (0x4U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP3_TMR10_GMUX_3 (0x8U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP3_TMR10_GMUX_MUX0 0x00000000U /*!< CH1/PB8 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR10_GMUX_MUX2 IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk /*!< CH1/PA6 */ + +/*!< TMR11_GMUX configuration */ +#define IOMUX_REMAP3_TMR11_GMUX_Pos (8U) +#define IOMUX_REMAP3_TMR11_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP3_TMR11_GMUX IOMUX_REMAP3_TMR11_GMUX_Msk /*!< TMR11_GMUX[3:0] bits (TMR11 IO general multiplexing) */ +#define IOMUX_REMAP3_TMR11_GMUX_0 (0x1U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP3_TMR11_GMUX_1 (0x2U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP3_TMR11_GMUX_2 (0x4U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */ + +/***************** Bit definition for IOMUX_REMAP4 register *****************/ +/*!< TMR1_GMUX configuration */ +#define IOMUX_REMAP4_TMR1_GMUX_Pos (0U) +#define IOMUX_REMAP4_TMR1_GMUX_Msk (0xFU << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP4_TMR1_GMUX IOMUX_REMAP4_TMR1_GMUX_Msk /*!< TMR1_GMUX[3:0] bits (TMR1 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR1_GMUX_0 (0x1U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_1 (0x2U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP4_TMR1_GMUX_2 (0x4U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP4_TMR1_GMUX_3 (0x8U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP4_TMR1_GMUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX1 IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ + +/*!< TMR2_GMUX configuration */ +#define IOMUX_REMAP4_TMR2_GMUX_Pos (4U) +#define IOMUX_REMAP4_TMR2_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000070 */ +#define IOMUX_REMAP4_TMR2_GMUX IOMUX_REMAP4_TMR2_GMUX_Msk /*!< TMR2_GMUX[2:0] bits (TMR2 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR2_GMUX_0 (0x1U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_1 (0x2U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP4_TMR2_GMUX_2 (0x4U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000040 */ + +#define IOMUX_REMAP4_TMR2_GMUX_MUX0 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX1 IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ + +/*!< TMR3_GMUX configuration */ +#define IOMUX_REMAP4_TMR3_GMUX_Pos (8U) +#define IOMUX_REMAP4_TMR3_GMUX_Msk (0xFU << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP4_TMR3_GMUX IOMUX_REMAP4_TMR3_GMUX_Msk /*!< TMR3_GMUX[3:0] bits (TMR3 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR3_GMUX_0 (0x1U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_1 (0x2U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP4_TMR3_GMUX_2 (0x4U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP4_TMR3_GMUX_3 (0x8U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP4_TMR3_GMUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR3_GMUX_MUX1 IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ + +/*!< TMR5_GMUX configuration */ +#define IOMUX_REMAP4_TMR5_GMUX_Pos (16U) +#define IOMUX_REMAP4_TMR5_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00070000 */ +#define IOMUX_REMAP4_TMR5_GMUX IOMUX_REMAP4_TMR5_GMUX_Msk /*!< TMR5_GMUX[2:0] bits (TMR5 IO general multiplexing) */ +#define IOMUX_REMAP4_TMR5_GMUX_0 (0x1U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_1 (0x2U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP4_TMR5_GMUX_2 (0x4U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00040000 */ + +#define IOMUX_REMAP4_TMR5_GMUX_MUX0 0x00000000U /*!< CH1/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR5_GMUX_MUX1 IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk /*!< CH1/PF4, CH2/PF5, CH3/PA2, CH4/PA3 */ + +#define IOMUX_REMAP4_TMR5CH4_GMUX_Pos (19U) +#define IOMUX_REMAP4_TMR5CH4_GMUX_Msk (0x1U << IOMUX_REMAP4_TMR5CH4_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP4_TMR5CH4_GMUX IOMUX_REMAP4_TMR5CH4_GMUX_Msk /*!< TMR5 channel 4 general multiplexing */ + +/***************** Bit definition for IOMUX_REMAP5 register *****************/ +/*!< I2C1_GMUX configuration */ +#define IOMUX_REMAP5_I2C1_GMUX_Pos (4U) +#define IOMUX_REMAP5_I2C1_GMUX_Msk (0xFU << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x000000F0 */ +#define IOMUX_REMAP5_I2C1_GMUX IOMUX_REMAP5_I2C1_GMUX_Msk /*!< I2C1_GMUX[3:0] bits (I2C1 IO general multiplexing) */ +#define IOMUX_REMAP5_I2C1_GMUX_0 (0x1U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_1 (0x2U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP5_I2C1_GMUX_2 (0x4U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP5_I2C1_GMUX_3 (0x8U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP5_I2C1_GMUX_MUX0 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX1 IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ + +/*!< I2C2_GMUX configuration */ +#define IOMUX_REMAP5_I2C2_GMUX_Pos (8U) +#define IOMUX_REMAP5_I2C2_GMUX_Msk (0xFU << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP5_I2C2_GMUX IOMUX_REMAP5_I2C2_GMUX_Msk /*!< I2C2_GMUX[3:0] bits (I2C2 IO general multiplexing) */ +#define IOMUX_REMAP5_I2C2_GMUX_0 (0x1U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_1 (0x2U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP5_I2C2_GMUX_2 (0x4U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP5_I2C2_GMUX_3 (0x8U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP5_I2C2_GMUX_MUX0 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX1 IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (8U) /*!< 0x00000300 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ + +/*!< SPI1_GMUX configuration */ +#define IOMUX_REMAP5_SPI1_GMUX_Pos (16U) +#define IOMUX_REMAP5_SPI1_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x000F0000 */ +#define IOMUX_REMAP5_SPI1_GMUX IOMUX_REMAP5_SPI1_GMUX_Msk /*!< SPI1_GMUX[3:0] bits (SPI1 IO general multiplexing) */ +#define IOMUX_REMAP5_SPI1_GMUX_0 (0x1U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_1 (0x2U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP5_SPI1_GMUX_2 (0x4U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP5_SPI1_GMUX_3 (0x8U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00080000 */ + +#define IOMUX_REMAP5_SPI1_GMUX_MUX0 0x00000000U /*!< CS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7, MCK/PB0 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI1_GMUX_MUX1 IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PB6 */ + +/*!< SPI2_GMUX configuration */ +#define IOMUX_REMAP5_SPI2_GMUX_Pos (20U) +#define IOMUX_REMAP5_SPI2_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00F00000 */ +#define IOMUX_REMAP5_SPI2_GMUX IOMUX_REMAP5_SPI2_GMUX_Msk /*!< SPI2_GMUX[3:0] bits (SPI2 IO general multiplexing) */ +#define IOMUX_REMAP5_SPI2_GMUX_0 (0x1U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_1 (0x2U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00200000 */ +#define IOMUX_REMAP5_SPI2_GMUX_2 (0x4U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00400000 */ +#define IOMUX_REMAP5_SPI2_GMUX_3 (0x8U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00800000 */ + +#define IOMUX_REMAP5_SPI2_GMUX_MUX0 0x00000000U /*!< CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15, MCK/PC6 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos (20U) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI2_GMUX_MUX1 IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PC7 */ + +/***************** Bit definition for IOMUX_REMAP6 register *****************/ +/*!< CAN1_GMUX configuration */ +#define IOMUX_REMAP6_CAN1_GMUX_Pos (0U) +#define IOMUX_REMAP6_CAN1_GMUX_Msk (0xFU << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x0000000F */ +#define IOMUX_REMAP6_CAN1_GMUX IOMUX_REMAP6_CAN1_GMUX_Msk /*!< CAN1_GMUX[3:0] bits (CAN1 IO general multiplexing) */ +#define IOMUX_REMAP6_CAN1_GMUX_0 (0x1U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP6_CAN1_GMUX_1 (0x2U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_2 (0x4U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP6_CAN1_GMUX_3 (0x8U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP6_CAN1_GMUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_CAN1_GMUX_MUX2 IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + +/*!< SDIO_GMUX configuration */ +#define IOMUX_REMAP6_SDIO_GMUX_Pos (8U) +#define IOMUX_REMAP6_SDIO_GMUX_Msk (0xFU << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000F00 */ +#define IOMUX_REMAP6_SDIO_GMUX IOMUX_REMAP6_SDIO_GMUX_Msk /*!< SDIO_GMUX[3:0] bits (SDIO IO general multiplexing) */ +#define IOMUX_REMAP6_SDIO_GMUX_0 (0x1U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP6_SDIO_GMUX_1 (0x2U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP6_SDIO_GMUX_2 (0x4U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_3 (0x8U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000800 */ + +#define IOMUX_REMAP6_SDIO_GMUX_MUX0 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (10U) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000500 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos (9U) /*!< 0x00000600 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX6 IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos (8U) /*!< 0x00000700 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX7 IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ + +/*!< USART1_GMUX configuration */ +#define IOMUX_REMAP6_USART1_GMUX_Pos (16U) +#define IOMUX_REMAP6_USART1_GMUX_Msk (0xFU << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x000F0000 */ +#define IOMUX_REMAP6_USART1_GMUX IOMUX_REMAP6_USART1_GMUX_Msk /*!< USART1_GMUX[3:0] bits (USART1 IO general multiplexing) */ +#define IOMUX_REMAP6_USART1_GMUX_0 (0x1U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_1 (0x2U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP6_USART1_GMUX_2 (0x4U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP6_USART1_GMUX_3 (0x8U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00080000 */ + +#define IOMUX_REMAP6_USART1_GMUX_MUX0 0x00000000U /*!< TX/PA9, RX/PA10 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART1_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART1_GMUX_MUX1 IOMUX_REMAP6_USART1_GMUX_MUX1_Msk /*!< TX/PB6, RX/PB7 */ + +/*!< USART3_GMUX configuration */ +#define IOMUX_REMAP6_USART3_GMUX_Pos (24U) +#define IOMUX_REMAP6_USART3_GMUX_Msk (0xFU << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x0F000000 */ +#define IOMUX_REMAP6_USART3_GMUX IOMUX_REMAP6_USART3_GMUX_Msk /*!< USART3_GMUX[3:0] bits (USART3 IO general multiplexing) */ +#define IOMUX_REMAP6_USART3_GMUX_0 (0x1U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_1 (0x2U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x02000000 */ +#define IOMUX_REMAP6_USART3_GMUX_2 (0x4U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP6_USART3_GMUX_3 (0x8U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP6_USART3_GMUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART3_GMUX_MUX1 IOMUX_REMAP6_USART3_GMUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2_Pos (25U) /*!< 0x02000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_USART3_GMUX_MUX2 IOMUX_REMAP6_USART3_GMUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ + +/*!< UART4_GMUX configuration */ +#define IOMUX_REMAP6_UART4_GMUX_Pos (28U) +#define IOMUX_REMAP6_UART4_GMUX_Msk (0xFU << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0xF0000000 */ +#define IOMUX_REMAP6_UART4_GMUX IOMUX_REMAP6_UART4_GMUX_Msk /*!< UART4_GMUX[3:0] bits (UART4 IO general multiplexing) */ +#define IOMUX_REMAP6_UART4_GMUX_0 (0x1U << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0x10000000 */ +#define IOMUX_REMAP6_UART4_GMUX_1 (0x2U << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0x20000000 */ +#define IOMUX_REMAP6_UART4_GMUX_2 (0x4U << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0x40000000 */ +#define IOMUX_REMAP6_UART4_GMUX_3 (0x8U << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0x80000000 */ + +#define IOMUX_REMAP6_UART4_GMUX_MUX0 0x00000000U /*!< TX/PC10, RX/PC11 */ +#define IOMUX_REMAP6_UART4_GMUX_MUX1_Pos (28U) /*!< 0x10000000 */ +#define IOMUX_REMAP6_UART4_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_UART4_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_UART4_GMUX_MUX1 IOMUX_REMAP6_UART4_GMUX_MUX1_Msk /*!< TX/PF4, RX/PF5 */ + +/***************** Bit definition for IOMUX_REMAP7 register *****************/ +#define IOMUX_REMAP7_ADC1_ETP_GMUX_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP7_ADC1_ETP_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETP_GMUX_Pos) +#define IOMUX_REMAP7_ADC1_ETP_GMUX IOMUX_REMAP7_ADC1_ETP_GMUX_Msk /*!< ADC1 External trigger preempted conversion general multiplexing */ +#define IOMUX_REMAP7_ADC1_ETO_GMUX_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP7_ADC1_ETO_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETO_GMUX_Pos) +#define IOMUX_REMAP7_ADC1_ETO_GMUX IOMUX_REMAP7_ADC1_ETO_GMUX_Msk /*!< ADC1 external trigger regular conversion general multiplexing */ + +/*!< SWJTAG_GMUX configuration */ +#define IOMUX_REMAP7_SWJTAG_GMUX_Pos (16U) +#define IOMUX_REMAP7_SWJTAG_GMUX_Msk (0x7U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00070000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX IOMUX_REMAP7_SWJTAG_GMUX_Msk /*!< SWJTAG_GMUX[2:0] bits (SWD JTAG IO general mutiplexing) */ +#define IOMUX_REMAP7_SWJTAG_GMUX_0 (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_1 (0x2U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_2 (0x4U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00040000 */ + +#define IOMUX_REMAP7_SWJTAG_GMUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos (17U) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos (18U) /*!< 0x00040000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ + +#define IOMUX_REMAP7_PD01_GMUX_Pos (20U) +#define IOMUX_REMAP7_PD01_GMUX_Msk (0x1U << IOMUX_REMAP7_PD01_GMUX_Pos) /*!< 0x00100000 */ +#define IOMUX_REMAP7_PD01_GMUX IOMUX_REMAP7_PD01_GMUX_Msk /*!< PD0/PD1 mapped onto HEXT_IN / HEXT_OUT */ + +/***************** Bit definition for IOMUX_REMAP8 register *****************/ +/*!< TMR1_BK1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Msk /*!< TMR1_BK1_CMP_GMUX[1:0] bits (TMR1 break channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */ + +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ + +/*!< TMR1_CH1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk /*!< TMR1_CH1_CMP_GMUX[1:0] bits (TMR1 channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */ + +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 channel 1 */ + +/*!< TMR2_CH4_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk /*!< TMR2_CH4_CMP_GMUX[1:0] bits (TMR2 channel 4 internal mapping) */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */ + +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 */ + +/*!< TMR3_CH1_CMP_GMUX configuration */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk /*!< TMR3_CH1_CMP_GMUX[1:0] bits (TMR3 channel 1 internal mapping) */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */ + +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR3_GMUX IO signal is connected to TMR3 channel 1 */ + +/******************************************************************************/ +/* */ +/* External interrupt/Event controller (EXINT) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for EXINT_INTEN register ******************/ +#define EXINT_INTEN_INTEN0_Pos (0U) +#define EXINT_INTEN_INTEN0_Msk (0x1U << EXINT_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_INTEN_INTEN0 EXINT_INTEN_INTEN0_Msk /*!< Interrupt enable or disable on line 0 */ +#define EXINT_INTEN_INTEN1_Pos (1U) +#define EXINT_INTEN_INTEN1_Msk (0x1U << EXINT_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_INTEN_INTEN1 EXINT_INTEN_INTEN1_Msk /*!< Interrupt enable or disable on line 1 */ +#define EXINT_INTEN_INTEN2_Pos (2U) +#define EXINT_INTEN_INTEN2_Msk (0x1U << EXINT_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_INTEN_INTEN2 EXINT_INTEN_INTEN2_Msk /*!< Interrupt enable or disable on line 2 */ +#define EXINT_INTEN_INTEN3_Pos (3U) +#define EXINT_INTEN_INTEN3_Msk (0x1U << EXINT_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_INTEN_INTEN3 EXINT_INTEN_INTEN3_Msk /*!< Interrupt enable or disable on line 3 */ +#define EXINT_INTEN_INTEN4_Pos (4U) +#define EXINT_INTEN_INTEN4_Msk (0x1U << EXINT_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_INTEN_INTEN4 EXINT_INTEN_INTEN4_Msk /*!< Interrupt enable or disable on line 4 */ +#define EXINT_INTEN_INTEN5_Pos (5U) +#define EXINT_INTEN_INTEN5_Msk (0x1U << EXINT_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_INTEN_INTEN5 EXINT_INTEN_INTEN5_Msk /*!< Interrupt enable or disable on line 5 */ +#define EXINT_INTEN_INTEN6_Pos (6U) +#define EXINT_INTEN_INTEN6_Msk (0x1U << EXINT_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_INTEN_INTEN6 EXINT_INTEN_INTEN6_Msk /*!< Interrupt enable or disable on line 6 */ +#define EXINT_INTEN_INTEN7_Pos (7U) +#define EXINT_INTEN_INTEN7_Msk (0x1U << EXINT_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_INTEN_INTEN7 EXINT_INTEN_INTEN7_Msk /*!< Interrupt enable or disable on line 7 */ +#define EXINT_INTEN_INTEN8_Pos (8U) +#define EXINT_INTEN_INTEN8_Msk (0x1U << EXINT_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_INTEN_INTEN8 EXINT_INTEN_INTEN8_Msk /*!< Interrupt enable or disable on line 8 */ +#define EXINT_INTEN_INTEN9_Pos (9U) +#define EXINT_INTEN_INTEN9_Msk (0x1U << EXINT_INTEN_INTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_INTEN_INTEN9 EXINT_INTEN_INTEN9_Msk /*!< Interrupt enable or disable on line 9 */ +#define EXINT_INTEN_INTEN10_Pos (10U) +#define EXINT_INTEN_INTEN10_Msk (0x1U << EXINT_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_INTEN_INTEN10 EXINT_INTEN_INTEN10_Msk /*!< Interrupt enable or disable on line 10 */ +#define EXINT_INTEN_INTEN11_Pos (11U) +#define EXINT_INTEN_INTEN11_Msk (0x1U << EXINT_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_INTEN_INTEN11 EXINT_INTEN_INTEN11_Msk /*!< Interrupt enable or disable on line 11 */ +#define EXINT_INTEN_INTEN12_Pos (12U) +#define EXINT_INTEN_INTEN12_Msk (0x1U << EXINT_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_INTEN_INTEN12 EXINT_INTEN_INTEN12_Msk /*!< Interrupt enable or disable on line 12 */ +#define EXINT_INTEN_INTEN13_Pos (13U) +#define EXINT_INTEN_INTEN13_Msk (0x1U << EXINT_INTEN_INTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_INTEN_INTEN13 EXINT_INTEN_INTEN13_Msk /*!< Interrupt enable or disable on line 13 */ +#define EXINT_INTEN_INTEN14_Pos (14U) +#define EXINT_INTEN_INTEN14_Msk (0x1U << EXINT_INTEN_INTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_INTEN_INTEN14 EXINT_INTEN_INTEN14_Msk /*!< Interrupt enable or disable on line 14 */ +#define EXINT_INTEN_INTEN15_Pos (15U) +#define EXINT_INTEN_INTEN15_Msk (0x1U << EXINT_INTEN_INTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_INTEN_INTEN15 EXINT_INTEN_INTEN15_Msk /*!< Interrupt enable or disable on line 15 */ +#define EXINT_INTEN_INTEN16_Pos (16U) +#define EXINT_INTEN_INTEN16_Msk (0x1U << EXINT_INTEN_INTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_INTEN_INTEN16 EXINT_INTEN_INTEN16_Msk /*!< Interrupt enable or disable on line 16 */ +#define EXINT_INTEN_INTEN17_Pos (17U) +#define EXINT_INTEN_INTEN17_Msk (0x1U << EXINT_INTEN_INTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_INTEN_INTEN17 EXINT_INTEN_INTEN17_Msk /*!< Interrupt enable or disable on line 17 */ +#define EXINT_INTEN_INTEN18_Pos (18U) +#define EXINT_INTEN_INTEN18_Msk (0x1U << EXINT_INTEN_INTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_INTEN_INTEN18 EXINT_INTEN_INTEN18_Msk /*!< Interrupt enable or disable on line 18 */ +#define EXINT_INTEN_INTEN19_Pos (19U) +#define EXINT_INTEN_INTEN19_Msk (0x1U << EXINT_INTEN_INTEN19_Pos) /*!< 0x00080000 */ +#define EXINT_INTEN_INTEN19 EXINT_INTEN_INTEN19_Msk /*!< Interrupt enable or disable on line 19 */ +#define EXINT_INTEN_INTEN20_Pos (20U) +#define EXINT_INTEN_INTEN20_Msk (0x1U << EXINT_INTEN_INTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_INTEN_INTEN20 EXINT_INTEN_INTEN20_Msk /*!< Interrupt enable or disable on line 20 */ +#define EXINT_INTEN_INTEN21_Pos (21U) +#define EXINT_INTEN_INTEN21_Msk (0x1U << EXINT_INTEN_INTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_INTEN_INTEN21 EXINT_INTEN_INTEN21_Msk /*!< Interrupt enable or disable on line 21 */ +#define EXINT_INTEN_INTEN22_Pos (22U) +#define EXINT_INTEN_INTEN22_Msk (0x1U << EXINT_INTEN_INTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_INTEN_INTEN22 EXINT_INTEN_INTEN22_Msk /*!< Interrupt enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_INTEN_INT0 EXINT_INTEN_INTEN0 +#define EXINT_INTEN_INT1 EXINT_INTEN_INTEN1 +#define EXINT_INTEN_INT2 EXINT_INTEN_INTEN2 +#define EXINT_INTEN_INT3 EXINT_INTEN_INTEN3 +#define EXINT_INTEN_INT4 EXINT_INTEN_INTEN4 +#define EXINT_INTEN_INT5 EXINT_INTEN_INTEN5 +#define EXINT_INTEN_INT6 EXINT_INTEN_INTEN6 +#define EXINT_INTEN_INT7 EXINT_INTEN_INTEN7 +#define EXINT_INTEN_INT8 EXINT_INTEN_INTEN8 +#define EXINT_INTEN_INT9 EXINT_INTEN_INTEN9 +#define EXINT_INTEN_INT10 EXINT_INTEN_INTEN10 +#define EXINT_INTEN_INT11 EXINT_INTEN_INTEN11 +#define EXINT_INTEN_INT12 EXINT_INTEN_INTEN12 +#define EXINT_INTEN_INT13 EXINT_INTEN_INTEN13 +#define EXINT_INTEN_INT14 EXINT_INTEN_INTEN14 +#define EXINT_INTEN_INT15 EXINT_INTEN_INTEN15 +#define EXINT_INTEN_INT16 EXINT_INTEN_INTEN16 +#define EXINT_INTEN_INT17 EXINT_INTEN_INTEN17 +#define EXINT_INTEN_INT18 EXINT_INTEN_INTEN18 +#define EXINT_INTEN_INT19 EXINT_INTEN_INTEN19 +#define EXINT_INTEN_INT20 EXINT_INTEN_INTEN20 +#define EXINT_INTEN_INT21 EXINT_INTEN_INTEN21 +#define EXINT_INTEN_INT22 EXINT_INTEN_INTEN22 +#define EXINT_INTEN_INT 0x007FFFFFU /*!< Interrupt enable or disable all */ + +/***************** Bit definition for EXINT_EVTEN register ******************/ +#define EXINT_EVTEN_EVTEN0_Pos (0U) +#define EXINT_EVTEN_EVTEN0_Msk (0x1U << EXINT_EVTEN_EVTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_EVTEN_EVTEN0 EXINT_EVTEN_EVTEN0_Msk /*!< Event enable or disable on line 0 */ +#define EXINT_EVTEN_EVTEN1_Pos (1U) +#define EXINT_EVTEN_EVTEN1_Msk (0x1U << EXINT_EVTEN_EVTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_EVTEN_EVTEN1 EXINT_EVTEN_EVTEN1_Msk /*!< Event enable or disable on line 1 */ +#define EXINT_EVTEN_EVTEN2_Pos (2U) +#define EXINT_EVTEN_EVTEN2_Msk (0x1U << EXINT_EVTEN_EVTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_EVTEN_EVTEN2 EXINT_EVTEN_EVTEN2_Msk /*!< Event enable or disable on line 2 */ +#define EXINT_EVTEN_EVTEN3_Pos (3U) +#define EXINT_EVTEN_EVTEN3_Msk (0x1U << EXINT_EVTEN_EVTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_EVTEN_EVTEN3 EXINT_EVTEN_EVTEN3_Msk /*!< Event enable or disable on line 3 */ +#define EXINT_EVTEN_EVTEN4_Pos (4U) +#define EXINT_EVTEN_EVTEN4_Msk (0x1U << EXINT_EVTEN_EVTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_EVTEN_EVTEN4 EXINT_EVTEN_EVTEN4_Msk /*!< Event enable or disable on line 4 */ +#define EXINT_EVTEN_EVTEN5_Pos (5U) +#define EXINT_EVTEN_EVTEN5_Msk (0x1U << EXINT_EVTEN_EVTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_EVTEN_EVTEN5 EXINT_EVTEN_EVTEN5_Msk /*!< Event enable or disable on line 5 */ +#define EXINT_EVTEN_EVTEN6_Pos (6U) +#define EXINT_EVTEN_EVTEN6_Msk (0x1U << EXINT_EVTEN_EVTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_EVTEN_EVTEN6 EXINT_EVTEN_EVTEN6_Msk /*!< Event enable or disable on line 6 */ +#define EXINT_EVTEN_EVTEN7_Pos (7U) +#define EXINT_EVTEN_EVTEN7_Msk (0x1U << EXINT_EVTEN_EVTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_EVTEN_EVTEN7 EXINT_EVTEN_EVTEN7_Msk /*!< Event enable or disable on line 7 */ +#define EXINT_EVTEN_EVTEN8_Pos (8U) +#define EXINT_EVTEN_EVTEN8_Msk (0x1U << EXINT_EVTEN_EVTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_EVTEN_EVTEN8 EXINT_EVTEN_EVTEN8_Msk /*!< Event enable or disable on line 8 */ +#define EXINT_EVTEN_EVTEN9_Pos (9U) +#define EXINT_EVTEN_EVTEN9_Msk (0x1U << EXINT_EVTEN_EVTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_EVTEN_EVTEN9 EXINT_EVTEN_EVTEN9_Msk /*!< Event enable or disable on line 9 */ +#define EXINT_EVTEN_EVTEN10_Pos (10U) +#define EXINT_EVTEN_EVTEN10_Msk (0x1U << EXINT_EVTEN_EVTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_EVTEN_EVTEN10 EXINT_EVTEN_EVTEN10_Msk /*!< Event enable or disable on line 10 */ +#define EXINT_EVTEN_EVTEN11_Pos (11U) +#define EXINT_EVTEN_EVTEN11_Msk (0x1U << EXINT_EVTEN_EVTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_EVTEN_EVTEN11 EXINT_EVTEN_EVTEN11_Msk /*!< Event enable or disable on line 11 */ +#define EXINT_EVTEN_EVTEN12_Pos (12U) +#define EXINT_EVTEN_EVTEN12_Msk (0x1U << EXINT_EVTEN_EVTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_EVTEN_EVTEN12 EXINT_EVTEN_EVTEN12_Msk /*!< Event enable or disable on line 12 */ +#define EXINT_EVTEN_EVTEN13_Pos (13U) +#define EXINT_EVTEN_EVTEN13_Msk (0x1U << EXINT_EVTEN_EVTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_EVTEN_EVTEN13 EXINT_EVTEN_EVTEN13_Msk /*!< Event enable or disable on line 13 */ +#define EXINT_EVTEN_EVTEN14_Pos (14U) +#define EXINT_EVTEN_EVTEN14_Msk (0x1U << EXINT_EVTEN_EVTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_EVTEN_EVTEN14 EXINT_EVTEN_EVTEN14_Msk /*!< Event enable or disable on line 14 */ +#define EXINT_EVTEN_EVTEN15_Pos (15U) +#define EXINT_EVTEN_EVTEN15_Msk (0x1U << EXINT_EVTEN_EVTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_EVTEN_EVTEN15 EXINT_EVTEN_EVTEN15_Msk /*!< Event enable or disable on line 15 */ +#define EXINT_EVTEN_EVTEN16_Pos (16U) +#define EXINT_EVTEN_EVTEN16_Msk (0x1U << EXINT_EVTEN_EVTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_EVTEN_EVTEN16 EXINT_EVTEN_EVTEN16_Msk /*!< Event enable or disable on line 16 */ +#define EXINT_EVTEN_EVTEN17_Pos (17U) +#define EXINT_EVTEN_EVTEN17_Msk (0x1U << EXINT_EVTEN_EVTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_EVTEN_EVTEN17 EXINT_EVTEN_EVTEN17_Msk /*!< Event enable or disable on line 17 */ +#define EXINT_EVTEN_EVTEN18_Pos (18U) +#define EXINT_EVTEN_EVTEN18_Msk (0x1U << EXINT_EVTEN_EVTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_EVTEN_EVTEN18 EXINT_EVTEN_EVTEN18_Msk /*!< Event enable or disable on line 18 */ +#define EXINT_EVTEN_EVTEN19_Pos (19U) +#define EXINT_EVTEN_EVTEN19_Msk (0x1U << EXINT_EVTEN_EVTEN19_Pos) /*!< 0x00080000 */ +#define EXINT_EVTEN_EVTEN19 EXINT_EVTEN_EVTEN19_Msk /*!< Event enable or disable on line 19 */ +#define EXINT_EVTEN_EVTEN20_Pos (20U) +#define EXINT_EVTEN_EVTEN20_Msk (0x1U << EXINT_EVTEN_EVTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_EVTEN_EVTEN20 EXINT_EVTEN_EVTEN20_Msk /*!< Event enable or disable on line 20 */ +#define EXINT_EVTEN_EVTEN21_Pos (21U) +#define EXINT_EVTEN_EVTEN21_Msk (0x1U << EXINT_EVTEN_EVTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_EVTEN_EVTEN21 EXINT_EVTEN_EVTEN21_Msk /*!< Event enable or disable on line 21 */ +#define EXINT_EVTEN_EVTEN22_Pos (22U) +#define EXINT_EVTEN_EVTEN22_Msk (0x1U << EXINT_EVTEN_EVTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_EVTEN_EVTEN22 EXINT_EVTEN_EVTEN22_Msk /*!< Event enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_EVTEN_EVT0 EXINT_EVTEN_EVTEN0 +#define EXINT_EVTEN_EVT1 EXINT_EVTEN_EVTEN1 +#define EXINT_EVTEN_EVT2 EXINT_EVTEN_EVTEN2 +#define EXINT_EVTEN_EVT3 EXINT_EVTEN_EVTEN3 +#define EXINT_EVTEN_EVT4 EXINT_EVTEN_EVTEN4 +#define EXINT_EVTEN_EVT5 EXINT_EVTEN_EVTEN5 +#define EXINT_EVTEN_EVT6 EXINT_EVTEN_EVTEN6 +#define EXINT_EVTEN_EVT7 EXINT_EVTEN_EVTEN7 +#define EXINT_EVTEN_EVT8 EXINT_EVTEN_EVTEN8 +#define EXINT_EVTEN_EVT9 EXINT_EVTEN_EVTEN9 +#define EXINT_EVTEN_EVT10 EXINT_EVTEN_EVTEN10 +#define EXINT_EVTEN_EVT11 EXINT_EVTEN_EVTEN11 +#define EXINT_EVTEN_EVT12 EXINT_EVTEN_EVTEN12 +#define EXINT_EVTEN_EVT13 EXINT_EVTEN_EVTEN13 +#define EXINT_EVTEN_EVT14 EXINT_EVTEN_EVTEN14 +#define EXINT_EVTEN_EVT15 EXINT_EVTEN_EVTEN15 +#define EXINT_EVTEN_EVT16 EXINT_EVTEN_EVTEN16 +#define EXINT_EVTEN_EVT17 EXINT_EVTEN_EVTEN17 +#define EXINT_EVTEN_EVT18 EXINT_EVTEN_EVTEN18 +#define EXINT_EVTEN_EVT19 EXINT_EVTEN_EVTEN19 +#define EXINT_EVTEN_EVT20 EXINT_EVTEN_EVTEN20 +#define EXINT_EVTEN_EVT21 EXINT_EVTEN_EVTEN21 +#define EXINT_EVTEN_EVT22 EXINT_EVTEN_EVTEN22 + +/**************** Bit definition for EXINT_POLCFG1 register *****************/ +#define EXINT_POLCFG1_RP0_Pos (0U) +#define EXINT_POLCFG1_RP0_Msk (0x1U << EXINT_POLCFG1_RP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG1_RP0 EXINT_POLCFG1_RP0_Msk /*!< Rising edge event configuration bit on line 0 */ +#define EXINT_POLCFG1_RP1_Pos (1U) +#define EXINT_POLCFG1_RP1_Msk (0x1U << EXINT_POLCFG1_RP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG1_RP1 EXINT_POLCFG1_RP1_Msk /*!< Rising edge event configuration bit on line 1 */ +#define EXINT_POLCFG1_RP2_Pos (2U) +#define EXINT_POLCFG1_RP2_Msk (0x1U << EXINT_POLCFG1_RP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG1_RP2 EXINT_POLCFG1_RP2_Msk /*!< Rising edge event configuration bit on line 2 */ +#define EXINT_POLCFG1_RP3_Pos (3U) +#define EXINT_POLCFG1_RP3_Msk (0x1U << EXINT_POLCFG1_RP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG1_RP3 EXINT_POLCFG1_RP3_Msk /*!< Rising edge event configuration bit on line 3 */ +#define EXINT_POLCFG1_RP4_Pos (4U) +#define EXINT_POLCFG1_RP4_Msk (0x1U << EXINT_POLCFG1_RP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG1_RP4 EXINT_POLCFG1_RP4_Msk /*!< Rising edge event configuration bit on line 4 */ +#define EXINT_POLCFG1_RP5_Pos (5U) +#define EXINT_POLCFG1_RP5_Msk (0x1U << EXINT_POLCFG1_RP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG1_RP5 EXINT_POLCFG1_RP5_Msk /*!< Rising edge event configuration bit on line 5 */ +#define EXINT_POLCFG1_RP6_Pos (6U) +#define EXINT_POLCFG1_RP6_Msk (0x1U << EXINT_POLCFG1_RP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG1_RP6 EXINT_POLCFG1_RP6_Msk /*!< Rising edge event configuration bit on line 6 */ +#define EXINT_POLCFG1_RP7_Pos (7U) +#define EXINT_POLCFG1_RP7_Msk (0x1U << EXINT_POLCFG1_RP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG1_RP7 EXINT_POLCFG1_RP7_Msk /*!< Rising edge event configuration bit on line 7 */ +#define EXINT_POLCFG1_RP8_Pos (8U) +#define EXINT_POLCFG1_RP8_Msk (0x1U << EXINT_POLCFG1_RP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG1_RP8 EXINT_POLCFG1_RP8_Msk /*!< Rising edge event configuration bit on line 8 */ +#define EXINT_POLCFG1_RP9_Pos (9U) +#define EXINT_POLCFG1_RP9_Msk (0x1U << EXINT_POLCFG1_RP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG1_RP9 EXINT_POLCFG1_RP9_Msk /*!< Rising edge event configuration bit on line 9 */ +#define EXINT_POLCFG1_RP10_Pos (10U) +#define EXINT_POLCFG1_RP10_Msk (0x1U << EXINT_POLCFG1_RP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG1_RP10 EXINT_POLCFG1_RP10_Msk /*!< Rising edge event configuration bit on line 10 */ +#define EXINT_POLCFG1_RP11_Pos (11U) +#define EXINT_POLCFG1_RP11_Msk (0x1U << EXINT_POLCFG1_RP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG1_RP11 EXINT_POLCFG1_RP11_Msk /*!< Rising edge event configuration bit on line 11 */ +#define EXINT_POLCFG1_RP12_Pos (12U) +#define EXINT_POLCFG1_RP12_Msk (0x1U << EXINT_POLCFG1_RP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG1_RP12 EXINT_POLCFG1_RP12_Msk /*!< Rising edge event configuration bit on line 12 */ +#define EXINT_POLCFG1_RP13_Pos (13U) +#define EXINT_POLCFG1_RP13_Msk (0x1U << EXINT_POLCFG1_RP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG1_RP13 EXINT_POLCFG1_RP13_Msk /*!< Rising edge event configuration bit on line 13 */ +#define EXINT_POLCFG1_RP14_Pos (14U) +#define EXINT_POLCFG1_RP14_Msk (0x1U << EXINT_POLCFG1_RP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG1_RP14 EXINT_POLCFG1_RP14_Msk /*!< Rising edge event configuration bit on line 14 */ +#define EXINT_POLCFG1_RP15_Pos (15U) +#define EXINT_POLCFG1_RP15_Msk (0x1U << EXINT_POLCFG1_RP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG1_RP15 EXINT_POLCFG1_RP15_Msk /*!< Rising edge event configuration bit on line 15 */ +#define EXINT_POLCFG1_RP16_Pos (16U) +#define EXINT_POLCFG1_RP16_Msk (0x1U << EXINT_POLCFG1_RP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG1_RP16 EXINT_POLCFG1_RP16_Msk /*!< Rising edge event configuration bit on line 16 */ +#define EXINT_POLCFG1_RP17_Pos (17U) +#define EXINT_POLCFG1_RP17_Msk (0x1U << EXINT_POLCFG1_RP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG1_RP17 EXINT_POLCFG1_RP17_Msk /*!< Rising edge event configuration bit on line 17 */ +#define EXINT_POLCFG1_RP18_Pos (18U) +#define EXINT_POLCFG1_RP18_Msk (0x1U << EXINT_POLCFG1_RP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG1_RP18 EXINT_POLCFG1_RP18_Msk /*!< Rising edge event configuration bit on line 18 */ +#define EXINT_POLCFG1_RP19_Pos (19U) +#define EXINT_POLCFG1_RP19_Msk (0x1U << EXINT_POLCFG1_RP19_Pos) /*!< 0x00080000 */ +#define EXINT_POLCFG1_RP19 EXINT_POLCFG1_RP19_Msk /*!< Rising edge event configuration bit on line 19 */ +#define EXINT_POLCFG1_RP20_Pos (20U) +#define EXINT_POLCFG1_RP20_Msk (0x1U << EXINT_POLCFG1_RP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG1_RP20 EXINT_POLCFG1_RP20_Msk /*!< Rising edge event configuration bit on line 20 */ +#define EXINT_POLCFG1_RP21_Pos (21U) +#define EXINT_POLCFG1_RP21_Msk (0x1U << EXINT_POLCFG1_RP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG1_RP21 EXINT_POLCFG1_RP21_Msk /*!< Rising edge event configuration bit on line 21 */ +#define EXINT_POLCFG1_RP22_Pos (22U) +#define EXINT_POLCFG1_RP22_Msk (0x1U << EXINT_POLCFG1_RP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG1_RP22 EXINT_POLCFG1_RP22_Msk /*!< Rising edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG1_POL0 EXINT_POLCFG1_RP0 +#define EXINT_POLCFG1_POL1 EXINT_POLCFG1_RP1 +#define EXINT_POLCFG1_POL2 EXINT_POLCFG1_RP2 +#define EXINT_POLCFG1_POL3 EXINT_POLCFG1_RP3 +#define EXINT_POLCFG1_POL4 EXINT_POLCFG1_RP4 +#define EXINT_POLCFG1_POL5 EXINT_POLCFG1_RP5 +#define EXINT_POLCFG1_POL6 EXINT_POLCFG1_RP6 +#define EXINT_POLCFG1_POL7 EXINT_POLCFG1_RP7 +#define EXINT_POLCFG1_POL8 EXINT_POLCFG1_RP8 +#define EXINT_POLCFG1_POL9 EXINT_POLCFG1_RP9 +#define EXINT_POLCFG1_POL10 EXINT_POLCFG1_RP10 +#define EXINT_POLCFG1_POL11 EXINT_POLCFG1_RP11 +#define EXINT_POLCFG1_POL12 EXINT_POLCFG1_RP12 +#define EXINT_POLCFG1_POL13 EXINT_POLCFG1_RP13 +#define EXINT_POLCFG1_POL14 EXINT_POLCFG1_RP14 +#define EXINT_POLCFG1_POL15 EXINT_POLCFG1_RP15 +#define EXINT_POLCFG1_POL16 EXINT_POLCFG1_RP16 +#define EXINT_POLCFG1_POL17 EXINT_POLCFG1_RP17 +#define EXINT_POLCFG1_POL18 EXINT_POLCFG1_RP18 +#define EXINT_POLCFG1_POL19 EXINT_POLCFG1_RP19 +#define EXINT_POLCFG1_POL20 EXINT_POLCFG1_RP20 +#define EXINT_POLCFG1_POL21 EXINT_POLCFG1_RP21 +#define EXINT_POLCFG1_POL22 EXINT_POLCFG1_RP22 + +/**************** Bit definition for EXINT_POLCFG2 register *****************/ +#define EXINT_POLCFG2_FP0_Pos (0U) +#define EXINT_POLCFG2_FP0_Msk (0x1U << EXINT_POLCFG2_FP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG2_FP0 EXINT_POLCFG2_FP0_Msk /*!< Falling edge event configuration bit on line 0 */ +#define EXINT_POLCFG2_FP1_Pos (1U) +#define EXINT_POLCFG2_FP1_Msk (0x1U << EXINT_POLCFG2_FP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG2_FP1 EXINT_POLCFG2_FP1_Msk /*!< Falling edge event configuration bit on line 1 */ +#define EXINT_POLCFG2_FP2_Pos (2U) +#define EXINT_POLCFG2_FP2_Msk (0x1U << EXINT_POLCFG2_FP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG2_FP2 EXINT_POLCFG2_FP2_Msk /*!< Falling edge event configuration bit on line 2 */ +#define EXINT_POLCFG2_FP3_Pos (3U) +#define EXINT_POLCFG2_FP3_Msk (0x1U << EXINT_POLCFG2_FP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG2_FP3 EXINT_POLCFG2_FP3_Msk /*!< Falling edge event configuration bit on line 3 */ +#define EXINT_POLCFG2_FP4_Pos (4U) +#define EXINT_POLCFG2_FP4_Msk (0x1U << EXINT_POLCFG2_FP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG2_FP4 EXINT_POLCFG2_FP4_Msk /*!< Falling edge event configuration bit on line 4 */ +#define EXINT_POLCFG2_FP5_Pos (5U) +#define EXINT_POLCFG2_FP5_Msk (0x1U << EXINT_POLCFG2_FP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG2_FP5 EXINT_POLCFG2_FP5_Msk /*!< Falling edge event configuration bit on line 5 */ +#define EXINT_POLCFG2_FP6_Pos (6U) +#define EXINT_POLCFG2_FP6_Msk (0x1U << EXINT_POLCFG2_FP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG2_FP6 EXINT_POLCFG2_FP6_Msk /*!< Falling edge event configuration bit on line 6 */ +#define EXINT_POLCFG2_FP7_Pos (7U) +#define EXINT_POLCFG2_FP7_Msk (0x1U << EXINT_POLCFG2_FP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG2_FP7 EXINT_POLCFG2_FP7_Msk /*!< Falling edge event configuration bit on line 7 */ +#define EXINT_POLCFG2_FP8_Pos (8U) +#define EXINT_POLCFG2_FP8_Msk (0x1U << EXINT_POLCFG2_FP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG2_FP8 EXINT_POLCFG2_FP8_Msk /*!< Falling edge event configuration bit on line 8 */ +#define EXINT_POLCFG2_FP9_Pos (9U) +#define EXINT_POLCFG2_FP9_Msk (0x1U << EXINT_POLCFG2_FP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG2_FP9 EXINT_POLCFG2_FP9_Msk /*!< Falling edge event configuration bit on line 9 */ +#define EXINT_POLCFG2_FP10_Pos (10U) +#define EXINT_POLCFG2_FP10_Msk (0x1U << EXINT_POLCFG2_FP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG2_FP10 EXINT_POLCFG2_FP10_Msk /*!< Falling edge event configuration bit on line 10 */ +#define EXINT_POLCFG2_FP11_Pos (11U) +#define EXINT_POLCFG2_FP11_Msk (0x1U << EXINT_POLCFG2_FP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG2_FP11 EXINT_POLCFG2_FP11_Msk /*!< Falling edge event configuration bit on line 11 */ +#define EXINT_POLCFG2_FP12_Pos (12U) +#define EXINT_POLCFG2_FP12_Msk (0x1U << EXINT_POLCFG2_FP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG2_FP12 EXINT_POLCFG2_FP12_Msk /*!< Falling edge event configuration bit on line 12 */ +#define EXINT_POLCFG2_FP13_Pos (13U) +#define EXINT_POLCFG2_FP13_Msk (0x1U << EXINT_POLCFG2_FP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG2_FP13 EXINT_POLCFG2_FP13_Msk /*!< Falling edge event configuration bit on line 13 */ +#define EXINT_POLCFG2_FP14_Pos (14U) +#define EXINT_POLCFG2_FP14_Msk (0x1U << EXINT_POLCFG2_FP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG2_FP14 EXINT_POLCFG2_FP14_Msk /*!< Falling edge event configuration bit on line 14 */ +#define EXINT_POLCFG2_FP15_Pos (15U) +#define EXINT_POLCFG2_FP15_Msk (0x1U << EXINT_POLCFG2_FP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG2_FP15 EXINT_POLCFG2_FP15_Msk /*!< Falling edge event configuration bit on line 15 */ +#define EXINT_POLCFG2_FP16_Pos (16U) +#define EXINT_POLCFG2_FP16_Msk (0x1U << EXINT_POLCFG2_FP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG2_FP16 EXINT_POLCFG2_FP16_Msk /*!< Falling edge event configuration bit on line 16 */ +#define EXINT_POLCFG2_FP17_Pos (17U) +#define EXINT_POLCFG2_FP17_Msk (0x1U << EXINT_POLCFG2_FP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG2_FP17 EXINT_POLCFG2_FP17_Msk /*!< Falling edge event configuration bit on line 17 */ +#define EXINT_POLCFG2_FP18_Pos (18U) +#define EXINT_POLCFG2_FP18_Msk (0x1U << EXINT_POLCFG2_FP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG2_FP18 EXINT_POLCFG2_FP18_Msk /*!< Falling edge event configuration bit on line 18 */ +#define EXINT_POLCFG2_FP19_Pos (19U) +#define EXINT_POLCFG2_FP19_Msk (0x1U << EXINT_POLCFG2_FP19_Pos) /*!< 0x00080000 */ +#define EXINT_POLCFG2_FP19 EXINT_POLCFG2_FP19_Msk /*!< Falling edge event configuration bit on line 19 */ +#define EXINT_POLCFG2_FP20_Pos (20U) +#define EXINT_POLCFG2_FP20_Msk (0x1U << EXINT_POLCFG2_FP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG2_FP20 EXINT_POLCFG2_FP20_Msk /*!< Falling edge event configuration bit on line 20 */ +#define EXINT_POLCFG2_FP21_Pos (21U) +#define EXINT_POLCFG2_FP21_Msk (0x1U << EXINT_POLCFG2_FP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG2_FP21 EXINT_POLCFG2_FP21_Msk /*!< Falling edge event configuration bit on line 21 */ +#define EXINT_POLCFG2_FP22_Pos (22U) +#define EXINT_POLCFG2_FP22_Msk (0x1U << EXINT_POLCFG2_FP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG2_FP22 EXINT_POLCFG2_FP22_Msk /*!< Falling edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG2_POL0 EXINT_POLCFG2_FP0 +#define EXINT_POLCFG2_POL1 EXINT_POLCFG2_FP1 +#define EXINT_POLCFG2_POL2 EXINT_POLCFG2_FP2 +#define EXINT_POLCFG2_POL3 EXINT_POLCFG2_FP3 +#define EXINT_POLCFG2_POL4 EXINT_POLCFG2_FP4 +#define EXINT_POLCFG2_POL5 EXINT_POLCFG2_FP5 +#define EXINT_POLCFG2_POL6 EXINT_POLCFG2_FP6 +#define EXINT_POLCFG2_POL7 EXINT_POLCFG2_FP7 +#define EXINT_POLCFG2_POL8 EXINT_POLCFG2_FP8 +#define EXINT_POLCFG2_POL9 EXINT_POLCFG2_FP9 +#define EXINT_POLCFG2_POL10 EXINT_POLCFG2_FP10 +#define EXINT_POLCFG2_POL11 EXINT_POLCFG2_FP11 +#define EXINT_POLCFG2_POL12 EXINT_POLCFG2_FP12 +#define EXINT_POLCFG2_POL13 EXINT_POLCFG2_FP13 +#define EXINT_POLCFG2_POL14 EXINT_POLCFG2_FP14 +#define EXINT_POLCFG2_POL15 EXINT_POLCFG2_FP15 +#define EXINT_POLCFG2_POL16 EXINT_POLCFG2_FP16 +#define EXINT_POLCFG2_POL17 EXINT_POLCFG2_FP17 +#define EXINT_POLCFG2_POL18 EXINT_POLCFG2_FP18 +#define EXINT_POLCFG2_POL19 EXINT_POLCFG2_FP19 +#define EXINT_POLCFG2_POL20 EXINT_POLCFG2_FP20 +#define EXINT_POLCFG2_POL21 EXINT_POLCFG2_FP21 +#define EXINT_POLCFG2_POL22 EXINT_POLCFG2_FP22 + +/***************** Bit definition for EXINT_SWTRG register ******************/ +#define EXINT_SWTRG_SWT0_Pos (0U) +#define EXINT_SWTRG_SWT0_Msk (0x1U << EXINT_SWTRG_SWT0_Pos) /*!< 0x00000001 */ +#define EXINT_SWTRG_SWT0 EXINT_SWTRG_SWT0_Msk /*!< Software trigger on line 0 */ +#define EXINT_SWTRG_SWT1_Pos (1U) +#define EXINT_SWTRG_SWT1_Msk (0x1U << EXINT_SWTRG_SWT1_Pos) /*!< 0x00000002 */ +#define EXINT_SWTRG_SWT1 EXINT_SWTRG_SWT1_Msk /*!< Software trigger on line 1 */ +#define EXINT_SWTRG_SWT2_Pos (2U) +#define EXINT_SWTRG_SWT2_Msk (0x1U << EXINT_SWTRG_SWT2_Pos) /*!< 0x00000004 */ +#define EXINT_SWTRG_SWT2 EXINT_SWTRG_SWT2_Msk /*!< Software trigger on line 2 */ +#define EXINT_SWTRG_SWT3_Pos (3U) +#define EXINT_SWTRG_SWT3_Msk (0x1U << EXINT_SWTRG_SWT3_Pos) /*!< 0x00000008 */ +#define EXINT_SWTRG_SWT3 EXINT_SWTRG_SWT3_Msk /*!< Software trigger on line 3 */ +#define EXINT_SWTRG_SWT4_Pos (4U) +#define EXINT_SWTRG_SWT4_Msk (0x1U << EXINT_SWTRG_SWT4_Pos) /*!< 0x00000010 */ +#define EXINT_SWTRG_SWT4 EXINT_SWTRG_SWT4_Msk /*!< Software trigger on line 4 */ +#define EXINT_SWTRG_SWT5_Pos (5U) +#define EXINT_SWTRG_SWT5_Msk (0x1U << EXINT_SWTRG_SWT5_Pos) /*!< 0x00000020 */ +#define EXINT_SWTRG_SWT5 EXINT_SWTRG_SWT5_Msk /*!< Software trigger on line 5 */ +#define EXINT_SWTRG_SWT6_Pos (6U) +#define EXINT_SWTRG_SWT6_Msk (0x1U << EXINT_SWTRG_SWT6_Pos) /*!< 0x00000040 */ +#define EXINT_SWTRG_SWT6 EXINT_SWTRG_SWT6_Msk /*!< Software trigger on line 6 */ +#define EXINT_SWTRG_SWT7_Pos (7U) +#define EXINT_SWTRG_SWT7_Msk (0x1U << EXINT_SWTRG_SWT7_Pos) /*!< 0x00000080 */ +#define EXINT_SWTRG_SWT7 EXINT_SWTRG_SWT7_Msk /*!< Software trigger on line 7 */ +#define EXINT_SWTRG_SWT8_Pos (8U) +#define EXINT_SWTRG_SWT8_Msk (0x1U << EXINT_SWTRG_SWT8_Pos) /*!< 0x00000100 */ +#define EXINT_SWTRG_SWT8 EXINT_SWTRG_SWT8_Msk /*!< Software trigger on line 8 */ +#define EXINT_SWTRG_SWT9_Pos (9U) +#define EXINT_SWTRG_SWT9_Msk (0x1U << EXINT_SWTRG_SWT9_Pos) /*!< 0x00000200 */ +#define EXINT_SWTRG_SWT9 EXINT_SWTRG_SWT9_Msk /*!< Software trigger on line 9 */ +#define EXINT_SWTRG_SWT10_Pos (10U) +#define EXINT_SWTRG_SWT10_Msk (0x1U << EXINT_SWTRG_SWT10_Pos) /*!< 0x00000400 */ +#define EXINT_SWTRG_SWT10 EXINT_SWTRG_SWT10_Msk /*!< Software trigger on line 10 */ +#define EXINT_SWTRG_SWT11_Pos (11U) +#define EXINT_SWTRG_SWT11_Msk (0x1U << EXINT_SWTRG_SWT11_Pos) /*!< 0x00000800 */ +#define EXINT_SWTRG_SWT11 EXINT_SWTRG_SWT11_Msk /*!< Software trigger on line 11 */ +#define EXINT_SWTRG_SWT12_Pos (12U) +#define EXINT_SWTRG_SWT12_Msk (0x1U << EXINT_SWTRG_SWT12_Pos) /*!< 0x00001000 */ +#define EXINT_SWTRG_SWT12 EXINT_SWTRG_SWT12_Msk /*!< Software trigger on line 12 */ +#define EXINT_SWTRG_SWT13_Pos (13U) +#define EXINT_SWTRG_SWT13_Msk (0x1U << EXINT_SWTRG_SWT13_Pos) /*!< 0x00002000 */ +#define EXINT_SWTRG_SWT13 EXINT_SWTRG_SWT13_Msk /*!< Software trigger on line 13 */ +#define EXINT_SWTRG_SWT14_Pos (14U) +#define EXINT_SWTRG_SWT14_Msk (0x1U << EXINT_SWTRG_SWT14_Pos) /*!< 0x00004000 */ +#define EXINT_SWTRG_SWT14 EXINT_SWTRG_SWT14_Msk /*!< Software trigger on line 14 */ +#define EXINT_SWTRG_SWT15_Pos (15U) +#define EXINT_SWTRG_SWT15_Msk (0x1U << EXINT_SWTRG_SWT15_Pos) /*!< 0x00008000 */ +#define EXINT_SWTRG_SWT15 EXINT_SWTRG_SWT15_Msk /*!< Software trigger on line 15 */ +#define EXINT_SWTRG_SWT16_Pos (16U) +#define EXINT_SWTRG_SWT16_Msk (0x1U << EXINT_SWTRG_SWT16_Pos) /*!< 0x00010000 */ +#define EXINT_SWTRG_SWT16 EXINT_SWTRG_SWT16_Msk /*!< Software trigger on line 16 */ +#define EXINT_SWTRG_SWT17_Pos (17U) +#define EXINT_SWTRG_SWT17_Msk (0x1U << EXINT_SWTRG_SWT17_Pos) /*!< 0x00020000 */ +#define EXINT_SWTRG_SWT17 EXINT_SWTRG_SWT17_Msk /*!< Software trigger on line 17 */ +#define EXINT_SWTRG_SWT18_Pos (18U) +#define EXINT_SWTRG_SWT18_Msk (0x1U << EXINT_SWTRG_SWT18_Pos) /*!< 0x00040000 */ +#define EXINT_SWTRG_SWT18 EXINT_SWTRG_SWT18_Msk /*!< Software trigger on line 18 */ +#define EXINT_SWTRG_SWT19_Pos (19U) +#define EXINT_SWTRG_SWT19_Msk (0x1U << EXINT_SWTRG_SWT19_Pos) /*!< 0x00080000 */ +#define EXINT_SWTRG_SWT19 EXINT_SWTRG_SWT19_Msk /*!< Software trigger on line 19 */ +#define EXINT_SWTRG_SWT20_Pos (20U) +#define EXINT_SWTRG_SWT20_Msk (0x1U << EXINT_SWTRG_SWT20_Pos) /*!< 0x00100000 */ +#define EXINT_SWTRG_SWT20 EXINT_SWTRG_SWT20_Msk /*!< Software trigger on line 20 */ +#define EXINT_SWTRG_SWT21_Pos (21U) +#define EXINT_SWTRG_SWT21_Msk (0x1U << EXINT_SWTRG_SWT21_Pos) /*!< 0x00200000 */ +#define EXINT_SWTRG_SWT21 EXINT_SWTRG_SWT21_Msk /*!< Software trigger on line 21 */ +#define EXINT_SWTRG_SWT22_Pos (22U) +#define EXINT_SWTRG_SWT22_Msk (0x1U << EXINT_SWTRG_SWT22_Pos) /*!< 0x00400000 */ +#define EXINT_SWTRG_SWT22 EXINT_SWTRG_SWT22_Msk /*!< Software trigger on line 22 */ + +/* References Defines */ +#define EXINT_SWTRG_SW0 EXINT_SWTRG_SWT0 +#define EXINT_SWTRG_SW1 EXINT_SWTRG_SWT1 +#define EXINT_SWTRG_SW2 EXINT_SWTRG_SWT2 +#define EXINT_SWTRG_SW3 EXINT_SWTRG_SWT3 +#define EXINT_SWTRG_SW4 EXINT_SWTRG_SWT4 +#define EXINT_SWTRG_SW5 EXINT_SWTRG_SWT5 +#define EXINT_SWTRG_SW6 EXINT_SWTRG_SWT6 +#define EXINT_SWTRG_SW7 EXINT_SWTRG_SWT7 +#define EXINT_SWTRG_SW8 EXINT_SWTRG_SWT8 +#define EXINT_SWTRG_SW9 EXINT_SWTRG_SWT9 +#define EXINT_SWTRG_SW10 EXINT_SWTRG_SWT10 +#define EXINT_SWTRG_SW11 EXINT_SWTRG_SWT11 +#define EXINT_SWTRG_SW12 EXINT_SWTRG_SWT12 +#define EXINT_SWTRG_SW13 EXINT_SWTRG_SWT13 +#define EXINT_SWTRG_SW14 EXINT_SWTRG_SWT14 +#define EXINT_SWTRG_SW15 EXINT_SWTRG_SWT15 +#define EXINT_SWTRG_SW16 EXINT_SWTRG_SWT16 +#define EXINT_SWTRG_SW17 EXINT_SWTRG_SWT17 +#define EXINT_SWTRG_SW18 EXINT_SWTRG_SWT18 +#define EXINT_SWTRG_SW19 EXINT_SWTRG_SWT19 +#define EXINT_SWTRG_SW20 EXINT_SWTRG_SWT20 +#define EXINT_SWTRG_SW21 EXINT_SWTRG_SWT21 +#define EXINT_SWTRG_SW22 EXINT_SWTRG_SWT22 + +/***************** Bit definition for EXINT_INTSTS register *****************/ +#define EXINT_INTSTS_LINE0_Pos (0U) +#define EXINT_INTSTS_LINE0_Msk (0x1U << EXINT_INTSTS_LINE0_Pos) /*!< 0x00000001 */ +#define EXINT_INTSTS_LINE0 EXINT_INTSTS_LINE0_Msk /*!< Status bit for line 0 */ +#define EXINT_INTSTS_LINE1_Pos (1U) +#define EXINT_INTSTS_LINE1_Msk (0x1U << EXINT_INTSTS_LINE1_Pos) /*!< 0x00000002 */ +#define EXINT_INTSTS_LINE1 EXINT_INTSTS_LINE1_Msk /*!< Status bit for line 1 */ +#define EXINT_INTSTS_LINE2_Pos (2U) +#define EXINT_INTSTS_LINE2_Msk (0x1U << EXINT_INTSTS_LINE2_Pos) /*!< 0x00000004 */ +#define EXINT_INTSTS_LINE2 EXINT_INTSTS_LINE2_Msk /*!< Status bit for line 2 */ +#define EXINT_INTSTS_LINE3_Pos (3U) +#define EXINT_INTSTS_LINE3_Msk (0x1U << EXINT_INTSTS_LINE3_Pos) /*!< 0x00000008 */ +#define EXINT_INTSTS_LINE3 EXINT_INTSTS_LINE3_Msk /*!< Status bit for line 3 */ +#define EXINT_INTSTS_LINE4_Pos (4U) +#define EXINT_INTSTS_LINE4_Msk (0x1U << EXINT_INTSTS_LINE4_Pos) /*!< 0x00000010 */ +#define EXINT_INTSTS_LINE4 EXINT_INTSTS_LINE4_Msk /*!< Status bit for line 4 */ +#define EXINT_INTSTS_LINE5_Pos (5U) +#define EXINT_INTSTS_LINE5_Msk (0x1U << EXINT_INTSTS_LINE5_Pos) /*!< 0x00000020 */ +#define EXINT_INTSTS_LINE5 EXINT_INTSTS_LINE5_Msk /*!< Status bit for line 5 */ +#define EXINT_INTSTS_LINE6_Pos (6U) +#define EXINT_INTSTS_LINE6_Msk (0x1U << EXINT_INTSTS_LINE6_Pos) /*!< 0x00000040 */ +#define EXINT_INTSTS_LINE6 EXINT_INTSTS_LINE6_Msk /*!< Status bit for line 6 */ +#define EXINT_INTSTS_LINE7_Pos (7U) +#define EXINT_INTSTS_LINE7_Msk (0x1U << EXINT_INTSTS_LINE7_Pos) /*!< 0x00000080 */ +#define EXINT_INTSTS_LINE7 EXINT_INTSTS_LINE7_Msk /*!< Status bit for line 7 */ +#define EXINT_INTSTS_LINE8_Pos (8U) +#define EXINT_INTSTS_LINE8_Msk (0x1U << EXINT_INTSTS_LINE8_Pos) /*!< 0x00000100 */ +#define EXINT_INTSTS_LINE8 EXINT_INTSTS_LINE8_Msk /*!< Status bit for line 8 */ +#define EXINT_INTSTS_LINE9_Pos (9U) +#define EXINT_INTSTS_LINE9_Msk (0x1U << EXINT_INTSTS_LINE9_Pos) /*!< 0x00000200 */ +#define EXINT_INTSTS_LINE9 EXINT_INTSTS_LINE9_Msk /*!< Status bit for line 9 */ +#define EXINT_INTSTS_LINE10_Pos (10U) +#define EXINT_INTSTS_LINE10_Msk (0x1U << EXINT_INTSTS_LINE10_Pos) /*!< 0x00000400 */ +#define EXINT_INTSTS_LINE10 EXINT_INTSTS_LINE10_Msk /*!< Status bit for line 10 */ +#define EXINT_INTSTS_LINE11_Pos (11U) +#define EXINT_INTSTS_LINE11_Msk (0x1U << EXINT_INTSTS_LINE11_Pos) /*!< 0x00000800 */ +#define EXINT_INTSTS_LINE11 EXINT_INTSTS_LINE11_Msk /*!< Status bit for line 11 */ +#define EXINT_INTSTS_LINE12_Pos (12U) +#define EXINT_INTSTS_LINE12_Msk (0x1U << EXINT_INTSTS_LINE12_Pos) /*!< 0x00001000 */ +#define EXINT_INTSTS_LINE12 EXINT_INTSTS_LINE12_Msk /*!< Status bit for line 12 */ +#define EXINT_INTSTS_LINE13_Pos (13U) +#define EXINT_INTSTS_LINE13_Msk (0x1U << EXINT_INTSTS_LINE13_Pos) /*!< 0x00002000 */ +#define EXINT_INTSTS_LINE13 EXINT_INTSTS_LINE13_Msk /*!< Status bit for line 13 */ +#define EXINT_INTSTS_LINE14_Pos (14U) +#define EXINT_INTSTS_LINE14_Msk (0x1U << EXINT_INTSTS_LINE14_Pos) /*!< 0x00004000 */ +#define EXINT_INTSTS_LINE14 EXINT_INTSTS_LINE14_Msk /*!< Status bit for line 14 */ +#define EXINT_INTSTS_LINE15_Pos (15U) +#define EXINT_INTSTS_LINE15_Msk (0x1U << EXINT_INTSTS_LINE15_Pos) /*!< 0x00008000 */ +#define EXINT_INTSTS_LINE15 EXINT_INTSTS_LINE15_Msk /*!< Status bit for line 15 */ +#define EXINT_INTSTS_LINE16_Pos (16U) +#define EXINT_INTSTS_LINE16_Msk (0x1U << EXINT_INTSTS_LINE16_Pos) /*!< 0x00010000 */ +#define EXINT_INTSTS_LINE16 EXINT_INTSTS_LINE16_Msk /*!< Status bit for line 16 */ +#define EXINT_INTSTS_LINE17_Pos (17U) +#define EXINT_INTSTS_LINE17_Msk (0x1U << EXINT_INTSTS_LINE17_Pos) /*!< 0x00020000 */ +#define EXINT_INTSTS_LINE17 EXINT_INTSTS_LINE17_Msk /*!< Status bit for line 17 */ +#define EXINT_INTSTS_LINE18_Pos (18U) +#define EXINT_INTSTS_LINE18_Msk (0x1U << EXINT_INTSTS_LINE18_Pos) /*!< 0x00040000 */ +#define EXINT_INTSTS_LINE18 EXINT_INTSTS_LINE18_Msk /*!< Status bit for line 18 */ +#define EXINT_INTSTS_LINE19_Pos (19U) +#define EXINT_INTSTS_LINE19_Msk (0x1U << EXINT_INTSTS_LINE19_Pos) /*!< 0x00080000 */ +#define EXINT_INTSTS_LINE19 EXINT_INTSTS_LINE19_Msk /*!< Status bit for line 19 */ +#define EXINT_INTSTS_LINE20_Pos (20U) +#define EXINT_INTSTS_LINE20_Msk (0x1U << EXINT_INTSTS_LINE20_Pos) /*!< 0x00100000 */ +#define EXINT_INTSTS_LINE20 EXINT_INTSTS_LINE20_Msk /*!< Status bit for line 20 */ +#define EXINT_INTSTS_LINE21_Pos (21U) +#define EXINT_INTSTS_LINE21_Msk (0x1U << EXINT_INTSTS_LINE21_Pos) /*!< 0x00200000 */ +#define EXINT_INTSTS_LINE21 EXINT_INTSTS_LINE21_Msk /*!< Status bit for line 21 */ +#define EXINT_INTSTS_LINE22_Pos (22U) +#define EXINT_INTSTS_LINE22_Msk (0x1U << EXINT_INTSTS_LINE22_Pos) /*!< 0x00400000 */ +#define EXINT_INTSTS_LINE22 EXINT_INTSTS_LINE22_Msk /*!< Status bit for line 22 */ + +/* References Defines */ +#define EXINT_INTSTS_INT0 EXINT_INTSTS_LINE0 +#define EXINT_INTSTS_INT1 EXINT_INTSTS_LINE1 +#define EXINT_INTSTS_INT2 EXINT_INTSTS_LINE2 +#define EXINT_INTSTS_INT3 EXINT_INTSTS_LINE3 +#define EXINT_INTSTS_INT4 EXINT_INTSTS_LINE4 +#define EXINT_INTSTS_INT5 EXINT_INTSTS_LINE5 +#define EXINT_INTSTS_INT6 EXINT_INTSTS_LINE6 +#define EXINT_INTSTS_INT7 EXINT_INTSTS_LINE7 +#define EXINT_INTSTS_INT8 EXINT_INTSTS_LINE8 +#define EXINT_INTSTS_INT9 EXINT_INTSTS_LINE9 +#define EXINT_INTSTS_INT10 EXINT_INTSTS_LINE10 +#define EXINT_INTSTS_INT11 EXINT_INTSTS_LINE11 +#define EXINT_INTSTS_INT12 EXINT_INTSTS_LINE12 +#define EXINT_INTSTS_INT13 EXINT_INTSTS_LINE13 +#define EXINT_INTSTS_INT14 EXINT_INTSTS_LINE14 +#define EXINT_INTSTS_INT15 EXINT_INTSTS_LINE15 +#define EXINT_INTSTS_INT16 EXINT_INTSTS_LINE16 +#define EXINT_INTSTS_INT17 EXINT_INTSTS_LINE17 +#define EXINT_INTSTS_INT18 EXINT_INTSTS_LINE18 +#define EXINT_INTSTS_INT19 EXINT_INTSTS_LINE19 +#define EXINT_INTSTS_INT20 EXINT_INTSTS_LINE20 +#define EXINT_INTSTS_INT21 EXINT_INTSTS_LINE21 +#define EXINT_INTSTS_INT22 EXINT_INTSTS_LINE22 + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_STS register ********************/ +#define DMA_STS_GF1_Pos (0U) +#define DMA_STS_GF1_Msk (0x1U << DMA_STS_GF1_Pos) /*!< 0x00000001 */ +#define DMA_STS_GF1 DMA_STS_GF1_Msk /*!< Channel 1 global event flag */ +#define DMA_STS_FDTF1_Pos (1U) +#define DMA_STS_FDTF1_Msk (0x1U << DMA_STS_FDTF1_Pos) /*!< 0x00000002 */ +#define DMA_STS_FDTF1 DMA_STS_FDTF1_Msk /*!< Channel 1 transfer complete event flag */ +#define DMA_STS_HDTF1_Pos (2U) +#define DMA_STS_HDTF1_Msk (0x1U << DMA_STS_HDTF1_Pos) /*!< 0x00000004 */ +#define DMA_STS_HDTF1 DMA_STS_HDTF1_Msk /*!< Channel 1 half transfer event flag */ +#define DMA_STS_DTERRF1_Pos (3U) +#define DMA_STS_DTERRF1_Msk (0x1U << DMA_STS_DTERRF1_Pos) /*!< 0x00000008 */ +#define DMA_STS_DTERRF1 DMA_STS_DTERRF1_Msk /*!< Channel 1 transfer error event flag */ +#define DMA_STS_GF2_Pos (4U) +#define DMA_STS_GF2_Msk (0x1U << DMA_STS_GF2_Pos) /*!< 0x00000010 */ +#define DMA_STS_GF2 DMA_STS_GF2_Msk /*!< Channel 2 global event flag */ +#define DMA_STS_FDTF2_Pos (5U) +#define DMA_STS_FDTF2_Msk (0x1U << DMA_STS_FDTF2_Pos) /*!< 0x00000020 */ +#define DMA_STS_FDTF2 DMA_STS_FDTF2_Msk /*!< Channel 2 transfer complete event flag */ +#define DMA_STS_HDTF2_Pos (6U) +#define DMA_STS_HDTF2_Msk (0x1U << DMA_STS_HDTF2_Pos) /*!< 0x00000040 */ +#define DMA_STS_HDTF2 DMA_STS_HDTF2_Msk /*!< Channel 2 half transfer event flag */ +#define DMA_STS_DTERRF2_Pos (7U) +#define DMA_STS_DTERRF2_Msk (0x1U << DMA_STS_DTERRF2_Pos) /*!< 0x00000080 */ +#define DMA_STS_DTERRF2 DMA_STS_DTERRF2_Msk /*!< Channel 2 transfer error event flag */ +#define DMA_STS_GF3_Pos (8U) +#define DMA_STS_GF3_Msk (0x1U << DMA_STS_GF3_Pos) /*!< 0x00000100 */ +#define DMA_STS_GF3 DMA_STS_GF3_Msk /*!< Channel 3 global event flag */ +#define DMA_STS_FDTF3_Pos (9U) +#define DMA_STS_FDTF3_Msk (0x1U << DMA_STS_FDTF3_Pos) /*!< 0x00000200 */ +#define DMA_STS_FDTF3 DMA_STS_FDTF3_Msk /*!< Channel 3 transfer complete event flag */ +#define DMA_STS_HDTF3_Pos (10U) +#define DMA_STS_HDTF3_Msk (0x1U << DMA_STS_HDTF3_Pos) /*!< 0x00000400 */ +#define DMA_STS_HDTF3 DMA_STS_HDTF3_Msk /*!< Channel 3 half transfer event flag */ +#define DMA_STS_DTERRF3_Pos (11U) +#define DMA_STS_DTERRF3_Msk (0x1U << DMA_STS_DTERRF3_Pos) /*!< 0x00000800 */ +#define DMA_STS_DTERRF3 DMA_STS_DTERRF3_Msk /*!< Channel 3 transfer error event flag */ +#define DMA_STS_GF4_Pos (12U) +#define DMA_STS_GF4_Msk (0x1U << DMA_STS_GF4_Pos) /*!< 0x00001000 */ +#define DMA_STS_GF4 DMA_STS_GF4_Msk /*!< Channel 4 global event flag */ +#define DMA_STS_FDTF4_Pos (13U) +#define DMA_STS_FDTF4_Msk (0x1U << DMA_STS_FDTF4_Pos) /*!< 0x00002000 */ +#define DMA_STS_FDTF4 DMA_STS_FDTF4_Msk /*!< Channel 4 transfer complete event flag */ +#define DMA_STS_HDTF4_Pos (14U) +#define DMA_STS_HDTF4_Msk (0x1U << DMA_STS_HDTF4_Pos) /*!< 0x00004000 */ +#define DMA_STS_HDTF4 DMA_STS_HDTF4_Msk /*!< Channel 4 half transfer event flag */ +#define DMA_STS_DTERRF4_Pos (15U) +#define DMA_STS_DTERRF4_Msk (0x1U << DMA_STS_DTERRF4_Pos) /*!< 0x00008000 */ +#define DMA_STS_DTERRF4 DMA_STS_DTERRF4_Msk /*!< Channel 4 transfer error event flag */ +#define DMA_STS_GF5_Pos (16U) +#define DMA_STS_GF5_Msk (0x1U << DMA_STS_GF5_Pos) /*!< 0x00010000 */ +#define DMA_STS_GF5 DMA_STS_GF5_Msk /*!< Channel 5 global event flag */ +#define DMA_STS_FDTF5_Pos (17U) +#define DMA_STS_FDTF5_Msk (0x1U << DMA_STS_FDTF5_Pos) /*!< 0x00020000 */ +#define DMA_STS_FDTF5 DMA_STS_FDTF5_Msk /*!< Channel 5 transfer complete event flag */ +#define DMA_STS_HDTF5_Pos (18U) +#define DMA_STS_HDTF5_Msk (0x1U << DMA_STS_HDTF5_Pos) /*!< 0x00040000 */ +#define DMA_STS_HDTF5 DMA_STS_HDTF5_Msk /*!< Channel 5 half transfer event flag */ +#define DMA_STS_DTERRF5_Pos (19U) +#define DMA_STS_DTERRF5_Msk (0x1U << DMA_STS_DTERRF5_Pos) /*!< 0x00080000 */ +#define DMA_STS_DTERRF5 DMA_STS_DTERRF5_Msk /*!< Channel 5 transfer error event flag */ +#define DMA_STS_GF6_Pos (20U) +#define DMA_STS_GF6_Msk (0x1U << DMA_STS_GF6_Pos) /*!< 0x00100000 */ +#define DMA_STS_GF6 DMA_STS_GF6_Msk /*!< Channel 6 global event flag */ +#define DMA_STS_FDTF6_Pos (21U) +#define DMA_STS_FDTF6_Msk (0x1U << DMA_STS_FDTF6_Pos) /*!< 0x00200000 */ +#define DMA_STS_FDTF6 DMA_STS_FDTF6_Msk /*!< Channel 6 transfer complete event flag */ +#define DMA_STS_HDTF6_Pos (22U) +#define DMA_STS_HDTF6_Msk (0x1U << DMA_STS_HDTF6_Pos) /*!< 0x00400000 */ +#define DMA_STS_HDTF6 DMA_STS_HDTF6_Msk /*!< Channel 6 half transfer event flag */ +#define DMA_STS_DTERRF6_Pos (23U) +#define DMA_STS_DTERRF6_Msk (0x1U << DMA_STS_DTERRF6_Pos) /*!< 0x00800000 */ +#define DMA_STS_DTERRF6 DMA_STS_DTERRF6_Msk /*!< Channel 6 transfer error event flag */ +#define DMA_STS_GF7_Pos (24U) +#define DMA_STS_GF7_Msk (0x1U << DMA_STS_GF7_Pos) /*!< 0x01000000 */ +#define DMA_STS_GF7 DMA_STS_GF7_Msk /*!< Channel 7 global event flag */ +#define DMA_STS_FDTF7_Pos (25U) +#define DMA_STS_FDTF7_Msk (0x1U << DMA_STS_FDTF7_Pos) /*!< 0x02000000 */ +#define DMA_STS_FDTF7 DMA_STS_FDTF7_Msk /*!< Channel 7 transfer complete event flag */ +#define DMA_STS_HDTF7_Pos (26U) +#define DMA_STS_HDTF7_Msk (0x1U << DMA_STS_HDTF7_Pos) /*!< 0x04000000 */ +#define DMA_STS_HDTF7 DMA_STS_HDTF7_Msk /*!< Channel 7 half transfer event flag */ +#define DMA_STS_DTERRF7_Pos (27U) +#define DMA_STS_DTERRF7_Msk (0x1U << DMA_STS_DTERRF7_Pos) /*!< 0x08000000 */ +#define DMA_STS_DTERRF7 DMA_STS_DTERRF7_Msk /*!< Channel 7 transfer error event flag */ + +/******************* Bit definition for DMA_CLR register ********************/ +#define DMA_CLR_GFC1_Pos (0U) +#define DMA_CLR_GFC1_Msk (0x1U << DMA_CLR_GFC1_Pos) /*!< 0x00000001 */ +#define DMA_CLR_GFC1 DMA_CLR_GFC1_Msk /*!< Channel 1 global interrupt flag clear */ +#define DMA_CLR_FDTFC1_Pos (1U) +#define DMA_CLR_FDTFC1_Msk (0x1U << DMA_CLR_FDTFC1_Pos) /*!< 0x00000002 */ +#define DMA_CLR_FDTFC1 DMA_CLR_FDTFC1_Msk /*!< Channel 1 transfer complete flag clear */ +#define DMA_CLR_HDTFC1_Pos (2U) +#define DMA_CLR_HDTFC1_Msk (0x1U << DMA_CLR_HDTFC1_Pos) /*!< 0x00000004 */ +#define DMA_CLR_HDTFC1 DMA_CLR_HDTFC1_Msk /*!< Channel 1 half transfer flag clear */ +#define DMA_CLR_DTERRFC1_Pos (3U) +#define DMA_CLR_DTERRFC1_Msk (0x1U << DMA_CLR_DTERRFC1_Pos) /*!< 0x00000008 */ +#define DMA_CLR_DTERRFC1 DMA_CLR_DTERRFC1_Msk /*!< Channel 1 data transfer error flag clear */ +#define DMA_CLR_GFC2_Pos (4U) +#define DMA_CLR_GFC2_Msk (0x1U << DMA_CLR_GFC2_Pos) /*!< 0x00000010 */ +#define DMA_CLR_GFC2 DMA_CLR_GFC2_Msk /*!< Channel 2 global interrupt flag clear */ +#define DMA_CLR_FDTFC2_Pos (5U) +#define DMA_CLR_FDTFC2_Msk (0x1U << DMA_CLR_FDTFC2_Pos) /*!< 0x00000020 */ +#define DMA_CLR_FDTFC2 DMA_CLR_FDTFC2_Msk /*!< Channel 2 transfer complete flag clear */ +#define DMA_CLR_HDTFC2_Pos (6U) +#define DMA_CLR_HDTFC2_Msk (0x1U << DMA_CLR_HDTFC2_Pos) /*!< 0x00000040 */ +#define DMA_CLR_HDTFC2 DMA_CLR_HDTFC2_Msk /*!< Channel 2 half transfer flag clear */ +#define DMA_CLR_DTERRFC2_Pos (7U) +#define DMA_CLR_DTERRFC2_Msk (0x1U << DMA_CLR_DTERRFC2_Pos) /*!< 0x00000080 */ +#define DMA_CLR_DTERRFC2 DMA_CLR_DTERRFC2_Msk /*!< Channel 2 data transfer error flag clear */ +#define DMA_CLR_GFC3_Pos (8U) +#define DMA_CLR_GFC3_Msk (0x1U << DMA_CLR_GFC3_Pos) /*!< 0x00000100 */ +#define DMA_CLR_GFC3 DMA_CLR_GFC3_Msk /*!< Channel 3 global interrupt flag clear */ +#define DMA_CLR_FDTFC3_Pos (9U) +#define DMA_CLR_FDTFC3_Msk (0x1U << DMA_CLR_FDTFC3_Pos) /*!< 0x00000200 */ +#define DMA_CLR_FDTFC3 DMA_CLR_FDTFC3_Msk /*!< Channel 3 transfer complete flag clear */ +#define DMA_CLR_HDTFC3_Pos (10U) +#define DMA_CLR_HDTFC3_Msk (0x1U << DMA_CLR_HDTFC3_Pos) /*!< 0x00000400 */ +#define DMA_CLR_HDTFC3 DMA_CLR_HDTFC3_Msk /*!< Channel 3 half transfer flag clear */ +#define DMA_CLR_DTERRFC3_Pos (11U) +#define DMA_CLR_DTERRFC3_Msk (0x1U << DMA_CLR_DTERRFC3_Pos) /*!< 0x00000800 */ +#define DMA_CLR_DTERRFC3 DMA_CLR_DTERRFC3_Msk /*!< Channel 3 data transfer error flag clear */ +#define DMA_CLR_GFC4_Pos (12U) +#define DMA_CLR_GFC4_Msk (0x1U << DMA_CLR_GFC4_Pos) /*!< 0x00001000 */ +#define DMA_CLR_GFC4 DMA_CLR_GFC4_Msk /*!< Channel 4 global interrupt flag clear */ +#define DMA_CLR_FDTFC4_Pos (13U) +#define DMA_CLR_FDTFC4_Msk (0x1U << DMA_CLR_FDTFC4_Pos) /*!< 0x00002000 */ +#define DMA_CLR_FDTFC4 DMA_CLR_FDTFC4_Msk /*!< Channel 4 transfer complete flag clear */ +#define DMA_CLR_HDTFC4_Pos (14U) +#define DMA_CLR_HDTFC4_Msk (0x1U << DMA_CLR_HDTFC4_Pos) /*!< 0x00004000 */ +#define DMA_CLR_HDTFC4 DMA_CLR_HDTFC4_Msk /*!< Channel 4 half transfer flag clear */ +#define DMA_CLR_DTERRFC4_Pos (15U) +#define DMA_CLR_DTERRFC4_Msk (0x1U << DMA_CLR_DTERRFC4_Pos) /*!< 0x00008000 */ +#define DMA_CLR_DTERRFC4 DMA_CLR_DTERRFC4_Msk /*!< Channel 4 data transfer error flag clear */ +#define DMA_CLR_GFC5_Pos (16U) +#define DMA_CLR_GFC5_Msk (0x1U << DMA_CLR_GFC5_Pos) /*!< 0x00010000 */ +#define DMA_CLR_GFC5 DMA_CLR_GFC5_Msk /*!< Channel 5 global interrupt flag clear */ +#define DMA_CLR_FDTFC5_Pos (17U) +#define DMA_CLR_FDTFC5_Msk (0x1U << DMA_CLR_FDTFC5_Pos) /*!< 0x00020000 */ +#define DMA_CLR_FDTFC5 DMA_CLR_FDTFC5_Msk /*!< Channel 5 transfer complete flag clear */ +#define DMA_CLR_HDTFC5_Pos (18U) +#define DMA_CLR_HDTFC5_Msk (0x1U << DMA_CLR_HDTFC5_Pos) /*!< 0x00040000 */ +#define DMA_CLR_HDTFC5 DMA_CLR_HDTFC5_Msk /*!< Channel 5 half transfer flag clear */ +#define DMA_CLR_DTERRFC5_Pos (19U) +#define DMA_CLR_DTERRFC5_Msk (0x1U << DMA_CLR_DTERRFC5_Pos) /*!< 0x00080000 */ +#define DMA_CLR_DTERRFC5 DMA_CLR_DTERRFC5_Msk /*!< Channel 5 data transfer error flag clear */ +#define DMA_CLR_GFC6_Pos (20U) +#define DMA_CLR_GFC6_Msk (0x1U << DMA_CLR_GFC6_Pos) /*!< 0x00100000 */ +#define DMA_CLR_GFC6 DMA_CLR_GFC6_Msk /*!< Channel 6 global interrupt flag clear */ +#define DMA_CLR_FDTFC6_Pos (21U) +#define DMA_CLR_FDTFC6_Msk (0x1U << DMA_CLR_FDTFC6_Pos) /*!< 0x00200000 */ +#define DMA_CLR_FDTFC6 DMA_CLR_FDTFC6_Msk /*!< Channel 6 transfer complete flag clear */ +#define DMA_CLR_HDTFC6_Pos (22U) +#define DMA_CLR_HDTFC6_Msk (0x1U << DMA_CLR_HDTFC6_Pos) /*!< 0x00400000 */ +#define DMA_CLR_HDTFC6 DMA_CLR_HDTFC6_Msk /*!< Channel 6 half transfer flag clear */ +#define DMA_CLR_DTERRFC6_Pos (23U) +#define DMA_CLR_DTERRFC6_Msk (0x1U << DMA_CLR_DTERRFC6_Pos) /*!< 0x00800000 */ +#define DMA_CLR_DTERRFC6 DMA_CLR_DTERRFC6_Msk /*!< Channel 6 data transfer error flag clear */ +#define DMA_CLR_GFC7_Pos (24U) +#define DMA_CLR_GFC7_Msk (0x1U << DMA_CLR_GFC7_Pos) /*!< 0x01000000 */ +#define DMA_CLR_GFC7 DMA_CLR_GFC7_Msk /*!< Channel 7 global interrupt flag clear */ +#define DMA_CLR_FDTFC7_Pos (25U) +#define DMA_CLR_FDTFC7_Msk (0x1U << DMA_CLR_FDTFC7_Pos) /*!< 0x02000000 */ +#define DMA_CLR_FDTFC7 DMA_CLR_FDTFC7_Msk /*!< Channel 7 transfer complete flag clear */ +#define DMA_CLR_HDTFC7_Pos (26U) +#define DMA_CLR_HDTFC7_Msk (0x1U << DMA_CLR_HDTFC7_Pos) /*!< 0x04000000 */ +#define DMA_CLR_HDTFC7 DMA_CLR_HDTFC7_Msk /*!< Channel 7 half transfer flag clear */ +#define DMA_CLR_DTERRFC7_Pos (27U) +#define DMA_CLR_DTERRFC7_Msk (0x1U << DMA_CLR_DTERRFC7_Pos) /*!< 0x08000000 */ +#define DMA_CLR_DTERRFC7 DMA_CLR_DTERRFC7_Msk /*!< Channel 7 data transfer error flag clear */ + +/****************** Bit definition for DMA_CCTRL register *******************/ +#define DMA_CCTRL_CHEN_Pos (0U) +#define DMA_CCTRL_CHEN_Msk (0x1U << DMA_CCTRL_CHEN_Pos) /*!< 0x00000001 */ +#define DMA_CCTRL_CHEN DMA_CCTRL_CHEN_Msk /*!< Channel enable */ +#define DMA_CCTRL_FDTIEN_Pos (1U) +#define DMA_CCTRL_FDTIEN_Msk (0x1U << DMA_CCTRL_FDTIEN_Pos) /*!< 0x00000002 */ +#define DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCTRL_HDTIEN_Pos (2U) +#define DMA_CCTRL_HDTIEN_Msk (0x1U << DMA_CCTRL_HDTIEN_Pos) /*!< 0x00000004 */ +#define DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN_Msk /*!< Half-transfer interrupt enable */ +#define DMA_CCTRL_DTERRIEN_Pos (3U) +#define DMA_CCTRL_DTERRIEN_Msk (0x1U << DMA_CCTRL_DTERRIEN_Pos) /*!< 0x00000008 */ +#define DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCTRL_DTD_Pos (4U) +#define DMA_CCTRL_DTD_Msk (0x1U << DMA_CCTRL_DTD_Pos) /*!< 0x00000010 */ +#define DMA_CCTRL_DTD DMA_CCTRL_DTD_Msk /*!< Data transfer direction */ +#define DMA_CCTRL_LM_Pos (5U) +#define DMA_CCTRL_LM_Msk (0x1U << DMA_CCTRL_LM_Pos) /*!< 0x00000020 */ +#define DMA_CCTRL_LM DMA_CCTRL_LM_Msk /*!< Circular mode */ +#define DMA_CCTRL_PINCM_Pos (6U) +#define DMA_CCTRL_PINCM_Msk (0x1U << DMA_CCTRL_PINCM_Pos) /*!< 0x00000040 */ +#define DMA_CCTRL_PINCM DMA_CCTRL_PINCM_Msk /*!< Peripheral address increment mode */ +#define DMA_CCTRL_MINCM_Pos (7U) +#define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ +#define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ + +#define DMA_CCTRL_PWIDTH_Pos (8U) +#define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ +#define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ +#define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ +#define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ + +#define DMA_CCTRL_MWIDTH_Pos (10U) +#define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ +#define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ +#define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ +#define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ + +#define DMA_CCTRL_CHPL_Pos (12U) +#define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ +#define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ +#define DMA_CCTRL_CHPL_0 (0x1U << DMA_CCTRL_CHPL_Pos) /*!< 0x00001000 */ +#define DMA_CCTRL_CHPL_1 (0x2U << DMA_CCTRL_CHPL_Pos) /*!< 0x00002000 */ + +#define DMA_CCTRL_M2M_Pos (14U) +#define DMA_CCTRL_M2M_Msk (0x1U << DMA_CCTRL_M2M_Pos) /*!< 0x00004000 */ +#define DMA_CCTRL_M2M DMA_CCTRL_M2M_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CDTCNT register ******************/ +#define DMA_CDTCNT_CNT_Pos (0U) +#define DMA_CDTCNT_CNT_Msk (0xFFFFU << DMA_CDTCNT_CNT_Pos) /*!< 0x0000FFFF */ +#define DMA_CDTCNT_CNT DMA_CDTCNT_CNT_Msk /*!< Number of data to transfer */ + +/****************** Bit definition for DMA_CPADDR register ******************/ +#define DMA_CPADDR_PADDR_Pos (0U) +#define DMA_CPADDR_PADDR_Msk (0xFFFFFFFFU << DMA_CPADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPADDR_PADDR DMA_CPADDR_PADDR_Msk /*!< Peripheral base address */ + +/****************** Bit definition for DMA_CMADDR register ******************/ +#define DMA_CMADDR_MADDR_Pos (0U) +#define DMA_CMADDR_MADDR_Msk (0xFFFFFFFFU << DMA_CMADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMADDR_MADDR DMA_CMADDR_MADDR_Msk /*!< Memory base address */ + +/***************** Bit definition for DMA_SRC_SEL0 register *****************/ +#define DMA_SRC_SEL0_CH1_SRC_Pos (0U) +#define DMA_SRC_SEL0_CH1_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH1_SRC_Pos) /*!< 0x000000FF */ +#define DMA_SRC_SEL0_CH1_SRC DMA_SRC_SEL0_CH1_SRC_Msk /*!< CH1 source select */ +#define DMA_SRC_SEL0_CH2_SRC_Pos (8U) +#define DMA_SRC_SEL0_CH2_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH2_SRC_Pos) /*!< 0x0000FF00 */ +#define DMA_SRC_SEL0_CH2_SRC DMA_SRC_SEL0_CH2_SRC_Msk /*!< CH2 source select */ +#define DMA_SRC_SEL0_CH3_SRC_Pos (16U) +#define DMA_SRC_SEL0_CH3_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH3_SRC_Pos) /*!< 0x00FF0000 */ +#define DMA_SRC_SEL0_CH3_SRC DMA_SRC_SEL0_CH3_SRC_Msk /*!< CH3 source select */ +#define DMA_SRC_SEL0_CH4_SRC_Pos (24U) +#define DMA_SRC_SEL0_CH4_SRC_Msk (0xFFU << DMA_SRC_SEL0_CH4_SRC_Pos) /*!< 0xFF000000 */ +#define DMA_SRC_SEL0_CH4_SRC DMA_SRC_SEL0_CH4_SRC_Msk /*!< CH4 source select */ + +/***************** Bit definition for DMA_SRC_SEL1 register *****************/ +#define DMA_SRC_SEL1_CH5_SRC_Pos (0U) +#define DMA_SRC_SEL1_CH5_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH5_SRC_Pos) /*!< 0x000000FF */ +#define DMA_SRC_SEL1_CH5_SRC DMA_SRC_SEL1_CH5_SRC_Msk /*!< CH5 source select */ +#define DMA_SRC_SEL1_CH6_SRC_Pos (8U) +#define DMA_SRC_SEL1_CH6_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH6_SRC_Pos) /*!< 0x0000FF00 */ +#define DMA_SRC_SEL1_CH6_SRC DMA_SRC_SEL1_CH6_SRC_Msk /*!< CH6 source select */ +#define DMA_SRC_SEL1_CH7_SRC_Pos (16U) +#define DMA_SRC_SEL1_CH7_SRC_Msk (0xFFU << DMA_SRC_SEL1_CH7_SRC_Pos) /*!< 0x00FF0000 */ +#define DMA_SRC_SEL1_CH7_SRC DMA_SRC_SEL1_CH7_SRC_Msk /*!< CH7 source select */ +#define DMA_SRC_SEL1_DMA_FLEX_EN_Pos (24U) +#define DMA_SRC_SEL1_DMA_FLEX_EN_Msk (0x1U << DMA_SRC_SEL1_DMA_FLEX_EN_Pos) /*!< 0x01000000 */ +#define DMA_SRC_SEL1_DMA_FLEX_EN DMA_SRC_SEL1_DMA_FLEX_EN_Msk /*!< DMA flexible request mapping enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for CRC_DT register ********************/ +#define CRC_DT_DT_Pos (0U) +#define CRC_DT_DT_Msk (0xFFFFFFFFU << CRC_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DT_DT CRC_DT_DT_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_CDT register ********************/ +#define CRC_CDT_CDT_Pos (0U) +#define CRC_CDT_CDT_Msk (0xFFU << CRC_CDT_CDT_Pos) /*!< 0x000000FF */ +#define CRC_CDT_CDT CRC_CDT_CDT_Msk /*!< General-purpose 8-bit data register bits */ + +/******************* Bit definition for CRC_CTRL register *******************/ +#define CRC_CTRL_RST_Pos (0U) +#define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ +#define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ + +/*!< REVID configuration */ +#define CRC_CTRL_REVID_Pos (5U) +#define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID CRC_CTRL_REVID_Msk /*!< REVID[1:0] bits (Reverse input data) */ +#define CRC_CTRL_REVID_0 (0x1U << CRC_CTRL_REVID_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_1 (0x2U << CRC_CTRL_REVID_Pos) /*!< 0x00000040 */ + +#define CRC_CTRL_REVID_NOREV 0x00000000U /*!< No effect */ +#define CRC_CTRL_REVID_BYTEREV_Pos (5U) +#define CRC_CTRL_REVID_BYTEREV_Msk (0x1U << CRC_CTRL_REVID_BYTEREV_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_BYTEREV CRC_CTRL_REVID_BYTEREV_Msk /*!< Byte reverse */ +#define CRC_CTRL_REVID_HALFREV_Pos (6U) +#define CRC_CTRL_REVID_HALFREV_Msk (0x1U << CRC_CTRL_REVID_HALFREV_Pos) /*!< 0x00000040 */ +#define CRC_CTRL_REVID_HALFREV CRC_CTRL_REVID_HALFREV_Msk /*!< Half-word reverse */ +#define CRC_CTRL_REVID_WORDREV_Pos (5U) +#define CRC_CTRL_REVID_WORDREV_Msk (0x3U << CRC_CTRL_REVID_WORDREV_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID_WORDREV CRC_CTRL_REVID_WORDREV_Msk /*!< Word reverse */ + +#define CRC_CTRL_REVOD_Pos (7U) +#define CRC_CTRL_REVOD_Msk (0x1U << CRC_CTRL_REVOD_Pos) /*!< 0x00000080 */ +#define CRC_CTRL_REVOD CRC_CTRL_REVOD_Msk /*!< Reverse output data */ + +/******************* Bit definition for CRC_IDT register ********************/ +#define CRC_IDT_IDT_Pos (0U) +#define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ + +/******************************************************************************/ +/* */ +/* Inter-integrated circuit interface (I2C) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2C_CTRL1 register *******************/ +#define I2C_CTRL1_I2CEN_Pos (0U) +#define I2C_CTRL1_I2CEN_Msk (0x1U << I2C_CTRL1_I2CEN_Pos) /*!< 0x00000001 */ +#define I2C_CTRL1_I2CEN I2C_CTRL1_I2CEN_Msk /*!< I2C peripheral enable */ +#define I2C_CTRL1_PERMODE_Pos (1U) +#define I2C_CTRL1_PERMODE_Msk (0x1U << I2C_CTRL1_PERMODE_Pos) /*!< 0x00000002 */ +#define I2C_CTRL1_PERMODE I2C_CTRL1_PERMODE_Msk /*!< I2C peripheral mode */ +#define I2C_CTRL1_SMBMODE_Pos (3U) +#define I2C_CTRL1_SMBMODE_Msk (0x1U << I2C_CTRL1_SMBMODE_Pos) /*!< 0x00000008 */ +#define I2C_CTRL1_SMBMODE I2C_CTRL1_SMBMODE_Msk /*!< SMBus device mode */ +#define I2C_CTRL1_ARPEN_Pos (4U) +#define I2C_CTRL1_ARPEN_Msk (0x1U << I2C_CTRL1_ARPEN_Pos) /*!< 0x00000010 */ +#define I2C_CTRL1_ARPEN I2C_CTRL1_ARPEN_Msk /*!< SMBus address resolution protocol enable */ +#define I2C_CTRL1_PECEN_Pos (5U) +#define I2C_CTRL1_PECEN_Msk (0x1U << I2C_CTRL1_PECEN_Pos) /*!< 0x00000020 */ +#define I2C_CTRL1_PECEN I2C_CTRL1_PECEN_Msk /*!< PEC calculation enable */ +#define I2C_CTRL1_GCAEN_Pos (6U) +#define I2C_CTRL1_GCAEN_Msk (0x1U << I2C_CTRL1_GCAEN_Pos) /*!< 0x00000040 */ +#define I2C_CTRL1_GCAEN I2C_CTRL1_GCAEN_Msk /*!< General call address enable */ +#define I2C_CTRL1_STRETCH_Pos (7U) +#define I2C_CTRL1_STRETCH_Msk (0x1U << I2C_CTRL1_STRETCH_Pos) /*!< 0x00000080 */ +#define I2C_CTRL1_STRETCH I2C_CTRL1_STRETCH_Msk /*!< Clock stretching mode */ +#define I2C_CTRL1_GENSTART_Pos (8U) +#define I2C_CTRL1_GENSTART_Msk (0x1U << I2C_CTRL1_GENSTART_Pos) /*!< 0x00000100 */ +#define I2C_CTRL1_GENSTART I2C_CTRL1_GENSTART_Msk /*!< Generate start condition */ +#define I2C_CTRL1_GENSTOP_Pos (9U) +#define I2C_CTRL1_GENSTOP_Msk (0x1U << I2C_CTRL1_GENSTOP_Pos) /*!< 0x00000200 */ +#define I2C_CTRL1_GENSTOP I2C_CTRL1_GENSTOP_Msk /*!< Generate stop condition */ +#define I2C_CTRL1_ACKEN_Pos (10U) +#define I2C_CTRL1_ACKEN_Msk (0x1U << I2C_CTRL1_ACKEN_Pos) /*!< 0x00000400 */ +#define I2C_CTRL1_ACKEN I2C_CTRL1_ACKEN_Msk /*!< Acknowledge enable */ +#define I2C_CTRL1_MACKCTRL_Pos (11U) +#define I2C_CTRL1_MACKCTRL_Msk (0x1U << I2C_CTRL1_MACKCTRL_Pos) /*!< 0x00000800 */ +#define I2C_CTRL1_MACKCTRL I2C_CTRL1_MACKCTRL_Msk /*!< Master receive mode acknowledge control */ +#define I2C_CTRL1_PECTEN_Pos (12U) +#define I2C_CTRL1_PECTEN_Msk (0x1U << I2C_CTRL1_PECTEN_Pos) /*!< 0x00001000 */ +#define I2C_CTRL1_PECTEN I2C_CTRL1_PECTEN_Msk /*!< Request PEC transfer enable */ +#define I2C_CTRL1_SMBALERT_Pos (13U) +#define I2C_CTRL1_SMBALERT_Msk (0x1U << I2C_CTRL1_SMBALERT_Pos) /*!< 0x00002000 */ +#define I2C_CTRL1_SMBALERT I2C_CTRL1_SMBALERT_Msk /*!< SMBus alert pin set */ +#define I2C_CTRL1_RESET_Pos (15U) +#define I2C_CTRL1_RESET_Msk (0x1U << I2C_CTRL1_RESET_Pos) /*!< 0x00008000 */ +#define I2C_CTRL1_RESET I2C_CTRL1_RESET_Msk /*!< I2C peripheral reset */ + +/****************** Bit definition for I2C_CTRL2 register *******************/ +/*!< CLKFREQ configuration */ +#define I2C_CTRL2_CLKFREQ_Pos (0U) +#define I2C_CTRL2_CLKFREQ_Msk (0xFFU << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x000000FF */ +#define I2C_CTRL2_CLKFREQ I2C_CTRL2_CLKFREQ_Msk /*!< CLKFREQ[7:0] bits (I2C input clock frequency) */ +#define I2C_CTRL2_CLKFREQ_0 (0x01U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000001 */ +#define I2C_CTRL2_CLKFREQ_1 (0x02U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000002 */ +#define I2C_CTRL2_CLKFREQ_2 (0x04U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000004 */ +#define I2C_CTRL2_CLKFREQ_3 (0x08U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000008 */ +#define I2C_CTRL2_CLKFREQ_4 (0x10U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000010 */ +#define I2C_CTRL2_CLKFREQ_5 (0x20U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000020 */ +#define I2C_CTRL2_CLKFREQ_6 (0x40U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000040 */ +#define I2C_CTRL2_CLKFREQ_7 (0x80U << I2C_CTRL2_CLKFREQ_Pos) /*!< 0x00000080 */ + +#define I2C_CTRL2_ERRIEN_Pos (8U) +#define I2C_CTRL2_ERRIEN_Msk (0x1U << I2C_CTRL2_ERRIEN_Pos) /*!< 0x00000100 */ +#define I2C_CTRL2_ERRIEN I2C_CTRL2_ERRIEN_Msk /*!< Error interrupt enable */ +#define I2C_CTRL2_EVTIEN_Pos (9U) +#define I2C_CTRL2_EVTIEN_Msk (0x1U << I2C_CTRL2_EVTIEN_Pos) /*!< 0x00000200 */ +#define I2C_CTRL2_EVTIEN I2C_CTRL2_EVTIEN_Msk /*!< Event interrupt enable */ +#define I2C_CTRL2_DATAIEN_Pos (10U) +#define I2C_CTRL2_DATAIEN_Msk (0x1U << I2C_CTRL2_DATAIEN_Pos) /*!< 0x00000400 */ +#define I2C_CTRL2_DATAIEN I2C_CTRL2_DATAIEN_Msk /*!< Data transfer interrupt enable */ +#define I2C_CTRL2_DMAEN_Pos (11U) +#define I2C_CTRL2_DMAEN_Msk (0x1U << I2C_CTRL2_DMAEN_Pos) /*!< 0x00000800 */ +#define I2C_CTRL2_DMAEN I2C_CTRL2_DMAEN_Msk /*!< DMA transfer enable */ +#define I2C_CTRL2_DMAEND_Pos (12U) +#define I2C_CTRL2_DMAEND_Msk (0x1U << I2C_CTRL2_DMAEND_Pos) /*!< 0x00001000 */ +#define I2C_CTRL2_DMAEND I2C_CTRL2_DMAEND_Msk /*!< End of DMA transfer */ + +/****************** Bit definition for I2C_OADDR1 register ******************/ +/*!< ADDR1 configuration */ +#define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ +#define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ +#define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ +#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ +#define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ +#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ +#define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ +#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ +#define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ +#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ +#define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ +#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ +#define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ +#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ +#define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ +#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ +#define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ +#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ +#define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ + +#define I2C_OADDR1_ADDR1MODE_Pos (15U) +#define I2C_OADDR1_ADDR1MODE_Msk (0x1U << I2C_OADDR1_ADDR1MODE_Pos) /*!< 0x00008000 */ +#define I2C_OADDR1_ADDR1MODE I2C_OADDR1_ADDR1MODE_Msk /*!< Address mode */ + +/****************** Bit definition for I2C_OADDR2 register ******************/ +#define I2C_OADDR2_ADDR2EN_Pos (0U) +#define I2C_OADDR2_ADDR2EN_Msk (0x1U << I2C_OADDR2_ADDR2EN_Pos) /*!< 0x00000001 */ +#define I2C_OADDR2_ADDR2EN I2C_OADDR2_ADDR2EN_Msk /*!< Own address 2 enable */ +#define I2C_OADDR2_ADDR2_Pos (1U) +#define I2C_OADDR2_ADDR2_Msk (0x7FU << I2C_OADDR2_ADDR2_Pos) /*!< 0x000000FE */ +#define I2C_OADDR2_ADDR2 I2C_OADDR2_ADDR2_Msk /*!< Own address 2 */ + +/******************** Bit definition for I2C_DT register ********************/ +#define I2C_DT_DT_Pos (0U) +#define I2C_DT_DT_Msk (0xFFU << I2C_DT_DT_Pos) /*!< 0x000000FF */ +#define I2C_DT_DT I2C_DT_DT_Msk /*!< This field is used to store data received or to be transferred */ + +/******************* Bit definition for I2C_STS1 register *******************/ +#define I2C_STS1_STARTF_Pos (0U) +#define I2C_STS1_STARTF_Msk (0x1U << I2C_STS1_STARTF_Pos) /*!< 0x00000001 */ +#define I2C_STS1_STARTF I2C_STS1_STARTF_Msk /*!< Start condition generation complete flag */ +#define I2C_STS1_ADDR7F_Pos (1U) +#define I2C_STS1_ADDR7F_Msk (0x1U << I2C_STS1_ADDR7F_Pos) /*!< 0x00000002 */ +#define I2C_STS1_ADDR7F I2C_STS1_ADDR7F_Msk /*!< 0 ~ 7 bit address match flag */ +#define I2C_STS1_TDC_Pos (2U) +#define I2C_STS1_TDC_Msk (0x1U << I2C_STS1_TDC_Pos) /*!< 0x00000004 */ +#define I2C_STS1_TDC I2C_STS1_TDC_Msk /*!< Data transfer complete flag */ +#define I2C_STS1_ADDRHF_Pos (3U) +#define I2C_STS1_ADDRHF_Msk (0x1U << I2C_STS1_ADDRHF_Pos) /*!< 0x00000008 */ +#define I2C_STS1_ADDRHF I2C_STS1_ADDRHF_Msk /*!< Master 9 ~ 8 bit address head match flag */ +#define I2C_STS1_STOPF_Pos (4U) +#define I2C_STS1_STOPF_Msk (0x1U << I2C_STS1_STOPF_Pos) /*!< 0x00000010 */ +#define I2C_STS1_STOPF I2C_STS1_STOPF_Msk /*!< Stop condition generation complete flag */ +#define I2C_STS1_RDBF_Pos (6U) +#define I2C_STS1_RDBF_Msk (0x1U << I2C_STS1_RDBF_Pos) /*!< 0x00000040 */ +#define I2C_STS1_RDBF I2C_STS1_RDBF_Msk /*!< Receive data buffer full flag */ +#define I2C_STS1_TDBE_Pos (7U) +#define I2C_STS1_TDBE_Msk (0x1U << I2C_STS1_TDBE_Pos) /*!< 0x00000080 */ +#define I2C_STS1_TDBE I2C_STS1_TDBE_Msk /*!< Transmit data buffer empty flag */ +#define I2C_STS1_BUSERR_Pos (8U) +#define I2C_STS1_BUSERR_Msk (0x1U << I2C_STS1_BUSERR_Pos) /*!< 0x00000100 */ +#define I2C_STS1_BUSERR I2C_STS1_BUSERR_Msk /*!< Bus error flag */ +#define I2C_STS1_ARLOST_Pos (9U) +#define I2C_STS1_ARLOST_Msk (0x1U << I2C_STS1_ARLOST_Pos) /*!< 0x00000200 */ +#define I2C_STS1_ARLOST I2C_STS1_ARLOST_Msk /*!< Arbitration lost flag */ +#define I2C_STS1_ACKFAIL_Pos (10U) +#define I2C_STS1_ACKFAIL_Msk (0x1U << I2C_STS1_ACKFAIL_Pos) /*!< 0x00000400 */ +#define I2C_STS1_ACKFAIL I2C_STS1_ACKFAIL_Msk /*!< Acknowledge failure flag */ +#define I2C_STS1_OUF_Pos (11U) +#define I2C_STS1_OUF_Msk (0x1U << I2C_STS1_OUF_Pos) /*!< 0x00000800 */ +#define I2C_STS1_OUF I2C_STS1_OUF_Msk /*!< Overload / underload flag */ +#define I2C_STS1_PECERR_Pos (12U) +#define I2C_STS1_PECERR_Msk (0x1U << I2C_STS1_PECERR_Pos) /*!< 0x00001000 */ +#define I2C_STS1_PECERR I2C_STS1_PECERR_Msk /*!< PEC receive error flag */ +#define I2C_STS1_TMOUT_Pos (14U) +#define I2C_STS1_TMOUT_Msk (0x1U << I2C_STS1_TMOUT_Pos) /*!< 0x00004000 */ +#define I2C_STS1_TMOUT I2C_STS1_TMOUT_Msk /*!< SMBus timeout flag */ +#define I2C_STS1_ALERTF_Pos (15U) +#define I2C_STS1_ALERTF_Msk (0x1U << I2C_STS1_ALERTF_Pos) /*!< 0x00008000 */ +#define I2C_STS1_ALERTF I2C_STS1_ALERTF_Msk /*!< SMBus alert flag */ + +/******************* Bit definition for I2C_STS2 register *******************/ +#define I2C_STS2_TRMODE_Pos (0U) +#define I2C_STS2_TRMODE_Msk (0x1U << I2C_STS2_TRMODE_Pos) /*!< 0x00000001 */ +#define I2C_STS2_TRMODE I2C_STS2_TRMODE_Msk /*!< Transmission mode */ +#define I2C_STS2_BUSYF_Pos (1U) +#define I2C_STS2_BUSYF_Msk (0x1U << I2C_STS2_BUSYF_Pos) /*!< 0x00000002 */ +#define I2C_STS2_BUSYF I2C_STS2_BUSYF_Msk /*!< Bus busy flag transmission mode */ +#define I2C_STS2_DIRF_Pos (2U) +#define I2C_STS2_DIRF_Msk (0x1U << I2C_STS2_DIRF_Pos) /*!< 0x00000004 */ +#define I2C_STS2_DIRF I2C_STS2_DIRF_Msk /*!< Transmission direction flag */ +#define I2C_STS2_GCADDRF_Pos (4U) +#define I2C_STS2_GCADDRF_Msk (0x1U << I2C_STS2_GCADDRF_Pos) /*!< 0x00000010 */ +#define I2C_STS2_GCADDRF I2C_STS2_GCADDRF_Msk /*!< General call address reception flag */ +#define I2C_STS2_DEVADDRF_Pos (5U) +#define I2C_STS2_DEVADDRF_Msk (0x1U << I2C_STS2_DEVADDRF_Pos) /*!< 0x00000020 */ +#define I2C_STS2_DEVADDRF I2C_STS2_DEVADDRF_Msk /*!< SMBus device address reception flag */ +#define I2C_STS2_HOSTADDRF_Pos (6U) +#define I2C_STS2_HOSTADDRF_Msk (0x1U << I2C_STS2_HOSTADDRF_Pos) /*!< 0x00000040 */ +#define I2C_STS2_HOSTADDRF I2C_STS2_HOSTADDRF_Msk /*!< SMBus host address reception flag */ +#define I2C_STS2_ADDR2F_Pos (7U) +#define I2C_STS2_ADDR2F_Msk (0x1U << I2C_STS2_ADDR2F_Pos) /*!< 0x00000080 */ +#define I2C_STS2_ADDR2F I2C_STS2_ADDR2F_Msk /*!< Received address 2 flag */ +#define I2C_STS2_PECVAL_Pos (8U) +#define I2C_STS2_PECVAL_Msk (0xFFU << I2C_STS2_PECVAL_Pos) /*!< 0x0000FF00 */ +#define I2C_STS2_PECVAL I2C_STS2_PECVAL_Msk /*!< PEC value */ + +/***************** Bit definition for I2C_CLKCTRL register ******************/ +#define I2C_CLKCTRL_SPEED_Pos (0U) +#define I2C_CLKCTRL_SPEED_Msk (0xFFFU << I2C_CLKCTRL_SPEED_Pos) /*!< 0x00000FFF */ +#define I2C_CLKCTRL_SPEED I2C_CLKCTRL_SPEED_Msk /*!< I2C bus speed config */ +#define I2C_CLKCTRL_DUTYMODE_Pos (14U) +#define I2C_CLKCTRL_DUTYMODE_Msk (0x1U << I2C_CLKCTRL_DUTYMODE_Pos) /*!< 0x00004000 */ +#define I2C_CLKCTRL_DUTYMODE I2C_CLKCTRL_DUTYMODE_Msk /*!< Fast mode duty cycle */ +#define I2C_CLKCTRL_SPEEDMODE_Pos (15U) +#define I2C_CLKCTRL_SPEEDMODE_Msk (0x1U << I2C_CLKCTRL_SPEEDMODE_Pos) /*!< 0x00008000 */ +#define I2C_CLKCTRL_SPEEDMODE I2C_CLKCTRL_SPEEDMODE_Msk /*!< Speed mode selection */ + +/****************** Bit definition for I2C_TMRISE register ******************/ +#define I2C_TMRISE_RISETIME_Pos (0U) +#define I2C_TMRISE_RISETIME_Msk (0x3FU << I2C_TMRISE_RISETIME_Pos) /*!< 0x0000003F */ +#define I2C_TMRISE_RISETIME I2C_TMRISE_RISETIME_Msk /*!< I2C bus rise time */ + +/******************************************************************************/ +/* */ +/* Universal synchronous/asynchronous receiver/transmitter (USART) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for USART_STS register *******************/ +#define USART_STS_PERR_Pos (0U) +#define USART_STS_PERR_Msk (0x1U << USART_STS_PERR_Pos) /*!< 0x00000001 */ +#define USART_STS_PERR USART_STS_PERR_Msk /*!< Parity error */ +#define USART_STS_FERR_Pos (1U) +#define USART_STS_FERR_Msk (0x1U << USART_STS_FERR_Pos) /*!< 0x00000002 */ +#define USART_STS_FERR USART_STS_FERR_Msk /*!< Framing error */ +#define USART_STS_NERR_Pos (2U) +#define USART_STS_NERR_Msk (0x1U << USART_STS_NERR_Pos) /*!< 0x00000004 */ +#define USART_STS_NERR USART_STS_NERR_Msk /*!< Noise error */ +#define USART_STS_ROERR_Pos (3U) +#define USART_STS_ROERR_Msk (0x1U << USART_STS_ROERR_Pos) /*!< 0x00000008 */ +#define USART_STS_ROERR USART_STS_ROERR_Msk /*!< Receiver overflow error */ +#define USART_STS_IDLEF_Pos (4U) +#define USART_STS_IDLEF_Msk (0x1U << USART_STS_IDLEF_Pos) /*!< 0x00000010 */ +#define USART_STS_IDLEF USART_STS_IDLEF_Msk /*!< Idle flag */ +#define USART_STS_RDBF_Pos (5U) +#define USART_STS_RDBF_Msk (0x1U << USART_STS_RDBF_Pos) /*!< 0x00000020 */ +#define USART_STS_RDBF USART_STS_RDBF_Msk /*!< Receive data buffer full */ +#define USART_STS_TDC_Pos (6U) +#define USART_STS_TDC_Msk (0x1U << USART_STS_TDC_Pos) /*!< 0x00000040 */ +#define USART_STS_TDC USART_STS_TDC_Msk /*!< Transmit data complete */ +#define USART_STS_TDBE_Pos (7U) +#define USART_STS_TDBE_Msk (0x1U << USART_STS_TDBE_Pos) /*!< 0x00000080 */ +#define USART_STS_TDBE USART_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define USART_STS_BFF_Pos (8U) +#define USART_STS_BFF_Msk (0x1U << USART_STS_BFF_Pos) /*!< 0x00000100 */ +#define USART_STS_BFF USART_STS_BFF_Msk /*!< Break frame flag */ +#define USART_STS_CTSCF_Pos (9U) +#define USART_STS_CTSCF_Msk (0x1U << USART_STS_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_STS_CTSCF USART_STS_CTSCF_Msk /*!< CTS change flag */ + +/******************* Bit definition for USART_DT register *******************/ +#define USART_DT_DT_Pos (0U) +#define USART_DT_DT_Msk (0x1FFU << USART_DT_DT_Pos) /*!< 0x000001FF */ +#define USART_DT_DT USART_DT_DT_Msk /*!< Data value */ + +/***************** Bit definition for USART_BAUDR register ******************/ +#define USART_BAUDR_DIV_Pos (0U) +#define USART_BAUDR_DIV_Msk (0xFFFFU << USART_BAUDR_DIV_Pos) /*!< 0x0000FFFF */ +#define USART_BAUDR_DIV USART_BAUDR_DIV_Msk /*!< Divider */ + +/***************** Bit definition for USART_CTRL1 register ******************/ +#define USART_CTRL1_SBF_Pos (0U) +#define USART_CTRL1_SBF_Msk (0x1U << USART_CTRL1_SBF_Pos) /*!< 0x00000001 */ +#define USART_CTRL1_SBF USART_CTRL1_SBF_Msk /*!< Send break frame */ +#define USART_CTRL1_RM_Pos (1U) +#define USART_CTRL1_RM_Msk (0x1U << USART_CTRL1_RM_Pos) /*!< 0x00000002 */ +#define USART_CTRL1_RM USART_CTRL1_RM_Msk /*!< Receiver mute */ +#define USART_CTRL1_REN_Pos (2U) +#define USART_CTRL1_REN_Msk (0x1U << USART_CTRL1_REN_Pos) /*!< 0x00000004 */ +#define USART_CTRL1_REN USART_CTRL1_REN_Msk /*!< Receiver enable */ +#define USART_CTRL1_TEN_Pos (3U) +#define USART_CTRL1_TEN_Msk (0x1U << USART_CTRL1_TEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL1_TEN USART_CTRL1_TEN_Msk /*!< Transmitter enable */ +#define USART_CTRL1_IDLEIEN_Pos (4U) +#define USART_CTRL1_IDLEIEN_Msk (0x1U << USART_CTRL1_IDLEIEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL1_IDLEIEN USART_CTRL1_IDLEIEN_Msk /*!< IDLE interrupt enable */ +#define USART_CTRL1_RDBFIEN_Pos (5U) +#define USART_CTRL1_RDBFIEN_Msk (0x1U << USART_CTRL1_RDBFIEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL1_RDBFIEN USART_CTRL1_RDBFIEN_Msk /*!< RDBF interrupt enable */ +#define USART_CTRL1_TDCIEN_Pos (6U) +#define USART_CTRL1_TDCIEN_Msk (0x1U << USART_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL1_TDCIEN USART_CTRL1_TDCIEN_Msk /*!< TDC interrupt enable */ +#define USART_CTRL1_TDBEIEN_Pos (7U) +#define USART_CTRL1_TDBEIEN_Msk (0x1U << USART_CTRL1_TDBEIEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL1_TDBEIEN USART_CTRL1_TDBEIEN_Msk /*!< TDBE interrupt enable */ +#define USART_CTRL1_PERRIEN_Pos (8U) +#define USART_CTRL1_PERRIEN_Msk (0x1U << USART_CTRL1_PERRIEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL1_PERRIEN USART_CTRL1_PERRIEN_Msk /*!< PERR interrupt enable */ +#define USART_CTRL1_PSEL_Pos (9U) +#define USART_CTRL1_PSEL_Msk (0x1U << USART_CTRL1_PSEL_Pos) /*!< 0x00000200 */ +#define USART_CTRL1_PSEL USART_CTRL1_PSEL_Msk /*!< Parity selection */ +#define USART_CTRL1_PEN_Pos (10U) +#define USART_CTRL1_PEN_Msk (0x1U << USART_CTRL1_PEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL1_PEN USART_CTRL1_PEN_Msk /*!< Parity enable */ +#define USART_CTRL1_WUM_Pos (11U) +#define USART_CTRL1_WUM_Msk (0x1U << USART_CTRL1_WUM_Pos) /*!< 0x00000800 */ +#define USART_CTRL1_WUM USART_CTRL1_WUM_Msk /*!< Wakeup mode */ +#define USART_CTRL1_DBN_Pos (12U) +#define USART_CTRL1_DBN_Msk (0x1U << USART_CTRL1_DBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL1_DBN USART_CTRL1_DBN_Msk /*!< Data bit num */ +#define USART_CTRL1_UEN_Pos (13U) +#define USART_CTRL1_UEN_Msk (0x1U << USART_CTRL1_UEN_Pos) /*!< 0x00002000 */ +#define USART_CTRL1_UEN USART_CTRL1_UEN_Msk /*!< USART enable */ + +/***************** Bit definition for USART_CTRL2 register ******************/ +#define USART_CTRL2_ID_Pos (0U) +#define USART_CTRL2_ID_Msk (0xFU << USART_CTRL2_ID_Pos) /*!< 0x0000000F */ +#define USART_CTRL2_ID USART_CTRL2_ID_Msk /*!< USART identification */ +#define USART_CTRL2_BFBN_Pos (5U) +#define USART_CTRL2_BFBN_Msk (0x1U << USART_CTRL2_BFBN_Pos) /*!< 0x00000020 */ +#define USART_CTRL2_BFBN USART_CTRL2_BFBN_Msk /*!< Break frame bit num */ +#define USART_CTRL2_BFIEN_Pos (6U) +#define USART_CTRL2_BFIEN_Msk (0x1U << USART_CTRL2_BFIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL2_BFIEN USART_CTRL2_BFIEN_Msk /*!< Break frame interrupt enable */ +#define USART_CTRL2_LBCP_Pos (8U) +#define USART_CTRL2_LBCP_Msk (0x1U << USART_CTRL2_LBCP_Pos) /*!< 0x00000100 */ +#define USART_CTRL2_LBCP USART_CTRL2_LBCP_Msk /*!< Last bit clock pulse */ +#define USART_CTRL2_CLKPHA_Pos (9U) +#define USART_CTRL2_CLKPHA_Msk (0x1U << USART_CTRL2_CLKPHA_Pos) /*!< 0x00000200 */ +#define USART_CTRL2_CLKPHA USART_CTRL2_CLKPHA_Msk /*!< Clock phase */ +#define USART_CTRL2_CLKPOL_Pos (10U) +#define USART_CTRL2_CLKPOL_Msk (0x1U << USART_CTRL2_CLKPOL_Pos) /*!< 0x00000400 */ +#define USART_CTRL2_CLKPOL USART_CTRL2_CLKPOL_Msk /*!< Clock polarity */ +#define USART_CTRL2_CLKEN_Pos (11U) +#define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ + +#define USART_CTRL2_STOPBN_Pos (12U) +#define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ +#define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ +#define USART_CTRL2_STOPBN_0 (0x1U << USART_CTRL2_STOPBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL2_STOPBN_1 (0x2U << USART_CTRL2_STOPBN_Pos) /*!< 0x00002000 */ + +#define USART_CTRL2_LINEN_Pos (14U) +#define USART_CTRL2_LINEN_Msk (0x1U << USART_CTRL2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CTRL2_LINEN USART_CTRL2_LINEN_Msk /*!< LIN mode enable */ + +/***************** Bit definition for USART_CTRL3 register ******************/ +#define USART_CTRL3_ERRIEN_Pos (0U) +#define USART_CTRL3_ERRIEN_Msk (0x1U << USART_CTRL3_ERRIEN_Pos) /*!< 0x00000001 */ +#define USART_CTRL3_ERRIEN USART_CTRL3_ERRIEN_Msk /*!< Error interrupt enable */ +#define USART_CTRL3_IRDAEN_Pos (1U) +#define USART_CTRL3_IRDAEN_Msk (0x1U << USART_CTRL3_IRDAEN_Pos) /*!< 0x00000002 */ +#define USART_CTRL3_IRDAEN USART_CTRL3_IRDAEN_Msk /*!< IrDA enable */ +#define USART_CTRL3_IRDALP_Pos (2U) +#define USART_CTRL3_IRDALP_Msk (0x1U << USART_CTRL3_IRDALP_Pos) /*!< 0x00000004 */ +#define USART_CTRL3_IRDALP USART_CTRL3_IRDALP_Msk /*!< IrDA low-power mode */ +#define USART_CTRL3_SLBEN_Pos (3U) +#define USART_CTRL3_SLBEN_Msk (0x1U << USART_CTRL3_SLBEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL3_SLBEN USART_CTRL3_SLBEN_Msk /*!< Single-wire bidirectional half-duplex enable */ +#define USART_CTRL3_SCNACKEN_Pos (4U) +#define USART_CTRL3_SCNACKEN_Msk (0x1U << USART_CTRL3_SCNACKEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL3_SCNACKEN USART_CTRL3_SCNACKEN_Msk /*!< Smart Card NACK enable */ +#define USART_CTRL3_SCMEN_Pos (5U) +#define USART_CTRL3_SCMEN_Msk (0x1U << USART_CTRL3_SCMEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL3_SCMEN USART_CTRL3_SCMEN_Msk /*!< Smart Card mode enable */ +#define USART_CTRL3_DMAREN_Pos (6U) +#define USART_CTRL3_DMAREN_Msk (0x1U << USART_CTRL3_DMAREN_Pos) /*!< 0x00000040 */ +#define USART_CTRL3_DMAREN USART_CTRL3_DMAREN_Msk /*!< DMA receiver enable */ +#define USART_CTRL3_DMATEN_Pos (7U) +#define USART_CTRL3_DMATEN_Msk (0x1U << USART_CTRL3_DMATEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL3_DMATEN USART_CTRL3_DMATEN_Msk /*!< DMA transmitter enable */ +#define USART_CTRL3_RTSEN_Pos (8U) +#define USART_CTRL3_RTSEN_Msk (0x1U << USART_CTRL3_RTSEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL3_RTSEN USART_CTRL3_RTSEN_Msk /*!< RTS enable */ +#define USART_CTRL3_CTSEN_Pos (9U) +#define USART_CTRL3_CTSEN_Msk (0x1U << USART_CTRL3_CTSEN_Pos) /*!< 0x00000200 */ +#define USART_CTRL3_CTSEN USART_CTRL3_CTSEN_Msk /*!< CTS enable */ +#define USART_CTRL3_CTSCFIEN_Pos (10U) +#define USART_CTRL3_CTSCFIEN_Msk (0x1U << USART_CTRL3_CTSCFIEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ + +/****************** Bit definition for USART_GDIV register ******************/ +#define USART_GDIV_ISDIV_Pos (0U) +#define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ +#define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ +#define USART_GDIV_ISDIV_0 (0x01U << USART_GDIV_ISDIV_Pos) /*!< 0x00000001 */ +#define USART_GDIV_ISDIV_1 (0x02U << USART_GDIV_ISDIV_Pos) /*!< 0x00000002 */ +#define USART_GDIV_ISDIV_2 (0x04U << USART_GDIV_ISDIV_Pos) /*!< 0x00000004 */ +#define USART_GDIV_ISDIV_3 (0x08U << USART_GDIV_ISDIV_Pos) /*!< 0x00000008 */ +#define USART_GDIV_ISDIV_4 (0x10U << USART_GDIV_ISDIV_Pos) /*!< 0x00000010 */ +#define USART_GDIV_ISDIV_5 (0x20U << USART_GDIV_ISDIV_Pos) /*!< 0x00000020 */ +#define USART_GDIV_ISDIV_6 (0x40U << USART_GDIV_ISDIV_Pos) /*!< 0x00000040 */ +#define USART_GDIV_ISDIV_7 (0x80U << USART_GDIV_ISDIV_Pos) /*!< 0x00000080 */ + +#define USART_GDIV_SCGT_Pos (8U) +#define USART_GDIV_SCGT_Msk (0xFFU << USART_GDIV_SCGT_Pos) /*!< 0x0000FF00 */ +#define USART_GDIV_SCGT USART_GDIV_SCGT_Msk /*!< Smart Card guard time value */ + +/******************************************************************************/ +/* */ +/* Serial peripheral interface (SPI) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SPI_CTRL1 register *******************/ +#define SPI_CTRL1_CLKPHA_Pos (0U) +#define SPI_CTRL1_CLKPHA_Msk (0x1U << SPI_CTRL1_CLKPHA_Pos) /*!< 0x00000001 */ +#define SPI_CTRL1_CLKPHA SPI_CTRL1_CLKPHA_Msk /*!< Clock phase */ +#define SPI_CTRL1_CLKPOL_Pos (1U) +#define SPI_CTRL1_CLKPOL_Msk (0x1U << SPI_CTRL1_CLKPOL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL1_CLKPOL SPI_CTRL1_CLKPOL_Msk /*!< Clock polarity */ +#define SPI_CTRL1_MSTEN_Pos (2U) +#define SPI_CTRL1_MSTEN_Msk (0x1U << SPI_CTRL1_MSTEN_Pos) /*!< 0x00000004 */ +#define SPI_CTRL1_MSTEN SPI_CTRL1_MSTEN_Msk /*!< Master enable */ + +/*!< MDIV configuration */ +#define SPI_CTRL1_MDIV_Msk ((SPI_CTRL2_MDIV) | (0x7U << 3) /*!< 0x00000138 */ +#define SPI_CTRL1_MDIV SPI_CTRL1_MDIV_Msk /*!< MDIV[3:0] bits (Master clock frequency division) */ +#define SPI_CTRL1_MDIV_0 (0x1U << 3) /*!< 0x00000008 */ +#define SPI_CTRL1_MDIV_1 (0x2U << 3) /*!< 0x00000010 */ +#define SPI_CTRL1_MDIV_2 (0x4U << 3) /*!< 0x00000020 */ +#define SPI_CTRL1_MDIV_3 SPI_CTRL2_MDIV /*!< 0x00000100 */ + +#define SPI_CTRL1_SPIEN_Pos (6U) +#define SPI_CTRL1_SPIEN_Msk (0x1U << SPI_CTRL1_SPIEN_Pos) /*!< 0x00000040 */ +#define SPI_CTRL1_SPIEN SPI_CTRL1_SPIEN_Msk /*!< SPI enable */ +#define SPI_CTRL1_LTF_Pos (7U) +#define SPI_CTRL1_LTF_Msk (0x1U << SPI_CTRL1_LTF_Pos) /*!< 0x00000080 */ +#define SPI_CTRL1_LTF SPI_CTRL1_LTF_Msk /*!< LSB transmit first */ +#define SPI_CTRL1_SWCSIL_Pos (8U) +#define SPI_CTRL1_SWCSIL_Msk (0x1U << SPI_CTRL1_SWCSIL_Pos) /*!< 0x00000100 */ +#define SPI_CTRL1_SWCSIL SPI_CTRL1_SWCSIL_Msk /*!< Software CS internal level */ +#define SPI_CTRL1_SWCSEN_Pos (9U) +#define SPI_CTRL1_SWCSEN_Msk (0x1U << SPI_CTRL1_SWCSEN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL1_SWCSEN SPI_CTRL1_SWCSEN_Msk /*!< Software CS enable */ +#define SPI_CTRL1_ORA_Pos (10U) +#define SPI_CTRL1_ORA_Msk (0x1U << SPI_CTRL1_ORA_Pos) /*!< 0x00000400 */ +#define SPI_CTRL1_ORA SPI_CTRL1_ORA_Msk /*!< Receive-only active */ +#define SPI_CTRL1_FBN_Pos (11U) +#define SPI_CTRL1_FBN_Msk (0x1U << SPI_CTRL1_FBN_Pos) /*!< 0x00000800 */ +#define SPI_CTRL1_FBN SPI_CTRL1_FBN_Msk /*!< Frame bit num */ +#define SPI_CTRL1_NTC_Pos (12U) +#define SPI_CTRL1_NTC_Msk (0x1U << SPI_CTRL1_NTC_Pos) /*!< 0x00001000 */ +#define SPI_CTRL1_NTC SPI_CTRL1_NTC_Msk /*!< Transmit CRC next */ +#define SPI_CTRL1_CCEN_Pos (13U) +#define SPI_CTRL1_CCEN_Msk (0x1U << SPI_CTRL1_CCEN_Pos) /*!< 0x00002000 */ +#define SPI_CTRL1_CCEN SPI_CTRL1_CCEN_Msk /*!< RC calculation enable */ +#define SPI_CTRL1_SLBTD_Pos (14U) +#define SPI_CTRL1_SLBTD_Msk (0x1U << SPI_CTRL1_SLBTD_Pos) /*!< 0x00004000 */ +#define SPI_CTRL1_SLBTD SPI_CTRL1_SLBTD_Msk /*!< Single line bidirectional half-duplex transmission direction */ +#define SPI_CTRL1_SLBEN_Pos (15U) +#define SPI_CTRL1_SLBEN_Msk (0x1U << SPI_CTRL1_SLBEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL1_SLBEN SPI_CTRL1_SLBEN_Msk /*!< Single line bidirectional half-duplex enable */ + +/****************** Bit definition for SPI_CTRL2 register *******************/ +#define SPI_CTRL2_DMAREN_Pos (0U) +#define SPI_CTRL2_DMAREN_Msk (0x1U << SPI_CTRL2_DMAREN_Pos) /*!< 0x00000001 */ +#define SPI_CTRL2_DMAREN SPI_CTRL2_DMAREN_Msk /*!< DMA receive enable */ +#define SPI_CTRL2_DMATEN_Pos (1U) +#define SPI_CTRL2_DMATEN_Msk (0x1U << SPI_CTRL2_DMATEN_Pos) /*!< 0x00000002 */ +#define SPI_CTRL2_DMATEN SPI_CTRL2_DMATEN_Msk /*!< DMA transmit enable */ +#define SPI_CTRL2_HWCSOE_Pos (2U) +#define SPI_CTRL2_HWCSOE_Msk (0x1U << SPI_CTRL2_HWCSOE_Pos) /*!< 0x00000004 */ +#define SPI_CTRL2_HWCSOE SPI_CTRL2_HWCSOE_Msk /*!< Hardware CS output enable */ +#define SPI_CTRL2_ERRIE_Pos (5U) +#define SPI_CTRL2_ERRIE_Msk (0x1U << SPI_CTRL2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CTRL2_ERRIE SPI_CTRL2_ERRIE_Msk /*!< Error interrupt enable */ +#define SPI_CTRL2_RDBFIE_Pos (6U) +#define SPI_CTRL2_RDBFIE_Msk (0x1U << SPI_CTRL2_RDBFIE_Pos) /*!< 0x00000040 */ +#define SPI_CTRL2_RDBFIE SPI_CTRL2_RDBFIE_Msk /*!< Receive data buffer full interrupt enable */ +#define SPI_CTRL2_TDBEIE_Pos (7U) +#define SPI_CTRL2_TDBEIE_Msk (0x1U << SPI_CTRL2_TDBEIE_Pos) /*!< 0x00000080 */ +#define SPI_CTRL2_TDBEIE SPI_CTRL2_TDBEIE_Msk /*!< Transmit data buffer empty interrupt enable */ +#define SPI_CTRL2_MDIV_Pos (8U) +#define SPI_CTRL2_MDIV_Msk (0x1U << SPI_CTRL2_MDIV_Pos) /*!< 0x00000100 */ +#define SPI_CTRL2_MDIV SPI_CTRL2_MDIV_Msk /*!< Master clock frequency division */ + +/******************* Bit definition for SPI_STS register ********************/ +#define SPI_STS_RDBF_Pos (0U) +#define SPI_STS_RDBF_Msk (0x1U << SPI_STS_RDBF_Pos) /*!< 0x00000001 */ +#define SPI_STS_RDBF SPI_STS_RDBF_Msk /*!< Receive data buffer full */ +#define SPI_STS_TDBE_Pos (1U) +#define SPI_STS_TDBE_Msk (0x1U << SPI_STS_TDBE_Pos) /*!< 0x00000002 */ +#define SPI_STS_TDBE SPI_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define SPI_STS_ACS_Pos (2U) +#define SPI_STS_ACS_Msk (0x1U << SPI_STS_ACS_Pos) /*!< 0x00000004 */ +#define SPI_STS_ACS SPI_STS_ACS_Msk /*!< Audio channel state */ +#define SPI_STS_TUERR_Pos (3U) +#define SPI_STS_TUERR_Msk (0x1U << SPI_STS_TUERR_Pos) /*!< 0x00000008 */ +#define SPI_STS_TUERR SPI_STS_TUERR_Msk /*!< Transmitter underload error */ +#define SPI_STS_CCERR_Pos (4U) +#define SPI_STS_CCERR_Msk (0x1U << SPI_STS_CCERR_Pos) /*!< 0x00000010 */ +#define SPI_STS_CCERR SPI_STS_CCERR_Msk /*!< CRC error */ +#define SPI_STS_MMERR_Pos (5U) +#define SPI_STS_MMERR_Msk (0x1U << SPI_STS_MMERR_Pos) /*!< 0x00000020 */ +#define SPI_STS_MMERR SPI_STS_MMERR_Msk /*!< Master mode error */ +#define SPI_STS_ROERR_Pos (6U) +#define SPI_STS_ROERR_Msk (0x1U << SPI_STS_ROERR_Pos) /*!< 0x00000040 */ +#define SPI_STS_ROERR SPI_STS_ROERR_Msk /*!< Receiver overflow error */ +#define SPI_STS_BF_Pos (7U) +#define SPI_STS_BF_Msk (0x1U << SPI_STS_BF_Pos) /*!< 0x00000080 */ +#define SPI_STS_BF SPI_STS_BF_Msk /*!< Busy flag */ + +/******************** Bit definition for SPI_DT register ********************/ +#define SPI_DT_DT_Pos (0U) +#define SPI_DT_DT_Msk (0xFFFFU << SPI_DT_DT_Pos) /*!< 0x0000FFFF */ +#define SPI_DT_DT SPI_DT_DT_Msk /*!< Data value */ + +/******************* Bit definition for SPI_CPOLY register ******************/ +#define SPI_CPOLY_CPOLY_Pos (0U) +#define SPI_CPOLY_CPOLY_Msk (0xFFFFU << SPI_CPOLY_CPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CPOLY_CPOLY SPI_CPOLY_CPOLY_Msk /*!< CRC polynomial */ + +/******************* Bit definition for SPI_RCRC register *******************/ +#define SPI_RCRC_RCRC_Pos (0U) +#define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Receive CRC */ + +/******************* Bit definition for SPI_TCRC register *******************/ +#define SPI_TCRC_TCRC_Pos (0U) +#define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Transmit CRC */ + +/***************** Bit definition for SPI_I2SCTRL register ******************/ +#define SPI_I2SCTRL_I2SCBN_Pos (0U) +#define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ + +#define SPI_I2SCTRL_I2SDBN_Pos (1U) +#define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ +#define SPI_I2SCTRL_I2SDBN_0 (0x1U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCTRL_I2SDBN_1 (0x2U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCTRL_I2SCLKPOL_Pos (3U) +#define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ + +#define SPI_I2SCTRL_STDSEL_Pos (4U) +#define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ +#define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ +#define SPI_I2SCTRL_STDSEL_0 (0x1U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000010 */ +#define SPI_I2SCTRL_STDSEL_1 (0x2U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCTRL_PCMFSSEL_Pos (7U) +#define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ +#define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ + +#define SPI_I2SCTRL_OPERSEL_Pos (8U) +#define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ +#define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ +#define SPI_I2SCTRL_OPERSEL_0 (0x1U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000100 */ +#define SPI_I2SCTRL_OPERSEL_1 (0x2U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCTRL_I2SEN_Pos (10U) +#define SPI_I2SCTRL_I2SEN_Msk (0x1U << SPI_I2SCTRL_I2SEN_Pos) /*!< 0x00000400 */ +#define SPI_I2SCTRL_I2SEN SPI_I2SCTRL_I2SEN_Msk /*!< I2S enable */ +#define SPI_I2SCTRL_I2SMSEL_Pos (11U) +#define SPI_I2SCTRL_I2SMSEL_Msk (0x1U << SPI_I2SCTRL_I2SMSEL_Pos) /*!< 0x00000800 */ +#define SPI_I2SCTRL_I2SMSEL SPI_I2SCTRL_I2SMSEL_Msk /*!< I2S mode select */ + +/***************** Bit definition for SPI_I2SCLKP register ******************/ +#define SPI_I2SCLKP_I2SDIV_Msk ((0xFFU << 0) | (0x3U << 10)) /*!< 0x00000CFF */ +#define SPI_I2SCLKP_I2SDIV SPI_I2SCLKP_I2SDIV_Msk /*!< I2SDIV[9:0] bits (I2S division) */ +#define SPI_I2SCLKP_I2SODD_Pos (8U) +#define SPI_I2SCLKP_I2SODD_Msk (0x1U << SPI_I2SCLKP_I2SODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SCLKP_I2SODD SPI_I2SCLKP_I2SODD_Msk /*!< Odd factor for I2S division */ +#define SPI_I2SCLKP_I2SMCLKOE_Pos (9U) +#define SPI_I2SCLKP_I2SMCLKOE_Msk (0x1U << SPI_I2SCLKP_I2SMCLKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SCLKP_I2SMCLKOE SPI_I2SCLKP_I2SMCLKOE_Msk /*!< I2S Master clock output enable */ + +/******************************************************************************/ +/* */ +/* Window watchdog timer (WWDT) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for WWDT_CTRL register *******************/ +#define WWDT_CTRL_CNT_Pos (0U) +#define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ +#define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ +#define WWDT_CTRL_CNT_0 (0x01U << WWDT_CTRL_CNT_Pos) /*!< 0x00000001 */ +#define WWDT_CTRL_CNT_1 (0x02U << WWDT_CTRL_CNT_Pos) /*!< 0x00000002 */ +#define WWDT_CTRL_CNT_2 (0x04U << WWDT_CTRL_CNT_Pos) /*!< 0x00000004 */ +#define WWDT_CTRL_CNT_3 (0x08U << WWDT_CTRL_CNT_Pos) /*!< 0x00000008 */ +#define WWDT_CTRL_CNT_4 (0x10U << WWDT_CTRL_CNT_Pos) /*!< 0x00000010 */ +#define WWDT_CTRL_CNT_5 (0x20U << WWDT_CTRL_CNT_Pos) /*!< 0x00000020 */ +#define WWDT_CTRL_CNT_6 (0x40U << WWDT_CTRL_CNT_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CTRL_CNT0 WWDT_CTRL_CNT_0 +#define WWDT_CTRL_CNT1 WWDT_CTRL_CNT_1 +#define WWDT_CTRL_CNT2 WWDT_CTRL_CNT_2 +#define WWDT_CTRL_CNT3 WWDT_CTRL_CNT_3 +#define WWDT_CTRL_CNT4 WWDT_CTRL_CNT_4 +#define WWDT_CTRL_CNT5 WWDT_CTRL_CNT_5 +#define WWDT_CTRL_CNT6 WWDT_CTRL_CNT_6 + +#define WWDT_CTRL_WWDTEN_Pos (7U) +#define WWDT_CTRL_WWDTEN_Msk (0x1U << WWDT_CTRL_WWDTEN_Pos) /*!< 0x00000080 */ +#define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ + +/******************* Bit definition for WWDT_CFG register *******************/ +#define WWDT_CFG_WIN_Pos (0U) +#define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ +#define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ +#define WWDT_CFG_WIN_0 (0x01U << WWDT_CFG_WIN_Pos) /*!< 0x00000001 */ +#define WWDT_CFG_WIN_1 (0x02U << WWDT_CFG_WIN_Pos) /*!< 0x00000002 */ +#define WWDT_CFG_WIN_2 (0x04U << WWDT_CFG_WIN_Pos) /*!< 0x00000004 */ +#define WWDT_CFG_WIN_3 (0x08U << WWDT_CFG_WIN_Pos) /*!< 0x00000008 */ +#define WWDT_CFG_WIN_4 (0x10U << WWDT_CFG_WIN_Pos) /*!< 0x00000010 */ +#define WWDT_CFG_WIN_5 (0x20U << WWDT_CFG_WIN_Pos) /*!< 0x00000020 */ +#define WWDT_CFG_WIN_6 (0x40U << WWDT_CFG_WIN_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CFG_WIN0 WWDT_CFG_WIN_0 +#define WWDT_CFG_WIN1 WWDT_CFG_WIN_1 +#define WWDT_CFG_WIN2 WWDT_CFG_WIN_2 +#define WWDT_CFG_WIN3 WWDT_CFG_WIN_3 +#define WWDT_CFG_WIN4 WWDT_CFG_WIN_4 +#define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 +#define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 + +#define WWDT_CFG_DIV_Pos (7U) +#define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ +#define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ +#define WWDT_CFG_DIV_0 (0x1U << WWDT_CFG_DIV_Pos) /*!< 0x00000080 */ +#define WWDT_CFG_DIV_1 (0x2U << WWDT_CFG_DIV_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDT_CFG_DIV0 WWDT_CFG_DIV_0 +#define WWDT_CFG_DIV1 WWDT_CFG_DIV_1 + +#define WWDT_CFG_RLDIEN_Pos (9U) +#define WWDT_CFG_RLDIEN_Msk (0x1U << WWDT_CFG_RLDIEN_Pos) /*!< 0x00000200 */ +#define WWDT_CFG_RLDIEN WWDT_CFG_RLDIEN_Msk /*!< Reload counter interrupt */ + +/******************* Bit definition for WWDT_STS register *******************/ +#define WWDT_STS_RLDF_Pos (0U) +#define WWDT_STS_RLDF_Msk (0x1U << WWDT_STS_RLDF_Pos) /*!< 0x00000001 */ +#define WWDT_STS_RLDF WWDT_STS_RLDF_Msk /*!< Reload counter interrupt flag */ + +/******************************************************************************/ +/* */ +/* Watchdog timer (WDT) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WDT_CMD register ********************/ +#define WDT_CMD_CMD_Pos (0U) +#define WDT_CMD_CMD_Msk (0xFFFFU << WDT_CMD_CMD_Pos) /*!< 0x0000FFFF */ +#define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ + +/******************* Bit definition for WDT_DIV register ********************/ +#define WDT_DIV_DIV_Pos (0U) +#define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ +#define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ +#define WDT_DIV_DIV_0 (0x1U << WDT_DIV_DIV_Pos) /*!< 0x00000001 */ +#define WDT_DIV_DIV_1 (0x2U << WDT_DIV_DIV_Pos) /*!< 0x00000002 */ +#define WDT_DIV_DIV_2 (0x4U << WDT_DIV_DIV_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for WDT_RLD register ********************/ +#define WDT_RLD_RLD_Pos (0U) +#define WDT_RLD_RLD_Msk (0xFFFU << WDT_RLD_RLD_Pos) /*!< 0x00000FFF */ +#define WDT_RLD_RLD WDT_RLD_RLD_Msk /*!< Reload value */ + +/******************* Bit definition for WDT_STS register ********************/ +#define WDT_STS_DIVF_Pos (0U) +#define WDT_STS_DIVF_Msk (0x1U << WDT_STS_DIVF_Pos) /*!< 0x00000001 */ +#define WDT_STS_DIVF WDT_STS_DIVF_Msk /*!< Division value update complete flag */ +#define WDT_STS_RLDF_Pos (1U) +#define WDT_STS_RLDF_Msk (0x1U << WDT_STS_RLDF_Pos) /*!< 0x00000002 */ +#define WDT_STS_RLDF WDT_STS_RLDF_Msk /*!< Reload value update complete flag */ + +/******************************************************************************/ +/* */ +/* Enhanced real-time clock (ERTC) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for ERTC_TIME register *******************/ +#define ERTC_TIME_SU_Pos (0U) +#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_TIME_ST_Pos (4U) +#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_TIME_MU_Pos (8U) +#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TIME_MT_Pos (12U) +#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_TIME_HU_Pos (16U) +#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_TIME_HT_Pos (20U) +#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TIME_AMPM_Pos (22U) +#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_DATE register *******************/ +#define ERTC_DATE_DU_Pos (0U) +#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ +#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ +#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ +#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ +#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ + +#define ERTC_DATE_DT_Pos (4U) +#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ +#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ +#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ + +#define ERTC_DATE_MU_Pos (8U) +#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ +#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ +#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ +#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_DATE_MT_Pos (12U) +#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ +#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ + +#define ERTC_DATE_WK_Pos (13U) +#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ +#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ +#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ + +#define ERTC_DATE_YU_Pos (16U) +#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ +#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ +#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ +#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ +#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ +#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ + +#define ERTC_DATE_YT_Pos (20U) +#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ +#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ +#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ +#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ +#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ +#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ERTC_CTRL register *******************/ +#define ERTC_CTRL_WATCLK_Pos (0U) +#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ +#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ +#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ +#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ +#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ + +#define ERTC_CTRL_TSEDG_Pos (3U) +#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ +#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ +#define ERTC_CTRL_RCDEN_Pos (4U) +#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ +#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ +#define ERTC_CTRL_DREN_Pos (5U) +#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ +#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ +#define ERTC_CTRL_HM_Pos (6U) +#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ +#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ +#define ERTC_CTRL_CCALEN_Pos (7U) +#define ERTC_CTRL_CCALEN_Msk (0x1U << ERTC_CTRL_CCALEN_Pos) /*!< 0x00000080 */ +#define ERTC_CTRL_CCALEN ERTC_CTRL_CCALEN_Msk /*!< Coarse calibration enable */ +#define ERTC_CTRL_ALAEN_Pos (8U) +#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ +#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ +#define ERTC_CTRL_ALBEN_Pos (9U) +#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ +#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ +#define ERTC_CTRL_WATEN_Pos (10U) +#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ +#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ +#define ERTC_CTRL_TSEN_Pos (11U) +#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ +#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ +#define ERTC_CTRL_ALAIEN_Pos (12U) +#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ +#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ +#define ERTC_CTRL_ALBIEN_Pos (13U) +#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ +#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ +#define ERTC_CTRL_WATIEN_Pos (14U) +#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ +#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ +#define ERTC_CTRL_TSIEN_Pos (15U) +#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ +#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ +#define ERTC_CTRL_ADD1H_Pos (16U) +#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ +#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ +#define ERTC_CTRL_DEC1H_Pos (17U) +#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ +#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ +#define ERTC_CTRL_BPR_Pos (18U) +#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ +#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ +#define ERTC_CTRL_CALOSEL_Pos (19U) +#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ +#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ +#define ERTC_CTRL_OUTP_Pos (20U) +#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ +#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ + +#define ERTC_CTRL_OUTSEL_Pos (21U) +#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< WATCLK[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ +#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ + +#define ERTC_CTRL_CALOEN_Pos (23U) +#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ +#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ + +/******************* Bit definition for ERTC_STS register *******************/ +#define ERTC_STS_ALAWF_Pos (0U) +#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ +#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ +#define ERTC_STS_ALBWF_Pos (1U) +#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ +#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ +#define ERTC_STS_WATWF_Pos (2U) +#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ +#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ +#define ERTC_STS_TADJF_Pos (3U) +#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ +#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ +#define ERTC_STS_INITF_Pos (4U) +#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ +#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ +#define ERTC_STS_UPDF_Pos (5U) +#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ +#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ +#define ERTC_STS_IMF_Pos (6U) +#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ +#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ +#define ERTC_STS_IMEN_Pos (7U) +#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ +#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ +#define ERTC_STS_ALAF_Pos (8U) +#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ +#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ +#define ERTC_STS_ALBF_Pos (9U) +#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ +#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ +#define ERTC_STS_WATF_Pos (10U) +#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ +#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ +#define ERTC_STS_TSF_Pos (11U) +#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ +#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ +#define ERTC_STS_TSOF_Pos (12U) +#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ +#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ +#define ERTC_STS_TP1F_Pos (13U) +#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ +#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ +#define ERTC_STS_CALUPDF_Pos (16U) +#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ +#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ + +/******************* Bit definition for ERTC_DIV register *******************/ +#define ERTC_DIV_DIVB_Pos (0U) +#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ +#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ +#define ERTC_DIV_DIVA_Pos (16U) +#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ +#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ + +/******************* Bit definition for ERTC_WAT register *******************/ +#define ERTC_WAT_VAL_Pos (0U) +#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ +#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ + +/****************** Bit definition for ERTC_CCAL register *******************/ +#define ERTC_CCAL_CALVAL_Pos (0U) +#define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ +#define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ +#define ERTC_CCAL_CALVAL_0 (0x1U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000001 */ +#define ERTC_CCAL_CALVAL_1 (0x2U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000002 */ +#define ERTC_CCAL_CALVAL_2 (0x4U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000004 */ +#define ERTC_CCAL_CALVAL_3 (0x8U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000008 */ +#define ERTC_CCAL_CALVAL_4 (0x10U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000010 */ + +#define ERTC_CCAL_CALDIR_Pos (7U) +#define ERTC_CCAL_CALDIR_Msk (0x1U << ERTC_CCAL_CALDIR_Pos) /*!< 0x00000080 */ +#define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ + +/******************* Bit definition for ERTC_ALA register *******************/ +#define ERTC_ALA_SU_Pos (0U) +#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_ALA_ST_Pos (4U) +#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALA_MASK1_Pos (7U) +#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ + +#define ERTC_ALA_MU_Pos (8U) +#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_ALA_MT_Pos (12U) +#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALA_MASK2_Pos (15U) +#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ + +#define ERTC_ALA_HU_Pos (16U) +#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_ALA_HT_Pos (20U) +#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALA_AMPM_Pos (22U) +#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALA_MASK3_Pos (23U) +#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ + +#define ERTC_ALA_DU_Pos (24U) +#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ + +#define ERTC_ALA_DT_Pos (28U) +#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALA_WKSEL_Pos (30U) +#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALA_MASK4_Pos (31U) +#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_ALB register *******************/ +#define ERTC_ALB_SU_Pos (0U) +#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_ALB_ST_Pos (4U) +#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALB_MASK1_Pos (7U) +#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ + +#define ERTC_ALB_MU_Pos (8U) +#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_ALB_MT_Pos (12U) +#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALB_MASK2_Pos (15U) +#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ + +#define ERTC_ALB_HU_Pos (16U) +#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_ALB_HT_Pos (20U) +#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALB_AMPM_Pos (22U) +#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALB_MASK3_Pos (23U) +#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ + +#define ERTC_ALB_DU_Pos (24U) +#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ + +#define ERTC_ALB_DT_Pos (28U) +#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALB_WKSEL_Pos (30U) +#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALB_MASK4_Pos (31U) +#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_WP register ********************/ +#define ERTC_WP_CMD_Pos (0U) +#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ +#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ + +/******************* Bit definition for ERTC_SBS register *******************/ +#define ERTC_SBS_SBS_Pos (0U) +#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_TADJ register *******************/ +#define ERTC_TADJ_DECSBS_Pos (0U) +#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ +#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ +#define ERTC_TADJ_ADD1S_Pos (31U) +#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ +#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ + +/****************** Bit definition for ERTC_TSTM register *******************/ +#define ERTC_TSTM_SU_Pos (0U) +#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ + +#define ERTC_TSTM_ST_Pos (4U) +#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_TSTM_MU_Pos (8U) +#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSTM_MT_Pos (12U) +#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_TSTM_HU_Pos (16U) +#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ + +#define ERTC_TSTM_HT_Pos (20U) +#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TSTM_AMPM_Pos (22U) +#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_TSDT register *******************/ +#define ERTC_TSDT_DU_Pos (0U) +#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ +#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ +#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ +#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ +#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ + +#define ERTC_TSDT_DT_Pos (4U) +#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ +#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ +#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ + +#define ERTC_TSDT_MU_Pos (8U) +#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSDT_MT_Pos (12U) +#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ + +#define ERTC_TSDT_WK_Pos (13U) +#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ +#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ +#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for ERTC_TSSBS register ******************/ +#define ERTC_TSSBS_SBS_Pos (0U) +#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_SCAL register *******************/ +#define ERTC_SCAL_DEC_Pos (0U) +#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ +#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ +#define ERTC_SCAL_CAL16_Pos (13U) +#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ +#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ +#define ERTC_SCAL_CAL8_Pos (14U) +#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ +#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ +#define ERTC_SCAL_ADD_Pos (15U) +#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ +#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ + +/****************** Bit definition for ERTC_TAMP register *******************/ +#define ERTC_TAMP_TP1EN_Pos (0U) +#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ +#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ +#define ERTC_TAMP_TP1EDG_Pos (1U) +#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ +#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ +#define ERTC_TAMP_TPIEN_Pos (2U) +#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ +#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ +#define ERTC_TAMP_TPTSEN_Pos (7U) +#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ +#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ + +#define ERTC_TAMP_TPFREQ_Pos (8U) +#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ +#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ +#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ +#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ +#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ + +#define ERTC_TAMP_TPFLT_Pos (11U) +#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ +#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ +#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ +#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ + +#define ERTC_TAMP_TPPR_Pos (13U) +#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ +#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ +#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ +#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ + +#define ERTC_TAMP_TPPU_Pos (15U) +#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ +#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ +#define ERTC_TAMP_OUTTYPE_Pos (18U) +#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ +#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ + +/***************** Bit definition for ERTC_ALASBS register ******************/ +#define ERTC_ALASBS_SBS_Pos (0U) +#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ + +#define ERTC_ALASBS_SBSMSK_Pos (24U) +#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for ERTC_ALBSBS register ******************/ +#define ERTC_ALBSBS_SBS_Pos (0U) +#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ + +#define ERTC_ALBSBS_SBSMSK_Pos (24U) +#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ERTC_BPR1 register *******************/ +#define ERTC_BPR1_DT_Pos (0U) +#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ + +/****************** Bit definition for ERTC_BPR2 register *******************/ +#define ERTC_BPR2_DT_Pos (0U) +#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ + +/****************** Bit definition for ERTC_BPR3 register *******************/ +#define ERTC_BPR3_DT_Pos (0U) +#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ + +/****************** Bit definition for ERTC_BPR4 register *******************/ +#define ERTC_BPR4_DT_Pos (0U) +#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ + +/****************** Bit definition for ERTC_BPR5 register *******************/ +#define ERTC_BPR5_DT_Pos (0U) +#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ + +/****************** Bit definition for ERTC_BPR6 register *******************/ +#define ERTC_BPR6_DT_Pos (0U) +#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ + +/****************** Bit definition for ERTC_BPR7 register *******************/ +#define ERTC_BPR7_DT_Pos (0U) +#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ + +/****************** Bit definition for ERTC_BPR8 register *******************/ +#define ERTC_BPR8_DT_Pos (0U) +#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ + +/****************** Bit definition for ERTC_BPR9 register *******************/ +#define ERTC_BPR9_DT_Pos (0U) +#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ + +/****************** Bit definition for ERTC_BPR10 register ******************/ +#define ERTC_BPR10_DT_Pos (0U) +#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ + +/****************** Bit definition for ERTC_BPR11 register ******************/ +#define ERTC_BPR11_DT_Pos (0U) +#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ + +/****************** Bit definition for ERTC_BPR12 register ******************/ +#define ERTC_BPR12_DT_Pos (0U) +#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ + +/****************** Bit definition for ERTC_BPR13 register ******************/ +#define ERTC_BPR13_DT_Pos (0U) +#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ + +/****************** Bit definition for ERTC_BPR14 register ******************/ +#define ERTC_BPR14_DT_Pos (0U) +#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ + +/****************** Bit definition for ERTC_BPR15 register ******************/ +#define ERTC_BPR15_DT_Pos (0U) +#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ + +/****************** Bit definition for ERTC_BPR16 register ******************/ +#define ERTC_BPR16_DT_Pos (0U) +#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ + +/****************** Bit definition for ERTC_BPR17 register ******************/ +#define ERTC_BPR17_DT_Pos (0U) +#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ + +/****************** Bit definition for ERTC_BPR18 register ******************/ +#define ERTC_BPR18_DT_Pos (0U) +#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ + +/****************** Bit definition for ERTC_BPR19 register ******************/ +#define ERTC_BPR19_DT_Pos (0U) +#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ + +/****************** Bit definition for ERTC_BPR20 register ******************/ +#define ERTC_BPR20_DT_Pos (0U) +#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ + +/************************* Number of backup registers *************************/ +#define ERTC_BPR_NUMBER 0x000000014U + +/******************************************************************************/ +/* */ +/* Analog-to-digital converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ADC_STS register ********************/ +#define ADC_STS_VMOR_Pos (0U) +#define ADC_STS_VMOR_Msk (0x1U << ADC_STS_VMOR_Pos) /*!< 0x00000001 */ +#define ADC_STS_VMOR ADC_STS_VMOR_Msk /*!< Voltage monitoring out of range flag */ +#define ADC_STS_OCCC_Pos (1U) +#define ADC_STS_OCCC_Msk (0x1U << ADC_STS_OCCC_Pos) /*!< 0x00000002 */ +#define ADC_STS_OCCC ADC_STS_OCCC_Msk /*!< End of conversion flag */ +#define ADC_STS_PCCC_Pos (2U) +#define ADC_STS_PCCC_Msk (0x1U << ADC_STS_PCCC_Pos) /*!< 0x00000004 */ +#define ADC_STS_PCCC ADC_STS_PCCC_Msk /*!< Preempted channel end of conversion flag */ +#define ADC_STS_PCCS_Pos (3U) +#define ADC_STS_PCCS_Msk (0x1U << ADC_STS_PCCS_Pos) /*!< 0x00000008 */ +#define ADC_STS_PCCS ADC_STS_PCCS_Msk /*!< Preempted channel conversion start flag */ +#define ADC_STS_OCCS_Pos (4U) +#define ADC_STS_OCCS_Msk (0x1U << ADC_STS_OCCS_Pos) /*!< 0x00000010 */ +#define ADC_STS_OCCS ADC_STS_OCCS_Msk /*!< Ordinary channel conversion start flag */ + +/* Legacy defines */ +#define ADC_STS_OCCE (ADC_STS_OCCC) +#define ADC_STS_PCCE (ADC_STS_PCCC) + +/****************** Bit definition for ADC_CTRL1 register *******************/ +#define ADC_CTRL1_VMCSEL_Pos (0U) +#define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ +#define ADC_CTRL1_VMCSEL_0 (0x01U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTRL1_VMCSEL_1 (0x02U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTRL1_VMCSEL_2 (0x04U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL1_VMCSEL_3 (0x08U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTRL1_VMCSEL_4 (0x10U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000010 */ + +#define ADC_CTRL1_CCCIEN_Pos (5U) +#define ADC_CTRL1_CCCIEN_Msk (0x1U << ADC_CTRL1_CCCIEN_Pos) /*!< 0x00000020 */ +#define ADC_CTRL1_CCCIEN ADC_CTRL1_CCCIEN_Msk /*!< Channel conversion end interrupt enable */ +#define ADC_CTRL1_VMORIEN_Pos (6U) +#define ADC_CTRL1_VMORIEN_Msk (0x1U << ADC_CTRL1_VMORIEN_Pos) /*!< 0x00000040 */ +#define ADC_CTRL1_VMORIEN ADC_CTRL1_VMORIEN_Msk /*!< Voltage monitoring out of range interrupt enable */ +#define ADC_CTRL1_PCCCIEN_Pos (7U) +#define ADC_CTRL1_PCCCIEN_Msk (0x1U << ADC_CTRL1_PCCCIEN_Pos) /*!< 0x00000080 */ +#define ADC_CTRL1_PCCCIEN ADC_CTRL1_PCCCIEN_Msk /*!< Conversion end interrupt enable on Preempted channels */ +#define ADC_CTRL1_SQEN_Pos (8U) +#define ADC_CTRL1_SQEN_Msk (0x1U << ADC_CTRL1_SQEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL1_SQEN ADC_CTRL1_SQEN_Msk /*!< Sequence mode enable */ +#define ADC_CTRL1_VMSGEN_Pos (9U) +#define ADC_CTRL1_VMSGEN_Msk (0x1U << ADC_CTRL1_VMSGEN_Pos) /*!< 0x00000200 */ +#define ADC_CTRL1_VMSGEN ADC_CTRL1_VMSGEN_Msk /*!< Voltage monitoring enable on a single channel */ +#define ADC_CTRL1_PCAUTOEN_Pos (10U) +#define ADC_CTRL1_PCAUTOEN_Msk (0x1U << ADC_CTRL1_PCAUTOEN_Pos) /*!< 0x00000400 */ +#define ADC_CTRL1_PCAUTOEN ADC_CTRL1_PCAUTOEN_Msk /*!< Preempted group automatic conversion enable after ordinary group */ +#define ADC_CTRL1_OCPEN_Pos (11U) +#define ADC_CTRL1_OCPEN_Msk (0x1U << ADC_CTRL1_OCPEN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL1_OCPEN ADC_CTRL1_OCPEN_Msk /*!< Partitioned mode enable on ordinary channels */ +#define ADC_CTRL1_PCPEN_Pos (12U) +#define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ +#define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ + +#define ADC_CTRL1_OCPCNT_Pos (13U) +#define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ +#define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ +#define ADC_CTRL1_OCPCNT_0 (0x1U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00002000 */ +#define ADC_CTRL1_OCPCNT_1 (0x2U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00004000 */ +#define ADC_CTRL1_OCPCNT_2 (0x4U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00008000 */ + +#define ADC_CTRL1_PCVMEN_Pos (22U) +#define ADC_CTRL1_PCVMEN_Msk (0x1U << ADC_CTRL1_PCVMEN_Pos) /*!< 0x00400000 */ +#define ADC_CTRL1_PCVMEN ADC_CTRL1_PCVMEN_Msk /*!< Voltage monitoring enable on preempted channels */ +#define ADC_CTRL1_OCVMEN_Pos (23U) +#define ADC_CTRL1_OCVMEN_Msk (0x1U << ADC_CTRL1_OCVMEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL1_OCVMEN ADC_CTRL1_OCVMEN_Msk /*!< Voltage monitoring enable on ordinary channels */ + +/* Legacy defines */ +#define ADC_CTRL1_CCEIEN (ADC_CTRL1_CCCIEN) +#define ADC_CTRL1_PCCEIEN (ADC_CTRL1_PCCCIEN) + +/****************** Bit definition for ADC_CTRL2 register *******************/ +#define ADC_CTRL2_ADCEN_Pos (0U) +#define ADC_CTRL2_ADCEN_Msk (0x1U << ADC_CTRL2_ADCEN_Pos) /*!< 0x00000001 */ +#define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ +#define ADC_CTRL2_RPEN_Pos (1U) +#define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repition mode enable */ +#define ADC_CTRL2_ADCAL_Pos (2U) +#define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ +#define ADC_CTRL2_ADCALINIT_Pos (3U) +#define ADC_CTRL2_ADCALINIT_Msk (0x1U << ADC_CTRL2_ADCALINIT_Pos) /*!< 0x00000008 */ +#define ADC_CTRL2_ADCALINIT ADC_CTRL2_ADCALINIT_Msk /*!< Initialize A/D calibration */ +#define ADC_CTRL2_OCDMAEN_Pos (8U) +#define ADC_CTRL2_OCDMAEN_Msk (0x1U << ADC_CTRL2_OCDMAEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL2_OCDMAEN ADC_CTRL2_OCDMAEN_Msk /*!< DMA transfer enable of ordinary channels */ +#define ADC_CTRL2_DTALIGN_Pos (11U) +#define ADC_CTRL2_DTALIGN_Msk (0x1U << ADC_CTRL2_DTALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL2_DTALIGN ADC_CTRL2_DTALIGN_Msk /*!< Data alignment */ + +/*!< PCTESEL configuration */ +#define ADC_CTRL2_PCTESEL_Msk ((0x7U << 12) | (0x1U << 24)) /*!< 0x01007000 */ +#define ADC_CTRL2_PCTESEL ADC_CTRL2_PCTESEL_Msk /*!< PCTESEL[3:0] bits (Trigger event select for preempted channels conversion) */ +#define ADC_CTRL2_PCTESEL_0 (0x1U << 12) /*!< 0x00001000 */ +#define ADC_CTRL2_PCTESEL_1 (0x2U << 12) /*!< 0x00002000 */ +#define ADC_CTRL2_PCTESEL_2 (0x4U << 12) /*!< 0x00004000 */ +#define ADC_CTRL2_PCTESEL_3 (0x1U << 24) /*!< 0x01000000 */ + +#define ADC_CTRL2_PCTEN_Pos (15U) +#define ADC_CTRL2_PCTEN_Msk (0x1U << ADC_CTRL2_PCTEN_Pos) /*!< 0x00008000 */ +#define ADC_CTRL2_PCTEN ADC_CTRL2_PCTEN_Msk /*!< Trigger mode enable for preempted channels conversion */ + +/*!< OCTESEL configuration */ +#define ADC_CTRL2_OCTESEL_Msk ((0x7U << 17) | (0x1U << 25)) /*!< 0x020E0000 */ +#define ADC_CTRL2_OCTESEL ADC_CTRL2_OCTESEL_Msk /*!< OCTESEL[3:0] bits (Trigger event select for ordinary channels conversion) */ +#define ADC_CTRL2_OCTESEL_0 (0x1U << 17) /*!< 0x00020000 */ +#define ADC_CTRL2_OCTESEL_1 (0x2U << 17) /*!< 0x00040000 */ +#define ADC_CTRL2_OCTESEL_2 (0x4U << 17) /*!< 0x00080000 */ +#define ADC_CTRL2_OCTESEL_3 (0x1U << 25) /*!< 0x02000000 */ + +#define ADC_CTRL2_OCTEN_Pos (20U) +#define ADC_CTRL2_OCTEN_Msk (0x1U << ADC_CTRL2_OCTEN_Pos) /*!< 0x00100000 */ +#define ADC_CTRL2_OCTEN ADC_CTRL2_OCTEN_Msk /*!< Trigger mode enable for ordinary channels conversion */ +#define ADC_CTRL2_PCSWTRG_Pos (21U) +#define ADC_CTRL2_PCSWTRG_Msk (0x1U << ADC_CTRL2_PCSWTRG_Pos) /*!< 0x00200000 */ +#define ADC_CTRL2_PCSWTRG ADC_CTRL2_PCSWTRG_Msk /*!< Conversion of preempted channels triggered by software */ +#define ADC_CTRL2_OCSWTRG_Pos (22U) +#define ADC_CTRL2_OCSWTRG_Msk (0x1U << ADC_CTRL2_OCSWTRG_Pos) /*!< 0x00400000 */ +#define ADC_CTRL2_OCSWTRG ADC_CTRL2_OCSWTRG_Msk /*!< Conversion of ordinary channels triggered by software */ +#define ADC_CTRL2_ITSRVEN_Pos (23U) +#define ADC_CTRL2_ITSRVEN_Msk (0x1U << ADC_CTRL2_ITSRVEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ + +/******************* Bit definition for ADC_SPT1 register *******************/ +#define ADC_SPT1_CSPT10_Pos (0U) +#define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ +#define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ +#define ADC_SPT1_CSPT10_0 (0x1U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000001 */ +#define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ +#define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ + +#define ADC_SPT1_CSPT11_Pos (3U) +#define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ +#define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ +#define ADC_SPT1_CSPT11_0 (0x1U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000008 */ +#define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ +#define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ + +#define ADC_SPT1_CSPT12_Pos (6U) +#define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ +#define ADC_SPT1_CSPT12_0 (0x1U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000040 */ +#define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ +#define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ + +#define ADC_SPT1_CSPT13_Pos (9U) +#define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ +#define ADC_SPT1_CSPT13_0 (0x1U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000200 */ +#define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ +#define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ + +#define ADC_SPT1_CSPT14_Pos (12U) +#define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ +#define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ +#define ADC_SPT1_CSPT14_0 (0x1U << ADC_SPT1_CSPT14_Pos) /*!< 0x00001000 */ +#define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ +#define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ + +#define ADC_SPT1_CSPT15_Pos (15U) +#define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ +#define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ +#define ADC_SPT1_CSPT15_0 (0x1U << ADC_SPT1_CSPT15_Pos) /*!< 0x00008000 */ +#define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ +#define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ + +#define ADC_SPT1_CSPT16_Pos (18U) +#define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ +#define ADC_SPT1_CSPT16_0 (0x1U << ADC_SPT1_CSPT16_Pos) /*!< 0x00040000 */ +#define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ +#define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ + +#define ADC_SPT1_CSPT17_Pos (21U) +#define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ +#define ADC_SPT1_CSPT17_0 (0x1U << ADC_SPT1_CSPT17_Pos) /*!< 0x00200000 */ +#define ADC_SPT1_CSPT17_1 (0x2U << ADC_SPT1_CSPT17_Pos) /*!< 0x00400000 */ +#define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SPT2 register *******************/ +#define ADC_SPT2_CSPT0_Pos (0U) +#define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ +#define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ +#define ADC_SPT2_CSPT0_0 (0x1U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000001 */ +#define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ +#define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ + +#define ADC_SPT2_CSPT1_Pos (3U) +#define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ +#define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ +#define ADC_SPT2_CSPT1_0 (0x1U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000008 */ +#define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ +#define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ + +#define ADC_SPT2_CSPT2_Pos (6U) +#define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ +#define ADC_SPT2_CSPT2_0 (0x1U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000040 */ +#define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ +#define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ + +#define ADC_SPT2_CSPT3_Pos (9U) +#define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ +#define ADC_SPT2_CSPT3_0 (0x1U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000200 */ +#define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ +#define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ + +#define ADC_SPT2_CSPT4_Pos (12U) +#define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ +#define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ +#define ADC_SPT2_CSPT4_0 (0x1U << ADC_SPT2_CSPT4_Pos) /*!< 0x00001000 */ +#define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ +#define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ + +#define ADC_SPT2_CSPT5_Pos (15U) +#define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ +#define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ +#define ADC_SPT2_CSPT5_0 (0x1U << ADC_SPT2_CSPT5_Pos) /*!< 0x00008000 */ +#define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ +#define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ + +#define ADC_SPT2_CSPT6_Pos (18U) +#define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ +#define ADC_SPT2_CSPT6_0 (0x1U << ADC_SPT2_CSPT6_Pos) /*!< 0x00040000 */ +#define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ +#define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ + +#define ADC_SPT2_CSPT7_Pos (21U) +#define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ +#define ADC_SPT2_CSPT7_0 (0x1U << ADC_SPT2_CSPT7_Pos) /*!< 0x00200000 */ +#define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ +#define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ + +#define ADC_SPT2_CSPT8_Pos (24U) +#define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ +#define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ +#define ADC_SPT2_CSPT8_0 (0x1U << ADC_SPT2_CSPT8_Pos) /*!< 0x01000000 */ +#define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ +#define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ + +#define ADC_SPT2_CSPT9_Pos (27U) +#define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ +#define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ +#define ADC_SPT2_CSPT9_0 (0x1U << ADC_SPT2_CSPT9_Pos) /*!< 0x08000000 */ +#define ADC_SPT2_CSPT9_1 (0x2U << ADC_SPT2_CSPT9_Pos) /*!< 0x10000000 */ +#define ADC_SPT2_CSPT9_2 (0x4U << ADC_SPT2_CSPT9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_PCDTO1 register ******************/ +#define ADC_PCDTO1_PCDTO1_Pos (0U) +#define ADC_PCDTO1_PCDTO1_Msk (0xFFFU << ADC_PCDTO1_PCDTO1_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO1_PCDTO1 ADC_PCDTO1_PCDTO1_Msk /*!< Data offset for Preempted channel 1 */ + +/****************** Bit definition for ADC_PCDTO2 register ******************/ +#define ADC_PCDTO2_PCDTO2_Pos (0U) +#define ADC_PCDTO2_PCDTO2_Msk (0xFFFU << ADC_PCDTO2_PCDTO2_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO2_PCDTO2 ADC_PCDTO2_PCDTO2_Msk /*!< Data offset for Preempted channel 2 */ + +/****************** Bit definition for ADC_PCDTO3 register ******************/ +#define ADC_PCDTO3_PCDTO3_Pos (0U) +#define ADC_PCDTO3_PCDTO3_Msk (0xFFFU << ADC_PCDTO3_PCDTO3_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO3_PCDTO3 ADC_PCDTO3_PCDTO3_Msk /*!< Data offset for Preempted channel 3 */ + +/****************** Bit definition for ADC_PCDTO4 register ******************/ +#define ADC_PCDTO4_PCDTO4_Pos (0U) +#define ADC_PCDTO4_PCDTO4_Msk (0xFFFU << ADC_PCDTO4_PCDTO4_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO4_PCDTO4 ADC_PCDTO4_PCDTO4_Msk /*!< Data offset for Preempted channel 4 */ + +/******************* Bit definition for ADC_VMHB register ********************/ +#define ADC_VMHB_VMHB_Pos (0U) +#define ADC_VMHB_VMHB_Msk (0xFFFU << ADC_VMHB_VMHB_Pos) /*!< 0x00000FFF */ +#define ADC_VMHB_VMHB ADC_VMHB_VMHB_Msk /*!< Voltage monitoring high boundary */ + +/******************* Bit definition for ADC_VMLB register ********************/ +#define ADC_VMLB_VMLB_Pos (0U) +#define ADC_VMLB_VMLB_Msk (0xFFFU << ADC_VMLB_VMLB_Pos) /*!< 0x00000FFF */ +#define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ + +/******************* Bit definition for ADC_OSQ1 register *******************/ +#define ADC_OSQ1_OSN13_Pos (0U) +#define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ +#define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN13_0 (0x01U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000001 */ +#define ADC_OSQ1_OSN13_1 (0x02U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000002 */ +#define ADC_OSQ1_OSN13_2 (0x04U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000004 */ +#define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ +#define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ1_OSN14_Pos (5U) +#define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN14_0 (0x01U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000020 */ +#define ADC_OSQ1_OSN14_1 (0x02U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000040 */ +#define ADC_OSQ1_OSN14_2 (0x04U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000080 */ +#define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ +#define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ1_OSN15_Pos (10U) +#define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN15_0 (0x01U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000400 */ +#define ADC_OSQ1_OSN15_1 (0x02U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000800 */ +#define ADC_OSQ1_OSN15_2 (0x04U << ADC_OSQ1_OSN15_Pos) /*!< 0x00001000 */ +#define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ +#define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ1_OSN16_Pos (15U) +#define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN16_0 (0x01U << ADC_OSQ1_OSN16_Pos) /*!< 0x00008000 */ +#define ADC_OSQ1_OSN16_1 (0x02U << ADC_OSQ1_OSN16_Pos) /*!< 0x00010000 */ +#define ADC_OSQ1_OSN16_2 (0x04U << ADC_OSQ1_OSN16_Pos) /*!< 0x00020000 */ +#define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ +#define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ1_OCLEN_Pos (20U) +#define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ +#define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ +#define ADC_OSQ1_OCLEN_0 (0x1U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00100000 */ +#define ADC_OSQ1_OCLEN_1 (0x2U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00200000 */ +#define ADC_OSQ1_OCLEN_2 (0x4U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00400000 */ +#define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_OSQ2 register *******************/ +#define ADC_OSQ2_OSN7_Pos (0U) +#define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ +#define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN7_0 (0x01U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000001 */ +#define ADC_OSQ2_OSN7_1 (0x02U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000002 */ +#define ADC_OSQ2_OSN7_2 (0x04U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000004 */ +#define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ +#define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ2_OSN8_Pos (5U) +#define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN8_0 (0x01U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000020 */ +#define ADC_OSQ2_OSN8_1 (0x02U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000040 */ +#define ADC_OSQ2_OSN8_2 (0x04U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000080 */ +#define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ +#define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ2_OSN9_Pos (10U) +#define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN9_0 (0x01U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000400 */ +#define ADC_OSQ2_OSN9_1 (0x02U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000800 */ +#define ADC_OSQ2_OSN9_2 (0x04U << ADC_OSQ2_OSN9_Pos) /*!< 0x00001000 */ +#define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ +#define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ2_OSN10_Pos (15U) +#define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN10_0 (0x01U << ADC_OSQ2_OSN10_Pos) /*!< 0x00008000 */ +#define ADC_OSQ2_OSN10_1 (0x02U << ADC_OSQ2_OSN10_Pos) /*!< 0x00010000 */ +#define ADC_OSQ2_OSN10_2 (0x04U << ADC_OSQ2_OSN10_Pos) /*!< 0x00020000 */ +#define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ +#define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ2_OSN11_Pos (20U) +#define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN11_0 (0x01U << ADC_OSQ2_OSN11_Pos) /*!< 0x00100000 */ +#define ADC_OSQ2_OSN11_1 (0x02U << ADC_OSQ2_OSN11_Pos) /*!< 0x00200000 */ +#define ADC_OSQ2_OSN11_2 (0x04U << ADC_OSQ2_OSN11_Pos) /*!< 0x00400000 */ +#define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ +#define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ + +#define ADC_OSQ2_OSN12_Pos (25U) +#define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN12_0 (0x01U << ADC_OSQ2_OSN12_Pos) /*!< 0x02000000 */ +#define ADC_OSQ2_OSN12_1 (0x02U << ADC_OSQ2_OSN12_Pos) /*!< 0x04000000 */ +#define ADC_OSQ2_OSN12_2 (0x04U << ADC_OSQ2_OSN12_Pos) /*!< 0x08000000 */ +#define ADC_OSQ2_OSN12_3 (0x08U << ADC_OSQ2_OSN12_Pos) /*!< 0x10000000 */ +#define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_OSQ3 register *******************/ +#define ADC_OSQ3_OSN1_Pos (0U) +#define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ +#define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN1_0 (0x01U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000001 */ +#define ADC_OSQ3_OSN1_1 (0x02U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000002 */ +#define ADC_OSQ3_OSN1_2 (0x04U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000004 */ +#define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ +#define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ + +#define ADC_OSQ3_OSN2_Pos (5U) +#define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN2_0 (0x01U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000020 */ +#define ADC_OSQ3_OSN2_1 (0x02U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000040 */ +#define ADC_OSQ3_OSN2_2 (0x04U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000080 */ +#define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ +#define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ + +#define ADC_OSQ3_OSN3_Pos (10U) +#define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN3_0 (0x01U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000400 */ +#define ADC_OSQ3_OSN3_1 (0x02U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000800 */ +#define ADC_OSQ3_OSN3_2 (0x04U << ADC_OSQ3_OSN3_Pos) /*!< 0x00001000 */ +#define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ +#define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ + +#define ADC_OSQ3_OSN4_Pos (15U) +#define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN4_0 (0x01U << ADC_OSQ3_OSN4_Pos) /*!< 0x00008000 */ +#define ADC_OSQ3_OSN4_1 (0x02U << ADC_OSQ3_OSN4_Pos) /*!< 0x00010000 */ +#define ADC_OSQ3_OSN4_2 (0x04U << ADC_OSQ3_OSN4_Pos) /*!< 0x00020000 */ +#define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ +#define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ + +#define ADC_OSQ3_OSN5_Pos (20U) +#define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN5_0 (0x01U << ADC_OSQ3_OSN5_Pos) /*!< 0x00100000 */ +#define ADC_OSQ3_OSN5_1 (0x02U << ADC_OSQ3_OSN5_Pos) /*!< 0x00200000 */ +#define ADC_OSQ3_OSN5_2 (0x04U << ADC_OSQ3_OSN5_Pos) /*!< 0x00400000 */ +#define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ +#define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ + +#define ADC_OSQ3_OSN6_Pos (25U) +#define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN6_0 (0x01U << ADC_OSQ3_OSN6_Pos) /*!< 0x02000000 */ +#define ADC_OSQ3_OSN6_1 (0x02U << ADC_OSQ3_OSN6_Pos) /*!< 0x04000000 */ +#define ADC_OSQ3_OSN6_2 (0x04U << ADC_OSQ3_OSN6_Pos) /*!< 0x08000000 */ +#define ADC_OSQ3_OSN6_3 (0x08U << ADC_OSQ3_OSN6_Pos) /*!< 0x10000000 */ +#define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_PSQ register ********************/ +#define ADC_PSQ_PSN1_Pos (0U) +#define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ +#define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ +#define ADC_PSQ_PSN1_0 (0x01U << ADC_PSQ_PSN1_Pos) /*!< 0x00000001 */ +#define ADC_PSQ_PSN1_1 (0x02U << ADC_PSQ_PSN1_Pos) /*!< 0x00000002 */ +#define ADC_PSQ_PSN1_2 (0x04U << ADC_PSQ_PSN1_Pos) /*!< 0x00000004 */ +#define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ +#define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ + +#define ADC_PSQ_PSN2_Pos (5U) +#define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ +#define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ +#define ADC_PSQ_PSN2_0 (0x01U << ADC_PSQ_PSN2_Pos) /*!< 0x00000020 */ +#define ADC_PSQ_PSN2_1 (0x02U << ADC_PSQ_PSN2_Pos) /*!< 0x00000040 */ +#define ADC_PSQ_PSN2_2 (0x04U << ADC_PSQ_PSN2_Pos) /*!< 0x00000080 */ +#define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ +#define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ + +#define ADC_PSQ_PSN3_Pos (10U) +#define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ +#define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ +#define ADC_PSQ_PSN3_0 (0x01U << ADC_PSQ_PSN3_Pos) /*!< 0x00000400 */ +#define ADC_PSQ_PSN3_1 (0x02U << ADC_PSQ_PSN3_Pos) /*!< 0x00000800 */ +#define ADC_PSQ_PSN3_2 (0x04U << ADC_PSQ_PSN3_Pos) /*!< 0x00001000 */ +#define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ +#define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ + +#define ADC_PSQ_PSN4_Pos (15U) +#define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ +#define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ +#define ADC_PSQ_PSN4_0 (0x01U << ADC_PSQ_PSN4_Pos) /*!< 0x00008000 */ +#define ADC_PSQ_PSN4_1 (0x02U << ADC_PSQ_PSN4_Pos) /*!< 0x00010000 */ +#define ADC_PSQ_PSN4_2 (0x04U << ADC_PSQ_PSN4_Pos) /*!< 0x00020000 */ +#define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ +#define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ + +#define ADC_PSQ_PCLEN_Pos (20U) +#define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ +#define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ +#define ADC_PSQ_PCLEN_0 (0x1U << ADC_PSQ_PCLEN_Pos) /*!< 0x00100000 */ +#define ADC_PSQ_PCLEN_1 (0x2U << ADC_PSQ_PCLEN_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_PDT1 register *******************/ +#define ADC_PDT1_PDT1_Pos (0U) +#define ADC_PDT1_PDT1_Msk (0xFFFFU << ADC_PDT1_PDT1_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT1_PDT1 ADC_PDT1_PDT1_Msk /*!< Conversion data from preempted channel 1 */ + +/******************* Bit definition for ADC_PDT2 register *******************/ +#define ADC_PDT2_PDT2_Pos (0U) +#define ADC_PDT2_PDT2_Msk (0xFFFFU << ADC_PDT2_PDT2_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT2_PDT2 ADC_PDT2_PDT2_Msk /*!< Conversion data from preempted channel 2 */ + +/******************* Bit definition for ADC_PDT3 register *******************/ +#define ADC_PDT3_PDT3_Pos (0U) +#define ADC_PDT3_PDT3_Msk (0xFFFFU << ADC_PDT3_PDT3_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT3_PDT3 ADC_PDT3_PDT3_Msk /*!< Conversion data from preempted channel 3 */ + +/******************* Bit definition for ADC_PDT4 register *******************/ +#define ADC_PDT4_PDT4_Pos (0U) +#define ADC_PDT4_PDT4_Msk (0xFFFFU << ADC_PDT4_PDT4_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT4_PDT4 ADC_PDT4_PDT4_Msk /*!< Conversion data from preempted channel 4 */ + +/******************* Bit definition for ADC_ODT register ********************/ +#define ADC_ODT_ODT_Pos (0U) +#define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ +#define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ +#define ADC_ODT_ADC2ODT_Pos (16U) +#define ADC_ODT_ADC2ODT_Msk (0xFFFFU << ADC_ODT_ADC2ODT_Pos) /*!< 0xFFFF0000 */ +#define ADC_ODT_ADC2ODT ADC_ODT_ADC2ODT_Msk /*!< ADC2 conversion data of ordinary channel */ + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN) */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/****************** Bit definition for CAN_MCTRL register *******************/ +#define CAN_MCTRL_FZEN_Pos (0U) +#define CAN_MCTRL_FZEN_Msk (0x1U << CAN_MCTRL_FZEN_Pos) /*!< 0x00000001 */ +#define CAN_MCTRL_FZEN CAN_MCTRL_FZEN_Msk /*!< Freeze mode enable */ +#define CAN_MCTRL_DZEN_Pos (1U) +#define CAN_MCTRL_DZEN_Msk (0x1U << CAN_MCTRL_DZEN_Pos) /*!< 0x00000002 */ +#define CAN_MCTRL_DZEN CAN_MCTRL_DZEN_Msk /*!< Doze mode enable */ +#define CAN_MCTRL_MMSSR_Pos (2U) +#define CAN_MCTRL_MMSSR_Msk (0x1U << CAN_MCTRL_MMSSR_Pos) /*!< 0x00000004 */ +#define CAN_MCTRL_MMSSR CAN_MCTRL_MMSSR_Msk /*!< Multiple message transmit sequence rule */ +#define CAN_MCTRL_MDRSEL_Pos (3U) +#define CAN_MCTRL_MDRSEL_Msk (0x1U << CAN_MCTRL_MDRSEL_Pos) /*!< 0x00000008 */ +#define CAN_MCTRL_MDRSEL CAN_MCTRL_MDRSEL_Msk /*!< Message discard rule select when overflow */ +#define CAN_MCTRL_PRSFEN_Pos (4U) +#define CAN_MCTRL_PRSFEN_Msk (0x1U << CAN_MCTRL_PRSFEN_Pos) /*!< 0x00000010 */ +#define CAN_MCTRL_PRSFEN CAN_MCTRL_PRSFEN_Msk /*!< Prohibit retransmission enable when sending fails enable */ +#define CAN_MCTRL_AEDEN_Pos (5U) +#define CAN_MCTRL_AEDEN_Msk (0x1U << CAN_MCTRL_AEDEN_Pos) /*!< 0x00000020 */ +#define CAN_MCTRL_AEDEN CAN_MCTRL_AEDEN_Msk /*!< Automatic exit doze mode enable */ +#define CAN_MCTRL_AEBOEN_Pos (6U) +#define CAN_MCTRL_AEBOEN_Msk (0x1U << CAN_MCTRL_AEBOEN_Pos) /*!< 0x00000040 */ +#define CAN_MCTRL_AEBOEN CAN_MCTRL_AEBOEN_Msk /*!< Automatic exit bus-off enable */ +#define CAN_MCTRL_TTCEN_Pos (7U) +#define CAN_MCTRL_TTCEN_Msk (0x1U << CAN_MCTRL_TTCEN_Pos) /*!< 0x00000080 */ +#define CAN_MCTRL_TTCEN CAN_MCTRL_TTCEN_Msk /*!< Time triggered communication mode enable */ +#define CAN_MCTRL_SPRST_Pos (15U) +#define CAN_MCTRL_SPRST_Msk (0x1U << CAN_MCTRL_SPRST_Pos) /*!< 0x00008000 */ +#define CAN_MCTRL_SPRST CAN_MCTRL_SPRST_Msk /*!< Software partial reset */ +#define CAN_MCTRL_PTD_Pos (16U) +#define CAN_MCTRL_PTD_Msk (0x1U << CAN_MCTRL_PTD_Pos) /*!< 0x00010000 */ +#define CAN_MCTRL_PTD CAN_MCTRL_PTD_Msk /*!< Prohibit trans when debug */ + +/******************* Bit definition for CAN_MSTS register *******************/ +#define CAN_MSTS_FZC_Pos (0U) +#define CAN_MSTS_FZC_Msk (0x1U << CAN_MSTS_FZC_Pos) /*!< 0x00000001 */ +#define CAN_MSTS_FZC CAN_MSTS_FZC_Msk /*!< Freeze mode confirm */ +#define CAN_MSTS_DZC_Pos (1U) +#define CAN_MSTS_DZC_Msk (0x1U << CAN_MSTS_DZC_Pos) /*!< 0x00000002 */ +#define CAN_MSTS_DZC CAN_MSTS_DZC_Msk /*!< Doze mode acknowledge */ +#define CAN_MSTS_EOIF_Pos (2U) +#define CAN_MSTS_EOIF_Msk (0x1U << CAN_MSTS_EOIF_Pos) /*!< 0x00000004 */ +#define CAN_MSTS_EOIF CAN_MSTS_EOIF_Msk /*!< Error occur interrupt flag */ +#define CAN_MSTS_QDZIF_Pos (3U) +#define CAN_MSTS_QDZIF_Msk (0x1U << CAN_MSTS_QDZIF_Pos) /*!< 0x00000008 */ +#define CAN_MSTS_QDZIF CAN_MSTS_QDZIF_Msk /*!< Exit doze mode interrupt flag */ +#define CAN_MSTS_EDZIF_Pos (4U) +#define CAN_MSTS_EDZIF_Msk (0x1U << CAN_MSTS_EDZIF_Pos) /*!< 0x00000010 */ +#define CAN_MSTS_EDZIF CAN_MSTS_EDZIF_Msk /*!< Enter doze mode interrupt flag */ +#define CAN_MSTS_CUSS_Pos (8U) +#define CAN_MSTS_CUSS_Msk (0x1U << CAN_MSTS_CUSS_Pos) /*!< 0x00000100 */ +#define CAN_MSTS_CUSS CAN_MSTS_CUSS_Msk /*!< Current transmit status */ +#define CAN_MSTS_CURS_Pos (9U) +#define CAN_MSTS_CURS_Msk (0x1U << CAN_MSTS_CURS_Pos) /*!< 0x00000200 */ +#define CAN_MSTS_CURS CAN_MSTS_CURS_Msk /*!< Current receive status */ +#define CAN_MSTS_LSAMPRX_Pos (10U) +#define CAN_MSTS_LSAMPRX_Msk (0x1U << CAN_MSTS_LSAMPRX_Pos) /*!< 0x00000400 */ +#define CAN_MSTS_LSAMPRX CAN_MSTS_LSAMPRX_Msk /*!< Last sample level on RX pin */ +#define CAN_MSTS_REALRX_Pos (11U) +#define CAN_MSTS_REALRX_Msk (0x1U << CAN_MSTS_REALRX_Pos) /*!< 0x00000800 */ +#define CAN_MSTS_REALRX CAN_MSTS_REALRX_Msk /*!< Real time level on RX pin */ + +/******************* Bit definition for CAN_TSTS register *******************/ +#define CAN_TSTS_TM0TCF_Pos (0U) +#define CAN_TSTS_TM0TCF_Msk (0x1U << CAN_TSTS_TM0TCF_Pos) /*!< 0x00000001 */ +#define CAN_TSTS_TM0TCF CAN_TSTS_TM0TCF_Msk /*!< Transmit mailbox 0 transmission completed flag */ +#define CAN_TSTS_TM0TSF_Pos (1U) +#define CAN_TSTS_TM0TSF_Msk (0x1U << CAN_TSTS_TM0TSF_Pos) /*!< 0x00000002 */ +#define CAN_TSTS_TM0TSF CAN_TSTS_TM0TSF_Msk /*!< Transmit mailbox 0 transmission success flag */ +#define CAN_TSTS_TM0ALF_Pos (2U) +#define CAN_TSTS_TM0ALF_Msk (0x1U << CAN_TSTS_TM0ALF_Pos) /*!< 0x00000004 */ +#define CAN_TSTS_TM0ALF CAN_TSTS_TM0ALF_Msk /*!< Transmit mailbox 0 arbitration lost flag */ +#define CAN_TSTS_TM0TEF_Pos (3U) +#define CAN_TSTS_TM0TEF_Msk (0x1U << CAN_TSTS_TM0TEF_Pos) /*!< 0x00000008 */ +#define CAN_TSTS_TM0TEF CAN_TSTS_TM0TEF_Msk /*!< Transmit mailbox 0 transmission error flag */ +#define CAN_TSTS_TM0CT_Pos (7U) +#define CAN_TSTS_TM0CT_Msk (0x1U << CAN_TSTS_TM0CT_Pos) /*!< 0x00000080 */ +#define CAN_TSTS_TM0CT CAN_TSTS_TM0CT_Msk /*!< Transmit mailbox 0 cancel transmit */ +#define CAN_TSTS_TM1TCF_Pos (8U) +#define CAN_TSTS_TM1TCF_Msk (0x1U << CAN_TSTS_TM1TCF_Pos) /*!< 0x00000100 */ +#define CAN_TSTS_TM1TCF CAN_TSTS_TM1TCF_Msk /*!< Transmit mailbox 1 transmission completed flag */ +#define CAN_TSTS_TM1TSF_Pos (9U) +#define CAN_TSTS_TM1TSF_Msk (0x1U << CAN_TSTS_TM1TSF_Pos) /*!< 0x00000200 */ +#define CAN_TSTS_TM1TSF CAN_TSTS_TM1TSF_Msk /*!< Transmit mailbox 1 transmission success flag */ +#define CAN_TSTS_TM1ALF_Pos (10U) +#define CAN_TSTS_TM1ALF_Msk (0x1U << CAN_TSTS_TM1ALF_Pos) /*!< 0x00000400 */ +#define CAN_TSTS_TM1ALF CAN_TSTS_TM1ALF_Msk /*!< Transmit mailbox 1 arbitration lost flag */ +#define CAN_TSTS_TM1TEF_Pos (11U) +#define CAN_TSTS_TM1TEF_Msk (0x1U << CAN_TSTS_TM1TEF_Pos) /*!< 0x00000800 */ +#define CAN_TSTS_TM1TEF CAN_TSTS_TM1TEF_Msk /*!< Transmit mailbox 1 transmission error flag */ +#define CAN_TSTS_TM1CT_Pos (15U) +#define CAN_TSTS_TM1CT_Msk (0x1U << CAN_TSTS_TM1CT_Pos) /*!< 0x00008000 */ +#define CAN_TSTS_TM1CT CAN_TSTS_TM1CT_Msk /*!< Transmit mailbox 1 cancel transmit */ +#define CAN_TSTS_TM2TCF_Pos (16U) +#define CAN_TSTS_TM2TCF_Msk (0x1U << CAN_TSTS_TM2TCF_Pos) /*!< 0x00010000 */ +#define CAN_TSTS_TM2TCF CAN_TSTS_TM2TCF_Msk /*!< Transmit mailbox 2 transmission completed flag */ +#define CAN_TSTS_TM2TSF_Pos (17U) +#define CAN_TSTS_TM2TSF_Msk (0x1U << CAN_TSTS_TM2TSF_Pos) /*!< 0x00020000 */ +#define CAN_TSTS_TM2TSF CAN_TSTS_TM2TSF_Msk /*!< Transmit mailbox 2 transmission success flag */ +#define CAN_TSTS_TM2ALF_Pos (18U) +#define CAN_TSTS_TM2ALF_Msk (0x1U << CAN_TSTS_TM2ALF_Pos) /*!< 0x00040000 */ +#define CAN_TSTS_TM2ALF CAN_TSTS_TM2ALF_Msk /*!< Transmit mailbox 2 arbitration lost flag */ +#define CAN_TSTS_TM2TEF_Pos (19U) +#define CAN_TSTS_TM2TEF_Msk (0x1U << CAN_TSTS_TM2TEF_Pos) /*!< 0x00080000 */ +#define CAN_TSTS_TM2TEF CAN_TSTS_TM2TEF_Msk /*!< Transmit mailbox 2 transmission error flag */ +#define CAN_TSTS_TM2CT_Pos (23U) +#define CAN_TSTS_TM2CT_Msk (0x1U << CAN_TSTS_TM2CT_Pos) /*!< 0x00800000 */ +#define CAN_TSTS_TM2CT CAN_TSTS_TM2CT_Msk /*!< Transmit mailbox 2 cancel transmit */ +#define CAN_TSTS_TMNR_Pos (24U) +#define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ +#define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ + +#define CAN_TSTS_TMEF_Pos (26U) +#define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ +#define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ +#define CAN_TSTS_TM0EF_Pos (26U) +#define CAN_TSTS_TM0EF_Msk (0x1U << CAN_TSTS_TM0EF_Pos) /*!< 0x04000000 */ +#define CAN_TSTS_TM0EF CAN_TSTS_TM0EF_Msk /*!< Transmit mailbox 0 empty flag */ +#define CAN_TSTS_TM1EF_Pos (27U) +#define CAN_TSTS_TM1EF_Msk (0x1U << CAN_TSTS_TM1EF_Pos) /*!< 0x08000000 */ +#define CAN_TSTS_TM1EF CAN_TSTS_TM1EF_Msk /*!< Transmit mailbox 1 empty flag */ +#define CAN_TSTS_TM2EF_Pos (28U) +#define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ +#define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ + +#define CAN_TSTS_TMLPF_Pos (29U) +#define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ +#define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ +#define CAN_TSTS_TM0LPF_Pos (29U) +#define CAN_TSTS_TM0LPF_Msk (0x1U << CAN_TSTS_TM0LPF_Pos) /*!< 0x20000000 */ +#define CAN_TSTS_TM0LPF CAN_TSTS_TM0LPF_Msk /*!< Transmit mailbox 0 lowest priority flag */ +#define CAN_TSTS_TM1LPF_Pos (30U) +#define CAN_TSTS_TM1LPF_Msk (0x1U << CAN_TSTS_TM1LPF_Pos) /*!< 0x40000000 */ +#define CAN_TSTS_TM1LPF CAN_TSTS_TM1LPF_Msk /*!< Transmit mailbox 1 lowest priority flag */ +#define CAN_TSTS_TM2LPF_Pos (31U) +#define CAN_TSTS_TM2LPF_Msk (0x1U << CAN_TSTS_TM2LPF_Pos) /*!< 0x80000000 */ +#define CAN_TSTS_TM2LPF CAN_TSTS_TM2LPF_Msk /*!< Transmit mailbox 2 lowest priority flag */ + +/******************* Bit definition for CAN_RF0 register ********************/ +#define CAN_RF0_RF0MN_Pos (0U) +#define CAN_RF0_RF0MN_Msk (0x3U << CAN_RF0_RF0MN_Pos) /*!< 0x00000003 */ +#define CAN_RF0_RF0MN CAN_RF0_RF0MN_Msk /*!< Receive FIFO 0 message num */ +#define CAN_RF0_RF0FF_Pos (3U) +#define CAN_RF0_RF0FF_Msk (0x1U << CAN_RF0_RF0FF_Pos) /*!< 0x00000008 */ +#define CAN_RF0_RF0FF CAN_RF0_RF0FF_Msk /*!< Receive FIFO 0 full flag */ +#define CAN_RF0_RF0OF_Pos (4U) +#define CAN_RF0_RF0OF_Msk (0x1U << CAN_RF0_RF0OF_Pos) /*!< 0x00000010 */ +#define CAN_RF0_RF0OF CAN_RF0_RF0OF_Msk /*!< Receive FIFO 0 overflow flag */ +#define CAN_RF0_RF0R_Pos (5U) +#define CAN_RF0_RF0R_Msk (0x1U << CAN_RF0_RF0R_Pos) /*!< 0x00000020 */ +#define CAN_RF0_RF0R CAN_RF0_RF0R_Msk /*!< Receive FIFO 0 release */ + +/******************* Bit definition for CAN_RF1 register ********************/ +#define CAN_RF1_RF1MN_Pos (0U) +#define CAN_RF1_RF1MN_Msk (0x3U << CAN_RF1_RF1MN_Pos) /*!< 0x00000003 */ +#define CAN_RF1_RF1MN CAN_RF1_RF1MN_Msk /*!< Receive FIFO 1 message num */ +#define CAN_RF1_RF1FF_Pos (3U) +#define CAN_RF1_RF1FF_Msk (0x1U << CAN_RF1_RF1FF_Pos) /*!< 0x00000008 */ +#define CAN_RF1_RF1FF CAN_RF1_RF1FF_Msk /*!< Receive FIFO 1 full flag */ +#define CAN_RF1_RF1OF_Pos (4U) +#define CAN_RF1_RF1OF_Msk (0x1U << CAN_RF1_RF1OF_Pos) /*!< 0x00000010 */ +#define CAN_RF1_RF1OF CAN_RF1_RF1OF_Msk /*!< Receive FIFO 1 overflow flag */ +#define CAN_RF1_RF1R_Pos (5U) +#define CAN_RF1_RF1R_Msk (0x1U << CAN_RF1_RF1R_Pos) /*!< 0x00000020 */ +#define CAN_RF1_RF1R CAN_RF1_RF1R_Msk /*!< Receive FIFO 1 release */ + +/****************** Bit definition for CAN_INTEN register *******************/ +#define CAN_INTEN_TCIEN_Pos (0U) +#define CAN_INTEN_TCIEN_Msk (0x1U << CAN_INTEN_TCIEN_Pos) /*!< 0x00000001 */ +#define CAN_INTEN_TCIEN CAN_INTEN_TCIEN_Msk /*!< Transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RF0MIEN_Pos (1U) +#define CAN_INTEN_RF0MIEN_Msk (0x1U << CAN_INTEN_RF0MIEN_Pos) /*!< 0x00000002 */ +#define CAN_INTEN_RF0MIEN CAN_INTEN_RF0MIEN_Msk /*!< FIFO 0 receive message interrupt enable */ +#define CAN_INTEN_RF0FIEN_Pos (2U) +#define CAN_INTEN_RF0FIEN_Msk (0x1U << CAN_INTEN_RF0FIEN_Pos) /*!< 0x00000004 */ +#define CAN_INTEN_RF0FIEN CAN_INTEN_RF0FIEN_Msk /*!< Receive FIFO 0 full interrupt enable */ +#define CAN_INTEN_RF0OIEN_Pos (3U) +#define CAN_INTEN_RF0OIEN_Msk (0x1U << CAN_INTEN_RF0OIEN_Pos) /*!< 0x00000008 */ +#define CAN_INTEN_RF0OIEN CAN_INTEN_RF0OIEN_Msk /*!< Receive FIFO 0 overflow interrupt enable */ +#define CAN_INTEN_RF1MIEN_Pos (4U) +#define CAN_INTEN_RF1MIEN_Msk (0x1U << CAN_INTEN_RF1MIEN_Pos) /*!< 0x00000010 */ +#define CAN_INTEN_RF1MIEN CAN_INTEN_RF1MIEN_Msk /*!< FIFO 1 receive message interrupt enable */ +#define CAN_INTEN_RF1FIEN_Pos (5U) +#define CAN_INTEN_RF1FIEN_Msk (0x1U << CAN_INTEN_RF1FIEN_Pos) /*!< 0x00000020 */ +#define CAN_INTEN_RF1FIEN CAN_INTEN_RF1FIEN_Msk /*!< Receive FIFO 1 full interrupt enable */ +#define CAN_INTEN_RF1OIEN_Pos (6U) +#define CAN_INTEN_RF1OIEN_Msk (0x1U << CAN_INTEN_RF1OIEN_Pos) /*!< 0x00000040 */ +#define CAN_INTEN_RF1OIEN CAN_INTEN_RF1OIEN_Msk /*!< Receive FIFO 1 overflow interrupt enable */ +#define CAN_INTEN_EAIEN_Pos (8U) +#define CAN_INTEN_EAIEN_Msk (0x1U << CAN_INTEN_EAIEN_Pos) /*!< 0x00000100 */ +#define CAN_INTEN_EAIEN CAN_INTEN_EAIEN_Msk /*!< Error active interrupt enable */ +#define CAN_INTEN_EPIEN_Pos (9U) +#define CAN_INTEN_EPIEN_Msk (0x1U << CAN_INTEN_EPIEN_Pos) /*!< 0x00000200 */ +#define CAN_INTEN_EPIEN CAN_INTEN_EPIEN_Msk /*!< Error passive interrupt enable */ +#define CAN_INTEN_BOIEN_Pos (10U) +#define CAN_INTEN_BOIEN_Msk (0x1U << CAN_INTEN_BOIEN_Pos) /*!< 0x00000400 */ +#define CAN_INTEN_BOIEN CAN_INTEN_BOIEN_Msk /*!< Bus-off interrupt enable */ +#define CAN_INTEN_ETRIEN_Pos (11U) +#define CAN_INTEN_ETRIEN_Msk (0x1U << CAN_INTEN_ETRIEN_Pos) /*!< 0x00000800 */ +#define CAN_INTEN_ETRIEN CAN_INTEN_ETRIEN_Msk /*!< Error type record interrupt enable */ +#define CAN_INTEN_EOIEN_Pos (15U) +#define CAN_INTEN_EOIEN_Msk (0x1U << CAN_INTEN_EOIEN_Pos) /*!< 0x00008000 */ +#define CAN_INTEN_EOIEN CAN_INTEN_EOIEN_Msk /*!< Error occur interrupt enable */ +#define CAN_INTEN_QDZIEN_Pos (16U) +#define CAN_INTEN_QDZIEN_Msk (0x1U << CAN_INTEN_QDZIEN_Pos) /*!< 0x00010000 */ +#define CAN_INTEN_QDZIEN CAN_INTEN_QDZIEN_Msk /*!< Quit doze mode interrupt enable */ +#define CAN_INTEN_EDZIEN_Pos (17U) +#define CAN_INTEN_EDZIEN_Msk (0x1U << CAN_INTEN_EDZIEN_Pos) /*!< 0x00020000 */ +#define CAN_INTEN_EDZIEN CAN_INTEN_EDZIEN_Msk /*!< Enter doze mode interrupt enable */ + +/******************* Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EAF_Pos (0U) +#define CAN_ESTS_EAF_Msk (0x1U << CAN_ESTS_EAF_Pos) /*!< 0x00000001 */ +#define CAN_ESTS_EAF CAN_ESTS_EAF_Msk /*!< Error active flag */ +#define CAN_ESTS_EPF_Pos (1U) +#define CAN_ESTS_EPF_Msk (0x1U << CAN_ESTS_EPF_Pos) /*!< 0x00000002 */ +#define CAN_ESTS_EPF CAN_ESTS_EPF_Msk /*!< Error passive flag */ +#define CAN_ESTS_BOF_Pos (2U) +#define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ +#define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ + +#define CAN_ESTS_ETR_Pos (4U) +#define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ +#define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ +#define CAN_ESTS_ETR_0 (0x1U << CAN_ESTS_ETR_Pos) /*!< 0x00000010 */ +#define CAN_ESTS_ETR_1 (0x2U << CAN_ESTS_ETR_Pos) /*!< 0x00000020 */ +#define CAN_ESTS_ETR_2 (0x4U << CAN_ESTS_ETR_Pos) /*!< 0x00000040 */ + +#define CAN_ESTS_TEC_Pos (16U) +#define CAN_ESTS_TEC_Msk (0xFFU << CAN_ESTS_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESTS_TEC CAN_ESTS_TEC_Msk /*!< Transmit error counter */ +#define CAN_ESTS_REC_Pos (24U) +#define CAN_ESTS_REC_Msk (0xFFU << CAN_ESTS_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESTS_REC CAN_ESTS_REC_Msk /*!< Receive error counter */ + +/******************* Bit definition for CAN_BTMG register ********************/ +#define CAN_BTMG_BRDIV_Pos (0U) +#define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ +#define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ + +#define CAN_BTMG_BTS1_Pos (16U) +#define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ +#define CAN_BTMG_BTS1_0 (0x1U << CAN_BTMG_BTS1_Pos) /*!< 0x00010000 */ +#define CAN_BTMG_BTS1_1 (0x2U << CAN_BTMG_BTS1_Pos) /*!< 0x00020000 */ +#define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ +#define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ + +#define CAN_BTMG_BTS2_Pos (20U) +#define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ +#define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ +#define CAN_BTMG_BTS2_0 (0x1U << CAN_BTMG_BTS2_Pos) /*!< 0x00100000 */ +#define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ +#define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ + +#define CAN_BTMG_RSAW_Pos (24U) +#define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ +#define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ +#define CAN_BTMG_RSAW_0 (0x1U << CAN_BTMG_RSAW_Pos) /*!< 0x01000000 */ +#define CAN_BTMG_RSAW_1 (0x2U << CAN_BTMG_RSAW_Pos) /*!< 0x02000000 */ + +#define CAN_BTMG_LBEN_Pos (30U) +#define CAN_BTMG_LBEN_Msk (0x1U << CAN_BTMG_LBEN_Pos) /*!< 0x40000000 */ +#define CAN_BTMG_LBEN CAN_BTMG_LBEN_Msk /*!< Loop back mode */ +#define CAN_BTMG_LOEN_Pos (31U) +#define CAN_BTMG_LOEN_Msk (0x1U << CAN_BTMG_LOEN_Pos) /*!< 0x80000000 */ +#define CAN_BTMG_LOEN CAN_BTMG_LOEN_Msk /*!< Listen-Only mode */ + +/*!< Mailbox registers */ +/******************* Bit definition for CAN_TMI0 register *******************/ +#define CAN_TMI0_TMSR_Pos (0U) +#define CAN_TMI0_TMSR_Msk (0x1U << CAN_TMI0_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI0_TMSR CAN_TMI0_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI0_TMFRSEL_Pos (1U) +#define CAN_TMI0_TMFRSEL_Msk (0x1U << CAN_TMI0_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI0_TMFRSEL CAN_TMI0_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI0_TMIDSEL_Pos (2U) +#define CAN_TMI0_TMIDSEL_Msk (0x1U << CAN_TMI0_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI0_TMIDSEL CAN_TMI0_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI0_TMEID_Pos (3U) +#define CAN_TMI0_TMEID_Msk (0x3FFFFU << CAN_TMI0_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI0_TMEID CAN_TMI0_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI0_TMSID_Pos (21U) +#define CAN_TMI0_TMSID_Msk (0x7FFU << CAN_TMI0_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI0_TMSID CAN_TMI0_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC0 register *******************/ +#define CAN_TMC0_TMDTBL_Pos (0U) +#define CAN_TMC0_TMDTBL_Msk (0xFU << CAN_TMC0_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC0_TMDTBL CAN_TMC0_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC0_TMTSTEN_Pos (8U) +#define CAN_TMC0_TMTSTEN_Msk (0x1U << CAN_TMC0_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC0_TMTSTEN CAN_TMC0_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC0_TMTS_Pos (16U) +#define CAN_TMC0_TMTS_Msk (0xFFFFU << CAN_TMC0_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC0_TMTS CAN_TMC0_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL0 register ******************/ +#define CAN_TMDTL0_TMDT0_Pos (0U) +#define CAN_TMDTL0_TMDT0_Msk (0xFFU << CAN_TMDTL0_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL0_TMDT0 CAN_TMDTL0_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL0_TMDT1_Pos (8U) +#define CAN_TMDTL0_TMDT1_Msk (0xFFU << CAN_TMDTL0_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL0_TMDT1 CAN_TMDTL0_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL0_TMDT2_Pos (16U) +#define CAN_TMDTL0_TMDT2_Msk (0xFFU << CAN_TMDTL0_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL0_TMDT2 CAN_TMDTL0_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL0_TMDT3_Pos (24U) +#define CAN_TMDTL0_TMDT3_Msk (0xFFU << CAN_TMDTL0_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL0_TMDT3 CAN_TMDTL0_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH0 register ******************/ +#define CAN_TMDTH0_TMDT4_Pos (0U) +#define CAN_TMDTH0_TMDT4_Msk (0xFFU << CAN_TMDTH0_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH0_TMDT4 CAN_TMDTH0_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH0_TMDT5_Pos (8U) +#define CAN_TMDTH0_TMDT5_Msk (0xFFU << CAN_TMDTH0_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH0_TMDT5 CAN_TMDTH0_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH0_TMDT6_Pos (16U) +#define CAN_TMDTH0_TMDT6_Msk (0xFFU << CAN_TMDTH0_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH0_TMDT6 CAN_TMDTH0_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH0_TMDT7_Pos (24U) +#define CAN_TMDTH0_TMDT7_Msk (0xFFU << CAN_TMDTH0_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH0_TMDT7 CAN_TMDTH0_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI1 register *******************/ +#define CAN_TMI1_TMSR_Pos (0U) +#define CAN_TMI1_TMSR_Msk (0x1U << CAN_TMI1_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI1_TMSR CAN_TMI1_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI1_TMFRSEL_Pos (1U) +#define CAN_TMI1_TMFRSEL_Msk (0x1U << CAN_TMI1_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI1_TMFRSEL CAN_TMI1_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI1_TMIDSEL_Pos (2U) +#define CAN_TMI1_TMIDSEL_Msk (0x1U << CAN_TMI1_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI1_TMIDSEL CAN_TMI1_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI1_TMEID_Pos (3U) +#define CAN_TMI1_TMEID_Msk (0x3FFFFU << CAN_TMI1_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI1_TMEID CAN_TMI1_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI1_TMSID_Pos (21U) +#define CAN_TMI1_TMSID_Msk (0x7FFU << CAN_TMI1_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI1_TMSID CAN_TMI1_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC1 register *******************/ +#define CAN_TMC1_TMDTBL_Pos (0U) +#define CAN_TMC1_TMDTBL_Msk (0xFU << CAN_TMC1_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC1_TMDTBL CAN_TMC1_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC1_TMTSTEN_Pos (8U) +#define CAN_TMC1_TMTSTEN_Msk (0x1U << CAN_TMC1_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC1_TMTSTEN CAN_TMC1_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC1_TMTS_Pos (16U) +#define CAN_TMC1_TMTS_Msk (0xFFFFU << CAN_TMC1_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC1_TMTS CAN_TMC1_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL1 register ******************/ +#define CAN_TMDTL1_TMDT0_Pos (0U) +#define CAN_TMDTL1_TMDT0_Msk (0xFFU << CAN_TMDTL1_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL1_TMDT0 CAN_TMDTL1_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL1_TMDT1_Pos (8U) +#define CAN_TMDTL1_TMDT1_Msk (0xFFU << CAN_TMDTL1_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL1_TMDT1 CAN_TMDTL1_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL1_TMDT2_Pos (16U) +#define CAN_TMDTL1_TMDT2_Msk (0xFFU << CAN_TMDTL1_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL1_TMDT2 CAN_TMDTL1_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL1_TMDT3_Pos (24U) +#define CAN_TMDTL1_TMDT3_Msk (0xFFU << CAN_TMDTL1_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL1_TMDT3 CAN_TMDTL1_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH1 register ******************/ +#define CAN_TMDTH1_TMDT4_Pos (0U) +#define CAN_TMDTH1_TMDT4_Msk (0xFFU << CAN_TMDTH1_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH1_TMDT4 CAN_TMDTH1_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH1_TMDT5_Pos (8U) +#define CAN_TMDTH1_TMDT5_Msk (0xFFU << CAN_TMDTH1_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH1_TMDT5 CAN_TMDTH1_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH1_TMDT6_Pos (16U) +#define CAN_TMDTH1_TMDT6_Msk (0xFFU << CAN_TMDTH1_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH1_TMDT6 CAN_TMDTH1_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH1_TMDT7_Pos (24U) +#define CAN_TMDTH1_TMDT7_Msk (0xFFU << CAN_TMDTH1_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH1_TMDT7 CAN_TMDTH1_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI2 register *******************/ +#define CAN_TMI2_TMSR_Pos (0U) +#define CAN_TMI2_TMSR_Msk (0x1U << CAN_TMI2_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI2_TMSR CAN_TMI2_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI2_TMFRSEL_Pos (1U) +#define CAN_TMI2_TMFRSEL_Msk (0x1U << CAN_TMI2_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI2_TMFRSEL CAN_TMI2_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI2_TMIDSEL_Pos (2U) +#define CAN_TMI2_TMIDSEL_Msk (0x1U << CAN_TMI2_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI2_TMIDSEL CAN_TMI2_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI2_TMEID_Pos (3U) +#define CAN_TMI2_TMEID_Msk (0x3FFFFU << CAN_TMI2_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI2_TMEID CAN_TMI2_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI2_TMSID_Pos (21U) +#define CAN_TMI2_TMSID_Msk (0x7FFU << CAN_TMI2_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI2_TMSID CAN_TMI2_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC2 register *******************/ +#define CAN_TMC2_TMDTBL_Pos (0U) +#define CAN_TMC2_TMDTBL_Msk (0xFU << CAN_TMC2_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC2_TMDTBL CAN_TMC2_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC2_TMTSTEN_Pos (8U) +#define CAN_TMC2_TMTSTEN_Msk (0x1U << CAN_TMC2_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC2_TMTSTEN CAN_TMC2_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC2_TMTS_Pos (16U) +#define CAN_TMC2_TMTS_Msk (0xFFFFU << CAN_TMC2_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC2_TMTS CAN_TMC2_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL2 register ******************/ +#define CAN_TMDTL2_TMDT0_Pos (0U) +#define CAN_TMDTL2_TMDT0_Msk (0xFFU << CAN_TMDTL2_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL2_TMDT0 CAN_TMDTL2_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL2_TMDT1_Pos (8U) +#define CAN_TMDTL2_TMDT1_Msk (0xFFU << CAN_TMDTL2_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL2_TMDT1 CAN_TMDTL2_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL2_TMDT2_Pos (16U) +#define CAN_TMDTL2_TMDT2_Msk (0xFFU << CAN_TMDTL2_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL2_TMDT2 CAN_TMDTL2_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL2_TMDT3_Pos (24U) +#define CAN_TMDTL2_TMDT3_Msk (0xFFU << CAN_TMDTL2_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL2_TMDT3 CAN_TMDTL2_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH2 register ******************/ +#define CAN_TMDTH2_TMDT4_Pos (0U) +#define CAN_TMDTH2_TMDT4_Msk (0xFFU << CAN_TMDTH2_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH2_TMDT4 CAN_TMDTH2_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH2_TMDT5_Pos (8U) +#define CAN_TMDTH2_TMDT5_Msk (0xFFU << CAN_TMDTH2_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH2_TMDT5 CAN_TMDTH2_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH2_TMDT6_Pos (16U) +#define CAN_TMDTH2_TMDT6_Msk (0xFFU << CAN_TMDTH2_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH2_TMDT6 CAN_TMDTH2_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH2_TMDT7_Pos (24U) +#define CAN_TMDTH2_TMDT7_Msk (0xFFU << CAN_TMDTH2_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH2_TMDT7 CAN_TMDTH2_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_RFI0 register *******************/ +#define CAN_RFI0_RFFRI_Pos (1U) +#define CAN_RFI0_RFFRI_Msk (0x1U << CAN_RFI0_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI0_RFFRI CAN_RFI0_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI0_RFIDI_Pos (2U) +#define CAN_RFI0_RFIDI_Msk (0x1U << CAN_RFI0_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI0_RFIDI CAN_RFI0_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI0_RFEID_Pos (3U) +#define CAN_RFI0_RFEID_Msk (0x3FFFFU << CAN_RFI0_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI0_RFEID CAN_RFI0_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI0_RFSID_Pos (21U) +#define CAN_RFI0_RFSID_Msk (0x7FFU << CAN_RFI0_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI0_RFSID CAN_RFI0_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC0 register *******************/ +#define CAN_RFC0_RFDTL_Pos (0U) +#define CAN_RFC0_RFDTL_Msk (0xFU << CAN_RFC0_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC0_RFDTL CAN_RFC0_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC0_RFFMN_Pos (8U) +#define CAN_RFC0_RFFMN_Msk (0xFFU << CAN_RFC0_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC0_RFFMN CAN_RFC0_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC0_RFTS_Pos (16U) +#define CAN_RFC0_RFTS_Msk (0xFFFFU << CAN_RFC0_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC0_RFTS CAN_RFC0_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL0 register ******************/ +#define CAN_RFDTL0_RFDT0_Pos (0U) +#define CAN_RFDTL0_RFDT0_Msk (0xFFU << CAN_RFDTL0_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL0_RFDT0 CAN_RFDTL0_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL0_RFDT1_Pos (8U) +#define CAN_RFDTL0_RFDT1_Msk (0xFFU << CAN_RFDTL0_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL0_RFDT1 CAN_RFDTL0_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL0_RFDT2_Pos (16U) +#define CAN_RFDTL0_RFDT2_Msk (0xFFU << CAN_RFDTL0_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL0_RFDT2 CAN_RFDTL0_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL0_RFDT3_Pos (24U) +#define CAN_RFDTL0_RFDT3_Msk (0xFFU << CAN_RFDTL0_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL0_RFDT3 CAN_RFDTL0_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH0 register ******************/ +#define CAN_RFDTH0_RFDT4_Pos (0U) +#define CAN_RFDTH0_RFDT4_Msk (0xFFU << CAN_RFDTH0_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH0_RFDT4 CAN_RFDTH0_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH0_RFDT5_Pos (8U) +#define CAN_RFDTH0_RFDT5_Msk (0xFFU << CAN_RFDTH0_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH0_RFDT5 CAN_RFDTH0_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH0_RFDT6_Pos (16U) +#define CAN_RFDTH0_RFDT6_Msk (0xFFU << CAN_RFDTH0_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH0_RFDT6 CAN_RFDTH0_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH0_RFDT7_Pos (24U) +#define CAN_RFDTH0_RFDT7_Msk (0xFFU << CAN_RFDTH0_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH0_RFDT7 CAN_RFDTH0_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/******************* Bit definition for CAN_RFI1 register *******************/ +#define CAN_RFI1_RFFRI_Pos (1U) +#define CAN_RFI1_RFFRI_Msk (0x1U << CAN_RFI1_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI1_RFFRI CAN_RFI1_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI1_RFIDI_Pos (2U) +#define CAN_RFI1_RFIDI_Msk (0x1U << CAN_RFI1_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI1_RFIDI CAN_RFI1_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI1_RFEID_Pos (3U) +#define CAN_RFI1_RFEID_Msk (0x3FFFFU << CAN_RFI1_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI1_RFEID CAN_RFI1_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI1_RFSID_Pos (21U) +#define CAN_RFI1_RFSID_Msk (0x7FFU << CAN_RFI1_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI1_RFSID CAN_RFI1_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC1 register *******************/ +#define CAN_RFC1_RFDTL_Pos (0U) +#define CAN_RFC1_RFDTL_Msk (0xFU << CAN_RFC1_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC1_RFDTL CAN_RFC1_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC1_RFFMN_Pos (8U) +#define CAN_RFC1_RFFMN_Msk (0xFFU << CAN_RFC1_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC1_RFFMN CAN_RFC1_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC1_RFTS_Pos (16U) +#define CAN_RFC1_RFTS_Msk (0xFFFFU << CAN_RFC1_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC1_RFTS CAN_RFC1_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL1 register ******************/ +#define CAN_RFDTL1_RFDT0_Pos (0U) +#define CAN_RFDTL1_RFDT0_Msk (0xFFU << CAN_RFDTL1_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL1_RFDT0 CAN_RFDTL1_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL1_RFDT1_Pos (8U) +#define CAN_RFDTL1_RFDT1_Msk (0xFFU << CAN_RFDTL1_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL1_RFDT1 CAN_RFDTL1_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL1_RFDT2_Pos (16U) +#define CAN_RFDTL1_RFDT2_Msk (0xFFU << CAN_RFDTL1_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL1_RFDT2 CAN_RFDTL1_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL1_RFDT3_Pos (24U) +#define CAN_RFDTL1_RFDT3_Msk (0xFFU << CAN_RFDTL1_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL1_RFDT3 CAN_RFDTL1_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH1 register ******************/ +#define CAN_RFDTH1_RFDT4_Pos (0U) +#define CAN_RFDTH1_RFDT4_Msk (0xFFU << CAN_RFDTH1_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH1_RFDT4 CAN_RFDTH1_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH1_RFDT5_Pos (8U) +#define CAN_RFDTH1_RFDT5_Msk (0xFFU << CAN_RFDTH1_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH1_RFDT5 CAN_RFDTH1_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH1_RFDT6_Pos (16U) +#define CAN_RFDTH1_RFDT6_Msk (0xFFU << CAN_RFDTH1_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH1_RFDT6 CAN_RFDTH1_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH1_RFDT7_Pos (24U) +#define CAN_RFDTH1_RFDT7_Msk (0xFFU << CAN_RFDTH1_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH1_RFDT7 CAN_RFDTH1_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/*!< CAN filter registers */ +/****************** Bit definition for CAN_FCTRL register *******************/ +#define CAN_FCTRL_FCS_Pos (0U) +#define CAN_FCTRL_FCS_Msk (0x1U << CAN_FCTRL_FCS_Pos) /*!< 0x00000001 */ +#define CAN_FCTRL_FCS CAN_FCTRL_FCS_Msk /*!< Filter configuration switch */ + +/****************** Bit definition for CAN_FMCFG register *******************/ +#define CAN_FMCFG_FMSEL_Pos (0U) +#define CAN_FMCFG_FMSEL_Msk (0x3FFFU << CAN_FMCFG_FMSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FMCFG_FMSEL CAN_FMCFG_FMSEL_Msk /*!< Filter mode select */ +#define CAN_FMCFG_FMSEL0_Pos (0U) +#define CAN_FMCFG_FMSEL0_Msk (0x1U << CAN_FMCFG_FMSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FMCFG_FMSEL0 CAN_FMCFG_FMSEL0_Msk /*!< Filter mode select for filter 0 */ +#define CAN_FMCFG_FMSEL1_Pos (1U) +#define CAN_FMCFG_FMSEL1_Msk (0x1U << CAN_FMCFG_FMSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FMCFG_FMSEL1 CAN_FMCFG_FMSEL1_Msk /*!< Filter mode select for filter 1 */ +#define CAN_FMCFG_FMSEL2_Pos (2U) +#define CAN_FMCFG_FMSEL2_Msk (0x1U << CAN_FMCFG_FMSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FMCFG_FMSEL2 CAN_FMCFG_FMSEL2_Msk /*!< Filter mode select for filter 2 */ +#define CAN_FMCFG_FMSEL3_Pos (3U) +#define CAN_FMCFG_FMSEL3_Msk (0x1U << CAN_FMCFG_FMSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FMCFG_FMSEL3 CAN_FMCFG_FMSEL3_Msk /*!< Filter mode select for filter 3 */ +#define CAN_FMCFG_FMSEL4_Pos (4U) +#define CAN_FMCFG_FMSEL4_Msk (0x1U << CAN_FMCFG_FMSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FMCFG_FMSEL4 CAN_FMCFG_FMSEL4_Msk /*!< Filter mode select for filter 4 */ +#define CAN_FMCFG_FMSEL5_Pos (5U) +#define CAN_FMCFG_FMSEL5_Msk (0x1U << CAN_FMCFG_FMSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FMCFG_FMSEL5 CAN_FMCFG_FMSEL5_Msk /*!< Filter mode select for filter 5 */ +#define CAN_FMCFG_FMSEL6_Pos (6U) +#define CAN_FMCFG_FMSEL6_Msk (0x1U << CAN_FMCFG_FMSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FMCFG_FMSEL6 CAN_FMCFG_FMSEL6_Msk /*!< Filter mode select for filter 6 */ +#define CAN_FMCFG_FMSEL7_Pos (7U) +#define CAN_FMCFG_FMSEL7_Msk (0x1U << CAN_FMCFG_FMSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FMCFG_FMSEL7 CAN_FMCFG_FMSEL7_Msk /*!< Filter mode select for filter 7 */ +#define CAN_FMCFG_FMSEL8_Pos (8U) +#define CAN_FMCFG_FMSEL8_Msk (0x1U << CAN_FMCFG_FMSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FMCFG_FMSEL8 CAN_FMCFG_FMSEL8_Msk /*!< Filter mode select for filter 8 */ +#define CAN_FMCFG_FMSEL9_Pos (9U) +#define CAN_FMCFG_FMSEL9_Msk (0x1U << CAN_FMCFG_FMSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FMCFG_FMSEL9 CAN_FMCFG_FMSEL9_Msk /*!< Filter mode select for filter 9 */ +#define CAN_FMCFG_FMSEL10_Pos (10U) +#define CAN_FMCFG_FMSEL10_Msk (0x1U << CAN_FMCFG_FMSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FMCFG_FMSEL10 CAN_FMCFG_FMSEL10_Msk /*!< Filter mode select for filter 10 */ +#define CAN_FMCFG_FMSEL11_Pos (11U) +#define CAN_FMCFG_FMSEL11_Msk (0x1U << CAN_FMCFG_FMSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FMCFG_FMSEL11 CAN_FMCFG_FMSEL11_Msk /*!< Filter mode select for filter 11 */ +#define CAN_FMCFG_FMSEL12_Pos (12U) +#define CAN_FMCFG_FMSEL12_Msk (0x1U << CAN_FMCFG_FMSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FMCFG_FMSEL12 CAN_FMCFG_FMSEL12_Msk /*!< Filter mode select for filter 12 */ +#define CAN_FMCFG_FMSEL13_Pos (13U) +#define CAN_FMCFG_FMSEL13_Msk (0x1U << CAN_FMCFG_FMSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FMCFG_FMSEL13 CAN_FMCFG_FMSEL13_Msk /*!< Filter mode select for filter 13 */ + +/****************** Bit definition for CAN_FBWCFG register ******************/ +#define CAN_FBWCFG_FBWSEL_Pos (0U) +#define CAN_FBWCFG_FBWSEL_Msk (0x3FFFU << CAN_FBWCFG_FBWSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FBWCFG_FBWSEL CAN_FBWCFG_FBWSEL_Msk /*!< Filter bit width select */ +#define CAN_FBWCFG_FBWSEL0_Pos (0U) +#define CAN_FBWCFG_FBWSEL0_Msk (0x1U << CAN_FBWCFG_FBWSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FBWCFG_FBWSEL0 CAN_FBWCFG_FBWSEL0_Msk /*!< Filter bit width select for filter 0 */ +#define CAN_FBWCFG_FBWSEL1_Pos (1U) +#define CAN_FBWCFG_FBWSEL1_Msk (0x1U << CAN_FBWCFG_FBWSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FBWCFG_FBWSEL1 CAN_FBWCFG_FBWSEL1_Msk /*!< Filter bit width select for filter 1 */ +#define CAN_FBWCFG_FBWSEL2_Pos (2U) +#define CAN_FBWCFG_FBWSEL2_Msk (0x1U << CAN_FBWCFG_FBWSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FBWCFG_FBWSEL2 CAN_FBWCFG_FBWSEL2_Msk /*!< Filter bit width select for filter 2 */ +#define CAN_FBWCFG_FBWSEL3_Pos (3U) +#define CAN_FBWCFG_FBWSEL3_Msk (0x1U << CAN_FBWCFG_FBWSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FBWCFG_FBWSEL3 CAN_FBWCFG_FBWSEL3_Msk /*!< Filter bit width select for filter 3 */ +#define CAN_FBWCFG_FBWSEL4_Pos (4U) +#define CAN_FBWCFG_FBWSEL4_Msk (0x1U << CAN_FBWCFG_FBWSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FBWCFG_FBWSEL4 CAN_FBWCFG_FBWSEL4_Msk /*!< Filter bit width select for filter 4 */ +#define CAN_FBWCFG_FBWSEL5_Pos (5U) +#define CAN_FBWCFG_FBWSEL5_Msk (0x1U << CAN_FBWCFG_FBWSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FBWCFG_FBWSEL5 CAN_FBWCFG_FBWSEL5_Msk /*!< Filter bit width select for filter 5 */ +#define CAN_FBWCFG_FBWSEL6_Pos (6U) +#define CAN_FBWCFG_FBWSEL6_Msk (0x1U << CAN_FBWCFG_FBWSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FBWCFG_FBWSEL6 CAN_FBWCFG_FBWSEL6_Msk /*!< Filter bit width select for filter 6 */ +#define CAN_FBWCFG_FBWSEL7_Pos (7U) +#define CAN_FBWCFG_FBWSEL7_Msk (0x1U << CAN_FBWCFG_FBWSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FBWCFG_FBWSEL7 CAN_FBWCFG_FBWSEL7_Msk /*!< Filter bit width select for filter 7 */ +#define CAN_FBWCFG_FBWSEL8_Pos (8U) +#define CAN_FBWCFG_FBWSEL8_Msk (0x1U << CAN_FBWCFG_FBWSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FBWCFG_FBWSEL8 CAN_FBWCFG_FBWSEL8_Msk /*!< Filter bit width select for filter 8 */ +#define CAN_FBWCFG_FBWSEL9_Pos (9U) +#define CAN_FBWCFG_FBWSEL9_Msk (0x1U << CAN_FBWCFG_FBWSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FBWCFG_FBWSEL9 CAN_FBWCFG_FBWSEL9_Msk /*!< Filter bit width select for filter 9 */ +#define CAN_FBWCFG_FBWSEL10_Pos (10U) +#define CAN_FBWCFG_FBWSEL10_Msk (0x1U << CAN_FBWCFG_FBWSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FBWCFG_FBWSEL10 CAN_FBWCFG_FBWSEL10_Msk /*!< Filter bit width select for filter 10 */ +#define CAN_FBWCFG_FBWSEL11_Pos (11U) +#define CAN_FBWCFG_FBWSEL11_Msk (0x1U << CAN_FBWCFG_FBWSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FBWCFG_FBWSEL11 CAN_FBWCFG_FBWSEL11_Msk /*!< Filter bit width select for filter 11 */ +#define CAN_FBWCFG_FBWSEL12_Pos (12U) +#define CAN_FBWCFG_FBWSEL12_Msk (0x1U << CAN_FBWCFG_FBWSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FBWCFG_FBWSEL12 CAN_FBWCFG_FBWSEL12_Msk /*!< Filter bit width select for filter 12 */ +#define CAN_FBWCFG_FBWSEL13_Pos (13U) +#define CAN_FBWCFG_FBWSEL13_Msk (0x1U << CAN_FBWCFG_FBWSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FBWCFG_FBWSEL13 CAN_FBWCFG_FBWSEL13_Msk /*!< Filter bit width select for filter 13 */ + +/******************* Bit definition for CAN_FRF register ********************/ +#define CAN_FRF_FRFSEL_Pos (0U) +#define CAN_FRF_FRFSEL_Msk (0x3FFFU << CAN_FRF_FRFSEL_Pos) /*!< 0x00003FFF */ +#define CAN_FRF_FRFSEL CAN_FRF_FRFSEL_Msk /*!< Filter relation FIFO select */ +#define CAN_FRF_FRFSEL0_Pos (0U) +#define CAN_FRF_FRFSEL0_Msk (0x1U << CAN_FRF_FRFSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FRF_FRFSEL0 CAN_FRF_FRFSEL0_Msk /*!< Filter relation FIFO select for filter 0 */ +#define CAN_FRF_FRFSEL1_Pos (1U) +#define CAN_FRF_FRFSEL1_Msk (0x1U << CAN_FRF_FRFSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FRF_FRFSEL1 CAN_FRF_FRFSEL1_Msk /*!< Filter relation FIFO select for filter 1 */ +#define CAN_FRF_FRFSEL2_Pos (2U) +#define CAN_FRF_FRFSEL2_Msk (0x1U << CAN_FRF_FRFSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FRF_FRFSEL2 CAN_FRF_FRFSEL2_Msk /*!< Filter relation FIFO select for filter 2 */ +#define CAN_FRF_FRFSEL3_Pos (3U) +#define CAN_FRF_FRFSEL3_Msk (0x1U << CAN_FRF_FRFSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FRF_FRFSEL3 CAN_FRF_FRFSEL3_Msk /*!< Filter relation FIFO select for filter 3 */ +#define CAN_FRF_FRFSEL4_Pos (4U) +#define CAN_FRF_FRFSEL4_Msk (0x1U << CAN_FRF_FRFSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FRF_FRFSEL4 CAN_FRF_FRFSEL4_Msk /*!< Filter relation FIFO select for filter 4 */ +#define CAN_FRF_FRFSEL5_Pos (5U) +#define CAN_FRF_FRFSEL5_Msk (0x1U << CAN_FRF_FRFSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FRF_FRFSEL5 CAN_FRF_FRFSEL5_Msk /*!< Filter relation FIFO select for filter 5 */ +#define CAN_FRF_FRFSEL6_Pos (6U) +#define CAN_FRF_FRFSEL6_Msk (0x1U << CAN_FRF_FRFSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FRF_FRFSEL6 CAN_FRF_FRFSEL6_Msk /*!< Filter relation FIFO select for filter 6 */ +#define CAN_FRF_FRFSEL7_Pos (7U) +#define CAN_FRF_FRFSEL7_Msk (0x1U << CAN_FRF_FRFSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FRF_FRFSEL7 CAN_FRF_FRFSEL7_Msk /*!< Filter relation FIFO select for filter 7 */ +#define CAN_FRF_FRFSEL8_Pos (8U) +#define CAN_FRF_FRFSEL8_Msk (0x1U << CAN_FRF_FRFSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FRF_FRFSEL8 CAN_FRF_FRFSEL8_Msk /*!< Filter relation FIFO select for filter 8 */ +#define CAN_FRF_FRFSEL9_Pos (9U) +#define CAN_FRF_FRFSEL9_Msk (0x1U << CAN_FRF_FRFSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FRF_FRFSEL9 CAN_FRF_FRFSEL9_Msk /*!< Filter relation FIFO select for filter 9 */ +#define CAN_FRF_FRFSEL10_Pos (10U) +#define CAN_FRF_FRFSEL10_Msk (0x1U << CAN_FRF_FRFSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FRF_FRFSEL10 CAN_FRF_FRFSEL10_Msk /*!< Filter relation FIFO select for filter 10 */ +#define CAN_FRF_FRFSEL11_Pos (11U) +#define CAN_FRF_FRFSEL11_Msk (0x1U << CAN_FRF_FRFSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FRF_FRFSEL11 CAN_FRF_FRFSEL11_Msk /*!< Filter relation FIFO select for filter 11 */ +#define CAN_FRF_FRFSEL12_Pos (12U) +#define CAN_FRF_FRFSEL12_Msk (0x1U << CAN_FRF_FRFSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FRF_FRFSEL12 CAN_FRF_FRFSEL12_Msk /*!< Filter relation FIFO select for filter 12 */ +#define CAN_FRF_FRFSEL13_Pos (13U) +#define CAN_FRF_FRFSEL13_Msk (0x1U << CAN_FRF_FRFSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FRF_FRFSEL13 CAN_FRF_FRFSEL13_Msk /*!< Filter relation FIFO select for filter 13 */ + +/****************** Bit definition for CAN_FACFG register *******************/ +#define CAN_FACFG_FAEN_Pos (0U) +#define CAN_FACFG_FAEN_Msk (0x3FFFU << CAN_FACFG_FAEN_Pos) /*!< 0x00003FFF */ +#define CAN_FACFG_FAEN CAN_FACFG_FAEN_Msk /*!< Filter active enable */ +#define CAN_FACFG_FAEN0_Pos (0U) +#define CAN_FACFG_FAEN0_Msk (0x1U << CAN_FACFG_FAEN0_Pos) /*!< 0x00000001 */ +#define CAN_FACFG_FAEN0 CAN_FACFG_FAEN0_Msk /*!< Filter 0 active enable */ +#define CAN_FACFG_FAEN1_Pos (1U) +#define CAN_FACFG_FAEN1_Msk (0x1U << CAN_FACFG_FAEN1_Pos) /*!< 0x00000002 */ +#define CAN_FACFG_FAEN1 CAN_FACFG_FAEN1_Msk /*!< Filter 1 active enable */ +#define CAN_FACFG_FAEN2_Pos (2U) +#define CAN_FACFG_FAEN2_Msk (0x1U << CAN_FACFG_FAEN2_Pos) /*!< 0x00000004 */ +#define CAN_FACFG_FAEN2 CAN_FACFG_FAEN2_Msk /*!< Filter 2 active enable */ +#define CAN_FACFG_FAEN3_Pos (3U) +#define CAN_FACFG_FAEN3_Msk (0x1U << CAN_FACFG_FAEN3_Pos) /*!< 0x00000008 */ +#define CAN_FACFG_FAEN3 CAN_FACFG_FAEN3_Msk /*!< Filter 3 active enable */ +#define CAN_FACFG_FAEN4_Pos (4U) +#define CAN_FACFG_FAEN4_Msk (0x1U << CAN_FACFG_FAEN4_Pos) /*!< 0x00000010 */ +#define CAN_FACFG_FAEN4 CAN_FACFG_FAEN4_Msk /*!< Filter 4 active enable */ +#define CAN_FACFG_FAEN5_Pos (5U) +#define CAN_FACFG_FAEN5_Msk (0x1U << CAN_FACFG_FAEN5_Pos) /*!< 0x00000020 */ +#define CAN_FACFG_FAEN5 CAN_FACFG_FAEN5_Msk /*!< Filter 5 active enable */ +#define CAN_FACFG_FAEN6_Pos (6U) +#define CAN_FACFG_FAEN6_Msk (0x1U << CAN_FACFG_FAEN6_Pos) /*!< 0x00000040 */ +#define CAN_FACFG_FAEN6 CAN_FACFG_FAEN6_Msk /*!< Filter 6 active enable */ +#define CAN_FACFG_FAEN7_Pos (7U) +#define CAN_FACFG_FAEN7_Msk (0x1U << CAN_FACFG_FAEN7_Pos) /*!< 0x00000080 */ +#define CAN_FACFG_FAEN7 CAN_FACFG_FAEN7_Msk /*!< Filter 7 active enable */ +#define CAN_FACFG_FAEN8_Pos (8U) +#define CAN_FACFG_FAEN8_Msk (0x1U << CAN_FACFG_FAEN8_Pos) /*!< 0x00000100 */ +#define CAN_FACFG_FAEN8 CAN_FACFG_FAEN8_Msk /*!< Filter 8 active enable */ +#define CAN_FACFG_FAEN9_Pos (9U) +#define CAN_FACFG_FAEN9_Msk (0x1U << CAN_FACFG_FAEN9_Pos) /*!< 0x00000200 */ +#define CAN_FACFG_FAEN9 CAN_FACFG_FAEN9_Msk /*!< Filter 9 active enable */ +#define CAN_FACFG_FAEN10_Pos (10U) +#define CAN_FACFG_FAEN10_Msk (0x1U << CAN_FACFG_FAEN10_Pos) /*!< 0x00000400 */ +#define CAN_FACFG_FAEN10 CAN_FACFG_FAEN10_Msk /*!< Filter 10 active enable */ +#define CAN_FACFG_FAEN11_Pos (11U) +#define CAN_FACFG_FAEN11_Msk (0x1U << CAN_FACFG_FAEN11_Pos) /*!< 0x00000800 */ +#define CAN_FACFG_FAEN11 CAN_FACFG_FAEN11_Msk /*!< Filter 11 active enable */ +#define CAN_FACFG_FAEN12_Pos (12U) +#define CAN_FACFG_FAEN12_Msk (0x1U << CAN_FACFG_FAEN12_Pos) /*!< 0x00001000 */ +#define CAN_FACFG_FAEN12 CAN_FACFG_FAEN12_Msk /*!< Filter 12 active enable */ +#define CAN_FACFG_FAEN13_Pos (13U) +#define CAN_FACFG_FAEN13_Msk (0x1U << CAN_FACFG_FAEN13_Pos) /*!< 0x00002000 */ +#define CAN_FACFG_FAEN13 CAN_FACFG_FAEN13_Msk /*!< Filter 13 active enable */ + +/****************** Bit definition for CAN_F0FB1 register *******************/ +#define CAN_F0FB1_FFDB0_Pos (0U) +#define CAN_F0FB1_FFDB0_Msk (0x1U << CAN_F0FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB1_FFDB0 CAN_F0FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB1_FFDB1_Pos (1U) +#define CAN_F0FB1_FFDB1_Msk (0x1U << CAN_F0FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB1_FFDB1 CAN_F0FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB1_FFDB2_Pos (2U) +#define CAN_F0FB1_FFDB2_Msk (0x1U << CAN_F0FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB1_FFDB2 CAN_F0FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB1_FFDB3_Pos (3U) +#define CAN_F0FB1_FFDB3_Msk (0x1U << CAN_F0FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB1_FFDB3 CAN_F0FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB1_FFDB4_Pos (4U) +#define CAN_F0FB1_FFDB4_Msk (0x1U << CAN_F0FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB1_FFDB4 CAN_F0FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB1_FFDB5_Pos (5U) +#define CAN_F0FB1_FFDB5_Msk (0x1U << CAN_F0FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB1_FFDB5 CAN_F0FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB1_FFDB6_Pos (6U) +#define CAN_F0FB1_FFDB6_Msk (0x1U << CAN_F0FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB1_FFDB6 CAN_F0FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB1_FFDB7_Pos (7U) +#define CAN_F0FB1_FFDB7_Msk (0x1U << CAN_F0FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB1_FFDB7 CAN_F0FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB1_FFDB8_Pos (8U) +#define CAN_F0FB1_FFDB8_Msk (0x1U << CAN_F0FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB1_FFDB8 CAN_F0FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB1_FFDB9_Pos (9U) +#define CAN_F0FB1_FFDB9_Msk (0x1U << CAN_F0FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB1_FFDB9 CAN_F0FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB1_FFDB10_Pos (10U) +#define CAN_F0FB1_FFDB10_Msk (0x1U << CAN_F0FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB1_FFDB10 CAN_F0FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB1_FFDB11_Pos (11U) +#define CAN_F0FB1_FFDB11_Msk (0x1U << CAN_F0FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB1_FFDB11 CAN_F0FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB1_FFDB12_Pos (12U) +#define CAN_F0FB1_FFDB12_Msk (0x1U << CAN_F0FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB1_FFDB12 CAN_F0FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB1_FFDB13_Pos (13U) +#define CAN_F0FB1_FFDB13_Msk (0x1U << CAN_F0FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB1_FFDB13 CAN_F0FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB1_FFDB14_Pos (14U) +#define CAN_F0FB1_FFDB14_Msk (0x1U << CAN_F0FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB1_FFDB14 CAN_F0FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB1_FFDB15_Pos (15U) +#define CAN_F0FB1_FFDB15_Msk (0x1U << CAN_F0FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB1_FFDB15 CAN_F0FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB1_FFDB16_Pos (16U) +#define CAN_F0FB1_FFDB16_Msk (0x1U << CAN_F0FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB1_FFDB16 CAN_F0FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB1_FFDB17_Pos (17U) +#define CAN_F0FB1_FFDB17_Msk (0x1U << CAN_F0FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB1_FFDB17 CAN_F0FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB1_FFDB18_Pos (18U) +#define CAN_F0FB1_FFDB18_Msk (0x1U << CAN_F0FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB1_FFDB18 CAN_F0FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB1_FFDB19_Pos (19U) +#define CAN_F0FB1_FFDB19_Msk (0x1U << CAN_F0FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB1_FFDB19 CAN_F0FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB1_FFDB20_Pos (20U) +#define CAN_F0FB1_FFDB20_Msk (0x1U << CAN_F0FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB1_FFDB20 CAN_F0FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB1_FFDB21_Pos (21U) +#define CAN_F0FB1_FFDB21_Msk (0x1U << CAN_F0FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB1_FFDB21 CAN_F0FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB1_FFDB22_Pos (22U) +#define CAN_F0FB1_FFDB22_Msk (0x1U << CAN_F0FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB1_FFDB22 CAN_F0FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB1_FFDB23_Pos (23U) +#define CAN_F0FB1_FFDB23_Msk (0x1U << CAN_F0FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB1_FFDB23 CAN_F0FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB1_FFDB24_Pos (24U) +#define CAN_F0FB1_FFDB24_Msk (0x1U << CAN_F0FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB1_FFDB24 CAN_F0FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB1_FFDB25_Pos (25U) +#define CAN_F0FB1_FFDB25_Msk (0x1U << CAN_F0FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB1_FFDB25 CAN_F0FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB1_FFDB26_Pos (26U) +#define CAN_F0FB1_FFDB26_Msk (0x1U << CAN_F0FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB1_FFDB26 CAN_F0FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB1_FFDB27_Pos (27U) +#define CAN_F0FB1_FFDB27_Msk (0x1U << CAN_F0FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB1_FFDB27 CAN_F0FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB1_FFDB28_Pos (28U) +#define CAN_F0FB1_FFDB28_Msk (0x1U << CAN_F0FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB1_FFDB28 CAN_F0FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB1_FFDB29_Pos (29U) +#define CAN_F0FB1_FFDB29_Msk (0x1U << CAN_F0FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB1_FFDB29 CAN_F0FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB1_FFDB30_Pos (30U) +#define CAN_F0FB1_FFDB30_Msk (0x1U << CAN_F0FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB1_FFDB30 CAN_F0FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB1_FFDB31_Pos (31U) +#define CAN_F0FB1_FFDB31_Msk (0x1U << CAN_F0FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB1_FFDB31 CAN_F0FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB1 register *******************/ +#define CAN_F1FB1_FFDB0_Pos (0U) +#define CAN_F1FB1_FFDB0_Msk (0x1U << CAN_F1FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB1_FFDB0 CAN_F1FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB1_FFDB1_Pos (1U) +#define CAN_F1FB1_FFDB1_Msk (0x1U << CAN_F1FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB1_FFDB1 CAN_F1FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB1_FFDB2_Pos (2U) +#define CAN_F1FB1_FFDB2_Msk (0x1U << CAN_F1FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB1_FFDB2 CAN_F1FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB1_FFDB3_Pos (3U) +#define CAN_F1FB1_FFDB3_Msk (0x1U << CAN_F1FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB1_FFDB3 CAN_F1FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB1_FFDB4_Pos (4U) +#define CAN_F1FB1_FFDB4_Msk (0x1U << CAN_F1FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB1_FFDB4 CAN_F1FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB1_FFDB5_Pos (5U) +#define CAN_F1FB1_FFDB5_Msk (0x1U << CAN_F1FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB1_FFDB5 CAN_F1FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB1_FFDB6_Pos (6U) +#define CAN_F1FB1_FFDB6_Msk (0x1U << CAN_F1FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB1_FFDB6 CAN_F1FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB1_FFDB7_Pos (7U) +#define CAN_F1FB1_FFDB7_Msk (0x1U << CAN_F1FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB1_FFDB7 CAN_F1FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB1_FFDB8_Pos (8U) +#define CAN_F1FB1_FFDB8_Msk (0x1U << CAN_F1FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB1_FFDB8 CAN_F1FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB1_FFDB9_Pos (9U) +#define CAN_F1FB1_FFDB9_Msk (0x1U << CAN_F1FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB1_FFDB9 CAN_F1FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB1_FFDB10_Pos (10U) +#define CAN_F1FB1_FFDB10_Msk (0x1U << CAN_F1FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB1_FFDB10 CAN_F1FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB1_FFDB11_Pos (11U) +#define CAN_F1FB1_FFDB11_Msk (0x1U << CAN_F1FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB1_FFDB11 CAN_F1FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB1_FFDB12_Pos (12U) +#define CAN_F1FB1_FFDB12_Msk (0x1U << CAN_F1FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB1_FFDB12 CAN_F1FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB1_FFDB13_Pos (13U) +#define CAN_F1FB1_FFDB13_Msk (0x1U << CAN_F1FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB1_FFDB13 CAN_F1FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB1_FFDB14_Pos (14U) +#define CAN_F1FB1_FFDB14_Msk (0x1U << CAN_F1FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB1_FFDB14 CAN_F1FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB1_FFDB15_Pos (15U) +#define CAN_F1FB1_FFDB15_Msk (0x1U << CAN_F1FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB1_FFDB15 CAN_F1FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB1_FFDB16_Pos (16U) +#define CAN_F1FB1_FFDB16_Msk (0x1U << CAN_F1FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB1_FFDB16 CAN_F1FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB1_FFDB17_Pos (17U) +#define CAN_F1FB1_FFDB17_Msk (0x1U << CAN_F1FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB1_FFDB17 CAN_F1FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB1_FFDB18_Pos (18U) +#define CAN_F1FB1_FFDB18_Msk (0x1U << CAN_F1FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB1_FFDB18 CAN_F1FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB1_FFDB19_Pos (19U) +#define CAN_F1FB1_FFDB19_Msk (0x1U << CAN_F1FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB1_FFDB19 CAN_F1FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB1_FFDB20_Pos (20U) +#define CAN_F1FB1_FFDB20_Msk (0x1U << CAN_F1FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB1_FFDB20 CAN_F1FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB1_FFDB21_Pos (21U) +#define CAN_F1FB1_FFDB21_Msk (0x1U << CAN_F1FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB1_FFDB21 CAN_F1FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB1_FFDB22_Pos (22U) +#define CAN_F1FB1_FFDB22_Msk (0x1U << CAN_F1FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB1_FFDB22 CAN_F1FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB1_FFDB23_Pos (23U) +#define CAN_F1FB1_FFDB23_Msk (0x1U << CAN_F1FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB1_FFDB23 CAN_F1FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB1_FFDB24_Pos (24U) +#define CAN_F1FB1_FFDB24_Msk (0x1U << CAN_F1FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB1_FFDB24 CAN_F1FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB1_FFDB25_Pos (25U) +#define CAN_F1FB1_FFDB25_Msk (0x1U << CAN_F1FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB1_FFDB25 CAN_F1FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB1_FFDB26_Pos (26U) +#define CAN_F1FB1_FFDB26_Msk (0x1U << CAN_F1FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB1_FFDB26 CAN_F1FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB1_FFDB27_Pos (27U) +#define CAN_F1FB1_FFDB27_Msk (0x1U << CAN_F1FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB1_FFDB27 CAN_F1FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB1_FFDB28_Pos (28U) +#define CAN_F1FB1_FFDB28_Msk (0x1U << CAN_F1FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB1_FFDB28 CAN_F1FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB1_FFDB29_Pos (29U) +#define CAN_F1FB1_FFDB29_Msk (0x1U << CAN_F1FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB1_FFDB29 CAN_F1FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB1_FFDB30_Pos (30U) +#define CAN_F1FB1_FFDB30_Msk (0x1U << CAN_F1FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB1_FFDB30 CAN_F1FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB1_FFDB31_Pos (31U) +#define CAN_F1FB1_FFDB31_Msk (0x1U << CAN_F1FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB1_FFDB31 CAN_F1FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB1 register *******************/ +#define CAN_F2FB1_FFDB0_Pos (0U) +#define CAN_F2FB1_FFDB0_Msk (0x1U << CAN_F2FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB1_FFDB0 CAN_F2FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB1_FFDB1_Pos (1U) +#define CAN_F2FB1_FFDB1_Msk (0x1U << CAN_F2FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB1_FFDB1 CAN_F2FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB1_FFDB2_Pos (2U) +#define CAN_F2FB1_FFDB2_Msk (0x1U << CAN_F2FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB1_FFDB2 CAN_F2FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB1_FFDB3_Pos (3U) +#define CAN_F2FB1_FFDB3_Msk (0x1U << CAN_F2FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB1_FFDB3 CAN_F2FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB1_FFDB4_Pos (4U) +#define CAN_F2FB1_FFDB4_Msk (0x1U << CAN_F2FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB1_FFDB4 CAN_F2FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB1_FFDB5_Pos (5U) +#define CAN_F2FB1_FFDB5_Msk (0x1U << CAN_F2FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB1_FFDB5 CAN_F2FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB1_FFDB6_Pos (6U) +#define CAN_F2FB1_FFDB6_Msk (0x1U << CAN_F2FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB1_FFDB6 CAN_F2FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB1_FFDB7_Pos (7U) +#define CAN_F2FB1_FFDB7_Msk (0x1U << CAN_F2FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB1_FFDB7 CAN_F2FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB1_FFDB8_Pos (8U) +#define CAN_F2FB1_FFDB8_Msk (0x1U << CAN_F2FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB1_FFDB8 CAN_F2FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB1_FFDB9_Pos (9U) +#define CAN_F2FB1_FFDB9_Msk (0x1U << CAN_F2FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB1_FFDB9 CAN_F2FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB1_FFDB10_Pos (10U) +#define CAN_F2FB1_FFDB10_Msk (0x1U << CAN_F2FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB1_FFDB10 CAN_F2FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB1_FFDB11_Pos (11U) +#define CAN_F2FB1_FFDB11_Msk (0x1U << CAN_F2FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB1_FFDB11 CAN_F2FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB1_FFDB12_Pos (12U) +#define CAN_F2FB1_FFDB12_Msk (0x1U << CAN_F2FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB1_FFDB12 CAN_F2FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB1_FFDB13_Pos (13U) +#define CAN_F2FB1_FFDB13_Msk (0x1U << CAN_F2FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB1_FFDB13 CAN_F2FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB1_FFDB14_Pos (14U) +#define CAN_F2FB1_FFDB14_Msk (0x1U << CAN_F2FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB1_FFDB14 CAN_F2FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB1_FFDB15_Pos (15U) +#define CAN_F2FB1_FFDB15_Msk (0x1U << CAN_F2FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB1_FFDB15 CAN_F2FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB1_FFDB16_Pos (16U) +#define CAN_F2FB1_FFDB16_Msk (0x1U << CAN_F2FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB1_FFDB16 CAN_F2FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB1_FFDB17_Pos (17U) +#define CAN_F2FB1_FFDB17_Msk (0x1U << CAN_F2FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB1_FFDB17 CAN_F2FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB1_FFDB18_Pos (18U) +#define CAN_F2FB1_FFDB18_Msk (0x1U << CAN_F2FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB1_FFDB18 CAN_F2FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB1_FFDB19_Pos (19U) +#define CAN_F2FB1_FFDB19_Msk (0x1U << CAN_F2FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB1_FFDB19 CAN_F2FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB1_FFDB20_Pos (20U) +#define CAN_F2FB1_FFDB20_Msk (0x1U << CAN_F2FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB1_FFDB20 CAN_F2FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB1_FFDB21_Pos (21U) +#define CAN_F2FB1_FFDB21_Msk (0x1U << CAN_F2FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB1_FFDB21 CAN_F2FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB1_FFDB22_Pos (22U) +#define CAN_F2FB1_FFDB22_Msk (0x1U << CAN_F2FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB1_FFDB22 CAN_F2FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB1_FFDB23_Pos (23U) +#define CAN_F2FB1_FFDB23_Msk (0x1U << CAN_F2FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB1_FFDB23 CAN_F2FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB1_FFDB24_Pos (24U) +#define CAN_F2FB1_FFDB24_Msk (0x1U << CAN_F2FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB1_FFDB24 CAN_F2FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB1_FFDB25_Pos (25U) +#define CAN_F2FB1_FFDB25_Msk (0x1U << CAN_F2FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB1_FFDB25 CAN_F2FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB1_FFDB26_Pos (26U) +#define CAN_F2FB1_FFDB26_Msk (0x1U << CAN_F2FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB1_FFDB26 CAN_F2FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB1_FFDB27_Pos (27U) +#define CAN_F2FB1_FFDB27_Msk (0x1U << CAN_F2FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB1_FFDB27 CAN_F2FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB1_FFDB28_Pos (28U) +#define CAN_F2FB1_FFDB28_Msk (0x1U << CAN_F2FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB1_FFDB28 CAN_F2FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB1_FFDB29_Pos (29U) +#define CAN_F2FB1_FFDB29_Msk (0x1U << CAN_F2FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB1_FFDB29 CAN_F2FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB1_FFDB30_Pos (30U) +#define CAN_F2FB1_FFDB30_Msk (0x1U << CAN_F2FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB1_FFDB30 CAN_F2FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB1_FFDB31_Pos (31U) +#define CAN_F2FB1_FFDB31_Msk (0x1U << CAN_F2FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB1_FFDB31 CAN_F2FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB1 register *******************/ +#define CAN_F3FB1_FFDB0_Pos (0U) +#define CAN_F3FB1_FFDB0_Msk (0x1U << CAN_F3FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB1_FFDB0 CAN_F3FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB1_FFDB1_Pos (1U) +#define CAN_F3FB1_FFDB1_Msk (0x1U << CAN_F3FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB1_FFDB1 CAN_F3FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB1_FFDB2_Pos (2U) +#define CAN_F3FB1_FFDB2_Msk (0x1U << CAN_F3FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB1_FFDB2 CAN_F3FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB1_FFDB3_Pos (3U) +#define CAN_F3FB1_FFDB3_Msk (0x1U << CAN_F3FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB1_FFDB3 CAN_F3FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB1_FFDB4_Pos (4U) +#define CAN_F3FB1_FFDB4_Msk (0x1U << CAN_F3FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB1_FFDB4 CAN_F3FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB1_FFDB5_Pos (5U) +#define CAN_F3FB1_FFDB5_Msk (0x1U << CAN_F3FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB1_FFDB5 CAN_F3FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB1_FFDB6_Pos (6U) +#define CAN_F3FB1_FFDB6_Msk (0x1U << CAN_F3FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB1_FFDB6 CAN_F3FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB1_FFDB7_Pos (7U) +#define CAN_F3FB1_FFDB7_Msk (0x1U << CAN_F3FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB1_FFDB7 CAN_F3FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB1_FFDB8_Pos (8U) +#define CAN_F3FB1_FFDB8_Msk (0x1U << CAN_F3FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB1_FFDB8 CAN_F3FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB1_FFDB9_Pos (9U) +#define CAN_F3FB1_FFDB9_Msk (0x1U << CAN_F3FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB1_FFDB9 CAN_F3FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB1_FFDB10_Pos (10U) +#define CAN_F3FB1_FFDB10_Msk (0x1U << CAN_F3FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB1_FFDB10 CAN_F3FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB1_FFDB11_Pos (11U) +#define CAN_F3FB1_FFDB11_Msk (0x1U << CAN_F3FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB1_FFDB11 CAN_F3FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB1_FFDB12_Pos (12U) +#define CAN_F3FB1_FFDB12_Msk (0x1U << CAN_F3FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB1_FFDB12 CAN_F3FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB1_FFDB13_Pos (13U) +#define CAN_F3FB1_FFDB13_Msk (0x1U << CAN_F3FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB1_FFDB13 CAN_F3FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB1_FFDB14_Pos (14U) +#define CAN_F3FB1_FFDB14_Msk (0x1U << CAN_F3FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB1_FFDB14 CAN_F3FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB1_FFDB15_Pos (15U) +#define CAN_F3FB1_FFDB15_Msk (0x1U << CAN_F3FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB1_FFDB15 CAN_F3FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB1_FFDB16_Pos (16U) +#define CAN_F3FB1_FFDB16_Msk (0x1U << CAN_F3FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB1_FFDB16 CAN_F3FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB1_FFDB17_Pos (17U) +#define CAN_F3FB1_FFDB17_Msk (0x1U << CAN_F3FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB1_FFDB17 CAN_F3FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB1_FFDB18_Pos (18U) +#define CAN_F3FB1_FFDB18_Msk (0x1U << CAN_F3FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB1_FFDB18 CAN_F3FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB1_FFDB19_Pos (19U) +#define CAN_F3FB1_FFDB19_Msk (0x1U << CAN_F3FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB1_FFDB19 CAN_F3FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB1_FFDB20_Pos (20U) +#define CAN_F3FB1_FFDB20_Msk (0x1U << CAN_F3FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB1_FFDB20 CAN_F3FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB1_FFDB21_Pos (21U) +#define CAN_F3FB1_FFDB21_Msk (0x1U << CAN_F3FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB1_FFDB21 CAN_F3FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB1_FFDB22_Pos (22U) +#define CAN_F3FB1_FFDB22_Msk (0x1U << CAN_F3FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB1_FFDB22 CAN_F3FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB1_FFDB23_Pos (23U) +#define CAN_F3FB1_FFDB23_Msk (0x1U << CAN_F3FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB1_FFDB23 CAN_F3FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB1_FFDB24_Pos (24U) +#define CAN_F3FB1_FFDB24_Msk (0x1U << CAN_F3FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB1_FFDB24 CAN_F3FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB1_FFDB25_Pos (25U) +#define CAN_F3FB1_FFDB25_Msk (0x1U << CAN_F3FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB1_FFDB25 CAN_F3FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB1_FFDB26_Pos (26U) +#define CAN_F3FB1_FFDB26_Msk (0x1U << CAN_F3FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB1_FFDB26 CAN_F3FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB1_FFDB27_Pos (27U) +#define CAN_F3FB1_FFDB27_Msk (0x1U << CAN_F3FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB1_FFDB27 CAN_F3FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB1_FFDB28_Pos (28U) +#define CAN_F3FB1_FFDB28_Msk (0x1U << CAN_F3FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB1_FFDB28 CAN_F3FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB1_FFDB29_Pos (29U) +#define CAN_F3FB1_FFDB29_Msk (0x1U << CAN_F3FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB1_FFDB29 CAN_F3FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB1_FFDB30_Pos (30U) +#define CAN_F3FB1_FFDB30_Msk (0x1U << CAN_F3FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB1_FFDB30 CAN_F3FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB1_FFDB31_Pos (31U) +#define CAN_F3FB1_FFDB31_Msk (0x1U << CAN_F3FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB1_FFDB31 CAN_F3FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB1 register *******************/ +#define CAN_F4FB1_FFDB0_Pos (0U) +#define CAN_F4FB1_FFDB0_Msk (0x1U << CAN_F4FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB1_FFDB0 CAN_F4FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB1_FFDB1_Pos (1U) +#define CAN_F4FB1_FFDB1_Msk (0x1U << CAN_F4FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB1_FFDB1 CAN_F4FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB1_FFDB2_Pos (2U) +#define CAN_F4FB1_FFDB2_Msk (0x1U << CAN_F4FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB1_FFDB2 CAN_F4FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB1_FFDB3_Pos (3U) +#define CAN_F4FB1_FFDB3_Msk (0x1U << CAN_F4FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB1_FFDB3 CAN_F4FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB1_FFDB4_Pos (4U) +#define CAN_F4FB1_FFDB4_Msk (0x1U << CAN_F4FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB1_FFDB4 CAN_F4FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB1_FFDB5_Pos (5U) +#define CAN_F4FB1_FFDB5_Msk (0x1U << CAN_F4FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB1_FFDB5 CAN_F4FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB1_FFDB6_Pos (6U) +#define CAN_F4FB1_FFDB6_Msk (0x1U << CAN_F4FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB1_FFDB6 CAN_F4FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB1_FFDB7_Pos (7U) +#define CAN_F4FB1_FFDB7_Msk (0x1U << CAN_F4FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB1_FFDB7 CAN_F4FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB1_FFDB8_Pos (8U) +#define CAN_F4FB1_FFDB8_Msk (0x1U << CAN_F4FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB1_FFDB8 CAN_F4FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB1_FFDB9_Pos (9U) +#define CAN_F4FB1_FFDB9_Msk (0x1U << CAN_F4FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB1_FFDB9 CAN_F4FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB1_FFDB10_Pos (10U) +#define CAN_F4FB1_FFDB10_Msk (0x1U << CAN_F4FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB1_FFDB10 CAN_F4FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB1_FFDB11_Pos (11U) +#define CAN_F4FB1_FFDB11_Msk (0x1U << CAN_F4FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB1_FFDB11 CAN_F4FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB1_FFDB12_Pos (12U) +#define CAN_F4FB1_FFDB12_Msk (0x1U << CAN_F4FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB1_FFDB12 CAN_F4FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB1_FFDB13_Pos (13U) +#define CAN_F4FB1_FFDB13_Msk (0x1U << CAN_F4FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB1_FFDB13 CAN_F4FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB1_FFDB14_Pos (14U) +#define CAN_F4FB1_FFDB14_Msk (0x1U << CAN_F4FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB1_FFDB14 CAN_F4FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB1_FFDB15_Pos (15U) +#define CAN_F4FB1_FFDB15_Msk (0x1U << CAN_F4FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB1_FFDB15 CAN_F4FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB1_FFDB16_Pos (16U) +#define CAN_F4FB1_FFDB16_Msk (0x1U << CAN_F4FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB1_FFDB16 CAN_F4FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB1_FFDB17_Pos (17U) +#define CAN_F4FB1_FFDB17_Msk (0x1U << CAN_F4FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB1_FFDB17 CAN_F4FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB1_FFDB18_Pos (18U) +#define CAN_F4FB1_FFDB18_Msk (0x1U << CAN_F4FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB1_FFDB18 CAN_F4FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB1_FFDB19_Pos (19U) +#define CAN_F4FB1_FFDB19_Msk (0x1U << CAN_F4FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB1_FFDB19 CAN_F4FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB1_FFDB20_Pos (20U) +#define CAN_F4FB1_FFDB20_Msk (0x1U << CAN_F4FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB1_FFDB20 CAN_F4FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB1_FFDB21_Pos (21U) +#define CAN_F4FB1_FFDB21_Msk (0x1U << CAN_F4FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB1_FFDB21 CAN_F4FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB1_FFDB22_Pos (22U) +#define CAN_F4FB1_FFDB22_Msk (0x1U << CAN_F4FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB1_FFDB22 CAN_F4FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB1_FFDB23_Pos (23U) +#define CAN_F4FB1_FFDB23_Msk (0x1U << CAN_F4FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB1_FFDB23 CAN_F4FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB1_FFDB24_Pos (24U) +#define CAN_F4FB1_FFDB24_Msk (0x1U << CAN_F4FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB1_FFDB24 CAN_F4FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB1_FFDB25_Pos (25U) +#define CAN_F4FB1_FFDB25_Msk (0x1U << CAN_F4FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB1_FFDB25 CAN_F4FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB1_FFDB26_Pos (26U) +#define CAN_F4FB1_FFDB26_Msk (0x1U << CAN_F4FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB1_FFDB26 CAN_F4FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB1_FFDB27_Pos (27U) +#define CAN_F4FB1_FFDB27_Msk (0x1U << CAN_F4FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB1_FFDB27 CAN_F4FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB1_FFDB28_Pos (28U) +#define CAN_F4FB1_FFDB28_Msk (0x1U << CAN_F4FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB1_FFDB28 CAN_F4FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB1_FFDB29_Pos (29U) +#define CAN_F4FB1_FFDB29_Msk (0x1U << CAN_F4FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB1_FFDB29 CAN_F4FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB1_FFDB30_Pos (30U) +#define CAN_F4FB1_FFDB30_Msk (0x1U << CAN_F4FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB1_FFDB30 CAN_F4FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB1_FFDB31_Pos (31U) +#define CAN_F4FB1_FFDB31_Msk (0x1U << CAN_F4FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB1_FFDB31 CAN_F4FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB1 register *******************/ +#define CAN_F5FB1_FFDB0_Pos (0U) +#define CAN_F5FB1_FFDB0_Msk (0x1U << CAN_F5FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB1_FFDB0 CAN_F5FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB1_FFDB1_Pos (1U) +#define CAN_F5FB1_FFDB1_Msk (0x1U << CAN_F5FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB1_FFDB1 CAN_F5FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB1_FFDB2_Pos (2U) +#define CAN_F5FB1_FFDB2_Msk (0x1U << CAN_F5FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB1_FFDB2 CAN_F5FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB1_FFDB3_Pos (3U) +#define CAN_F5FB1_FFDB3_Msk (0x1U << CAN_F5FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB1_FFDB3 CAN_F5FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB1_FFDB4_Pos (4U) +#define CAN_F5FB1_FFDB4_Msk (0x1U << CAN_F5FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB1_FFDB4 CAN_F5FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB1_FFDB5_Pos (5U) +#define CAN_F5FB1_FFDB5_Msk (0x1U << CAN_F5FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB1_FFDB5 CAN_F5FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB1_FFDB6_Pos (6U) +#define CAN_F5FB1_FFDB6_Msk (0x1U << CAN_F5FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB1_FFDB6 CAN_F5FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB1_FFDB7_Pos (7U) +#define CAN_F5FB1_FFDB7_Msk (0x1U << CAN_F5FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB1_FFDB7 CAN_F5FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB1_FFDB8_Pos (8U) +#define CAN_F5FB1_FFDB8_Msk (0x1U << CAN_F5FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB1_FFDB8 CAN_F5FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB1_FFDB9_Pos (9U) +#define CAN_F5FB1_FFDB9_Msk (0x1U << CAN_F5FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB1_FFDB9 CAN_F5FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB1_FFDB10_Pos (10U) +#define CAN_F5FB1_FFDB10_Msk (0x1U << CAN_F5FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB1_FFDB10 CAN_F5FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB1_FFDB11_Pos (11U) +#define CAN_F5FB1_FFDB11_Msk (0x1U << CAN_F5FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB1_FFDB11 CAN_F5FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB1_FFDB12_Pos (12U) +#define CAN_F5FB1_FFDB12_Msk (0x1U << CAN_F5FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB1_FFDB12 CAN_F5FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB1_FFDB13_Pos (13U) +#define CAN_F5FB1_FFDB13_Msk (0x1U << CAN_F5FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB1_FFDB13 CAN_F5FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB1_FFDB14_Pos (14U) +#define CAN_F5FB1_FFDB14_Msk (0x1U << CAN_F5FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB1_FFDB14 CAN_F5FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB1_FFDB15_Pos (15U) +#define CAN_F5FB1_FFDB15_Msk (0x1U << CAN_F5FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB1_FFDB15 CAN_F5FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB1_FFDB16_Pos (16U) +#define CAN_F5FB1_FFDB16_Msk (0x1U << CAN_F5FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB1_FFDB16 CAN_F5FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB1_FFDB17_Pos (17U) +#define CAN_F5FB1_FFDB17_Msk (0x1U << CAN_F5FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB1_FFDB17 CAN_F5FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB1_FFDB18_Pos (18U) +#define CAN_F5FB1_FFDB18_Msk (0x1U << CAN_F5FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB1_FFDB18 CAN_F5FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB1_FFDB19_Pos (19U) +#define CAN_F5FB1_FFDB19_Msk (0x1U << CAN_F5FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB1_FFDB19 CAN_F5FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB1_FFDB20_Pos (20U) +#define CAN_F5FB1_FFDB20_Msk (0x1U << CAN_F5FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB1_FFDB20 CAN_F5FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB1_FFDB21_Pos (21U) +#define CAN_F5FB1_FFDB21_Msk (0x1U << CAN_F5FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB1_FFDB21 CAN_F5FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB1_FFDB22_Pos (22U) +#define CAN_F5FB1_FFDB22_Msk (0x1U << CAN_F5FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB1_FFDB22 CAN_F5FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB1_FFDB23_Pos (23U) +#define CAN_F5FB1_FFDB23_Msk (0x1U << CAN_F5FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB1_FFDB23 CAN_F5FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB1_FFDB24_Pos (24U) +#define CAN_F5FB1_FFDB24_Msk (0x1U << CAN_F5FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB1_FFDB24 CAN_F5FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB1_FFDB25_Pos (25U) +#define CAN_F5FB1_FFDB25_Msk (0x1U << CAN_F5FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB1_FFDB25 CAN_F5FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB1_FFDB26_Pos (26U) +#define CAN_F5FB1_FFDB26_Msk (0x1U << CAN_F5FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB1_FFDB26 CAN_F5FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB1_FFDB27_Pos (27U) +#define CAN_F5FB1_FFDB27_Msk (0x1U << CAN_F5FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB1_FFDB27 CAN_F5FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB1_FFDB28_Pos (28U) +#define CAN_F5FB1_FFDB28_Msk (0x1U << CAN_F5FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB1_FFDB28 CAN_F5FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB1_FFDB29_Pos (29U) +#define CAN_F5FB1_FFDB29_Msk (0x1U << CAN_F5FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB1_FFDB29 CAN_F5FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB1_FFDB30_Pos (30U) +#define CAN_F5FB1_FFDB30_Msk (0x1U << CAN_F5FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB1_FFDB30 CAN_F5FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB1_FFDB31_Pos (31U) +#define CAN_F5FB1_FFDB31_Msk (0x1U << CAN_F5FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB1_FFDB31 CAN_F5FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB1 register *******************/ +#define CAN_F6FB1_FFDB0_Pos (0U) +#define CAN_F6FB1_FFDB0_Msk (0x1U << CAN_F6FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB1_FFDB0 CAN_F6FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB1_FFDB1_Pos (1U) +#define CAN_F6FB1_FFDB1_Msk (0x1U << CAN_F6FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB1_FFDB1 CAN_F6FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB1_FFDB2_Pos (2U) +#define CAN_F6FB1_FFDB2_Msk (0x1U << CAN_F6FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB1_FFDB2 CAN_F6FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB1_FFDB3_Pos (3U) +#define CAN_F6FB1_FFDB3_Msk (0x1U << CAN_F6FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB1_FFDB3 CAN_F6FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB1_FFDB4_Pos (4U) +#define CAN_F6FB1_FFDB4_Msk (0x1U << CAN_F6FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB1_FFDB4 CAN_F6FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB1_FFDB5_Pos (5U) +#define CAN_F6FB1_FFDB5_Msk (0x1U << CAN_F6FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB1_FFDB5 CAN_F6FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB1_FFDB6_Pos (6U) +#define CAN_F6FB1_FFDB6_Msk (0x1U << CAN_F6FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB1_FFDB6 CAN_F6FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB1_FFDB7_Pos (7U) +#define CAN_F6FB1_FFDB7_Msk (0x1U << CAN_F6FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB1_FFDB7 CAN_F6FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB1_FFDB8_Pos (8U) +#define CAN_F6FB1_FFDB8_Msk (0x1U << CAN_F6FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB1_FFDB8 CAN_F6FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB1_FFDB9_Pos (9U) +#define CAN_F6FB1_FFDB9_Msk (0x1U << CAN_F6FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB1_FFDB9 CAN_F6FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB1_FFDB10_Pos (10U) +#define CAN_F6FB1_FFDB10_Msk (0x1U << CAN_F6FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB1_FFDB10 CAN_F6FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB1_FFDB11_Pos (11U) +#define CAN_F6FB1_FFDB11_Msk (0x1U << CAN_F6FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB1_FFDB11 CAN_F6FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB1_FFDB12_Pos (12U) +#define CAN_F6FB1_FFDB12_Msk (0x1U << CAN_F6FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB1_FFDB12 CAN_F6FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB1_FFDB13_Pos (13U) +#define CAN_F6FB1_FFDB13_Msk (0x1U << CAN_F6FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB1_FFDB13 CAN_F6FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB1_FFDB14_Pos (14U) +#define CAN_F6FB1_FFDB14_Msk (0x1U << CAN_F6FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB1_FFDB14 CAN_F6FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB1_FFDB15_Pos (15U) +#define CAN_F6FB1_FFDB15_Msk (0x1U << CAN_F6FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB1_FFDB15 CAN_F6FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB1_FFDB16_Pos (16U) +#define CAN_F6FB1_FFDB16_Msk (0x1U << CAN_F6FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB1_FFDB16 CAN_F6FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB1_FFDB17_Pos (17U) +#define CAN_F6FB1_FFDB17_Msk (0x1U << CAN_F6FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB1_FFDB17 CAN_F6FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB1_FFDB18_Pos (18U) +#define CAN_F6FB1_FFDB18_Msk (0x1U << CAN_F6FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB1_FFDB18 CAN_F6FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB1_FFDB19_Pos (19U) +#define CAN_F6FB1_FFDB19_Msk (0x1U << CAN_F6FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB1_FFDB19 CAN_F6FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB1_FFDB20_Pos (20U) +#define CAN_F6FB1_FFDB20_Msk (0x1U << CAN_F6FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB1_FFDB20 CAN_F6FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB1_FFDB21_Pos (21U) +#define CAN_F6FB1_FFDB21_Msk (0x1U << CAN_F6FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB1_FFDB21 CAN_F6FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB1_FFDB22_Pos (22U) +#define CAN_F6FB1_FFDB22_Msk (0x1U << CAN_F6FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB1_FFDB22 CAN_F6FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB1_FFDB23_Pos (23U) +#define CAN_F6FB1_FFDB23_Msk (0x1U << CAN_F6FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB1_FFDB23 CAN_F6FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB1_FFDB24_Pos (24U) +#define CAN_F6FB1_FFDB24_Msk (0x1U << CAN_F6FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB1_FFDB24 CAN_F6FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB1_FFDB25_Pos (25U) +#define CAN_F6FB1_FFDB25_Msk (0x1U << CAN_F6FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB1_FFDB25 CAN_F6FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB1_FFDB26_Pos (26U) +#define CAN_F6FB1_FFDB26_Msk (0x1U << CAN_F6FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB1_FFDB26 CAN_F6FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB1_FFDB27_Pos (27U) +#define CAN_F6FB1_FFDB27_Msk (0x1U << CAN_F6FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB1_FFDB27 CAN_F6FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB1_FFDB28_Pos (28U) +#define CAN_F6FB1_FFDB28_Msk (0x1U << CAN_F6FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB1_FFDB28 CAN_F6FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB1_FFDB29_Pos (29U) +#define CAN_F6FB1_FFDB29_Msk (0x1U << CAN_F6FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB1_FFDB29 CAN_F6FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB1_FFDB30_Pos (30U) +#define CAN_F6FB1_FFDB30_Msk (0x1U << CAN_F6FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB1_FFDB30 CAN_F6FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB1_FFDB31_Pos (31U) +#define CAN_F6FB1_FFDB31_Msk (0x1U << CAN_F6FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB1_FFDB31 CAN_F6FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB1 register *******************/ +#define CAN_F7FB1_FFDB0_Pos (0U) +#define CAN_F7FB1_FFDB0_Msk (0x1U << CAN_F7FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB1_FFDB0 CAN_F7FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB1_FFDB1_Pos (1U) +#define CAN_F7FB1_FFDB1_Msk (0x1U << CAN_F7FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB1_FFDB1 CAN_F7FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB1_FFDB2_Pos (2U) +#define CAN_F7FB1_FFDB2_Msk (0x1U << CAN_F7FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB1_FFDB2 CAN_F7FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB1_FFDB3_Pos (3U) +#define CAN_F7FB1_FFDB3_Msk (0x1U << CAN_F7FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB1_FFDB3 CAN_F7FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB1_FFDB4_Pos (4U) +#define CAN_F7FB1_FFDB4_Msk (0x1U << CAN_F7FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB1_FFDB4 CAN_F7FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB1_FFDB5_Pos (5U) +#define CAN_F7FB1_FFDB5_Msk (0x1U << CAN_F7FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB1_FFDB5 CAN_F7FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB1_FFDB6_Pos (6U) +#define CAN_F7FB1_FFDB6_Msk (0x1U << CAN_F7FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB1_FFDB6 CAN_F7FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB1_FFDB7_Pos (7U) +#define CAN_F7FB1_FFDB7_Msk (0x1U << CAN_F7FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB1_FFDB7 CAN_F7FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB1_FFDB8_Pos (8U) +#define CAN_F7FB1_FFDB8_Msk (0x1U << CAN_F7FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB1_FFDB8 CAN_F7FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB1_FFDB9_Pos (9U) +#define CAN_F7FB1_FFDB9_Msk (0x1U << CAN_F7FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB1_FFDB9 CAN_F7FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB1_FFDB10_Pos (10U) +#define CAN_F7FB1_FFDB10_Msk (0x1U << CAN_F7FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB1_FFDB10 CAN_F7FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB1_FFDB11_Pos (11U) +#define CAN_F7FB1_FFDB11_Msk (0x1U << CAN_F7FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB1_FFDB11 CAN_F7FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB1_FFDB12_Pos (12U) +#define CAN_F7FB1_FFDB12_Msk (0x1U << CAN_F7FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB1_FFDB12 CAN_F7FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB1_FFDB13_Pos (13U) +#define CAN_F7FB1_FFDB13_Msk (0x1U << CAN_F7FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB1_FFDB13 CAN_F7FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB1_FFDB14_Pos (14U) +#define CAN_F7FB1_FFDB14_Msk (0x1U << CAN_F7FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB1_FFDB14 CAN_F7FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB1_FFDB15_Pos (15U) +#define CAN_F7FB1_FFDB15_Msk (0x1U << CAN_F7FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB1_FFDB15 CAN_F7FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB1_FFDB16_Pos (16U) +#define CAN_F7FB1_FFDB16_Msk (0x1U << CAN_F7FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB1_FFDB16 CAN_F7FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB1_FFDB17_Pos (17U) +#define CAN_F7FB1_FFDB17_Msk (0x1U << CAN_F7FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB1_FFDB17 CAN_F7FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB1_FFDB18_Pos (18U) +#define CAN_F7FB1_FFDB18_Msk (0x1U << CAN_F7FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB1_FFDB18 CAN_F7FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB1_FFDB19_Pos (19U) +#define CAN_F7FB1_FFDB19_Msk (0x1U << CAN_F7FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB1_FFDB19 CAN_F7FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB1_FFDB20_Pos (20U) +#define CAN_F7FB1_FFDB20_Msk (0x1U << CAN_F7FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB1_FFDB20 CAN_F7FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB1_FFDB21_Pos (21U) +#define CAN_F7FB1_FFDB21_Msk (0x1U << CAN_F7FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB1_FFDB21 CAN_F7FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB1_FFDB22_Pos (22U) +#define CAN_F7FB1_FFDB22_Msk (0x1U << CAN_F7FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB1_FFDB22 CAN_F7FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB1_FFDB23_Pos (23U) +#define CAN_F7FB1_FFDB23_Msk (0x1U << CAN_F7FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB1_FFDB23 CAN_F7FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB1_FFDB24_Pos (24U) +#define CAN_F7FB1_FFDB24_Msk (0x1U << CAN_F7FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB1_FFDB24 CAN_F7FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB1_FFDB25_Pos (25U) +#define CAN_F7FB1_FFDB25_Msk (0x1U << CAN_F7FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB1_FFDB25 CAN_F7FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB1_FFDB26_Pos (26U) +#define CAN_F7FB1_FFDB26_Msk (0x1U << CAN_F7FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB1_FFDB26 CAN_F7FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB1_FFDB27_Pos (27U) +#define CAN_F7FB1_FFDB27_Msk (0x1U << CAN_F7FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB1_FFDB27 CAN_F7FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB1_FFDB28_Pos (28U) +#define CAN_F7FB1_FFDB28_Msk (0x1U << CAN_F7FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB1_FFDB28 CAN_F7FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB1_FFDB29_Pos (29U) +#define CAN_F7FB1_FFDB29_Msk (0x1U << CAN_F7FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB1_FFDB29 CAN_F7FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB1_FFDB30_Pos (30U) +#define CAN_F7FB1_FFDB30_Msk (0x1U << CAN_F7FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB1_FFDB30 CAN_F7FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB1_FFDB31_Pos (31U) +#define CAN_F7FB1_FFDB31_Msk (0x1U << CAN_F7FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB1_FFDB31 CAN_F7FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB1 register *******************/ +#define CAN_F8FB1_FFDB0_Pos (0U) +#define CAN_F8FB1_FFDB0_Msk (0x1U << CAN_F8FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB1_FFDB0 CAN_F8FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB1_FFDB1_Pos (1U) +#define CAN_F8FB1_FFDB1_Msk (0x1U << CAN_F8FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB1_FFDB1 CAN_F8FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB1_FFDB2_Pos (2U) +#define CAN_F8FB1_FFDB2_Msk (0x1U << CAN_F8FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB1_FFDB2 CAN_F8FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB1_FFDB3_Pos (3U) +#define CAN_F8FB1_FFDB3_Msk (0x1U << CAN_F8FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB1_FFDB3 CAN_F8FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB1_FFDB4_Pos (4U) +#define CAN_F8FB1_FFDB4_Msk (0x1U << CAN_F8FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB1_FFDB4 CAN_F8FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB1_FFDB5_Pos (5U) +#define CAN_F8FB1_FFDB5_Msk (0x1U << CAN_F8FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB1_FFDB5 CAN_F8FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB1_FFDB6_Pos (6U) +#define CAN_F8FB1_FFDB6_Msk (0x1U << CAN_F8FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB1_FFDB6 CAN_F8FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB1_FFDB7_Pos (7U) +#define CAN_F8FB1_FFDB7_Msk (0x1U << CAN_F8FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB1_FFDB7 CAN_F8FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB1_FFDB8_Pos (8U) +#define CAN_F8FB1_FFDB8_Msk (0x1U << CAN_F8FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB1_FFDB8 CAN_F8FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB1_FFDB9_Pos (9U) +#define CAN_F8FB1_FFDB9_Msk (0x1U << CAN_F8FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB1_FFDB9 CAN_F8FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB1_FFDB10_Pos (10U) +#define CAN_F8FB1_FFDB10_Msk (0x1U << CAN_F8FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB1_FFDB10 CAN_F8FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB1_FFDB11_Pos (11U) +#define CAN_F8FB1_FFDB11_Msk (0x1U << CAN_F8FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB1_FFDB11 CAN_F8FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB1_FFDB12_Pos (12U) +#define CAN_F8FB1_FFDB12_Msk (0x1U << CAN_F8FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB1_FFDB12 CAN_F8FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB1_FFDB13_Pos (13U) +#define CAN_F8FB1_FFDB13_Msk (0x1U << CAN_F8FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB1_FFDB13 CAN_F8FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB1_FFDB14_Pos (14U) +#define CAN_F8FB1_FFDB14_Msk (0x1U << CAN_F8FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB1_FFDB14 CAN_F8FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB1_FFDB15_Pos (15U) +#define CAN_F8FB1_FFDB15_Msk (0x1U << CAN_F8FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB1_FFDB15 CAN_F8FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB1_FFDB16_Pos (16U) +#define CAN_F8FB1_FFDB16_Msk (0x1U << CAN_F8FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB1_FFDB16 CAN_F8FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB1_FFDB17_Pos (17U) +#define CAN_F8FB1_FFDB17_Msk (0x1U << CAN_F8FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB1_FFDB17 CAN_F8FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB1_FFDB18_Pos (18U) +#define CAN_F8FB1_FFDB18_Msk (0x1U << CAN_F8FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB1_FFDB18 CAN_F8FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB1_FFDB19_Pos (19U) +#define CAN_F8FB1_FFDB19_Msk (0x1U << CAN_F8FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB1_FFDB19 CAN_F8FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB1_FFDB20_Pos (20U) +#define CAN_F8FB1_FFDB20_Msk (0x1U << CAN_F8FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB1_FFDB20 CAN_F8FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB1_FFDB21_Pos (21U) +#define CAN_F8FB1_FFDB21_Msk (0x1U << CAN_F8FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB1_FFDB21 CAN_F8FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB1_FFDB22_Pos (22U) +#define CAN_F8FB1_FFDB22_Msk (0x1U << CAN_F8FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB1_FFDB22 CAN_F8FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB1_FFDB23_Pos (23U) +#define CAN_F8FB1_FFDB23_Msk (0x1U << CAN_F8FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB1_FFDB23 CAN_F8FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB1_FFDB24_Pos (24U) +#define CAN_F8FB1_FFDB24_Msk (0x1U << CAN_F8FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB1_FFDB24 CAN_F8FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB1_FFDB25_Pos (25U) +#define CAN_F8FB1_FFDB25_Msk (0x1U << CAN_F8FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB1_FFDB25 CAN_F8FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB1_FFDB26_Pos (26U) +#define CAN_F8FB1_FFDB26_Msk (0x1U << CAN_F8FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB1_FFDB26 CAN_F8FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB1_FFDB27_Pos (27U) +#define CAN_F8FB1_FFDB27_Msk (0x1U << CAN_F8FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB1_FFDB27 CAN_F8FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB1_FFDB28_Pos (28U) +#define CAN_F8FB1_FFDB28_Msk (0x1U << CAN_F8FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB1_FFDB28 CAN_F8FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB1_FFDB29_Pos (29U) +#define CAN_F8FB1_FFDB29_Msk (0x1U << CAN_F8FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB1_FFDB29 CAN_F8FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB1_FFDB30_Pos (30U) +#define CAN_F8FB1_FFDB30_Msk (0x1U << CAN_F8FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB1_FFDB30 CAN_F8FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB1_FFDB31_Pos (31U) +#define CAN_F8FB1_FFDB31_Msk (0x1U << CAN_F8FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB1_FFDB31 CAN_F8FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB1 register *******************/ +#define CAN_F9FB1_FFDB0_Pos (0U) +#define CAN_F9FB1_FFDB0_Msk (0x1U << CAN_F9FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB1_FFDB0 CAN_F9FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB1_FFDB1_Pos (1U) +#define CAN_F9FB1_FFDB1_Msk (0x1U << CAN_F9FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB1_FFDB1 CAN_F9FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB1_FFDB2_Pos (2U) +#define CAN_F9FB1_FFDB2_Msk (0x1U << CAN_F9FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB1_FFDB2 CAN_F9FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB1_FFDB3_Pos (3U) +#define CAN_F9FB1_FFDB3_Msk (0x1U << CAN_F9FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB1_FFDB3 CAN_F9FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB1_FFDB4_Pos (4U) +#define CAN_F9FB1_FFDB4_Msk (0x1U << CAN_F9FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB1_FFDB4 CAN_F9FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB1_FFDB5_Pos (5U) +#define CAN_F9FB1_FFDB5_Msk (0x1U << CAN_F9FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB1_FFDB5 CAN_F9FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB1_FFDB6_Pos (6U) +#define CAN_F9FB1_FFDB6_Msk (0x1U << CAN_F9FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB1_FFDB6 CAN_F9FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB1_FFDB7_Pos (7U) +#define CAN_F9FB1_FFDB7_Msk (0x1U << CAN_F9FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB1_FFDB7 CAN_F9FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB1_FFDB8_Pos (8U) +#define CAN_F9FB1_FFDB8_Msk (0x1U << CAN_F9FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB1_FFDB8 CAN_F9FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB1_FFDB9_Pos (9U) +#define CAN_F9FB1_FFDB9_Msk (0x1U << CAN_F9FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB1_FFDB9 CAN_F9FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB1_FFDB10_Pos (10U) +#define CAN_F9FB1_FFDB10_Msk (0x1U << CAN_F9FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB1_FFDB10 CAN_F9FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB1_FFDB11_Pos (11U) +#define CAN_F9FB1_FFDB11_Msk (0x1U << CAN_F9FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB1_FFDB11 CAN_F9FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB1_FFDB12_Pos (12U) +#define CAN_F9FB1_FFDB12_Msk (0x1U << CAN_F9FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB1_FFDB12 CAN_F9FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB1_FFDB13_Pos (13U) +#define CAN_F9FB1_FFDB13_Msk (0x1U << CAN_F9FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB1_FFDB13 CAN_F9FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB1_FFDB14_Pos (14U) +#define CAN_F9FB1_FFDB14_Msk (0x1U << CAN_F9FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB1_FFDB14 CAN_F9FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB1_FFDB15_Pos (15U) +#define CAN_F9FB1_FFDB15_Msk (0x1U << CAN_F9FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB1_FFDB15 CAN_F9FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB1_FFDB16_Pos (16U) +#define CAN_F9FB1_FFDB16_Msk (0x1U << CAN_F9FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB1_FFDB16 CAN_F9FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB1_FFDB17_Pos (17U) +#define CAN_F9FB1_FFDB17_Msk (0x1U << CAN_F9FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB1_FFDB17 CAN_F9FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB1_FFDB18_Pos (18U) +#define CAN_F9FB1_FFDB18_Msk (0x1U << CAN_F9FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB1_FFDB18 CAN_F9FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB1_FFDB19_Pos (19U) +#define CAN_F9FB1_FFDB19_Msk (0x1U << CAN_F9FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB1_FFDB19 CAN_F9FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB1_FFDB20_Pos (20U) +#define CAN_F9FB1_FFDB20_Msk (0x1U << CAN_F9FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB1_FFDB20 CAN_F9FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB1_FFDB21_Pos (21U) +#define CAN_F9FB1_FFDB21_Msk (0x1U << CAN_F9FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB1_FFDB21 CAN_F9FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB1_FFDB22_Pos (22U) +#define CAN_F9FB1_FFDB22_Msk (0x1U << CAN_F9FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB1_FFDB22 CAN_F9FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB1_FFDB23_Pos (23U) +#define CAN_F9FB1_FFDB23_Msk (0x1U << CAN_F9FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB1_FFDB23 CAN_F9FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB1_FFDB24_Pos (24U) +#define CAN_F9FB1_FFDB24_Msk (0x1U << CAN_F9FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB1_FFDB24 CAN_F9FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB1_FFDB25_Pos (25U) +#define CAN_F9FB1_FFDB25_Msk (0x1U << CAN_F9FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB1_FFDB25 CAN_F9FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB1_FFDB26_Pos (26U) +#define CAN_F9FB1_FFDB26_Msk (0x1U << CAN_F9FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB1_FFDB26 CAN_F9FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB1_FFDB27_Pos (27U) +#define CAN_F9FB1_FFDB27_Msk (0x1U << CAN_F9FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB1_FFDB27 CAN_F9FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB1_FFDB28_Pos (28U) +#define CAN_F9FB1_FFDB28_Msk (0x1U << CAN_F9FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB1_FFDB28 CAN_F9FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB1_FFDB29_Pos (29U) +#define CAN_F9FB1_FFDB29_Msk (0x1U << CAN_F9FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB1_FFDB29 CAN_F9FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB1_FFDB30_Pos (30U) +#define CAN_F9FB1_FFDB30_Msk (0x1U << CAN_F9FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB1_FFDB30 CAN_F9FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB1_FFDB31_Pos (31U) +#define CAN_F9FB1_FFDB31_Msk (0x1U << CAN_F9FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB1_FFDB31 CAN_F9FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB1 register ******************/ +#define CAN_F10FB1_FFDB0_Pos (0U) +#define CAN_F10FB1_FFDB0_Msk (0x1U << CAN_F10FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB1_FFDB0 CAN_F10FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB1_FFDB1_Pos (1U) +#define CAN_F10FB1_FFDB1_Msk (0x1U << CAN_F10FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB1_FFDB1 CAN_F10FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB1_FFDB2_Pos (2U) +#define CAN_F10FB1_FFDB2_Msk (0x1U << CAN_F10FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB1_FFDB2 CAN_F10FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB1_FFDB3_Pos (3U) +#define CAN_F10FB1_FFDB3_Msk (0x1U << CAN_F10FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB1_FFDB3 CAN_F10FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB1_FFDB4_Pos (4U) +#define CAN_F10FB1_FFDB4_Msk (0x1U << CAN_F10FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB1_FFDB4 CAN_F10FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB1_FFDB5_Pos (5U) +#define CAN_F10FB1_FFDB5_Msk (0x1U << CAN_F10FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB1_FFDB5 CAN_F10FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB1_FFDB6_Pos (6U) +#define CAN_F10FB1_FFDB6_Msk (0x1U << CAN_F10FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB1_FFDB6 CAN_F10FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB1_FFDB7_Pos (7U) +#define CAN_F10FB1_FFDB7_Msk (0x1U << CAN_F10FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB1_FFDB7 CAN_F10FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB1_FFDB8_Pos (8U) +#define CAN_F10FB1_FFDB8_Msk (0x1U << CAN_F10FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB1_FFDB8 CAN_F10FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB1_FFDB9_Pos (9U) +#define CAN_F10FB1_FFDB9_Msk (0x1U << CAN_F10FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB1_FFDB9 CAN_F10FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB1_FFDB10_Pos (10U) +#define CAN_F10FB1_FFDB10_Msk (0x1U << CAN_F10FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB1_FFDB10 CAN_F10FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB1_FFDB11_Pos (11U) +#define CAN_F10FB1_FFDB11_Msk (0x1U << CAN_F10FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB1_FFDB11 CAN_F10FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB1_FFDB12_Pos (12U) +#define CAN_F10FB1_FFDB12_Msk (0x1U << CAN_F10FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB1_FFDB12 CAN_F10FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB1_FFDB13_Pos (13U) +#define CAN_F10FB1_FFDB13_Msk (0x1U << CAN_F10FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB1_FFDB13 CAN_F10FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB1_FFDB14_Pos (14U) +#define CAN_F10FB1_FFDB14_Msk (0x1U << CAN_F10FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB1_FFDB14 CAN_F10FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB1_FFDB15_Pos (15U) +#define CAN_F10FB1_FFDB15_Msk (0x1U << CAN_F10FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB1_FFDB15 CAN_F10FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB1_FFDB16_Pos (16U) +#define CAN_F10FB1_FFDB16_Msk (0x1U << CAN_F10FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB1_FFDB16 CAN_F10FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB1_FFDB17_Pos (17U) +#define CAN_F10FB1_FFDB17_Msk (0x1U << CAN_F10FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB1_FFDB17 CAN_F10FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB1_FFDB18_Pos (18U) +#define CAN_F10FB1_FFDB18_Msk (0x1U << CAN_F10FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB1_FFDB18 CAN_F10FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB1_FFDB19_Pos (19U) +#define CAN_F10FB1_FFDB19_Msk (0x1U << CAN_F10FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB1_FFDB19 CAN_F10FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB1_FFDB20_Pos (20U) +#define CAN_F10FB1_FFDB20_Msk (0x1U << CAN_F10FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB1_FFDB20 CAN_F10FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB1_FFDB21_Pos (21U) +#define CAN_F10FB1_FFDB21_Msk (0x1U << CAN_F10FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB1_FFDB21 CAN_F10FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB1_FFDB22_Pos (22U) +#define CAN_F10FB1_FFDB22_Msk (0x1U << CAN_F10FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB1_FFDB22 CAN_F10FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB1_FFDB23_Pos (23U) +#define CAN_F10FB1_FFDB23_Msk (0x1U << CAN_F10FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB1_FFDB23 CAN_F10FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB1_FFDB24_Pos (24U) +#define CAN_F10FB1_FFDB24_Msk (0x1U << CAN_F10FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB1_FFDB24 CAN_F10FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB1_FFDB25_Pos (25U) +#define CAN_F10FB1_FFDB25_Msk (0x1U << CAN_F10FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB1_FFDB25 CAN_F10FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB1_FFDB26_Pos (26U) +#define CAN_F10FB1_FFDB26_Msk (0x1U << CAN_F10FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB1_FFDB26 CAN_F10FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB1_FFDB27_Pos (27U) +#define CAN_F10FB1_FFDB27_Msk (0x1U << CAN_F10FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB1_FFDB27 CAN_F10FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB1_FFDB28_Pos (28U) +#define CAN_F10FB1_FFDB28_Msk (0x1U << CAN_F10FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB1_FFDB28 CAN_F10FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB1_FFDB29_Pos (29U) +#define CAN_F10FB1_FFDB29_Msk (0x1U << CAN_F10FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB1_FFDB29 CAN_F10FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB1_FFDB30_Pos (30U) +#define CAN_F10FB1_FFDB30_Msk (0x1U << CAN_F10FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB1_FFDB30 CAN_F10FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB1_FFDB31_Pos (31U) +#define CAN_F10FB1_FFDB31_Msk (0x1U << CAN_F10FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB1_FFDB31 CAN_F10FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB1 register ******************/ +#define CAN_F11FB1_FFDB0_Pos (0U) +#define CAN_F11FB1_FFDB0_Msk (0x1U << CAN_F11FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB1_FFDB0 CAN_F11FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB1_FFDB1_Pos (1U) +#define CAN_F11FB1_FFDB1_Msk (0x1U << CAN_F11FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB1_FFDB1 CAN_F11FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB1_FFDB2_Pos (2U) +#define CAN_F11FB1_FFDB2_Msk (0x1U << CAN_F11FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB1_FFDB2 CAN_F11FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB1_FFDB3_Pos (3U) +#define CAN_F11FB1_FFDB3_Msk (0x1U << CAN_F11FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB1_FFDB3 CAN_F11FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB1_FFDB4_Pos (4U) +#define CAN_F11FB1_FFDB4_Msk (0x1U << CAN_F11FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB1_FFDB4 CAN_F11FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB1_FFDB5_Pos (5U) +#define CAN_F11FB1_FFDB5_Msk (0x1U << CAN_F11FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB1_FFDB5 CAN_F11FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB1_FFDB6_Pos (6U) +#define CAN_F11FB1_FFDB6_Msk (0x1U << CAN_F11FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB1_FFDB6 CAN_F11FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB1_FFDB7_Pos (7U) +#define CAN_F11FB1_FFDB7_Msk (0x1U << CAN_F11FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB1_FFDB7 CAN_F11FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB1_FFDB8_Pos (8U) +#define CAN_F11FB1_FFDB8_Msk (0x1U << CAN_F11FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB1_FFDB8 CAN_F11FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB1_FFDB9_Pos (9U) +#define CAN_F11FB1_FFDB9_Msk (0x1U << CAN_F11FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB1_FFDB9 CAN_F11FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB1_FFDB10_Pos (10U) +#define CAN_F11FB1_FFDB10_Msk (0x1U << CAN_F11FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB1_FFDB10 CAN_F11FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB1_FFDB11_Pos (11U) +#define CAN_F11FB1_FFDB11_Msk (0x1U << CAN_F11FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB1_FFDB11 CAN_F11FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB1_FFDB12_Pos (12U) +#define CAN_F11FB1_FFDB12_Msk (0x1U << CAN_F11FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB1_FFDB12 CAN_F11FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB1_FFDB13_Pos (13U) +#define CAN_F11FB1_FFDB13_Msk (0x1U << CAN_F11FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB1_FFDB13 CAN_F11FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB1_FFDB14_Pos (14U) +#define CAN_F11FB1_FFDB14_Msk (0x1U << CAN_F11FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB1_FFDB14 CAN_F11FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB1_FFDB15_Pos (15U) +#define CAN_F11FB1_FFDB15_Msk (0x1U << CAN_F11FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB1_FFDB15 CAN_F11FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB1_FFDB16_Pos (16U) +#define CAN_F11FB1_FFDB16_Msk (0x1U << CAN_F11FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB1_FFDB16 CAN_F11FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB1_FFDB17_Pos (17U) +#define CAN_F11FB1_FFDB17_Msk (0x1U << CAN_F11FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB1_FFDB17 CAN_F11FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB1_FFDB18_Pos (18U) +#define CAN_F11FB1_FFDB18_Msk (0x1U << CAN_F11FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB1_FFDB18 CAN_F11FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB1_FFDB19_Pos (19U) +#define CAN_F11FB1_FFDB19_Msk (0x1U << CAN_F11FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB1_FFDB19 CAN_F11FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB1_FFDB20_Pos (20U) +#define CAN_F11FB1_FFDB20_Msk (0x1U << CAN_F11FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB1_FFDB20 CAN_F11FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB1_FFDB21_Pos (21U) +#define CAN_F11FB1_FFDB21_Msk (0x1U << CAN_F11FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB1_FFDB21 CAN_F11FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB1_FFDB22_Pos (22U) +#define CAN_F11FB1_FFDB22_Msk (0x1U << CAN_F11FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB1_FFDB22 CAN_F11FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB1_FFDB23_Pos (23U) +#define CAN_F11FB1_FFDB23_Msk (0x1U << CAN_F11FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB1_FFDB23 CAN_F11FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB1_FFDB24_Pos (24U) +#define CAN_F11FB1_FFDB24_Msk (0x1U << CAN_F11FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB1_FFDB24 CAN_F11FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB1_FFDB25_Pos (25U) +#define CAN_F11FB1_FFDB25_Msk (0x1U << CAN_F11FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB1_FFDB25 CAN_F11FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB1_FFDB26_Pos (26U) +#define CAN_F11FB1_FFDB26_Msk (0x1U << CAN_F11FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB1_FFDB26 CAN_F11FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB1_FFDB27_Pos (27U) +#define CAN_F11FB1_FFDB27_Msk (0x1U << CAN_F11FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB1_FFDB27 CAN_F11FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB1_FFDB28_Pos (28U) +#define CAN_F11FB1_FFDB28_Msk (0x1U << CAN_F11FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB1_FFDB28 CAN_F11FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB1_FFDB29_Pos (29U) +#define CAN_F11FB1_FFDB29_Msk (0x1U << CAN_F11FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB1_FFDB29 CAN_F11FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB1_FFDB30_Pos (30U) +#define CAN_F11FB1_FFDB30_Msk (0x1U << CAN_F11FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB1_FFDB30 CAN_F11FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB1_FFDB31_Pos (31U) +#define CAN_F11FB1_FFDB31_Msk (0x1U << CAN_F11FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB1_FFDB31 CAN_F11FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB1 register ******************/ +#define CAN_F12FB1_FFDB0_Pos (0U) +#define CAN_F12FB1_FFDB0_Msk (0x1U << CAN_F12FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB1_FFDB0 CAN_F12FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB1_FFDB1_Pos (1U) +#define CAN_F12FB1_FFDB1_Msk (0x1U << CAN_F12FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB1_FFDB1 CAN_F12FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB1_FFDB2_Pos (2U) +#define CAN_F12FB1_FFDB2_Msk (0x1U << CAN_F12FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB1_FFDB2 CAN_F12FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB1_FFDB3_Pos (3U) +#define CAN_F12FB1_FFDB3_Msk (0x1U << CAN_F12FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB1_FFDB3 CAN_F12FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB1_FFDB4_Pos (4U) +#define CAN_F12FB1_FFDB4_Msk (0x1U << CAN_F12FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB1_FFDB4 CAN_F12FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB1_FFDB5_Pos (5U) +#define CAN_F12FB1_FFDB5_Msk (0x1U << CAN_F12FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB1_FFDB5 CAN_F12FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB1_FFDB6_Pos (6U) +#define CAN_F12FB1_FFDB6_Msk (0x1U << CAN_F12FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB1_FFDB6 CAN_F12FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB1_FFDB7_Pos (7U) +#define CAN_F12FB1_FFDB7_Msk (0x1U << CAN_F12FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB1_FFDB7 CAN_F12FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB1_FFDB8_Pos (8U) +#define CAN_F12FB1_FFDB8_Msk (0x1U << CAN_F12FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB1_FFDB8 CAN_F12FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB1_FFDB9_Pos (9U) +#define CAN_F12FB1_FFDB9_Msk (0x1U << CAN_F12FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB1_FFDB9 CAN_F12FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB1_FFDB10_Pos (10U) +#define CAN_F12FB1_FFDB10_Msk (0x1U << CAN_F12FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB1_FFDB10 CAN_F12FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB1_FFDB11_Pos (11U) +#define CAN_F12FB1_FFDB11_Msk (0x1U << CAN_F12FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB1_FFDB11 CAN_F12FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB1_FFDB12_Pos (12U) +#define CAN_F12FB1_FFDB12_Msk (0x1U << CAN_F12FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB1_FFDB12 CAN_F12FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB1_FFDB13_Pos (13U) +#define CAN_F12FB1_FFDB13_Msk (0x1U << CAN_F12FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB1_FFDB13 CAN_F12FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB1_FFDB14_Pos (14U) +#define CAN_F12FB1_FFDB14_Msk (0x1U << CAN_F12FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB1_FFDB14 CAN_F12FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB1_FFDB15_Pos (15U) +#define CAN_F12FB1_FFDB15_Msk (0x1U << CAN_F12FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB1_FFDB15 CAN_F12FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB1_FFDB16_Pos (16U) +#define CAN_F12FB1_FFDB16_Msk (0x1U << CAN_F12FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB1_FFDB16 CAN_F12FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB1_FFDB17_Pos (17U) +#define CAN_F12FB1_FFDB17_Msk (0x1U << CAN_F12FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB1_FFDB17 CAN_F12FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB1_FFDB18_Pos (18U) +#define CAN_F12FB1_FFDB18_Msk (0x1U << CAN_F12FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB1_FFDB18 CAN_F12FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB1_FFDB19_Pos (19U) +#define CAN_F12FB1_FFDB19_Msk (0x1U << CAN_F12FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB1_FFDB19 CAN_F12FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB1_FFDB20_Pos (20U) +#define CAN_F12FB1_FFDB20_Msk (0x1U << CAN_F12FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB1_FFDB20 CAN_F12FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB1_FFDB21_Pos (21U) +#define CAN_F12FB1_FFDB21_Msk (0x1U << CAN_F12FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB1_FFDB21 CAN_F12FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB1_FFDB22_Pos (22U) +#define CAN_F12FB1_FFDB22_Msk (0x1U << CAN_F12FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB1_FFDB22 CAN_F12FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB1_FFDB23_Pos (23U) +#define CAN_F12FB1_FFDB23_Msk (0x1U << CAN_F12FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB1_FFDB23 CAN_F12FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB1_FFDB24_Pos (24U) +#define CAN_F12FB1_FFDB24_Msk (0x1U << CAN_F12FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB1_FFDB24 CAN_F12FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB1_FFDB25_Pos (25U) +#define CAN_F12FB1_FFDB25_Msk (0x1U << CAN_F12FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB1_FFDB25 CAN_F12FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB1_FFDB26_Pos (26U) +#define CAN_F12FB1_FFDB26_Msk (0x1U << CAN_F12FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB1_FFDB26 CAN_F12FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB1_FFDB27_Pos (27U) +#define CAN_F12FB1_FFDB27_Msk (0x1U << CAN_F12FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB1_FFDB27 CAN_F12FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB1_FFDB28_Pos (28U) +#define CAN_F12FB1_FFDB28_Msk (0x1U << CAN_F12FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB1_FFDB28 CAN_F12FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB1_FFDB29_Pos (29U) +#define CAN_F12FB1_FFDB29_Msk (0x1U << CAN_F12FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB1_FFDB29 CAN_F12FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB1_FFDB30_Pos (30U) +#define CAN_F12FB1_FFDB30_Msk (0x1U << CAN_F12FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB1_FFDB30 CAN_F12FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB1_FFDB31_Pos (31U) +#define CAN_F12FB1_FFDB31_Msk (0x1U << CAN_F12FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB1_FFDB31 CAN_F12FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB1 register ******************/ +#define CAN_F13FB1_FFDB0_Pos (0U) +#define CAN_F13FB1_FFDB0_Msk (0x1U << CAN_F13FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB1_FFDB0 CAN_F13FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB1_FFDB1_Pos (1U) +#define CAN_F13FB1_FFDB1_Msk (0x1U << CAN_F13FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB1_FFDB1 CAN_F13FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB1_FFDB2_Pos (2U) +#define CAN_F13FB1_FFDB2_Msk (0x1U << CAN_F13FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB1_FFDB2 CAN_F13FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB1_FFDB3_Pos (3U) +#define CAN_F13FB1_FFDB3_Msk (0x1U << CAN_F13FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB1_FFDB3 CAN_F13FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB1_FFDB4_Pos (4U) +#define CAN_F13FB1_FFDB4_Msk (0x1U << CAN_F13FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB1_FFDB4 CAN_F13FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB1_FFDB5_Pos (5U) +#define CAN_F13FB1_FFDB5_Msk (0x1U << CAN_F13FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB1_FFDB5 CAN_F13FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB1_FFDB6_Pos (6U) +#define CAN_F13FB1_FFDB6_Msk (0x1U << CAN_F13FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB1_FFDB6 CAN_F13FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB1_FFDB7_Pos (7U) +#define CAN_F13FB1_FFDB7_Msk (0x1U << CAN_F13FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB1_FFDB7 CAN_F13FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB1_FFDB8_Pos (8U) +#define CAN_F13FB1_FFDB8_Msk (0x1U << CAN_F13FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB1_FFDB8 CAN_F13FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB1_FFDB9_Pos (9U) +#define CAN_F13FB1_FFDB9_Msk (0x1U << CAN_F13FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB1_FFDB9 CAN_F13FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB1_FFDB10_Pos (10U) +#define CAN_F13FB1_FFDB10_Msk (0x1U << CAN_F13FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB1_FFDB10 CAN_F13FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB1_FFDB11_Pos (11U) +#define CAN_F13FB1_FFDB11_Msk (0x1U << CAN_F13FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB1_FFDB11 CAN_F13FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB1_FFDB12_Pos (12U) +#define CAN_F13FB1_FFDB12_Msk (0x1U << CAN_F13FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB1_FFDB12 CAN_F13FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB1_FFDB13_Pos (13U) +#define CAN_F13FB1_FFDB13_Msk (0x1U << CAN_F13FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB1_FFDB13 CAN_F13FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB1_FFDB14_Pos (14U) +#define CAN_F13FB1_FFDB14_Msk (0x1U << CAN_F13FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB1_FFDB14 CAN_F13FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB1_FFDB15_Pos (15U) +#define CAN_F13FB1_FFDB15_Msk (0x1U << CAN_F13FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB1_FFDB15 CAN_F13FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB1_FFDB16_Pos (16U) +#define CAN_F13FB1_FFDB16_Msk (0x1U << CAN_F13FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB1_FFDB16 CAN_F13FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB1_FFDB17_Pos (17U) +#define CAN_F13FB1_FFDB17_Msk (0x1U << CAN_F13FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB1_FFDB17 CAN_F13FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB1_FFDB18_Pos (18U) +#define CAN_F13FB1_FFDB18_Msk (0x1U << CAN_F13FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB1_FFDB18 CAN_F13FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB1_FFDB19_Pos (19U) +#define CAN_F13FB1_FFDB19_Msk (0x1U << CAN_F13FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB1_FFDB19 CAN_F13FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB1_FFDB20_Pos (20U) +#define CAN_F13FB1_FFDB20_Msk (0x1U << CAN_F13FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB1_FFDB20 CAN_F13FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB1_FFDB21_Pos (21U) +#define CAN_F13FB1_FFDB21_Msk (0x1U << CAN_F13FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB1_FFDB21 CAN_F13FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB1_FFDB22_Pos (22U) +#define CAN_F13FB1_FFDB22_Msk (0x1U << CAN_F13FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB1_FFDB22 CAN_F13FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB1_FFDB23_Pos (23U) +#define CAN_F13FB1_FFDB23_Msk (0x1U << CAN_F13FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB1_FFDB23 CAN_F13FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB1_FFDB24_Pos (24U) +#define CAN_F13FB1_FFDB24_Msk (0x1U << CAN_F13FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB1_FFDB24 CAN_F13FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB1_FFDB25_Pos (25U) +#define CAN_F13FB1_FFDB25_Msk (0x1U << CAN_F13FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB1_FFDB25 CAN_F13FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB1_FFDB26_Pos (26U) +#define CAN_F13FB1_FFDB26_Msk (0x1U << CAN_F13FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB1_FFDB26 CAN_F13FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB1_FFDB27_Pos (27U) +#define CAN_F13FB1_FFDB27_Msk (0x1U << CAN_F13FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB1_FFDB27 CAN_F13FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB1_FFDB28_Pos (28U) +#define CAN_F13FB1_FFDB28_Msk (0x1U << CAN_F13FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB1_FFDB28 CAN_F13FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB1_FFDB29_Pos (29U) +#define CAN_F13FB1_FFDB29_Msk (0x1U << CAN_F13FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB1_FFDB29 CAN_F13FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB1_FFDB30_Pos (30U) +#define CAN_F13FB1_FFDB30_Msk (0x1U << CAN_F13FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB1_FFDB30 CAN_F13FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB1_FFDB31_Pos (31U) +#define CAN_F13FB1_FFDB31_Msk (0x1U << CAN_F13FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB1_FFDB31 CAN_F13FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F0FB2 register *******************/ +#define CAN_F0FB2_FFDB0_Pos (0U) +#define CAN_F0FB2_FFDB0_Msk (0x1U << CAN_F0FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB2_FFDB0 CAN_F0FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB2_FFDB1_Pos (1U) +#define CAN_F0FB2_FFDB1_Msk (0x1U << CAN_F0FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB2_FFDB1 CAN_F0FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB2_FFDB2_Pos (2U) +#define CAN_F0FB2_FFDB2_Msk (0x1U << CAN_F0FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB2_FFDB2 CAN_F0FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB2_FFDB3_Pos (3U) +#define CAN_F0FB2_FFDB3_Msk (0x1U << CAN_F0FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB2_FFDB3 CAN_F0FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB2_FFDB4_Pos (4U) +#define CAN_F0FB2_FFDB4_Msk (0x1U << CAN_F0FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB2_FFDB4 CAN_F0FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB2_FFDB5_Pos (5U) +#define CAN_F0FB2_FFDB5_Msk (0x1U << CAN_F0FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB2_FFDB5 CAN_F0FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB2_FFDB6_Pos (6U) +#define CAN_F0FB2_FFDB6_Msk (0x1U << CAN_F0FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB2_FFDB6 CAN_F0FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB2_FFDB7_Pos (7U) +#define CAN_F0FB2_FFDB7_Msk (0x1U << CAN_F0FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB2_FFDB7 CAN_F0FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB2_FFDB8_Pos (8U) +#define CAN_F0FB2_FFDB8_Msk (0x1U << CAN_F0FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB2_FFDB8 CAN_F0FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB2_FFDB9_Pos (9U) +#define CAN_F0FB2_FFDB9_Msk (0x1U << CAN_F0FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB2_FFDB9 CAN_F0FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB2_FFDB10_Pos (10U) +#define CAN_F0FB2_FFDB10_Msk (0x1U << CAN_F0FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB2_FFDB10 CAN_F0FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB2_FFDB11_Pos (11U) +#define CAN_F0FB2_FFDB11_Msk (0x1U << CAN_F0FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB2_FFDB11 CAN_F0FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB2_FFDB12_Pos (12U) +#define CAN_F0FB2_FFDB12_Msk (0x1U << CAN_F0FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB2_FFDB12 CAN_F0FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB2_FFDB13_Pos (13U) +#define CAN_F0FB2_FFDB13_Msk (0x1U << CAN_F0FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB2_FFDB13 CAN_F0FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB2_FFDB14_Pos (14U) +#define CAN_F0FB2_FFDB14_Msk (0x1U << CAN_F0FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB2_FFDB14 CAN_F0FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB2_FFDB15_Pos (15U) +#define CAN_F0FB2_FFDB15_Msk (0x1U << CAN_F0FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB2_FFDB15 CAN_F0FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB2_FFDB16_Pos (16U) +#define CAN_F0FB2_FFDB16_Msk (0x1U << CAN_F0FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB2_FFDB16 CAN_F0FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB2_FFDB17_Pos (17U) +#define CAN_F0FB2_FFDB17_Msk (0x1U << CAN_F0FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB2_FFDB17 CAN_F0FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB2_FFDB18_Pos (18U) +#define CAN_F0FB2_FFDB18_Msk (0x1U << CAN_F0FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB2_FFDB18 CAN_F0FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB2_FFDB19_Pos (19U) +#define CAN_F0FB2_FFDB19_Msk (0x1U << CAN_F0FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB2_FFDB19 CAN_F0FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB2_FFDB20_Pos (20U) +#define CAN_F0FB2_FFDB20_Msk (0x1U << CAN_F0FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB2_FFDB20 CAN_F0FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB2_FFDB21_Pos (21U) +#define CAN_F0FB2_FFDB21_Msk (0x1U << CAN_F0FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB2_FFDB21 CAN_F0FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB2_FFDB22_Pos (22U) +#define CAN_F0FB2_FFDB22_Msk (0x1U << CAN_F0FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB2_FFDB22 CAN_F0FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB2_FFDB23_Pos (23U) +#define CAN_F0FB2_FFDB23_Msk (0x1U << CAN_F0FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB2_FFDB23 CAN_F0FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB2_FFDB24_Pos (24U) +#define CAN_F0FB2_FFDB24_Msk (0x1U << CAN_F0FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB2_FFDB24 CAN_F0FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB2_FFDB25_Pos (25U) +#define CAN_F0FB2_FFDB25_Msk (0x1U << CAN_F0FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB2_FFDB25 CAN_F0FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB2_FFDB26_Pos (26U) +#define CAN_F0FB2_FFDB26_Msk (0x1U << CAN_F0FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB2_FFDB26 CAN_F0FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB2_FFDB27_Pos (27U) +#define CAN_F0FB2_FFDB27_Msk (0x1U << CAN_F0FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB2_FFDB27 CAN_F0FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB2_FFDB28_Pos (28U) +#define CAN_F0FB2_FFDB28_Msk (0x1U << CAN_F0FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB2_FFDB28 CAN_F0FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB2_FFDB29_Pos (29U) +#define CAN_F0FB2_FFDB29_Msk (0x1U << CAN_F0FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB2_FFDB29 CAN_F0FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB2_FFDB30_Pos (30U) +#define CAN_F0FB2_FFDB30_Msk (0x1U << CAN_F0FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB2_FFDB30 CAN_F0FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB2_FFDB31_Pos (31U) +#define CAN_F0FB2_FFDB31_Msk (0x1U << CAN_F0FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB2_FFDB31 CAN_F0FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB2 register *******************/ +#define CAN_F1FB2_FFDB0_Pos (0U) +#define CAN_F1FB2_FFDB0_Msk (0x1U << CAN_F1FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB2_FFDB0 CAN_F1FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB2_FFDB1_Pos (1U) +#define CAN_F1FB2_FFDB1_Msk (0x1U << CAN_F1FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB2_FFDB1 CAN_F1FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB2_FFDB2_Pos (2U) +#define CAN_F1FB2_FFDB2_Msk (0x1U << CAN_F1FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB2_FFDB2 CAN_F1FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB2_FFDB3_Pos (3U) +#define CAN_F1FB2_FFDB3_Msk (0x1U << CAN_F1FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB2_FFDB3 CAN_F1FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB2_FFDB4_Pos (4U) +#define CAN_F1FB2_FFDB4_Msk (0x1U << CAN_F1FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB2_FFDB4 CAN_F1FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB2_FFDB5_Pos (5U) +#define CAN_F1FB2_FFDB5_Msk (0x1U << CAN_F1FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB2_FFDB5 CAN_F1FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB2_FFDB6_Pos (6U) +#define CAN_F1FB2_FFDB6_Msk (0x1U << CAN_F1FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB2_FFDB6 CAN_F1FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB2_FFDB7_Pos (7U) +#define CAN_F1FB2_FFDB7_Msk (0x1U << CAN_F1FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB2_FFDB7 CAN_F1FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB2_FFDB8_Pos (8U) +#define CAN_F1FB2_FFDB8_Msk (0x1U << CAN_F1FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB2_FFDB8 CAN_F1FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB2_FFDB9_Pos (9U) +#define CAN_F1FB2_FFDB9_Msk (0x1U << CAN_F1FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB2_FFDB9 CAN_F1FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB2_FFDB10_Pos (10U) +#define CAN_F1FB2_FFDB10_Msk (0x1U << CAN_F1FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB2_FFDB10 CAN_F1FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB2_FFDB11_Pos (11U) +#define CAN_F1FB2_FFDB11_Msk (0x1U << CAN_F1FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB2_FFDB11 CAN_F1FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB2_FFDB12_Pos (12U) +#define CAN_F1FB2_FFDB12_Msk (0x1U << CAN_F1FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB2_FFDB12 CAN_F1FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB2_FFDB13_Pos (13U) +#define CAN_F1FB2_FFDB13_Msk (0x1U << CAN_F1FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB2_FFDB13 CAN_F1FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB2_FFDB14_Pos (14U) +#define CAN_F1FB2_FFDB14_Msk (0x1U << CAN_F1FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB2_FFDB14 CAN_F1FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB2_FFDB15_Pos (15U) +#define CAN_F1FB2_FFDB15_Msk (0x1U << CAN_F1FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB2_FFDB15 CAN_F1FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB2_FFDB16_Pos (16U) +#define CAN_F1FB2_FFDB16_Msk (0x1U << CAN_F1FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB2_FFDB16 CAN_F1FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB2_FFDB17_Pos (17U) +#define CAN_F1FB2_FFDB17_Msk (0x1U << CAN_F1FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB2_FFDB17 CAN_F1FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB2_FFDB18_Pos (18U) +#define CAN_F1FB2_FFDB18_Msk (0x1U << CAN_F1FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB2_FFDB18 CAN_F1FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB2_FFDB19_Pos (19U) +#define CAN_F1FB2_FFDB19_Msk (0x1U << CAN_F1FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB2_FFDB19 CAN_F1FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB2_FFDB20_Pos (20U) +#define CAN_F1FB2_FFDB20_Msk (0x1U << CAN_F1FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB2_FFDB20 CAN_F1FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB2_FFDB21_Pos (21U) +#define CAN_F1FB2_FFDB21_Msk (0x1U << CAN_F1FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB2_FFDB21 CAN_F1FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB2_FFDB22_Pos (22U) +#define CAN_F1FB2_FFDB22_Msk (0x1U << CAN_F1FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB2_FFDB22 CAN_F1FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB2_FFDB23_Pos (23U) +#define CAN_F1FB2_FFDB23_Msk (0x1U << CAN_F1FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB2_FFDB23 CAN_F1FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB2_FFDB24_Pos (24U) +#define CAN_F1FB2_FFDB24_Msk (0x1U << CAN_F1FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB2_FFDB24 CAN_F1FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB2_FFDB25_Pos (25U) +#define CAN_F1FB2_FFDB25_Msk (0x1U << CAN_F1FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB2_FFDB25 CAN_F1FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB2_FFDB26_Pos (26U) +#define CAN_F1FB2_FFDB26_Msk (0x1U << CAN_F1FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB2_FFDB26 CAN_F1FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB2_FFDB27_Pos (27U) +#define CAN_F1FB2_FFDB27_Msk (0x1U << CAN_F1FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB2_FFDB27 CAN_F1FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB2_FFDB28_Pos (28U) +#define CAN_F1FB2_FFDB28_Msk (0x1U << CAN_F1FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB2_FFDB28 CAN_F1FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB2_FFDB29_Pos (29U) +#define CAN_F1FB2_FFDB29_Msk (0x1U << CAN_F1FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB2_FFDB29 CAN_F1FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB2_FFDB30_Pos (30U) +#define CAN_F1FB2_FFDB30_Msk (0x1U << CAN_F1FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB2_FFDB30 CAN_F1FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB2_FFDB31_Pos (31U) +#define CAN_F1FB2_FFDB31_Msk (0x1U << CAN_F1FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB2_FFDB31 CAN_F1FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB2 register *******************/ +#define CAN_F2FB2_FFDB0_Pos (0U) +#define CAN_F2FB2_FFDB0_Msk (0x1U << CAN_F2FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB2_FFDB0 CAN_F2FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB2_FFDB1_Pos (1U) +#define CAN_F2FB2_FFDB1_Msk (0x1U << CAN_F2FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB2_FFDB1 CAN_F2FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB2_FFDB2_Pos (2U) +#define CAN_F2FB2_FFDB2_Msk (0x1U << CAN_F2FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB2_FFDB2 CAN_F2FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB2_FFDB3_Pos (3U) +#define CAN_F2FB2_FFDB3_Msk (0x1U << CAN_F2FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB2_FFDB3 CAN_F2FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB2_FFDB4_Pos (4U) +#define CAN_F2FB2_FFDB4_Msk (0x1U << CAN_F2FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB2_FFDB4 CAN_F2FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB2_FFDB5_Pos (5U) +#define CAN_F2FB2_FFDB5_Msk (0x1U << CAN_F2FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB2_FFDB5 CAN_F2FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB2_FFDB6_Pos (6U) +#define CAN_F2FB2_FFDB6_Msk (0x1U << CAN_F2FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB2_FFDB6 CAN_F2FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB2_FFDB7_Pos (7U) +#define CAN_F2FB2_FFDB7_Msk (0x1U << CAN_F2FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB2_FFDB7 CAN_F2FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB2_FFDB8_Pos (8U) +#define CAN_F2FB2_FFDB8_Msk (0x1U << CAN_F2FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB2_FFDB8 CAN_F2FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB2_FFDB9_Pos (9U) +#define CAN_F2FB2_FFDB9_Msk (0x1U << CAN_F2FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB2_FFDB9 CAN_F2FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB2_FFDB10_Pos (10U) +#define CAN_F2FB2_FFDB10_Msk (0x1U << CAN_F2FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB2_FFDB10 CAN_F2FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB2_FFDB11_Pos (11U) +#define CAN_F2FB2_FFDB11_Msk (0x1U << CAN_F2FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB2_FFDB11 CAN_F2FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB2_FFDB12_Pos (12U) +#define CAN_F2FB2_FFDB12_Msk (0x1U << CAN_F2FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB2_FFDB12 CAN_F2FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB2_FFDB13_Pos (13U) +#define CAN_F2FB2_FFDB13_Msk (0x1U << CAN_F2FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB2_FFDB13 CAN_F2FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB2_FFDB14_Pos (14U) +#define CAN_F2FB2_FFDB14_Msk (0x1U << CAN_F2FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB2_FFDB14 CAN_F2FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB2_FFDB15_Pos (15U) +#define CAN_F2FB2_FFDB15_Msk (0x1U << CAN_F2FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB2_FFDB15 CAN_F2FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB2_FFDB16_Pos (16U) +#define CAN_F2FB2_FFDB16_Msk (0x1U << CAN_F2FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB2_FFDB16 CAN_F2FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB2_FFDB17_Pos (17U) +#define CAN_F2FB2_FFDB17_Msk (0x1U << CAN_F2FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB2_FFDB17 CAN_F2FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB2_FFDB18_Pos (18U) +#define CAN_F2FB2_FFDB18_Msk (0x1U << CAN_F2FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB2_FFDB18 CAN_F2FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB2_FFDB19_Pos (19U) +#define CAN_F2FB2_FFDB19_Msk (0x1U << CAN_F2FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB2_FFDB19 CAN_F2FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB2_FFDB20_Pos (20U) +#define CAN_F2FB2_FFDB20_Msk (0x1U << CAN_F2FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB2_FFDB20 CAN_F2FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB2_FFDB21_Pos (21U) +#define CAN_F2FB2_FFDB21_Msk (0x1U << CAN_F2FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB2_FFDB21 CAN_F2FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB2_FFDB22_Pos (22U) +#define CAN_F2FB2_FFDB22_Msk (0x1U << CAN_F2FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB2_FFDB22 CAN_F2FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB2_FFDB23_Pos (23U) +#define CAN_F2FB2_FFDB23_Msk (0x1U << CAN_F2FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB2_FFDB23 CAN_F2FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB2_FFDB24_Pos (24U) +#define CAN_F2FB2_FFDB24_Msk (0x1U << CAN_F2FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB2_FFDB24 CAN_F2FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB2_FFDB25_Pos (25U) +#define CAN_F2FB2_FFDB25_Msk (0x1U << CAN_F2FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB2_FFDB25 CAN_F2FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB2_FFDB26_Pos (26U) +#define CAN_F2FB2_FFDB26_Msk (0x1U << CAN_F2FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB2_FFDB26 CAN_F2FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB2_FFDB27_Pos (27U) +#define CAN_F2FB2_FFDB27_Msk (0x1U << CAN_F2FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB2_FFDB27 CAN_F2FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB2_FFDB28_Pos (28U) +#define CAN_F2FB2_FFDB28_Msk (0x1U << CAN_F2FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB2_FFDB28 CAN_F2FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB2_FFDB29_Pos (29U) +#define CAN_F2FB2_FFDB29_Msk (0x1U << CAN_F2FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB2_FFDB29 CAN_F2FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB2_FFDB30_Pos (30U) +#define CAN_F2FB2_FFDB30_Msk (0x1U << CAN_F2FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB2_FFDB30 CAN_F2FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB2_FFDB31_Pos (31U) +#define CAN_F2FB2_FFDB31_Msk (0x1U << CAN_F2FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB2_FFDB31 CAN_F2FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB2 register *******************/ +#define CAN_F3FB2_FFDB0_Pos (0U) +#define CAN_F3FB2_FFDB0_Msk (0x1U << CAN_F3FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB2_FFDB0 CAN_F3FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB2_FFDB1_Pos (1U) +#define CAN_F3FB2_FFDB1_Msk (0x1U << CAN_F3FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB2_FFDB1 CAN_F3FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB2_FFDB2_Pos (2U) +#define CAN_F3FB2_FFDB2_Msk (0x1U << CAN_F3FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB2_FFDB2 CAN_F3FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB2_FFDB3_Pos (3U) +#define CAN_F3FB2_FFDB3_Msk (0x1U << CAN_F3FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB2_FFDB3 CAN_F3FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB2_FFDB4_Pos (4U) +#define CAN_F3FB2_FFDB4_Msk (0x1U << CAN_F3FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB2_FFDB4 CAN_F3FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB2_FFDB5_Pos (5U) +#define CAN_F3FB2_FFDB5_Msk (0x1U << CAN_F3FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB2_FFDB5 CAN_F3FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB2_FFDB6_Pos (6U) +#define CAN_F3FB2_FFDB6_Msk (0x1U << CAN_F3FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB2_FFDB6 CAN_F3FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB2_FFDB7_Pos (7U) +#define CAN_F3FB2_FFDB7_Msk (0x1U << CAN_F3FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB2_FFDB7 CAN_F3FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB2_FFDB8_Pos (8U) +#define CAN_F3FB2_FFDB8_Msk (0x1U << CAN_F3FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB2_FFDB8 CAN_F3FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB2_FFDB9_Pos (9U) +#define CAN_F3FB2_FFDB9_Msk (0x1U << CAN_F3FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB2_FFDB9 CAN_F3FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB2_FFDB10_Pos (10U) +#define CAN_F3FB2_FFDB10_Msk (0x1U << CAN_F3FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB2_FFDB10 CAN_F3FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB2_FFDB11_Pos (11U) +#define CAN_F3FB2_FFDB11_Msk (0x1U << CAN_F3FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB2_FFDB11 CAN_F3FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB2_FFDB12_Pos (12U) +#define CAN_F3FB2_FFDB12_Msk (0x1U << CAN_F3FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB2_FFDB12 CAN_F3FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB2_FFDB13_Pos (13U) +#define CAN_F3FB2_FFDB13_Msk (0x1U << CAN_F3FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB2_FFDB13 CAN_F3FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB2_FFDB14_Pos (14U) +#define CAN_F3FB2_FFDB14_Msk (0x1U << CAN_F3FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB2_FFDB14 CAN_F3FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB2_FFDB15_Pos (15U) +#define CAN_F3FB2_FFDB15_Msk (0x1U << CAN_F3FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB2_FFDB15 CAN_F3FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB2_FFDB16_Pos (16U) +#define CAN_F3FB2_FFDB16_Msk (0x1U << CAN_F3FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB2_FFDB16 CAN_F3FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB2_FFDB17_Pos (17U) +#define CAN_F3FB2_FFDB17_Msk (0x1U << CAN_F3FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB2_FFDB17 CAN_F3FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB2_FFDB18_Pos (18U) +#define CAN_F3FB2_FFDB18_Msk (0x1U << CAN_F3FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB2_FFDB18 CAN_F3FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB2_FFDB19_Pos (19U) +#define CAN_F3FB2_FFDB19_Msk (0x1U << CAN_F3FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB2_FFDB19 CAN_F3FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB2_FFDB20_Pos (20U) +#define CAN_F3FB2_FFDB20_Msk (0x1U << CAN_F3FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB2_FFDB20 CAN_F3FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB2_FFDB21_Pos (21U) +#define CAN_F3FB2_FFDB21_Msk (0x1U << CAN_F3FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB2_FFDB21 CAN_F3FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB2_FFDB22_Pos (22U) +#define CAN_F3FB2_FFDB22_Msk (0x1U << CAN_F3FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB2_FFDB22 CAN_F3FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB2_FFDB23_Pos (23U) +#define CAN_F3FB2_FFDB23_Msk (0x1U << CAN_F3FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB2_FFDB23 CAN_F3FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB2_FFDB24_Pos (24U) +#define CAN_F3FB2_FFDB24_Msk (0x1U << CAN_F3FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB2_FFDB24 CAN_F3FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB2_FFDB25_Pos (25U) +#define CAN_F3FB2_FFDB25_Msk (0x1U << CAN_F3FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB2_FFDB25 CAN_F3FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB2_FFDB26_Pos (26U) +#define CAN_F3FB2_FFDB26_Msk (0x1U << CAN_F3FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB2_FFDB26 CAN_F3FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB2_FFDB27_Pos (27U) +#define CAN_F3FB2_FFDB27_Msk (0x1U << CAN_F3FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB2_FFDB27 CAN_F3FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB2_FFDB28_Pos (28U) +#define CAN_F3FB2_FFDB28_Msk (0x1U << CAN_F3FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB2_FFDB28 CAN_F3FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB2_FFDB29_Pos (29U) +#define CAN_F3FB2_FFDB29_Msk (0x1U << CAN_F3FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB2_FFDB29 CAN_F3FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB2_FFDB30_Pos (30U) +#define CAN_F3FB2_FFDB30_Msk (0x1U << CAN_F3FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB2_FFDB30 CAN_F3FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB2_FFDB31_Pos (31U) +#define CAN_F3FB2_FFDB31_Msk (0x1U << CAN_F3FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB2_FFDB31 CAN_F3FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB2 register *******************/ +#define CAN_F4FB2_FFDB0_Pos (0U) +#define CAN_F4FB2_FFDB0_Msk (0x1U << CAN_F4FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB2_FFDB0 CAN_F4FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB2_FFDB1_Pos (1U) +#define CAN_F4FB2_FFDB1_Msk (0x1U << CAN_F4FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB2_FFDB1 CAN_F4FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB2_FFDB2_Pos (2U) +#define CAN_F4FB2_FFDB2_Msk (0x1U << CAN_F4FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB2_FFDB2 CAN_F4FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB2_FFDB3_Pos (3U) +#define CAN_F4FB2_FFDB3_Msk (0x1U << CAN_F4FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB2_FFDB3 CAN_F4FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB2_FFDB4_Pos (4U) +#define CAN_F4FB2_FFDB4_Msk (0x1U << CAN_F4FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB2_FFDB4 CAN_F4FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB2_FFDB5_Pos (5U) +#define CAN_F4FB2_FFDB5_Msk (0x1U << CAN_F4FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB2_FFDB5 CAN_F4FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB2_FFDB6_Pos (6U) +#define CAN_F4FB2_FFDB6_Msk (0x1U << CAN_F4FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB2_FFDB6 CAN_F4FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB2_FFDB7_Pos (7U) +#define CAN_F4FB2_FFDB7_Msk (0x1U << CAN_F4FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB2_FFDB7 CAN_F4FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB2_FFDB8_Pos (8U) +#define CAN_F4FB2_FFDB8_Msk (0x1U << CAN_F4FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB2_FFDB8 CAN_F4FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB2_FFDB9_Pos (9U) +#define CAN_F4FB2_FFDB9_Msk (0x1U << CAN_F4FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB2_FFDB9 CAN_F4FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB2_FFDB10_Pos (10U) +#define CAN_F4FB2_FFDB10_Msk (0x1U << CAN_F4FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB2_FFDB10 CAN_F4FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB2_FFDB11_Pos (11U) +#define CAN_F4FB2_FFDB11_Msk (0x1U << CAN_F4FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB2_FFDB11 CAN_F4FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB2_FFDB12_Pos (12U) +#define CAN_F4FB2_FFDB12_Msk (0x1U << CAN_F4FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB2_FFDB12 CAN_F4FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB2_FFDB13_Pos (13U) +#define CAN_F4FB2_FFDB13_Msk (0x1U << CAN_F4FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB2_FFDB13 CAN_F4FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB2_FFDB14_Pos (14U) +#define CAN_F4FB2_FFDB14_Msk (0x1U << CAN_F4FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB2_FFDB14 CAN_F4FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB2_FFDB15_Pos (15U) +#define CAN_F4FB2_FFDB15_Msk (0x1U << CAN_F4FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB2_FFDB15 CAN_F4FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB2_FFDB16_Pos (16U) +#define CAN_F4FB2_FFDB16_Msk (0x1U << CAN_F4FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB2_FFDB16 CAN_F4FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB2_FFDB17_Pos (17U) +#define CAN_F4FB2_FFDB17_Msk (0x1U << CAN_F4FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB2_FFDB17 CAN_F4FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB2_FFDB18_Pos (18U) +#define CAN_F4FB2_FFDB18_Msk (0x1U << CAN_F4FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB2_FFDB18 CAN_F4FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB2_FFDB19_Pos (19U) +#define CAN_F4FB2_FFDB19_Msk (0x1U << CAN_F4FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB2_FFDB19 CAN_F4FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB2_FFDB20_Pos (20U) +#define CAN_F4FB2_FFDB20_Msk (0x1U << CAN_F4FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB2_FFDB20 CAN_F4FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB2_FFDB21_Pos (21U) +#define CAN_F4FB2_FFDB21_Msk (0x1U << CAN_F4FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB2_FFDB21 CAN_F4FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB2_FFDB22_Pos (22U) +#define CAN_F4FB2_FFDB22_Msk (0x1U << CAN_F4FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB2_FFDB22 CAN_F4FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB2_FFDB23_Pos (23U) +#define CAN_F4FB2_FFDB23_Msk (0x1U << CAN_F4FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB2_FFDB23 CAN_F4FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB2_FFDB24_Pos (24U) +#define CAN_F4FB2_FFDB24_Msk (0x1U << CAN_F4FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB2_FFDB24 CAN_F4FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB2_FFDB25_Pos (25U) +#define CAN_F4FB2_FFDB25_Msk (0x1U << CAN_F4FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB2_FFDB25 CAN_F4FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB2_FFDB26_Pos (26U) +#define CAN_F4FB2_FFDB26_Msk (0x1U << CAN_F4FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB2_FFDB26 CAN_F4FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB2_FFDB27_Pos (27U) +#define CAN_F4FB2_FFDB27_Msk (0x1U << CAN_F4FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB2_FFDB27 CAN_F4FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB2_FFDB28_Pos (28U) +#define CAN_F4FB2_FFDB28_Msk (0x1U << CAN_F4FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB2_FFDB28 CAN_F4FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB2_FFDB29_Pos (29U) +#define CAN_F4FB2_FFDB29_Msk (0x1U << CAN_F4FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB2_FFDB29 CAN_F4FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB2_FFDB30_Pos (30U) +#define CAN_F4FB2_FFDB30_Msk (0x1U << CAN_F4FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB2_FFDB30 CAN_F4FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB2_FFDB31_Pos (31U) +#define CAN_F4FB2_FFDB31_Msk (0x1U << CAN_F4FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB2_FFDB31 CAN_F4FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB2 register *******************/ +#define CAN_F5FB2_FFDB0_Pos (0U) +#define CAN_F5FB2_FFDB0_Msk (0x1U << CAN_F5FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB2_FFDB0 CAN_F5FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB2_FFDB1_Pos (1U) +#define CAN_F5FB2_FFDB1_Msk (0x1U << CAN_F5FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB2_FFDB1 CAN_F5FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB2_FFDB2_Pos (2U) +#define CAN_F5FB2_FFDB2_Msk (0x1U << CAN_F5FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB2_FFDB2 CAN_F5FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB2_FFDB3_Pos (3U) +#define CAN_F5FB2_FFDB3_Msk (0x1U << CAN_F5FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB2_FFDB3 CAN_F5FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB2_FFDB4_Pos (4U) +#define CAN_F5FB2_FFDB4_Msk (0x1U << CAN_F5FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB2_FFDB4 CAN_F5FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB2_FFDB5_Pos (5U) +#define CAN_F5FB2_FFDB5_Msk (0x1U << CAN_F5FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB2_FFDB5 CAN_F5FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB2_FFDB6_Pos (6U) +#define CAN_F5FB2_FFDB6_Msk (0x1U << CAN_F5FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB2_FFDB6 CAN_F5FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB2_FFDB7_Pos (7U) +#define CAN_F5FB2_FFDB7_Msk (0x1U << CAN_F5FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB2_FFDB7 CAN_F5FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB2_FFDB8_Pos (8U) +#define CAN_F5FB2_FFDB8_Msk (0x1U << CAN_F5FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB2_FFDB8 CAN_F5FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB2_FFDB9_Pos (9U) +#define CAN_F5FB2_FFDB9_Msk (0x1U << CAN_F5FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB2_FFDB9 CAN_F5FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB2_FFDB10_Pos (10U) +#define CAN_F5FB2_FFDB10_Msk (0x1U << CAN_F5FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB2_FFDB10 CAN_F5FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB2_FFDB11_Pos (11U) +#define CAN_F5FB2_FFDB11_Msk (0x1U << CAN_F5FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB2_FFDB11 CAN_F5FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB2_FFDB12_Pos (12U) +#define CAN_F5FB2_FFDB12_Msk (0x1U << CAN_F5FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB2_FFDB12 CAN_F5FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB2_FFDB13_Pos (13U) +#define CAN_F5FB2_FFDB13_Msk (0x1U << CAN_F5FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB2_FFDB13 CAN_F5FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB2_FFDB14_Pos (14U) +#define CAN_F5FB2_FFDB14_Msk (0x1U << CAN_F5FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB2_FFDB14 CAN_F5FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB2_FFDB15_Pos (15U) +#define CAN_F5FB2_FFDB15_Msk (0x1U << CAN_F5FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB2_FFDB15 CAN_F5FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB2_FFDB16_Pos (16U) +#define CAN_F5FB2_FFDB16_Msk (0x1U << CAN_F5FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB2_FFDB16 CAN_F5FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB2_FFDB17_Pos (17U) +#define CAN_F5FB2_FFDB17_Msk (0x1U << CAN_F5FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB2_FFDB17 CAN_F5FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB2_FFDB18_Pos (18U) +#define CAN_F5FB2_FFDB18_Msk (0x1U << CAN_F5FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB2_FFDB18 CAN_F5FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB2_FFDB19_Pos (19U) +#define CAN_F5FB2_FFDB19_Msk (0x1U << CAN_F5FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB2_FFDB19 CAN_F5FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB2_FFDB20_Pos (20U) +#define CAN_F5FB2_FFDB20_Msk (0x1U << CAN_F5FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB2_FFDB20 CAN_F5FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB2_FFDB21_Pos (21U) +#define CAN_F5FB2_FFDB21_Msk (0x1U << CAN_F5FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB2_FFDB21 CAN_F5FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB2_FFDB22_Pos (22U) +#define CAN_F5FB2_FFDB22_Msk (0x1U << CAN_F5FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB2_FFDB22 CAN_F5FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB2_FFDB23_Pos (23U) +#define CAN_F5FB2_FFDB23_Msk (0x1U << CAN_F5FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB2_FFDB23 CAN_F5FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB2_FFDB24_Pos (24U) +#define CAN_F5FB2_FFDB24_Msk (0x1U << CAN_F5FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB2_FFDB24 CAN_F5FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB2_FFDB25_Pos (25U) +#define CAN_F5FB2_FFDB25_Msk (0x1U << CAN_F5FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB2_FFDB25 CAN_F5FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB2_FFDB26_Pos (26U) +#define CAN_F5FB2_FFDB26_Msk (0x1U << CAN_F5FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB2_FFDB26 CAN_F5FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB2_FFDB27_Pos (27U) +#define CAN_F5FB2_FFDB27_Msk (0x1U << CAN_F5FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB2_FFDB27 CAN_F5FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB2_FFDB28_Pos (28U) +#define CAN_F5FB2_FFDB28_Msk (0x1U << CAN_F5FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB2_FFDB28 CAN_F5FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB2_FFDB29_Pos (29U) +#define CAN_F5FB2_FFDB29_Msk (0x1U << CAN_F5FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB2_FFDB29 CAN_F5FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB2_FFDB30_Pos (30U) +#define CAN_F5FB2_FFDB30_Msk (0x1U << CAN_F5FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB2_FFDB30 CAN_F5FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB2_FFDB31_Pos (31U) +#define CAN_F5FB2_FFDB31_Msk (0x1U << CAN_F5FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB2_FFDB31 CAN_F5FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB2 register *******************/ +#define CAN_F6FB2_FFDB0_Pos (0U) +#define CAN_F6FB2_FFDB0_Msk (0x1U << CAN_F6FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB2_FFDB0 CAN_F6FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB2_FFDB1_Pos (1U) +#define CAN_F6FB2_FFDB1_Msk (0x1U << CAN_F6FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB2_FFDB1 CAN_F6FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB2_FFDB2_Pos (2U) +#define CAN_F6FB2_FFDB2_Msk (0x1U << CAN_F6FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB2_FFDB2 CAN_F6FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB2_FFDB3_Pos (3U) +#define CAN_F6FB2_FFDB3_Msk (0x1U << CAN_F6FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB2_FFDB3 CAN_F6FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB2_FFDB4_Pos (4U) +#define CAN_F6FB2_FFDB4_Msk (0x1U << CAN_F6FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB2_FFDB4 CAN_F6FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB2_FFDB5_Pos (5U) +#define CAN_F6FB2_FFDB5_Msk (0x1U << CAN_F6FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB2_FFDB5 CAN_F6FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB2_FFDB6_Pos (6U) +#define CAN_F6FB2_FFDB6_Msk (0x1U << CAN_F6FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB2_FFDB6 CAN_F6FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB2_FFDB7_Pos (7U) +#define CAN_F6FB2_FFDB7_Msk (0x1U << CAN_F6FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB2_FFDB7 CAN_F6FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB2_FFDB8_Pos (8U) +#define CAN_F6FB2_FFDB8_Msk (0x1U << CAN_F6FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB2_FFDB8 CAN_F6FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB2_FFDB9_Pos (9U) +#define CAN_F6FB2_FFDB9_Msk (0x1U << CAN_F6FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB2_FFDB9 CAN_F6FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB2_FFDB10_Pos (10U) +#define CAN_F6FB2_FFDB10_Msk (0x1U << CAN_F6FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB2_FFDB10 CAN_F6FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB2_FFDB11_Pos (11U) +#define CAN_F6FB2_FFDB11_Msk (0x1U << CAN_F6FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB2_FFDB11 CAN_F6FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB2_FFDB12_Pos (12U) +#define CAN_F6FB2_FFDB12_Msk (0x1U << CAN_F6FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB2_FFDB12 CAN_F6FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB2_FFDB13_Pos (13U) +#define CAN_F6FB2_FFDB13_Msk (0x1U << CAN_F6FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB2_FFDB13 CAN_F6FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB2_FFDB14_Pos (14U) +#define CAN_F6FB2_FFDB14_Msk (0x1U << CAN_F6FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB2_FFDB14 CAN_F6FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB2_FFDB15_Pos (15U) +#define CAN_F6FB2_FFDB15_Msk (0x1U << CAN_F6FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB2_FFDB15 CAN_F6FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB2_FFDB16_Pos (16U) +#define CAN_F6FB2_FFDB16_Msk (0x1U << CAN_F6FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB2_FFDB16 CAN_F6FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB2_FFDB17_Pos (17U) +#define CAN_F6FB2_FFDB17_Msk (0x1U << CAN_F6FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB2_FFDB17 CAN_F6FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB2_FFDB18_Pos (18U) +#define CAN_F6FB2_FFDB18_Msk (0x1U << CAN_F6FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB2_FFDB18 CAN_F6FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB2_FFDB19_Pos (19U) +#define CAN_F6FB2_FFDB19_Msk (0x1U << CAN_F6FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB2_FFDB19 CAN_F6FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB2_FFDB20_Pos (20U) +#define CAN_F6FB2_FFDB20_Msk (0x1U << CAN_F6FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB2_FFDB20 CAN_F6FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB2_FFDB21_Pos (21U) +#define CAN_F6FB2_FFDB21_Msk (0x1U << CAN_F6FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB2_FFDB21 CAN_F6FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB2_FFDB22_Pos (22U) +#define CAN_F6FB2_FFDB22_Msk (0x1U << CAN_F6FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB2_FFDB22 CAN_F6FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB2_FFDB23_Pos (23U) +#define CAN_F6FB2_FFDB23_Msk (0x1U << CAN_F6FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB2_FFDB23 CAN_F6FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB2_FFDB24_Pos (24U) +#define CAN_F6FB2_FFDB24_Msk (0x1U << CAN_F6FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB2_FFDB24 CAN_F6FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB2_FFDB25_Pos (25U) +#define CAN_F6FB2_FFDB25_Msk (0x1U << CAN_F6FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB2_FFDB25 CAN_F6FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB2_FFDB26_Pos (26U) +#define CAN_F6FB2_FFDB26_Msk (0x1U << CAN_F6FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB2_FFDB26 CAN_F6FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB2_FFDB27_Pos (27U) +#define CAN_F6FB2_FFDB27_Msk (0x1U << CAN_F6FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB2_FFDB27 CAN_F6FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB2_FFDB28_Pos (28U) +#define CAN_F6FB2_FFDB28_Msk (0x1U << CAN_F6FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB2_FFDB28 CAN_F6FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB2_FFDB29_Pos (29U) +#define CAN_F6FB2_FFDB29_Msk (0x1U << CAN_F6FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB2_FFDB29 CAN_F6FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB2_FFDB30_Pos (30U) +#define CAN_F6FB2_FFDB30_Msk (0x1U << CAN_F6FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB2_FFDB30 CAN_F6FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB2_FFDB31_Pos (31U) +#define CAN_F6FB2_FFDB31_Msk (0x1U << CAN_F6FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB2_FFDB31 CAN_F6FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB2 register *******************/ +#define CAN_F7FB2_FFDB0_Pos (0U) +#define CAN_F7FB2_FFDB0_Msk (0x1U << CAN_F7FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB2_FFDB0 CAN_F7FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB2_FFDB1_Pos (1U) +#define CAN_F7FB2_FFDB1_Msk (0x1U << CAN_F7FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB2_FFDB1 CAN_F7FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB2_FFDB2_Pos (2U) +#define CAN_F7FB2_FFDB2_Msk (0x1U << CAN_F7FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB2_FFDB2 CAN_F7FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB2_FFDB3_Pos (3U) +#define CAN_F7FB2_FFDB3_Msk (0x1U << CAN_F7FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB2_FFDB3 CAN_F7FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB2_FFDB4_Pos (4U) +#define CAN_F7FB2_FFDB4_Msk (0x1U << CAN_F7FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB2_FFDB4 CAN_F7FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB2_FFDB5_Pos (5U) +#define CAN_F7FB2_FFDB5_Msk (0x1U << CAN_F7FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB2_FFDB5 CAN_F7FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB2_FFDB6_Pos (6U) +#define CAN_F7FB2_FFDB6_Msk (0x1U << CAN_F7FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB2_FFDB6 CAN_F7FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB2_FFDB7_Pos (7U) +#define CAN_F7FB2_FFDB7_Msk (0x1U << CAN_F7FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB2_FFDB7 CAN_F7FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB2_FFDB8_Pos (8U) +#define CAN_F7FB2_FFDB8_Msk (0x1U << CAN_F7FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB2_FFDB8 CAN_F7FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB2_FFDB9_Pos (9U) +#define CAN_F7FB2_FFDB9_Msk (0x1U << CAN_F7FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB2_FFDB9 CAN_F7FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB2_FFDB10_Pos (10U) +#define CAN_F7FB2_FFDB10_Msk (0x1U << CAN_F7FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB2_FFDB10 CAN_F7FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB2_FFDB11_Pos (11U) +#define CAN_F7FB2_FFDB11_Msk (0x1U << CAN_F7FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB2_FFDB11 CAN_F7FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB2_FFDB12_Pos (12U) +#define CAN_F7FB2_FFDB12_Msk (0x1U << CAN_F7FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB2_FFDB12 CAN_F7FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB2_FFDB13_Pos (13U) +#define CAN_F7FB2_FFDB13_Msk (0x1U << CAN_F7FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB2_FFDB13 CAN_F7FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB2_FFDB14_Pos (14U) +#define CAN_F7FB2_FFDB14_Msk (0x1U << CAN_F7FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB2_FFDB14 CAN_F7FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB2_FFDB15_Pos (15U) +#define CAN_F7FB2_FFDB15_Msk (0x1U << CAN_F7FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB2_FFDB15 CAN_F7FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB2_FFDB16_Pos (16U) +#define CAN_F7FB2_FFDB16_Msk (0x1U << CAN_F7FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB2_FFDB16 CAN_F7FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB2_FFDB17_Pos (17U) +#define CAN_F7FB2_FFDB17_Msk (0x1U << CAN_F7FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB2_FFDB17 CAN_F7FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB2_FFDB18_Pos (18U) +#define CAN_F7FB2_FFDB18_Msk (0x1U << CAN_F7FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB2_FFDB18 CAN_F7FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB2_FFDB19_Pos (19U) +#define CAN_F7FB2_FFDB19_Msk (0x1U << CAN_F7FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB2_FFDB19 CAN_F7FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB2_FFDB20_Pos (20U) +#define CAN_F7FB2_FFDB20_Msk (0x1U << CAN_F7FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB2_FFDB20 CAN_F7FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB2_FFDB21_Pos (21U) +#define CAN_F7FB2_FFDB21_Msk (0x1U << CAN_F7FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB2_FFDB21 CAN_F7FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB2_FFDB22_Pos (22U) +#define CAN_F7FB2_FFDB22_Msk (0x1U << CAN_F7FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB2_FFDB22 CAN_F7FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB2_FFDB23_Pos (23U) +#define CAN_F7FB2_FFDB23_Msk (0x1U << CAN_F7FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB2_FFDB23 CAN_F7FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB2_FFDB24_Pos (24U) +#define CAN_F7FB2_FFDB24_Msk (0x1U << CAN_F7FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB2_FFDB24 CAN_F7FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB2_FFDB25_Pos (25U) +#define CAN_F7FB2_FFDB25_Msk (0x1U << CAN_F7FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB2_FFDB25 CAN_F7FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB2_FFDB26_Pos (26U) +#define CAN_F7FB2_FFDB26_Msk (0x1U << CAN_F7FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB2_FFDB26 CAN_F7FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB2_FFDB27_Pos (27U) +#define CAN_F7FB2_FFDB27_Msk (0x1U << CAN_F7FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB2_FFDB27 CAN_F7FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB2_FFDB28_Pos (28U) +#define CAN_F7FB2_FFDB28_Msk (0x1U << CAN_F7FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB2_FFDB28 CAN_F7FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB2_FFDB29_Pos (29U) +#define CAN_F7FB2_FFDB29_Msk (0x1U << CAN_F7FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB2_FFDB29 CAN_F7FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB2_FFDB30_Pos (30U) +#define CAN_F7FB2_FFDB30_Msk (0x1U << CAN_F7FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB2_FFDB30 CAN_F7FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB2_FFDB31_Pos (31U) +#define CAN_F7FB2_FFDB31_Msk (0x1U << CAN_F7FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB2_FFDB31 CAN_F7FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB2 register *******************/ +#define CAN_F8FB2_FFDB0_Pos (0U) +#define CAN_F8FB2_FFDB0_Msk (0x1U << CAN_F8FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB2_FFDB0 CAN_F8FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB2_FFDB1_Pos (1U) +#define CAN_F8FB2_FFDB1_Msk (0x1U << CAN_F8FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB2_FFDB1 CAN_F8FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB2_FFDB2_Pos (2U) +#define CAN_F8FB2_FFDB2_Msk (0x1U << CAN_F8FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB2_FFDB2 CAN_F8FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB2_FFDB3_Pos (3U) +#define CAN_F8FB2_FFDB3_Msk (0x1U << CAN_F8FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB2_FFDB3 CAN_F8FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB2_FFDB4_Pos (4U) +#define CAN_F8FB2_FFDB4_Msk (0x1U << CAN_F8FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB2_FFDB4 CAN_F8FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB2_FFDB5_Pos (5U) +#define CAN_F8FB2_FFDB5_Msk (0x1U << CAN_F8FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB2_FFDB5 CAN_F8FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB2_FFDB6_Pos (6U) +#define CAN_F8FB2_FFDB6_Msk (0x1U << CAN_F8FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB2_FFDB6 CAN_F8FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB2_FFDB7_Pos (7U) +#define CAN_F8FB2_FFDB7_Msk (0x1U << CAN_F8FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB2_FFDB7 CAN_F8FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB2_FFDB8_Pos (8U) +#define CAN_F8FB2_FFDB8_Msk (0x1U << CAN_F8FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB2_FFDB8 CAN_F8FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB2_FFDB9_Pos (9U) +#define CAN_F8FB2_FFDB9_Msk (0x1U << CAN_F8FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB2_FFDB9 CAN_F8FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB2_FFDB10_Pos (10U) +#define CAN_F8FB2_FFDB10_Msk (0x1U << CAN_F8FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB2_FFDB10 CAN_F8FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB2_FFDB11_Pos (11U) +#define CAN_F8FB2_FFDB11_Msk (0x1U << CAN_F8FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB2_FFDB11 CAN_F8FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB2_FFDB12_Pos (12U) +#define CAN_F8FB2_FFDB12_Msk (0x1U << CAN_F8FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB2_FFDB12 CAN_F8FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB2_FFDB13_Pos (13U) +#define CAN_F8FB2_FFDB13_Msk (0x1U << CAN_F8FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB2_FFDB13 CAN_F8FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB2_FFDB14_Pos (14U) +#define CAN_F8FB2_FFDB14_Msk (0x1U << CAN_F8FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB2_FFDB14 CAN_F8FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB2_FFDB15_Pos (15U) +#define CAN_F8FB2_FFDB15_Msk (0x1U << CAN_F8FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB2_FFDB15 CAN_F8FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB2_FFDB16_Pos (16U) +#define CAN_F8FB2_FFDB16_Msk (0x1U << CAN_F8FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB2_FFDB16 CAN_F8FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB2_FFDB17_Pos (17U) +#define CAN_F8FB2_FFDB17_Msk (0x1U << CAN_F8FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB2_FFDB17 CAN_F8FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB2_FFDB18_Pos (18U) +#define CAN_F8FB2_FFDB18_Msk (0x1U << CAN_F8FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB2_FFDB18 CAN_F8FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB2_FFDB19_Pos (19U) +#define CAN_F8FB2_FFDB19_Msk (0x1U << CAN_F8FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB2_FFDB19 CAN_F8FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB2_FFDB20_Pos (20U) +#define CAN_F8FB2_FFDB20_Msk (0x1U << CAN_F8FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB2_FFDB20 CAN_F8FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB2_FFDB21_Pos (21U) +#define CAN_F8FB2_FFDB21_Msk (0x1U << CAN_F8FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB2_FFDB21 CAN_F8FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB2_FFDB22_Pos (22U) +#define CAN_F8FB2_FFDB22_Msk (0x1U << CAN_F8FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB2_FFDB22 CAN_F8FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB2_FFDB23_Pos (23U) +#define CAN_F8FB2_FFDB23_Msk (0x1U << CAN_F8FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB2_FFDB23 CAN_F8FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB2_FFDB24_Pos (24U) +#define CAN_F8FB2_FFDB24_Msk (0x1U << CAN_F8FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB2_FFDB24 CAN_F8FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB2_FFDB25_Pos (25U) +#define CAN_F8FB2_FFDB25_Msk (0x1U << CAN_F8FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB2_FFDB25 CAN_F8FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB2_FFDB26_Pos (26U) +#define CAN_F8FB2_FFDB26_Msk (0x1U << CAN_F8FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB2_FFDB26 CAN_F8FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB2_FFDB27_Pos (27U) +#define CAN_F8FB2_FFDB27_Msk (0x1U << CAN_F8FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB2_FFDB27 CAN_F8FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB2_FFDB28_Pos (28U) +#define CAN_F8FB2_FFDB28_Msk (0x1U << CAN_F8FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB2_FFDB28 CAN_F8FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB2_FFDB29_Pos (29U) +#define CAN_F8FB2_FFDB29_Msk (0x1U << CAN_F8FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB2_FFDB29 CAN_F8FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB2_FFDB30_Pos (30U) +#define CAN_F8FB2_FFDB30_Msk (0x1U << CAN_F8FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB2_FFDB30 CAN_F8FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB2_FFDB31_Pos (31U) +#define CAN_F8FB2_FFDB31_Msk (0x1U << CAN_F8FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB2_FFDB31 CAN_F8FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB2 register *******************/ +#define CAN_F9FB2_FFDB0_Pos (0U) +#define CAN_F9FB2_FFDB0_Msk (0x1U << CAN_F9FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB2_FFDB0 CAN_F9FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB2_FFDB1_Pos (1U) +#define CAN_F9FB2_FFDB1_Msk (0x1U << CAN_F9FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB2_FFDB1 CAN_F9FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB2_FFDB2_Pos (2U) +#define CAN_F9FB2_FFDB2_Msk (0x1U << CAN_F9FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB2_FFDB2 CAN_F9FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB2_FFDB3_Pos (3U) +#define CAN_F9FB2_FFDB3_Msk (0x1U << CAN_F9FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB2_FFDB3 CAN_F9FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB2_FFDB4_Pos (4U) +#define CAN_F9FB2_FFDB4_Msk (0x1U << CAN_F9FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB2_FFDB4 CAN_F9FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB2_FFDB5_Pos (5U) +#define CAN_F9FB2_FFDB5_Msk (0x1U << CAN_F9FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB2_FFDB5 CAN_F9FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB2_FFDB6_Pos (6U) +#define CAN_F9FB2_FFDB6_Msk (0x1U << CAN_F9FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB2_FFDB6 CAN_F9FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB2_FFDB7_Pos (7U) +#define CAN_F9FB2_FFDB7_Msk (0x1U << CAN_F9FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB2_FFDB7 CAN_F9FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB2_FFDB8_Pos (8U) +#define CAN_F9FB2_FFDB8_Msk (0x1U << CAN_F9FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB2_FFDB8 CAN_F9FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB2_FFDB9_Pos (9U) +#define CAN_F9FB2_FFDB9_Msk (0x1U << CAN_F9FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB2_FFDB9 CAN_F9FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB2_FFDB10_Pos (10U) +#define CAN_F9FB2_FFDB10_Msk (0x1U << CAN_F9FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB2_FFDB10 CAN_F9FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB2_FFDB11_Pos (11U) +#define CAN_F9FB2_FFDB11_Msk (0x1U << CAN_F9FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB2_FFDB11 CAN_F9FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB2_FFDB12_Pos (12U) +#define CAN_F9FB2_FFDB12_Msk (0x1U << CAN_F9FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB2_FFDB12 CAN_F9FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB2_FFDB13_Pos (13U) +#define CAN_F9FB2_FFDB13_Msk (0x1U << CAN_F9FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB2_FFDB13 CAN_F9FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB2_FFDB14_Pos (14U) +#define CAN_F9FB2_FFDB14_Msk (0x1U << CAN_F9FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB2_FFDB14 CAN_F9FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB2_FFDB15_Pos (15U) +#define CAN_F9FB2_FFDB15_Msk (0x1U << CAN_F9FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB2_FFDB15 CAN_F9FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB2_FFDB16_Pos (16U) +#define CAN_F9FB2_FFDB16_Msk (0x1U << CAN_F9FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB2_FFDB16 CAN_F9FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB2_FFDB17_Pos (17U) +#define CAN_F9FB2_FFDB17_Msk (0x1U << CAN_F9FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB2_FFDB17 CAN_F9FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB2_FFDB18_Pos (18U) +#define CAN_F9FB2_FFDB18_Msk (0x1U << CAN_F9FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB2_FFDB18 CAN_F9FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB2_FFDB19_Pos (19U) +#define CAN_F9FB2_FFDB19_Msk (0x1U << CAN_F9FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB2_FFDB19 CAN_F9FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB2_FFDB20_Pos (20U) +#define CAN_F9FB2_FFDB20_Msk (0x1U << CAN_F9FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB2_FFDB20 CAN_F9FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB2_FFDB21_Pos (21U) +#define CAN_F9FB2_FFDB21_Msk (0x1U << CAN_F9FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB2_FFDB21 CAN_F9FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB2_FFDB22_Pos (22U) +#define CAN_F9FB2_FFDB22_Msk (0x1U << CAN_F9FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB2_FFDB22 CAN_F9FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB2_FFDB23_Pos (23U) +#define CAN_F9FB2_FFDB23_Msk (0x1U << CAN_F9FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB2_FFDB23 CAN_F9FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB2_FFDB24_Pos (24U) +#define CAN_F9FB2_FFDB24_Msk (0x1U << CAN_F9FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB2_FFDB24 CAN_F9FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB2_FFDB25_Pos (25U) +#define CAN_F9FB2_FFDB25_Msk (0x1U << CAN_F9FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB2_FFDB25 CAN_F9FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB2_FFDB26_Pos (26U) +#define CAN_F9FB2_FFDB26_Msk (0x1U << CAN_F9FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB2_FFDB26 CAN_F9FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB2_FFDB27_Pos (27U) +#define CAN_F9FB2_FFDB27_Msk (0x1U << CAN_F9FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB2_FFDB27 CAN_F9FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB2_FFDB28_Pos (28U) +#define CAN_F9FB2_FFDB28_Msk (0x1U << CAN_F9FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB2_FFDB28 CAN_F9FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB2_FFDB29_Pos (29U) +#define CAN_F9FB2_FFDB29_Msk (0x1U << CAN_F9FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB2_FFDB29 CAN_F9FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB2_FFDB30_Pos (30U) +#define CAN_F9FB2_FFDB30_Msk (0x1U << CAN_F9FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB2_FFDB30 CAN_F9FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB2_FFDB31_Pos (31U) +#define CAN_F9FB2_FFDB31_Msk (0x1U << CAN_F9FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB2_FFDB31 CAN_F9FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB2 register ******************/ +#define CAN_F10FB2_FFDB0_Pos (0U) +#define CAN_F10FB2_FFDB0_Msk (0x1U << CAN_F10FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB2_FFDB0 CAN_F10FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB2_FFDB1_Pos (1U) +#define CAN_F10FB2_FFDB1_Msk (0x1U << CAN_F10FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB2_FFDB1 CAN_F10FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB2_FFDB2_Pos (2U) +#define CAN_F10FB2_FFDB2_Msk (0x1U << CAN_F10FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB2_FFDB2 CAN_F10FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB2_FFDB3_Pos (3U) +#define CAN_F10FB2_FFDB3_Msk (0x1U << CAN_F10FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB2_FFDB3 CAN_F10FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB2_FFDB4_Pos (4U) +#define CAN_F10FB2_FFDB4_Msk (0x1U << CAN_F10FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB2_FFDB4 CAN_F10FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB2_FFDB5_Pos (5U) +#define CAN_F10FB2_FFDB5_Msk (0x1U << CAN_F10FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB2_FFDB5 CAN_F10FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB2_FFDB6_Pos (6U) +#define CAN_F10FB2_FFDB6_Msk (0x1U << CAN_F10FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB2_FFDB6 CAN_F10FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB2_FFDB7_Pos (7U) +#define CAN_F10FB2_FFDB7_Msk (0x1U << CAN_F10FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB2_FFDB7 CAN_F10FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB2_FFDB8_Pos (8U) +#define CAN_F10FB2_FFDB8_Msk (0x1U << CAN_F10FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB2_FFDB8 CAN_F10FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB2_FFDB9_Pos (9U) +#define CAN_F10FB2_FFDB9_Msk (0x1U << CAN_F10FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB2_FFDB9 CAN_F10FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB2_FFDB10_Pos (10U) +#define CAN_F10FB2_FFDB10_Msk (0x1U << CAN_F10FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB2_FFDB10 CAN_F10FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB2_FFDB11_Pos (11U) +#define CAN_F10FB2_FFDB11_Msk (0x1U << CAN_F10FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB2_FFDB11 CAN_F10FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB2_FFDB12_Pos (12U) +#define CAN_F10FB2_FFDB12_Msk (0x1U << CAN_F10FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB2_FFDB12 CAN_F10FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB2_FFDB13_Pos (13U) +#define CAN_F10FB2_FFDB13_Msk (0x1U << CAN_F10FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB2_FFDB13 CAN_F10FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB2_FFDB14_Pos (14U) +#define CAN_F10FB2_FFDB14_Msk (0x1U << CAN_F10FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB2_FFDB14 CAN_F10FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB2_FFDB15_Pos (15U) +#define CAN_F10FB2_FFDB15_Msk (0x1U << CAN_F10FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB2_FFDB15 CAN_F10FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB2_FFDB16_Pos (16U) +#define CAN_F10FB2_FFDB16_Msk (0x1U << CAN_F10FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB2_FFDB16 CAN_F10FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB2_FFDB17_Pos (17U) +#define CAN_F10FB2_FFDB17_Msk (0x1U << CAN_F10FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB2_FFDB17 CAN_F10FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB2_FFDB18_Pos (18U) +#define CAN_F10FB2_FFDB18_Msk (0x1U << CAN_F10FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB2_FFDB18 CAN_F10FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB2_FFDB19_Pos (19U) +#define CAN_F10FB2_FFDB19_Msk (0x1U << CAN_F10FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB2_FFDB19 CAN_F10FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB2_FFDB20_Pos (20U) +#define CAN_F10FB2_FFDB20_Msk (0x1U << CAN_F10FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB2_FFDB20 CAN_F10FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB2_FFDB21_Pos (21U) +#define CAN_F10FB2_FFDB21_Msk (0x1U << CAN_F10FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB2_FFDB21 CAN_F10FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB2_FFDB22_Pos (22U) +#define CAN_F10FB2_FFDB22_Msk (0x1U << CAN_F10FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB2_FFDB22 CAN_F10FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB2_FFDB23_Pos (23U) +#define CAN_F10FB2_FFDB23_Msk (0x1U << CAN_F10FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB2_FFDB23 CAN_F10FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB2_FFDB24_Pos (24U) +#define CAN_F10FB2_FFDB24_Msk (0x1U << CAN_F10FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB2_FFDB24 CAN_F10FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB2_FFDB25_Pos (25U) +#define CAN_F10FB2_FFDB25_Msk (0x1U << CAN_F10FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB2_FFDB25 CAN_F10FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB2_FFDB26_Pos (26U) +#define CAN_F10FB2_FFDB26_Msk (0x1U << CAN_F10FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB2_FFDB26 CAN_F10FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB2_FFDB27_Pos (27U) +#define CAN_F10FB2_FFDB27_Msk (0x1U << CAN_F10FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB2_FFDB27 CAN_F10FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB2_FFDB28_Pos (28U) +#define CAN_F10FB2_FFDB28_Msk (0x1U << CAN_F10FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB2_FFDB28 CAN_F10FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB2_FFDB29_Pos (29U) +#define CAN_F10FB2_FFDB29_Msk (0x1U << CAN_F10FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB2_FFDB29 CAN_F10FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB2_FFDB30_Pos (30U) +#define CAN_F10FB2_FFDB30_Msk (0x1U << CAN_F10FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB2_FFDB30 CAN_F10FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB2_FFDB31_Pos (31U) +#define CAN_F10FB2_FFDB31_Msk (0x1U << CAN_F10FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB2_FFDB31 CAN_F10FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB2 register ******************/ +#define CAN_F11FB2_FFDB0_Pos (0U) +#define CAN_F11FB2_FFDB0_Msk (0x1U << CAN_F11FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB2_FFDB0 CAN_F11FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB2_FFDB1_Pos (1U) +#define CAN_F11FB2_FFDB1_Msk (0x1U << CAN_F11FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB2_FFDB1 CAN_F11FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB2_FFDB2_Pos (2U) +#define CAN_F11FB2_FFDB2_Msk (0x1U << CAN_F11FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB2_FFDB2 CAN_F11FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB2_FFDB3_Pos (3U) +#define CAN_F11FB2_FFDB3_Msk (0x1U << CAN_F11FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB2_FFDB3 CAN_F11FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB2_FFDB4_Pos (4U) +#define CAN_F11FB2_FFDB4_Msk (0x1U << CAN_F11FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB2_FFDB4 CAN_F11FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB2_FFDB5_Pos (5U) +#define CAN_F11FB2_FFDB5_Msk (0x1U << CAN_F11FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB2_FFDB5 CAN_F11FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB2_FFDB6_Pos (6U) +#define CAN_F11FB2_FFDB6_Msk (0x1U << CAN_F11FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB2_FFDB6 CAN_F11FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB2_FFDB7_Pos (7U) +#define CAN_F11FB2_FFDB7_Msk (0x1U << CAN_F11FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB2_FFDB7 CAN_F11FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB2_FFDB8_Pos (8U) +#define CAN_F11FB2_FFDB8_Msk (0x1U << CAN_F11FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB2_FFDB8 CAN_F11FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB2_FFDB9_Pos (9U) +#define CAN_F11FB2_FFDB9_Msk (0x1U << CAN_F11FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB2_FFDB9 CAN_F11FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB2_FFDB10_Pos (10U) +#define CAN_F11FB2_FFDB10_Msk (0x1U << CAN_F11FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB2_FFDB10 CAN_F11FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB2_FFDB11_Pos (11U) +#define CAN_F11FB2_FFDB11_Msk (0x1U << CAN_F11FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB2_FFDB11 CAN_F11FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB2_FFDB12_Pos (12U) +#define CAN_F11FB2_FFDB12_Msk (0x1U << CAN_F11FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB2_FFDB12 CAN_F11FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB2_FFDB13_Pos (13U) +#define CAN_F11FB2_FFDB13_Msk (0x1U << CAN_F11FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB2_FFDB13 CAN_F11FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB2_FFDB14_Pos (14U) +#define CAN_F11FB2_FFDB14_Msk (0x1U << CAN_F11FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB2_FFDB14 CAN_F11FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB2_FFDB15_Pos (15U) +#define CAN_F11FB2_FFDB15_Msk (0x1U << CAN_F11FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB2_FFDB15 CAN_F11FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB2_FFDB16_Pos (16U) +#define CAN_F11FB2_FFDB16_Msk (0x1U << CAN_F11FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB2_FFDB16 CAN_F11FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB2_FFDB17_Pos (17U) +#define CAN_F11FB2_FFDB17_Msk (0x1U << CAN_F11FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB2_FFDB17 CAN_F11FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB2_FFDB18_Pos (18U) +#define CAN_F11FB2_FFDB18_Msk (0x1U << CAN_F11FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB2_FFDB18 CAN_F11FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB2_FFDB19_Pos (19U) +#define CAN_F11FB2_FFDB19_Msk (0x1U << CAN_F11FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB2_FFDB19 CAN_F11FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB2_FFDB20_Pos (20U) +#define CAN_F11FB2_FFDB20_Msk (0x1U << CAN_F11FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB2_FFDB20 CAN_F11FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB2_FFDB21_Pos (21U) +#define CAN_F11FB2_FFDB21_Msk (0x1U << CAN_F11FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB2_FFDB21 CAN_F11FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB2_FFDB22_Pos (22U) +#define CAN_F11FB2_FFDB22_Msk (0x1U << CAN_F11FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB2_FFDB22 CAN_F11FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB2_FFDB23_Pos (23U) +#define CAN_F11FB2_FFDB23_Msk (0x1U << CAN_F11FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB2_FFDB23 CAN_F11FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB2_FFDB24_Pos (24U) +#define CAN_F11FB2_FFDB24_Msk (0x1U << CAN_F11FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB2_FFDB24 CAN_F11FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB2_FFDB25_Pos (25U) +#define CAN_F11FB2_FFDB25_Msk (0x1U << CAN_F11FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB2_FFDB25 CAN_F11FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB2_FFDB26_Pos (26U) +#define CAN_F11FB2_FFDB26_Msk (0x1U << CAN_F11FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB2_FFDB26 CAN_F11FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB2_FFDB27_Pos (27U) +#define CAN_F11FB2_FFDB27_Msk (0x1U << CAN_F11FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB2_FFDB27 CAN_F11FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB2_FFDB28_Pos (28U) +#define CAN_F11FB2_FFDB28_Msk (0x1U << CAN_F11FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB2_FFDB28 CAN_F11FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB2_FFDB29_Pos (29U) +#define CAN_F11FB2_FFDB29_Msk (0x1U << CAN_F11FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB2_FFDB29 CAN_F11FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB2_FFDB30_Pos (30U) +#define CAN_F11FB2_FFDB30_Msk (0x1U << CAN_F11FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB2_FFDB30 CAN_F11FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB2_FFDB31_Pos (31U) +#define CAN_F11FB2_FFDB31_Msk (0x1U << CAN_F11FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB2_FFDB31 CAN_F11FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB2 register ******************/ +#define CAN_F12FB2_FFDB0_Pos (0U) +#define CAN_F12FB2_FFDB0_Msk (0x1U << CAN_F12FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB2_FFDB0 CAN_F12FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB2_FFDB1_Pos (1U) +#define CAN_F12FB2_FFDB1_Msk (0x1U << CAN_F12FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB2_FFDB1 CAN_F12FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB2_FFDB2_Pos (2U) +#define CAN_F12FB2_FFDB2_Msk (0x1U << CAN_F12FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB2_FFDB2 CAN_F12FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB2_FFDB3_Pos (3U) +#define CAN_F12FB2_FFDB3_Msk (0x1U << CAN_F12FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB2_FFDB3 CAN_F12FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB2_FFDB4_Pos (4U) +#define CAN_F12FB2_FFDB4_Msk (0x1U << CAN_F12FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB2_FFDB4 CAN_F12FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB2_FFDB5_Pos (5U) +#define CAN_F12FB2_FFDB5_Msk (0x1U << CAN_F12FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB2_FFDB5 CAN_F12FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB2_FFDB6_Pos (6U) +#define CAN_F12FB2_FFDB6_Msk (0x1U << CAN_F12FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB2_FFDB6 CAN_F12FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB2_FFDB7_Pos (7U) +#define CAN_F12FB2_FFDB7_Msk (0x1U << CAN_F12FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB2_FFDB7 CAN_F12FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB2_FFDB8_Pos (8U) +#define CAN_F12FB2_FFDB8_Msk (0x1U << CAN_F12FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB2_FFDB8 CAN_F12FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB2_FFDB9_Pos (9U) +#define CAN_F12FB2_FFDB9_Msk (0x1U << CAN_F12FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB2_FFDB9 CAN_F12FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB2_FFDB10_Pos (10U) +#define CAN_F12FB2_FFDB10_Msk (0x1U << CAN_F12FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB2_FFDB10 CAN_F12FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB2_FFDB11_Pos (11U) +#define CAN_F12FB2_FFDB11_Msk (0x1U << CAN_F12FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB2_FFDB11 CAN_F12FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB2_FFDB12_Pos (12U) +#define CAN_F12FB2_FFDB12_Msk (0x1U << CAN_F12FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB2_FFDB12 CAN_F12FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB2_FFDB13_Pos (13U) +#define CAN_F12FB2_FFDB13_Msk (0x1U << CAN_F12FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB2_FFDB13 CAN_F12FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB2_FFDB14_Pos (14U) +#define CAN_F12FB2_FFDB14_Msk (0x1U << CAN_F12FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB2_FFDB14 CAN_F12FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB2_FFDB15_Pos (15U) +#define CAN_F12FB2_FFDB15_Msk (0x1U << CAN_F12FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB2_FFDB15 CAN_F12FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB2_FFDB16_Pos (16U) +#define CAN_F12FB2_FFDB16_Msk (0x1U << CAN_F12FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB2_FFDB16 CAN_F12FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB2_FFDB17_Pos (17U) +#define CAN_F12FB2_FFDB17_Msk (0x1U << CAN_F12FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB2_FFDB17 CAN_F12FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB2_FFDB18_Pos (18U) +#define CAN_F12FB2_FFDB18_Msk (0x1U << CAN_F12FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB2_FFDB18 CAN_F12FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB2_FFDB19_Pos (19U) +#define CAN_F12FB2_FFDB19_Msk (0x1U << CAN_F12FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB2_FFDB19 CAN_F12FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB2_FFDB20_Pos (20U) +#define CAN_F12FB2_FFDB20_Msk (0x1U << CAN_F12FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB2_FFDB20 CAN_F12FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB2_FFDB21_Pos (21U) +#define CAN_F12FB2_FFDB21_Msk (0x1U << CAN_F12FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB2_FFDB21 CAN_F12FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB2_FFDB22_Pos (22U) +#define CAN_F12FB2_FFDB22_Msk (0x1U << CAN_F12FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB2_FFDB22 CAN_F12FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB2_FFDB23_Pos (23U) +#define CAN_F12FB2_FFDB23_Msk (0x1U << CAN_F12FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB2_FFDB23 CAN_F12FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB2_FFDB24_Pos (24U) +#define CAN_F12FB2_FFDB24_Msk (0x1U << CAN_F12FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB2_FFDB24 CAN_F12FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB2_FFDB25_Pos (25U) +#define CAN_F12FB2_FFDB25_Msk (0x1U << CAN_F12FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB2_FFDB25 CAN_F12FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB2_FFDB26_Pos (26U) +#define CAN_F12FB2_FFDB26_Msk (0x1U << CAN_F12FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB2_FFDB26 CAN_F12FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB2_FFDB27_Pos (27U) +#define CAN_F12FB2_FFDB27_Msk (0x1U << CAN_F12FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB2_FFDB27 CAN_F12FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB2_FFDB28_Pos (28U) +#define CAN_F12FB2_FFDB28_Msk (0x1U << CAN_F12FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB2_FFDB28 CAN_F12FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB2_FFDB29_Pos (29U) +#define CAN_F12FB2_FFDB29_Msk (0x1U << CAN_F12FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB2_FFDB29 CAN_F12FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB2_FFDB30_Pos (30U) +#define CAN_F12FB2_FFDB30_Msk (0x1U << CAN_F12FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB2_FFDB30 CAN_F12FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB2_FFDB31_Pos (31U) +#define CAN_F12FB2_FFDB31_Msk (0x1U << CAN_F12FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB2_FFDB31 CAN_F12FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB2 register ******************/ +#define CAN_F13FB2_FFDB0_Pos (0U) +#define CAN_F13FB2_FFDB0_Msk (0x1U << CAN_F13FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB2_FFDB0 CAN_F13FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB2_FFDB1_Pos (1U) +#define CAN_F13FB2_FFDB1_Msk (0x1U << CAN_F13FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB2_FFDB1 CAN_F13FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB2_FFDB2_Pos (2U) +#define CAN_F13FB2_FFDB2_Msk (0x1U << CAN_F13FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB2_FFDB2 CAN_F13FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB2_FFDB3_Pos (3U) +#define CAN_F13FB2_FFDB3_Msk (0x1U << CAN_F13FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB2_FFDB3 CAN_F13FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB2_FFDB4_Pos (4U) +#define CAN_F13FB2_FFDB4_Msk (0x1U << CAN_F13FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB2_FFDB4 CAN_F13FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB2_FFDB5_Pos (5U) +#define CAN_F13FB2_FFDB5_Msk (0x1U << CAN_F13FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB2_FFDB5 CAN_F13FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB2_FFDB6_Pos (6U) +#define CAN_F13FB2_FFDB6_Msk (0x1U << CAN_F13FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB2_FFDB6 CAN_F13FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB2_FFDB7_Pos (7U) +#define CAN_F13FB2_FFDB7_Msk (0x1U << CAN_F13FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB2_FFDB7 CAN_F13FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB2_FFDB8_Pos (8U) +#define CAN_F13FB2_FFDB8_Msk (0x1U << CAN_F13FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB2_FFDB8 CAN_F13FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB2_FFDB9_Pos (9U) +#define CAN_F13FB2_FFDB9_Msk (0x1U << CAN_F13FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB2_FFDB9 CAN_F13FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB2_FFDB10_Pos (10U) +#define CAN_F13FB2_FFDB10_Msk (0x1U << CAN_F13FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB2_FFDB10 CAN_F13FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB2_FFDB11_Pos (11U) +#define CAN_F13FB2_FFDB11_Msk (0x1U << CAN_F13FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB2_FFDB11 CAN_F13FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB2_FFDB12_Pos (12U) +#define CAN_F13FB2_FFDB12_Msk (0x1U << CAN_F13FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB2_FFDB12 CAN_F13FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB2_FFDB13_Pos (13U) +#define CAN_F13FB2_FFDB13_Msk (0x1U << CAN_F13FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB2_FFDB13 CAN_F13FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB2_FFDB14_Pos (14U) +#define CAN_F13FB2_FFDB14_Msk (0x1U << CAN_F13FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB2_FFDB14 CAN_F13FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB2_FFDB15_Pos (15U) +#define CAN_F13FB2_FFDB15_Msk (0x1U << CAN_F13FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB2_FFDB15 CAN_F13FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB2_FFDB16_Pos (16U) +#define CAN_F13FB2_FFDB16_Msk (0x1U << CAN_F13FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB2_FFDB16 CAN_F13FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB2_FFDB17_Pos (17U) +#define CAN_F13FB2_FFDB17_Msk (0x1U << CAN_F13FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB2_FFDB17 CAN_F13FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB2_FFDB18_Pos (18U) +#define CAN_F13FB2_FFDB18_Msk (0x1U << CAN_F13FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB2_FFDB18 CAN_F13FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB2_FFDB19_Pos (19U) +#define CAN_F13FB2_FFDB19_Msk (0x1U << CAN_F13FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB2_FFDB19 CAN_F13FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB2_FFDB20_Pos (20U) +#define CAN_F13FB2_FFDB20_Msk (0x1U << CAN_F13FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB2_FFDB20 CAN_F13FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB2_FFDB21_Pos (21U) +#define CAN_F13FB2_FFDB21_Msk (0x1U << CAN_F13FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB2_FFDB21 CAN_F13FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB2_FFDB22_Pos (22U) +#define CAN_F13FB2_FFDB22_Msk (0x1U << CAN_F13FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB2_FFDB22 CAN_F13FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB2_FFDB23_Pos (23U) +#define CAN_F13FB2_FFDB23_Msk (0x1U << CAN_F13FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB2_FFDB23 CAN_F13FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB2_FFDB24_Pos (24U) +#define CAN_F13FB2_FFDB24_Msk (0x1U << CAN_F13FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB2_FFDB24 CAN_F13FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB2_FFDB25_Pos (25U) +#define CAN_F13FB2_FFDB25_Msk (0x1U << CAN_F13FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB2_FFDB25 CAN_F13FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB2_FFDB26_Pos (26U) +#define CAN_F13FB2_FFDB26_Msk (0x1U << CAN_F13FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB2_FFDB26 CAN_F13FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB2_FFDB27_Pos (27U) +#define CAN_F13FB2_FFDB27_Msk (0x1U << CAN_F13FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB2_FFDB27 CAN_F13FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB2_FFDB28_Pos (28U) +#define CAN_F13FB2_FFDB28_Msk (0x1U << CAN_F13FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB2_FFDB28 CAN_F13FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB2_FFDB29_Pos (29U) +#define CAN_F13FB2_FFDB29_Msk (0x1U << CAN_F13FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB2_FFDB29 CAN_F13FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB2_FFDB30_Pos (30U) +#define CAN_F13FB2_FFDB30_Msk (0x1U << CAN_F13FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB2_FFDB30 CAN_F13FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB2_FFDB31_Pos (31U) +#define CAN_F13FB2_FFDB31_Msk (0x1U << CAN_F13FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB2_FFDB31 CAN_F13FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/******************************************************************************/ +/* */ +/* SD/SDIO MMC card host interface (SDIO) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SDIO_PWRCTRL register *****************/ +#define SDIO_PWRCTRL_PS_Pos (0U) +#define SDIO_PWRCTRL_PS_Msk (0x3U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000003 */ +#define SDIO_PWRCTRL_PS SDIO_PWRCTRL_PS_Msk /*!< PS[1:0] bits (Power switch) */ +#define SDIO_PWRCTRL_PS_0 (0x1U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000001 */ +#define SDIO_PWRCTRL_PS_1 (0x2U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for SDIO_CLKCTRL register *****************/ +#define SDIO_CLKCTRL_CLKDIV_Msk ((0xFFU << 0) | (0x3U << 15)) /*!< 0x000180FF */ +#define SDIO_CLKCTRL_CLKDIV SDIO_CLKCTRL_CLKDIV_Msk /*!< CLKDIV[9:0] bits (Clock division) */ +#define SDIO_CLKCTRL_CLKOEN_Pos (8U) +#define SDIO_CLKCTRL_CLKOEN_Msk (0x1U << SDIO_CLKCTRL_CLKOEN_Pos) /*!< 0x00000100 */ +#define SDIO_CLKCTRL_CLKOEN SDIO_CLKCTRL_CLKOEN_Msk /*!< Clock output enable */ +#define SDIO_CLKCTRL_PWRSVEN_Pos (9U) +#define SDIO_CLKCTRL_PWRSVEN_Msk (0x1U << SDIO_CLKCTRL_PWRSVEN_Pos) /*!< 0x00000200 */ +#define SDIO_CLKCTRL_PWRSVEN SDIO_CLKCTRL_PWRSVEN_Msk /*!< Power saving mode enable */ +#define SDIO_CLKCTRL_BYPSEN_Pos (10U) +#define SDIO_CLKCTRL_BYPSEN_Msk (0x1U << SDIO_CLKCTRL_BYPSEN_Pos) /*!< 0x00000400 */ +#define SDIO_CLKCTRL_BYPSEN SDIO_CLKCTRL_BYPSEN_Msk /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCTRL_BUSWS_Pos (11U) +#define SDIO_CLKCTRL_BUSWS_Msk (0x3U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001800 */ +#define SDIO_CLKCTRL_BUSWS SDIO_CLKCTRL_BUSWS_Msk /*!< BUSWS[1:0] bits (Bus width selection) */ +#define SDIO_CLKCTRL_BUSWS_0 (0x1U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00000800 */ +#define SDIO_CLKCTRL_BUSWS_1 (0x2U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001000 */ + +#define SDIO_CLKCTRL_CLKEGS_Pos (13U) +#define SDIO_CLKCTRL_CLKEGS_Msk (0x1U << SDIO_CLKCTRL_CLKEGS_Pos) /*!< 0x00002000 */ +#define SDIO_CLKCTRL_CLKEGS SDIO_CLKCTRL_CLKEGS_Msk /*!< SDIO_CK edge selection */ +#define SDIO_CLKCTRL_HFCEN_Pos (14U) +#define SDIO_CLKCTRL_HFCEN_Msk (0x1U << SDIO_CLKCTRL_HFCEN_Pos) /*!< 0x00004000 */ +#define SDIO_CLKCTRL_HFCEN SDIO_CLKCTRL_HFCEN_Msk /*!< Hardware flow control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_ARGU_Pos (0U) +#define SDIO_ARG_ARGU_Msk (0xFFFFFFFFU << SDIO_ARG_ARGU_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_ARG_ARGU SDIO_ARG_ARGU_Msk /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDIDX_Pos (0U) +#define SDIO_CMD_CMDIDX_Msk (0x3FU << SDIO_CMD_CMDIDX_Pos) /*!< 0x0000003F */ +#define SDIO_CMD_CMDIDX SDIO_CMD_CMDIDX_Msk /*!< Command index */ + +#define SDIO_CMD_RSPWT_Pos (6U) +#define SDIO_CMD_RSPWT_Msk (0x3U << SDIO_CMD_RSPWT_Pos) /*!< 0x000000C0 */ +#define SDIO_CMD_RSPWT SDIO_CMD_RSPWT_Msk /*!< RSPWT[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_RSPWT_0 (0x1U << SDIO_CMD_RSPWT_Pos) /*!< 0x00000040 */ +#define SDIO_CMD_RSPWT_1 (0x2U << SDIO_CMD_RSPWT_Pos) /*!< 0x00000080 */ + +#define SDIO_CMD_INTWT_Pos (8U) +#define SDIO_CMD_INTWT_Msk (0x1U << SDIO_CMD_INTWT_Pos) /*!< 0x00000100 */ +#define SDIO_CMD_INTWT SDIO_CMD_INTWT_Msk /*!< CCSM waits for interrupt request */ +#define SDIO_CMD_PNDWT_Pos (9U) +#define SDIO_CMD_PNDWT_Msk (0x1U << SDIO_CMD_PNDWT_Pos) /*!< 0x00000200 */ +#define SDIO_CMD_PNDWT SDIO_CMD_PNDWT_Msk /*!< CCSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CCSMEN_Pos (10U) +#define SDIO_CMD_CCSMEN_Msk (0x1U << SDIO_CMD_CCSMEN_Pos) /*!< 0x00000400 */ +#define SDIO_CMD_CCSMEN SDIO_CMD_CCSMEN_Msk /*!< Command channel state machine (CCSM) enable bit */ +#define SDIO_CMD_IOSUSP_Pos (11U) +#define SDIO_CMD_IOSUSP_Msk (0x1U << SDIO_CMD_IOSUSP_Pos) /*!< 0x00000800 */ +#define SDIO_CMD_IOSUSP SDIO_CMD_IOSUSP_Msk /*!< SD I/O suspend command */ + +/***************** Bit definition for SDIO_RSPCMD register ******************/ +#define SDIO_RSPCMD_RSPCMD_Pos (0U) +#define SDIO_RSPCMD_RSPCMD_Msk (0x3FU << SDIO_RSPCMD_RSPCMD_Pos) /*!< 0x0000003F */ +#define SDIO_RSPCMD_RSPCMD SDIO_RSPCMD_RSPCMD_Msk /*!< Response command index */ + +/****************** Bit definition for SDIO_RSP1 register *******************/ +#define SDIO_RSP1_CARDSTS1_Pos (0U) +#define SDIO_RSP1_CARDSTS1_Msk (0xFFFFFFFFU << SDIO_RSP1_CARDSTS1_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP1_CARDSTS1 SDIO_RSP1_CARDSTS1_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP2 register *******************/ +#define SDIO_RSP2_CARDSTS2_Pos (0U) +#define SDIO_RSP2_CARDSTS2_Msk (0xFFFFFFFFU << SDIO_RSP2_CARDSTS2_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP2_CARDSTS2 SDIO_RSP2_CARDSTS2_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP3 register *******************/ +#define SDIO_RSP3_CARDSTS3_Pos (0U) +#define SDIO_RSP3_CARDSTS3_Msk (0xFFFFFFFFU << SDIO_RSP3_CARDSTS3_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP3_CARDSTS3 SDIO_RSP3_CARDSTS3_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_RSP4 register *******************/ +#define SDIO_RSP4_CARDSTS4_Pos (0U) +#define SDIO_RSP4_CARDSTS4_Msk (0xFFFFFFFFU << SDIO_RSP4_CARDSTS4_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RSP4_CARDSTS4 SDIO_RSP4_CARDSTS4_Msk /*!< Card status */ + +/****************** Bit definition for SDIO_DTTMR register ******************/ +#define SDIO_DTTMR_TIMEOUT_Pos (0U) +#define SDIO_DTTMR_TIMEOUT_Msk (0xFFFFFFFFU << SDIO_DTTMR_TIMEOUT_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_DTTMR_TIMEOUT SDIO_DTTMR_TIMEOUT_Msk /*!< Data timeout period */ + +/****************** Bit definition for SDIO_DTLEN register ******************/ +#define SDIO_DTLEN_DTLEN_Pos (0U) +#define SDIO_DTLEN_DTLEN_Msk (0x1FFFFFFU << SDIO_DTLEN_DTLEN_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DTLEN_DTLEN SDIO_DTLEN_DTLEN_Msk /*!< Data length value */ + +/***************** Bit definition for SDIO_DTCTRL register ******************/ +#define SDIO_DTCTRL_TFREN_Pos (0U) +#define SDIO_DTCTRL_TFREN_Msk (0x1U << SDIO_DTCTRL_TFREN_Pos) /*!< 0x00000001 */ +#define SDIO_DTCTRL_TFREN SDIO_DTCTRL_TFREN_Msk /*!< Data transfer enabled bit */ +#define SDIO_DTCTRL_TFRDIR_Pos (1U) +#define SDIO_DTCTRL_TFRDIR_Msk (0x1U << SDIO_DTCTRL_TFRDIR_Pos) /*!< 0x00000002 */ +#define SDIO_DTCTRL_TFRDIR SDIO_DTCTRL_TFRDIR_Msk /*!< Data transfer direction selection */ +#define SDIO_DTCTRL_TFRMODE_Pos (2U) +#define SDIO_DTCTRL_TFRMODE_Msk (0x1U << SDIO_DTCTRL_TFRMODE_Pos) /*!< 0x00000004 */ +#define SDIO_DTCTRL_TFRMODE SDIO_DTCTRL_TFRMODE_Msk /*!< Data transfer mode selection */ +#define SDIO_DTCTRL_DMAEN_Pos (3U) +#define SDIO_DTCTRL_DMAEN_Msk (0x1U << SDIO_DTCTRL_DMAEN_Pos) /*!< 0x00000008 */ +#define SDIO_DTCTRL_DMAEN SDIO_DTCTRL_DMAEN_Msk /*!< DMA enable bit */ + +#define SDIO_DTCTRL_BLKSIZE_Pos (4U) +#define SDIO_DTCTRL_BLKSIZE_Msk (0xFU << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x000000F0 */ +#define SDIO_DTCTRL_BLKSIZE SDIO_DTCTRL_BLKSIZE_Msk /*!< BLKSIZE[3:0] bits (Data block size) */ +#define SDIO_DTCTRL_BLKSIZE_0 (0x1U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000010 */ +#define SDIO_DTCTRL_BLKSIZE_1 (0x2U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000020 */ +#define SDIO_DTCTRL_BLKSIZE_2 (0x4U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000040 */ +#define SDIO_DTCTRL_BLKSIZE_3 (0x8U << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x00000080 */ + +#define SDIO_DTCTRL_RDWTSTART_Pos (8U) +#define SDIO_DTCTRL_RDWTSTART_Msk (0x1U << SDIO_DTCTRL_RDWTSTART_Pos) /*!< 0x00000100 */ +#define SDIO_DTCTRL_RDWTSTART SDIO_DTCTRL_RDWTSTART_Msk /*!< Read wait start */ +#define SDIO_DTCTRL_RDWTSTOP_Pos (9U) +#define SDIO_DTCTRL_RDWTSTOP_Msk (0x1U << SDIO_DTCTRL_RDWTSTOP_Pos) /*!< 0x00000200 */ +#define SDIO_DTCTRL_RDWTSTOP SDIO_DTCTRL_RDWTSTOP_Msk /*!< Read wait stop */ +#define SDIO_DTCTRL_RDWTMODE_Pos (10U) +#define SDIO_DTCTRL_RDWTMODE_Msk (0x1U << SDIO_DTCTRL_RDWTMODE_Pos) /*!< 0x00000400 */ +#define SDIO_DTCTRL_RDWTMODE SDIO_DTCTRL_RDWTMODE_Msk /*!< Read wait mode */ +#define SDIO_DTCTRL_IOEN_Pos (11U) +#define SDIO_DTCTRL_IOEN_Msk (0x1U << SDIO_DTCTRL_IOEN_Pos) /*!< 0x00000800 */ +#define SDIO_DTCTRL_IOEN SDIO_DTCTRL_IOEN_Msk /*!< SD I/O enable functions */ + +/***************** Bit definition for SDIO_DTCNTR register ******************/ +#define SDIO_DTCNTR_CNT_Pos (0U) +#define SDIO_DTCNTR_CNT_Msk (0x1FFFFFFU << SDIO_DTCNTR_CNT_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DTCNTR_CNT SDIO_DTCNTR_CNT_Msk /*!< Data count value */ + +/******************* Bit definition for SDIO_STS register *******************/ +#define SDIO_STS_CMDFAIL_Pos (0U) +#define SDIO_STS_CMDFAIL_Msk (0x1U << SDIO_STS_CMDFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_STS_CMDFAIL SDIO_STS_CMDFAIL_Msk /*!< Command response received (CRC check failed) */ +#define SDIO_STS_DTFAIL_Pos (1U) +#define SDIO_STS_DTFAIL_Msk (0x1U << SDIO_STS_DTFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_STS_DTFAIL SDIO_STS_DTFAIL_Msk /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STS_CMDTIMEOUT_Pos (2U) +#define SDIO_STS_CMDTIMEOUT_Msk (0x1U << SDIO_STS_CMDTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_STS_CMDTIMEOUT SDIO_STS_CMDTIMEOUT_Msk /*!< Command response timeout */ +#define SDIO_STS_DTTIMEOUT_Pos (3U) +#define SDIO_STS_DTTIMEOUT_Msk (0x1U << SDIO_STS_DTTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_STS_DTTIMEOUT SDIO_STS_DTTIMEOUT_Msk /*!< Data timeout */ +#define SDIO_STS_TXERRU_Pos (4U) +#define SDIO_STS_TXERRU_Msk (0x1U << SDIO_STS_TXERRU_Pos) /*!< 0x00000010 */ +#define SDIO_STS_TXERRU SDIO_STS_TXERRU_Msk /*!< Transmit BUF underrun error */ +#define SDIO_STS_RXERRO_Pos (5U) +#define SDIO_STS_RXERRO_Msk (0x1U << SDIO_STS_RXERRO_Pos) /*!< 0x00000020 */ +#define SDIO_STS_RXERRO SDIO_STS_RXERRO_Msk /*!< Received BUF overrun error */ +#define SDIO_STS_CMDRSPCMPL_Pos (6U) +#define SDIO_STS_CMDRSPCMPL_Msk (0x1U << SDIO_STS_CMDRSPCMPL_Pos) /*!< 0x00000040 */ +#define SDIO_STS_CMDRSPCMPL SDIO_STS_CMDRSPCMPL_Msk /*!< Command response (CRC check passed) */ +#define SDIO_STS_CMDCMPL_Pos (7U) +#define SDIO_STS_CMDCMPL_Msk (0x1U << SDIO_STS_CMDCMPL_Pos) /*!< 0x00000080 */ +#define SDIO_STS_CMDCMPL SDIO_STS_CMDCMPL_Msk /*!< Command sent (no response required) */ +#define SDIO_STS_DTCMPL_Pos (8U) +#define SDIO_STS_DTCMPL_Msk (0x1U << SDIO_STS_DTCMPL_Pos) /*!< 0x00000100 */ +#define SDIO_STS_DTCMPL SDIO_STS_DTCMPL_Msk /*!< Data end (data counter, SDIO CNT, is zero) */ +#define SDIO_STS_SBITERR_Pos (9U) +#define SDIO_STS_SBITERR_Msk (0x1U << SDIO_STS_SBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_STS_SBITERR SDIO_STS_SBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STS_DTBLKCMPL_Pos (10U) +#define SDIO_STS_DTBLKCMPL_Msk (0x1U << SDIO_STS_DTBLKCMPL_Pos) /*!< 0x00000400 */ +#define SDIO_STS_DTBLKCMPL SDIO_STS_DTBLKCMPL_Msk /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STS_DOCMD_Pos (11U) +#define SDIO_STS_DOCMD_Msk (0x1U << SDIO_STS_DOCMD_Pos) /*!< 0x00000800 */ +#define SDIO_STS_DOCMD SDIO_STS_DOCMD_Msk /*!< Command transfer in progress */ +#define SDIO_STS_DOTX_Pos (12U) +#define SDIO_STS_DOTX_Msk (0x1U << SDIO_STS_DOTX_Pos) /*!< 0x00001000 */ +#define SDIO_STS_DOTX SDIO_STS_DOTX_Msk /*!< Data transmit in progress */ +#define SDIO_STS_DORX_Pos (13U) +#define SDIO_STS_DORX_Msk (0x1U << SDIO_STS_DORX_Pos) /*!< 0x00002000 */ +#define SDIO_STS_DORX SDIO_STS_DORX_Msk /*!< Data receive in progress */ +#define SDIO_STS_TXBUFH_Pos (14U) +#define SDIO_STS_TXBUFH_Msk (0x1U << SDIO_STS_TXBUFH_Pos) /*!< 0x00004000 */ +#define SDIO_STS_TXBUFH SDIO_STS_TXBUFH_Msk /*!< Transmit BUF half empty: At least 8 words can be written to the BUF */ +#define SDIO_STS_RXBUFH_Pos (15U) +#define SDIO_STS_RXBUFH_Msk (0x1U << SDIO_STS_RXBUFH_Pos) /*!< 0x00008000 */ +#define SDIO_STS_RXBUFH SDIO_STS_RXBUFH_Msk /*!< Receive BUF half full: There are at least 8 words in the BUF */ +#define SDIO_STS_TXBUFF_Pos (16U) +#define SDIO_STS_TXBUFF_Msk (0x1U << SDIO_STS_TXBUFF_Pos) /*!< 0x00010000 */ +#define SDIO_STS_TXBUFF SDIO_STS_TXBUFF_Msk /*!< Transmit BUF full */ +#define SDIO_STS_RXBUFF_Pos (17U) +#define SDIO_STS_RXBUFF_Msk (0x1U << SDIO_STS_RXBUFF_Pos) /*!< 0x00020000 */ +#define SDIO_STS_RXBUFF SDIO_STS_RXBUFF_Msk /*!< Receive BUF full */ +#define SDIO_STS_TXBUFE_Pos (18U) +#define SDIO_STS_TXBUFE_Msk (0x1U << SDIO_STS_TXBUFE_Pos) /*!< 0x00040000 */ +#define SDIO_STS_TXBUFE SDIO_STS_TXBUFE_Msk /*!< Transmit BUF empty */ +#define SDIO_STS_RXBUFE_Pos (19U) +#define SDIO_STS_RXBUFE_Msk (0x1U << SDIO_STS_RXBUFE_Pos) /*!< 0x00080000 */ +#define SDIO_STS_RXBUFE SDIO_STS_RXBUFE_Msk /*!< Receive BUF empty */ +#define SDIO_STS_TXBUF_Pos (20U) +#define SDIO_STS_TXBUF_Msk (0x1U << SDIO_STS_TXBUF_Pos) /*!< 0x00100000 */ +#define SDIO_STS_TXBUF SDIO_STS_TXBUF_Msk /*!< Data available in transmit BUF */ +#define SDIO_STS_RXBUF_Pos (21U) +#define SDIO_STS_RXBUF_Msk (0x1U << SDIO_STS_RXBUF_Pos) /*!< 0x00200000 */ +#define SDIO_STS_RXBUF SDIO_STS_RXBUF_Msk /*!< Data available in receive BUF */ +#define SDIO_STS_IOIF_Pos (22U) +#define SDIO_STS_IOIF_Msk (0x1U << SDIO_STS_IOIF_Pos) /*!< 0x00400000 */ +#define SDIO_STS_IOIF SDIO_STS_IOIF_Msk /*!< SD I/O interrupt received */ + +/***************** Bit definition for SDIO_INTCLR register ******************/ +#define SDIO_INTCLR_CMDFAIL_Pos (0U) +#define SDIO_INTCLR_CMDFAIL_Msk (0x1U << SDIO_INTCLR_CMDFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_INTCLR_CMDFAIL SDIO_INTCLR_CMDFAIL_Msk /*!< CMDFAIL flag clear bit */ +#define SDIO_INTCLR_DTFAIL_Pos (1U) +#define SDIO_INTCLR_DTFAIL_Msk (0x1U << SDIO_INTCLR_DTFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_INTCLR_DTFAIL SDIO_INTCLR_DTFAIL_Msk /*!< DTFAIL flag clear bit */ +#define SDIO_INTCLR_CMDTIMEOUT_Pos (2U) +#define SDIO_INTCLR_CMDTIMEOUT_Msk (0x1U << SDIO_INTCLR_CMDTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_INTCLR_CMDTIMEOUT SDIO_INTCLR_CMDTIMEOUT_Msk /*!< CMDTIMEOUT flag clear bit */ +#define SDIO_INTCLR_DTTIMEOUT_Pos (3U) +#define SDIO_INTCLR_DTTIMEOUT_Msk (0x1U << SDIO_INTCLR_DTTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_INTCLR_DTTIMEOUT SDIO_INTCLR_DTTIMEOUT_Msk /*!< DTTIMEOUT flag clear bit */ +#define SDIO_INTCLR_TXERRU_Pos (4U) +#define SDIO_INTCLR_TXERRU_Msk (0x1U << SDIO_INTCLR_TXERRU_Pos) /*!< 0x00000010 */ +#define SDIO_INTCLR_TXERRU SDIO_INTCLR_TXERRU_Msk /*!< TXERRU flag clear bit */ +#define SDIO_INTCLR_RXERRO_Pos (5U) +#define SDIO_INTCLR_RXERRO_Msk (0x1U << SDIO_INTCLR_RXERRO_Pos) /*!< 0x00000020 */ +#define SDIO_INTCLR_RXERRO SDIO_INTCLR_RXERRO_Msk /*!< RXERRO flag clear bit */ +#define SDIO_INTCLR_CMDRSPCMPL_Pos (6U) +#define SDIO_INTCLR_CMDRSPCMPL_Msk (0x1U << SDIO_INTCLR_CMDRSPCMPL_Pos) /*!< 0x00000040 */ +#define SDIO_INTCLR_CMDRSPCMPL SDIO_INTCLR_CMDRSPCMPL_Msk /*!< CMDRSPCMPL flag clear bit */ +#define SDIO_INTCLR_CMDCMPL_Pos (7U) +#define SDIO_INTCLR_CMDCMPL_Msk (0x1U << SDIO_INTCLR_CMDCMPL_Pos) /*!< 0x00000080 */ +#define SDIO_INTCLR_CMDCMPL SDIO_INTCLR_CMDCMPL_Msk /*!< CMDCMPL flag clear bit */ +#define SDIO_INTCLR_DTCMPL_Pos (8U) +#define SDIO_INTCLR_DTCMPL_Msk (0x1U << SDIO_INTCLR_DTCMPL_Pos) /*!< 0x00000100 */ +#define SDIO_INTCLR_DTCMPL SDIO_INTCLR_DTCMPL_Msk /*!< DTCMPL flag clear bit */ +#define SDIO_INTCLR_SBITERR_Pos (9U) +#define SDIO_INTCLR_SBITERR_Msk (0x1U << SDIO_INTCLR_SBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_INTCLR_SBITERR SDIO_INTCLR_SBITERR_Msk /*!< SBITERR flag clear bit */ +#define SDIO_INTCLR_DTBLKCMPL_Pos (10U) +#define SDIO_INTCLR_DTBLKCMPL_Msk (0x1U << SDIO_INTCLR_DTBLKCMPL_Pos) /*!< 0x00000400 */ +#define SDIO_INTCLR_DTBLKCMPL SDIO_INTCLR_DTBLKCMPL_Msk /*!< DTBLKCMPL flag clear bit */ +#define SDIO_INTCLR_IOIF_Pos (22U) +#define SDIO_INTCLR_IOIF_Msk (0x1U << SDIO_INTCLR_IOIF_Pos) /*!< 0x00400000 */ +#define SDIO_INTCLR_IOIF SDIO_INTCLR_IOIF_Msk /*!< SD I/O interface flag clear bit */ + +/****************** Bit definition for SDIO_INTEN register ******************/ +#define SDIO_INTEN_CMDFAILIEN_Pos (0U) +#define SDIO_INTEN_CMDFAILIEN_Msk (0x1U << SDIO_INTEN_CMDFAILIEN_Pos) /*!< 0x00000001 */ +#define SDIO_INTEN_CMDFAILIEN SDIO_INTEN_CMDFAILIEN_Msk /*!< Command CRC fail interrupt enable */ +#define SDIO_INTEN_DTFAILIEN_Pos (1U) +#define SDIO_INTEN_DTFAILIEN_Msk (0x1U << SDIO_INTEN_DTFAILIEN_Pos) /*!< 0x00000002 */ +#define SDIO_INTEN_DTFAILIEN SDIO_INTEN_DTFAILIEN_Msk /*!< Data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTIMEOUTIEN_Pos (2U) +#define SDIO_INTEN_CMDTIMEOUTIEN_Msk (0x1U << SDIO_INTEN_CMDTIMEOUTIEN_Pos) /*!< 0x00000004 */ +#define SDIO_INTEN_CMDTIMEOUTIEN SDIO_INTEN_CMDTIMEOUTIEN_Msk /*!< Command timeout interrupt enable */ +#define SDIO_INTEN_DTTIMEOUTIEN_Pos (3U) +#define SDIO_INTEN_DTTIMEOUTIEN_Msk (0x1U << SDIO_INTEN_DTTIMEOUTIEN_Pos) /*!< 0x00000008 */ +#define SDIO_INTEN_DTTIMEOUTIEN SDIO_INTEN_DTTIMEOUTIEN_Msk /*!< Data timeout interrupt enable */ +#define SDIO_INTEN_TXERRUIEN_Pos (4U) +#define SDIO_INTEN_TXERRUIEN_Msk (0x1U << SDIO_INTEN_TXERRUIEN_Pos) /*!< 0x00000010 */ +#define SDIO_INTEN_TXERRUIEN SDIO_INTEN_TXERRUIEN_Msk /*!< TxBUF underrun error interrupt enable */ +#define SDIO_INTEN_RXERROIEN_Pos (5U) +#define SDIO_INTEN_RXERROIEN_Msk (0x1U << SDIO_INTEN_RXERROIEN_Pos) /*!< 0x00000020 */ +#define SDIO_INTEN_RXERROIEN SDIO_INTEN_RXERROIEN_Msk /*!< RxBUF overrun error interrupt enable */ +#define SDIO_INTEN_CMDRSPCMPLIEN_Pos (6U) +#define SDIO_INTEN_CMDRSPCMPLIEN_Msk (0x1U << SDIO_INTEN_CMDRSPCMPLIEN_Pos) /*!< 0x00000040 */ +#define SDIO_INTEN_CMDRSPCMPLIEN SDIO_INTEN_CMDRSPCMPLIEN_Msk /*!< Command response received interrupt enable */ +#define SDIO_INTEN_CMDCMPLIEN_Pos (7U) +#define SDIO_INTEN_CMDCMPLIEN_Msk (0x1U << SDIO_INTEN_CMDCMPLIEN_Pos) /*!< 0x00000080 */ +#define SDIO_INTEN_CMDCMPLIEN SDIO_INTEN_CMDCMPLIEN_Msk /*!< Command sent interrupt enable */ +#define SDIO_INTEN_DTCMPLIEN_Pos (8U) +#define SDIO_INTEN_DTCMPLIEN_Msk (0x1U << SDIO_INTEN_DTCMPLIEN_Pos) /*!< 0x00000100 */ +#define SDIO_INTEN_DTCMPLIEN SDIO_INTEN_DTCMPLIEN_Msk /*!< Data end interrupt enable */ +#define SDIO_INTEN_SBITERRIEN_Pos (9U) +#define SDIO_INTEN_SBITERRIEN_Msk (0x1U << SDIO_INTEN_SBITERRIEN_Pos) /*!< 0x00000200 */ +#define SDIO_INTEN_SBITERRIEN SDIO_INTEN_SBITERRIEN_Msk /*!< Start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKCMPLIEN_Pos (10U) +#define SDIO_INTEN_DTBLKCMPLIEN_Msk (0x1U << SDIO_INTEN_DTBLKCMPLIEN_Pos) /*!< 0x00000400 */ +#define SDIO_INTEN_DTBLKCMPLIEN SDIO_INTEN_DTBLKCMPLIEN_Msk /*!< Data block end interrupt enable */ +#define SDIO_INTEN_DOCMDIEN_Pos (11U) +#define SDIO_INTEN_DOCMDIEN_Msk (0x1U << SDIO_INTEN_DOCMDIEN_Pos) /*!< 0x00000800 */ +#define SDIO_INTEN_DOCMDIEN SDIO_INTEN_DOCMDIEN_Msk /*!< Command acting interrupt enable */ +#define SDIO_INTEN_DOTXIEN_Pos (12U) +#define SDIO_INTEN_DOTXIEN_Msk (0x1U << SDIO_INTEN_DOTXIEN_Pos) /*!< 0x00001000 */ +#define SDIO_INTEN_DOTXIEN SDIO_INTEN_DOTXIEN_Msk /*!< Data transmit acting interrupt enable */ +#define SDIO_INTEN_DORXIEN_Pos (13U) +#define SDIO_INTEN_DORXIEN_Msk (0x1U << SDIO_INTEN_DORXIEN_Pos) /*!< 0x00002000 */ +#define SDIO_INTEN_DORXIEN SDIO_INTEN_DORXIEN_Msk /*!< Data receive acting interrupt enable */ +#define SDIO_INTEN_TXBUFHIEN_Pos (14U) +#define SDIO_INTEN_TXBUFHIEN_Msk (0x1U << SDIO_INTEN_TXBUFHIEN_Pos) /*!< 0x00004000 */ +#define SDIO_INTEN_TXBUFHIEN SDIO_INTEN_TXBUFHIEN_Msk /*!< TxBUF half empty interrupt enable */ +#define SDIO_INTEN_RXBUFHIEN_Pos (15U) +#define SDIO_INTEN_RXBUFHIEN_Msk (0x1U << SDIO_INTEN_RXBUFHIEN_Pos) /*!< 0x00008000 */ +#define SDIO_INTEN_RXBUFHIEN SDIO_INTEN_RXBUFHIEN_Msk /*!< RxBUF half full interrupt enable */ +#define SDIO_INTEN_TXBUFFIEN_Pos (16U) +#define SDIO_INTEN_TXBUFFIEN_Msk (0x1U << SDIO_INTEN_TXBUFFIEN_Pos) /*!< 0x00010000 */ +#define SDIO_INTEN_TXBUFFIEN SDIO_INTEN_TXBUFFIEN_Msk /*!< TxBUF full interrupt enable */ +#define SDIO_INTEN_RXBUFFIEN_Pos (17U) +#define SDIO_INTEN_RXBUFFIEN_Msk (0x1U << SDIO_INTEN_RXBUFFIEN_Pos) /*!< 0x00020000 */ +#define SDIO_INTEN_RXBUFFIEN SDIO_INTEN_RXBUFFIEN_Msk /*!< RxBUF full interrupt enable */ +#define SDIO_INTEN_TXBUFEIEN_Pos (18U) +#define SDIO_INTEN_TXBUFEIEN_Msk (0x1U << SDIO_INTEN_TXBUFEIEN_Pos) /*!< 0x00040000 */ +#define SDIO_INTEN_TXBUFEIEN SDIO_INTEN_TXBUFEIEN_Msk /*!< TxBUF empty interrupt enable */ +#define SDIO_INTEN_RXBUFEIEN_Pos (19U) +#define SDIO_INTEN_RXBUFEIEN_Msk (0x1U << SDIO_INTEN_RXBUFEIEN_Pos) /*!< 0x00080000 */ +#define SDIO_INTEN_RXBUFEIEN SDIO_INTEN_RXBUFEIEN_Msk /*!< RxBUF empty interrupt enable */ +#define SDIO_INTEN_TXBUFIEN_Pos (20U) +#define SDIO_INTEN_TXBUFIEN_Msk (0x1U << SDIO_INTEN_TXBUFIEN_Pos) /*!< 0x00100000 */ +#define SDIO_INTEN_TXBUFIEN SDIO_INTEN_TXBUFIEN_Msk /*!< Data available in TxBUF interrupt enable */ +#define SDIO_INTEN_RXBUFIEN_Pos (21U) +#define SDIO_INTEN_RXBUFIEN_Msk (0x1U << SDIO_INTEN_RXBUFIEN_Pos) /*!< 0x00200000 */ +#define SDIO_INTEN_RXBUFIEN SDIO_INTEN_RXBUFIEN_Msk /*!< Data available in RxBUF interrupt enable */ +#define SDIO_INTEN_IOIFIEN_Pos (22U) +#define SDIO_INTEN_IOIFIEN_Msk (0x1U << SDIO_INTEN_IOIFIEN_Pos) /*!< 0x00400000 */ +#define SDIO_INTEN_IOIFIEN SDIO_INTEN_IOIFIEN_Msk /*!< SD I/O mode received interrupt enable */ + +/***************** Bit definition for SDIO_BUFCNTR register ******************/ +#define SDIO_BUFCNTR_CNT_Pos (0U) +#define SDIO_BUFCNTR_CNT_Msk (0xFFFFFFU << SDIO_BUFCNTR_CNT_Pos) /*!< 0x00FFFFFF */ +#define SDIO_BUFCNTR_CNT SDIO_BUFCNTR_CNT_Msk /*!< Number of words to be written to or read from the BUF */ + +/******************* Bit definition for SDIO_BUF register *******************/ +#define SDIO_BUF_DT_Pos (0U) +#define SDIO_BUF_DT_Msk (0xFFFFFFFFU << SDIO_BUF_DT_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_BUF_DT SDIO_BUF_DT_Msk /*!< Receive and transmit BUF data */ + +/******************************************************************************/ +/* */ +/* Comparator (COMP) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for CMP_CTRLSTS1 register *****************/ +#define CMP_CTRLSTS1_CMP1EN_Pos (0U) +#define CMP_CTRLSTS1_CMP1EN_Msk (0x1U << CMP_CTRLSTS1_CMP1EN_Pos) /*!< 0x00000001 */ +#define CMP_CTRLSTS1_CMP1EN CMP_CTRLSTS1_CMP1EN_Msk /*!< Comparator 1 enable */ +#define CMP_CTRLSTS1_CMP1IS_Pos (1U) +#define CMP_CTRLSTS1_CMP1IS_Msk (0x1U << CMP_CTRLSTS1_CMP1IS_Pos) /*!< 0x00000002 */ +#define CMP_CTRLSTS1_CMP1IS CMP_CTRLSTS1_CMP1IS_Msk /*!< Comparator 1 input shift */ +#define CMP_CTRLSTS1_CMP1SSEL_Pos (2U) +#define CMP_CTRLSTS1_CMP1SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP1SSEL_Pos) /*!< 0x00000004 */ +#define CMP_CTRLSTS1_CMP1SSEL CMP_CTRLSTS1_CMP1SSEL_Msk /*!< Comparator 1 speed selection */ + +#define CMP_CTRLSTS1_CMP1INVSEL_Pos (4U) +#define CMP_CTRLSTS1_CMP1INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000070 */ +#define CMP_CTRLSTS1_CMP1INVSEL CMP_CTRLSTS1_CMP1INVSEL_Msk /*!< CMP1INVSEL[2:0] bits (Comparator 1 inverting selection) */ +#define CMP_CTRLSTS1_CMP1INVSEL_0 (0x1U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000010 */ +#define CMP_CTRLSTS1_CMP1INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000020 */ +#define CMP_CTRLSTS1_CMP1INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000040 */ + +#define CMP_CTRLSTS1_CMP1TAG_Pos (8U) +#define CMP_CTRLSTS1_CMP1TAG_Msk (0x7U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000700 */ +#define CMP_CTRLSTS1_CMP1TAG CMP_CTRLSTS1_CMP1TAG_Msk /*!< CMP1TAG[2:0] bits (Comparator 1 output target) */ +#define CMP_CTRLSTS1_CMP1TAG_0 (0x1U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000100 */ +#define CMP_CTRLSTS1_CMP1TAG_1 (0x2U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000200 */ +#define CMP_CTRLSTS1_CMP1TAG_2 (0x4U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000400 */ + +#define CMP_CTRLSTS1_CMP1P_Pos (11U) +#define CMP_CTRLSTS1_CMP1P_Msk (0x1U << CMP_CTRLSTS1_CMP1P_Pos) /*!< 0x00000800 */ +#define CMP_CTRLSTS1_CMP1P CMP_CTRLSTS1_CMP1P_Msk /*!< Comparator 1 polarity */ + +#define CMP_CTRLSTS1_CMP1HYST_Pos (12U) +#define CMP_CTRLSTS1_CMP1HYST_Msk (0x3U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00003000 */ +#define CMP_CTRLSTS1_CMP1HYST CMP_CTRLSTS1_CMP1HYST_Msk /*!< CMP1HYST[1:0] bits (Comparator 1 hysteresis) */ +#define CMP_CTRLSTS1_CMP1HYST_0 (0x1U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00001000 */ +#define CMP_CTRLSTS1_CMP1HYST_1 (0x2U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00002000 */ + +#define CMP_CTRLSTS1_CMP1VALUE_Pos (14U) +#define CMP_CTRLSTS1_CMP1VALUE_Msk (0x1U << CMP_CTRLSTS1_CMP1VALUE_Pos) /*!< 0x00004000 */ +#define CMP_CTRLSTS1_CMP1VALUE CMP_CTRLSTS1_CMP1VALUE_Msk /*!< Comparator 1 output value */ +#define CMP_CTRLSTS1_CMP1WP_Pos (15U) +#define CMP_CTRLSTS1_CMP1WP_Msk (0x1U << CMP_CTRLSTS1_CMP1WP_Pos) /*!< 0x00008000 */ +#define CMP_CTRLSTS1_CMP1WP CMP_CTRLSTS1_CMP1WP_Msk /*!< Comparator 1 write protect */ +#define CMP_CTRLSTS1_CMP2EN_Pos (16U) +#define CMP_CTRLSTS1_CMP2EN_Msk (0x1U << CMP_CTRLSTS1_CMP2EN_Pos) /*!< 0x00010000 */ +#define CMP_CTRLSTS1_CMP2EN CMP_CTRLSTS1_CMP2EN_Msk /*!< Comparator 2 enable */ +#define CMP_CTRLSTS1_CMP2SSEL_Pos (18U) +#define CMP_CTRLSTS1_CMP2SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP2SSEL_Pos) /*!< 0x00040000 */ +#define CMP_CTRLSTS1_CMP2SSEL CMP_CTRLSTS1_CMP2SSEL_Msk /*!< Comparator 2 speed selection */ + +#define CMP_CTRLSTS1_CMP2INVSEL_Pos (20U) +#define CMP_CTRLSTS1_CMP2INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00700000 */ +#define CMP_CTRLSTS1_CMP2INVSEL CMP_CTRLSTS1_CMP2INVSEL_Msk /*!< CMP2INVSEL[2:0] bits (Comparator 2 inverting selection) */ +#define CMP_CTRLSTS1_CMP2INVSEL_0 (0x1U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00100000 */ +#define CMP_CTRLSTS1_CMP2INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00200000 */ +#define CMP_CTRLSTS1_CMP2INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00400000 */ + +#define CMP_CTRLSTS1_DCMPEN_Pos (23U) +#define CMP_CTRLSTS1_DCMPEN_Msk (0x1U << CMP_CTRLSTS1_DCMPEN_Pos) /*!< 0x00800000 */ +#define CMP_CTRLSTS1_DCMPEN CMP_CTRLSTS1_DCMPEN_Msk /*!< Double comparator mode enable */ + +#define CMP_CTRLSTS1_CMP2TAG_Pos (24U) +#define CMP_CTRLSTS1_CMP2TAG_Msk (0x7U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x07000000 */ +#define CMP_CTRLSTS1_CMP2TAG CMP_CTRLSTS1_CMP2TAG_Msk /*!< CMP2TAG[2:0] bits (Comparator 2 output target) */ +#define CMP_CTRLSTS1_CMP2TAG_0 (0x1U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x01000000 */ +#define CMP_CTRLSTS1_CMP2TAG_1 (0x2U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x02000000 */ +#define CMP_CTRLSTS1_CMP2TAG_2 (0x4U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x04000000 */ + +#define CMP_CTRLSTS1_CMP2P_Pos (27U) +#define CMP_CTRLSTS1_CMP2P_Msk (0x1U << CMP_CTRLSTS1_CMP2P_Pos) /*!< 0x08000000 */ +#define CMP_CTRLSTS1_CMP2P CMP_CTRLSTS1_CMP2P_Msk /*!< Comparator 2 polarity */ + +#define CMP_CTRLSTS1_CMP2HYST_Pos (28U) +#define CMP_CTRLSTS1_CMP2HYST_Msk (0x3U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x30000000 */ +#define CMP_CTRLSTS1_CMP2HYST CMP_CTRLSTS1_CMP2HYST_Msk /*!< CMP2HYST[1:0] bits (Comparator 2 hysteresis) */ +#define CMP_CTRLSTS1_CMP2HYST_0 (0x1U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x10000000 */ +#define CMP_CTRLSTS1_CMP2HYST_1 (0x2U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x20000000 */ + +#define CMP_CTRLSTS1_CMP2VALUE_Pos (30U) +#define CMP_CTRLSTS1_CMP2VALUE_Msk (0x1U << CMP_CTRLSTS1_CMP2VALUE_Pos) /*!< 0x40000000 */ +#define CMP_CTRLSTS1_CMP2VALUE CMP_CTRLSTS1_CMP2VALUE_Msk /*!< Comparator 2 output value */ +#define CMP_CTRLSTS1_CMP2WP_Pos (31U) +#define CMP_CTRLSTS1_CMP2WP_Msk (0x1U << CMP_CTRLSTS1_CMP2WP_Pos) /*!< 0x80000000 */ +#define CMP_CTRLSTS1_CMP2WP CMP_CTRLSTS1_CMP2WP_Msk /*!< Comparator 2 write protect */ + +/***************** Bit definition for CMP_CTRLSTS2 register *****************/ +#define CMP_CTRLSTS2_CMP1NINVSEL_Pos (0U) +#define CMP_CTRLSTS2_CMP1NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000003 */ +#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< Comparator 1 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP1NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000001 */ +#define CMP_CTRLSTS2_CMP1NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000002 */ + +#define CMP_CTRLSTS2_CMP2NINVSEL_Pos (16U) +#define CMP_CTRLSTS2_CMP2NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00030000 */ +#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< Comparator 2 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP2NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00010000 */ +#define CMP_CTRLSTS2_CMP2NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00020000 */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DEBUG) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DEBUG_IDCODE register *****************/ +#define DEBUG_IDCODE_PID_Pos (0U) +#define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ +#define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ +#define DEBUG_IDCODE_PID_0 (0x00000001U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000001 */ +#define DEBUG_IDCODE_PID_1 (0x00000002U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000002 */ +#define DEBUG_IDCODE_PID_2 (0x00000004U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000004 */ +#define DEBUG_IDCODE_PID_3 (0x00000008U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000008 */ +#define DEBUG_IDCODE_PID_4 (0x00000010U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000010 */ +#define DEBUG_IDCODE_PID_5 (0x00000020U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000020 */ +#define DEBUG_IDCODE_PID_6 (0x00000040U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000040 */ +#define DEBUG_IDCODE_PID_7 (0x00000080U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000080 */ +#define DEBUG_IDCODE_PID_8 (0x00000100U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000100 */ +#define DEBUG_IDCODE_PID_9 (0x00000200U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000200 */ +#define DEBUG_IDCODE_PID_10 (0x00000400U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000400 */ +#define DEBUG_IDCODE_PID_11 (0x00000800U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000800 */ +#define DEBUG_IDCODE_PID_12 (0x00001000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00001000 */ +#define DEBUG_IDCODE_PID_13 (0x00002000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00002000 */ +#define DEBUG_IDCODE_PID_14 (0x00004000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00004000 */ +#define DEBUG_IDCODE_PID_15 (0x00008000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00008000 */ +#define DEBUG_IDCODE_PID_16 (0x00010000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00010000 */ +#define DEBUG_IDCODE_PID_17 (0x00020000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00020000 */ +#define DEBUG_IDCODE_PID_18 (0x00040000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00040000 */ +#define DEBUG_IDCODE_PID_19 (0x00080000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00080000 */ +#define DEBUG_IDCODE_PID_20 (0x00100000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00100000 */ +#define DEBUG_IDCODE_PID_21 (0x00200000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00200000 */ +#define DEBUG_IDCODE_PID_22 (0x00400000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00400000 */ +#define DEBUG_IDCODE_PID_23 (0x00800000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00800000 */ +#define DEBUG_IDCODE_PID_24 (0x01000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x01000000 */ +#define DEBUG_IDCODE_PID_25 (0x02000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x02000000 */ +#define DEBUG_IDCODE_PID_26 (0x04000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x04000000 */ +#define DEBUG_IDCODE_PID_27 (0x08000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x08000000 */ +#define DEBUG_IDCODE_PID_28 (0x10000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x10000000 */ +#define DEBUG_IDCODE_PID_29 (0x20000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x20000000 */ +#define DEBUG_IDCODE_PID_30 (0x40000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x40000000 */ +#define DEBUG_IDCODE_PID_31 (0x80000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DEBUG_CTRL register ******************/ +#define DEBUG_CTRL_SLEEP_DEBUG_Pos (0U) +#define DEBUG_CTRL_SLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_SLEEP_DEBUG_Pos) /*!< 0x00000001 */ +#define DEBUG_CTRL_SLEEP_DEBUG DEBUG_CTRL_SLEEP_DEBUG_Msk /*!< Debug Sleep mode control bit */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos) +#define DEBUG_CTRL_DEEPSLEEP_DEBUG DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk /*!< Debug Deep sleep mode control bit */ +#define DEBUG_CTRL_STANDBY_DEBUG_Pos (2U) +#define DEBUG_CTRL_STANDBY_DEBUG_Msk (0x1U << DEBUG_CTRL_STANDBY_DEBUG_Pos) /*!< 0x00000004 */ +#define DEBUG_CTRL_STANDBY_DEBUG DEBUG_CTRL_STANDBY_DEBUG_Msk /*!< Debug Standby mode control bit */ +#define DEBUG_CTRL_TRACE_IOEN_Pos (5U) +#define DEBUG_CTRL_TRACE_IOEN_Msk (0x1U << DEBUG_CTRL_TRACE_IOEN_Pos) /*!< 0x00000020 */ +#define DEBUG_CTRL_TRACE_IOEN DEBUG_CTRL_TRACE_IOEN_Msk /*!< Trace pin assignment enable */ + +#define DEBUG_CTRL_TRACE_MODE_Pos (6U) +#define DEBUG_CTRL_TRACE_MODE_Msk (0x3U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DEBUG_CTRL_TRACE_MODE DEBUG_CTRL_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace pin assignment control) */ +#define DEBUG_CTRL_TRACE_MODE_0 (0x1U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DEBUG_CTRL_TRACE_MODE_1 (0x2U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x00000080 */ + +#define DEBUG_CTRL_WDT_PAUSE_Pos (8U) +#define DEBUG_CTRL_WDT_PAUSE_Msk (0x1U << DEBUG_CTRL_WDT_PAUSE_Pos) /*!< 0x00000100 */ +#define DEBUG_CTRL_WDT_PAUSE DEBUG_CTRL_WDT_PAUSE_Msk /*!< Watchdog pause control bit */ +#define DEBUG_CTRL_WWDT_PAUSE_Pos (9U) +#define DEBUG_CTRL_WWDT_PAUSE_Msk (0x1U << DEBUG_CTRL_WWDT_PAUSE_Pos) /*!< 0x00000200 */ +#define DEBUG_CTRL_WWDT_PAUSE DEBUG_CTRL_WWDT_PAUSE_Msk /*!< Window watchdog pause control bit */ +#define DEBUG_CTRL_TMR1_PAUSE_Pos (10U) +#define DEBUG_CTRL_TMR1_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR1_PAUSE_Pos) /*!< 0x00000400 */ +#define DEBUG_CTRL_TMR1_PAUSE DEBUG_CTRL_TMR1_PAUSE_Msk /*!< TMR1 pause control bit */ +#define DEBUG_CTRL_TMR2_PAUSE_Pos (11U) +#define DEBUG_CTRL_TMR2_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR2_PAUSE_Pos) /*!< 0x00000800 */ +#define DEBUG_CTRL_TMR2_PAUSE DEBUG_CTRL_TMR2_PAUSE_Msk /*!< TMR2 pause control bit */ +#define DEBUG_CTRL_TMR3_PAUSE_Pos (12U) +#define DEBUG_CTRL_TMR3_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR3_PAUSE_Pos) /*!< 0x00001000 */ +#define DEBUG_CTRL_TMR3_PAUSE DEBUG_CTRL_TMR3_PAUSE_Msk /*!< TMR3 pause control bit */ +#define DEBUG_CTRL_TMR4_PAUSE_Pos (13U) +#define DEBUG_CTRL_TMR4_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR4_PAUSE_Pos) /*!< 0x00002000 */ +#define DEBUG_CTRL_TMR4_PAUSE DEBUG_CTRL_TMR4_PAUSE_Msk /*!< TMR4 pause control bit */ +#define DEBUG_CTRL_CAN1_PAUSE_Pos (14U) +#define DEBUG_CTRL_CAN1_PAUSE_Msk (0x1U << DEBUG_CTRL_CAN1_PAUSE_Pos) /*!< 0x00004000 */ +#define DEBUG_CTRL_CAN1_PAUSE DEBUG_CTRL_CAN1_PAUSE_Msk /*!< CAN1 pause control bit */ +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Pos (15U) /*!< 0x00008000 */ +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Pos) +#define DEBUG_CTRL_I2C1_SMBUS_TIMEOUT DEBUG_CTRL_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 pause control bit */ +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Pos (16U) /*!< 0x00010000 */ +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Pos) +#define DEBUG_CTRL_I2C2_SMBUS_TIMEOUT DEBUG_CTRL_I2C2_SMBUS_TIMEOUT_Msk /*!< I2C2 pause control bit */ +#define DEBUG_CTRL_TMR5_PAUSE_Pos (18U) +#define DEBUG_CTRL_TMR5_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR5_PAUSE_Pos) /*!< 0x00040000 */ +#define DEBUG_CTRL_TMR5_PAUSE DEBUG_CTRL_TMR5_PAUSE_Msk /*!< TMR5 pause control bit */ +#define DEBUG_CTRL_TMR9_PAUSE_Pos (28U) +#define DEBUG_CTRL_TMR9_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR9_PAUSE_Pos) /*!< 0x10000000 */ +#define DEBUG_CTRL_TMR9_PAUSE DEBUG_CTRL_TMR9_PAUSE_Msk /*!< TMR9 pause control bit */ +#define DEBUG_CTRL_TMR10_PAUSE_Pos (29U) +#define DEBUG_CTRL_TMR10_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR10_PAUSE_Pos) /*!< 0x20000000 */ +#define DEBUG_CTRL_TMR10_PAUSE DEBUG_CTRL_TMR10_PAUSE_Msk /*!< TMR10 pause control bit */ +#define DEBUG_CTRL_TMR11_PAUSE_Pos (30U) +#define DEBUG_CTRL_TMR11_PAUSE_Msk (0x1U << DEBUG_CTRL_TMR11_PAUSE_Pos) /*!< 0x40000000 */ +#define DEBUG_CTRL_TMR11_PAUSE DEBUG_CTRL_TMR11_PAUSE_Msk /*!< TMR11 pause control bit */ + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +/******************************* CAN Instances ********************************/ +#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + +/******************************* DMA Instances ********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ + ((INSTANCE) == DMA1_Channel2) || \ + ((INSTANCE) == DMA1_Channel3) || \ + ((INSTANCE) == DMA1_Channel4) || \ + ((INSTANCE) == DMA1_Channel5) || \ + ((INSTANCE) == DMA1_Channel6) || \ + ((INSTANCE) == DMA1_Channel7) || \ + ((INSTANCE) == DMA2_Channel1) || \ + ((INSTANCE) == DMA2_Channel2) || \ + ((INSTANCE) == DMA2_Channel3) || \ + ((INSTANCE) == DMA2_Channel4) || \ + ((INSTANCE) == DMA2_Channel5) || \ + ((INSTANCE) == DMA2_Channel6) || \ + ((INSTANCE) == DMA2_Channel7)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOF)) + +/********************* IOMUX Multiplex Function Instances *********************/ +#define IS_IOMUX_ALL_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************* I2C Instances ********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE + +/******************************* I2S Instances ********************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/******************************* WDT Instances ********************************/ +#define IS_WDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WDT) + +/******************************* SDIO Instances *******************************/ +#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) + +/******************************* SPI Instances ********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/**************************** START TMR Instances *****************************/ +/******************************* TMR Instances ********************************/ +#define IS_TMR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_C1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_C2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_C3_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_C4_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_CLOCKSOURCE_EXTMODE1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_CLOCKSOURCE_EXTMODE2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_CLOCKSOURCE_TRGIN_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_CLOCKSOURCE_ISX_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_XOR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_MASTER_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_SLAVE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9)) + +#define IS_TMR_DMABURST_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_BREAK_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_CX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TMR1) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR2) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR3) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR4) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR5) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3) || \ + ((CHANNEL) == TMR_CHANNEL_4))) \ + || \ + (((INSTANCE) == TMR9) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2))) \ + || \ + (((INSTANCE) == TMR10) && \ + (((CHANNEL) == TMR_CHANNEL_1))) \ + || \ + (((INSTANCE) == TMR11) && \ + (((CHANNEL) == TMR_CHANNEL_1)))) + +#define IS_TMR_CXN_INSTANCE(INSTANCE, CHANNEL) \ + (((INSTANCE) == TMR1) && \ + (((CHANNEL) == TMR_CHANNEL_1) || \ + ((CHANNEL) == TMR_CHANNEL_2) || \ + ((CHANNEL) == TMR_CHANNEL_3))) + +#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1) + +#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5) || \ + ((INSTANCE) == TMR9) || \ + ((INSTANCE) == TMR10) || \ + ((INSTANCE) == TMR11)) + +#define IS_TMR_DMA_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_DMA_CC_INSTANCE(INSTANCE)\ + (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ + ((INSTANCE) == TMR1)) + +#define IS_TMR_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3) || \ + ((INSTANCE) == TMR4) || \ + ((INSTANCE) == TMR5)) + +#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE) 0U + +/***************************** END TMR Instances ******************************/ + +/********************* USART Instances : Synchronous mode *********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/********************* UART Instances : Asynchronous mode *********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/********************* UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/************************* UART Instances : LIN mode **************************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/******************* UART Instances : Hardware Flow control *******************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/********************* UART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/************************* UART Instances : IRDA mode *************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/******************* UART Instances : Multi-Processor mode ********************/ +#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/******************** UART Instances : DMA mode available *********************/ +#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == UART4)) + +/******************************* ERTC Instances *******************************/ +#define IS_ERTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ERTC) + +/******************************* WWDT Instances *******************************/ +#define IS_WWDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDT) + +#define CRM_HEXT_MIN 4000000U +#define CRM_HEXT_MAX 25000000U + +#define CRM_MAX_FREQUENCY 150000000U + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F415Rx_H */ + +/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h new file mode 100644 index 0000000000..e6a798bae5 --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h @@ -0,0 +1,112 @@ +/** + ************************************************************************** + * @file system_at32f415.h + * @author Artery Technology & HorrorTroll & Zhaqian + * @brief CMSIS AT32F415 system header file + * + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup AT32F415_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ + +#ifndef __SYSTEM_AT32F415_H +#define __SYSTEM_AT32F415_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup AT32F415_System_Includes + * @{ + */ + +/** @defgroup AT32F415_System_Clock_Stable_Definition + * @{ + */ + +#define HEXT_STABLE_DELAY (5000u) +#define PLL_STABLE_DELAY (500u) + +/** + * @} + */ + +/** @defgroup AT32F415_System_Exported_Variables + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup AT32F415_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup AT32F415_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup AT32F415_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_AT32F415_H */ + +/** + * @} + */ + +/** + * @} + */ + +/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld new file mode 100644 index 0000000000..f42f326a33 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld @@ -0,0 +1,87 @@ +/* + Copyright (C) 2023..2024 Artery Technology + Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT32F415x8 memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 64k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld new file mode 100644 index 0000000000..5ddf72c8f7 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld @@ -0,0 +1,87 @@ +/* + Copyright (C) 2023..2024 Artery Technology + Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT32F415xB memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld new file mode 100644 index 0000000000..4625d97aa9 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld @@ -0,0 +1,87 @@ +/* + Copyright (C) 2023..2024 Artery Technology + Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT32F415xC memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 256k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk new file mode 100644 index 0000000000..42ed33dbe5 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk @@ -0,0 +1,19 @@ +# List of the ChibiOS generic AT32F415x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/AT32F415 \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ArteryTek/AT32F415 + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h new file mode 100644 index 0000000000..0e45ffc616 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio. + (C) 2015 RedoX (https://github.com/RedoXyde) + (C) 2023-2024 HorrorTroll (https://github.com/HorrorTroll) + (C) 2023-2024 Zhaqian (https://github.com/zhaqian12) + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AT32F415/cmparams.h + * @brief ARM Cortex-M4 parameters for the Artery AT32F415 + * + * @defgroup ARMCMx_AT32F415 Artery AT32F415 Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * Artery AT32F415 platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the include file.*/ +#if !defined(AT32F415KB) && !defined(AT32F415KC) && !defined(AT32F415CB) && \ + !defined(AT32F415CC) && !defined(AT32F415RB) && !defined(AT32F415RC) +#include "board.h" +#endif + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 80 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "at32f415.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/hal/boards/AT_START_F415/board.c b/os/hal/boards/AT_START_F415/board.c new file mode 100644 index 0000000000..ef92f8d769 --- /dev/null +++ b/os/hal/boards/AT_START_F415/board.c @@ -0,0 +1,55 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODT, VAL_GPIOACFGLR, VAL_GPIOACFGHR}, + {VAL_GPIOBODT, VAL_GPIOBCFGLR, VAL_GPIOBCFGHR}, +#if AT32_HAS_GPIOC + {VAL_GPIOCODT, VAL_GPIOCCFGLR, VAL_GPIOCCFGHR}, +#endif + {VAL_GPIODODT, VAL_GPIODCFGLR, VAL_GPIODCFGHR}, +#if AT32_HAS_GPIOF + {VAL_GPIOFODT, VAL_GPIOFCFGLR, VAL_GPIOFCFGHR}, +#endif +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + at32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/AT_START_F415/board.h b/os/hal/boards/AT_START_F415/board.h new file mode 100644 index 0000000000..ae3de31e48 --- /dev/null +++ b/os/hal/boards/AT_START_F415/board.h @@ -0,0 +1,230 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a AT-START-F415 board. + */ + +/* + * Board identifier. + */ +#define BOARD_AT_START_F415 +#define BOARD_NAME "Artery AT-START-F415" + +/* + * Board frequencies. + */ +#define AT32_LEXTCLK 32768 +#define AT32_HEXTCLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define AT32F415RC + +/* + * IO pins assignments. + */ +#define GPIOA_ARD_A0 0U +#define GPIOA_ADC1_IN0 0U +#define GPIOA_BUTTON 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_ADC1_IN1 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_USART2_TX 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_USART2_RX 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ADC1_IN4 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_ARD_D10 15U + +#define GPIOB_ARD_A3 0U +#define GPIOB_ADC1_IN8 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_ARD_D3 3U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_ARD_SCL 8U +#define GPIOB_ARD_SDA 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_PIN10 10U +#define GPIOB_ARD_PB11 11U +#define GPIOB_PIN11 11U +#define GPIOB_ARD_NSS 12U +#define GPIOB_PIN12 12U +#define GPIOB_ARD_SCK 13U +#define GPIOB_ARD_MISO 14U +#define GPIOB_ARD_MOSI 15U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ADC1_IN10 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ADC1_IN11 1U +#define GPIOC_LED_RED 2U +#define GPIOC_LED_YELLOW 3U +#define GPIOC_PIN4 4U +#define GPIOC_LED_GREEN 5U +#define GPIOC_PIN6 6U +#define GPIOC_ARD_D9 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_BUTTON 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_OSC_IN 0U +#define GPIOD_PIN0 0U +#define GPIOD_OSC_OUT 1U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with Pull-Up or Pull-Down resistor depending on ODT. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the AT32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (GPIOA_BUTTON) + * PA2 - Alternate output (GPIOA_ARD_D1, GPIOA_USART2_TX) + * PA3 - Normal input (GPIOA_ARD_D0, GPIOA_USART2_RX) + * PA13 - Pull-up input (GPIOA_SWDIO) + * PA14 - Pull-down input (GPIOA_SWCLK) + */ +#define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */ +#define VAL_GPIOACFGHR 0x88888888 /* PA15...PA8 */ +#define VAL_GPIOAODT 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB3 - Pull-up input (GPIOB_SWO) + */ +#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */ +#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */ +#define VAL_GPIOBODT 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC2 - Push Pull output (GPIOC_LED_RED) + * PC3 - Push Pull output (GPIOC_LED_YELLOW) + * PC5 - Push Pull output (GPIOC_LED_GREEN) + * PC13 - Normal input (GPIOC_BUTTON) + */ +#define VAL_GPIOCCFGLR 0x88383388 /* PC7...PC0 */ +#define VAL_GPIOCCFGHR 0x88488888 /* PC15...PC8 */ +#define VAL_GPIOCODT 0xFFFFFFFF + +/* + * Port D setup. + * PD0 - Normal input (GPIOD_OSC_IN). + * PD1 - Normal input (GPIOD_OSC_OUT). + */ +#define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODT 0xFFFFFFFF + +/* + * Port F setup. + */ +#define VAL_GPIOFCFGLR 0x88888888 /* PF7...PF0 */ +#define VAL_GPIOFCFGHR 0x88888888 /* PF15...PF8 */ +#define VAL_GPIOFODT 0xFFFFFFFF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/AT_START_F415/board.mk b/os/hal/boards/AT_START_F415/board.mk new file mode 100644 index 0000000000..ae0eab3ba7 --- /dev/null +++ b/os/hal/boards/AT_START_F415/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/AT_START_F415 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/ports/AT32/AT32F415/at32_crm.h b/os/hal/ports/AT32/AT32F415/at32_crm.h new file mode 100644 index 0000000000..0c42907f63 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/at32_crm.h @@ -0,0 +1,815 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/at32_crm.h + * @brief CRM helper driver header. + * @note This file requires definitions from the AT header file + * @p at32f415.h. + * + * @addtogroup AT32F415_CRM + * @{ + */ + +#ifndef AT32_CRM_H +#define AT32_CRM_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic CRM operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableAPB1(mask, lp) { \ + CRM->APB1EN |= (mask); \ + (void)CRM->APB1EN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define crmDisableAPB1(mask) { \ + CRM->APB1EN &= ~(mask); \ + (void)CRM->APB1EN; \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define crmResetAPB1(mask) { \ + CRM->APB1RST |= (mask); \ + CRM->APB1RST &= ~(mask); \ + (void)CRM->APB1RST; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableAPB2(mask, lp) { \ + CRM->APB2EN |= (mask); \ + (void)CRM->APB2EN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define crmDisableAPB2(mask) { \ + CRM->APB2EN &= ~(mask); \ + (void)CRM->APB2EN; \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define crmResetAPB2(mask) { \ + CRM->APB2RST |= (mask); \ + CRM->APB2RST &= ~(mask); \ + (void)CRM->APB2RST; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableAHB(mask, lp) { \ + CRM->AHBEN |= (mask); \ + (void)CRM->AHBEN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define crmDisableAHB(mask) { \ + CRM->AHBEN &= ~(mask); \ + (void)CRM->AHBEN; \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define crmResetAHB(mask) { \ + CRM->AHBRST |= (mask); \ + CRM->AHBRST &= ~(mask); \ + (void)CRM->AHBRST; \ +} +/** @} */ + +/** + * @name ADC peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableADC1(lp) crmEnableAPB2(CRM_APB2EN_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @api + */ +#define crmDisableADC1() crmDisableAPB2(CRM_APB2EN_ADC1EN) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define crmResetADC1() crmResetAPB2(CRM_APB2RST_ADC1RST) +/** @} */ + +/** + * @name PWC interface specific CRM operations + * @{ + */ +/** + * @brief Enables the PWC interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnablePWCInterface(lp) crmEnableAPB1(CRM_APB1EN_PWCEN, lp) + +/** + * @brief Disables PWC interface clock. + * + * @api + */ +#define crmDisablePWCInterface() crmDisableAPB1(CRM_APB1EN_PWCEN) + +/** + * @brief Resets the PWC interface. + * + * @api + */ +#define crmResetPWCInterface() crmResetAPB1(CRM_APB1RST_PWCRST) +/** @} */ + +/** + * @name CAN peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableCAN1(lp) crmEnableAPB1(CRM_APB1EN_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * + * @api + */ +#define crmDisableCAN1() crmDisableAPB1(CRM_APB1EN_CAN1EN) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define crmResetCAN1() crmResetAPB1(CRM_APB1RST_CAN1RST) + +/** + * @name DMA peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableDMA1(lp) crmEnableAHB(CRM_AHBEN_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @api + */ +#define crmDisableDMA1() crmDisableAHB(CRM_AHBEN_DMA1EN) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define crmResetDMA1() + +/** + * @brief Enables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableDMA2(lp) crmEnableAHB(CRM_AHBEN_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @api + */ +#define crmDisableDMA2() crmDisableAHB(CRM_AHBEN_DMA2EN) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define crmResetDMA2() +/** @} */ + +/** + * @name I2C peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableI2C1(lp) crmEnableAPB1(CRM_APB1EN_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @api + */ +#define crmDisableI2C1() crmDisableAPB1(CRM_APB1EN_I2C1EN) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define crmResetI2C1() crmResetAPB1(CRM_APB1RST_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableI2C2(lp) crmEnableAPB1(CRM_APB1EN_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @api + */ +#define crmDisableI2C2() crmDisableAPB1(CRM_APB1EN_I2C2EN) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define crmResetI2C2() crmResetAPB1(CRM_APB1RST_I2C2RST) +/** @} */ + +/** + * @name OTG peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableOTG_FS(lp) crmEnableAHB(CRM_AHBEN_OTGFSEN, lp) + +/** + * @brief Disables the OTG_FS peripheral clock. + * + * @api + */ +#define crmDisableOTG_FS() crmDisableAHB(CRM_AHBEN_OTGFSEN) + +/** + * @brief Resets the OTG_FS peripheral. + * + * @api + */ +#define crmResetOTG_FS() crmResetAHB(CRM_AHBRST_OTGFSRST) +/** @} */ + +/** + * @name SDIO peripheral specific CRM operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableSDIO(lp) crmEnableAHB(CRM_AHBEN_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * + * @api + */ +#define crmDisableSDIO() crmDisableAHB(CRM_AHBEN_SDIOEN) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define crmResetSDIO() +/** @} */ + +/** + * @name SPI peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableSPI1(lp) crmEnableAPB2(CRM_APB2EN_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @api + */ +#define crmDisableSPI1() crmDisableAPB2(CRM_APB2EN_SPI1EN) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define crmResetSPI1() crmResetAPB2(CRM_APB2RST_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableSPI2(lp) crmEnableAPB1(CRM_APB1EN_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @api + */ +#define crmDisableSPI2() crmDisableAPB1(CRM_APB1EN_SPI2EN) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define crmResetSPI2() crmResetAPB1(CRM_APB1RST_SPI2RST) + +/** + * @name TMR peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the TMR1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR1(lp) crmEnableAPB2(CRM_APB2EN_TMR1EN, lp) + +/** + * @brief Disables the TMR1 peripheral clock. + * + * @api + */ +#define crmDisableTMR1() crmDisableAPB2(CRM_APB2EN_TMR1EN) + +/** + * @brief Resets the TMR1 peripheral. + * + * @api + */ +#define crmResetTMR1() crmResetAPB2(CRM_APB2RST_TMR1RST) + +/** + * @brief Enables the TMR2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR2(lp) crmEnableAPB1(CRM_APB1EN_TMR2EN, lp) + +/** + * @brief Disables the TMR2 peripheral clock. + * + * @api + */ +#define crmDisableTMR2() crmDisableAPB1(CRM_APB1EN_TMR2EN) + +/** + * @brief Resets the TMR2 peripheral. + * + * @api + */ +#define crmResetTMR2() crmResetAPB1(CRM_APB1RST_TMR2RST) + +/** + * @brief Enables the TMR3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR3(lp) crmEnableAPB1(CRM_APB1EN_TMR3EN, lp) + +/** + * @brief Disables the TMR3 peripheral clock. + * + * @api + */ +#define crmDisableTMR3() crmDisableAPB1(CRM_APB1EN_TMR3EN) + +/** + * @brief Resets the TMR3 peripheral. + * + * @api + */ +#define crmResetTMR3() crmResetAPB1(CRM_APB1RST_TMR3RST) + +/** + * @brief Enables the TMR4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR4(lp) crmEnableAPB1(CRM_APB1EN_TMR4EN, lp) + +/** + * @brief Disables the TMR4 peripheral clock. + * + * @api + */ +#define crmDisableTMR4() crmDisableAPB1(CRM_APB1EN_TMR4EN) + +/** + * @brief Resets the TMR4 peripheral. + * + * @api + */ +#define crmResetTMR4() crmResetAPB1(CRM_APB1RST_TMR4RST) + +/** + * @brief Enables the TMR5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR5(lp) crmEnableAPB1(CRM_APB1EN_TMR5EN, lp) + +/** + * @brief Disables the TMR5 peripheral clock. + * + * @api + */ +#define crmDisableTMR5() crmDisableAPB1(CRM_APB1EN_TMR5EN) + +/** + * @brief Resets the TMR5 peripheral. + * + * @api + */ +#define crmResetTMR5() crmResetAPB1(CRM_APB1RST_TMR5RST) + +/** + * @brief Enables the TMR9 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR9(lp) crmEnableAPB2(CRM_APB2EN_TMR9EN, lp) + +/** + * @brief Disables the TMR9 peripheral clock. + * + * @api + */ +#define crmDisableTMR9() crmDisableAPB2(CRM_APB2EN_TMR9EN) + +/** + * @brief Resets the TMR9 peripheral. + * + * @api + */ +#define crmResetTMR9() crmResetAPB2(CRM_APB2RST_TMR9RST) + +/** + * @brief Enables the TMR10 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR10(lp) crmEnableAPB2(CRM_APB2EN_TMR10EN, lp) + +/** + * @brief Disables the TMR10 peripheral clock. + * + * @api + */ +#define crmDisableTMR10() crmDisableAPB2(CRM_APB2EN_TMR10EN) + +/** + * @brief Resets the TMR10 peripheral. + * + * @api + */ +#define crmResetTMR10() crmResetAPB2(CRM_APB2RST_TMR10RST) + +/** + * @brief Enables the TMR11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableTMR11(lp) crmEnableAPB2(CRM_APB2EN_TMR11EN, lp) + +/** + * @brief Disables the TMR11 peripheral clock. + * + * @api + */ +#define crmDisableTMR11() crmDisableAPB2(CRM_APB2EN_TMR11EN) + +/** + * @brief Resets the TMR11 peripheral. + * + * @api + */ +#define crmResetTMR11() crmResetAPB2(CRM_APB2RST_TMR11RST) + +/** + * @name USART/UART peripherals specific CRM operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableUSART1(lp) crmEnableAPB2(CRM_APB2EN_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @api + */ +#define crmDisableUSART1() crmDisableAPB2(CRM_APB2EN_USART1EN) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define crmResetUSART1() crmResetAPB2(CRM_APB2RST_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableUSART2(lp) crmEnableAPB1(CRM_APB1EN_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @api + */ +#define crmDisableUSART2() crmDisableAPB1(CRM_APB1EN_USART2EN) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define crmResetUSART2() crmResetAPB1(CRM_APB1RST_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableUSART3(lp) crmEnableAPB1(CRM_APB1EN_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @api + */ +#define crmDisableUSART3() crmDisableAPB1(CRM_APB1EN_USART3EN) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define crmResetUSART3() crmResetAPB1(CRM_APB1RST_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableUART4(lp) crmEnableAPB1(CRM_APB1EN_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * + * @api + */ +#define crmDisableUART4() crmDisableAPB1(CRM_APB1EN_UART4EN) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define crmResetUART4() crmResetAPB1(CRM_APB1RST_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define crmEnableUART5(lp) crmEnableAPB1(CRM_APB1EN_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * + * @api + */ +#define crmDisableUART5() crmDisableAPB1(CRM_APB1EN_UART5EN) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define crmResetUART5() crmResetAPB1(CRM_APB1RST_UART5RST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* AT32_CRM_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/at32_dmamux.h b/os/hal/ports/AT32/AT32F415/at32_dmamux.h new file mode 100644 index 0000000000..a584394b20 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/at32_dmamux.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/at32_dmamux.h + * @brief AT32F415 DMAMUX handler header. + * + * @addtogroup AT32F415_DMAMUX + * @{ + */ + +#ifndef AT32_DMAMUX_H +#define AT32_DMAMUX_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name DMAMUX request sources + * @{ + */ +#define AT32_DMAMUX_ADC1 1 +#define AT32_DMAMUX_SPI1_RX 9 +#define AT32_DMAMUX_SPI1_TX 10 +#define AT32_DMAMUX_SPI2_RX 11 +#define AT32_DMAMUX_SPI2_TX 12 +#define AT32_DMAMUX_USART1_RX 25 +#define AT32_DMAMUX_USART1_TX 26 +#define AT32_DMAMUX_USART2_RX 27 +#define AT32_DMAMUX_USART2_TX 28 +#define AT32_DMAMUX_USART3_RX 29 +#define AT32_DMAMUX_USART3_TX 30 +#define AT32_DMAMUX_UART4_RX 31 +#define AT32_DMAMUX_UART4_TX 32 +#define AT32_DMAMUX_UART5_RX 33 +#define AT32_DMAMUX_UART5_TX 34 +#define AT32_DMAMUX_I2C1_RX 41 +#define AT32_DMAMUX_I2C1_TX 42 +#define AT32_DMAMUX_I2C2_RX 43 +#define AT32_DMAMUX_I2C2_TX 44 +#define AT32_DMAMUX_SDIO1 49 +#define AT32_DMAMUX_TMR1_TRIG 53 +#define AT32_DMAMUX_TMR1_HALL 54 +#define AT32_DMAMUX_TMR1_OVERFLOW 55 +#define AT32_DMAMUX_TMR1_CH1 56 +#define AT32_DMAMUX_TMR1_CH2 57 +#define AT32_DMAMUX_TMR1_CH3 58 +#define AT32_DMAMUX_TMR1_CH4 59 +#define AT32_DMAMUX_TMR2_TRIG 61 +#define AT32_DMAMUX_TMR2_OVERFLOW 63 +#define AT32_DMAMUX_TMR2_CH1 64 +#define AT32_DMAMUX_TMR2_CH2 65 +#define AT32_DMAMUX_TMR2_CH3 66 +#define AT32_DMAMUX_TMR2_CH4 67 +#define AT32_DMAMUX_TMR3_TRIG 69 +#define AT32_DMAMUX_TMR3_OVERFLOW 71 +#define AT32_DMAMUX_TMR3_CH1 72 +#define AT32_DMAMUX_TMR3_CH2 73 +#define AT32_DMAMUX_TMR3_CH3 74 +#define AT32_DMAMUX_TMR3_CH4 75 +#define AT32_DMAMUX_TMR4_TRIG 77 +#define AT32_DMAMUX_TMR4_OVERFLOW 79 +#define AT32_DMAMUX_TMR4_CH1 80 +#define AT32_DMAMUX_TMR4_CH2 81 +#define AT32_DMAMUX_TMR4_CH3 82 +#define AT32_DMAMUX_TMR4_CH4 83 +#define AT32_DMAMUX_TMR5_TRIG 85 +#define AT32_DMAMUX_TMR5_OVERFLOW 87 +#define AT32_DMAMUX_TMR5_CH1 88 +#define AT32_DMAMUX_TMR5_CH2 89 +#define AT32_DMAMUX_TMR5_CH3 90 +#define AT32_DMAMUX_TMR5_CH4 91 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* AT32_DMAMUX_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.c b/os/hal/ports/AT32/AT32F415/at32_isr.c new file mode 100644 index 0000000000..0ffb999140 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/at32_isr.c @@ -0,0 +1,157 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/at32_isr.c + * @brief AT32F415 ISR handler code. + * + * @addtogroup AT32F415_ISR + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#define exint_serve_irq(intsts, channel) { \ + \ + if ((intsts) & (1U << (channel))) { \ + _pal_isr_code(channel); \ + } \ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#include "at32_exint0.inc" +#include "at32_exint1.inc" +#include "at32_exint2.inc" +#include "at32_exint3.inc" +#include "at32_exint4.inc" +#include "at32_exint5_9.inc" +#include "at32_exint10_15.inc" +#include "at32_exint16.inc" +#include "at32_exint17.inc" +#include "at32_exint18.inc" +#include "at32_exint19.inc" +#include "at32_exint20.inc" +#include "at32_exint21.inc" +#include "at32_exint22.inc" + +#include "at32_tmr1_9_10_11.inc" +#include "at32_tmr2.inc" +#include "at32_tmr3.inc" +#include "at32_tmr4.inc" +#include "at32_tmr5.inc" + +#include "at32_usart1.inc" +#include "at32_usart2.inc" +#include "at32_usart3.inc" +#include "at32_uart4.inc" +#include "at32_uart5.inc" + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables IRQ sources. + * + * @notapi + */ +void irqInit(void) { + + exint0_irq_init(); + exint1_irq_init(); + exint2_irq_init(); + exint3_irq_init(); + exint4_irq_init(); + exint5_9_irq_init(); + exint10_15_irq_init(); + exint16_irq_init(); + exint17_irq_init(); + exint18_irq_init(); + exint19_irq_init(); + exint20_irq_init(); + exint21_irq_init(); + exint22_irq_init(); + + tmr1_tmr9_tmr10_tmr11_irq_init(); + tmr2_irq_init(); + tmr3_irq_init(); + tmr4_irq_init(); + tmr5_irq_init(); + + usart1_irq_init(); + usart2_irq_init(); + usart3_irq_init(); + uart4_irq_init(); + uart5_irq_init(); +} + +/** + * @brief Disables IRQ sources. + * + * @notapi + */ +void irqDeinit(void) { + + exint0_irq_deinit(); + exint1_irq_deinit(); + exint2_irq_deinit(); + exint3_irq_deinit(); + exint4_irq_deinit(); + exint5_9_irq_deinit(); + exint10_15_irq_deinit(); + exint16_irq_deinit(); + exint17_irq_deinit(); + exint18_irq_deinit(); + exint19_irq_deinit(); + exint20_irq_deinit(); + exint21_irq_deinit(); + exint22_irq_deinit(); + + tmr1_tmr9_tmr10_tmr11_irq_deinit(); + tmr2_irq_deinit(); + tmr3_irq_deinit(); + tmr4_irq_deinit(); + tmr5_irq_deinit(); + + usart1_irq_deinit(); + usart2_irq_deinit(); + usart3_irq_deinit(); + uart4_irq_deinit(); + uart5_irq_deinit(); +} + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.h b/os/hal/ports/AT32/AT32F415/at32_isr.h new file mode 100644 index 0000000000..239867cc1a --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/at32_isr.h @@ -0,0 +1,260 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/at32_isr.h + * @brief AT32F415 ISR handler header. + * + * @addtogroup AT32F415_ISR + * @{ + */ + +#ifndef AT32_ISR_H +#define AT32_ISR_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISRs suppressed in standard drivers + * @{ + */ +#define AT32_TMR1_SUPPRESS_ISR +#define AT32_TMR2_SUPPRESS_ISR +#define AT32_TMR3_SUPPRESS_ISR +#define AT32_TMR4_SUPPRESS_ISR +#define AT32_TMR5_SUPPRESS_ISR +#define AT32_TMR9_SUPPRESS_ISR +#define AT32_TMR10_SUPPRESS_ISR +#define AT32_TMR11_SUPPRESS_ISR + +#define AT32_USART1_SUPPRESS_ISR +#define AT32_USART2_SUPPRESS_ISR +#define AT32_USART3_SUPPRESS_ISR +#define AT32_UART4_SUPPRESS_ISR +#define AT32_UART5_SUPPRESS_ISR +/** @} */ + +/** + * @name ISR names and numbers remapping + * @{ + */ +/* + * CAN units. + */ +#define AT32_CAN1_TX_HANDLER Vector8C +#define AT32_CAN1_RX0_HANDLER Vector90 +#define AT32_CAN1_RX1_HANDLER Vector94 +#define AT32_CAN1_SE_HANDLER Vector98 + +#define AT32_CAN1_TX_NUMBER 19 +#define AT32_CAN1_RX0_NUMBER 20 +#define AT32_CAN1_RX1_NUMBER 21 +#define AT32_CAN1_SE_NUMBER 22 + +/* + * DMA unit + */ +#define AT32_DMA1_CH1_HANDLER Vector6C +#define AT32_DMA1_CH2_HANDLER Vector70 +#define AT32_DMA1_CH3_HANDLER Vector74 +#define AT32_DMA1_CH4_HANDLER Vector78 +#define AT32_DMA1_CH5_HANDLER Vector7C +#define AT32_DMA1_CH6_HANDLER Vector80 +#define AT32_DMA1_CH7_HANDLER Vector84 + +#define AT32_DMA1_CH1_NUMBER 11 +#define AT32_DMA1_CH2_NUMBER 12 +#define AT32_DMA1_CH3_NUMBER 13 +#define AT32_DMA1_CH4_NUMBER 14 +#define AT32_DMA1_CH5_NUMBER 15 +#define AT32_DMA1_CH6_NUMBER 16 +#define AT32_DMA1_CH7_NUMBER 17 + +#define AT32_DMA2_CH1_HANDLER Vector120 +#define AT32_DMA2_CH2_HANDLER Vector124 +#define AT32_DMA2_CH3_HANDLER Vector128 +#define AT32_DMA2_CH4_5_HANDLER Vector12C +#define AT32_DMA2_CH6_7_HANDLER Vector16C + +#define AT32_DMA2_CH1_NUMBER 56 +#define AT32_DMA2_CH2_NUMBER 57 +#define AT32_DMA2_CH3_NUMBER 58 +#define AT32_DMA2_CH4_5_NUMBER 59 +#define AT32_DMA2_CH6_7_NUMBER 75 + +#define AT32_DMA2_CH4_NUMBER AT32_DMA2_CH4_5_NUMBER +#define AT32_DMA2_CH5_NUMBER AT32_DMA2_CH4_5_NUMBER +#define AT32_DMA2_CH6_NUMBER AT32_DMA2_CH6_7_NUMBER +#define AT32_DMA2_CH7_NUMBER AT32_DMA2_CH6_7_NUMBER + +#define AT32_DMA2_CH4_CMASK 0x00000C00U +#define AT32_DMA2_CH5_CMASK 0x00000C00U +#define AT32_DMA2_CH6_CMASK 0x00003000U +#define AT32_DMA2_CH7_CMASK 0x00003000U + +/* + * ERTC unit + */ +#define AT32_ERTC_TAMP_STAMP_HANDLER Vector48 +#define AT32_ERTC_WKUP_HANDLER Vector4C +#define AT32_ERTC_ALARM_HANDLER VectorE4 + +#define AT32_ERTC_TAMP_STAMP_NUMBER 2 +#define AT32_ERTC_WKUP_NUMBER 3 +#define AT32_ERTC_ALARM_NUMBER 41 + +#define AT32_ERTC_ALARM_EXINT 17 +#define AT32_ERTC_TAMP_STAMP_EXINT 21 +#define AT32_ERTC_WKUP_EXINT 22 +#define AT32_ERTC_IRQ_ENABLE() do { \ + nvicEnableVector(AT32_ERTC_TAMP_STAMP_NUMBER, AT32_IRQ_EXINT21_PRIORITY); \ + nvicEnableVector(AT32_ERTC_WKUP_NUMBER, AT32_IRQ_EXINT22_PRIORITY); \ + nvicEnableVector(AT32_ERTC_ALARM_NUMBER, AT32_IRQ_EXINT17_PRIORITY); \ +} while (false) + +/* + * EXINT unit. + */ +#define AT32_EXINT0_HANDLER Vector58 +#define AT32_EXINT1_HANDLER Vector5C +#define AT32_EXINT2_HANDLER Vector60 +#define AT32_EXINT3_HANDLER Vector64 +#define AT32_EXINT4_HANDLER Vector68 +#define AT32_EXINT5_9_HANDLER Vector9C +#define AT32_EXINT10_15_HANDLER VectorE0 +#define AT32_EXINT16_HANDLER Vector44 /* Note: same as PVM_IRQn */ +#define AT32_EXINT17_HANDLER VectorE4 /* Note: same as ERTCAlarm_IRQn */ +#define AT32_EXINT18_HANDLER VectorE8 /* Note: same as OTGFS_WKUP_IRQn */ +#define AT32_EXINT19_HANDLER Vector158 /* Note: same as CMP1_IRQn */ +#define AT32_EXINT20_HANDLER Vector15C /* Note: same as CMP2_IRQn */ +#define AT32_EXINT21_HANDLER Vector48 /* Note: same as TAMPER_IRQn */ +#define AT32_EXINT22_HANDLER Vector4C /* Note: same as ERTC_IRQn */ + +#define AT32_EXINT0_NUMBER 6 +#define AT32_EXINT1_NUMBER 7 +#define AT32_EXINT2_NUMBER 8 +#define AT32_EXINT3_NUMBER 9 +#define AT32_EXINT4_NUMBER 10 +#define AT32_EXINT5_9_NUMBER 23 +#define AT32_EXINT10_15_NUMBER 40 +#define AT32_EXINT16_NUMBER 1 /* Note: same as PVM_IRQn */ +#define AT32_EXINT17_NUMBER 41 /* Note: same as ERTCAlarm_IRQn */ +#define AT32_EXINT18_NUMBER 42 /* Note: same as OTGFS_WKUP_IRQn */ +#define AT32_EXINT19_NUMBER 70 /* Note: same as CMP1_IRQn */ +#define AT32_EXINT20_NUMBER 71 /* Note: same as CMP2_IRQn */ +#define AT32_EXINT21_NUMBER 2 /* Note: same as TAMPER_IRQn */ +#define AT32_EXINT22_NUMBER 3 /* Note: same as ERTC_IRQn */ + +/* + * I2C units. + */ +#define AT32_I2C1_EVENT_HANDLER VectorBC +#define AT32_I2C1_ERROR_HANDLER VectorC0 +#define AT32_I2C2_EVENT_HANDLER VectorC4 +#define AT32_I2C2_ERROR_HANDLER VectorC8 + +#define AT32_I2C1_EVENT_NUMBER 31 +#define AT32_I2C1_ERROR_NUMBER 32 +#define AT32_I2C2_EVENT_NUMBER 33 +#define AT32_I2C2_ERROR_NUMBER 34 + +/* + * OTGFS units. + */ +#define AT32_OTG1_HANDLER Vector14C + +#define AT32_OTG1_NUMBER 67 + +/* + * SDIO unit. + */ +#define AT32_SDIO_HANDLER Vector104 + +#define AT32_SDIO_NUMBER 49 + +/* + * TMR units. + */ +#define AT32_TMR1_BRK_TMR9_HANDLER VectorA0 +#define AT32_TMR1_OVF_TMR10_HANDLER VectorA4 +#define AT32_TMR1_HALL_TMR11_HANDLER VectorA8 +#define AT32_TMR1_CH_HANDLER VectorAC +#define AT32_TMR2_HANDLER VectorB0 +#define AT32_TMR3_HANDLER VectorB4 +#define AT32_TMR4_HANDLER VectorB8 +#define AT32_TMR5_HANDLER Vector108 + +#define AT32_TMR1_BRK_TMR9_NUMBER 24 +#define AT32_TMR1_OVF_TMR10_NUMBER 25 +#define AT32_TMR1_HALL_TMR11_NUMBER 26 +#define AT32_TMR1_CH_NUMBER 27 +#define AT32_TMR2_NUMBER 28 +#define AT32_TMR3_NUMBER 29 +#define AT32_TMR4_NUMBER 30 +#define AT32_TMR5_NUMBER 50 + +/* + * USART units. + */ +#define AT32_USART1_HANDLER VectorD4 +#define AT32_USART2_HANDLER VectorD8 +#define AT32_USART3_HANDLER VectorDC +#define AT32_UART4_HANDLER Vector110 +#define AT32_UART5_HANDLER Vector114 + +#define AT32_USART1_NUMBER 37 +#define AT32_USART2_NUMBER 38 +#define AT32_USART3_NUMBER 39 +#define AT32_UART4_NUMBER 52 +#define AT32_UART5_NUMBER 53 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void irqInit(void); + void irqDeinit(void); +#ifdef __cplusplus +} +#endif + +#endif /* AT32_ISR_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h new file mode 100644 index 0000000000..859e24d829 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -0,0 +1,1408 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/at32_registry.h + * @brief AT32F415 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef AT32_REGISTRY_H +#define AT32_REGISTRY_H + +#if defined(AT32F415KB) +#define AT32F415K_MD + +#elif defined(AT32F415KC) +#define AT32F415K_HD + +#elif defined(AT32F415CB) +#define AT32F415C_MD + +#elif defined(AT32F415CC) +#define AT32F415C_HD + +#elif defined(AT32F415RB) +#define AT32F415R_MD + +#elif defined(AT32F415RC) +#define AT32F415R_HD + +#else +#error "unsupported or unrecognized AT32F415 member" +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(AT32F415K_MD) || defined(__DOXYGEN__) +/** + * @name AT32F415K MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#else +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_DMA_SUPPORTS_DMAMUX TRUE +#else +#define AT32_DMA_SUPPORTS_DMAMUX FALSE +#endif + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#define AT32_EXINT_NUM_LINES 23 +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#define AT32_FLASH_SECTOR_SIZE 1024U + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC FALSE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF FALSE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#endif + +#define AT32_HAS_I2C2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#else +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#endif + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#endif + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#endif + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR5 TRUE +#define AT32_TMR5_IS_32BITS TRUE +#define AT32_TMR5_CHANNELS 4 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +#define AT32_HAS_USART2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#endif + +#define AT32_HAS_USART3 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#endif + +#define AT32_HAS_UART4 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) +#endif + +#define AT32_HAS_UART5 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#endif + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 1 +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 3 + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE +/** @} */ +#endif /* defined(AT32F415K_MD) */ + +#if defined(AT32F415K_HD) || defined(__DOXYGEN__) +/** + * @name AT32F415K HD capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#else +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_DMA_SUPPORTS_DMAMUX TRUE +#else +#define AT32_DMA_SUPPORTS_DMAMUX FALSE +#endif + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#define AT32_EXINT_NUM_LINES 23 +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#define AT32_FLASH_SECTOR_SIZE 2048U + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC FALSE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF FALSE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#endif + +#define AT32_HAS_I2C2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#else +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#endif + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#endif + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#endif + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR5 TRUE +#define AT32_TMR5_IS_32BITS TRUE +#define AT32_TMR5_CHANNELS 4 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +#define AT32_HAS_USART2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#endif + +#define AT32_HAS_USART3 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#endif + +#define AT32_HAS_UART4 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) +#endif + +#define AT32_HAS_UART5 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#endif + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 1 +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 3 + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE +/** @} */ +#endif /* defined(AT32F415K_HD) */ + +#if defined(AT32F415C_MD) || defined(__DOXYGEN__) +/** + * @name AT32F415C MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#else +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_DMA_SUPPORTS_DMAMUX TRUE +#else +#define AT32_DMA_SUPPORTS_DMAMUX FALSE +#endif + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#define AT32_EXINT_NUM_LINES 23 +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#define AT32_FLASH_SECTOR_SIZE 1024U + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF TRUE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#endif + +#define AT32_HAS_I2C2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#else +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#endif + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#endif + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#endif + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR5 TRUE +#define AT32_TMR5_IS_32BITS TRUE +#define AT32_TMR5_CHANNELS 4 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +#define AT32_HAS_USART2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#endif + +#define AT32_HAS_USART3 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#endif + +#define AT32_HAS_UART4 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) +#endif + +#define AT32_HAS_UART5 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#endif + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 1 +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 3 + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE +/** @} */ +#endif /* defined(AT32F415C_MD) */ + +#if defined(AT32F415C_HD) || defined(__DOXYGEN__) +/** + * @name AT32F415C HD capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#else +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_DMA_SUPPORTS_DMAMUX TRUE +#else +#define AT32_DMA_SUPPORTS_DMAMUX FALSE +#endif + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#define AT32_EXINT_NUM_LINES 23 +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#define AT32_FLASH_SECTOR_SIZE 2048U + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF TRUE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#endif + +#define AT32_HAS_I2C2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#else +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#endif + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#endif + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#endif + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR5 TRUE +#define AT32_TMR5_IS_32BITS TRUE +#define AT32_TMR5_CHANNELS 4 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +#define AT32_HAS_USART2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#endif + +#define AT32_HAS_USART3 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#endif + +#define AT32_HAS_UART4 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) +#endif + +#define AT32_HAS_UART5 FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#endif + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 1 +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 3 + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE +/** @} */ +#endif /* defined(AT32F415C_HD) */ + +#if defined(AT32F415R_MD) || defined(__DOXYGEN__) +/** + * @name AT32F415R MD capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#else +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_DMA_SUPPORTS_DMAMUX TRUE +#else +#define AT32_DMA_SUPPORTS_DMAMUX FALSE +#endif + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#define AT32_EXINT_NUM_LINES 23 +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#define AT32_FLASH_SECTOR_SIZE 1024U + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF TRUE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#endif + +#define AT32_HAS_I2C2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#else +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#endif + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#endif + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#endif + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR5 TRUE +#define AT32_TMR5_IS_32BITS TRUE +#define AT32_TMR5_CHANNELS 4 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +#define AT32_HAS_USART2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#endif + +#define AT32_HAS_USART3 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#endif + +#define AT32_HAS_UART4 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) +#endif + +#define AT32_HAS_UART5 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#endif + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 1 +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 3 + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE +/** @} */ +#endif /* defined(AT32F415R_MD) */ + +#if defined(AT32F415R_HD) || defined(__DOXYGEN__) +/** + * @name AT32F415R HD capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#else +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_DMA_SUPPORTS_DMAMUX TRUE +#else +#define AT32_DMA_SUPPORTS_DMAMUX FALSE +#endif + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#define AT32_EXINT_NUM_LINES 23 +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#define AT32_FLASH_SECTOR_SIZE 2048U + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF TRUE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#endif + +#define AT32_HAS_I2C2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#else +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#else +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#endif + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#endif + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX FALSE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#else +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#endif + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR5 TRUE +#define AT32_TMR5_IS_32BITS TRUE +#define AT32_TMR5_CHANNELS 4 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#endif + +#define AT32_HAS_USART2 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#endif + +#define AT32_HAS_USART3 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#endif + +#define AT32_HAS_UART4 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#else +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) +#endif + +#define AT32_HAS_UART5 TRUE + +#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#endif + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 1 +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 3 + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE +/** @} */ +#endif /* defined(AT32F415R_HD) */ + +#endif /* AT32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c new file mode 100644 index 0000000000..f14e0b1ca3 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c @@ -0,0 +1,492 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.c + * @brief AT32F415 Embedded Flash subsystem low level driver source. + * + * @addtogroup HAL_EFL + * @{ + */ + +#include + +#include "hal.h" + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define AT32_FLASH_LINE_SIZE 2U +#define AT32_FLASH_LINE_MASK (AT32_FLASH_LINE_SIZE - 1U) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EFL1 driver identifier. + */ +EFlashDriver EFLD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const flash_descriptor_t efl_lld_descriptor = { + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED, + .page_size = AT32_FLASH_LINE_SIZE, + .sectors_count = AT32_FLASH_NUMBER_OF_BANKS * + AT32_FLASH_SECTORS_PER_BANK, + .sectors = NULL, + .sectors_size = AT32_FLASH_SECTOR_SIZE, + .address = (uint8_t *)FLASH_BASE, + .size = AT32_FLASH_NUMBER_OF_BANKS * + AT32_FLASH_SECTORS_PER_BANK * + AT32_FLASH_SECTOR_SIZE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void at32_flash_lock(EFlashDriver *eflp) { + + eflp->flash->CTRL |= FLASH_CTRL_OPLK; +} + +static inline void at32_flash_unlock(EFlashDriver *eflp) { + + eflp->flash->UNLOCK = FLASH_KEY1; + eflp->flash->UNLOCK = FLASH_KEY2; +} + +static inline void at32_flash_enable_pgm(EFlashDriver *eflp) { + + eflp->flash->CTRL |= FLASH_CTRL_FPRGM; +} + +static inline void at32_flash_disable_pgm(EFlashDriver *eflp) { + + eflp->flash->CTRL &= ~FLASH_CTRL_FPRGM; +} + +static inline void at32_flash_clear_status(EFlashDriver *eflp) { + + eflp->flash->STS = 0x0000001FU; +} + +static inline uint32_t at32_flash_is_busy(EFlashDriver *eflp) { + + return (eflp->flash->STS & FLASH_STS_OBF); +} + +static inline void at32_flash_wait_busy(EFlashDriver *eflp) { + + /* Wait for busy bit clear.*/ + while (at32_flash_is_busy(eflp) != 0U) { + } +} + +static inline flash_error_t at32_flash_check_errors(EFlashDriver *eflp) { + uint32_t sts = eflp->flash->STS; + + /* Clearing error conditions.*/ + eflp->flash->STS = sts & 0x0000001FU; + + /* Decoding relevant errors.*/ + if ((sts & FLASH_STS_EPPERR) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + if ((sts & FLASH_STS_PRGMERR) != 0U) { + return FLASH_ERROR_PROGRAM; /* There is no error on erase.*/ + } + + return FLASH_NO_ERROR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level Embedded Flash driver initialization. + * + * @notapi + */ +void efl_lld_init(void) { + + /* Driver initialization.*/ + eflObjectInit(&EFLD1); + EFLD1.flash = FLASH; +} + +/** + * @brief Configures and activates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_start(EFlashDriver *eflp) { + + at32_flash_unlock(eflp); + FLASH->CTRL = 0x00000000U; +} + +/** + * @brief Deactivates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_stop(EFlashDriver *eflp) { + + at32_flash_lock(eflp); +} + +/** + * @brief Gets the flash descriptor structure. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return A flash device descriptor. + * + * @notapi + */ +const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { + + (void)instance; + + return &efl_lld_descriptor; +} + +/** + * @brief Read operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset flash offset + * @param[in] n number of bytes to be read + * @param[out] rp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_READ if the read operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No reading while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_READY state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Clearing error status bits.*/ + at32_flash_clear_status(devp); + + /* Actual read implementation.*/ + memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Program operation. + * @note It is only possible to write erased pages once except + * when writing all zeroes. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset flash offset + * @param[in] n number of bytes to be programmed + * @param[in] pp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_PROGRAM if the program operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size); + + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No programming while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_PGM; + + /* Clearing error status bits.*/ + at32_flash_clear_status(devp); + + /* Enabling PGM mode in the controller.*/ + at32_flash_enable_pgm(devp); + + /* Actual program implementation.*/ + while (n > 0U) { + volatile uint16_t *address; + + union { + uint16_t hw[AT32_FLASH_LINE_SIZE / sizeof (uint16_t)]; + uint8_t b[AT32_FLASH_LINE_SIZE / sizeof (uint8_t)]; + } line; + + /* Unwritten bytes are initialized to all ones.*/ + line.hw[0] = 0xFFFFU; + + /* Programming address aligned to flash lines.*/ + address = (volatile uint16_t *)(efl_lld_descriptor.address + + (offset & ~AT32_FLASH_LINE_MASK)); + + /* Copying data inside the prepared line.*/ + do { + line.b[offset & AT32_FLASH_LINE_MASK] = *pp; + offset++; + n--; + pp++; + } + while ((n > 0U) & ((offset & AT32_FLASH_LINE_MASK) != 0U)); + + /* Programming line.*/ + address[0] = line.hw[0]; + at32_flash_wait_busy(devp); + + err = at32_flash_check_errors(devp); + if (err != FLASH_NO_ERROR) { + break; + } + + /* Check for flash error.*/ + if (address[0] != line.hw[0]) { + err = FLASH_ERROR_PROGRAM; + break; + } + } + + /* Disabling PGM mode in the controller.*/ + at32_flash_disable_pgm(devp); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Starts a whole-device erase operation. + * @note This function does nothing, the flash memory is where the program + * is running on. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_all(void *instance) { + (void) instance; + + return FLASH_ERROR_UNIMPLEMENTED; +} + +/** + * @brief Starts an sector erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be erased + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < efl_lld_descriptor.sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + at32_flash_clear_status(devp); + + /* Enable page erase.*/ + devp->flash->CTRL |= FLASH_CTRL_SECERS; + + /* Set the page.*/ + devp->flash->ADDR = (uint32_t)(efl_lld_descriptor.address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* Start the erase.*/ + devp->flash->CTRL |= FLASH_CTRL_ERSTR; + + return FLASH_NO_ERROR; +} + +/** + * @brief Queries the driver for erase operation progress. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[out] wait_time recommended time, in milliseconds, that + * should be spent before calling this + * function again, can be @p NULL + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_ERASE if the erase operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @api + */ +flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err; + + /* If there is an erase in progress then the device must be checked.*/ + if (devp->state == FLASH_ERASE) { + + /* Checking for operation in progress.*/ + if (at32_flash_is_busy(devp) == 0U) { + + /* Disabling the various erase control bits.*/ + devp->flash->CTRL &= ~(FLASH_CTRL_USDERS | FLASH_CTRL_USDPRGM | + FLASH_CTRL_BANKERS | FLASH_CTRL_SECERS); + + /* Back to ready state.*/ + devp->state = FLASH_READY; + + err = FLASH_NO_ERROR; + } + else { + /* Recommended time before polling again, this is a simplified + implementation.*/ + if (wait_time != NULL) { + *wait_time = (uint32_t)AT32_FLASH_WAIT_TIME_MS; + } + + err = FLASH_BUSY_ERASING; + } + } + else { + err = FLASH_NO_ERROR; + } + + return err; +} + +/** + * @brief Returns the erase state of a sector. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be verified + * @return An error code. + * @retval FLASH_NO_ERROR if the sector is erased. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_VERIFY if the verify operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + uint32_t *address; + flash_error_t err = FLASH_NO_ERROR; + unsigned i; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < efl_lld_descriptor.sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No verifying while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* Address of the sector.*/ + address = (uint32_t *)(efl_lld_descriptor.address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* FLASH_READY state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Scanning the sector space.*/ + for (i = 0U; i < AT32_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) { + if (*address != 0xFFFFFFFFU) { + err = FLASH_ERROR_VERIFY; + break; + } + address++; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +#endif /* HAL_USE_EFL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.h b/os/hal/ports/AT32/AT32F415/hal_efl_lld.h new file mode 100644 index 0000000000..327d3cfb37 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.h @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.h + * @brief AT32F415 Embedded Flash subsystem low level driver header. + * + * @addtogroup HAL_EFL + * @{ + */ + +#ifndef HAL_EFL_LLD_H +#define HAL_EFL_LLD_H + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name AT32F415 configuration options + * @{ + */ +/** + * @brief Suggested wait time during erase operations polling. + */ +#if !defined(AT32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) +#define AT32_FLASH_WAIT_TIME_MS 1 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(AT32_FLASH_SECTOR_SIZE) +#error "AT32_FLASH_SECTOR_SIZE not defined in registry" +#endif + +#if !defined(AT32_FLASH_NUMBER_OF_BANKS) +#error "AT32_FLASH_NUMBER_OF_BANKS not defined in registry" +#endif + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) +#error "AT32_FLASH_SECTORS_PER_BANK not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the embedded flash driver structure. + */ +#define efl_lld_driver_fields \ + /* Flash registers.*/ \ + FLASH_TypeDef *flash + +/** + * @brief Low level fields of the embedded flash configuration structure. + */ +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EFlashDriver EFLD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void efl_lld_init(void); + void efl_lld_start(EFlashDriver *eflp); + void efl_lld_stop(EFlashDriver *eflp); + const flash_descriptor_t *efl_lld_get_descriptor(void *instance); + flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t efl_lld_start_erase_all(void *instance); + flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector); + flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time); + flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EFL == TRUE */ + +#endif /* HAL_EFL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.c b/os/hal/ports/AT32/AT32F415/hal_lld.c new file mode 100644 index 0000000000..40bacd1d27 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/hal_lld.c @@ -0,0 +1,281 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/hal_lld.c + * @brief AT32F415 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief CMSIS system core clock variable. + * @note It is declared in system_at32f415.h. + */ +uint32_t SystemCoreClock = AT32_HCLK; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the battery powered domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BPR domain. + */ +static void hal_lld_battery_powered_domain_init(void) { + + /* Battery powered domain access enabled and left open. */ + PWC->CTRL |= PWC_CTRL_BPWEN; + + /* Reset BPR domain if different clock source selected. */ + if ((CRM->BPDC & AT32_ERTCSEL_MASK) != AT32_ERTCSEL) { + /* Battery powered domain reset. */ + CRM->BPDC = CRM_BPDC_BPDRST; + CRM->BPDC = 0; + } + +#if AT32_LEXT_ENABLED +#if defined(AT32_LEXT_BYPASS) + /* LEXT Bypass. */ + CRM->BPDC |= CRM_BPDC_LEXTEN | CRM_BPDC_LEXTBYPS; +#else + /* No LEXT Bypass. */ + CRM->BPDC |= CRM_BPDC_LEXTEN; +#endif + while ((CRM->BPDC & CRM_BPDC_LEXTSTBL) == 0) + ; /* Waits until LEXT is stable. */ +#endif + +#if HAL_USE_RTC + /* If the battery powered domain hasn't been initialized yet then proceed + with initialization. */ + if ((CRM->BPDC & CRM_BPDC_ERTCEN) == 0) { + /* Selects clock source. */ + CRM->BPDC |= AT32_ERTCSEL; + + /* ERTC clock enabled. */ + CRM->BPDC |= CRM_BPDC_ERTCEN; + } +#endif /* HAL_USE_RTC */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_DMA_REQUIRED) || defined(__DOXYGEN__) +#if defined(AT32_DMA2_CH4_5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 streams 4 and 5 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH4_5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + /* Check on channel 4 of DMA2. */ + dmaServeInterrupt(AT32_DMA2_STREAM4); + + /* Check on channel 5 of DMA2. */ + dmaServeInterrupt(AT32_DMA2_STREAM5); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* defined(AT32_DMA2_CH4_5_HANDLER) */ + +#if defined(AT32_DMA2_CH6_7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 streams 6 and 7 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH6_7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + /* Check on channel 6 of DMA2.*/ + dmaServeInterrupt(AT32_DMA2_STREAM6); + + /* Check on channel 7 of DMA2.*/ + dmaServeInterrupt(AT32_DMA2_STREAM7); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* defined(AT32_DMA2_CH6_7_HANDLER) */ +#endif /* defined(AT32_DMA_REQUIRED) */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals. */ + crmResetAPB1(0xFFFFFFFF); + crmResetAPB2(0xFFFFFFFF); + + /* PWC clocks enabled. */ + crmEnablePWCInterface(true); + + /* Initializes the backup domain. */ + hal_lld_battery_powered_domain_init(); + + /* DMA subsystems initialization. */ +#if defined(AT32_DMA_REQUIRED) + dmaInit(); +#endif + + /* IRQ subsystem initialization. */ + irqInit(); + + /* Power voltage monitoring enable. */ +#if AT32_PVM_ENABLE + PWC->CTRL |= PWC_CTRL_PVMEN | (AT32_PVMSEL & AT32_PVMSEL_MASK); +#endif /* AT32_PVM_ENABLE */ +} + +/** + * @brief AT32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ + +/* + * Clocks initialization for all series. + */ +void at32_clock_init(void) { + +#if !AT32_NO_INIT + /* HICK setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations. */ + CRM->CTRL |= CRM_CTRL_HICKEN; /* Make sure HICK is ON. */ + while (!(CRM->CTRL & CRM_CTRL_HICKSTBL)) + ; /* Wait until HICK is stable. */ + + /* HICK is selected as new source without touching the other fields in + CFGR. Clearing the register has to be postponed after HICK is the + new source. */ + CRM->CFG &= ~CRM_CFG_SCLKSEL; /* Reset SCLKSEL, selecting HICK. */ + while ((CRM->CFG & CRM_CFG_SCLKSTS) != CRM_CFG_SCLKSTS_HICK) + ; /* Waits until HICK is selected. */ + + /* Registers finally cleared to reset values. */ + CRM->CTRL &= ~(0x010D0000U); /* CTRL reset value. */ + CRM->CFG = 0x00000000; /* CFG reset value. */ + CRM->PLL = 0x00001F10U; /* PLL reset value. */ + CRM->MISC1 = 0x00100000; /* MISC1 reset value. */ + CRM->MISC2 = 0x0000000D; /* MISC2 reset value. */ + CRM->CLKINT = 0x009F0000; /* CLKINT reset value. */ + + /* Flash setup and final clock selection. */ + FLASH->PSR = AT32_FLASHBITS; /* Flash wait states depending on clock. */ + while ((FLASH->PSR & FLASH_PSR_WTCYC_Msk) != + (AT32_FLASHBITS & FLASH_PSR_WTCYC_Msk)) { + } + +#if AT32_HEXT_ENABLED +#if defined(AT32_HEXT_BYPASS) + /* HEXT Bypass. */ + CRM->CTRL |= CRM_CTRL_HEXTEN | CRM_CTRL_HEXTBYPS; +#endif + /* HEXT activation. */ + CRM->CTRL |= CRM_CTRL_HEXTEN; + while (!(CRM->CTRL & CRM_CTRL_HEXTSTBL)) + ; /* Waits until HEXT is stable. */ +#endif + +#if AT32_LICK_ENABLED + /* LICK activation. */ + CRM->CTRLSTS |= CRM_CTRLSTS_LICKEN; + while ((CRM->CTRLSTS & CRM_CTRLSTS_LICKSTBL) == 0) + ; /* Waits until LICK is stable. */ +#endif + +#if AT32_ACTIVATE_PLL + /* PLL activation. */ +#if (AT32_PLLCFGEN == AT32_PLLCFGEN_SOLID) + /* Solid PLL config. */ + CRM->CFG |= AT32_PLLMULT | AT32_PLLHEXTDIV | AT32_PLLRCS; +#ifdef AT32_PLLCLKREF + CRM->PLL |= AT32_PLLCLKREF; +#endif +#else + /* Flexible PLL config. */ + CRM->CFG |= AT32_PLLHEXTDIV | AT32_PLLRCS; + CRM->PLL = AT32_PLL_FR | AT32_PLL_MS | AT32_PLL_NS | AT32_PLLCFGEN; +#endif + + CRM->CTRL |= CRM_CTRL_PLLEN; + while (!(CRM->CTRL & CRM_CTRL_PLLSTBL)) + ; /* Waits until PLL is stable. */ +#endif + + /* Clock settings.*/ +#if AT32_HAS_OTG1 + CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MSK) | AT32_USBDIV | AT32_ADCDIV | + AT32_APB2DIV | AT32_APB1DIV | AT32_AHBDIV; +#else + CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MSK) | AT32_ADCDIV | + AT32_APB2DIV | AT32_APB1DIV | AT32_AHBDIV; +#endif + CRM->MISC1 |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_MISC_MSK) >> 11; + + /* PLL Auto Step activation. */ + CRM->MISC2 |= CRM_MISC2_AUTO_STEP_EN; + + /* Switching to the configured clock source if it is different from HICK. */ +#if (AT32_SCLKSEL != AT32_SCLKSEL_HICK) + /* Switches clock source. */ + CRM->CFG |= AT32_SCLKSEL; + while ((CRM->CFG & CRM_CFG_SCLKSTS) != (AT32_SCLKSEL << 2)) + ; /* Waits selection complete. */ +#endif + + /* PLL Auto Step inactivation. */ + CRM->MISC2 &= ~CRM_MISC2_AUTO_STEP_EN; + +#if !AT32_HICK_ENABLED + CRM->CTRL &= ~CRM_CTRL_HICKEN; +#endif +#endif /* !AT32_NO_INIT */ +} +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.h b/os/hal/ports/AT32/AT32F415/hal_lld.h new file mode 100644 index 0000000000..d1c8375fb2 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/hal_lld.h @@ -0,0 +1,958 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F415/hal_lld.h + * @brief AT32F415 HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - AT32_LEXTCLK. + * - AT32_LEXT_BYPASS (optionally). + * - AT32_HEXTCLK. + * - AT32_HEXT_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - AT32F415KB for K Value Medium Density devices. + * - AT32F415CB for C Value Medium Density devices. + * - AT32F415RB for R Value Medium Density devices. + * - AT32F415KC for K Value High Density devices. + * - AT32F415CC for C Value High Density devices. + * - AT32F415RC for R Value High Density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "at32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Requires use of SPIv2 driver model. + */ +#define HAL_LLD_SELECT_SPI_V2 TRUE + +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "AT32F415" + +#elif defined(AT32F415K_MD) +#define PLATFORM_NAME "AT32F415K Value Line Medium Density" + +#elif defined(AT32F415K_HD) +#define PLATFORM_NAME "AT32F415K Value Line High Density" + +#elif defined(AT32F415C_MD) +#define PLATFORM_NAME "AT32F415C Value Line Medium Density" + +#elif defined(AT32F415C_HD) +#define PLATFORM_NAME "AT32F415C Value Line High Density" + +#elif defined(AT32F415R_MD) +#define PLATFORM_NAME "AT32F415R Value Line Medium Density" + +#elif defined(AT32F415R_HD) +#define PLATFORM_NAME "AT32F415R Value Line High Density" + +#else +#error "unsupported or unrecognized AT32F415 member" +#endif + +/** + * @brief Sub-family identifier. + */ +#if !defined(AT32F415) || defined(__DOXYGEN__) +#define AT32F415 +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ + +/** + * @brief Maximum system clock frequency. + */ +#define AT32_SYSCLK_MAX 150000000 + +/** + * @brief Maximum HEXT clock frequency. + */ +#define AT32_HEXTCLK_MAX 25000000 + +/** + * @brief Minimum HEXT clock frequency. + */ +#define AT32_HEXTCLK_MIN 4000000 + +/** + * @brief Maximum LEXT clock frequency. + */ +#define AT32_LEXTCLK_MAX 1000000 + +/** + * @brief Minimum LEXT clock frequency. + */ +#define AT32_LEXTCLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define AT32_PLLIN_MAX 16000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define AT32_PLLIN_MIN 2000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define AT32_PLLOUT_MAX 150000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define AT32_PLLOUT_MIN 4000000 + +/** + * @brief Maximum PLL FR clock frequency. + */ +#define AT32_PLLFR_MAX 1000000000 + +/** + * @brief Minimum PLL FR clock frequency. + */ +#define AT32_PLLFR_MIN 500000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define AT32_PCLK1_MAX 75000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define AT32_PCLK2_MAX 75000000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define AT32_ADCCLK_MAX 28000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define AT32_HICKCLK 48000000 /**< High speed internal clock. */ +#define AT32_LICKCLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWC_CTRL register bits definitions + * @{ + */ +#define AT32_PVMSEL_MASK (7 << 5) /**< PVMSEL bits mask. */ +#define AT32_PVMSEL_LEV1 (1 << 5) /**< PVM level 1. */ +#define AT32_PVMSEL_LEV2 (2 << 5) /**< PVM level 2. */ +#define AT32_PVMSEL_LEV3 (3 << 5) /**< PVM level 3. */ +#define AT32_PVMSEL_LEV4 (4 << 5) /**< PVM level 4. */ +#define AT32_PVMSEL_LEV5 (5 << 5) /**< PVM level 5. */ +#define AT32_PVMSEL_LEV6 (6 << 5) /**< PVM level 6. */ +#define AT32_PVMSEL_LEV7 (7 << 5) /**< PVM level 7. */ +/** @} */ + +/** + * @name CRM_CFG register bits definitions + * @{ + */ +#define AT32_SCLKSEL_HICK (0 << 0) /**< SCLK source is HICK. */ +#define AT32_SCLKSEL_HEXT (1 << 0) /**< SCLK source is HEXT. */ +#define AT32_SCLKSEL_PLL (2 << 0) /**< SCLK source is PLL. */ + +#define AT32_SCLKSTS_HICK (0 << 2) /**< SCLK use HICK. */ +#define AT32_SCLKSTS_HEXT (1 << 2) /**< SCLK use HEXT. */ +#define AT32_SCLKSTS_PLL (2 << 2) /**< SCLK use PLL. */ + +#define AT32_AHBDIV_DIV1 (0 << 4) /**< SCLK divided by 1. */ +#define AT32_AHBDIV_DIV2 (8 << 4) /**< SCLK divided by 2. */ +#define AT32_AHBDIV_DIV4 (9 << 4) /**< SCLK divided by 4. */ +#define AT32_AHBDIV_DIV8 (10 << 4) /**< SCLK divided by 8. */ +#define AT32_AHBDIV_DIV16 (11 << 4) /**< SCLK divided by 16. */ +#define AT32_AHBDIV_DIV64 (12 << 4) /**< SCLK divided by 64. */ +#define AT32_AHBDIV_DIV128 (13 << 4) /**< SCLK divided by 128. */ +#define AT32_AHBDIV_DIV256 (14 << 4) /**< SCLK divided by 256. */ +#define AT32_AHBDIV_DIV512 (15 << 4) /**< SCLK divided by 512. */ + +#define AT32_APB1DIV_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define AT32_APB1DIV_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define AT32_APB1DIV_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define AT32_APB1DIV_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define AT32_APB1DIV_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define AT32_APB2DIV_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define AT32_APB2DIV_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define AT32_APB2DIV_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define AT32_APB2DIV_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define AT32_APB2DIV_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define AT32_ADCDIV_DIV2 (0 << 14) /**< APB2DIV divided by 2. */ +#define AT32_ADCDIV_DIV4 (1 << 14) /**< APB2DIV divided by 4. */ +#define AT32_ADCDIV_DIV6 (2 << 14) /**< APB2DIV divided by 6. */ +#define AT32_ADCDIV_DIV8 (3 << 14) /**< APB2DIV divided by 8. */ +#define AT32_ADCDIV_DIV12 ((1 << 28) | (1 << 14)) /**< APB2DIV divided by 12. */ +#define AT32_ADCDIV_DIV16 ((1 << 28) | (3 << 14)) /**< APB2DIV divided by 16. */ + +#define AT32_PLLRCS_HICK (0 << 16) /**< PLL clock source is HICK. */ +#define AT32_PLLRCS_HEXT (1 << 16) /**< PLL clock source is HEXT. */ + +#define AT32_PLLHEXTDIV_DIV1 (0 << 17) /**< HEXT divided by 1. */ +#define AT32_PLLHEXTDIV_DIV2 (1 << 17) /**< HEXT divided by 2. */ + +#define AT32_USBDIV_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */ +#define AT32_USBDIV_DIV1 (1 << 22) /**< PLLOUT divided by 1. */ +#define AT32_USBDIV_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */ +#define AT32_USBDIV_DIV2 (3 << 22) /**< PLLOUT divided by 2. */ +#define AT32_USBDIV_DIV3P5 (1 << 27) /**< PLLOUT divided by 3.5. */ +#define AT32_USBDIV_DIV3 ((1 << 27) | (1 << 22)) /**< PLLOUT divided by 3. */ +#define AT32_USBDIV_DIV4 ((1 << 27) | (2 << 22)) /**< PLLOUT divided by 4. */ + +#define AT32_CLKOUT_SEL_CFG_MSK (7 << 24) /**< CLKOUT_SEL pin on CRM_CFG mask. */ +#define AT32_CLKOUT_SEL_NOCLOCK (0 << 24) /**< No clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_LICK (2 << 24) /**< LICK clockon CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_LEXT (3 << 24) /**< LEXT clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_SCLK (4 << 24) /**< SCLK on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_HICK (5 << 24) /**< HICK clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_HEXT (6 << 24) /**< HEXT clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on CLKOUT_SEL pin. */ +/** @} */ + +/** + * @name CRM_BPDC register bits definitions + * @{ + */ +#define AT32_ERTCSEL_MASK (3 << 8) /**< ERTC clock source mask. */ +#define AT32_ERTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define AT32_ERTCSEL_LEXT (1 << 8) /**< LEXT used as ERTC clock. */ +#define AT32_ERTCSEL_LICK (2 << 8) /**< LICK used as ERTC clock. */ +#define AT32_ERTCSEL_HEXTDIV (3 << 8) /**< HEXT divided by 128 used as + ERTC clock. */ +/** @} */ + +/** + * @name CRM_PLL register bits definitions + * @{ + */ +#define AT32_PLL_FR_MASK (7 << 0) /**< PLL FR mask. */ +#define AT32_PLL_FR_DIV1 (0 << 0) /**< PLL divided by 1. */ +#define AT32_PLL_FR_DIV2 (1 << 0) /**< PLL divided by 2. */ +#define AT32_PLL_FR_DIV4 (2 << 0) /**< PLL divided by 4. */ +#define AT32_PLL_FR_DIV8 (3 << 0) /**< PLL divided by 8. */ +#define AT32_PLL_FR_DIV16 (4 << 0) /**< PLL divided by 16. */ +#define AT32_PLL_FR_DIV32 (5 << 0) /**< PLL divided by 32. */ + +#define AT32_PLLCFGEN_SOLID (0 << 31) /**< PLL use solid config. */ +#define AT32_PLLCFGEN_FLEX (1 << 31) /**< PLL use flexible config. */ + +/** + * @name CRM_MISC1 Additional Register + * @{ + */ +#define AT32_CLKOUT_SEL_MISC_MSK (1 << 27) /**< CLKOUT_SEL pin on CRM_MISC1 mask. */ +#define AT32_CLKOUT_SEL_PLLDIV4 ((1 << 16) | (AT32_CLKOUT_SEL_SCLK)) + /**< PLL/4 clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_USB ((1 << 16) | (AT32_CLKOUT_SEL_HICK)) + /**< USB clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_ADC ((1 << 16) | (AT32_CLKOUT_SEL_HEXT)) + /**< ADC clock on CLKOUT_SEL pin. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWC/CRM initialization in the HAL. + */ +#if !defined(AT32_NO_INIT) || defined(__DOXYGEN__) +#define AT32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the power voltage monitoring. + */ +#if !defined(AT32_PVM_ENABLE) || defined(__DOXYGEN__) +#define AT32_PVM_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for power voltage monitoring. + */ +#if !defined(AT32_PVMSEL) || defined(__DOXYGEN__) +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#endif + +/** + * @brief Enables or disables the HICK clock source. + */ +#if !defined(AT32_HICK_ENABLED) || defined(__DOXYGEN__) +#define AT32_HICK_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LICK clock source. + */ +#if !defined(AT32_LICK_ENABLED) || defined(__DOXYGEN__) +#define AT32_LICK_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HEXT clock source. + */ +#if !defined(AT32_HEXT_ENABLED) || defined(__DOXYGEN__) +#define AT32_HEXT_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LEXT clock source. + */ +#if !defined(AT32_LEXT_ENABLED) || defined(__DOXYGEN__) +#define AT32_LEXT_ENABLED FALSE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 144MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(AT32_SCLKSEL) || defined(__DOXYGEN__) +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 144MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(AT32_PLLRCS) || defined(__DOXYGEN__) +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#endif + +/** + * @brief Crystal PLL pre-divider. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 144MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(AT32_PLLHEXTDIV) || defined(__DOXYGEN__) +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed range is 2...64. + * @note The default value is calculated for a 144MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(AT32_PLLMULT_VALUE) || defined(__DOXYGEN__) +#define AT32_PLLMULT_VALUE 18 +#endif + +/** + * @brief PLL config method. + */ +#if !defined(AT32_PLLCFGEN) || defined(__DOXYGEN__) +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#endif + +/** + * @brief PLL FR divider value. + * @note The allowed values are 1, 2, 4, 8, 16, 32. + * @note The default value is calculated for a 144MHz system clock from + * an external 8MHz HEXT clock. + */ +#if !defined(AT32_PLL_FR_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_FR_VALUE 4 +#endif + +/** + * @brief PLL MS divider value. + * @note The allowed values are 1..15. + * @note The default value is calculated for a 144MHz system clock from + * an external 8MHz HEXT clock. + */ +#if !defined(AT32_PLL_MS_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_MS_VALUE 1 +#endif + +/** + * @brief PLL NS multiplier value. + * @note The allowed values are 31..500. + * @note The default value is calculated for a 144MHz system clock from + * an external 8MHz HEXT clock. + */ +#if !defined(AT32_PLL_NS_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_NS_VALUE 72 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 144MHz system clock from + * a 8MHz crystal using the PLL. + */ +#if !defined(AT32_AHBDIV) || defined(__DOXYGEN__) +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(AT32_APB1DIV) || defined(__DOXYGEN__) +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(AT32_APB2DIV) || defined(__DOXYGEN__) +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#endif + +/** + * @brief ADC prescaler value. + */ +#if !defined(AT32_ADCDIV) || defined(__DOXYGEN__) +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(AT32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__) +#define AT32_USB_CLOCK_REQUIRED TRUE +#endif + +/** + * @brief USB prescaler initialization. + */ +#if !defined(AT32_USBDIV) || defined(__DOXYGEN__) +#define AT32_USBDIV AT32_USBDIV_DIV3 +#endif + +/** + * @brief CLKOUT_SEL pin setting. + */ +#if !defined(AT32_CLKOUT_SEL) || defined(__DOXYGEN__) +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#endif + +/** + * @brief ERTC clock source. + */ +#if !defined(AT32_ERTCSEL) || defined(__DOXYGEN__) +#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(AT32F415_MCUCONF) +#error "Using a wrong mcuconf.h file, AT32F415_MCUCONF not defined" +#endif + +/* + * HICK related checks. + */ +#if AT32_HICK_ENABLED +#else /* !AT32_HICK_ENABLED */ + +#if AT32_SCLKSEL == AT32_SCLKSEL_HICK +#error "HICK not enabled, required by AT32_SCLKSEL" +#endif + +#if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HICK) +#error "HICK not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" +#endif + +#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_HICK) || \ + (((AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLLDIV2) || \ + (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLLDIV4)) && \ + (AT32_PLLRCS == AT32_PLLRCS_HICK)) +#error "HICK not enabled, required by AT32_CLKOUT_SEL" +#endif + +#endif /* !AT32_HICK_ENABLED */ + +/* + * HEXT related checks. + */ +#if AT32_HEXT_ENABLED + +#if AT32_HEXTCLK == 0 +#error "HEXT frequency not defined" +#elif (AT32_HEXTCLK < AT32_HEXTCLK_MIN) || (AT32_HEXTCLK > AT32_HEXTCLK_MAX) +#error "AT32_HEXTCLK outside acceptable range (AT32_HEXTCLK_MIN...AT32_HEXTCLK_MAX)" +#endif + +#else /* !AT32_HEXT_ENABLED */ + +#if AT32_SCLKSEL == AT32_SCLKSEL_HEXT +#error "HEXT not enabled, required by AT32_SCLKSEL" +#endif + +#if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HEXT) +#error "HEXT not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" +#endif + +#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_HEXT) || \ + (((AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLLDIV2) || \ + (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLLDIV4)) && \ + (AT32_PLLRCS == AT32_PLLRCS_HEXT)) +#error "HEXT not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if (AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV) +#error "HEXT not enabled, required by AT32_ERTCSEL" +#endif +#endif /* !AT32_HEXT_ENABLED */ + +/* + * LICK related checks. + */ +#if AT32_LICK_ENABLED +#else /* !AT32_LICK_ENABLED */ + +#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LICK) +#error "LICK not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if HAL_USE_RTC && (AT32_ERTCSEL == AT32_ERTCSEL_LICK) +#error "LICK not enabled, required by AT32_ERTCSEL" +#endif +#endif /* !AT32_LICK_ENABLED */ + +/* + * LEXT related checks. + */ +#if AT32_LEXT_ENABLED + +#if (AT32_LEXTCLK == 0) +#error "LEXT frequency not defined" +#endif + +#if (AT32_LEXTCLK < AT32_LEXTCLK_MIN) || (AT32_LEXTCLK > AT32_LEXTCLK_MAX) +#error "AT32_LEXTCLK outside acceptable range (AT32_LEXTCLK_MIN...AT32_LEXTCLK_MAX)" +#endif + +#else /* !AT32_LEXT_ENABLED */ + +#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LEXT) +#error "LEXT not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if AT32_ERTCSEL == AT32_ERTCSEL_LEXT +#error "LEXT not enabled, required by AT32_ERTCSEL" +#endif + +#endif /* !AT32_LEXT_ENABLED */ + +/* PLL activation conditions.*/ +#if AT32_USB_CLOCK_REQUIRED || \ + (AT32_SCLKSEL == AT32_SCLKSEL_PLL) || \ + (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLLDIV2) || \ + (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLLDIV4) || \ + defined(__DOXYGEN__) + +/** + * @brief PLL activation flag. + */ +#define AT32_ACTIVATE_PLL TRUE +#else +#define AT32_ACTIVATE_PLL FALSE +#endif + +/* HEXT prescaler setting check.*/ +#if (AT32_PLLHEXTDIV != AT32_PLLHEXTDIV_DIV1) && \ + (AT32_PLLHEXTDIV != AT32_PLLHEXTDIV_DIV2) +#error "invalid AT32_PLLHEXTDIV value specified" +#endif + +/** + * @brief PLLMULT field. + */ +#if ((AT32_PLLMULT_VALUE >= 2) && (AT32_PLLMULT_VALUE <= 16)) || \ + defined(__DOXYGEN__) +#define AT32_PLLMULT ((AT32_PLLMULT_VALUE - 2) << 18) +#elif ((AT32_PLLMULT_VALUE >= 17) && (AT32_PLLMULT_VALUE <= 32)) +#define AT32_PLLMULT ((1 << 29) | ((AT32_PLLMULT_VALUE - 17) << 18)) +#elif ((AT32_PLLMULT_VALUE >= 33) && (AT32_PLLMULT_VALUE <= 48)) +#define AT32_PLLMULT ((1 << 30) | ((AT32_PLLMULT_VALUE - 33) << 18)) +#elif ((AT32_PLLMULT_VALUE >= 49) && (AT32_PLLMULT_VALUE <= 64)) +#define AT32_PLLMULT ((3 << 29) | ((AT32_PLLMULT_VALUE - 49) << 18)) +#else +#error "invalid AT32_PLLMULT_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (AT32_PLLRCS == AT32_PLLRCS_HEXT) || defined(__DOXYGEN__) +#if AT32_PLLHEXTDIV == AT32_PLLHEXTDIV_DIV1 || defined(__DOXYGEN__) +#define AT32_PLLRCSCLK (AT32_HEXTCLK / 1) +#else +#define AT32_PLLRCSCLK (AT32_HEXTCLK / 2) +#endif +#elif AT32_PLLRCS == AT32_PLLRCS_HICK +#define AT32_PLLRCSCLK (AT32_HICKCLK / 12) +#else +#error "invalid AT32_PLLRCS value specified" +#endif + +/** + * @brief AT32_PLL_NS field. + */ +#if ((AT32_PLL_NS_VALUE >= 31) && (AT32_PLL_NS_VALUE <= 500)) || \ + defined(__DOXYGEN__) +#define AT32_PLL_NS (AT32_PLL_NS_VALUE << 8) +#else +#error "invalid AT32_PLL_NS_VALUE value specified" +#endif + +/** + * @brief AT32_PLL_MS field. + */ +#if ((AT32_PLL_MS_VALUE >= 1) && (AT32_PLL_MS_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define AT32_PLL_MS (AT32_PLL_MS_VALUE << 4) +#else +#error "invalid AT32_PLL_MS_VALUE value specified" +#endif + +/** + * @brief AT32_PLL_FR field. + */ +#if (AT32_PLL_FR_VALUE == 1) || defined(__DOXYGEN__) +#define AT32_PLL_FR AT32_PLL_FR_DIV1 +#elif AT32_PLL_FR_VALUE == 2 +#define AT32_PLL_FR AT32_PLL_FR_DIV2 +#elif AT32_PLL_FR_VALUE == 4 +#define AT32_PLL_FR AT32_PLL_FR_DIV4 +#elif AT32_PLL_FR_VALUE == 8 +#define AT32_PLL_FR AT32_PLL_FR_DIV8 +#elif AT32_PLL_FR_VALUE == 16 +#define AT32_PLL_FR AT32_PLL_FR_DIV16 +#elif AT32_PLL_FR_VALUE == 32 +#define AT32_PLL_FR AT32_PLL_FR_DIV32 +#else +#error "invalid AT32_PLL_FR_VALUE value specified" +#endif + +/** + * @brief PLL input and output clock frequency. + */ +#if (AT32_PLLCFGEN == AT32_PLLCFGEN_SOLID) || defined(__DOXYGEN__) +#define AT32_PLLCLKIN AT32_PLLRCSCLK +#define AT32_PLLCLKOUT (AT32_PLLCLKIN * AT32_PLLMULT_VALUE) +#elif (AT32_PLLCFGEN == AT32_PLLCFGEN_FLEX) +#define AT32_PLLCLKIN (AT32_PLLRCSCLK / AT32_PLL_MS_VALUE) +#define AT32_PLLFRCLK (AT32_PLLCLKIN * AT32_PLL_NS_VALUE) +#define AT32_PLLCLKOUT (AT32_PLLFRCLK / AT32_PLL_FR_VALUE) + +/* PLL FR frequency range check.*/ +#if (AT32_PLLFRCLK < AT32_PLLFR_MIN) || (AT32_PLLFRCLK > AT32_PLLFR_MAX) +#error "AT32_PLLFRCLK outside acceptable range (AT32_PLLFR_MIN...AT32_PLLFR_MAX)" +#endif +#else +#error "invalid AT32_PLLCFGEN value specified" +#endif + +/* PLL input frequency range check.*/ +#if (AT32_PLLCLKIN < AT32_PLLIN_MIN) || (AT32_PLLCLKIN > AT32_PLLIN_MAX) +#error "AT32_PLLCLKIN outside acceptable range (AT32_PLLIN_MIN...AT32_PLLIN_MAX)" +#endif + +/* PLL output frequency range check.*/ +#if (AT32_PLLCLKOUT < AT32_PLLOUT_MIN) || (AT32_PLLCLKOUT > AT32_PLLOUT_MAX) +#error "AT32_PLLCLKOUT outside acceptable range (AT32_PLLOUT_MIN...AT32_PLLOUT_MAX)" +#endif + +/** + * @brief PLL frequency reference. + */ +#if ((AT32_PLLCLKIN > 3900000) && (AT32_PLLCLKIN < 5000000)) +#define AT32_PLLCLKREF CRM_PLL_PLL_FREF_4M +#elif ((AT32_PLLCLKIN > 5200000) && (AT32_PLLCLKIN < 6250000)) +#define AT32_PLLCLKREF CRM_PLL_PLL_FREF_6M +#elif ((AT32_PLLCLKIN > 7812500) && (AT32_PLLCLKIN < 8330000)) +#define AT32_PLLCLKREF CRM_PLL_PLL_FREF_8M +#elif ((AT32_PLLCLKIN > 8330000) && (AT32_PLLCLKIN < 12500000)) +#define AT32_PLLCLKREF CRM_PLL_PLL_FREF_12M +#elif ((AT32_PLLCLKIN > 15625000) && (AT32_PLLCLKIN < 20830000)) +#define AT32_PLLCLKREF CRM_PLL_PLL_FREF_16M +#elif ((AT32_PLLCLKIN > 20830000) && (AT32_PLLCLKIN < 31255000)) +#define AT32_PLLCLKREF CRM_PLL_PLL_FREF_25M +#endif + +/** + * @brief System clock source. + */ +#if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) || defined(__DOXYGEN__) +#define AT32_SYSCLK AT32_PLLCLKOUT +#elif (AT32_SCLKSEL == AT32_SCLKSEL_HICK) +#define AT32_SYSCLK AT32_HICKCLK +#elif (AT32_SCLKSEL == AT32_SCLKSEL_HEXT) +#define AT32_SYSCLK AT32_HEXTCLK +#else +#error "invalid AT32_SCLKSEL value specified" +#endif + +/* Check on the system clock.*/ +#if AT32_SYSCLK > AT32_SYSCLK_MAX +#error "AT32_SYSCLK exceeding maximum frequency (AT32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (AT32_AHBDIV == AT32_AHBDIV_DIV1) || defined(__DOXYGEN__) +#define AT32_HCLK (AT32_SYSCLK / 1) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV2 +#define AT32_HCLK (AT32_SYSCLK / 2) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV4 +#define AT32_HCLK (AT32_SYSCLK / 4) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV8 +#define AT32_HCLK (AT32_SYSCLK / 8) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV16 +#define AT32_HCLK (AT32_SYSCLK / 16) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV64 +#define AT32_HCLK (AT32_SYSCLK / 64) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV128 +#define AT32_HCLK (AT32_SYSCLK / 128) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV256 +#define AT32_HCLK (AT32_SYSCLK / 256) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV512 +#define AT32_HCLK (AT32_SYSCLK / 512) +#else +#error "invalid AT32_AHBDIV value specified" +#endif + +/* AHB frequency check.*/ +#if AT32_HCLK > AT32_SYSCLK_MAX +#error "AT32_HCLK exceeding maximum frequency (AT32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (AT32_APB1DIV == AT32_APB1DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_PCLK1 (AT32_HCLK / 1) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV2 +#define AT32_PCLK1 (AT32_HCLK / 2) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV4 +#define AT32_PCLK1 (AT32_HCLK / 4) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV8 +#define AT32_PCLK1 (AT32_HCLK / 8) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV16 +#define AT32_PCLK1 (AT32_HCLK / 16) +#else +#error "invalid AT32_APB1DIV value specified" +#endif + +/* APB1 frequency check.*/ +#if AT32_PCLK1 > AT32_PCLK1_MAX +#error "AT32_PCLK1 exceeding maximum frequency (AT32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (AT32_APB2DIV == AT32_APB2DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_PCLK2 (AT32_HCLK / 1) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV2 +#define AT32_PCLK2 (AT32_HCLK / 2) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV4 +#define AT32_PCLK2 (AT32_HCLK / 4) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV8 +#define AT32_PCLK2 (AT32_HCLK / 8) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV16 +#define AT32_PCLK2 (AT32_HCLK / 16) +#else +#error "invalid AT32_APB2DIV value specified" +#endif + +/* APB2 frequency check.*/ +#if AT32_PCLK2 > AT32_PCLK2_MAX +#error "AT32_PCLK2 exceeding maximum frequency (AT32_PCLK2_MAX)" +#endif + +/** + * @brief ERTC clock. + */ +#if (AT32_ERTCSEL == AT32_ERTCSEL_LEXT) || defined(__DOXYGEN__) +#define AT32_ERTCCLK AT32_LEXTCLK +#elif AT32_ERTCSEL == AT32_ERTCSEL_LICK +#define AT32_ERTCCLK AT32_LICKCLK +#elif AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV +#define AT32_ERTCCLK (AT32_HEXTCLK / 128) +#elif AT32_ERTCSEL == AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCCLK 0 +#else +#error "invalid source selected for ERTC clock" +#endif + +/** + * @brief ADC frequency. + */ +#if (AT32_ADCDIV == AT32_ADCDIV_DIV2) || defined(__DOXYGEN__) +#define AT32_ADCCLK (AT32_PCLK2 / 2) +#elif AT32_ADCDIV == AT32_ADCDIV_DIV4 +#define AT32_ADCCLK (AT32_PCLK2 / 4) +#elif AT32_ADCDIV == AT32_ADCDIV_DIV6 +#define AT32_ADCCLK (AT32_PCLK2 / 6) +#elif AT32_ADCDIV == AT32_ADCDIV_DIV8 +#define AT32_ADCCLK (AT32_PCLK2 / 8) +#elif AT32_ADCDIV == AT32_ADCDIV_DIV12 +#define AT32_ADCCLK (AT32_PCLK2 / 12) +#elif AT32_ADCDIV == AT32_ADCDIV_DIV16 +#define AT32_ADCCLK (AT32_PCLK2 / 16) +#else +#error "invalid AT32_ADCDIV value specified" +#endif + +/* ADC frequency check.*/ +#if AT32_ADCCLK > AT32_ADCCLK_MAX +#error "AT32_ADCCLK exceeding maximum frequency (AT32_ADCCLK_MAX)" +#endif + +/** + * @brief USB frequency. + */ +#if (AT32_USBDIV == AT32_USBDIV_DIV1P5) || defined(__DOXYGEN__) +#define AT32_USBCLK ((AT32_PLLCLKOUT * 2) / 3) +#elif (AT32_USBDIV == AT32_USBDIV_DIV1) +#define AT32_USBCLK AT32_PLLCLKOUT +#elif (AT32_USBDIV == AT32_USBDIV_DIV2P5) +#define AT32_USBCLK ((AT32_PLLCLKOUT * 2) / 5) +#elif (AT32_USBDIV == AT32_USBDIV_DIV2) +#define AT32_USBCLK (AT32_PLLCLKOUT / 2) +#elif (AT32_USBDIV == AT32_USBDIV_DIV3P5) +#define AT32_USBCLK ((AT32_PLLCLKOUT * 2) / 7) +#elif (AT32_USBDIV == AT32_USBDIV_DIV3) +#define AT32_USBCLK (AT32_PLLCLKOUT / 3) +#elif (AT32_USBDIV == AT32_USBDIV_DIV4) +#define AT32_USBCLK (AT32_PLLCLKOUT / 4) +#else +#error "invalid AT32_USBDIV value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 5 clock. + */ +#if (AT32_APB1DIV == AT32_APB1DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_TMRCLK1 (AT32_PCLK1 * 1) +#else +#define AT32_TMRCLK1 (AT32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 9, 10, 11 clock. + */ +#if (AT32_APB2DIV == AT32_APB2DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_TMRCLK2 (AT32_PCLK2 * 1) +#else +#define AT32_TMRCLK2 (AT32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (AT32_HCLK <= 32000000) || defined(__DOXYGEN__) +#define AT32_FLASHBITS 0x00000010 +#elif (AT32_HCLK <= 64000000) +#define AT32_FLASHBITS 0x00000011 +#elif (AT32_HCLK <= 96000000) +#define AT32_FLASHBITS 0x00000012 +#elif (AT32_HCLK <= 128000000) +#define AT32_FLASHBITS 0x00000013 +#elif (AT32_HCLK <= 150000000) +#define AT32_FLASHBITS 0x00000014 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" +#include "at32_crm.h" +#include "at32_dma.h" +#include "at32_exint.h" +#include "at32_isr.h" +#include "at32_tmr.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void at32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/platform.mk b/os/hal/ports/AT32/AT32F415/platform.mk new file mode 100644 index 0000000000..bf897f7dd7 --- /dev/null +++ b/os/hal/ports/AT32/AT32F415/platform.mk @@ -0,0 +1,42 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/at32_isr.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/hal_lld.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/hal_efl_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415 + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) +endif + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/DMAv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/EXINTv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/GPIOv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/RTCv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/xWDGv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/AT32/LLD/ADCv1/driver.mk b/os/hal/ports/AT32/LLD/ADCv1/driver.mk new file mode 100644 index 0000000000..bd3dff296b --- /dev/null +++ b/os/hal/ports/AT32/LLD/ADCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/ADCv1 diff --git a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c new file mode 100644 index 0000000000..0f42b0a5ed --- /dev/null +++ b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c @@ -0,0 +1,242 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADCv1/hal_adc_lld.c + * @brief AT32 ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if AT32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the STS register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & AT32_DMA_STS_DTERRF) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + if ((flags & AT32_DMA_STS_FDTF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + else if ((flags & AT32_DMA_STS_HDTF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if AT32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = NULL; + ADCD1.dmamode = AT32_DMA_CCTRL_CHPL(AT32_ADC_ADC1_DMA_PRIORITY) | + AT32_DMA_CCTRL_MWIDTH_HWORD | AT32_DMA_CCTRL_PWIDTH_HWORD | + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + + /* Temporary activation.*/ + crmEnableADC1(true); + ADC1->CTRL1 = 0; + ADC1->CTRL2 = ADC_CTRL2_ADCEN; + + /* Reset calibration just to be safe.*/ + ADC1->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCALINIT; + while ((ADC1->CTRL2 & ADC_CTRL2_ADCALINIT) != 0) + ; + + /* Calibration.*/ + ADC1->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCAL; + while ((ADC1->CTRL2 & ADC_CTRL2_ADCAL) != 0) + ; + + /* Return the ADC in low power mode.*/ + ADC1->CTRL2 = 0; + crmDisableADC1(); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if AT32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + adcp->dmastp = dmaStreamAllocI(AT32_ADC_ADC1_DMA_STREAM, + AT32_ADC_ADC1_IRQ_PRIORITY, + (at32_dmasts_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(adcp->dmastp, AT32_ADC_ADC1_DMAMUX_CHANNEL, AT32_DMAMUX_ADC1); +#endif + + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->ODT); + crmEnableADC1(true); + } +#endif + + /* ADC setup, the calibration procedure has already been performed + during initialization.*/ + adcp->adc->CTRL1 = 0; + adcp->adc->CTRL2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if AT32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CTRL1 = 0; + ADC1->CTRL2 = 0; + + dmaStreamFreeI(adcp->dmastp); + adcp->dmastp = NULL; + + crmDisableADC1(); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode, ctrl2; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= AT32_DMA_CCTRL_LM; + if (adcp->depth > 1) { + /* If circular buffer depth > 1, then the half transfer interrupt + is enabled in order to allow streaming processing.*/ + mode |= AT32_DMA_CCTRL_HDTIEN; + } + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->CTRL1 = grpp->ctrl1 | ADC_CTRL1_SQEN; + ctrl2 = grpp->ctrl2 | ADC_CTRL2_OCDMAEN | ADC_CTRL2_ADCEN; + if ((ctrl2 & (ADC_CTRL2_OCTEN | ADC_CTRL2_PCTEN)) == 0) + ctrl2 |= ADC_CTRL2_RPEN; + adcp->adc->CTRL2 = grpp->ctrl2 | ctrl2; + adcp->adc->SPT1 = grpp->spt1; + adcp->adc->SPT2 = grpp->spt2; + adcp->adc->OSQ1 = grpp->osq1; + adcp->adc->OSQ2 = grpp->osq2; + adcp->adc->OSQ3 = grpp->osq3; + + /* ADC start by writing ADC_CTRL2_ADCEN a second time.*/ + adcp->adc->CTRL2 = ctrl2; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CTRL2 = 0; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h new file mode 100644 index 0000000000..a54d9b8988 --- /dev/null +++ b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h @@ -0,0 +1,286 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADCv1/hal_adc_lld.h + * @brief AT32 ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef HAL_ADC_LLD_H +#define HAL_ADC_LLD_H + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CTRL2_OCTESEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CTRL2_OCTESEL_OCSWTRG (7 << 17) /**< @brief Software trigger. */ +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREF 17 /**< @brief Internal reference. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(AT32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define AT32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(AT32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(AT32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if AT32_ADC_USE_ADC1 && !AT32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !AT32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(AT32_DMA_REQUIRED) +#define AT32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ +} adcerror_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the ADC driver structure. + */ +#define adc_lld_driver_fields \ + /* Pointer to the ADCx registers block.*/ \ + ADC_TypeDef *adc; \ + /* Pointer to associated DMA channel.*/ \ + const at32_dma_stream_t *dmastp; \ + /* DMA mode bit mask.*/ \ + uint32_t dmamode + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_configuration_group_fields \ + /* ADC CTRL1 register initialization data. \ + NOTE: All the required bits must be defined into this field except \ + @p ADC_CTRL1_SQEN that is enforced inside the driver.*/ \ + uint32_t ctrl1; \ + /* ADC CTRL2 register initialization data. \ + NOTE: All the required bits must be defined into this field except \ + @p ADC_CTRL2_OCDMAEN, @p ADC_CTRL2_RPEN and @p ADC_CTRL2_ADCEN \ + that are enforced inside the driver.*/ \ + uint32_t ctrl2; \ + /* ADC SPT1 register initialization data. \ + NOTE: In this field must be specified the sample times for channels \ + 10...17.*/ \ + uint32_t spt1; \ + /* ADC SPT2 register initialization data. \ + NOTE: In this field must be specified the sample times for channels \ + 0...9.*/ \ + uint32_t spt2; \ + /* ADC OSQ1 register initialization data. \ + NOTE: Conversion group sequence 13...16 + sequence length.*/ \ + uint32_t osq1; \ + /* ADC OSQ2 register initialization data. \ + NOTE: Conversion group sequence 7...12.*/ \ + uint32_t osq2; \ + /* ADC OSQ3 register initialization data. \ + NOTE: Conversion group sequence 1...6.*/ \ + uint32_t osq3 + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_OSQ1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_OSQ3_OSN1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_OSQ3_OSN2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_OSQ3_OSN3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_OSQ3_OSN4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_OSQ3_OSN5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_OSQ3_OSN6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_OSQ2_OSN7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_OSQ2_OSN8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_OSQ2_OSN9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_OSQ2_OSN10_N(n) ((n) << 15) /**< @brief 10th channel in seq. */ +#define ADC_OSQ2_OSN11_N(n) ((n) << 20) /**< @brief 11th channel in seq. */ +#define ADC_OSQ2_OSN12_N(n) ((n) << 25) /**< @brief 12th channel in seq. */ + +#define ADC_OSQ1_OSN13_N(n) ((n) << 0) /**< @brief 13th channel in seq. */ +#define ADC_OSQ1_OSN14_N(n) ((n) << 5) /**< @brief 14th channel in seq. */ +#define ADC_OSQ1_OSN15_N(n) ((n) << 10) /**< @brief 15th channel in seq. */ +#define ADC_OSQ1_OSN16_N(n) ((n) << 15) /**< @brief 16th channel in seq. */ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SPT2_CSPT_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SPT2_CSPT_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SPT2_CSPT_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SPT2_CSPT_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SPT2_CSPT_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SPT2_CSPT_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SPT2_CSPT_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SPT2_CSPT_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SPT2_CSPT_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SPT2_CSPT_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SPT1_CSPT_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SPT1_CSPT_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SPT1_CSPT_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SPT1_CSPT_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SPT1_CSPT_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SPT1_CSPT_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SPT1_CSPT_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SPT1_CSPT_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* HAL_ADC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c new file mode 100644 index 0000000000..be862b066b --- /dev/null +++ b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c @@ -0,0 +1,692 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DMAv1/at32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup AT32_DMA + * @details DMA sharing helper driver. In the AT32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA STS handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * STSs when allocating streams. + * @{ + */ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(AT32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define AT32_DMA1_STREAMS_MASK ((1U << AT32_DMA1_NUM_CHANNELS) - 1U) + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define AT32_DMA2_STREAMS_MASK (((1U << AT32_DMA2_NUM_CHANNELS) - \ + 1U) << AT32_DMA1_NUM_CHANNELS) + +#define DMA1_CH1_VARIANT 0 +#define DMA1_CH2_VARIANT 0 +#define DMA1_CH3_VARIANT 0 +#define DMA1_CH4_VARIANT 0 +#define DMA1_CH5_VARIANT 0 +#define DMA1_CH6_VARIANT 0 +#define DMA1_CH7_VARIANT 0 +#define DMA2_CH1_VARIANT 0 +#define DMA2_CH2_VARIANT 0 +#define DMA2_CH3_VARIANT 0 +#define DMA2_CH4_VARIANT 0 +#define DMA2_CH5_VARIANT 0 +#define DMA2_CH6_VARIANT 0 +#define DMA2_CH7_VARIANT 0 + +/* + * Default STS collision masks. + */ +#if !defined(AT32_DMA1_CH1_CMASK) +#define AT32_DMA1_CH1_CMASK (1U << 0U) +#endif + +#if !defined(AT32_DMA1_CH2_CMASK) +#define AT32_DMA1_CH2_CMASK (1U << 1U) +#endif + +#if !defined(AT32_DMA1_CH3_CMASK) +#define AT32_DMA1_CH3_CMASK (1U << 2U) +#endif + +#if !defined(AT32_DMA1_CH4_CMASK) +#define AT32_DMA1_CH4_CMASK (1U << 3U) +#endif + +#if !defined(AT32_DMA1_CH5_CMASK) +#define AT32_DMA1_CH5_CMASK (1U << 4U) +#endif + +#if !defined(AT32_DMA1_CH6_CMASK) +#define AT32_DMA1_CH6_CMASK (1U << 5U) +#endif + +#if !defined(AT32_DMA1_CH7_CMASK) +#define AT32_DMA1_CH7_CMASK (1U << 6U) +#endif + +#if !defined(AT32_DMA2_CH1_CMASK) +#define AT32_DMA2_CH1_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 0U)) +#endif + +#if !defined(AT32_DMA2_CH2_CMASK) +#define AT32_DMA2_CH2_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 1U)) +#endif + +#if !defined(AT32_DMA2_CH3_CMASK) +#define AT32_DMA2_CH3_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 2U)) +#endif + +#if !defined(AT32_DMA2_CH4_CMASK) +#define AT32_DMA2_CH4_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 3U)) +#endif + +#if !defined(AT32_DMA2_CH5_CMASK) +#define AT32_DMA2_CH5_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 4U)) +#endif + +#if !defined(AT32_DMA2_CH6_CMASK) +#define AT32_DMA2_CH6_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 5U)) +#endif + +#if !defined(AT32_DMA2_CH7_CMASK) +#define AT32_DMA2_CH7_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 6U)) +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p AT32_DMA1_STREAM1, @p AT32_DMA1_STREAM2 etc. + */ +const at32_dma_stream_t _at32_dma_streams[AT32_DMA_STREAMS] = { +#if AT32_DMA1_NUM_CHANNELS > 0 + {DMA1, DMA1_Channel1, AT32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 0, 0, AT32_DMA1_CH1_NUMBER}, +#endif +#if AT32_DMA1_NUM_CHANNELS > 1 + {DMA1, DMA1_Channel2, AT32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 4, 1, AT32_DMA1_CH2_NUMBER}, +#endif +#if AT32_DMA1_NUM_CHANNELS > 2 + {DMA1, DMA1_Channel3, AT32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 8, 2, AT32_DMA1_CH3_NUMBER}, +#endif +#if AT32_DMA1_NUM_CHANNELS > 3 + {DMA1, DMA1_Channel4, AT32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 12, 3, AT32_DMA1_CH4_NUMBER}, +#endif +#if AT32_DMA1_NUM_CHANNELS > 4 + {DMA1, DMA1_Channel5, AT32_DMA1_CH5_CMASK, DMA1_CH5_VARIANT, 16, 4, AT32_DMA1_CH5_NUMBER}, +#endif +#if AT32_DMA1_NUM_CHANNELS > 5 + {DMA1, DMA1_Channel6, AT32_DMA1_CH6_CMASK, DMA1_CH6_VARIANT, 20, 5, AT32_DMA1_CH6_NUMBER}, +#endif +#if AT32_DMA1_NUM_CHANNELS > 6 + {DMA1, DMA1_Channel7, AT32_DMA1_CH7_CMASK, DMA1_CH7_VARIANT, 24, 6, AT32_DMA1_CH7_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 0 + {DMA2, DMA2_Channel1, AT32_DMA2_CH1_CMASK, DMA2_CH1_VARIANT, 0, 0 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH1_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 1 + {DMA2, DMA2_Channel2, AT32_DMA2_CH2_CMASK, DMA2_CH2_VARIANT, 4, 1 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH2_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 2 + {DMA2, DMA2_Channel3, AT32_DMA2_CH3_CMASK, DMA2_CH3_VARIANT, 8, 2 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH3_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 3 + {DMA2, DMA2_Channel4, AT32_DMA2_CH4_CMASK, DMA2_CH4_VARIANT, 12, 3 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH4_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 4 + {DMA2, DMA2_Channel5, AT32_DMA2_CH5_CMASK, DMA2_CH5_VARIANT, 16, 4 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH5_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 5 + {DMA2, DMA2_Channel6, AT32_DMA2_CH6_CMASK, DMA2_CH6_VARIANT, 20, 5 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH6_NUMBER}, +#endif +#if AT32_DMA2_NUM_CHANNELS > 6 + {DMA2, DMA2_Channel7, AT32_DMA2_CH7_CMASK, DMA2_CH7_VARIANT, 24, 6 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH7_NUMBER}, +#endif +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Global DMA-related data structures. + */ +static struct { + /** + * @brief Mask of the allocated streams. + */ + uint32_t allocated_mask; + /** + * @brief Mask of the enabled streams STSs. + */ + uint32_t sts_mask; + /** + * @brief DMA IRQ redirectors. + */ + struct { + /** + * @brief DMA callback function. + */ + at32_dmasts_t func; + /** + * @brief DMA callback parameter. + */ + void *param; + } streams[AT32_DMA_STREAMS]; +} dma; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA1_CH7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA1_STREAM7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 6 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 7 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_DMA2_CH7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(AT32_DMA2_STREAM7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AT32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma.allocated_mask = 0U; + dma.sts_mask = 0U; + for (i = 0; i < AT32_DMA_STREAMS; i++) { + _at32_dma_streams[i].channel->CCTRL = AT32_DMA_CCTRL_RESET_VALUE; + dma.streams[i].func = NULL; + } + DMA1->CLR = 0xFFFFFFFFU; +#if AT32_DMA2_NUM_CHANNELS > 0 + DMA2->CLR = 0xFFFFFFFFU; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * + * @param[in] id numeric identifiers of a specific stream or: + * - @p AT32_DMA_STREAM_ID_ANY for any stream. + * - @p AT32_DMA_STREAM_ID_ANY_DMA1 for any stream + * on DMA1. + * - @p AT32_DMA_STREAM_ID_ANY_DMA2 for any stream + * on DMA2. + * . + * @param[in] priority IRQ priority for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return Pointer to the allocated @p at32_dma_stream_t + * structure. + * @retval NULL if a/the stream is not available. + * + * @iclass + */ +const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, + uint32_t priority, + at32_dmasts_t func, + void *param) { + uint32_t i, startid, endid; + + osalDbgCheckClassI(); + + if (id < AT32_DMA_STREAMS) { + startid = id; + endid = id; + } + else { + osalDbgCheck(false); + return NULL; + } + + for (i = startid; i <= endid; i++) { + uint32_t mask = (1U << i); + if ((dma.allocated_mask & mask) == 0U) { + const at32_dma_stream_t *dmastp = AT32_DMA_STREAM(i); + + /* Installs the DMA handler.*/ + dma.streams[i].func = func; + dma.streams[i].param = param; + dma.allocated_mask |= mask; + + /* Enabling DMA clocks required by the current streams set.*/ + if ((AT32_DMA1_STREAMS_MASK & mask) != 0U) { + crmEnableDMA1(true); + } +#if AT32_DMA2_NUM_CHANNELS > 0 + if ((AT32_DMA2_STREAMS_MASK & mask) != 0U) { + crmEnableDMA2(true); + } +#endif + + /* Enables the associated IRQ vector if not already enabled and if a + callback is defined.*/ + if (func != NULL) { + if ((dma.sts_mask & dmastp->cmask) == 0U) { + nvicEnableVector(dmastp->vector, priority); + } + dma.sts_mask |= mask; + } + + /* Putting the stream in a known state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCTRL = AT32_DMA_CCTRL_RESET_VALUE; + + return dmastp; + } + } + + return NULL; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * + * @param[in] id numeric identifiers of a specific stream or: + * - @p AT32_DMA_STREAM_ID_ANY for any stream. + * - @p AT32_DMA_STREAM_ID_ANY_DMA1 for any stream + * on DMA1. + * - @p AT32_DMA_STREAM_ID_ANY_DMA2 for any stream + * on DMA2. + * . + * @param[in] priority IRQ priority for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return Pointer to the allocated @p at32_dma_stream_t + * structure. + * @retval NULL if a/the stream is not available. + * + * @api + */ +const at32_dma_stream_t *dmaStreamAlloc(uint32_t id, + uint32_t priority, + at32_dmasts_t func, + void *param) { + const at32_dma_stream_t *dmastp; + + osalSysLock(); + dmastp = dmaStreamAllocI(id, priority, func, param); + osalSysUnlock(); + + return dmastp; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * + * @iclass + */ +void dmaStreamFreeI(const at32_dma_stream_t *dmastp) { + uint32_t selfindex = (uint32_t)dmastp->selfindex; + + osalDbgCheck(dmastp != NULL); + + /* Check if the streams is not taken.*/ + osalDbgAssert((dma.allocated_mask & (1 << selfindex)) != 0U, + "not allocated"); + + /* Marks the stream as not allocated.*/ + dma.allocated_mask &= ~(1U << selfindex); + dma.sts_mask &= ~(1U << selfindex); + + /* Disables the associated IRQ vector if it is no more in use.*/ + if ((dma.sts_mask & dmastp->cmask) == 0U) { + nvicDisableVector(dmastp->vector); + } + + /* Removes the DMA handler.*/ + dma.streams[selfindex].func = NULL; + dma.streams[selfindex].param = NULL; + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma.allocated_mask & AT32_DMA1_STREAMS_MASK) == 0U) { + crmDisableDMA1(); + } +#if AT32_DMA2_NUM_CHANNELS > 0 + if ((dma.allocated_mask & AT32_DMA2_STREAMS_MASK) == 0U) { + crmDisableDMA2(); + } +#endif +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * + * @api + */ +void dmaStreamFree(const at32_dma_stream_t *dmastp) { + + osalSysLock(); + dmaStreamFreeI(dmastp); + osalSysUnlock(); +} + +/** + * @brief Serves a DMA IRQ. + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * + * @special + */ +void dmaServeInterrupt(const at32_dma_stream_t *dmastp) { + uint32_t flags; + uint32_t selfindex = (uint32_t)dmastp->selfindex; + + flags = (dmastp->dma->STS >> dmastp->shift) & AT32_DMA_STS_MASK; + if (flags & dmastp->channel->CCTRL) { + dmastp->dma->CLR = flags << dmastp->shift; + if (dma.streams[selfindex].func) { + dma.streams[selfindex].func(dma.streams[selfindex].param, flags); + } + } +} + +#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__) +/** + * @brief Associates a peripheral request to a DMA stream. + * @note This function can be invoked in both STS or thread context. + * + * @param[in] dmastp pointer to a @p at32_dma_stream_t structure + * @param[in] channel channel to use + * @param[in] per peripheral identifier + * + * @special + */ +void dmaSetRequestSource(const at32_dma_stream_t *dmastp, uint32_t channel, uint32_t per) { + + osalDbgCheck(per < 256U); + + dmastp->dma->SRC_SEL1 |= DMA_SRC_SEL1_DMA_FLEX_EN; + if (channel < 5) { + dmastp->dma->SRC_SEL0 |= (per << ((channel - 1) * 8)); + } else { + dmastp->dma->SRC_SEL1 |= (per << ((channel - 5) * 8)); + } +} +#endif + +#endif /* AT32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h new file mode 100644 index 0000000000..c09aecee36 --- /dev/null +++ b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h @@ -0,0 +1,442 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DMAv1/at32_dma.h + * @brief DMA helper driver header. + * + * @addtogroup AT32_DMA + * @{ + */ + +#ifndef AT32_DMA_H +#define AT32_DMA_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief DMA capability. + * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, + * scatter gather and other advanced features. + */ +#define AT32_DMA_ADVANCED FALSE + +/** + * @brief Maximum number of transfers in a single operation. + */ +#define AT32_DMA_MAX_TRANSFER 65535 + +/** + * @brief Total number of DMA streams. + * @details This is the total number of streams among all the DMA units. + */ +#define AT32_DMA_STREAMS (AT32_DMA1_NUM_CHANNELS + \ + AT32_DMA2_NUM_CHANNELS) + +/** + * @brief Mask of the STS bits passed to the DMA callback functions. + */ +#define AT32_DMA_STS_MASK 0x0E + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval false invalid DMA priority. + * @retval true correct DMA priority. + */ +#define AT32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define AT32_DMA_STREAM_ID(dma, stream) \ + ((((dma) - 1) * AT32_DMA1_NUM_CHANNELS) + ((stream) - 1)) + +/** + * @name DMA streams identifiers + * @{ + */ +/** + * @brief Returns a pointer to a at32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the at32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define AT32_DMA_STREAM(id) (&_at32_dma_streams[id]) + +#if AT32_DMA1_NUM_CHANNELS > 0 +#define AT32_DMA1_STREAM1 AT32_DMA_STREAM(0) +#endif +#if AT32_DMA1_NUM_CHANNELS > 1 +#define AT32_DMA1_STREAM2 AT32_DMA_STREAM(1) +#endif +#if AT32_DMA1_NUM_CHANNELS > 2 +#define AT32_DMA1_STREAM3 AT32_DMA_STREAM(2) +#endif +#if AT32_DMA1_NUM_CHANNELS > 3 +#define AT32_DMA1_STREAM4 AT32_DMA_STREAM(3) +#endif +#if AT32_DMA1_NUM_CHANNELS > 4 +#define AT32_DMA1_STREAM5 AT32_DMA_STREAM(4) +#endif +#if AT32_DMA1_NUM_CHANNELS > 5 +#define AT32_DMA1_STREAM6 AT32_DMA_STREAM(5) +#endif +#if AT32_DMA1_NUM_CHANNELS > 6 +#define AT32_DMA1_STREAM7 AT32_DMA_STREAM(6) +#endif +#if AT32_DMA2_NUM_CHANNELS > 0 +#define AT32_DMA2_STREAM1 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 0) +#endif +#if AT32_DMA2_NUM_CHANNELS > 1 +#define AT32_DMA2_STREAM2 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 1) +#endif +#if AT32_DMA2_NUM_CHANNELS > 2 +#define AT32_DMA2_STREAM3 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 2) +#endif +#if AT32_DMA2_NUM_CHANNELS > 3 +#define AT32_DMA2_STREAM4 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 3) +#endif +#if AT32_DMA2_NUM_CHANNELS > 4 +#define AT32_DMA2_STREAM5 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 4) +#endif +#if AT32_DMA2_NUM_CHANNELS > 5 +#define AT32_DMA2_STREAM6 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 5) +#endif +#if AT32_DMA2_NUM_CHANNELS > 6 +#define AT32_DMA2_STREAM7 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 6) +#endif +/** @} */ + +/** + * @name CCTRL register constants common to all DMA types + * @{ + */ +#define AT32_DMA_CCTRL_RESET_VALUE 0x00000000U +#define AT32_DMA_CCTRL_CHEN DMA_CCTRL_CHEN +#define AT32_DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN +#define AT32_DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN +#define AT32_DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN +#define AT32_DMA_CCTRL_DTD_MASK (DMA_CCTRL_DTD | DMA_CCTRL_M2M) +#define AT32_DMA_CCTRL_DTD_P2M 0U +#define AT32_DMA_CCTRL_DTD_M2P DMA_CCTRL_DTD +#define AT32_DMA_CCTRL_DTD_M2M DMA_CCTRL_M2M +#define AT32_DMA_CCTRL_LM DMA_CCTRL_LM +#define AT32_DMA_CCTRL_PINCM DMA_CCTRL_PINCM +#define AT32_DMA_CCTRL_MINCM DMA_CCTRL_MINCM +#define AT32_DMA_CCTRL_PWIDTH_MASK DMA_CCTRL_PWIDTH +#define AT32_DMA_CCTRL_PWIDTH_BYTE 0U +#define AT32_DMA_CCTRL_PWIDTH_HWORD DMA_CCTRL_PWIDTH_0 +#define AT32_DMA_CCTRL_PWIDTH_WORD DMA_CCTRL_PWIDTH_1 +#define AT32_DMA_CCTRL_MWIDTH_MASK DMA_CCTRL_MWIDTH +#define AT32_DMA_CCTRL_MWIDTH_BYTE 0U +#define AT32_DMA_CCTRL_MWIDTH_HWORD DMA_CCTRL_MWIDTH_0 +#define AT32_DMA_CCTRL_MWIDTH_WORD DMA_CCTRL_MWIDTH_1 +#define AT32_DMA_CCTRL_SIZE_MASK (AT32_DMA_CCTRL_PWIDTH_MASK | \ + AT32_DMA_CCTRL_MWIDTH_MASK) +#define AT32_DMA_CCTRL_CHPL_MASK DMA_CCTRL_CHPL +#define AT32_DMA_CCTRL_CHPL(n) ((n) << 12U) +/** @} */ + +/** + * @name Status flags passed to the STS callbacks + * @{ + */ +#define AT32_DMA_STS_DTERRF DMA_STS_DTERRF1 +#define AT32_DMA_STS_HDTF DMA_STS_HDTF1 +#define AT32_DMA_STS_FDTF DMA_STS_FDTF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(AT32_DMA_SUPPORTS_DMAMUX) +#error "AT32_DMA_SUPPORTS_DMAMUX not defined in registry" +#endif + +#if !defined(AT32_DMA1_NUM_CHANNELS) +#error "AT32_DMA1_NUM_CHANNELS not defined in registry" +#endif + +#if !defined(AT32_DMA2_NUM_CHANNELS) +#error "AT32_DMA2_NUM_CHANNELS not defined in registry" +#endif + +#if (AT32_DMA1_NUM_CHANNELS < 0) || (AT32_DMA1_NUM_CHANNELS > 7) +#error "unsupported channels configuration" +#endif + +#if (AT32_DMA2_NUM_CHANNELS < 0) || (AT32_DMA2_NUM_CHANNELS > 7) +#error "unsupported channels configuration" +#endif + +#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__) +#include "at32_dmamux.h" +#endif + +#if !defined(AT32_DMA_USE_DMAMUX) || defined(__DOXYGEN__) +#define AT32_DMA_USE_DMAMUX FALSE +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a DMA callback. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the STS register, the bits + * are aligned to bit zero + */ +typedef void (*at32_dmasts_t)(void *p, uint32_t flags); + +/** + * @brief AT32 DMA stream descriptor structure. + */ +typedef struct { + DMA_TypeDef *dma; /**< @brief Associated DMA. */ + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + uint32_t cmask; /**< @brief Mask of streams sharing + the same STS. */ + uint8_t dummy; /**< @brief Filler. */ + uint8_t shift; /**< @brief Bit offset in STS, CLR */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} at32_dma_stream_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * @param[in] addr value to be written in the CPADDR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPADDR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * @param[in] addr value to be written in the CMADDR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMADDR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * @param[in] size value to be written in the CDTCNT register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CDTCNT = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CDTCNT)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * @param[in] mode value to be written in the CCTRL register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCTRL = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCTRL |= AT32_DMA_CCTRL_CHEN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCTRL &= ~(AT32_DMA_CCTRL_FDTIEN | \ + AT32_DMA_CCTRL_HDTIEN | \ + AT32_DMA_CCTRL_DTERRIEN | \ + AT32_DMA_CCTRL_CHEN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + (dmastp)->dma->CLR = AT32_DMA_STS_MASK << (dmastp)->shift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + * @param[in] mode value to be written in the CCTRL register, this value + * is implicitly ORed with: + * - @p AT32_DMA_CCTRL_MINCM + * - @p AT32_DMA_CCTRL_PINCM + * - @p AT32_DMA_CCTRL_DTD_M2M + * - @p AT32_DMA_CCTRL_CHEN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_PINCM | \ + AT32_DMA_CCTRL_DTD_M2M | AT32_DMA_CCTRL_CHEN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAlloc(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a at32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CDTCNT > 0U) \ + ; \ + dmaStreamDisable(dmastp); \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const at32_dma_stream_t _at32_dma_streams[AT32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, + uint32_t priority, + at32_dmasts_t func, + void *param); + const at32_dma_stream_t *dmaStreamAlloc(uint32_t id, + uint32_t priority, + at32_dmasts_t func, + void *param); + void dmaStreamFreeI(const at32_dma_stream_t *dmastp); + void dmaStreamFree(const at32_dma_stream_t *dmastp); + void dmaServeInterrupt(const at32_dma_stream_t *dmastp); +#if AT32_DMA_SUPPORTS_DMAMUX == TRUE + void dmaSetRequestSource(const at32_dma_stream_t *dmastp, uint32_t channel, uint32_t per); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* AT32_DMA_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/DMAv1/driver.mk b/os/hal/ports/AT32/LLD/DMAv1/driver.mk new file mode 100644 index 0000000000..9508cbf0bd --- /dev/null +++ b/os/hal/ports/AT32/LLD/DMAv1/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/DMAv1 diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c new file mode 100644 index 0000000000..562d860d33 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c @@ -0,0 +1,141 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint.c + * @brief EXINT helper driver code. + * + * @addtogroup AT32_EXINT + * @details EXINT sharing helper driver. + * @{ + */ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring EXINT services + has been enabled.*/ +#if defined(AT32_EXINT_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AT32 EXINT group 1 lines initialization. + * + * @param[in] mask mask of group 1 lines to be initialized + * @param[in] mode initialization mode + * + * @api + */ +void exintEnableGroup1(uint32_t mask, exintmode_t mode) { + uint32_t cmask; + + /* Mask including only configurable lines.*/ + cmask = mask & ~AT32_EXINT_INTEN_MASK; + + if ((mode & EXINT_MODE_EDGES_MASK) == 0U) { + /* Disabling channels.*/ + EXINT->INTEN &= ~mask; + EXINT->EVTEN &= ~mask; + EXINT->POLCFG1 &= ~cmask; + EXINT->POLCFG2 &= ~cmask; + EXINT->INTSTS = cmask; + } + else { + /* Programming edge registers.*/ + if (mode & EXINT_MODE_RISING_EDGE) { + EXINT->POLCFG1 |= cmask; + } + else { + EXINT->POLCFG1 &= ~cmask; + } + if (mode & EXINT_MODE_FALLING_EDGE) { + EXINT->POLCFG2 |= cmask; + } + else { + EXINT->POLCFG2 &= ~cmask; + } + + /* Programming interrupt and event registers.*/ + if ((mode & EXINT_MODE_ACTION_MASK) == EXINT_MODE_ACTION_INTERRUPT) { + EXINT->INTEN |= mask; + EXINT->EVTEN &= ~mask; + } + else { + EXINT->EVTEN |= mask; + EXINT->INTEN &= ~mask; + } + } +} + +/** + * @brief AT32 EXINT line initialization. + * + * @param[in] line line to be initialized + * @param[in] mode initialization mode + * + * @api + */ +void exintEnableLine(exintline_t line, exintmode_t mode) { + uint32_t mask = (1U << (line & 0x1FU)); + + osalDbgCheck(line < AT32_EXINT_NUM_LINES); + osalDbgCheck((mode & ~EXINT_MODE_MASK) == 0U); + + exintEnableGroup1(mask, mode); +} + +/** + * @brief AT32 EXINT line IRQ status clearing. + * + * @param[in] line line to be initialized + * + * @api + */ +void exintClearLine(exintline_t line) { + uint32_t mask = (1U << (line & 0x1FU)); + + osalDbgCheck(line < AT32_EXINT_NUM_LINES); + + exintClearGroup1(mask); +} + +#endif /* AT32_EXINT_REQUIRED */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h new file mode 100644 index 0000000000..138f14fdbc --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h @@ -0,0 +1,138 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint.h + * @brief EXINT helper driver header. + * + * @addtogroup AT32_EXINT + * @{ + */ + +#ifndef AT32_EXINT_H +#define AT32_EXINT_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name EXINT channel modes + * @{ + */ +#define EXINT_MODE_MASK 7U /**< @brief Mode parameter mask. */ +#define EXINT_MODE_EDGES_MASK 3U /**< @brief Edges field mask. */ +#define EXINT_MODE_DISABLED 0U /**< @brief Channel disabled. */ +#define EXINT_MODE_RISING_EDGE 1U /**< @brief Rising edge callback. */ +#define EXINT_MODE_FALLING_EDGE 2U /**< @brief Falling edge callback. */ +#define EXINT_MODE_BOTH_EDGES 3U /**< @brief Both edges callback. */ +#define EXINT_MODE_ACTION_MASK 4U /**< @brief Action field mask. */ +#define EXINT_MODE_ACTION_INTERRUPT 0U /**< @brief Interrupt mode. */ +#define EXINT_MODE_ACTION_EVENT 4U /**< @brief Event mode. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(AT32_EXINT_NUM_LINES) +#error "AT32_EXINT_NUM_LINES not defined in registry" +#endif + +#if (AT32_EXINT_NUM_LINES < 0) || (AT32_EXINT_NUM_LINES > 23) +#error "invalid AT32_EXINT_NUM_LINES value" +#endif + +#if !defined(AT32_EXINT_INTEN_MASK) +#error "AT32_EXINT_INTEN_MASK not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an EXINT line identifier. + */ +typedef uint32_t exintline_t; + +/** + * @brief Type of an EXINT line mode. + */ +typedef uint32_t exintmode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief From group 1 line number to mask. + * + * @param[in] line line number in range 0..31 + */ +#define EXINT_MASK1(line) (uint32_t)(1U << (line)) + +/** + * @brief AT32 EXINT group 1 IRQ status clearing. + * + * @param[in] mask mask of group 1 lines to be initialized + * + * @special + */ +#define exintClearGroup1(mask) do { \ + osalDbgAssert(((mask) & AT32_EXINT_INTEN_MASK) == 0U, "fixed lines"); \ + EXINT->INTSTS = (uint32_t)(mask); \ +} while (false) + +/** + * @brief Serves an EXINT interrupt in group 1. + * + * @param[in] mask mask of lines to be cleared + * @param[out] out mask of lines needing processing + * + * @special + */ +#define exintGetAndClearGroup1(mask, out) do { \ + uint32_t intsts; \ + \ + intsts = EXINT->INTSTS & (mask); \ + (out) = intsts; \ + EXINT->INTSTS = intsts; \ +} while (false) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void exintEnableGroup1(uint32_t mask, exintmode_t mode); + void exintEnableLine(exintline_t line, exintmode_t mode); + void exintClearLine(exintline_t line); + #ifdef __cplusplus +} +#endif + +#endif /* AT32_EXINT_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc new file mode 100644 index 0000000000..8b66e3fa46 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint0.inc + * @brief Shared EXINT0 handler. + * + * @addtogroup AT32_EXINT0_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT0_PRIORITY) +#error "AT32_IRQ_EXINT0_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT0_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT0_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT0_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint0_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT0_NUMBER, AT32_IRQ_EXINT0_PRIORITY); +#endif +} + +static inline void exint0_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT0_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT0_HANDLER) +/** + * @brief EXINT[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT0_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 0, intsts); + + exint_serve_irq(intsts, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc new file mode 100644 index 0000000000..e33a9e57b8 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint1.inc + * @brief Shared EXINT1 handler. + * + * @addtogroup AT32_EXINT1_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT1_PRIORITY) +#error "AT32_IRQ_EXINT1_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT1_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT1_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT1_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint1_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT1_NUMBER, AT32_IRQ_EXINT1_PRIORITY); +#endif +} + +static inline void exint1_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT1_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT1_HANDLER) +/** + * @brief EXINT[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT1_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + extiGetAndClearGroup1(1U << 1, intsts); + + exint_serve_irq(intsts, 1); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc new file mode 100644 index 0000000000..222415d510 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc @@ -0,0 +1,104 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint10_15.inc + * @brief Shared EXINT10_15 handler. + * + * @addtogroup AT32_EXINT10_15_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT10_15_PRIORITY) +#error "AT32_IRQ_EXINT10_15_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT10_15_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT10_15_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT10_15_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint10_15_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT10_15_NUMBER, AT32_IRQ_EXINT10_15_PRIORITY); +#endif +} + +static inline void exint10_15_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT10_15_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT10_15_HANDLER) +/** + * @brief EXINT[10]..EXINT[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT10_15_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15), intsts); + + exint_serve_irq(intsts, 10); + exint_serve_irq(intsts, 11); + exint_serve_irq(intsts, 12); + exint_serve_irq(intsts, 13); + exint_serve_irq(intsts, 14); + exint_serve_irq(intsts, 15); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc new file mode 100644 index 0000000000..9c0b7db12f --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint16.inc + * @brief Shared EXINT16 handler. + * + * @addtogroup AT32_EXINT16_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT16_PRIORITY) +#error "AT32_IRQ_EXINT16_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT16_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT16_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT16_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint16_irq_init(void) { +#if defined(AT32_EXINT16_IS_USED) + nvicEnableVector(AT32_EXINT16_NUMBER, AT32_IRQ_EXINT16_PRIORITY); +#endif +} + +static inline void exint16_irq_deinit(void) { +#if defined(AT32_EXINT16_IS_USED) + nvicDisableVector(AT32_EXINT16_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT16_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT16_HANDLER) +/** + * @brief EXINT[16] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT16_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 16, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT16_ISR) + AT32_EXINT16_ISR(intsts, 16); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc new file mode 100644 index 0000000000..9d6d39e6bb --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint17.inc + * @brief Shared EXINT17 handler. + * + * @addtogroup AT32_EXINT17_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT17_PRIORITY) +#error "AT32_IRQ_EXINT17_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT17_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT17_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT17_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint17_irq_init(void) { +#if defined(AT32_EXINT17_IS_USED) + nvicEnableVector(AT32_EXINT17_NUMBER, AT32_IRQ_EXINT17_PRIORITY); +#endif +} + +static inline void exint17_irq_deinit(void) { +#if defined(AT32_EXINT17_IS_USED) + nvicDisableVector(AT32_EXINT17_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT17_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT17_HANDLER) +/** + * @brief EXINT[17] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT17_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 17, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT17_ISR) + AT32_EXINT17_ISR(intsts, 17); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc new file mode 100644 index 0000000000..644488de5b --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint18.inc + * @brief Shared EXINT18 handler. + * + * @addtogroup AT32_EXINT18_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT18_PRIORITY) +#error "AT32_IRQ_EXINT18_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT18_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT18_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT18_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint18_irq_init(void) { +#if defined(AT32_EXINT18_IS_USED) + nvicEnableVector(AT32_EXINT18_NUMBER, AT32_IRQ_EXINT18_PRIORITY); +#endif +} + +static inline void exint18_irq_deinit(void) { +#if defined(AT32_EXINT18_IS_USED) + nvicDisableVector(AT32_EXINT18_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT18_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT18_HANDLER) +/** + * @brief EXINT[18] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT18_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 18, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT18_ISR) + AT32_EXINT18_ISR(intsts, 18); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc new file mode 100644 index 0000000000..f6ccd70063 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint19.inc + * @brief Shared EXINT19 handler. + * + * @addtogroup AT32_EXINT19_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT19_PRIORITY) +#error "AT32_IRQ_EXINT19_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT19_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT19_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT19_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint19_irq_init(void) { +#if defined(AT32_EXINT19_IS_USED) + nvicEnableVector(AT32_EXINT19_NUMBER, AT32_IRQ_EXINT19_PRIORITY); +#endif +} + +static inline void exint19_irq_deinit(void) { +#if defined(AT32_EXINT19_IS_USED) + nvicDisableVector(AT32_EXINT19_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT19_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT19_HANDLER) +/** + * @brief EXINT[19] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT19_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 19, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT19_ISR) + AT32_EXINT19_ISR(intsts, 19); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc new file mode 100644 index 0000000000..43caec1e48 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint2.inc + * @brief Shared EXINT2 handler. + * + * @addtogroup AT32_EXINT2_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT2_PRIORITY) +#error "AT32_IRQ_EXINT2_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT2_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT2_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT2_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint2_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT2_NUMBER, AT32_IRQ_EXINT2_PRIORITY); +#endif +} + +static inline void exint2_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT2_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT2_HANDLER) +/** + * @brief EXINT[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT2_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 2, intsts); + + exint_serve_irq(intsts, 2); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc new file mode 100644 index 0000000000..6eaef17174 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint20.inc + * @brief Shared EXINT20 handler. + * + * @addtogroup AT32_EXINT20_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT20_PRIORITY) +#error "AT32_IRQ_EXINT20_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT20_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT20_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT20_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint20_irq_init(void) { +#if defined(AT32_EXINT20_IS_USED) + nvicEnableVector(AT32_EXINT20_NUMBER, AT32_IRQ_EXINT20_PRIORITY); +#endif +} + +static inline void exint20_irq_deinit(void) { +#if defined(AT32_EXINT20_IS_USED) + nvicDisableVector(AT32_EXINT20_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT20_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT20_HANDLER) +/** + * @brief EXINT[20] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT20_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 20, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT20_ISR) + AT32_EXINT20_ISR(intsts, 20); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc new file mode 100644 index 0000000000..2f3e1ee21b --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint21.inc + * @brief Shared EXINT21 handler. + * + * @addtogroup AT32_EXINT21_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT21_PRIORITY) +#error "AT32_IRQ_EXINT21_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT21_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT21_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT21_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint21_irq_init(void) { +#if defined(AT32_EXINT21_IS_USED) + nvicEnableVector(AT32_EXINT21_NUMBER, AT32_IRQ_EXINT21_PRIORITY); +#endif +} + +static inline void exint21_irq_deinit(void) { +#if defined(AT32_EXINT21_IS_USED) + nvicDisableVector(AT32_EXINT21_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT21_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT21_HANDLER) +/** + * @brief EXINT[21] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT21_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 21, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT21_ISR) + AT32_EXINT21_ISR(intsts, 21); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc new file mode 100644 index 0000000000..b202b57e57 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint22.inc + * @brief Shared EXINT22 handler. + * + * @addtogroup AT32_EXINT22_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT22_PRIORITY) +#error "AT32_IRQ_EXINT22_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT22_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT22_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT22_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint22_irq_init(void) { +#if defined(AT32_EXINT22_IS_USED) + nvicEnableVector(AT32_EXINT22_NUMBER, AT32_IRQ_EXINT22_PRIORITY); +#endif +} + +static inline void exint22_irq_deinit(void) { +#if defined(AT32_EXINT22_IS_USED) + nvicDisableVector(AT32_EXINT22_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_EXINT22_IS_USED) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT22_HANDLER) +/** + * @brief EXINT[22] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT22_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 22, intsts); + + /* Could be unused.*/ + (void)intsts; + +#if defined(AT32_EXINT22_ISR) + AT32_EXINT22_ISR(intsts, 22); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc new file mode 100644 index 0000000000..883d82bc7b --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint3.inc + * @brief Shared EXINT3 handler. + * + * @addtogroup AT32_EXINT3_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT3_PRIORITY) +#error "AT32_IRQ_EXINT3_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT3_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT3_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT3_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint3_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT3_NUMBER, AT32_IRQ_EXINT3_PRIORITY); +#endif +} + +static inline void exint3_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT3_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT3_HANDLER) +/** + * @brief EXINT[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT3_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 3, intsts); + + exint_serve_irq(intsts, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc new file mode 100644 index 0000000000..3388a97493 --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint4.inc + * @brief Shared EXINT4 handler. + * + * @addtogroup AT32_EXINT4_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT4_PRIORITY) +#error "AT32_IRQ_EXINT4_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT4_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT4_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT4_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint4_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT4_NUMBER, AT32_IRQ_EXINT4_PRIORITY); +#endif +} + +static inline void exint4_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT4_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT4_HANDLER) +/** + * @brief EXINT[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT4_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1(1U << 4, intsts); + + exint_serve_irq(intsts, 4); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc new file mode 100644 index 0000000000..56cc2b499b --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXINTv1/at32_exint5_9.inc + * @brief Shared EXINT5_9 handler. + * + * @addtogroup AT32_EXINT5_9_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_EXINT5_9_PRIORITY) +#error "AT32_IRQ_EXINT5_9_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_DISABLE_EXINT5_9_HANDLER) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_EXINT5_9_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_EXINT5_9_PRIORITY" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void exint5_9_irq_init(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicEnableVector(AT32_EXINT5_9_NUMBER, AT32_IRQ_EXINT5_9_PRIORITY); +#endif +} + +static inline void exint5_9_irq_deinit(void) { +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) + nvicDisableVector(AT32_EXINT5_9_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(AT32_DISABLE_EXINT5_9_HANDLER) +/** + * @brief EXINT[5]..EXINT[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_EXINT5_9_HANDLER) { + uint32_t intsts; + + OSAL_IRQ_PROLOGUE(); + + exintGetAndClearGroup1((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9), intsts); + + exint_serve_irq(intsts, 5); + exint_serve_irq(intsts, 6); + exint_serve_irq(intsts, 7); + exint_serve_irq(intsts, 8); + exint_serve_irq(intsts, 9); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/driver.mk b/os/hal/ports/AT32/LLD/EXINTv1/driver.mk new file mode 100644 index 0000000000..c65887b1bd --- /dev/null +++ b/os/hal/ports/AT32/LLD/EXINTv1/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/EXINTv1 diff --git a/os/hal/ports/AT32/LLD/GPIOv1/driver.mk b/os/hal/ports/AT32/LLD/GPIOv1/driver.mk new file mode 100644 index 0000000000..4c91943294 --- /dev/null +++ b/os/hal/ports/AT32/LLD/GPIOv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/GPIOv1 diff --git a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c new file mode 100644 index 0000000000..ee967c7cff --- /dev/null +++ b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c @@ -0,0 +1,292 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv1/hal_pal_lld.c + * @brief AT32 PAL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if AT32_HAS_GPIOF +#define APB2_EN_MASK (CRM_APB2EN_GPIOAEN | CRM_APB2EN_GPIOBEN | \ + CRM_APB2EN_GPIOCEN | CRM_APB2EN_GPIODEN | \ + CRM_APB2EN_GPIOFEN | CRM_APB2EN_IOMUXEN) +#elif AT32_HAS_GPIOC +#define APB2_EN_MASK (CRM_APB2EN_GPIOAEN | CRM_APB2EN_GPIOBEN | \ + CRM_APB2EN_GPIOCEN | CRM_APB2EN_GPIODEN | \ + CRM_APB2EN_IOMUXEN) +#else +#define APB2_EN_MASK (CRM_APB2EN_GPIOAEN | CRM_APB2EN_GPIOBEN | \ + CRM_APB2EN_GPIODEN | CRM_APB2EN_IOMUXEN) +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Event records for the 16 GPIO EXINT channels. + */ +palevent_t _pal_events[16]; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AT32 I/O ports configuration. + * @details Ports A, B, D(C, F) clocks enabled, IOMUX clock enabled. + * + * @param[in] config the AT32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < 16; i++) { + _pal_init_event(i); + } +#endif + + /* + * Enables the GPIO related clocks. + */ + crmEnableAPB2(APB2_EN_MASK, true); + + /* + * Initial GPIO setup. + */ + GPIOA->ODT = config->PAData.odt; + GPIOA->CFGHR = config->PAData.cfghr; + GPIOA->CFGLR = config->PAData.cfglr; + GPIOB->ODT = config->PBData.odt; + GPIOB->CFGHR = config->PBData.cfghr; + GPIOB->CFGLR = config->PBData.cfglr; +#if AT32_HAS_GPIOC || defined(__DOXYGEN__) + GPIOC->ODT = config->PCData.odt; + GPIOC->CFGHR = config->PCData.cfghr; + GPIOC->CFGLR = config->PCData.cfglr; +#endif + GPIOD->ODT = config->PDData.odt; + GPIOD->CFGHR = config->PDData.cfghr; + GPIOD->CFGLR = config->PDData.cfglr; +#if AT32_HAS_GPIOF || defined(__DOXYGEN__) + GPIOF->ODT = config->PFData.odt; + GPIOF->CFGHR = config->PFData.cfghr; + GPIOF->CFGLR = config->PFData.cfglr; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + static const uint8_t cfgtab[] = { + 4, /* PAL_MODE_RESET, implemented as input.*/ + 2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/ + 4, /* PAL_MODE_INPUT */ + 8, /* PAL_MODE_INPUT_PULLUP */ + 8, /* PAL_MODE_INPUT_PULLDOWN */ + 0, /* PAL_MODE_INPUT_ANALOG */ + 3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/ + 7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 8, /* Reserved.*/ + 0xB, /* PAL_MODE_AT32_ALTERNATE_PUSHPULL, 50MHz.*/ + 0xF, /* PAL_MODE_AT32_ALTERNATE_OPENDRAIN, 50MHz.*/ + }; + uint32_t mh, ml, cfghr, cfglr, cfg; + unsigned i; + + if (mode == PAL_MODE_INPUT_PULLUP) + port->SCR = mask; + else if (mode == PAL_MODE_INPUT_PULLDOWN) + port->CLR = mask; + cfg = cfgtab[mode]; + mh = ml = cfghr = cfglr = 0; + for (i = 0; i < 8; i++) { + ml <<= 4; + mh <<= 4; + cfglr <<= 4; + cfghr <<= 4; + if ((mask & 0x0080) == 0) + ml |= 0xf; + else + cfglr |= cfg; + if ((mask & 0x8000) == 0) + mh |= 0xf; + else + cfghr |= cfg; + mask <<= 1; + } + port->CFGHR = (port->CFGHR & mh) | cfghr; + port->CFGLR = (port->CFGLR & ml) | cfglr; +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) { + + uint32_t padmask, cridx, croff, crmask, portidx; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + /* Multiple channel setting of the same channel not allowed, first disable + it. This is done because on AT32 the same channel cannot be mapped on + multiple ports.*/ + osalDbgAssert(((EXINT->POLCFG1 & padmask) == 0U) && + ((EXINT->POLCFG2 & padmask) == 0U), "channel already in use"); + + /* Index and mask of the SYSCFG CR register to be used.*/ + cridx = (uint32_t)pad >> 2U; + croff = ((uint32_t)pad & 3U) * 4U; + crmask = ~(0xFU << croff); + + /* Port index is obtained assuming that GPIO ports are placed at regular + 0x400 intervals in memory space. So far this is true for all devices.*/ + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; + + /* Port selection in SYSCFG.*/ + IOMUX->EXINTC[cridx] = (IOMUX->EXINTC[cridx] & crmask) | (portidx << croff); + + /* Programming edge registers.*/ + if (mode & PAL_EVENT_MODE_RISING_EDGE) + EXINT->POLCFG1 |= padmask; + else + EXINT->POLCFG1 &= ~padmask; + if (mode & PAL_EVENT_MODE_FALLING_EDGE) + EXINT->POLCFG2 |= padmask; + else + EXINT->POLCFG2 &= ~padmask; + + /* Programming interrupt and event registers.*/ + EXINT->INTEN |= padmask; + EXINT->EVTEN &= ~padmask; +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { + uint32_t padmask, polcfg1_1, polcfg2_1; + + polcfg1_1 = EXINT->POLCFG1; + polcfg2_1 = EXINT->POLCFG2; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + /* If either POLCFG1_1 or POLCFG2_1 is enabled then the channel is in use.*/ + if (((polcfg1_1 | polcfg2_1) & padmask) != 0U) { + uint32_t cridx, croff, crport, portidx; + + /* Index and mask of the SYSCFG CR register to be used.*/ + cridx = (uint32_t)pad >> 2U; + croff = ((uint32_t)pad & 3U) * 4U; + + /* Port index is obtained assuming that GPIO ports are placed at regular + 0x400 intervals in memory space. So far this is true for all devices.*/ + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; + + crport = (IOMUX->EXINTC[cridx] >> croff) & 0xFU; + + osalDbgAssert(crport == portidx, "channel mapped on different port"); + + /* Disabling channel.*/ + EXINT->INTEN &= ~padmask; + EXINT->EVTEN &= ~padmask; + EXINT->POLCFG1 = polcfg1_1 & ~padmask; + EXINT->POLCFG2 = polcfg2_1 & ~padmask; + EXINT->INTSTS = padmask; + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(pad); +#endif + } +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h new file mode 100644 index 0000000000..8cc3136781 --- /dev/null +++ b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h @@ -0,0 +1,441 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv1/hal_pal_lld.h + * @brief AT32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/** + * @name AT32-specific I/O mode flags + * @{ + */ +/** + * @brief AT32 specific alternate push-pull output mode. + */ +#define PAL_MODE_AT32_ALTERNATE_PUSHPULL 16 + +/** + * @brief AT32 specific alternate open-drain output mode. + */ +#define PAL_MODE_AT32_ALTERNATE_OPENDRAIN 17 +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for ODT register.*/ + uint32_t odt; + /** Initial value for CFGLR register.*/ + uint32_t cfglr; + /** Initial value for CFGHR register.*/ + uint32_t cfghr; +} at32_gpio_setup_t; + +/** + * @brief AT32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port A setup data.*/ + at32_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + at32_gpio_setup_t PBData; +#if AT32_HAS_GPIOC || defined(__DOXYGEN__) + /** @brief Port C setup data.*/ + at32_gpio_setup_t PCData; +#endif + /** @brief Port D setup data.*/ + at32_gpio_setup_t PDData; +#if AT32_HAS_GPIOF || defined(__DOXYGEN__) + /** @brief Port F setup data.*/ + at32_gpio_setup_t PFData; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the AT32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if AT32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if AT32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if AT32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if AT32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/** + * @brief GPIO port F identifier. + */ +#if AT32_HAS_GPIOF || defined(__DOXYGEN__) +#define IOPORT5 GPIOF +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDT register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((ioportmask_t)((port)->IDT)) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODT register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((ioportmask_t)((port)->ODT)) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODT register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODT = (uint32_t)(bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO SCR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->SCR = (uint32_t)(bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO CLR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->CLR = (uint32_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO SCR register, the + * implementation has no side effects. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) { \ + uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ + ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ + (port)->SCR = w; \ +} + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note Writing on pads programmed as pull-up or pull-down has the side + * effect to modify the resistor setting because the output latched + * data is used for the resistor selection. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[pad]; (void)(port) + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[PAL_PAD(line)] + +/** + * @brief Pad event enable check. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return Pad event status. + * @retval false if the pad event is disabled. + * @retval true if the pad event is enabled. + * + * @notapi + */ +#define pal_lld_ispadeventenabled(port, pad) \ + (bool)((EXINT->INTEN & (1U << (uint32_t)pad)) != 0U) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) +extern palevent_t _pal_events[16]; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/I2Cv1/driver.mk b/os/hal/ports/AT32/LLD/I2Cv1/driver.mk new file mode 100644 index 0000000000..9a2fdb995c --- /dev/null +++ b/os/hal/ports/AT32/LLD/I2Cv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1 diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c new file mode 100644 index 0000000000..6e6482301a --- /dev/null +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c @@ -0,0 +1,790 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file I2Cv1/hal_i2c_lld.c + * @brief AT32 I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define I2C_EV5_MASTER_MODE_SELECT \ + ((uint32_t)(((I2C_STS2_TRMODE | I2C_STS2_BUSYF) << 16) | I2C_STS1_STARTF)) + +#define I2C_EV5_MASTER_MODE_SELECT_NO_BUSY \ + ((uint32_t)((I2C_STS2_TRMODE << 16) | I2C_STS1_STARTF)) + +#define I2C_EV6_MASTER_TRA_MODE_SELECTED \ + ((uint32_t)(((I2C_STS2_TRMODE | I2C_STS2_BUSYF | I2C_STS2_DIRF) << 16) | \ + I2C_STS1_ADDR7F | I2C_STS1_TDBE)) + +#define I2C_EV6_MASTER_REC_MODE_SELECTED \ + ((uint32_t)(((I2C_STS2_TRMODE | I2C_STS2_BUSYF) << 16) | I2C_STS1_ADDR7F)) + +#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ + ((uint32_t)(((I2C_STS2_TRMODE | I2C_STS2_BUSYF | I2C_STS2_DIRF) << 16) | \ + I2C_STS1_TDC | I2C_STS1_TDBE)) + +#define I2C_EV9_MASTER_ADD10 \ + ((uint32_t)(((I2C_STS2_TRMODE | I2C_STS2_BUSYF) << 16) | I2C_STS1_ADDRHF)) + +#define I2C_EV5_MASTER_MODE_INVALID \ + ((uint32_t)(((I2C_STS2_TRMODE | I2C_STS2_BUSYF) << 16) | (I2C_STS1_STARTF | \ + I2C_STS1_STOPF))) + +#define I2C_EV_MASK 0x00FF00FF + +#define I2C_ERROR_MASK \ + ((uint16_t)(I2C_STS1_BUSERR | I2C_STS1_ARLOST | I2C_STS1_ACKFAIL | \ + I2C_STS1_OUF | I2C_STS1_PECERR | I2C_STS1_TMOUT | \ + I2C_STS1_ALERTF)) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if AT32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if AT32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Aborts an I2C transaction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_abort_operation(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + /* Stops the I2C peripheral.*/ + dp->CTRL1 = I2C_CTRL1_RESET; + dp->CTRL1 = 0; + dp->CTRL2 = 0; + dp->STS1 = 0; + + /* Stops the associated DMA streams.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); +} + +/** + * @brief Set clock speed. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_set_clock(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + uint16_t regCLKCTRL, clock_div; + int32_t clock_speed = i2cp->config->clock_speed; + i2cdutycycle_t duty = i2cp->config->duty_cycle; + + osalDbgCheck((i2cp != NULL) && + (clock_speed > 0) && + (clock_speed <= 400000)); + + /* CTRL2 Configuration.*/ + dp->CTRL2 &= (uint16_t)~I2C_CTRL2_CLKFREQ; + dp->CTRL2 |= (uint16_t)I2C_CLK_FREQ; + + /* CLKCTRL Configuration.*/ + regCLKCTRL = 0; + clock_div = I2C_CLKCTRL_SPEED; + + if (clock_speed <= 100000) { + /* Configure clock_div in standard mode.*/ + osalDbgAssert(duty == STD_DUTY_CYCLE, "invalid standard mode duty cycle"); + + /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/ + osalDbgAssert((AT32_PCLK1 % (clock_speed * 2)) == 0, + "PCLK1 must be divisible without remainder"); + clock_div = (uint16_t)(AT32_PCLK1 / (clock_speed * 2)); + + osalDbgAssert(clock_div >= 0x04, + "clock divider less then 0x04 not allowed"); + regCLKCTRL |= (clock_div & I2C_CLKCTRL_SPEED); + + /* Sets the Maximum Rise Time for standard mode.*/ + dp->TMRISE = I2C_CLK_FREQ + 1; + } + else if (clock_speed <= 400000) { + /* Configure clock_div in fast mode.*/ + osalDbgAssert((duty == FAST_DUTY_CYCLE_2) || + (duty == FAST_DUTY_CYCLE_16_9), + "invalid fast mode duty cycle"); + + if (duty == FAST_DUTY_CYCLE_2) { + /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/ + osalDbgAssert((AT32_PCLK1 % (clock_speed * 3)) == 0, + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(AT32_PCLK1 / (clock_speed * 3)); + } + else if (duty == FAST_DUTY_CYCLE_16_9) { + /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/ + osalDbgAssert((AT32_PCLK1 % (clock_speed * 25)) == 0, + "PCLK1 must be divided without remainder"); + clock_div = (uint16_t)(AT32_PCLK1 / (clock_speed * 25)); + regCLKCTRL |= I2C_CLKCTRL_DUTYMODE; + } + + osalDbgAssert(clock_div >= 0x01, + "clock divider less then 0x04 not allowed"); + regCLKCTRL |= (I2C_CLKCTRL_SPEEDMODE | (clock_div & I2C_CLKCTRL_SPEED)); + + /* Sets the Maximum Rise Time for fast mode.*/ + dp->TMRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; + } + + osalDbgAssert((clock_div <= I2C_CLKCTRL_SPEED), "the selected clock is too low"); + + dp->CLKCTRL = regCLKCTRL; +} + +/** + * @brief Set operation mode of I2C hardware. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_set_opmode(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + i2copmode_t opmode = i2cp->config->op_mode; + uint16_t regCTRL1; + + regCTRL1 = dp->CTRL1; + switch (opmode) { + case OPMODE_I2C: + regCTRL1 &= (uint16_t)~(I2C_CTRL1_PERMODE|I2C_CTRL1_SMBMODE); + break; + case OPMODE_SMBUS_DEVICE: + regCTRL1 |= I2C_CTRL1_PERMODE; + regCTRL1 &= (uint16_t)~(I2C_CTRL1_SMBMODE); + break; + case OPMODE_SMBUS_HOST: + regCTRL1 |= (I2C_CTRL1_PERMODE|I2C_CTRL1_SMBMODE); + break; + } + dp->CTRL1 = regCTRL1; +} + +/** + * @brief I2C shared ISR code. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + uint32_t regSTS2 = dp->STS2; + uint32_t event = dp->STS1; + + /* Interrupts are disabled just before dmaStreamEnable() because there + is no need of interrupts until next transaction begin. All the work is + done by the DMA.*/ + switch (I2C_EV_MASK & (event | (regSTS2 << 16))) { + case I2C_EV5_MASTER_MODE_SELECT: + case I2C_EV5_MASTER_MODE_SELECT_NO_BUSY: + if ((i2cp->addr >> 8) > 0) { + /* 10-bit address: 1 1 1 1 0 X X R/W */ + dp->DT = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr); + } else { + dp->DT = i2cp->addr; + } + break; + case I2C_EV9_MASTER_ADD10: + /* Set second addr byte (10-bit addressing)*/ + dp->DT = (0xFF & (i2cp->addr >> 1)); + break; + case I2C_EV6_MASTER_REC_MODE_SELECTED: + dp->CTRL2 &= ~I2C_CTRL2_EVTIEN; + dmaStreamEnable(i2cp->dmarx); + dp->CTRL2 |= I2C_CTRL2_DMAEND; /* Needed in receiver mode. */ + if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2) + dp->CTRL1 &= ~I2C_CTRL1_ACKEN; + break; + case I2C_EV6_MASTER_TRA_MODE_SELECTED: + dp->CTRL2 &= ~I2C_CTRL2_EVTIEN; + dmaStreamEnable(i2cp->dmatx); + break; + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: + /* Catches TDC event after the end of transmission.*/ + (void)dp->DT; /* Clear TDC.*/ + if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { + /* Starts "read after write" operation, LSB = 1 -> receive.*/ + i2cp->addr |= 0x01; + dp->CTRL1 |= I2C_CTRL1_GENSTART | I2C_CTRL1_ACKEN; + return; + } + dp->CTRL2 &= ~I2C_CTRL2_EVTIEN; + dp->CTRL1 |= I2C_CTRL1_GENSTOP; + _i2c_wakeup_isr(i2cp); + break; + case I2C_EV5_MASTER_MODE_INVALID: + i2c_lld_abort_operation(i2cp); + dp->CTRL2 &= ~I2C_CTRL2_EVTIEN; + break; + default: + break; + } + /* Clear ADDR7F flag. */ + if (event & (I2C_STS1_ADDR7F | I2C_STS1_ADDRHF)) + (void)dp->STS2; +} + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(AT32_I2C_DMA_ERROR_HOOK) + if ((flags & AT32_DMA_STS_DTERRF) != 0) { + AT32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmarx); + + dp->CTRL2 &= ~I2C_CTRL2_DMAEND; + dp->CTRL1 &= ~I2C_CTRL1_ACKEN; + dp->CTRL1 |= I2C_CTRL1_GENSTOP; + _i2c_wakeup_isr(i2cp); +} + +/** + * @brief DMA TX end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { + I2C_TypeDef *dp = i2cp->i2c; + + /* DMA errors handling.*/ +#if defined(AT32_I2C_DMA_ERROR_HOOK) + if ((flags & AT32_DMA_STS_DTERRF) != 0) { + AT32_I2C_DMA_ERROR_HOOK(i2cp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(i2cp->dmatx); + /* Enables interrupts to catch BTF event meaning transmission part complete. + Interrupt handler will decide to generate GENSTOP or to begin receiving + part of R/W transaction itself.*/ + dp->CTRL2 |= I2C_CTRL2_EVTIEN; +} + +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] sts content of the STS1 register to be decoded + * + * @notapi + */ +static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sts) { + + /* Clears interrupt flags just to be safe.*/ + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + + i2cp->errors = I2C_NO_ERROR; + + if (sts & I2C_STS1_BUSERR) { /* Bus error. */ + i2cp->errors |= I2C_BUS_ERROR; + } + + if (sts & I2C_STS1_ARLOST) /* Arbitration lost. */ + i2cp->errors |= I2C_ARBITRATION_LOST; + + if (sts & I2C_STS1_ACKFAIL) { /* Acknowledge failure. */ + i2cp->i2c->CTRL2 &= ~I2C_CTRL2_EVTIEN; + i2cp->i2c->CTRL1 |= I2C_CTRL1_GENSTOP; /* Generate stop. */ + i2cp->errors |= I2C_ACK_FAILURE; + } + + if (sts & I2C_STS1_OUF) /* Overload. */ + i2cp->errors |= I2C_OVERRUN; + + if (sts & I2C_STS1_TMOUT) /* SMBus timeout. */ + i2cp->errors |= I2C_TIMEOUT; + + if (sts & I2C_STS1_PECERR) /* PEC receive error. */ + i2cp->errors |= I2C_PEC_ERROR; + + if (sts & I2C_STS1_ALERTF) /* SMBus alert. */ + i2cp->errors |= I2C_SMB_ALERT; + + /* If some error has been identified then sends wakes the waiting thread.*/ + if (i2cp->errors != I2C_NO_ERROR) + _i2c_wakeup_error_isr(i2cp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(AT32_I2C1_EVENT_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief I2C1 error interrupt handler. + */ +OSAL_IRQ_HANDLER(AT32_I2C1_ERROR_HANDLER) { + uint16_t sts = I2CD1.i2c->STS1; + + OSAL_IRQ_PROLOGUE(); + + I2CD1.i2c->STS1 = ~(sts & I2C_ERROR_MASK); + i2c_lld_serve_error_interrupt(&I2CD1, sts); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* AT32_I2C_USE_I2C1 */ + +#if AT32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(AT32_I2C2_EVENT_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief I2C2 error interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(AT32_I2C2_ERROR_HANDLER) { + uint16_t sts = I2CD2.i2c->STS1; + + OSAL_IRQ_PROLOGUE(); + + I2CD2.i2c->STS1 = ~(sts & I2C_ERROR_MASK); + i2c_lld_serve_error_interrupt(&I2CD2, sts); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* AT32_I2C_USE_I2C2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if AT32_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = I2C1; + I2CD1.dmarx = NULL; + I2CD1.dmatx = NULL; +#endif /* AT32_I2C_USE_I2C1 */ + +#if AT32_I2C_USE_I2C2 + i2cObjectInit(&I2CD2); + I2CD2.thread = NULL; + I2CD2.i2c = I2C2; + I2CD2.dmarx = NULL; + I2CD2.dmatx = NULL; +#endif /* AT32_I2C_USE_I2C2 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->i2c; + + /* If in stopped state then enables the I2C and DMA clocks.*/ + if (i2cp->state == I2C_STOP) { + + i2cp->txdmamode = AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE | + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_DTERRIEN | + AT32_DMA_CCTRL_FDTIEN | AT32_DMA_CCTRL_DTD_M2P; + i2cp->rxdmamode = AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE | + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_DTERRIEN | + AT32_DMA_CCTRL_FDTIEN | AT32_DMA_CCTRL_DTD_P2M; + +#if AT32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + crmResetI2C1(); + + i2cp->dmarx = dmaStreamAllocI(AT32_I2C_I2C1_RX_DMA_STREAM, + AT32_I2C_I2C1_IRQ_PRIORITY, + (at32_dmasts_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream"); + i2cp->dmatx = dmaStreamAllocI(AT32_I2C_I2C1_TX_DMA_STREAM, + AT32_I2C_I2C1_IRQ_PRIORITY, + (at32_dmasts_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(i2cp->dmarx, AT32_I2C_I2C1_RX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C1_RX); + dmaSetRequestSource(i2cp->dmatx, AT32_I2C_I2C1_TX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C1_TX); +#endif + + crmEnableI2C1(true); + nvicEnableVector(I2C1_EVT_IRQn, AT32_I2C_I2C1_IRQ_PRIORITY); + nvicEnableVector(I2C1_ERR_IRQn, AT32_I2C_I2C1_IRQ_PRIORITY); + + i2cp->rxdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C1_DMA_PRIORITY); + i2cp->txdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C1_DMA_PRIORITY); + } +#endif /* AT32_I2C_USE_I2C1 */ + +#if AT32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + crmResetI2C2(); + + i2cp->dmarx = dmaStreamAllocI(AT32_I2C_I2C2_RX_DMA_STREAM, + AT32_I2C_I2C2_IRQ_PRIORITY, + (at32_dmasts_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream"); + i2cp->dmatx = dmaStreamAllocI(AT32_I2C_I2C2_TX_DMA_STREAM, + AT32_I2C_I2C2_IRQ_PRIORITY, + (at32_dmasts_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(i2cp->dmarx, AT32_I2C_I2C2_RX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C2_RX); + dmaSetRequestSource(i2cp->dmatx, AT32_I2C_I2C2_TX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C2_TX); +#endif + + crmEnableI2C2(true); + nvicEnableVector(I2C2_EVT_IRQn, AT32_I2C_I2C2_IRQ_PRIORITY); + nvicEnableVector(I2C2_ERR_IRQn, AT32_I2C_I2C2_IRQ_PRIORITY); + + i2cp->rxdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C2_DMA_PRIORITY); + i2cp->txdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C2_DMA_PRIORITY); + } +#endif /* AT32_I2C_USE_I2C2 */ + } + + /* I2C registers pointed by the DMA.*/ + dmaStreamSetPeripheral(i2cp->dmarx, &dp->DT); + dmaStreamSetPeripheral(i2cp->dmatx, &dp->DT); + + /* Reset i2c peripheral.*/ + dp->CTRL1 = I2C_CTRL1_RESET; + dp->CTRL1 = 0; + dp->CTRL2 = I2C_CTRL2_ERRIEN | I2C_CTRL2_DMAEN; + + /* Setup I2C parameters.*/ + i2c_lld_set_clock(i2cp); + i2c_lld_set_opmode(i2cp); + + /* Ready to go.*/ + dp->CTRL1 |= I2C_CTRL1_I2CEN; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + i2c_lld_abort_operation(i2cp); + dmaStreamFreeI(i2cp->dmatx); + dmaStreamFreeI(i2cp->dmarx); + i2cp->dmatx = NULL; + i2cp->dmarx = NULL; + +#if AT32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + nvicDisableVector(I2C1_EVT_IRQn); + nvicDisableVector(I2C1_ERR_IRQn); + crmDisableI2C1(); + } +#endif + +#if AT32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + nvicDisableVector(I2C2_EVT_IRQn); + nvicDisableVector(I2C2_ERR_IRQn); + crmDisableI2C2(); + } +#endif + } +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1. This is hardware + * restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + systime_t start, end; + msg_t msg; + + osalDbgCheck(rxbytes > 1); + + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2C_NO_ERROR; + + /* Initializes driver fields, LSB = 1 -> receive.*/ + i2cp->addr = (addr << 1) | 0x01; + + /* Releases the lock from high level driver.*/ + osalSysUnlock(); + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = osalTimeAddX(start, OSAL_MS2I(AT32_I2C_BUSY_TIMEOUT)); + + /* Waits until BUSY flag is reset or, alternatively, for a timeout + condition.*/ + while (true) { + osalSysLock(); + + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if (!(dp->STS2 & I2C_STS2_BUSYF) && !(dp->CTRL1 & I2C_CTRL1_GENSTOP)) + break; + + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) { + dmaStreamDisable(i2cp->dmarx); + return MSG_TIMEOUT; + } + + osalSysUnlock(); + } + + /* Starts the operation.*/ + dp->CTRL2 |= I2C_CTRL2_EVTIEN; + dp->CTRL1 |= I2C_CTRL1_GENSTART | I2C_CTRL1_ACKEN; + + /* Waits for the operation completion or a timeout.*/ + msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); + if (msg != MSG_OK) { + dmaStreamDisable(i2cp->dmarx); + } + + return msg; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout) { + I2C_TypeDef *dp = i2cp->i2c; + systime_t start, end; + msg_t msg; + + osalDbgCheck((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))); + + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2C_NO_ERROR; + + /* Initializes driver fields, LSB = 0 -> transmit.*/ + i2cp->addr = (addr << 1); + + /* Releases the lock from high level driver.*/ + osalSysUnlock(); + + /* TX DMA setup.*/ + dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); + dmaStreamSetMemory0(i2cp->dmatx, txbuf); + dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = osalTimeAddX(start, OSAL_MS2I(AT32_I2C_BUSY_TIMEOUT)); + + /* Waits until BUSY flag is reset or, alternatively, for a timeout + condition.*/ + while (true) { + osalSysLock(); + + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if (!(dp->STS2 & I2C_STS2_BUSYF) && !(dp->CTRL1 & I2C_CTRL1_GENSTOP)) + break; + + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) { + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + return MSG_TIMEOUT; + } + + osalSysUnlock(); + } + + /* Starts the operation.*/ + dp->CTRL2 |= I2C_CTRL2_EVTIEN; + dp->CTRL1 |= I2C_CTRL1_GENSTART; + + /* Waits for the operation completion or a timeout.*/ + msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); + if (msg != MSG_OK) { + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + } + + return msg; +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h new file mode 100644 index 0000000000..ca73059d07 --- /dev/null +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h @@ -0,0 +1,328 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file I2Cv1/hal_i2c_lld.h + * @brief AT32 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef HAL_I2C_LLD_H +#define HAL_I2C_LLD_H + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Peripheral clock frequency. + */ +#define I2C_CLK_FREQ ((AT32_PCLK1) / 1000000) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define AT32_I2C_USE_I2C1 FALSE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define AT32_I2C_USE_I2C2 FALSE +#endif + +/** + * @brief I2C timeout on busy condition in milliseconds. + */ +#if !defined(AT32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) +#define AT32_I2C_BUSY_TIMEOUT 50 +#endif + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(AT32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_IRQ_PRIORITY 10 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + */ +#if !defined(AT32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_IRQ_PRIORITY 10 +#endif + +/** +* @brief I2C1 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(AT32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_I2C_I2C1_DMA_PRIORITY 1 +#endif + +/** +* @brief I2C2 DMA priority (0..3|lowest..highest). +* @note The priority level is used for both the TX and RX DMA streams but +* because of the streams ordering the RX stream has always priority +* over the TX stream. +*/ +#if !defined(AT32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_I2C_I2C2_DMA_PRIORITY 1 +#endif + +/** + * @brief I2C DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(AT32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** @brief error checks */ +#if AT32_I2C_USE_I2C1 && !AT32_HAS_I2C1 +#error "I2C1 not present in the selected device" +#endif + +#if AT32_I2C_USE_I2C2 && !AT32_HAS_I2C2 +#error "I2C2 not present in the selected device" +#endif + +#if !AT32_I2C_USE_I2C1 && !AT32_I2C_USE_I2C2 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + +#if AT32_I2C_USE_I2C1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_I2C_I2C1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C1" +#endif + +#if AT32_I2C_USE_I2C2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_I2C_I2C2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C2" +#endif + +#if AT32_I2C_USE_I2C1 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_I2C_I2C1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to I2C1" +#endif + +#if AT32_I2C_USE_I2C2 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_I2C_I2C2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to I2C2" +#endif + +#if !defined(AT32_DMA_REQUIRED) +#define AT32_DMA_REQUIRED +#endif + +/* Check clock range. */ +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 72) +#error "I2C peripheral clock frequency out of range." +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing an I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief Type of I2C driver condition flags. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Supported modes for the I2C bus. + */ +typedef enum { + OPMODE_I2C = 1, + OPMODE_SMBUS_DEVICE = 2, + OPMODE_SMBUS_HOST = 3, +} i2copmode_t; + +/** + * @brief Supported duty cycle modes for the I2C bus. + */ +typedef enum { + STD_DUTY_CYCLE = 1, + FAST_DUTY_CYCLE_2 = 2, + FAST_DUTY_CYCLE_16_9 = 3, +} i2cdutycycle_t; + +/** + * @brief I2C driver configuration structure. + */ +struct hal_i2c_config { + /* End of the mandatory fields.*/ + i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ + uint32_t clock_speed; /**< @brief Specifies the clock frequency. + @note Must be set to a value lower + than 400kHz. */ + i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode + duty cycle. */ +}; + +/** + * @brief Type of a structure representing an I2C configuration. + */ +typedef struct hal_i2c_config I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct hal_i2c_driver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct hal_i2c_driver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + thread_reference_t thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; + /** + * @brief Receive DMA channel. + */ + const at32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const at32_dma_stream_t *dmatx; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if AT32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if AT32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* HAL_I2C_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h new file mode 100644 index 0000000000..5f670e430d --- /dev/null +++ b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h @@ -0,0 +1,921 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file OTGv1/at32_otg.h + * @brief AT32 OTG registers layout header. + * + * @addtogroup USB + * @{ + */ + +#ifndef AT32_OTG_H +#define AT32_OTG_H + +/** + * @brief OTG_FS FIFO memory size in words. + */ +#define AT32_OTG1_FIFO_MEM_SIZE 320 + +/** + * @brief OTG_HS FIFO memory size in words. + */ +#define AT32_OTG2_FIFO_MEM_SIZE 1024 + +/** + * @brief Host channel registers group. + */ +typedef struct { + volatile uint32_t HCCHAR; /**< @brief Host channel characteristics + register. */ + volatile uint32_t resvd8; + volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ + volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask + register. */ + volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size + register. */ + volatile uint32_t resvd14; + volatile uint32_t resvd18; + volatile uint32_t resvd1c; +} at32_otg_host_chn_t; + +/** + * @brief Device input endpoint registers group. + */ +typedef struct { + volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint + control register. */ + volatile uint32_t resvd4; + volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt + register. */ + volatile uint32_t resvdC; + volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size + register. */ + volatile uint32_t resvd14; + volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO + status register. */ + volatile uint32_t resvd1C; +} at32_otg_in_ep_t; + +/** + * @brief Device output endpoint registers group. + */ +typedef struct { + volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint + control register. */ + volatile uint32_t resvd4; + volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt + register. */ + volatile uint32_t resvdC; + volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer + size register. */ + volatile uint32_t resvd14; + volatile uint32_t resvd18; + volatile uint32_t resvd1C; +} at32_otg_out_ep_t; + +/** + * @brief USB registers memory map. + */ +typedef struct { + volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ + volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ + volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ + volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ + volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ + volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ + volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ + volatile uint32_t GRXSTSR; /**< @brief Receive status debug read + register. */ + volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop + register. */ + volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ + volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size + register. */ + volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue + status register. */ + volatile uint32_t resvd30; + volatile uint32_t resvd34; + volatile uint32_t GCCFG; /**< @brief General core configuration. */ + volatile uint32_t CID; /**< @brief Core ID register. */ + volatile uint32_t resvd58[48]; + volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size + register. */ + volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO + size registers. */ + volatile uint32_t resvd140[176]; + volatile uint32_t HCFG; /**< @brief Host configuration register. */ + volatile uint32_t HFIR; /**< @brief Host frame interval register. */ + volatile uint32_t HFNUM; /**< @brief Host frame number/frame time + Remaining register. */ + volatile uint32_t resvd40C; + volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue + status register. */ + volatile uint32_t HAINT; /**< @brief Host all channels interrupt + register. */ + volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask + register. */ + volatile uint32_t resvd41C[9]; + volatile uint32_t HPRT; /**< @brief Host port control and status + register. */ + volatile uint32_t resvd444[47]; + at32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */ + volatile uint32_t resvd700[64]; + volatile uint32_t DCFG; /**< @brief Device configuration register. */ + volatile uint32_t DCTL; /**< @brief Device control register. */ + volatile uint32_t DSTS; /**< @brief Device status register. */ + volatile uint32_t resvd80C; + volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common + interrupt mask register. */ + volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common + interrupt mask register. */ + volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt + register. */ + volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt + mask register. */ + volatile uint32_t resvd820; + volatile uint32_t resvd824; + volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time + register. */ + volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time + register. */ + volatile uint32_t resvd830; + volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty + interrupt mask register. */ + volatile uint32_t resvd838; + volatile uint32_t resvd83C; + volatile uint32_t resvd840[16]; + volatile uint32_t resvd880[16]; + volatile uint32_t resvd8C0[16]; + at32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ + at32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ + volatile uint32_t resvdD00[64]; + volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control + register. */ + volatile uint32_t resvdE04[127]; + volatile uint32_t FIFO[16][1024]; +} at32_otg_t; + +/** + * @name GOTGCTL register bit definitions + * @{ + */ +#define GOTGCTL_BSVLD (1U << 19) /**< B-Session Valid. */ +#define GOTGCTL_ASVLD (1U << 18) /**< A-Session Valid. */ +#define GOTGCTL_DBCT (1U << 17) /**< Long/Short debounce time. */ +#define GOTGCTL_CIDSTS (1U << 16) /**< Connector ID status. */ +#define GOTGCTL_EHEN (1U << 12) +#define GOTGCTL_DHNPEN (1U << 11) /**< Device HNP enabled. */ +#define GOTGCTL_HSHNPEN (1U << 10) /**< Host Set HNP enable. */ +#define GOTGCTL_HNPRQ (1U << 9) /**< HNP request. */ +#define GOTGCTL_HNGSCS (1U << 8) /**< Host negotiation success. */ +#define GOTGCTL_BVALOVAL (1U << 7) +#define GOTGCTL_BVALOEN (1U << 6) +#define GOTGCTL_AVALOVAL (1U << 5) +#define GOTGCTL_AVALOEN (1U << 4) +#define GOTGCTL_VBVALOVAL (1U << 3) +#define GOTGCTL_VBVALOEN (1U << 2) +#define GOTGCTL_SRQ (1U << 1) /**< Session request. */ +#define GOTGCTL_SRQSCS (1U << 0) /**< Session request success. */ +/** @} */ + +/** + * @name GOTGINT register bit definitions + * @{ + */ +#define GOTGINT_DBCDNE (1U << 19) /**< Debounce done. */ +#define GOTGINT_ADTOCHG (1U << 18) /**< A-Device timeout change. */ +#define GOTGINT_HNGDET (1U << 17) /**< Host negotiation detected. */ +#define GOTGINT_HNSSCHG (1U << 9) /**< Host negotiation success + status change. */ +#define GOTGINT_SRSSCHG (1U << 8) /**< Session request success + status change. */ +#define GOTGINT_SEDET (1U << 2) /**< Session end detected. */ +/** @} */ + +/** + * @name GAHBCFG register bit definitions + * @{ + */ +#define GAHBCFG_PTXFELVL (1U << 8) /**< Periodic TxFIFO empty + level. */ +#define GAHBCFG_TXFELVL (1U << 7) /**< Non-periodic TxFIFO empty + level. */ +#define GAHBCFG_DMAEN (1U << 5) /**< DMA enable (HS only). */ +#define GAHBCFG_HBSTLEN_MASK (15U << 1) /**< Burst length/type mask (HS + only). */ +#define GAHBCFG_HBSTLEN(n) ((n) << 1) /**< Burst length/type (HS + only). */ +#define GAHBCFG_GINTMSK (1U << 0) /**< Global interrupt mask. */ +/** @} */ + +/** + * @name GUSBCFG register bit definitions + * @{ + */ +#define GUSBCFG_CTXPKT (1U << 31) /**< Corrupt Tx packet. */ +#define GUSBCFG_FDMOD (1U << 30) /**< Force Device Mode. */ +#define GUSBCFG_FHMOD (1U << 29) /**< Force Host Mode. */ +#define GUSBCFG_TRDT_MASK (15U << 10) /**< USB Turnaround time field + mask. */ +#define GUSBCFG_TRDT(n) ((n) << 10) /**< USB Turnaround time field + value. */ +#define GUSBCFG_HNPCAP (1U << 9) /**< HNP-Capable. */ +#define GUSBCFG_SRPCAP (1U << 8) /**< SRP-Capable. */ +#define GUSBCFG_PHYSEL (1U << 6) /**< USB 2.0 High-Speed PHY or + USB 1.1 Full-Speed serial + transceiver Select. */ +#define GUSBCFG_TOCAL_MASK (7U << 0) /**< HS/FS timeout calibration + field mask. */ +#define GUSBCFG_TOCAL(n) ((n) << 0) /**< HS/FS timeout calibration + field value. */ +/** @} */ + +/** + * @name GRSTCTL register bit definitions + * @{ + */ +#define GRSTCTL_AHBIDL (1U << 31) /**< AHB Master Idle. */ +#define GRSTCTL_TXFNUM_MASK (31U << 6) /**< TxFIFO number field mask. */ +#define GRSTCTL_TXFNUM(n) ((n) << 6) /**< TxFIFO number field value. */ +#define GRSTCTL_TXFFLSH (1U << 5) /**< TxFIFO flush. */ +#define GRSTCTL_RXFFLSH (1U << 4) /**< RxFIFO flush. */ +#define GRSTCTL_FCRST (1U << 2) /**< Host frame counter reset. */ +#define GRSTCTL_HSRST (1U << 1) /**< HClk soft reset. */ +#define GRSTCTL_CSRST (1U << 0) /**< Core soft reset. */ +/** @} */ + +/** + * @name GINTSTS register bit definitions + * @{ + */ +#define GINTSTS_WKUPINT (1U << 31) /**< Resume/Remote wakeup + detected interrupt. */ +#define GINTSTS_SRQINT (1U << 30) /**< Session request/New session + detected interrupt. */ +#define GINTSTS_DISCINT (1U << 29) /**< Disconnect detected + interrupt. */ +#define GINTSTS_CIDSCHG (1U << 28) /**< Connector ID status change.*/ +#define GINTSTS_PTXFE (1U << 26) /**< Periodic TxFIFO empty. */ +#define GINTSTS_HCINT (1U << 25) /**< Host channels interrupt. */ +#define GINTSTS_HPRTINT (1U << 24) /**< Host port interrupt. */ +#define GINTSTS_IPXFR (1U << 21) /**< Incomplete periodic + transfer. */ +#define GINTSTS_IISOOXFR (1U << 21) /**< Incomplete isochronous OUT + transfer. */ +#define GINTSTS_IISOIXFR (1U << 20) /**< Incomplete isochronous IN + transfer. */ +#define GINTSTS_OEPINT (1U << 19) /**< OUT endpoints interrupt. */ +#define GINTSTS_IEPINT (1U << 18) /**< IN endpoints interrupt. */ +#define GINTSTS_EOPF (1U << 15) /**< End of periodic frame + interrupt. */ +#define GINTSTS_ISOODRP (1U << 14) /**< Isochronous OUT packet + dropped interrupt. */ +#define GINTSTS_ENUMDNE (1U << 13) /**< Enumeration done. */ +#define GINTSTS_USBRST (1U << 12) /**< USB reset. */ +#define GINTSTS_USBSUSP (1U << 11) /**< USB suspend. */ +#define GINTSTS_ESUSP (1U << 10) /**< Early suspend. */ +#define GINTSTS_GONAKEFF (1U << 7) /**< Global OUT NAK effective. */ +#define GINTSTS_GINAKEFF (1U << 6) /**< Global IN non-periodic NAK + effective. */ +#define GINTSTS_NPTXFE (1U << 5) /**< Non-periodic TxFIFO empty. */ +#define GINTSTS_RXFLVL (1U << 4) /**< RxFIFO non-empty. */ +#define GINTSTS_SOF (1U << 3) /**< Start of frame. */ +#define GINTSTS_OTGINT (1U << 2) /**< OTG interrupt. */ +#define GINTSTS_MMIS (1U << 1) /**< Mode Mismatch interrupt. */ +#define GINTSTS_CMOD (1U << 0) /**< Current mode of operation. */ +/** @} */ + +/** + * @name GINTMSK register bit definitions + * @{ + */ +#define GINTMSK_WKUM (1U << 31) /**< Resume/remote wakeup + detected interrupt mask. */ +#define GINTMSK_SRQM (1U << 30) /**< Session request/New session + detected interrupt mask. */ +#define GINTMSK_DISCM (1U << 29) /**< Disconnect detected + interrupt mask. */ +#define GINTMSK_CIDSCHGM (1U << 28) /**< Connector ID status change + mask. */ +#define GINTMSK_PTXFEM (1U << 26) /**< Periodic TxFIFO empty mask.*/ +#define GINTMSK_HCM (1U << 25) /**< Host channels interrupt + mask. */ +#define GINTMSK_HPRTM (1U << 24) /**< Host port interrupt mask. */ +#define GINTMSK_IPXFRM (1U << 21) /**< Incomplete periodic + transfer mask. */ +#define GINTMSK_IISOOXFRM (1U << 21) /**< Incomplete isochronous OUT + transfer mask. */ +#define GINTMSK_IISOIXFRM (1U << 20) /**< Incomplete isochronous IN + transfer mask. */ +#define GINTMSK_OEPM (1U << 19) /**< OUT endpoints interrupt + mask. */ +#define GINTMSK_IEPM (1U << 18) /**< IN endpoints interrupt + mask. */ +#define GINTMSK_EOPFM (1U << 15) /**< End of periodic frame + interrupt mask. */ +#define GINTMSK_ISOODRPM (1U << 14) /**< Isochronous OUT packet + dropped interrupt mask. */ +#define GINTMSK_ENUMDNEM (1U << 13) /**< Enumeration done mask. */ +#define GINTMSK_USBRSTM (1U << 12) /**< USB reset mask. */ +#define GINTMSK_USBSUSPM (1U << 11) /**< USB suspend mask. */ +#define GINTMSK_ESUSPM (1U << 10) /**< Early suspend mask. */ +#define GINTMSK_GONAKEFFM (1U << 7) /**< Global OUT NAK effective + mask. */ +#define GINTMSK_GINAKEFFM (1U << 6) /**< Global non-periodic IN NAK + effective mask. */ +#define GINTMSK_NPTXFEM (1U << 5) /**< Non-periodic TxFIFO empty + mask. */ +#define GINTMSK_RXFLVLM (1U << 4) /**< Receive FIFO non-empty + mask. */ +#define GINTMSK_SOFM (1U << 3) /**< Start of (micro)frame mask.*/ +#define GINTMSK_OTGM (1U << 2) /**< OTG interrupt mask. */ +#define GINTMSK_MMISM (1U << 1) /**< Mode Mismatch interrupt + mask. */ +/** @} */ + +/** + * @name GRXSTSR register bit definitions + * @{ + */ +#define GRXSTSR_PKTSTS_MASK (15U << 17) /**< Packet status mask. */ +#define GRXSTSR_PKTSTS(n) ((n) << 17) /**< Packet status value. */ +#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) +#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) +#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) +#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) +#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) +#define GRXSTSR_DPID_MASK (3U << 15) /**< Data PID mask. */ +#define GRXSTSR_DPID(n) ((n) << 15) /**< Data PID value. */ +#define GRXSTSR_BCNT_MASK (0x7FFU << 4) /**< Byte count mask. */ +#define GRXSTSR_BCNT(n) ((n) << 4) /**< Byte count value. */ +#define GRXSTSR_CHNUM_MASK (15U << 0) /**< Channel number mask. */ +#define GRXSTSR_CHNUM(n) ((n) << 0) /**< Channel number value. */ +#define GRXSTSR_EPNUM_MASK (15U << 0) /**< Endpoint number mask. */ +#define GRXSTSR_EPNUM(n) ((n) << 0) /**< Endpoint number value. */ +/** @} */ + +/** + * @name GRXSTSP register bit definitions + * @{ + */ +#define GRXSTSP_PKTSTS_MASK (15U << 17) /**< Packet status mask. */ +#define GRXSTSP_PKTSTS(n) ((n) << 17) /**< Packet status value. */ +#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) +#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) +#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) +#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) +#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) +#define GRXSTSP_DPID_MASK (3U << 15) /**< Data PID mask. */ +#define GRXSTSP_DPID(n) ((n) << 15) /**< Data PID value. */ +#define GRXSTSP_BCNT_MASK (0x7FFU << 4) /**< Byte count mask. */ +#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ +#define GRXSTSP_BCNT(n) ((n) << 4) /**< Byte count value. */ +#define GRXSTSP_CHNUM_MASK (15U << 0) /**< Channel number mask. */ +#define GRXSTSP_CHNUM(n) ((n) << 0) /**< Channel number value. */ +#define GRXSTSP_EPNUM_MASK (15U << 0) /**< Endpoint number mask. */ +#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ +#define GRXSTSP_EPNUM(n) ((n) << 0) /**< Endpoint number value. */ +/** @} */ + +/** + * @name GRXFSIZ register bit definitions + * @{ + */ +#define GRXFSIZ_RXFD_MASK (0xFFFFU << 0) /**< RxFIFO depth mask. */ +#define GRXFSIZ_RXFD(n) ((n) << 0) /**< RxFIFO depth value. */ +/** @} */ + +/** + * @name DIEPTXFx register bit definitions + * @{ + */ +#define DIEPTXF_INEPTXFD_MASK (0xFFFFU << 16) /**< IN endpoint TxFIFO depth + mask. */ +#define DIEPTXF_INEPTXFD(n) ((n) << 16) /**< IN endpoint TxFIFO depth + value. */ +#define DIEPTXF_INEPTXSA_MASK (0xFFFFU << 0) /**< IN endpoint FIFOx transmit + RAM start address mask.*/ +#define DIEPTXF_INEPTXSA(n) ((n) << 0) /**< IN endpoint FIFOx transmit + RAM start address value.*/ +/** @} */ + +/** + * @name GCCFG register bit definitions + * @{ + */ +/* Definitions for stepping 1.*/ +#define GCCFG_NOVBUSSENS (1U << 21) /**< VBUS sensing disable. */ +#define GCCFG_SOFOUTEN (1U << 20) /**< SOF output enable. */ +#define GCCFG_VBUSBSEN (1U << 19) /**< Enable the VBUS sensing "B" + device. */ +#define GCCFG_VBUSASEN (1U << 18) /**< Enable the VBUS sensing "A" + device. */ + +/* Definitions for stepping 2.*/ +#define GCCFG_VBDEN (1U << 21) /**< VBUS sensing enable. */ +#define GCCFG_PWRDWN (1U << 16) /**< Power down. */ +/** @} */ + +/** + * @name HPTXFSIZ register bit definitions + * @{ + */ +#define HPTXFSIZ_PTXFD_MASK (0xFFFFU << 16) /**< Host periodic TxFIFO + depth mask. */ +#define HPTXFSIZ_PTXFD(n) ((n) << 16) /**< Host periodic TxFIFO + depth value. */ +#define HPTXFSIZ_PTXSA_MASK (0xFFFFU << 0) /**< Host periodic TxFIFO + Start address mask. */ +#define HPTXFSIZ_PTXSA(n) ((n) << 0) /**< Host periodic TxFIFO + start address value. */ +/** @} */ + +/** + * @name HCFG register bit definitions + * @{ + */ +#define HCFG_FSLSS (1U << 2) /**< FS- and LS-only support. */ +#define HCFG_FSLSPCS_MASK (3U << 0) /**< FS/LS PHY clock select + mask. */ +#define HCFG_FSLSPCS_48 (1U << 0) /**< PHY clock is running at + 48 MHz. */ +#define HCFG_FSLSPCS_6 (2U << 0) /**< PHY clock is running at + 6 MHz. */ +/** @} */ + +/** + * @name HFIR register bit definitions + * @{ + */ +#define HFIR_FRIVL_MASK (0xFFFFU << 0) /**< Frame interval mask. */ +#define HFIR_FRIVL(n) ((n) << 0) /**< Frame interval value. */ +/** @} */ + +/** + * @name HFNUM register bit definitions + * @{ + */ +#define HFNUM_FTREM_MASK (0xFFFFU << 16) /**< Frame time Remaining + mask. */ +#define HFNUM_FTREM(n) ((n) << 16) /**< Frame time Remaining + value. */ +#define HFNUM_FRNUM_MASK (0xFFFFU << 0) /**< Frame number mask. */ +#define HFNUM_FRNUM(n) ((n) << 0) /**< Frame number value. */ +/** @} */ + +/** + * @name HPTXSTS register bit definitions + * @{ + */ +#define HPTXSTS_PTXQTOP_MASK (0xFFU << 24) /**< Top of the periodic + transmit request queue + mask. */ +#define HPTXSTS_PTXQTOP(n) ((n) << 24) /**< Top of the periodic + transmit request queue + value. */ +#define HPTXSTS_PTXQSAV_MASK (0xFF<< 16) /**< Periodic transmit request + queue Space Available + mask. */ +#define HPTXSTS_PTXQSAV(n) ((n) << 16) /**< Periodic transmit request + queue Space Available + value. */ +#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<< 0) /**< Periodic transmit Data + FIFO Space Available + mask. */ +#define HPTXSTS_PTXFSAVL(n) ((n) << 0) /**< Periodic transmit Data + FIFO Space Available + value. */ +/** @} */ + +/** + * @name HAINT register bit definitions + * @{ + */ +#define HAINT_HAINT_MASK (0xFFFFU << 0) /**< Channel interrupts + mask. */ +#define HAINT_HAINT(n) ((n) << 0) /**< Channel interrupts + value. */ +/** @} */ + +/** + * @name HAINTMSK register bit definitions + * @{ + */ +#define HAINTMSK_HAINTM_MASK (0xFFFFU << 0) /**< Channel interrupt mask + mask. */ +#define HAINTMSK_HAINTM(n) ((n) << 0) /**< Channel interrupt mask + value. */ +/** @} */ + +/** + * @name HPRT register bit definitions + * @{ + */ +#define HPRT_PSPD_MASK (3U << 17) /**< Port speed mask. */ +#define HPRT_PSPD_FS (1U << 17) /**< Full speed value. */ +#define HPRT_PSPD_LS (2U << 17) /**< Low speed value. */ +#define HPRT_PTCTL_MASK (15U << 13) /**< Port Test control mask. */ +#define HPRT_PTCTL(n) ((n) << 13) /**< Port Test control value. */ +#define HPRT_PPWR (1U << 12) /**< Port power. */ +#define HPRT_PLSTS_MASK (3U << 11) /**< Port Line status mask. */ +#define HPRT_PLSTS_DM (1U << 11) /**< Logic level of D-. */ +#define HPRT_PLSTS_DP (1U << 10) /**< Logic level of D+. */ +#define HPRT_PRST (1U << 8) /**< Port reset. */ +#define HPRT_PSUSP (1U << 7) /**< Port suspend. */ +#define HPRT_PRES (1U << 6) /**< Port Resume. */ +#define HPRT_POCCHNG (1U << 5) /**< Port overcurrent change. */ +#define HPRT_POCA (1U << 4) /**< Port overcurrent active. */ +#define HPRT_PENCHNG (1U << 3) /**< Port enable/disable change.*/ +#define HPRT_PENA (1U << 2) /**< Port enable. */ +#define HPRT_PCDET (1U << 1) /**< Port Connect detected. */ +#define HPRT_PCSTS (1U << 0) /**< Port connect status. */ +/** @} */ + +/** + * @name HCCHAR register bit definitions + * @{ + */ +#define HCCHAR_CHENA (1U << 31) /**< Channel enable. */ +#define HCCHAR_CHDIS (1U << 30) /**< Channel Disable. */ +#define HCCHAR_ODDFRM (1U << 29) /**< Odd frame. */ +#define HCCHAR_DAD_MASK (0x7FU << 22) /**< Device Address mask. */ +#define HCCHAR_DAD(n) ((n) << 22) /**< Device Address value. */ +#define HCCHAR_MCNT_MASK (3U << 20) /**< Multicount mask. */ +#define HCCHAR_MCNT(n) ((n) << 20) /**< Multicount value. */ +#define HCCHAR_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ +#define HCCHAR_EPTYP(n) ((n) << 18) /**< Endpoint type value. */ +#define HCCHAR_EPTYP_CTL (0U << 18) /**< Control endpoint value. */ +#define HCCHAR_EPTYP_ISO (1U << 18) /**< Isochronous endpoint value.*/ +#define HCCHAR_EPTYP_BULK (2U << 18) /**< Bulk endpoint value. */ +#define HCCHAR_EPTYP_INTR (3U << 18) /**< Interrupt endpoint value. */ +#define HCCHAR_LSDEV (1U << 17) /**< Low-Speed device. */ +#define HCCHAR_EPDIR (1U << 15) /**< Endpoint direction. */ +#define HCCHAR_EPNUM_MASK (15U << 11) /**< Endpoint number mask. */ +#define HCCHAR_EPNUM(n) ((n) << 11) /**< Endpoint number value. */ +#define HCCHAR_MPS_MASK (0x7FFU << 0) /**< Maximum packet size mask.*/ +#define HCCHAR_MPS(n) ((n) << 0) /**< Maximum packet size value. */ +/** @} */ + +/** + * @name HCINT register bit definitions + * @{ + */ +#define HCINT_DTERR (1U << 10) /**< Data toggle error. */ +#define HCINT_FRMOR (1U << 9) /**< Frame overrun. */ +#define HCINT_BBERR (1U << 8) /**< Babble error. */ +#define HCINT_TRERR (1U << 7) /**< Transaction Error. */ +#define HCINT_ACK (1U << 5) /**< ACK response + received/transmitted + interrupt. */ +#define HCINT_NAK (1U << 4) /**< NAK response received + interrupt. */ +#define HCINT_STALL (1U << 3) /**< STALL response received + interrupt. */ +#define HCINT_AHBERR (1U << 2) /**< AHB error interrupt. */ +#define HCINT_CHH (1U << 1) /**< Channel halted. */ +#define HCINT_XFRC (1U << 0) /**< Transfer completed. */ +/** @} */ + +/** + * @name HCINTMSK register bit definitions + * @{ + */ +#define HCINTMSK_DTERRM (1U << 10) /**< Data toggle error mask. */ +#define HCINTMSK_FRMORM (1U << 9) /**< Frame overrun mask. */ +#define HCINTMSK_BBERRM (1U << 8) /**< Babble error mask. */ +#define HCINTMSK_TRERRM (1U << 7) /**< Transaction error mask. */ +#define HCINTMSK_NYET (1U << 6) /**< NYET response received + interrupt mask. */ +#define HCINTMSK_ACKM (1U << 5) /**< ACK Response + received/transmitted + interrupt mask. */ +#define HCINTMSK_NAKM (1U << 4) /**< NAK response received + interrupt mask. */ +#define HCINTMSK_STALLM (1U << 3) /**< STALL response received + interrupt mask. */ +#define HCINTMSK_AHBERRM (1U << 2) /**< AHB error interrupt mask. */ +#define HCINTMSK_CHHM (1U << 1) /**< Channel halted mask. */ +#define HCINTMSK_XFRCM (1U << 0) /**< Transfer completed mask. */ +/** @} */ + +/** + * @name HCTSIZ register bit definitions + * @{ + */ +#define HCTSIZ_DPID_MASK (3U << 29) /**< PID mask. */ +#define HCTSIZ_DPID_DATA0 (0U << 29) /**< DATA0. */ +#define HCTSIZ_DPID_DATA2 (1U << 29) /**< DATA2. */ +#define HCTSIZ_DPID_DATA1 (2U << 29) /**< DATA1. */ +#define HCTSIZ_DPID_MDATA (3U << 29) /**< MDATA. */ +#define HCTSIZ_DPID_SETUP (3U << 29) /**< SETUP. */ +#define HCTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */ +#define HCTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ +#define HCTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define HCTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ +/** @} */ + +/** + * @name DCFG register bit definitions + * @{ + */ +#define DCFG_PFIVL_MASK (3U << 11) /**< Periodic frame interval + mask. */ +#define DCFG_PFIVL(n) ((n) << 11) /**< Periodic frame interval + value. */ +#define DCFG_DAD_MASK (0x7FU << 4)/**< Device address mask. */ +#define DCFG_DAD(n) ((n) << 4) /**< Device address value. */ +#define DCFG_NZLSOHSK (1U << 2) /**< Non-Zero-Length status + OUT handshake. */ +#define DCFG_DSPD_MASK (3U << 0) /**< Device speed mask. */ +#define DCFG_DSPD_HS (0U << 0) /**< High speed (USB 2.0). */ +#define DCFG_DSPD_HS_FS (1U << 0) /**< High speed (USB 2.0) in FS + mode. */ +#define DCFG_DSPD_FS11 (3U << 0) /**< Full speed (USB 1.1 + transceiver clock is 48 + MHz). */ +/** @} */ + +/** + * @name DCTL register bit definitions + * @{ + */ +#define DCTL_POPRGDNE (1U << 11) /**< Power-on programming done. */ +#define DCTL_CGONAK (1U << 10) /**< Clear global OUT NAK. */ +#define DCTL_SGONAK (1U << 9) /**< Set global OUT NAK. */ +#define DCTL_CGINAK (1U << 8) /**< Clear global non-periodic + IN NAK. */ +#define DCTL_SGINAK (1U << 7) /**< Set global non-periodic + IN NAK. */ +#define DCTL_TCTL_MASK (7U << 4) /**< Test control mask. */ +#define DCTL_TCTL(n) ((n) << 4 /**< Test control value. */ +#define DCTL_GONSTS (1U << 3) /**< Global OUT NAK status. */ +#define DCTL_GINSTS (1U << 2) /**< Global non-periodic IN + NAK status. */ +#define DCTL_SDIS (1U << 1) /**< Soft disconnect. */ +#define DCTL_RWUSIG (1U << 0) /**< Remote wakeup signaling. */ +/** @} */ + +/** + * @name DSTS register bit definitions + * @{ + */ +#define DSTS_FNSOF_MASK (0x3FFU << 8) /**< Frame number of the + received SOF mask. */ +#define DSTS_FNSOF(n) ((n) << 8) /**< Frame number of the + received SOF value. */ +#define DSTS_FNSOF_ODD (1U << 8) /**< Frame parity of the + received SOF value. */ +#define DSTS_EERR (1U << 3) /**< Erratic error. */ +#define DSTS_ENUMSPD_MASK (3U << 1) /**< Enumerated speed mask. */ +#define DSTS_ENUMSPD_FS_48 (3U << 1) /**< Full speed (PHY clock is + running at 48 MHz). */ +#define DSTS_ENUMSPD_HS_480 (0U << 1) /**< High speed. */ +#define DSTS_SUSPSTS (1U << 0) /**< Suspend status. */ +/** @} */ + +/** + * @name DIEPMSK register bit definitions + * @{ + */ +#define DIEPMSK_TXFEM (1U << 6) /**< Transmit FIFO empty mask. */ +#define DIEPMSK_INEPNEM (1U << 6) /**< IN endpoint NAK effective + mask. */ +#define DIEPMSK_ITTXFEMSK (1U << 4) /**< IN token received when + TxFIFO empty mask. */ +#define DIEPMSK_TOCM (1U << 3) /**< Timeout condition mask. */ +#define DIEPMSK_EPDM (1U << 1) /**< Endpoint disabled + interrupt mask. */ +#define DIEPMSK_XFRCM (1U << 0) /**< Transfer completed + interrupt mask. */ +/** @} */ + +/** + * @name DOEPMSK register bit definitions + * @{ + */ +#define DOEPMSK_OTEPDM (1U << 4) /**< OUT token received when + endpoint disabled mask. */ +#define DOEPMSK_STUPM (1U << 3) /**< SETUP phase done mask. */ +#define DOEPMSK_EPDM (1U << 1) /**< Endpoint disabled + interrupt mask. */ +#define DOEPMSK_XFRCM (1U << 0) /**< Transfer completed + interrupt mask. */ +/** @} */ + +/** + * @name DAINT register bit definitions + * @{ + */ +#define DAINT_OEPINT_MASK (0xFFFFU << 16) /**< OUT endpoint interrupt + bits mask. */ +#define DAINT_OEPINT(n) ((n) << 16) /**< OUT endpoint interrupt + bits value. */ +#define DAINT_IEPINT_MASK (0xFFFFU << 0) /**< IN endpoint interrupt + bits mask. */ +#define DAINT_IEPINT(n) ((n) << 0) /**< IN endpoint interrupt + bits value. */ +/** @} */ + +/** + * @name DAINTMSK register bit definitions + * @{ + */ +#define DAINTMSK_OEPM_MASK (0xFFFFU << 16) /**< OUT EP interrupt mask + bits mask. */ +#define DAINTMSK_OEPM(n) (1U <<(16+(n))) /**< OUT EP interrupt mask + bits value. */ +#define DAINTMSK_IEPM_MASK (0xFFFFU << 0) /**< IN EP interrupt mask + bits mask. */ +#define DAINTMSK_IEPM(n) (1U <<(n)) /**< IN EP interrupt mask + bits value. */ +/** @} */ + +/** + * @name DVBUSDIS register bit definitions + * @{ + */ +#define DVBUSDIS_VBUSDT_MASK (0xFFFFU << 0) /**< Device VBUS discharge + time mask. */ +#define DVBUSDIS_VBUSDT(n) ((n) << 0) /**< Device VBUS discharge + time value. */ +/** @} */ + +/** + * @name DVBUSPULSE register bit definitions + * @{ + */ +#define DVBUSPULSE_DVBUSP_MASK (0xFFFU << 0) /**< Device VBUSpulsing time + mask. */ +#define DVBUSPULSE_DVBUSP(n) ((n) << 0) /**< Device VBUS pulsing time + value. */ +/** @} */ + +/** + * @name DIEPEMPMSK register bit definitions + * @{ + */ +#define DIEPEMPMSK_INEPTXFEM(n) (1U << (n)) /**< IN EP Tx FIFO empty + interrupt mask bit. */ +/** @} */ + +/** + * @name DIEPCTL register bit definitions + * @{ + */ +#define DIEPCTL_EPENA (1U << 31) /**< Endpoint enable. */ +#define DIEPCTL_EPDIS (1U << 30) /**< Endpoint disable. */ +#define DIEPCTL_SD1PID (1U << 29) /**< Set DATA1 PID. */ +#define DIEPCTL_SODDFRM (1U << 29) /**< Set odd frame. */ +#define DIEPCTL_SD0PID (1U << 28) /**< Set DATA0 PID. */ +#define DIEPCTL_SEVNFRM (1U << 28) /**< Set even frame. */ +#define DIEPCTL_SNAK (1U << 27) /**< Set NAK. */ +#define DIEPCTL_CNAK (1U << 26) /**< Clear NAK. */ +#define DIEPCTL_TXFNUM_MASK (15U << 22) /**< TxFIFO number mask. */ +#define DIEPCTL_TXFNUM(n) ((n) << 22) /**< TxFIFO number value. */ +#define DIEPCTL_STALL (1U << 21) /**< STALL handshake. */ +#define DIEPCTL_SNPM (1U << 20) /**< Snoop mode. */ +#define DIEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ +#define DIEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */ +#define DIEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */ +#define DIEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */ +#define DIEPCTL_EPTYP_INTR (3U << 18) /**< Interrupt. */ +#define DIEPCTL_NAKSTS (1U << 17) /**< NAK status. */ +#define DIEPCTL_EONUM (1U << 16) /**< Even/odd frame. */ +#define DIEPCTL_DPID (1U << 16) /**< Endpoint data PID. */ +#define DIEPCTL_USBAEP (1U << 15) /**< USB active endpoint. */ +#define DIEPCTL_MPSIZ_MASK (0x3FFU << 0) /**< Maximum Packet size mask.*/ +#define DIEPCTL_MPSIZ(n) ((n) << 0) /**< Maximum Packet size value. */ +/** @} */ + +/** + * @name DIEPINT register bit definitions + * @{ + */ +#define DIEPINT_TXFE (1U << 7) /**< Transmit FIFO empty. */ +#define DIEPINT_INEPNE (1U << 6) /**< IN endpoint NAK effective. */ +#define DIEPINT_ITTXFE (1U << 4) /**< IN Token received when + TxFIFO is empty. */ +#define DIEPINT_TOC (1U << 3) /**< Timeout condition. */ +#define DIEPINT_EPDISD (1U << 1) /**< Endpoint disabled + interrupt. */ +#define DIEPINT_XFRC (1U << 0) /**< Transfer completed. */ +/** @} */ + +/** + * @name DIEPTSIZ register bit definitions + * @{ + */ +#define DIEPTSIZ_MCNT_MASK (3U << 29) /**< Multi count mask. */ +#define DIEPTSIZ_MCNT(n) ((n) << 29) /**< Multi count value. */ +#define DIEPTSIZ_PKTCNT_MASK (0x3FF<< 19) /**< Packet count mask. */ +#define DIEPTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ +#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define DIEPTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ +/** @} */ + +/** + * @name DTXFSTS register bit definitions. + * @{ + */ +#define DTXFSTS_INEPTFSAV_MASK (0xFFFFU << 0) /**< IN endpoint TxFIFO space + available. */ +/** @} */ + +/** + * @name DOEPCTL register bit definitions. + * @{ + */ +#define DOEPCTL_EPENA (1U << 31) /**< Endpoint enable. */ +#define DOEPCTL_EPDIS (1U << 30) /**< Endpoint disable. */ +#define DOEPCTL_SD1PID (1U << 29) /**< Set DATA1 PID. */ +#define DOEPCTL_SODDFRM (1U << 29) /**< Set odd frame. */ +#define DOEPCTL_SD0PID (1U << 28) /**< Set DATA0 PID. */ +#define DOEPCTL_SEVNFRM (1U << 28) /**< Set even frame. */ +#define DOEPCTL_SNAK (1U << 27) /**< Set NAK. */ +#define DOEPCTL_CNAK (1U << 26) /**< Clear NAK. */ +#define DOEPCTL_STALL (1U << 21) /**< STALL handshake. */ +#define DOEPCTL_SNPM (1U << 20) /**< Snoop mode. */ +#define DOEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ +#define DOEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */ +#define DOEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */ +#define DOEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */ +#define DOEPCTL_EPTYP_INTR (3U << 18) /**< Interrupt. */ +#define DOEPCTL_NAKSTS (1U << 17) /**< NAK status. */ +#define DOEPCTL_EONUM (1U << 16) /**< Even/odd frame. */ +#define DOEPCTL_DPID (1U << 16) /**< Endpoint data PID. */ +#define DOEPCTL_USBAEP (1U << 15) /**< USB active endpoint. */ +#define DOEPCTL_MPSIZ_MASK (0x3FFU << 0)/**< Maximum Packet size mask. */ +#define DOEPCTL_MPSIZ(n) ((n) << 0) /**< Maximum Packet size value. */ +/** @} */ + +/** + * @name DOEPINT register bit definitions + * @{ + */ +#define DOEPINT_SETUP_RCVD (1U << 15) /**< SETUP packet received. */ +#define DOEPINT_B2BSTUP (1U << 6) /**< Back-to-back SETUP packets + received. */ +#define DOEPINT_OTEPDIS (1U << 4) /**< OUT token received when + endpoint disabled. */ +#define DOEPINT_STUP (1U << 3) /**< SETUP phase done. */ +#define DOEPINT_EPDISD (1U << 1) /**< Endpoint disabled + interrupt. */ +#define DOEPINT_XFRC (1U << 0) /**< Transfer completed + interrupt. */ +/** @} */ + +/** + * @name DOEPTSIZ register bit definitions + * @{ + */ +#define DOEPTSIZ_RXDPID_MASK (3U << 29) /**< Received data PID mask. */ +#define DOEPTSIZ_RXDPID(n) ((n) << 29) /**< Received data PID value. */ +#define DOEPTSIZ_STUPCNT_MASK (3U << 29) /**< SETUP packet count mask. */ +#define DOEPTSIZ_STUPCNT(n) ((n) << 29) /**< SETUP packet count value. */ +#define DOEPTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */ +#define DOEPTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ +#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define DOEPTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ +/** @} */ + +/** + * @name PCGCCTL register bit definitions + * @{ + */ +#define PCGCCTL_PHYSUSP (1U << 4) /**< PHY Suspended. */ +#define PCGCCTL_GATEHCLK (1U << 1) /**< Gate HCLK. */ +#define PCGCCTL_STPPCLK (1U << 0) /**< Stop PCLK. */ +/** @} */ + +#define OTG_FS_ADDR 0x50000000 +#define OTG_HS_ADDR 0x40040000 + +/** + * @brief Accesses to the OTG_FS registers block. + */ +#define OTG_FS ((at32_otg_t *)OTG_FS_ADDR) + +/** + * @brief Accesses to the OTG_HS registers block. + */ +#define OTG_HS ((at32_otg_t *)OTG_HS_ADDR) + +#endif /* AT32_OTG_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/OTGv1/driver.mk b/os/hal/ports/AT32/LLD/OTGv1/driver.mk new file mode 100644 index 0000000000..99ad1bac49 --- /dev/null +++ b/os/hal/ports/AT32/LLD/OTGv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1 diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c new file mode 100644 index 0000000000..1801e04f4e --- /dev/null +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c @@ -0,0 +1,1280 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file OTGv1/hal_usb_lld.c + * @brief AT32 USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include + +#include "hal.h" + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define TRDT_VALUE_FS 5 +#define TRDT_VALUE_HS 9 + +#define EP0_MAX_INSIZE 64 +#define EP0_MAX_OUTSIZE 64 + +#if AT32_OTG_STEPPING == 1 +#if defined(BOARD_OTG_NOVBUSSENS) +#define GCCFG_INIT_VALUE (GCCFG_NOVBUSSENS | GCCFG_PWRDWN) +#else +#define GCCFG_INIT_VALUE (GCCFG_VBUSASEN | GCCFG_VBUSBSEN | \ + GCCFG_PWRDWN) +#endif + +#elif AT32_OTG_STEPPING == 2 +#if defined(BOARD_OTG_NOVBUSSENS) +#define GCCFG_INIT_VALUE GCCFG_PWRDWN +#else +#define GCCFG_INIT_VALUE (GCCFG_VBDEN | GCCFG_PWRDWN) +#endif + +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief OTG_FS driver identifier.*/ +#if AT32_USB_USE_OTG1 || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/** @brief OTG_HS driver identifier.*/ +#if AT32_USB_USE_OTG2 || defined(__DOXYGEN__) +USBDriver USBD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief Buffer for the EP0 setup packets. + */ +static uint8_t ep0setup_buffer[8]; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out, + 1, + ep0setup_buffer +}; + +#if AT32_USB_USE_OTG1 +static const at32_otg_params_t fsparams = { + AT32_USB_OTG1_RX_FIFO_SIZE / 4, + AT32_OTG1_FIFO_MEM_SIZE, + AT32_OTG1_ENDPOINTS +}; +#endif + +#if AT32_USB_USE_OTG2 +static const at32_otg_params_t hsparams = { + AT32_USB_OTG2_RX_FIFO_SIZE / 4, + AT32_OTG2_FIFO_MEM_SIZE, + AT32_OTG2_ENDPOINTS +}; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void otg_core_reset(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + + /* Wait AHB idle condition.*/ + while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) + ; + + /* Core reset and delay of at least 3 PHY cycles.*/ + otgp->GRSTCTL = GRSTCTL_CSRST; + osalSysPolledDelayX(12); + while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) + ; + + osalSysPolledDelayX(18); + + /* Wait AHB idle condition again.*/ + while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) + ; +} + +static void otg_disable_ep(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + unsigned i; + + for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { + + if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0U) { + otgp->ie[i].DIEPCTL |= DIEPCTL_EPDIS; + } + + if ((otgp->oe[i].DOEPCTL & DIEPCTL_EPENA) != 0U) { + otgp->oe[i].DOEPCTL |= DIEPCTL_EPDIS; + } + + otgp->ie[i].DIEPINT = 0xFFFFFFFF; + otgp->oe[i].DOEPINT = 0xFFFFFFFF; + } + otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); +} + +static void otg_rxfifo_flush(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + + otgp->GRSTCTL = GRSTCTL_RXFFLSH; + while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) + ; + /* Wait for 3 PHY Clocks.*/ + osalSysPolledDelayX(18); +} + +static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) { + at32_otg_t *otgp = usbp->otg; + + otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH; + while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) + ; + /* Wait for 3 PHY Clocks.*/ + osalSysPolledDelayX(18); +} + +/** + * @brief Resets the FIFO RAM memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void otg_ram_reset(USBDriver *usbp) { + + usbp->pmnext = usbp->otgparams->rx_fifo_size; +} + +/** + * @brief Allocates a block from the FIFO RAM memory. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] size size of the packet buffer to allocate in words + * + * @notapi + */ +static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) { + uint32_t next; + + next = usbp->pmnext; + usbp->pmnext += size; + osalDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size, + "OTG FIFO memory overflow"); + return next; +} + +/** + * @brief Writes to a TX FIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[in] buf buffer where to copy the endpoint data + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +static void otg_fifo_write_from_buffer(volatile uint32_t *fifop, + const uint8_t *buf, + size_t n) { + + osalDbgAssert(n > 0, "is zero"); + + while (true) { + *fifop = *((uint32_t *)buf); + if (n <= 4) { + break; + } + n -= 4; + buf += 4; + } +} + +/** + * @brief Reads a packet from the RXFIFO. + * + * @param[in] fifop pointer to the FIFO register + * @param[out] buf buffer where to copy the endpoint data + * @param[in] n number of bytes to pull from the FIFO + * @param[in] max number of bytes to copy into the buffer + * + * @notapi + */ +static void otg_fifo_read_to_buffer(volatile uint32_t *fifop, + uint8_t *buf, + size_t n, + size_t max) { + uint32_t w = 0; + size_t i = 0; + + while (i < n) { + if ((i & 3) == 0) { + w = *fifop; + } + if (i < max) { + *buf++ = (uint8_t)w; + w >>= 8; + } + i++; + } +} + +/** + * @brief Incoming packets handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void otg_rxfifo_handler(USBDriver *usbp) { + uint32_t sts, cnt, ep; + + /* Popping the event word out of the RX FIFO.*/ + sts = usbp->otg->GRXSTSP; + + /* Event details.*/ + cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; + ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; + + switch (sts & GRXSTSP_PKTSTS_MASK) { + case GRXSTSP_SETUP_DATA: + otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf, + cnt, 8); + break; + case GRXSTSP_SETUP_COMP: + break; + case GRXSTSP_OUT_DATA: + otg_fifo_read_to_buffer(usbp->otg->FIFO[0], + usbp->epc[ep]->out_state->rxbuf, + cnt, + usbp->epc[ep]->out_state->rxsize - + usbp->epc[ep]->out_state->rxcnt); + usbp->epc[ep]->out_state->rxbuf += cnt; + usbp->epc[ep]->out_state->rxcnt += cnt; + break; + case GRXSTSP_OUT_COMP: + break; + case GRXSTSP_OUT_GLOBAL_NAK: + break; + default: + break; + } +} + +/** + * @brief Outgoing packets handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { + + /* The TXFIFO is filled until there is space and data to be transmitted.*/ + while (true) { + uint32_t n; + + /* Transaction end condition.*/ + if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) { +#if 1 + usbp->otg->DIEPEMPMSK &= ~DIEPEMPMSK_INEPTXFEM(ep); +#endif + return true; + } + + /* Number of bytes remaining in current transaction.*/ + n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt; + if (n > usbp->epc[ep]->in_maxsize) + n = usbp->epc[ep]->in_maxsize; + + /* Checks if in the TXFIFO there is enough space to accommodate the + next packet.*/ + if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n) + return false; + +#if AT32_USB_OTGFIFO_FILL_BASEPRI + __set_BASEPRI(CORTEX_PRIO_MASK(AT32_USB_OTGFIFO_FILL_BASEPRI)); +#endif + otg_fifo_write_from_buffer(usbp->otg->FIFO[ep], + usbp->epc[ep]->in_state->txbuf, + n); + usbp->epc[ep]->in_state->txbuf += n; + usbp->epc[ep]->in_state->txcnt += n; +#if AT32_USB_OTGFIFO_FILL_BASEPRI + __set_BASEPRI(0); +#endif + } +} + +/** + * @brief Generic endpoint IN handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { + at32_otg_t *otgp = usbp->otg; + uint32_t epint = otgp->ie[ep].DIEPINT; + + otgp->ie[ep].DIEPINT = epint; + + if (epint & DIEPINT_TOC) { + /* Timeouts not handled yet, not sure how to handle.*/ + } + if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) { + /* Transmit transfer complete.*/ + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + if (isp->txsize < isp->totsize) { + /* In case the transaction covered only part of the total transfer + then another transaction is immediately started in order to + cover the remaining.*/ + isp->txsize = isp->totsize - isp->txsize; + isp->txcnt = 0; + osalSysLockFromISR(); + usb_lld_start_in(usbp, ep); + osalSysUnlockFromISR(); + } + else { + /* End on IN transfer.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + } + if ((epint & DIEPINT_TXFE) && + (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) { + /* TX FIFO empty or emptying.*/ + otg_txfifo_handler(usbp, ep); + } +} + +/** + * @brief Generic endpoint OUT handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { + at32_otg_t *otgp = usbp->otg; + uint32_t epint = otgp->oe[ep].DOEPINT; + + /* Resets all EP IRQ sources.*/ + otgp->oe[ep].DOEPINT = epint; + + if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) { + /* Setup packets handling, setup packets are handled using a + specific callback.*/ + _usb_isr_invoke_setup_cb(usbp, ep); + } + + if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) { + USBOutEndpointState *osp; + + /* OUT state structure pointer for this endpoint.*/ + osp = usbp->epc[ep]->out_state; + + /* EP0 requires special handling.*/ + if (ep == 0) { + +#if defined(AT32_OTG_SEQUENCE_WORKAROUND) + /* If an OUT transaction end interrupt is processed while the state + machine is not in an OUT state then it is ignored, this is caused + on some devices (L4) apparently injecting spurious data complete + words in the RX FIFO.*/ + if ((usbp->ep0state & USB_OUT_STATE) == 0) + return; +#endif + + /* In case the transaction covered only part of the total transfer + then another transaction is immediately started in order to + cover the remaining.*/ + if (((osp->rxcnt % usbp->epc[ep]->out_maxsize) == 0) && + (osp->rxsize < osp->totsize)) { + osp->rxsize = osp->totsize - osp->rxsize; + osp->rxcnt = 0; + osalSysLockFromISR(); + usb_lld_start_out(usbp, ep); + osalSysUnlockFromISR(); + return; + } + } + + /* End on OUT transfer.*/ + _usb_isr_invoke_out_cb(usbp, ep); + } +} + +/** + * @brief Isochronous IN transfer failed handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void otg_isoc_in_failed_handler(USBDriver *usbp) { + usbep_t ep; + at32_otg_t *otgp = usbp->otg; + + for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { + if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYP_MASK) == DIEPCTL_EPTYP_ISO) && + ((otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) != 0)) { + /* Endpoint enabled -> ISOC IN transfer failed.*/ + /* Disable endpoint.*/ + otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPDIS | DIEPCTL_SNAK); + while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) + ; + + /* Flush FIFO.*/ + otg_txfifo_flush(usbp, ep); + + /* Prepare data for next frame.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + } +} + +/** + * @brief Isochronous OUT transfer failed handler. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void otg_isoc_out_failed_handler(USBDriver *usbp) { + usbep_t ep; + at32_otg_t *otgp = usbp->otg; + + for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { + if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) && + ((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) { +#if 0 + /* Endpoint enabled -> ISOC OUT transfer failed.*/ + /* Disable endpoint.*/ + /* CHTODO:: Core stucks here */ + otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK); + while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) + ; +#endif + /* Prepare transfer for next frame.*/ + _usb_isr_invoke_out_cb(usbp, ep); + } + } +} + +/** + * @brief OTG shared ISR. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void usb_lld_serve_interrupt(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + uint32_t sts, src; + + sts = otgp->GINTSTS; + sts &= otgp->GINTMSK; + otgp->GINTSTS = sts; + + /* Reset interrupt handling.*/ + if (sts & GINTSTS_USBRST) { + /* Default reset action.*/ + _usb_reset(usbp); + + /* Preventing execution of more handlers, the core has been reset.*/ + return; + } + + /* Wake-up handling.*/ + if (sts & GINTSTS_WKUPINT) { + /* If clocks are gated off, turn them back on (may be the case if + coming out of suspend mode).*/ + if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) { + /* Set to zero to un-gate the USB core clocks.*/ + otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK); + } + + /* Clear the Remote Wake-up Signaling.*/ + otgp->DCTL &= ~DCTL_RWUSIG; + + _usb_wakeup(usbp); + } + + /* Suspend handling.*/ + if (sts & GINTSTS_USBSUSP) { + /* Stopping all ongoing transfers.*/ + otg_disable_ep(usbp); + + /* Default suspend action.*/ + _usb_suspend(usbp); + } + + /* Enumeration done.*/ + if (sts & GINTSTS_ENUMDNE) { + /* Full or High speed timing selection.*/ + if ((otgp->DSTS & DSTS_ENUMSPD_MASK) == DSTS_ENUMSPD_HS_480) { + otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | + GUSBCFG_TRDT(TRDT_VALUE_HS); + } + else { + otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | + GUSBCFG_TRDT(TRDT_VALUE_FS); + } + } + + /* SOF interrupt handling.*/ + if (sts & GINTSTS_SOF) { + /* SOF interrupt was used to detect resume of the USB bus after issuing a + remote wake up of the host, therefore we disable it again.*/ + if (usbp->config->sof_cb == NULL) { + otgp->GINTMSK &= ~GINTMSK_SOFM; + } + if (usbp->state == USB_SUSPENDED) { + /* If clocks are gated off, turn them back on (may be the case if + coming out of suspend mode).*/ + if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) { + /* Set to zero to un-gate the USB core clocks.*/ + otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK); + } + _usb_wakeup(usbp); + } + + _usb_isr_invoke_sof_cb(usbp); + } + + /* Isochronous IN failed handling */ + if (sts & GINTSTS_IISOIXFR) { + otg_isoc_in_failed_handler(usbp); + } + + /* Isochronous OUT failed handling */ + if (sts & GINTSTS_IISOOXFR) { + otg_isoc_out_failed_handler(usbp); + } + + /* Performing the whole FIFO emptying in the ISR, it is advised to keep + this IRQ at a very low priority level.*/ + if ((sts & GINTSTS_RXFLVL) != 0U) { + otg_rxfifo_handler(usbp); + } + + /* IN/OUT endpoints event handling.*/ + src = otgp->DAINT; + if (sts & GINTSTS_OEPINT) { + if (src & (1 << 16)) + otg_epout_handler(usbp, 0); + if (src & (1 << 17)) + otg_epout_handler(usbp, 1); + if (src & (1 << 18)) + otg_epout_handler(usbp, 2); + if (src & (1 << 19)) + otg_epout_handler(usbp, 3); +#if USB_MAX_ENDPOINTS >= 4 + if (src & (1 << 20)) + otg_epout_handler(usbp, 4); +#endif +#if USB_MAX_ENDPOINTS >= 5 + if (src & (1 << 21)) + otg_epout_handler(usbp, 5); +#endif +#if USB_MAX_ENDPOINTS >= 6 + if (src & (1 << 22)) + otg_epout_handler(usbp, 6); +#endif +#if USB_MAX_ENDPOINTS >= 7 + if (src & (1 << 23)) + otg_epout_handler(usbp, 7); +#endif +#if USB_MAX_ENDPOINTS >= 8 + if (src & (1 << 24)) + otg_epout_handler(usbp, 8); +#endif + } + if (sts & GINTSTS_IEPINT) { + if (src & (1 << 0)) + otg_epin_handler(usbp, 0); + if (src & (1 << 1)) + otg_epin_handler(usbp, 1); + if (src & (1 << 2)) + otg_epin_handler(usbp, 2); + if (src & (1 << 3)) + otg_epin_handler(usbp, 3); +#if USB_MAX_ENDPOINTS >= 4 + if (src & (1 << 4)) + otg_epin_handler(usbp, 4); +#endif +#if USB_MAX_ENDPOINTS >= 5 + if (src & (1 << 5)) + otg_epin_handler(usbp, 5); +#endif +#if USB_MAX_ENDPOINTS >= 6 + if (src & (1 << 6)) + otg_epin_handler(usbp, 6); +#endif +#if USB_MAX_ENDPOINTS >= 7 + if (src & (1 << 7)) + otg_epin_handler(usbp, 7); +#endif +#if USB_MAX_ENDPOINTS >= 8 + if (src & (1 << 8)) + otg_epin_handler(usbp, 8); +#endif + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_USB_USE_OTG1 || defined(__DOXYGEN__) +/** + * @brief OTG1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_OTG1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + usb_lld_serve_interrupt(&USBD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if AT32_USB_USE_OTG2 || defined(__DOXYGEN__) +/** + * @brief OTG2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_OTG2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + usb_lld_serve_interrupt(&USBD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + + /* Driver initialization.*/ +#if AT32_USB_USE_OTG1 + usbObjectInit(&USBD1); + USBD1.otg = OTG_FS; + USBD1.otgparams = &fsparams; + +#endif + +#if AT32_USB_USE_OTG2 + usbObjectInit(&USBD2); + USBD2.otg = OTG_HS; + USBD2.otgparams = &hsparams; +#endif +} + +/** + * @brief Configures and activates the USB peripheral. + * @note Starting the OTG cell can be a slow operation carried out with + * interrupts disabled, perform it before starting time-critical + * operations. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + + if (usbp->state == USB_STOP) { + /* Clock activation.*/ + +#if AT32_USB_USE_OTG1 + if (&USBD1 == usbp) { + /* OTG FS clock enable and reset.*/ + crmEnableOTG_FS(true); + crmResetOTG_FS(); + + /* Enables IRQ vector.*/ + nvicEnableVector(AT32_OTG1_NUMBER, AT32_USB_OTG1_IRQ_PRIORITY); + + /* - Forced device mode. + - USB turn-around time = TRDT_VALUE_FS. + - Full Speed 1.1 PHY.*/ + otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | + GUSBCFG_PHYSEL; + + /* 48MHz 1.1 PHY.*/ + otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; + } +#endif + +#if AT32_USB_USE_OTG2 + if (&USBD2 == usbp) { + /* OTG HS clock enable and reset.*/ + crmEnableOTG_HS(true); + crmResetOTG_HS(); + + /* ULPI clock is managed depending on the presence of an external + PHY.*/ +#if defined(BOARD_OTG2_USES_ULPI) + crmEnableOTG_HSULPI(true); +#else + /* Workaround for the problem described here: + http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798.*/ + crmDisableOTG_HSULPI(); +#endif + + /* Enables IRQ vector.*/ + nvicEnableVector(AT32_OTG2_NUMBER, AT32_USB_OTG2_IRQ_PRIORITY); + + /* - Forced device mode. + - USB turn-around time = TRDT_VALUE_HS or TRDT_VALUE_FS.*/ +#if defined(BOARD_OTG2_USES_ULPI) + /* High speed ULPI PHY.*/ + otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_HS) | + GUSBCFG_SRPCAP | GUSBCFG_HNPCAP; +#else + otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | + GUSBCFG_PHYSEL; +#endif + +#if defined(BOARD_OTG2_USES_ULPI) +#if AT32_USE_USB_OTG2_HS + /* USB 2.0 High Speed PHY in HS mode.*/ + otgp->DCFG = 0x02200000 | DCFG_DSPD_HS; +#else + /* USB 2.0 High Speed PHY in FS mode.*/ + otgp->DCFG = 0x02200000 | DCFG_DSPD_HS_FS; +#endif +#else + /* 48MHz 1.1 PHY.*/ + otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; +#endif + } +#endif + + /* PHY enabled.*/ + otgp->PCGCCTL = 0; + + /* VBUS sensing and transceiver enabled.*/ + otgp->GOTGCTL = GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; + +#if defined(BOARD_OTG2_USES_ULPI) +#if AT32_USB_USE_OTG1 + if (&USBD1 == usbp) { + otgp->GCCFG = GCCFG_INIT_VALUE; + } +#endif + +#if AT32_USB_USE_OTG2 + if (&USBD2 == usbp) { + otgp->GCCFG = 0; + } +#endif +#else + otgp->GCCFG = GCCFG_INIT_VALUE; +#endif + + /* Soft core reset.*/ + otg_core_reset(usbp); + + /* Interrupts on TXFIFOs half empty.*/ + otgp->GAHBCFG = 0; + + /* Endpoints re-initialization.*/ + otg_disable_ep(usbp); + + /* Clear all pending Device Interrupts, only the USB Reset interrupt + is required initially.*/ + otgp->DIEPMSK = 0; + otgp->DOEPMSK = 0; + otgp->DAINTMSK = 0; + if (usbp->config->sof_cb == NULL) + otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | + GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | + GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM; + else + otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | + GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | + GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM | + GINTMSK_SOFM; + + /* Clears all pending IRQs, if any. */ + otgp->GINTSTS = 0xFFFFFFFF; + + /* Global interrupts enable.*/ + otgp->GAHBCFG |= GAHBCFG_GINTMSK; + } +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + + /* If in ready state then disables the USB clock.*/ + if (usbp->state != USB_STOP) { + + /* Disabling all endpoints in case the driver has been stopped while + active.*/ + otg_disable_ep(usbp); + + otgp->DAINTMSK = 0; + otgp->GAHBCFG = 0; + otgp->GCCFG = 0; + +#if AT32_USB_USE_OTG1 + if (&USBD1 == usbp) { + nvicDisableVector(AT32_OTG1_NUMBER); + crmDisableOTG_FS(); + } +#endif + +#if AT32_USB_USE_OTG2 + if (&USBD2 == usbp) { + nvicDisableVector(AT32_OTG2_NUMBER); + crmDisableOTG_HS(); +#if defined(BOARD_OTG2_USES_ULPI) + crmDisableOTG_HSULPI(); +#endif + } +#endif + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + unsigned i; + at32_otg_t *otgp = usbp->otg; + + /* Flush the Tx FIFO.*/ + otg_txfifo_flush(usbp, 0); + + /* Endpoint interrupts all disabled and cleared.*/ + otgp->DIEPEMPMSK = 0; + otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); + + /* All endpoints in NAK mode, interrupts cleared.*/ + for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { + otgp->ie[i].DIEPCTL = DIEPCTL_SNAK; + otgp->oe[i].DOEPCTL = DOEPCTL_SNAK; + otgp->ie[i].DIEPINT = 0xFFFFFFFF; + otgp->oe[i].DOEPINT = 0xFFFFFFFF; + } + + /* Resets the FIFO memory allocator.*/ + otg_ram_reset(usbp); + + /* Receive FIFO size initialization, the address is always zero.*/ + otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size; + otg_rxfifo_flush(usbp); + + /* Resets the device address to zero.*/ + otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0); + + /* Enables also EP-related interrupt sources.*/ + otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM; + otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM; + otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; + + /* EP0 initialization, it is a special case.*/ + usbp->epc[0] = &ep0config; + otgp->oe[0].DOEPTSIZ = DOEPTSIZ_STUPCNT(3); + otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL | + DOEPCTL_MPSIZ(ep0config.out_maxsize); + otgp->ie[0].DIEPTSIZ = 0; + otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL | + DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize); + otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) | + DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, + ep0config.in_maxsize / 4)); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + at32_otg_t *otgp = usbp->otg; + + otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address); +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + uint32_t ctl, fsize; + at32_otg_t *otgp = usbp->otg; + + /* IN and OUT common parameters.*/ + switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_CTRL: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL; + break; + case USB_EP_MODE_TYPE_ISOC: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO; + break; + case USB_EP_MODE_TYPE_BULK: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK; + break; + case USB_EP_MODE_TYPE_INTR: + ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR; + break; + default: + return; + } + + /* OUT endpoint activation or deactivation.*/ + otgp->oe[ep].DOEPTSIZ = 0; + if (usbp->epc[ep]->out_state != NULL) { + otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize); + otgp->DAINTMSK |= DAINTMSK_OEPM(ep); + } + else { + otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP; + otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep); + } + + /* IN endpoint activation or deactivation.*/ + otgp->ie[ep].DIEPTSIZ = 0; + if (usbp->epc[ep]->in_state != NULL) { + /* FIFO allocation for the IN endpoint.*/ + fsize = usbp->epc[ep]->in_maxsize / 4; + if (usbp->epc[ep]->in_multiplier > 1) + fsize *= usbp->epc[ep]->in_multiplier; + otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) | + DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize)); + otg_txfifo_flush(usbp, ep); + + otgp->ie[ep].DIEPCTL = ctl | + DIEPCTL_TXFNUM(ep) | + DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize); + otgp->DAINTMSK |= DAINTMSK_IEPM(ep); + } + else { + otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/ + otg_txfifo_flush(usbp, ep); + otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP; + otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep); + } +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + + /* Resets the FIFO memory allocator.*/ + otg_ram_reset(usbp); + + /* Disabling all endpoints.*/ + otg_disable_ep(usbp); +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + uint32_t ctl; + + (void)usbp; + + ctl = usbp->otg->oe[ep].DOEPCTL; + if (!(ctl & DOEPCTL_USBAEP)) + return EP_STATUS_DISABLED; + if (ctl & DOEPCTL_STALL) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + uint32_t ctl; + + (void)usbp; + + ctl = usbp->otg->ie[ep].DIEPCTL; + if (!(ctl & DIEPCTL_USBAEP)) + return EP_STATUS_DISABLED; + if (ctl & DIEPCTL_STALL) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + + memcpy(buf, usbp->epc[ep]->setup_buf, 8); +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + uint32_t pcnt, rxsize; + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + /* Transfer initialization.*/ + osp->totsize = osp->rxsize; + if ((ep == 0) && (osp->rxsize > EP0_MAX_OUTSIZE)) + osp->rxsize = EP0_MAX_OUTSIZE; + + /* Transaction size is rounded to a multiple of packet size because the + following requirement in the RM: + "For OUT transfers, the transfer size field in the endpoint's transfer + size register must be a multiple of the maximum packet size of the + endpoint, adjusted to the Word boundary".*/ + pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1U) / + usbp->epc[ep]->out_maxsize; + rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU; + + /* Setting up transaction parameters in DOEPTSIZ.*/ + usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | + DOEPTSIZ_XFRSIZ(rxsize); + + /* Special case of isochronous endpoint.*/ + if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { + /* Odd/even bit toggling for isochronous endpoint.*/ + if (usbp->otg->DSTS & DSTS_FNSOF_ODD) + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SEVNFRM; + else + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SODDFRM; + } + + /* Starting operation.*/ + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK; +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + /* Transfer initialization.*/ + isp->totsize = isp->txsize; + if (isp->txsize == 0) { + /* Special case, sending zero size packet.*/ + usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0); + } + else { + if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE)) + isp->txsize = EP0_MAX_INSIZE; + + /* Normal case.*/ + uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) / + usbp->epc[ep]->in_maxsize; + /* CHTODO: Support more than one packet per frame for isochronous transfers.*/ + usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MCNT(1) | DIEPTSIZ_PKTCNT(pcnt) | + DIEPTSIZ_XFRSIZ(isp->txsize); + } + + /* Special case of isochronous endpoint.*/ + if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { + /* Odd/even bit toggling.*/ + if (usbp->otg->DSTS & DSTS_FNSOF_ODD) + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SEVNFRM; + else + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SODDFRM; + } + + /* Starting operation.*/ + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; + usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep); +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL; +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL; +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + + usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL; +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + + usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL; +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h new file mode 100644 index 0000000000..d205b2be5a --- /dev/null +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h @@ -0,0 +1,592 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file OTGv1/hal_usb_lld.h + * @brief AT32 USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef HAL_USB_LLD_H +#define HAL_USB_LLD_H + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#include "at32_otg.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Status stage handling method. + */ +#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW + +/** + * @brief The address can be changed immediately upon packet reception. + */ +#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS + +/** + * @brief Method for set address acknowledge. + */ +#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief OTG1 driver enable switch. + * @details If set to @p TRUE the support for OTG_FS is included. + * @note The default is @p FALSE + */ +#if !defined(AT32_USB_USE_OTG1) || defined(__DOXYGEN__) +#define AT32_USB_USE_OTG1 FALSE +#endif + +/** + * @brief OTG2 driver enable switch. + * @details If set to @p TRUE the support for OTG_HS is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_USB_USE_OTG2) || defined(__DOXYGEN__) +#define AT32_USB_USE_OTG2 FALSE +#endif + +/** + * @brief OTG1 interrupt priority level setting. + */ +#if !defined(AT32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#endif + +/** + * @brief OTG2 interrupt priority level setting. + */ +#if !defined(AT32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#endif + +/** + * @brief OTG1 RX shared FIFO size. + * @note Must be a multiple of 4. + */ +#if !defined(AT32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__) +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#endif + +/** + * @brief OTG2 RX shared FIFO size. + * @note Must be a multiple of 4. + */ +#if !defined(AT32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__) +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#endif + +/** + * @brief Enables HS mode on OTG2 else FS mode. + * @note The default is @p TRUE. + * @note Has effect only if @p BOARD_OTG2_USES_ULPI is defined. + */ +#if !defined(AT32_USE_USB_OTG2_HS) || defined(__DOXYGEN__) +#define AT32_USE_USB_OTG2_HS TRUE +#endif + +/** + * @brief Exception priority level during TXFIFOs operations. + * @note Because an undocumented silicon behavior the operation of + * copying a packet into a TXFIFO must not be interrupted by + * any other operation on the OTG peripheral. + * This parameter represents the priority mask during copy + * operations. The default value only allows to call USB + * functions from callbacks invoked from USB ISR handlers. + * If you need to invoke USB functions from other handlers + * then raise this priority mast to the same level of the + * handler you need to use. + * @note The value zero means disabled, when disabled calling USB + * functions is only safe from thread level or from USB + * callbacks. + */ +#if !defined(AT32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__) +#define AT32_USB_OTGFIFO_FILL_BASEPRI 0 +#endif + +/** + * @brief Host wake-up procedure duration. + */ +#if !defined(AT32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__) +#define AT32_USB_HOST_WAKEUP_DURATION 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks.*/ +#if !defined(AT32_OTG_STEPPING) +#error "AT32_OTG_STEPPING not defined in registry" +#endif + +#if (AT32_OTG_STEPPING < 1) || (AT32_OTG_STEPPING > 2) +#error "unsupported AT32_OTG_STEPPING" +#endif + +/* +#if !defined(AT32_HAS_OTG1) || !defined(AT32_HAS_OTG2) +#error "AT32_HAS_OTGx not defined in registry" +#endif +*/ + +#if AT32_HAS_OTG1 && !defined(AT32_OTG1_ENDPOINTS) +#error "AT32_OTG1_ENDPOINTS not defined in registry" +#endif + +#if AT32_HAS_OTG2 && !defined(AT32_OTG2_ENDPOINTS) +#error "AT32_OTG2_ENDPOINTS not defined in registry" +#endif + +#if AT32_HAS_OTG1 && !defined(AT32_OTG1_FIFO_MEM_SIZE) +#error "AT32_OTG1_FIFO_MEM_SIZE not defined in registry" +#endif + +#if AT32_HAS_OTG2 && !defined(AT32_OTG2_FIFO_MEM_SIZE) +#error "AT32_OTG2_FIFO_MEM_SIZE not defined in registry" +#endif + +#if (AT32_USB_USE_OTG1 && !defined(AT32_OTG1_HANDLER)) || \ + (AT32_USB_USE_OTG2 && !defined(AT32_OTG2_HANDLER)) +#error "AT32_OTGx_HANDLER not defined in registry" +#endif + +#if (AT32_USB_USE_OTG1 && !defined(AT32_OTG1_NUMBER)) || \ + (AT32_USB_USE_OTG2 && !defined(AT32_OTG2_NUMBER)) +#error "AT32_OTGx_NUMBER not defined in registry" +#endif + +#if AT32_USB_USE_OTG1 && !AT32_HAS_OTG1 +#error "OTG1 not present in the selected device" +#endif + +#if AT32_USB_USE_OTG2 && !AT32_HAS_OTG2 +#error "OTG2 not present in the selected device" +#endif + +#if !AT32_USB_USE_OTG1 && !AT32_USB_USE_OTG2 +#error "USB driver activated but no USB peripheral assigned" +#endif + +/* Maximum endpoint address.*/ +#if AT32_HAS_OTG1 && AT32_USB_USE_OTG1 && AT32_HAS_OTG2 && AT32_USB_USE_OTG2 + #if AT32_OTG1_ENDPOINTS < AT32_OTG2_ENDPOINTS + #define USB_MAX_ENDPOINTS AT32_OTG2_ENDPOINTS + #else + #define USB_MAX_ENDPOINTS AT32_OTG1_ENDPOINTS + #endif +#elif AT32_HAS_OTG1 && AT32_USB_USE_OTG1 + #define USB_MAX_ENDPOINTS AT32_OTG1_ENDPOINTS +#elif AT32_HAS_OTG2 && AT32_USB_USE_OTG2 + #define USB_MAX_ENDPOINTS AT32_OTG2_ENDPOINTS +#endif + +#if AT32_USB_USE_OTG1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_USB_OTG1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to OTG1" +#endif + +#if AT32_USB_USE_OTG2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_USB_OTG2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to OTG2" +#endif + +#if (AT32_USB_OTG1_RX_FIFO_SIZE & 3) != 0 +#error "OTG1 RX FIFO size must be a multiple of 4" +#endif + +#if (AT32_USB_OTG2_RX_FIFO_SIZE & 3) != 0 +#error "OTG2 RX FIFO size must be a multiple of 4" +#endif + +/* Allowing for a small tolerance.*/ +#if AT32_USBCLK < 47880000 || AT32_USBCLK > 48120000 +#error "the USB OTG driver requires a 48MHz clock" +#endif + +#if (AT32_USB_HOST_WAKEUP_DURATION < 2) || (AT32_USB_HOST_WAKEUP_DURATION > 15) +#error "invalid AT32_USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Peripheral-specific parameters block. + */ +typedef struct { + uint32_t rx_fifo_size; + uint32_t otg_ram_size; + uint32_t num_endpoints; +} at32_otg_params_t; + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Total transmit transfer size. + */ + size_t totsize; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Total receive transfer size. + */ + size_t totsize; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if callback is not required. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if callback is not required. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /** + * @brief Determines the space allocated for the TXFIFO as multiples of + * the packet size (@p in_maxsize). Note that zero is interpreted + * as one for simplicity and robustness. + */ + uint16_t in_multiplier; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; + /** + * @brief State of the driver when a suspend happened. + */ + usbstate_t saved_state; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the OTG peripheral associated to this driver. + */ + at32_otg_t *otg; + /** + * @brief Peripheral-specific parameters. + */ + const at32_otg_params_t *otgparams; + /** + * @brief Pointer to the next address in the packet memory. + */ + uint32_t pmnext; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Connects the USB device. + * + * @notapi + */ +#if (AT32_OTG_STEPPING == 1) || defined(__DOXYGEN__) +#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN) +#else +#define usb_lld_connect_bus(usbp) ((usbp)->otg->DCTL &= ~DCTL_SDIS) +#endif + +/** + * @brief Disconnect the USB device. + * + * @notapi + */ +#if (AT32_OTG_STEPPING == 1) || defined(__DOXYGEN__) +#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN) +#else +#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->DCTL |= DCTL_SDIS) +#endif + +/** + * @brief Start of host wake-up procedure. + * + * @notapi + */ +#define usb_lld_wakeup_host(usbp) \ + do { \ + (usbp)->otg->DCTL |= DCTL_RWUSIG; \ + /* remote wakeup doesn't trigger the wakeup interrupt, therefore + we use the SOF interrupt to detect resume of the bus.*/ \ + (usbp)->otg->GINTSTS |= GINTSTS_SOF; \ + (usbp)->otg->GINTMSK |= GINTMSK_SOFM; \ + osalThreadSleepMilliseconds(AT32_USB_HOST_WAKEUP_DURATION); \ + (usbp)->otg->DCTL &= ~DCTL_RWUSIG; \ + } while (false) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_USB_USE_OTG1 && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#if AT32_USB_USE_OTG2 && !defined(__DOXYGEN__) +extern USBDriver USBD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* HAL_USB_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/RTCv2/driver.mk b/os/hal/ports/AT32/LLD/RTCv2/driver.mk new file mode 100644 index 0000000000..d351de588f --- /dev/null +++ b/os/hal/ports/AT32/LLD/RTCv2/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/RTCv2 diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c new file mode 100644 index 0000000000..e9e0c19358 --- /dev/null +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c @@ -0,0 +1,783 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. +*/ + +/** + * @file RTCv2/hal_rtc_lld.c + * @brief AT32 RTC low level driver. + * + * @addtogroup RTC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define ERTC_TIME_AMPM_OFFSET 22 +#define ERTC_TIME_HT_OFFSET 20 +#define ERTC_TIME_HU_OFFSET 16 +#define ERTC_TIME_MT_OFFSET 12 +#define ERTC_TIME_MU_OFFSET 8 +#define ERTC_TIME_ST_OFFSET 4 +#define ERTC_TIME_SU_OFFSET 0 + +#define ERTC_DATE_YT_OFFSET 20 +#define ERTC_DATE_YU_OFFSET 16 +#define ERTC_DATE_WK_OFFSET 13 +#define ERTC_DATE_MT_OFFSET 12 +#define ERTC_DATE_MU_OFFSET 8 +#define ERTC_DATE_DT_OFFSET 4 +#define ERTC_DATE_DU_OFFSET 0 + +#define ERTC_CTRL_BPR_OFFSET 18 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Beginning of configuration procedure. + * + * @notapi + */ +static void rtc_enter_init(void) { + + RTCD1.rtc->STS |= ERTC_STS_IMEN; + while ((RTCD1.rtc->STS & ERTC_STS_IMF) == 0) + ; +} + +/** + * @brief Finalizing of configuration procedure. + * + * @notapi + */ +static inline void rtc_exit_init(void) { + + RTCD1.rtc->STS &= ~ERTC_STS_IMEN; +} + +/** + * @brief Converts time from TIME register encoding to timespec. + * + * @param[in] time TIME register value + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +static void rtc_decode_time(uint32_t time, RTCDateTime *timespec) { + uint32_t n; + + n = ((time >> ERTC_TIME_HT_OFFSET) & 3) * 36000000; + n += ((time >> ERTC_TIME_HU_OFFSET) & 15) * 3600000; + n += ((time >> ERTC_TIME_MT_OFFSET) & 7) * 600000; + n += ((time >> ERTC_TIME_MU_OFFSET) & 15) * 60000; + n += ((time >> ERTC_TIME_ST_OFFSET) & 7) * 10000; + n += ((time >> ERTC_TIME_SU_OFFSET) & 15) * 1000; + timespec->millisecond = n; +} + +/** + * @brief Converts date from DATE register encoding to timespec. + * + * @param[in] date DATE register value + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +static void rtc_decode_date(uint32_t date, RTCDateTime *timespec) { + + timespec->year = (((date >> ERTC_DATE_YT_OFFSET) & 15) * 10) + + ((date >> ERTC_DATE_YU_OFFSET) & 15); + timespec->month = (((date >> ERTC_DATE_MT_OFFSET) & 1) * 10) + + ((date >> ERTC_DATE_MU_OFFSET) & 15); + timespec->day = (((date >> ERTC_DATE_DT_OFFSET) & 3) * 10) + + ((date >> ERTC_DATE_DU_OFFSET) & 15); + timespec->dayofweek = (date >> ERTC_DATE_WK_OFFSET) & 7; +} + +/** + * @brief Converts time from timespec to TIME register encoding. + * + * @param[in] timespec pointer to a @p RTCDateTime structure + * @return the TIME register encoding. + * + * @notapi + */ +static uint32_t rtc_encode_time(const RTCDateTime *timespec) { + uint32_t n, time = 0; + + /* Subseconds cannot be set.*/ + n = timespec->millisecond / 1000; + + /* Seconds conversion.*/ + time = time | ((n % 10) << ERTC_TIME_SU_OFFSET); + n /= 10; + time = time | ((n % 6) << ERTC_TIME_ST_OFFSET); + n /= 6; + + /* Minutes conversion.*/ + time = time | ((n % 10) << ERTC_TIME_MU_OFFSET); + n /= 10; + time = time | ((n % 6) << ERTC_TIME_MT_OFFSET); + n /= 6; + + /* Hours conversion.*/ + time = time | ((n % 10) << ERTC_TIME_HU_OFFSET); + n /= 10; + time = time | (n << ERTC_TIME_HT_OFFSET); + + return time; +} + +/** + * @brief Converts a date from timespec to DATE register encoding. + * + * @param[in] timespec pointer to a @p RTCDateTime structure + * @return the DATE register encoding. + * + * @notapi + */ +static uint32_t rtc_encode_date(const RTCDateTime *timespec) { + uint32_t n, date = 0; + + /* Year conversion. Note, only years last two digits are considered.*/ + n = timespec->year; + date = date | ((n % 10) << ERTC_DATE_YU_OFFSET); + n /= 10; + date = date | ((n % 10) << ERTC_DATE_YT_OFFSET); + + /* Months conversion.*/ + n = timespec->month; + date = date | ((n % 10) << ERTC_DATE_MU_OFFSET); + n /= 10; + date = date | ((n % 10) << ERTC_DATE_MT_OFFSET); + + /* Days conversion.*/ + n = timespec->day; + date = date | ((n % 10) << ERTC_DATE_DU_OFFSET); + n /= 10; + date = date | ((n % 10) << ERTC_DATE_DT_OFFSET); + + /* Days of week conversion.*/ + date = date | (timespec->dayofweek << ERTC_DATE_WK_OFFSET); + + return date; +} + +#if RTC_HAS_STORAGE == TRUE +static size_t _getsize(void *instance) { + + (void)instance; + + return (size_t)AT32_ERTC_STORAGE_SIZE; +} + +static ps_error_t _read(void *instance, ps_offset_t offset, + size_t n, uint8_t *rp) { + volatile uint32_t *bpr = &((RTCDriver *)instance)->rtc->BPR1; + unsigned i; + + osalDbgCheck((instance != NULL) && (rp != NULL)); + osalDbgCheck((n > 0U) && (n <= AT32_ERTC_STORAGE_SIZE)); + osalDbgCheck((offset < AT32_ERTC_STORAGE_SIZE) && + (offset + n <= AT32_ERTC_STORAGE_SIZE)); + + for (i = 0; i < (unsigned)n; i++) { + unsigned index = ((unsigned)offset + i) / sizeof (uint32_t); + unsigned shift = ((unsigned)offset + i) % sizeof (uint32_t); + *rp++ = (uint8_t)(bpr[index] >> (shift * 8U)); + } + + return PS_NO_ERROR; +} + +static ps_error_t _write(void *instance, ps_offset_t offset, + size_t n, const uint8_t *wp) { + volatile uint32_t *bpr = &((RTCDriver *)instance)->rtc->BPR1; + unsigned i; + + osalDbgCheck((instance != NULL) && (wp != NULL)); + osalDbgCheck((n > 0U) && (n <= AT32_ERTC_STORAGE_SIZE)); + osalDbgCheck((offset < AT32_ERTC_STORAGE_SIZE) && + (offset + n <= AT32_ERTC_STORAGE_SIZE)); + + for (i = 0; i < (unsigned)n; i++) { + unsigned index = ((unsigned)offset + i) / sizeof (uint32_t); + unsigned shift = ((unsigned)offset + i) % sizeof (uint32_t); + uint32_t regval = bpr[index]; + regval &= ~(0xFFU << (shift * 8U)); + regval |= (uint32_t)*wp++ << (shift * 8U); + bpr[index] = regval; + } + + return PS_NO_ERROR; +} + +/** + * @brief VMT for the RTC storage file interface. + */ +struct RTCDriverVMT _rtc_lld_vmt = { + (size_t)0, + _getsize, _read, _write +}; +#endif /* RTC_HAS_STORAGE == TRUE */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_ERTC_COMMON_HANDLER) +#if !defined(AT32_ERTC_SUPPRESS_COMMON_ISR) +/** + * @brief RTC common interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_ERTC_COMMON_HANDLER) { + uint32_t sts, clear; + + OSAL_IRQ_PROLOGUE(); + + clear = (0U + | ERTC_STS_TSF + | ERTC_STS_TSOF +#if defined(ERTC_STS_TP1F) + | ERTC_STS_TP1F +#endif +#if defined(ERTC_STS_WATF) + | ERTC_STS_WATF +#endif +#if defined(ERTC_STS_ALAF) + | ERTC_STS_ALAF +#endif +#if defined(ERTC_STS_ALBF) + | ERTC_STS_ALBF +#endif + ); + + sts = RTCD1.rtc->STS; + RTCD1.rtc->STS = sts & ~clear; + + exintClearGroup1(EXINT_MASK1(AT32_ERTC_ALARM_EXINT) | + EXINT_MASK1(AT32_ERTC_TAMP_STAMP_EXINT) | + EXINT_MASK1(AT32_ERTC_WKUP_EXINT)); + + if (RTCD1.callback != NULL) { + uint32_t ctrl = RTCD1.rtc->CTRL; + uint32_t tamp; + +#if defined(ERTC_STS_WATF) + if (((ctrl & ERTC_CTRL_WATIEN) != 0U) && ((sts & ERTC_STS_WATF) != 0U)) { + RTCD1.callback(&RTCD1, RTC_EVENT_WAKEUP); + } +#endif + +#if defined(ERTC_STS_ALAF) + if (((ctrl & ERTC_CTRL_ALAIEN) != 0U) && ((sts & ERTC_STS_ALAF) != 0U)) { + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_A); + } +#endif +#if defined(ERTC_STS_ALBF) + if (((ctrl & ERTC_CTRL_ALBIEN) != 0U) && ((sts & ERTC_STS_ALBF) != 0U)) { + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_B); + } +#endif + + if ((ctrl & ERTC_CTRL_TSIEN) != 0U) { + if ((sts & ERTC_STS_TSF) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TS); + } + if ((sts & ERTC_STS_TSOF) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TS_OVF); + } + } + +#if defined(ERTC_TAMP_TP1EN) + tamp = RTCD1.rtc->TAMP; + if ((tamp & ERTC_TAMP_TPIEN) != 0U) { +#if defined(ERTC_STS_TP1F) + if ((sts & ERTC_STS_TP1F) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); + } +#endif + } +#endif /* !defined(ERTC_TAMP_TP1EN) */ + } + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_ERTC_SUPPRESS_COMMON_ISR) */ + +#elif defined(AT32_ERTC_TAMP_STAMP_HANDLER) && \ + defined(AT32_ERTC_WKUP_HANDLER) && \ + defined(AT32_ERTC_ALARM_HANDLER) +/** + * @brief RTC TAMP/STAMP interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_ERTC_TAMP_STAMP_HANDLER) { + uint32_t sts, clear; + + OSAL_IRQ_PROLOGUE(); + + clear = (0U + | ERTC_STS_TSF + | ERTC_STS_TSOF +#if defined(ERTC_STS_TP1F) + | ERTC_STS_TP1F +#endif + ); + + sts = RTCD1.rtc->STS; + RTCD1.rtc->STS = sts & ~clear; + + exintClearGroup1(EXINT_MASK1(AT32_ERTC_TAMP_STAMP_EXINT)); + + if (RTCD1.callback != NULL) { + uint32_t ctrl, tamp; + + ctrl = RTCD1.rtc->CTRL; + if ((ctrl & ERTC_CTRL_TSIEN) != 0U) { + if ((sts & ERTC_STS_TSF) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TS); + } + if ((sts & ERTC_STS_TSOF) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TS_OVF); + } + } + +#if defined(ERTC_TAMP_TP1EN) + tamp = RTCD1.rtc->TAMP; + if ((tamp & ERTC_TAMP_TPIEN) != 0U) { +#if defined(ERTC_STS_TP1F) + if ((sts & ERTC_STS_TP1F) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); + } +#endif + } +#endif /* !defined(ERTC_TAMP_TP1EN) */ + } + + OSAL_IRQ_EPILOGUE(); +} +/** + * @brief RTC wakeup interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_ERTC_WKUP_HANDLER) { + uint32_t sts; + + OSAL_IRQ_PROLOGUE(); + + sts = RTCD1.rtc->STS; + RTCD1.rtc->STS = sts & ~ERTC_STS_WATF; + + exintClearGroup1(EXINT_MASK1(AT32_ERTC_WKUP_EXINT)); + + if (RTCD1.callback != NULL) { + uint32_t ctrl = RTCD1.rtc->CTRL; + + if (((ctrl & ERTC_CTRL_WATIEN) != 0U) && ((sts & ERTC_STS_WATF) != 0U)) { + RTCD1.callback(&RTCD1, RTC_EVENT_WAKEUP); + } + } + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief RTC alarm interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_ERTC_ALARM_HANDLER) { + uint32_t sts, clear; + + OSAL_IRQ_PROLOGUE(); + + clear = (0U +#if defined(ERTC_STS_ALAF) + | ERTC_STS_ALAF +#endif +#if defined(ERTC_STS_ALBF) + | ERTC_STS_ALBF +#endif + ); + + sts = RTCD1.rtc->STS; + RTCD1.rtc->STS = sts & ~clear; + + exintClearGroup1(EXINT_MASK1(AT32_ERTC_ALARM_EXINT)); + + if (RTCD1.callback != NULL) { + uint32_t ctrl = RTCD1.rtc->CTRL; +#if defined(ERTC_STS_ALAF) + if (((ctrl & ERTC_CTRL_ALAIEN) != 0U) && ((sts & ERTC_STS_ALAF) != 0U)) { + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_A); + } +#endif +#if defined(ERTC_STS_ALBF) + if (((ctrl & ERTC_CTRL_ALBIEN) != 0U) && ((sts & ERTC_STS_ALBF) != 0U)) { + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_B); + } +#endif + } + + OSAL_IRQ_EPILOGUE(); +} + +#else +#error "missing required RTC handlers definitions in IRQ" +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers. + * + * @notapi + */ +void rtc_lld_init(void) { + + /* RTC object initialization.*/ + rtcObjectInit(&RTCD1); + + /* RTC pointer initialization.*/ + RTCD1.rtc = ERTC; + + /* Disable write protection. */ + RTCD1.rtc->WP = 0xCA; + RTCD1.rtc->WP = 0x53; + + /* If calendar has not been initialized yet then proceed with the + initial setup.*/ + if (!(RTCD1.rtc->STS & ERTC_STS_INITF)) { + + rtc_enter_init(); + + RTCD1.rtc->CTRL = AT32_ERTC_CTRL_INIT; +#if defined(ERTC_TAMP_TP1EN) + RTCD1.rtc->TAMP = AT32_ERTC_TAMP_INIT; +#endif + RTCD1.rtc->STS = ERTC_STS_IMEN; /* Clearing all but ERTC_STS_IMEN. */ + RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS; + RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS; + + rtc_exit_init(); + } + else { + RTCD1.rtc->STS &= ~ERTC_STS_UPDF; + } + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + /* Enabling RTC-related EXINT lines.*/ + exintEnableGroup1(EXINT_MASK1(AT32_ERTC_ALARM_EXINT) | + EXINT_MASK1(AT32_ERTC_TAMP_STAMP_EXINT) | + EXINT_MASK1(AT32_ERTC_WKUP_EXINT), + EXINT_MODE_RISING_EDGE | EXINT_MODE_ACTION_INTERRUPT); + + /* IRQ vectors permanently assigned to this driver.*/ + AT32_ERTC_IRQ_ENABLE(); +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to set it on AT32 platform. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { + uint32_t date, time; + syssts_t sts; + + time = rtc_encode_time(timespec); + date = rtc_encode_date(timespec); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Writing the registers.*/ + rtc_enter_init(); + rtcp->rtc->TIME = time; + rtcp->rtc->DATE = date; + rtcp->rtc->CTRL = (rtcp->rtc->CTRL & ~(1U << ERTC_CTRL_BPR_OFFSET)) | + (timespec->dstflag << ERTC_CTRL_BPR_OFFSET); + rtc_exit_init(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get current time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { + uint32_t date, time, ctrl; + uint32_t subs; +#if AT32_ERTC_HAS_SUBSECONDS + uint32_t oldsbs, sbs; +#endif /* AT32_ERTC_HAS_SUBSECONDS */ + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Synchronization with the RTC and reading the registers, note + DATE must be read last.*/ + while ((rtcp->rtc->STS & ERTC_STS_UPDF) == 0) + ; +#if AT32_ERTC_HAS_SUBSECONDS + do +#endif /* AT32_ERTC_HAS_SUBSECONDS */ + { + oldsbs = rtcp->rtc->SBS; + time = rtcp->rtc->TIME; + date = rtcp->rtc->DATE; + } +#if AT32_ERTC_HAS_SUBSECONDS + while (oldsbs != (sbs = rtcp->rtc->SBS)); + (void) rtcp->rtc->DATE; +#endif /* AT32_ERTC_HAS_SUBSECONDS */ + ctrl = rtcp->rtc->CTRL; + rtcp->rtc->STS &= ~ERTC_STS_UPDF; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); + + /* Decoding day time, this starts the atomic read sequence, see "Reading + the calendar" in the RTC documentation.*/ + rtc_decode_time(time, timespec); + + /* If the RTC is capable of sub-second counting then the value is + normalized in milliseconds and added to the time.*/ +#if AT32_ERTC_HAS_SUBSECONDS + subs = (((AT32_ERTC_DIVB_VALUE - 1U) - sbs) * 1000U) / AT32_ERTC_DIVB_VALUE; +#else + subs = 0; +#endif /* AT32_ERTC_HAS_SUBSECONDS */ + timespec->millisecond += subs; + + /* Decoding date, this concludes the atomic read sequence.*/ + rtc_decode_date(date, timespec); + + /* Retrieving the DST bit.*/ + timespec->dstflag = (ctrl >> ERTC_CTRL_BPR_OFFSET) & 1; +} + +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) +/** + * @brief Set alarm time. + * @note Default value after BPR domain reset for both comparators is 0. + * @note Function does not performs any checks of alarm time validity. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure. + * @param[in] alarm alarm identifier. Can be 0 or 1. + * @param[in] alarmspec pointer to a @p RTCAlarm structure. + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + if (alarm == 0) { + if (alarmspec != NULL) { + rtcp->rtc->CTRL &= ~ERTC_CTRL_ALAEN; + while (!(rtcp->rtc->STS & ERTC_STS_ALAWF)) + ; + rtcp->rtc->ALA = alarmspec->alrmr; + rtcp->rtc->CTRL |= ERTC_CTRL_ALAEN; + rtcp->rtc->CTRL |= ERTC_CTRL_ALAIEN; + } + else { + rtcp->rtc->CTRL &= ~ERTC_CTRL_ALAIEN; + rtcp->rtc->CTRL &= ~ERTC_CTRL_ALAEN; + } + } +#if RTC_ALARMS > 1 + else { + if (alarmspec != NULL) { + rtcp->rtc->CTRL &= ~ERTC_CTRL_ALBEN; + while (!(rtcp->rtc->STS & ERTC_STS_ALBWF)) + ; + rtcp->rtc->ALB = alarmspec->alrmr; + rtcp->rtc->CTRL |= ERTC_CTRL_ALBEN; + rtcp->rtc->CTRL |= ERTC_CTRL_ALBIEN; + } + else { + rtcp->rtc->CTRL &= ~ERTC_CTRL_ALBIEN; + rtcp->rtc->CTRL &= ~ERTC_CTRL_ALBEN; + } + } +#endif /* RTC_ALARMS > 1 */ + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get alarm time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier. Can be 0 or 1. + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { + + if (alarm == 0) + alarmspec->alrmr = rtcp->rtc->ALA; +#if RTC_ALARMS > 1 + else + alarmspec->alrmr = rtcp->rtc->ALB; +#endif /* RTC_ALARMS > 1 */ +} +#endif /* RTC_ALARMS > 0 */ + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + + rtcp->callback = callback; +} + +#if AT32_ERTC_HAS_PERIODIC_WAKEUPS || defined(__DOXYGEN__) +/** + * @brief Sets time of periodic wakeup. + * @note Default value after BPR domain reset is 0x0000FFFF + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] wakeupspec pointer to a @p RTCWakeup structure + * + * @api + */ +void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + if (wakeupspec != NULL) { + osalDbgCheck(wakeupspec->wat != 0x30000); + + rtcp->rtc->CTRL &= ~ERTC_CTRL_WATEN; + rtcp->rtc->CTRL &= ~ERTC_CTRL_WATIEN; + while (!(rtcp->rtc->STS & ERTC_STS_WATWF)) + ; + rtcp->rtc->WAT = wakeupspec->wat & 0xFFFF; + rtcp->rtc->CTRL &= ~ERTC_CTRL_WATCLK; + rtcp->rtc->CTRL |= (wakeupspec->wat >> 16) & ERTC_CTRL_WATCLK; + rtcp->rtc->CTRL |= ERTC_CTRL_WATIEN; + rtcp->rtc->CTRL |= ERTC_CTRL_WATEN; + } + else { + rtcp->rtc->CTRL &= ~ERTC_CTRL_WATEN; + rtcp->rtc->CTRL &= ~ERTC_CTRL_WATIEN; + } + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Gets time of periodic wakeup. + * @note Default value after BPR domain reset is 0x0000FFFF + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] wakeupspec pointer to a @p RTCWakeup structure + * + * @api + */ +void ertcAT32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + wakeupspec->wat = 0; + wakeupspec->wat |= rtcp->rtc->WAT; + wakeupspec->wat |= (((uint32_t)rtcp->rtc->CTRL) & 0x7) << 16; + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} +#endif /* AT32_ERTC_HAS_PERIODIC_WAKEUPS */ + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h new file mode 100644 index 0000000000..f7bcdda1cd --- /dev/null +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h @@ -0,0 +1,249 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. +*/ + +/** + * @file RTCv2/hal_rtc_lld.h + * @brief AT32 RTC low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + * @{ + */ +/** + * @brief Callback support int the driver. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief Number of alarms available. + */ +#define RTC_ALARMS AT32_ERTC_NUM_ALARMS + +/** + * @brief Presence of a local persistent storage. + */ +#define RTC_HAS_STORAGE (AT32_ERTC_STORAGE_SIZE > 0) +/** @} */ + +/** + * @brief RTC DIV register initializer. + */ +#define RTC_DIV(a, s) ((((a) - 1) << 16) | ((s) - 1)) + +/** + * @name Alarm helper macros + * @{ + */ +#define RTC_ALRM_MASK4 (1U << 31) +#define RTC_ALRM_WKSEL (1U << 30) +#define RTC_ALRM_DT(n) ((n) << 28) +#define RTC_ALRM_DU(n) ((n) << 24) +#define RTC_ALRM_MASK3 (1U << 23) +#define RTC_ALRM_HT(n) ((n) << 20) +#define RTC_ALRM_HU(n) ((n) << 16) +#define RTC_ALRM_MASK2 (1U << 15) +#define RTC_ALRM_MT(n) ((n) << 12) +#define RTC_ALRM_MU(n) ((n) << 8) +#define RTC_ALRM_MASK1 (1U << 7) +#define RTC_ALRM_ST(n) ((n) << 4) +#define RTC_ALRM_SU(n) ((n) << 0) +/** @} */ + +/* Requires services from the EXINT driver.*/ +#if !defined(AT32_EXINT_REQUIRED) +#define AT32_EXINT_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief RTC DIVA register initialization. + * @note The default is calculated for a 32768Hz clock. + */ +#if !defined(AT32_ERTC_DIVA_VALUE) || defined(__DOXYGEN__) +#define AT32_ERTC_DIVA_VALUE 32 +#endif + +/** + * @brief RTC DIVB divider initialization. + * @note The default is calculated for a 32768Hz clock. + */ +#if !defined(AT32_ERTC_DIVB_VALUE) || defined(__DOXYGEN__) +#define AT32_ERTC_DIVB_VALUE 1024 +#endif + +/** + * @brief RTC CTRL register initialization value. + * @note Use this value to initialize features not directly handled by + * the RTC driver. + */ +#if !defined(AT32_ERTC_CTRL_INIT) || defined(__DOXYGEN__) +#define AT32_ERTC_CTRL_INIT 0 +#endif + +/** + * @brief RTC TAMP register initialization value. + * @note Use this value to initialize features not directly handled by + * the RTC driver. + * @note On some devices this values goes in the similar TAMP register. + */ +#if !defined(AT32_ERTC_TAMP_INIT) || defined(__DOXYGEN__) +#define AT32_ERTC_TAMP_INIT 0 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !AT32_HAS_ERTC +#error "RTC not present in the selected device" +#endif + +#if !defined(AT32_ERTCCLK) +#error "RTC clock not exported by HAL layer" +#endif + +#if AT32_PCLK1 < (AT32_ERTCCLK * 7) +#error "AT32_PCLK1 frequency is too low" +#endif + +/** + * @brief Initialization for the RTC_DIV register. + */ +#define AT32_ERTC_DIV_BITS RTC_DIV(AT32_ERTC_DIVA_VALUE, \ + AT32_ERTC_DIVB_VALUE) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_ALARM_A = 0, /** Alarm A. */ + RTC_EVENT_ALARM_B = 1, /** Alarm B. */ + RTC_EVENT_TS = 2, /** Time stamp. */ + RTC_EVENT_TS_OVF = 3, /** Time stamp overflow. */ + RTC_EVENT_TAMP1 = 4, /** Tamper 1. */ + RTC_EVENT_TAMP2 = 5, /** Tamper 2- */ + RTC_EVENT_TAMP3 = 6, /** Tamper 3. */ + RTC_EVENT_WAKEUP = 7 /** Wakeup. */ + } rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct hal_rtc_alarm { + /** + * @brief Type of an alarm as encoded in RTC ALx registers. + */ + uint32_t alrmr; +} RTCAlarm; + +#if AT32_ERTC_HAS_PERIODIC_WAKEUPS +/** + * @brief Type of a wakeup as encoded in RTC WAT register. + */ +typedef struct hal_rtc_wakeup { + /** + * @brief Wakeup as encoded in RTC WAT register. + * @note ((WAT == 0) || (WATCLK == 3)) are a forbidden combination. + * @note Bits 16..18 are copied in the CTRL bits 0..2 (WATCLK). + */ + uint32_t wat; +} RTCWakeup; +#endif + +/** + * @brief Implementation-specific @p RTCDriver fields. + */ +#define rtc_lld_driver_fields \ + /* Pointer to the RTC registers block.*/ \ + ERTC_TypeDef *rtc; \ + /* Callback pointer.*/ \ + rtccb_t callback + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); +#if RTC_SUPPORTS_CALLBACKS == TRUE + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); +#endif +#if RTC_ALARMS > 0 + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec); +#endif +#if AT32_ERTC_HAS_PERIODIC_WAKEUPS + void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec); + void ertcAT32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec); +#endif /* AT32_ERTC_HAS_PERIODIC_WAKEUPS */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/SPIv1/driver.mk b/os/hal/ports/AT32/LLD/SPIv1/driver.mk new file mode 100644 index 0000000000..fdf216ccdf --- /dev/null +++ b/os/hal/ports/AT32/LLD/SPIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv1 diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c new file mode 100644 index 0000000000..5a1398ef2d --- /dev/null +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c @@ -0,0 +1,617 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPIv1/hal_spi_v2_lld.c + * @brief AT32 SPI (v2) subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI1 driver identifier.*/ +#if AT32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI2 driver identifier.*/ +#if AT32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void spi_lld_configure(SPIDriver *spip) { + uint32_t ctrl1, ctrl2; + + /* Disabling SPI during (re)configuration.*/ + spip->spi->CTRL1 = 0U; + + /* Common CTRL1 and CTRL2 options.*/ + ctrl1 = spip->config->ctrl1 & ~(SPI_CTRL1_MSTEN | SPI_CTRL1_SPIEN); + ctrl2 = spip->config->ctrl2 | SPI_CTRL2_DMAREN | SPI_CTRL2_DMATEN; + + /* SPI setup.*/ + if (spip->config->slave == false) { + ctrl1 |= SPI_CTRL1_SWCSEN | SPI_CTRL1_SWCSIL | SPI_CTRL1_MSTEN; + ctrl2 |= SPI_CTRL2_HWCSOE; + } + + /* New configuration.*/ + spip->spi->CTRL2 = ctrl2; + spip->spi->CTRL1 = ctrl1; + spip->spi->CTRL1 = ctrl1 | SPI_CTRL1_SPIEN; +} + +/** + * @brief Stopping the SPI transaction. + * @note This is done nicely or by brutally resetting it depending on + * the mode and settings. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static msg_t spi_lld_stop_abort(SPIDriver *spip) { + + if (!spip->config->slave) { + /* Master mode, stopping gracefully.*/ + + /* Stopping TX DMA channel.*/ + dmaStreamDisable(spip->dmatx); + + /* Waiting for current frame completion then stop SPI.*/ + while ((spip->spi->STS & SPI_STS_BF) != 0U) { + } + + /* Now it is idle, stopping RX DMA channel.*/ + dmaStreamDisable(spip->dmarx); + } + else { + /* Slave mode, this will not be nice.*/ + + /* Stopping DMAs.*/ + dmaStreamDisable(spip->dmatx); + dmaStreamDisable(spip->dmarx); + + /* Resetting SPI, this will stop it for sure and leave it + in a clean state.*/ + if (false) { + } + +#if AT32_SPI_USE_SPI1 + else if (&SPID1 == spip) { + crmResetSPI1(); + } +#endif + +#if AT32_SPI_USE_SPI2 + else if (&SPID2 == spip) { + crmResetSPI2(); + } +#endif + + else { + osalDbgAssert(false, "invalid SPI instance"); + } + + /* Reconfiguring SPI.*/ + spi_lld_configure(spip); + } + + return HAL_RET_SUCCESS; +} + +/** + * @brief Shared end-of-rx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the STS register + */ +static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & AT32_DMA_STS_DTERRF) != 0) { +#if defined(AT32_SPI_DMA_ERROR_HOOK) + /* Hook first, if defined.*/ + AT32_SPI_DMA_ERROR_HOOK(spip); +#endif + + /* Aborting the transfer.*/ + (void) spi_lld_stop_abort(spip); + + /* Reporting the failure.*/ + __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); + } + else if (spip->config->circular) { + if ((flags & AT32_DMA_STS_HDTF) != 0U) { + /* Half buffer interrupt.*/ + __spi_isr_half_code(spip); + } + if ((flags & AT32_DMA_STS_FDTF) != 0U) { + /* End buffer interrupt.*/ + __spi_isr_full_code(spip); + } + } + else { + /* Stopping the transfer.*/ + (void) spi_lld_stop_abort(spip); + + /* Operation finished interrupt.*/ + __spi_isr_complete_code(spip); + } +} + +/** + * @brief Shared end-of-tx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the STS register + */ +static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & AT32_DMA_STS_DTERRF) != 0) { +#if defined(AT32_SPI_DMA_ERROR_HOOK) + /* Hook first, if defined.*/ + AT32_SPI_DMA_ERROR_HOOK(spip); +#endif + + /* Aborting the transfer.*/ + (void) spi_lld_stop_abort(spip); + + /* Reporting the failure.*/ + __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); + } +} + +/** + * @brief DMA streams allocation. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] rxstream stream to be allocated for RX + * @param[in] txstream stream to be allocated for TX + * @param[in] priority streams IRQ priority + * @return The operation status. + */ +static msg_t spi_lld_get_dma(SPIDriver *spip, uint32_t rxstream, + uint32_t txstream, uint32_t priority) { + + spip->dmarx = dmaStreamAllocI(rxstream, priority, + (at32_dmasts_t)spi_lld_serve_rx_interrupt, + (void *)spip); + if (spip->dmarx == NULL) { + return HAL_RET_NO_RESOURCE; + } + + spip->dmatx = dmaStreamAllocI(txstream, priority, + (at32_dmasts_t)spi_lld_serve_tx_interrupt, + (void *)spip); + if (spip->dmatx == NULL) { + dmaStreamFreeI(spip->dmarx); + return HAL_RET_NO_RESOURCE; + } + + return HAL_RET_SUCCESS; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if AT32_SPI_USE_SPI1 + spiObjectInit(&SPID1); + SPID1.spi = SPI1; + SPID1.dmarx = NULL; + SPID1.dmatx = NULL; + SPID1.rxdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI1_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + SPID1.txdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI1_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_DTERRIEN; +#endif + +#if AT32_SPI_USE_SPI2 + spiObjectInit(&SPID2); + SPID2.spi = SPI2; + SPID2.dmarx = NULL; + SPID2.dmatx = NULL; + SPID2.rxdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI2_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + SPID2.txdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI2_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_DTERRIEN; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_start(SPIDriver *spip) { + msg_t msg; + + /* Resetting TX pattern source.*/ + spip->txsource = (uint32_t)AT32_SPI_FILLER_PATTERN; + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { + if (false) { + } + +#if AT32_SPI_USE_SPI1 + else if (&SPID1 == spip) { + msg = spi_lld_get_dma(spip, + AT32_SPI_SPI1_RX_DMA_STREAM, + AT32_SPI_SPI1_TX_DMA_STREAM, + AT32_SPI_SPI1_IRQ_PRIORITY); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + crmEnableSPI1(true); + crmResetSPI1(); +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(spip->dmarx, AT32_SPI_SPI1_RX_DMAMUX_CHANNEL, AT32_DMAMUX_SPI1_RX); + dmaSetRequestSource(spip->dmatx, AT32_SPI_SPI1_TX_DMAMUX_CHANNEL, AT32_DMAMUX_SPI1_TX); +#endif + } +#endif + +#if AT32_SPI_USE_SPI2 + else if (&SPID2 == spip) { + msg = spi_lld_get_dma(spip, + AT32_SPI_SPI2_RX_DMA_STREAM, + AT32_SPI_SPI2_TX_DMA_STREAM, + AT32_SPI_SPI2_IRQ_PRIORITY); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + crmEnableSPI2(true); + crmResetSPI2(); +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(spip->dmarx, AT32_SPI_SPI2_RX_DMAMUX_CHANNEL, AT32_DMAMUX_SPI2_RX); + dmaSetRequestSource(spip->dmatx, AT32_SPI_SPI2_TX_DMAMUX_CHANNEL, AT32_DMAMUX_SPI2_TX); +#endif + } +#endif + + else { + osalDbgAssert(false, "invalid SPI instance"); + } + + /* DMA setup.*/ + dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DT); + dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DT); + } + + /* Configuration-specific DMA setup.*/ + if ((spip->config->ctrl1 & SPI_CTRL1_FBN) == 0) { + /* Frame width is 8 bits or smaller.*/ + spip->rxdmamode = (spip->rxdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE; + spip->txdmamode = (spip->txdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE; + } + else { + /* Frame width is larger than 8 bits.*/ + spip->rxdmamode = (spip->rxdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; + spip->txdmamode = (spip->txdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; + } + + if (spip->config->circular) { + spip->rxdmamode |= (AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); + spip->txdmamode |= (AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); + } + else { + spip->rxdmamode &= ~(AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); + spip->txdmamode &= ~(AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); + } + + /* SPI setup.*/ + spi_lld_configure(spip); + + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + /* Just in case this has been called uncleanly.*/ + (void) spi_lld_stop_abort(spip); + + /* SPI cleanup.*/ + spip->spi->CTRL1 = 0; + spip->spi->CTRL2 = 0; + + /* DMA channels release.*/ + dmaStreamFreeI(spip->dmatx); + dmaStreamFreeI(spip->dmarx); + spip->dmarx = NULL; + spip->dmatx = NULL; + + /* Clock shutdown.*/ + if (false) { + } + +#if AT32_SPI_USE_SPI1 + else if (&SPID1 == spip) { + crmDisableSPI1(); + } +#endif + +#if AT32_SPI_USE_SPI2 + else if (&SPID2 == spip) { + crmDisableSPI2(); + } +#endif + + else { + osalDbgAssert(false, "invalid SPI instance"); + } + } +} + +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + /* No implementation on AT32.*/ +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + /* No implementation on AT32.*/ +} +#endif + +/** + * @brief Ignores data on the SPI bus. + * @details This synchronous function performs the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre In order to use this function the option @p SPI_USE_SYNCHRONIZATION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_ignore(SPIDriver *spip, size_t n) { + + osalDbgAssert(n <= AT32_DMA_MAX_TRANSFER, "unsupported DMA transfer size"); + + dmaStreamSetMemory0(spip->dmarx, &spip->rxsink); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, &spip->txsource); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); + + return HAL_RET_SUCCESS; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + osalDbgAssert(n <= AT32_DMA_MAX_TRANSFER, "unsupported DMA transfer size"); + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | AT32_DMA_CCTRL_MINCM); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | AT32_DMA_CCTRL_MINCM); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); + + return HAL_RET_SUCCESS; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + osalDbgAssert(n <= AT32_DMA_MAX_TRANSFER, "unsupported DMA transfer size"); + + dmaStreamSetMemory0(spip->dmarx, &spip->rxsink); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode); + + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | AT32_DMA_CCTRL_MINCM); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); + + return HAL_RET_SUCCESS; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + osalDbgAssert(n <= AT32_DMA_MAX_TRANSFER, "unsupported DMA transfer size"); + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | AT32_DMA_CCTRL_MINCM); + + dmaStreamSetMemory0(spip->dmatx, &spip->txsource); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->txdmamode); + + dmaStreamEnable(spip->dmarx); + dmaStreamEnable(spip->dmatx); + + return HAL_RET_SUCCESS; +} + +/** + * @brief Aborts the ongoing SPI operation, if any. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[out] sizep pointer to the counter of frames not yet transferred + * or @p NULL + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep) { + msg_t msg; + + /* Stopping everything.*/ + msg = spi_lld_stop_abort(spip); + + if (sizep != NULL) { + *sizep = dmaStreamGetTransactionSize(spip->dmarx); + } + + return msg; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->DT = frame; + while ((spip->spi->STS & SPI_STS_RDBF) == 0U) + ; + return spip->spi->DT; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h new file mode 100644 index 0000000000..d2abef7203 --- /dev/null +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h @@ -0,0 +1,226 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPIv1/hal_spi_v2_lld.h + * @brief AT32 SPI (v2) subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef HAL_SPI_V2_LLD_H +#define HAL_SPI_V2_LLD_H + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Circular mode support flag. + */ +#define SPI_SUPPORTS_CIRCULAR TRUE + +/** + * @brief Slave mode support flag. + */ +#define SPI_SUPPORTS_SLAVE_MODE TRUE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define AT32_SPI_USE_SPI1 FALSE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define AT32_SPI_USE_SPI2 FALSE +#endif + +/** + * @brief Filler pattern used when there is nothing to transmit. + */ +#if !defined(AT32_SPI_FILLER_PATTERN) || defined(__DOXYGEN__) +#define AT32_SPI_FILLER_PATTERN 0xFFFFFFFFU +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(AT32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(AT32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(AT32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(AT32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI DMA error hook. + */ +#if !defined(AT32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if AT32_SPI_USE_SPI1 && !AT32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if AT32_SPI_USE_SPI2 && !AT32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if !AT32_SPI_USE_SPI1 && !AT32_SPI_USE_SPI2 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if AT32_SPI_USE_SPI1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SPI_SPI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI1" +#endif + +#if AT32_SPI_USE_SPI2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SPI_SPI2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI2" +#endif + +#if !defined(AT32_DMA_REQUIRED) +#define AT32_DMA_REQUIRED +#endif + +#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD +#error "SPI_SELECT_MODE_LLD not supported by this driver" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#define spi_lld_driver_fields \ + /* Pointer to the SPIx registers block.*/ \ + SPI_TypeDef *spi; \ + /* Receive DMA stream.*/ \ + const at32_dma_stream_t *dmarx; \ + /* Transmit DMA stream.*/ \ + const at32_dma_stream_t *dmatx; \ + /* RX DMA mode bit mask.*/ \ + uint32_t rxdmamode; \ + /* TX DMA mode bit mask.*/ \ + uint32_t txdmamode; \ + /* Sink for discarded data.*/ \ + uint32_t rxsink; \ + /* Source for default TX pattern.*/ \ + uint32_t txsource + +/** + * @brief Low level fields of the SPI configuration structure. + */ +#define spi_lld_config_fields \ + /* SPI CTRL1 register initialization data.*/ \ + uint16_t ctrl1; \ + /* SPI CTRL2 register initialization data.*/ \ + uint16_t ctrl2 + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if AT32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + msg_t spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); +#endif + msg_t spi_lld_ignore(SPIDriver *spip, size_t n); + msg_t spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* HAL_SPI_V2_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk b/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk new file mode 100644 index 0000000000..02016429dd --- /dev/null +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk @@ -0,0 +1,4 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1 + diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c new file mode 100644 index 0000000000..fd23d1d6f6 --- /dev/null +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c @@ -0,0 +1,343 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv1/hal_st_lld.c + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32) +#error "unsupported ST resolution" +#endif + +#if (OSAL_ST_RESOLUTION == 32) +#define ST_PR_INIT 0xFFFFFFFFU +#define ST_CTRL1_INIT 0x00000400U +#else +#define ST_PR_INIT 0x0000FFFFU +#define ST_CTRL1_INIT 0x00000000U +#endif + +#if AT32_ST_USE_TIMER == 2 + +#if !AT32_HAS_TMR2 +#error "TMR2 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR2_IS_32BITS +#error "TMR2 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR2_HANDLER +#define ST_NUMBER AT32_TMR2_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK1 +#define ST_ENABLE_CLOCK() crmEnableTMR2(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR2_PAUSE + +#elif AT32_ST_USE_TIMER == 3 + +#if !AT32_HAS_TMR3 +#error "TMR3 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR3_IS_32BITS +#error "TMR3 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR3_HANDLER +#define ST_NUMBER AT32_TMR3_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK1 +#define ST_ENABLE_CLOCK() crmEnableTMR3(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR3_PAUSE + +#elif AT32_ST_USE_TIMER == 4 + +#if !AT32_HAS_TMR4 +#error "TMR4 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR4_IS_32BITS +#error "TMR4 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR4_HANDLER +#define ST_NUMBER AT32_TMR4_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK1 +#define ST_ENABLE_CLOCK() crmEnableTMR4(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR4_PAUSE + +#elif AT32_ST_USE_TIMER == 5 + +#if !AT32_HAS_TMR5 +#error "TMR5 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR5_IS_32BITS +#error "TMR5 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR5_HANDLER +#define ST_NUMBER AT32_TMR5_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK1 +#define ST_ENABLE_CLOCK() crmEnableTMR5(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR5_PAUSE + +#elif AT32_ST_USE_TIMER == 9 + +#if !AT32_HAS_TMR9 +#error "TMR9 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR9_IS_32BITS +#error "TMR9 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR9_HANDLER +#define ST_NUMBER AT32_TMR9_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK2 +#define ST_ENABLE_CLOCK() crmEnableTMR9(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR9_PAUSE + +#elif AT32_ST_USE_TIMER == 10 + +#if !AT32_HAS_TMR10 +#error "TMR10 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR10_IS_32BITS +#error "TMR10 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR10_HANDLER +#define ST_NUMBER AT32_TMR10_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK2 +#define ST_ENABLE_CLOCK() crmEnableTMR10(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR10_PAUSE + +#elif AT32_ST_USE_TIMER == 11 + +#if !AT32_HAS_TMR11 +#error "TMR11 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR11_IS_32BITS +#error "TMR11 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR11_HANDLER +#define ST_NUMBER AT32_TMR11_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK2 +#define ST_ENABLE_CLOCK() crmEnableTMR11(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR11_PAUSE + +#else +#error "AT32_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if 0 /* TODO remove */ +#if ST_CLOCK_SRC % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#error "the selected ST frequency is not obtainable because TMR timer prescaler limits" +#endif +#endif + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + +#define ST_HANDLER SysTick_Handler + +#if defined(AT32_CORE_CK) +#define SYSTICK_CK AT32_CORE_CK +#else +#define SYSTICK_CK AT32_HCLK +#endif + +#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF +#error "the selected ST frequency is not obtainable because SysTick timer counter limits" +#endif + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(AT32_SYSTICK_SUPPRESS_ISR) +/** + * @brief Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + st_lld_serve_interrupt(); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + osalDbgAssert((ST_CLOCK_SRC % OSAL_ST_FREQUENCY) == 0U, + "clock rounding error"); + osalDbgAssert(((ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1U) < 0x10000, + "clock prescaler overflow"); + + /* Enabling timer clock.*/ + ST_ENABLE_CLOCK(); + + /* Enabling the pause mode during debug for this timer.*/ + ST_ENABLE_PAUSE(); + + /* Initializing the counter in free running mode.*/ + AT32_ST_TMR->CTRL1 = ST_CTRL1_INIT; + AT32_ST_TMR->DIV = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1; + AT32_ST_TMR->PR = ST_PR_INIT; + AT32_ST_TMR->CM1 = 0; + AT32_ST_TMR->CDT[0] = 0; +#if ST_LLD_NUM_ALARMS > 1 + AT32_ST_TMR->CDT[1] = 0; +#endif +#if ST_LLD_NUM_ALARMS > 2 + AT32_ST_TMR->CDT[2] = 0; +#endif +#if ST_LLD_NUM_ALARMS > 3 + AT32_ST_TMR->CDT[3] = 0; +#endif + AT32_ST_TMR->IDEN = 0; + AT32_ST_TMR->CTRL2 = 0; + AT32_ST_TMR->SWEVT = AT32_TMR_SWEVT_OVFSWTR; + AT32_ST_TMR->CTRL1 |= AT32_TMR_CTRL1_TMREN; + +#if !defined(AT32_SYSTICK_SUPPRESS_ISR) + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, AT32_ST_IRQ_PRIORITY); +#endif +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, AT32_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + uint32_t ists; + at32_tmr_t *timp = AT32_ST_TMR; + + ists = timp->ISTS; + ists &= timp->IDEN & AT32_TMR_IDEN_IRQ_MASK; + timp->ISTS = ~ists; + + if ((ists & AT32_TMR_ISTS_C1IF) != 0U) +#endif + { + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + } +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING +#if ST_LLD_NUM_ALARMS > 1 + if ((ists & AT32_TMR_ISTS_C2IF) != 0U) { + if (st_callbacks[1] != NULL) { + st_callbacks[1](1U); + } + } +#endif +#if ST_LLD_NUM_ALARMS > 2 + if ((ists & AT32_TMR_ISTS_C3IF) != 0U) { + if (st_callbacks[2] != NULL) { + st_callbacks[2](2U); + } + } +#endif +#if ST_LLD_NUM_ALARMS > 3 + if ((ists & AT32_TMR_ISTS_C4IF) != 0U) { + if (st_callbacks[3] != NULL) { + st_callbacks[3](3U); + } + } +#endif +#endif +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h new file mode 100644 index 0000000000..d53329abc6 --- /dev/null +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h @@ -0,0 +1,507 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SYSTICKv1/hal_st_lld.h + * @brief ST Driver subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(AT32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ST_IRQ_PRIORITY 8 +#endif + +/** + * @brief TIMx unit (by number) to be used for free running operations. + * @note You must select a 32 bits timer if a 32 bits @p systick_t type + * is required. + * @note Timers 2, 3, 4, 5, 9, 10 and 11 are supported. + */ +#if !defined(AT32_ST_USE_TIMER) || defined(__DOXYGEN__) +#define AT32_ST_USE_TIMER 2 +#endif + +/** + * @brief Overrides the number of supported alarms. + * @note The default number of alarms is equal to the number of + * comparators in the timer, overriding it to one makes + * the driver a little faster and smaller. The kernel itself + * only needs one alarm, additional features could need more. + * @note Zero means do not override. + * @note This setting is only meaningful in free running mode, in + * tick mode there are no alarms. + */ +#if !defined(AT32_ST_OVERRIDE_ALARMS) || defined(__DOXYGEN__) +#define AT32_ST_OVERRIDE_ALARMS 1 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* This has to go after transition to shared handlers is complete for all + platforms.*/ +#if !defined(AT32_HAS_TMR2) +#define AT32_HAS_TMR2 FALSE +#endif + +#if !defined(AT32_HAS_TMR3) +#define AT32_HAS_TMR3 FALSE +#endif + +#if !defined(AT32_HAS_TMR4) +#define AT32_HAS_TMR4 FALSE +#endif + +#if !defined(AT32_HAS_TMR5) +#define AT32_HAS_TMR5 FALSE +#endif + +#if !defined(AT32_HAS_TMR9) +#define AT32_HAS_TMR9 FALSE +#endif + +#if !defined(AT32_HAS_TMR10) +#define AT32_HAS_TMR10 FALSE +#endif + +#if !defined(AT32_HAS_TMR11) +#define AT32_HAS_TMR11 FALSE +#endif +/* End of checks to be removed.*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if AT32_ST_USE_TIMER == 2 + +#if defined(AT32_TMR2_IS_USED) +#error "ST requires TMR2 but the timer is already used" +#else +#define AT32_TMR2_IS_USED +#endif + +#if defined(AT32_TMR2_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR2 +#define ST_LLD_NUM_ALARMS AT32_TMR2_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 TRUE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 3 + +#if defined(AT32_TMR3_IS_USED) +#error "ST requires TMR3 but the timer is already used" +#else +#define AT32_TMR3_IS_USED +#endif + +#if defined(AT32_TMR3_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR3 +#define ST_LLD_NUM_ALARMS AT32_TMR3_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 TRUE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 4 + +#if defined(AT32_TMR4_IS_USED) +#error "ST requires TMR4 but the timer is already used" +#else +#define AT32_TMR4_IS_USED +#endif + +#if defined(AT32_TMR4_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR4 +#define ST_LLD_NUM_ALARMS AT32_TMR4_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 TRUE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 5 + +#if defined(AT32_TMR5_IS_USED) +#error "ST requires TMR5 but the timer is already used" +#else +#define AT32_TMR5_IS_USED +#endif + +#if defined(AT32_TMR5_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR5 +#define ST_LLD_NUM_ALARMS AT32_TMR5_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 TRUE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 9 + +#if defined(AT32_TMR9_IS_USED) +#error "ST requires TMR9 but the timer is already used" +#else +#define AT32_TMR9_IS_USED +#endif + +#if defined(AT32_TMR9_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR9 +#define ST_LLD_NUM_ALARMS AT32_TMR9_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 TRUE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 10 + +#if defined(AT32_TMR10_IS_USED) +#error "ST requires TMR10 but the timer is already used" +#else +#define AT32_TMR10_IS_USED +#endif + +#if defined(AT32_TMR10_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR10 +#define ST_LLD_NUM_ALARMS AT32_TMR10_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 TRUE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 11 + +#if defined(AT32_TMR11_IS_USED) +#error "ST requires TMR11 but the timer is already used" +#else +#define AT32_TMR11_IS_USED +#endif + +#if defined(AT32_TMR11_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR11 +#define ST_LLD_NUM_ALARMS AT32_TMR11_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 TRUE + +#else +#error "AT32_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (AT32_ST_OVERRIDE_ALARMS < 0) || \ + (AT32_ST_OVERRIDE_ALARMS > ST_LLD_NUM_ALARMS) +#error "invalid AT32_ST_OVERRIDE_ALARMS value" +#endif + +#if AT32_ST_OVERRIDE_ALARMS > 0 +#undef ST_LLD_NUM_ALARMS +#define ST_LLD_NUM_ALARMS AT32_ST_OVERRIDE_ALARMS +#endif + +#elif OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + +#define AT32_ST_USE_SYSTICK TRUE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#else + +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); + void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + + return (systime_t)AT32_ST_TMR->CVAL; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + + AT32_ST_TMR->CDT[0] = (uint32_t)abstime; + AT32_ST_TMR->ISTS = 0; +#if ST_LLD_NUM_ALARMS == 1 + AT32_ST_TMR->IDEN = AT32_TMR_IDEN_C1IEN; +#else + AT32_ST_TMR->IDEN |= AT32_TMR_IDEN_C1IEN; +#endif +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + +#if ST_LLD_NUM_ALARMS == 1 + AT32_ST_TMR->IDEN = 0U; +#else + AT32_ST_TMR->IDEN &= ~AT32_TMR_IDEN_C1IEN; +#endif +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + + AT32_ST_TMR->CDT[0] = (uint32_t)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)AT32_ST_TMR->CDT[0]; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return (bool)((AT32_ST_TMR->IDEN & AT32_TMR_IDEN_C1IEN) != 0); +} + +#if (ST_LLD_NUM_ALARMS > 1) || defined(__DOXYGEN__) +/** + * @brief Starts an alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * + * @param[in] abstime the time to be set for the first alarm + * @param[in] alarm alarm channel number + * + * @notapi + */ +static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) { + + AT32_ST_TMR->CDT[alarm] = (uint32_t)abstime; + AT32_ST_TMR->ISTS = 0; + AT32_ST_TMR->IDEN |= (AT32_TMR_IDEN_C1IEN << alarm); +} + +/** + * @brief Stops an alarm interrupt. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * + * @param[in] alarm alarm channel number + * + * @notapi + */ +static inline void st_lld_stop_alarm_n(unsigned alarm) { + + AT32_ST_TMR->IDEN &= ~(AT32_TMR_IDEN_C1IEN << alarm); +} + +/** + * @brief Sets an alarm time. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * + * @param[in] alarm alarm channel number + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm_n(unsigned alarm, systime_t abstime) { + + AT32_ST_TMR->CDT[alarm] = (uint32_t)abstime; +} + +/** + * @brief Returns an alarm current time. + * @note This functionality is only available in free running mode, the + * behavior in periodic mode is undefined. + * + * @param[in] alarm alarm channel number + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm_n(unsigned alarm) { + + return (systime_t)AT32_ST_TMR->CDT[alarm]; +} + +/** + * @brief Determines if an alarm is active. + * + * @param[in] alarm alarm channel number + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active_n(unsigned alarm) { + + return (bool)((AT32_ST_TMR->IDEN & (AT32_TMR_IDEN_C1IEN << alarm)) != 0); +} +#endif /* ST_LLD_NUM_ALARMS > 1 */ + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h new file mode 100644 index 0000000000..18411700c0 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h @@ -0,0 +1,362 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/at32_tmr.h + * @brief AT32 TMR units common header. + * @note This file requires definitions from the AT AT32 header file. + * + * @addtogroup AT32_TMRv1 + * @{ + */ + +#ifndef AT32_TMR_H +#define AT32_TMR_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name TMR_CTRL1 register + * @{ + */ +#define AT32_TMR_CTRL1_TMREN (1U << 0) +#define AT32_TMR_CTRL1_OVFEN (1U << 1) +#define AT32_TMR_CTRL1_OVFS (1U << 2) +#define AT32_TMR_CTRL1_OCMEN (1U << 3) +#define AT32_TMR_CTRL1_OWCDIR (1U << 4) + +#define AT32_TMR_CTRL1_TWCMSEL_MASK (3U << 5) +#define AT32_TMR_CTRL1_TWCMSEL(n) ((n) << 5) + +#define AT32_TMR_CTRL1_PRBEN (1U << 7) + +#define AT32_TMR_CTRL1_CLKDIV_MASK (3U << 8) +#define AT32_TMR_CTRL1_CLKDIV(n) ((n) << 8) + +#define AT32_TMR_CTRL1_PMEN (1U << 10) +/** @} */ + +/** + * @name TMR_CTRL2 register + * @{ + */ +#define AT32_TMR_CTRL2_CBCTRL (1U << 0) +#define AT32_TMR_CTRL2_CCFS (1U << 2) +#define AT32_TMR_CTRL2_DRS (1U << 3) + +#define AT32_TMR_CTRL2_PTOS_MASK (7U << 4) +#define AT32_TMR_CTRL2_PTOS(n) ((n) << 4) + +#define AT32_TMR_CTRL2_C1INSEL (1U << 7) +#define AT32_TMR_CTRL2_C1IOS (1U << 8) +#define AT32_TMR_CTRL2_C1CIOS (1U << 9) +#define AT32_TMR_CTRL2_C2IOS (1U << 10) +#define AT32_TMR_CTRL2_C2CIOS (1U << 11) +#define AT32_TMR_CTRL2_C3IOS (1U << 12) +#define AT32_TMR_CTRL2_C3CIOS (1U << 13) +#define AT32_TMR_CTRL2_C4IOS (1U << 14) +/** @} */ + +/** + * @name TMR_STCTRL register + * @{ + */ +#define AT32_TMR_STCTRL_SMSEL_MASK (7U << 0) +#define AT32_TMR_STCTRL_SMSEL(n) ((n) << 0) + +#define AT32_TMR_STCTRL_COSSEL (1U << 3) + +#define AT32_TMR_STCTRL_STIS_MASK (7U << 4) +#define AT32_TMR_STCTRL_STIS(n) ((n) << 4) + +#define AT32_TMR_STCTRL_STS (1U << 7) + +#define AT32_TMR_STCTRL_ESF_MASK (15U << 8) +#define AT32_TMR_STCTRL_ESF(n) ((n) << 8) + +#define AT32_TMR_STCTRL_ESDIV_MASK (3U << 12) +#define AT32_TMR_STCTRL_ESDIV(n) ((n) << 12) + +#define AT32_TMR_STCTRL_ECMBEN (1U << 14) +#define AT32_TMR_STCTRL_ESP (1U << 15) +/** @} */ + +/** + * @name TMR_IDEN register + * @{ + */ +#define AT32_TMR_IDEN_OVFIEN (1U << 0) +#define AT32_TMR_IDEN_C1IEN (1U << 1) +#define AT32_TMR_IDEN_C2IEN (1U << 2) +#define AT32_TMR_IDEN_C3IEN (1U << 3) +#define AT32_TMR_IDEN_C4IEN (1U << 4) +#define AT32_TMR_IDEN_HALLIEN (1U << 5) +#define AT32_TMR_IDEN_TIEN (1U << 6) +#define AT32_TMR_IDEN_BRKIE (1U << 7) +#define AT32_TMR_IDEN_OVFDEN (1U << 8) +#define AT32_TMR_IDEN_C1DEN (1U << 9) +#define AT32_TMR_IDEN_C2DEN (1U << 10) +#define AT32_TMR_IDEN_C3DEN (1U << 11) +#define AT32_TMR_IDEN_C4DEN (1U << 12) +#define AT32_TMR_IDEN_HALLDE (1U << 13) +#define AT32_TMR_IDEN_TDEN (1U << 14) + +#define AT32_TMR_IDEN_IRQ_MASK (AT32_TMR_IDEN_OVFIEN | \ + AT32_TMR_IDEN_C1IEN | \ + AT32_TMR_IDEN_C2IEN | \ + AT32_TMR_IDEN_C3IEN | \ + AT32_TMR_IDEN_C4IEN | \ + AT32_TMR_IDEN_HALLIEN | \ + AT32_TMR_IDEN_TIEN | \ + AT32_TMR_IDEN_BRKIE) + +/** @} */ + +/** + * @name TMR_ISTS register + * @{ + */ +#define AT32_TMR_ISTS_OVFIF (1U << 0) +#define AT32_TMR_ISTS_C1IF (1U << 1) +#define AT32_TMR_ISTS_C2IF (1U << 2) +#define AT32_TMR_ISTS_C3IF (1U << 3) +#define AT32_TMR_ISTS_C4IF (1U << 4) +#define AT32_TMR_ISTS_HALLIF (1U << 5) +#define AT32_TMR_ISTS_TRGIF (1U << 6) +#define AT32_TMR_ISTS_BRKIF (1U << 7) +#define AT32_TMR_ISTS_C1RF (1U << 9) +#define AT32_TMR_ISTS_C2RF (1U << 10) +#define AT32_TMR_ISTS_C3RF (1U << 11) +#define AT32_TMR_ISTS_C4RF (1U << 12) +/** @} */ + +/** + * @name TMR_SWEVT register + * @{ + */ +#define AT32_TMR_SWEVT_OVFSWTR (1U << 0) +#define AT32_TMR_SWEVT_C1SWTR (1U << 1) +#define AT32_TMR_SWEVT_C2SWTR (1U << 2) +#define AT32_TMR_SWEVT_C3SWTR (1U << 3) +#define AT32_TMR_SWEVT_C4SWTR (1U << 4) +#define AT32_TMR_SWEVT_HALLSWTR (1U << 5) +#define AT32_TMR_SWEVT_TRGSWTR (1U << 6) +#define AT32_TMR_SWEVT_BRKSWTR (1U << 7) +/** @} */ + +/** + * @name TMR_CM1 register (output) + * @{ + */ +#define AT32_TMR_CM1_C1C_MASK (3U << 0) +#define AT32_TMR_CM1_C1C(n) ((n) << 0) + +#define AT32_TMR_CM1_C1OIEN (1U << 2) +#define AT32_TMR_CM1_C1OBEN (1U << 3) + +#define AT32_TMR_CM1_C1OCTRL_MASK (7U << 4) +#define AT32_TMR_CM1_C1OCTRL(n) ((n) << 4) + +#define AT32_TMR_CM1_C1OSEN (1U << 7) + +#define AT32_TMR_CM1_C2C_MASK (3U << 8) +#define AT32_TMR_CM1_C2C(n) ((n) << 8) + +#define AT32_TMR_CM1_C2OIEN (1U << 10) +#define AT32_TMR_CM1_C2OBEN (1U << 11) + +#define AT32_TMR_CM1_C2OCTRL_MASK (7U << 12) +#define AT32_TMR_CM1_C2OCTRL(n) ((n) << 12) + +#define AT32_TMR_CM1_C2OSEN (1U << 15) +/** @} */ + +/** + * @name TMR_CM1 register (input) + * @{ + */ +#define AT32_TMR_CM1_C1IDIV_MASK (3U << 2) +#define AT32_TMR_CM1_C1IDIV(n) ((n) << 2) + +#define AT32_TMR_CM1_C1DF_MASK (15U << 4) +#define AT32_TMR_CM1_C1DF(n) ((n) << 4) + +#define AT32_TMR_CM1_C2IDIV_MASK (3U << 10) +#define AT32_TMR_CM1_C2IDIV(n) ((n) << 10) + +#define AT32_TMR_CM1_C2DF_MASK (15U << 12) +#define AT32_TMR_CM1_C2DF(n) ((n) << 12) +/** @} */ + +/** + * @name TMR_CM2 register (output) + * @{ + */ +#define AT32_TMR_CM2_C3C_MASK (3U << 0) +#define AT32_TMR_CM2_C3C(n) ((n) << 0) + +#define AT32_TMR_CM2_C3OIEN (1U << 2) +#define AT32_TMR_CM2_C3OBEN (1U << 3) + +#define AT32_TMR_CM2_C3OCTRL_MASK (7U << 4) +#define AT32_TMR_CM2_C3OCTRL(n) ((n) << 4) + +#define AT32_TMR_CM2_C3OSEN (1U << 7) + +#define AT32_TMR_CM2_C4C_MASK (3U << 8) +#define AT32_TMR_CM2_C4C(n) ((n) << 8) + +#define AT32_TMR_CM2_C4OIEN (1U << 10) +#define AT32_TMR_CM2_C4OBEN (1U << 11) + +#define AT32_TMR_CM2_C4OCTRL_MASK (7U << 12) +#define AT32_TMR_CM2_C4OCTRL(n) ((n) << 12) + +#define AT32_TMR_CM2_C4OSEN (1U << 15) +/** @} */ + +/** + * @name TMR_CM2 register (input) + * @{ + */ +#define AT32_TMR_CM2_C3IDIV_MASK (3U << 2) +#define AT32_TMR_CM2_C3IDIV(n) ((n) << 2) + +#define AT32_TMR_CM2_C3DF_MASK (15U << 4) +#define AT32_TMR_CM2_C3DF(n) ((n) << 4) + +#define AT32_TMR_CM2_C4IDIV_MASK (3U << 10) +#define AT32_TMR_CM2_C4IDIV(n) ((n) << 10) + +#define AT32_TMR_CM2_C4DF_MASK (15U << 12) +#define AT32_TMR_CM2_C4DF(n) ((n) << 12) +/** @} */ + +/** + * @name TMR_CCTRL register + * @{ + */ +#define AT32_TMR_CCTRL_C1EN (1U << 0) +#define AT32_TMR_CCTRL_C1P (1U << 1) +#define AT32_TMR_CCTRL_C1CEN (1U << 2) +#define AT32_TMR_CCTRL_C1CP (1U << 3) +#define AT32_TMR_CCTRL_C2EN (1U << 4) +#define AT32_TMR_CCTRL_C2P (1U << 5) +#define AT32_TMR_CCTRL_C2CEN (1U << 6) +#define AT32_TMR_CCTRL_C2CP (1U << 7) +#define AT32_TMR_CCTRL_C3EN (1U << 8) +#define AT32_TMR_CCTRL_C3P (1U << 9) +#define AT32_TMR_CCTRL_C3CEN (1U << 10) +#define AT32_TMR_CCTRL_C3CP (1U << 11) +#define AT32_TMR_CCTRL_C4EN (1U << 12) +#define AT32_TMR_CCTRL_C4P (1U << 13) +/** @} */ + +/** + * @name TMR_BRK register + * @{ + */ +#define AT32_TMR_BRK_DTC_MASK (255U << 0) +#define AT32_TMR_BRK_DTC(n) ((n) << 0) + +#define AT32_TMR_BRK_WPC_MASK (3U << 8) +#define AT32_TMR_BRK_WPC(n) ((n) << 8) + +#define AT32_TMR_BRK_FCSODIS (1U << 10) +#define AT32_TMR_BRK_FCSOEN (1U << 11) +#define AT32_TMR_BRK_BRKEN (1U << 12) +#define AT32_TMR_BRK_BRKV (1U << 13) +#define AT32_TMR_BRK_AOEN (1U << 14) +#define AT32_TMR_BRK_OEN (1U << 15) +/** @} */ + +/** + * @name TMR_DMACTRL register + * @{ + */ +#define AT32_TMR_DMACTRL_ADDR_MASK (31U << 0) +#define AT32_TMR_DMACTRL_ADDR(n) ((n) << 0) + +#define AT32_TMR_DMACTRL_DTB_MASK (31U << 8) +#define AT32_TMR_DMACTRL_DTB(n) ((n) << 8) +/** @} */ + +/** + * @name TMR units references + * @{ + */ +#define AT32_TMR1 ((at32_tmr_t *)TMR1_BASE) +#define AT32_TMR2 ((at32_tmr_t *)TMR2_BASE) +#define AT32_TMR3 ((at32_tmr_t *)TMR3_BASE) +#define AT32_TMR4 ((at32_tmr_t *)TMR4_BASE) +#define AT32_TMR5 ((at32_tmr_t *)TMR5_BASE) +#define AT32_TMR9 ((at32_tmr_t *)TMR9_BASE) +#define AT32_TMR10 ((at32_tmr_t *)TMR10_BASE) +#define AT32_TMR11 ((at32_tmr_t *)TMR11_BASE) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief AT32 TMR registers block. + * @note This is the most general known form, not all timers have + * necessarily all registers and bits. + */ +typedef struct { + volatile uint32_t CTRL1; + volatile uint32_t CTRL2; + volatile uint32_t STCTRL; + volatile uint32_t IDEN; + volatile uint32_t ISTS; + volatile uint32_t SWEVT; + volatile uint32_t CM1; + volatile uint32_t CM2; + volatile uint32_t CCTRL; + volatile uint32_t CVAL; + volatile uint32_t DIV; + volatile uint32_t PR; + volatile uint32_t RPR; + volatile uint32_t CDT[4]; + volatile uint32_t BRK; + volatile uint32_t DMACTRL; + volatile uint32_t DMADT; +} at32_tmr_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* AT32_TMR_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc new file mode 100644 index 0000000000..d4d536d15b --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc @@ -0,0 +1,345 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/at32_tmr1_9_10_11.inc + * @brief Shared TMR1, TMR9, TMR10, TMR11 handler. + * + * @addtogroup AT32_TMR1_TMR9_TMR10_TMR11_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_TMR1) +#error "AT32_HAS_TMR1 not defined in registry" +#endif + +#if !defined(AT32_HAS_TMR9) +#error "AT32_HAS_TMR9 not defined in registry" +#endif + +#if !defined(AT32_HAS_TMR10) +#error "AT32_HAS_TMR10 not defined in registry" +#endif + +#if !defined(AT32_HAS_TMR11) +#error "AT32_HAS_TMR11 not defined in registry" +#endif + +/* Driver checks for robustness, undefined USE macros are defaulted to + FALSE. This makes this module independent from drivers implementation.*/ +#if !defined(AT32_GPT_USE_TMR1) +#define AT32_GPT_USE_TMR1 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR1) +#define AT32_ICU_USE_TMR1 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR1) +#define AT32_PWM_USE_TMR1 FALSE +#endif +#if !defined(AT32_ST_USE_TMR1) +#define AT32_ST_USE_TMR1 FALSE +#endif + +#if !defined(AT32_GPT_USE_TMR9) +#define AT32_GPT_USE_TMR9 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR9) +#define AT32_ICU_USE_TMR9 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR9) +#define AT32_PWM_USE_TMR9 FALSE +#endif +#if !defined(AT32_ST_USE_TMR9) +#define AT32_ST_USE_TMR9 FALSE +#endif + +#if !defined(AT32_GPT_USE_TMR10) +#define AT32_GPT_USE_TMR10 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR10) +#define AT32_ICU_USE_TMR10 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR10) +#define AT32_PWM_USE_TMR10 FALSE +#endif +#if !defined(AT32_ST_USE_TMR10) +#define AT32_ST_USE_TMR10 FALSE +#endif + +#if !defined(AT32_GPT_USE_TMR11) +#define AT32_GPT_USE_TMR11 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR11) +#define AT32_ICU_USE_TMR11 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR11) +#define AT32_PWM_USE_TMR11 FALSE +#endif +#if !defined(AT32_ST_USE_TMR11) +#define AT32_ST_USE_TMR11 FALSE +#endif + +#if AT32_HAS_TMR1 || AT32_HAS_TMR9 || AT32_HAS_TMR10 || AT32_HAS_TMR11 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_TMR1_BRK_TMR9_PRIORITY) +#error "AT32_IRQ_TMR1_BRK_TMR9_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_IRQ_TMR1_OVF_TMR10_PRIORITY) +#error "AT32_IRQ_TMR1_OVF_TMR10_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_IRQ_TMR1_HALL_TMR11_PRIORITY) +#error "AT32_IRQ_TMR1_HALL_TMR11_PRIORITY not defined in mcuconf.h" +#endif + +#if !defined(AT32_IRQ_TMR1_CH_PRIORITY) +#error "AT32_IRQ_TMR1_CH_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR1_BRK_TMR9_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR1_BRK_TMR9_PRIORITY" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR1_OVF_TMR10_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR1_OVF_TMR10_PRIORITY" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR1_HALL_TMR11_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR1_HALL_TMR11_PRIORITY" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR1_CH_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR1_CH_PRIORITY" +#endif + +#endif /* AT32_HAS_TMR1 || AT32_HAS_TMR9 || AT32_HAS_TMR10 || AT32_HAS_TMR11 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tmr1_tmr9_tmr10_tmr11_irq_init(void) { +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR9_IS_USED) + nvicEnableVector(AT32_TMR1_BRK_TMR9_NUMBER, + AT32_IRQ_TMR1_BRK_TMR9_PRIORITY); +#endif +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR10_IS_USED) + nvicEnableVector(AT32_TMR1_OVF_TMR10_NUMBER, + AT32_IRQ_TMR1_OVF_TMR10_PRIORITY); +#endif +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR11_IS_USED) + nvicEnableVector(AT32_TMR1_HALL_TMR11_NUMBER, + AT32_IRQ_TMR1_HALL_TMR11_PRIORITY); +#endif +#if defined(AT32_TMR1_IS_USED) + nvicEnableVector(AT32_TMR1_CH_NUMBER, + AT32_IRQ_TMR1_CH_PRIORITY); +#endif +} + +static inline void tmr1_tmr9_tmr10_tmr11_irq_deinit(void) { +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR9_IS_USED) + nvicDisableVector(AT32_TMR1_BRK_TMR9_NUMBER); +#endif +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR10_IS_USED) + nvicDisableVector(AT32_TMR1_OVF_TMR10_NUMBER); +#endif +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR11_IS_USED) + nvicDisableVector(AT32_TMR1_HALL_TMR11_NUMBER); +#endif +#if defined(AT32_TMR1_IS_USED) + nvicDisableVector(AT32_TMR1_CH_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR9_IS_USED) || \ + defined(__DOXYGEN__) +/** + * @brief TMR1-BRK, TMR9 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_BRK_TMR9_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR9 + gpt_lld_serve_interrupt(&GPTD9); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR9 + icu_lld_serve_interrupt(&ICUD9); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR9 + pwm_lld_serve_interrupt(&PWMD9); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR9 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR10_IS_USED) || \ + defined(__DOXYGEN__) +/** + * @brief TMR1-OVF, TMR10 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_OVF_TMR10_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR1 + gpt_lld_serve_interrupt(&GPTD1); +#endif +#if AT32_GPT_USE_TMR10 + gpt_lld_serve_interrupt(&GPTD10); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR1 + icu_lld_serve_interrupt(&ICUD1); +#endif +#if AT32_ICU_USE_TMR10 + icu_lld_serve_interrupt(&ICUD10); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR1 + pwm_lld_serve_interrupt(&PWMD1); +#endif +#if AT32_PWM_USE_TMR10 + pwm_lld_serve_interrupt(&PWMD10); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR1 + st_lld_serve_interrupt(); +#endif +#if AT32_ST_USE_TMR10 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_TMR1_IS_USED) || defined(AT32_TMR11_IS_USED) || \ + defined(__DOXYGEN__) +/** + * @brief TMR1-TRG-HALL, TMR11 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_HALL_TMR11_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR11 + gpt_lld_serve_interrupt(&GPTD11); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR11 + icu_lld_serve_interrupt(&ICUD11); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR11 + pwm_lld_serve_interrupt(&PWMD11); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR11 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(AT32_TMR1_IS_USED) +/** + * @brief TMR1-CH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_CH_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT + /* Not used by GPT.*/ +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR1 + icu_lld_serve_interrupt(&ICUD1); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR1 + pwm_lld_serve_interrupt(&PWMD1); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc new file mode 100644 index 0000000000..6198264c28 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc @@ -0,0 +1,135 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/at32_tmr2.inc + * @brief Shared TMR2 handler. + * + * @addtogroup AT32_TMR2_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_TMR2) +#error "AT32_HAS_TMR2 not defined in registry" +#endif + +/* Driver checks for robustness, undefined USE macros are defaulted to + FALSE. This makes this module independent from drivers implementation.*/ +#if !defined(AT32_GPT_USE_TMR2) +#define AT32_GPT_USE_TMR2 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR2) +#define AT32_ICU_USE_TMR2 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR2) +#define AT32_PWM_USE_TMR2 FALSE +#endif +#if !defined(AT32_ST_USE_TMR2) +#define AT32_ST_USE_TMR2 FALSE +#endif + +#if AT32_HAS_TMR2 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_TMR2_PRIORITY) +#error "AT32_IRQ_TMR2_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR2_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR2_PRIORITY" +#endif + +#endif /* AT32_HAS_TMR2 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tmr2_irq_init(void) { +#if defined(AT32_TMR2_IS_USED) + nvicEnableVector(AT32_TMR2_NUMBER, AT32_IRQ_TMR2_PRIORITY); +#endif +} + +static inline void tmr2_irq_deinit(void) { +#if defined(AT32_TMR2_IS_USED) + nvicDisableVector(AT32_TMR2_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_TMR2_IS_USED) || defined(__DOXYGEN__) +/** + * @brief TMR2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR2 + gpt_lld_serve_interrupt(&GPTD2); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR2 + icu_lld_serve_interrupt(&ICUD2); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR2 + pwm_lld_serve_interrupt(&PWMD2); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR2 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc new file mode 100644 index 0000000000..5c2ea3954e --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc @@ -0,0 +1,135 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/at32_tmr3.inc + * @brief Shared TMR3 handler. + * + * @addtogroup AT32_TMR3_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_TMR3) +#error "AT32_HAS_TMR3 not defined in registry" +#endif + +/* Driver checks for robustness, undefined USE macros are defaulted to + FALSE. This makes this module independent from drivers implementation.*/ +#if !defined(AT32_GPT_USE_TMR3) +#define AT32_GPT_USE_TMR3 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR3) +#define AT32_ICU_USE_TMR3 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR3) +#define AT32_PWM_USE_TMR3 FALSE +#endif +#if !defined(AT32_ST_USE_TMR3) +#define AT32_ST_USE_TMR3 FALSE +#endif + +#if AT32_HAS_TMR3 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_TMR3_PRIORITY) +#error "AT32_IRQ_TMR3_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR3_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR3_PRIORITY" +#endif + +#endif /* AT32_HAS_TMR3 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tmr3_irq_init(void) { +#if defined(AT32_TMR3_IS_USED) + nvicEnableVector(AT32_TMR3_NUMBER, AT32_IRQ_TMR3_PRIORITY); +#endif +} + +static inline void tmr3_irq_deinit(void) { +#if defined(AT32_TMR3_IS_USED) + nvicDisableVector(AT32_TMR3_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_TMR3_IS_USED) || defined(__DOXYGEN__) +/** + * @brief TMR3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR3 + gpt_lld_serve_interrupt(&GPTD3); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR3 + icu_lld_serve_interrupt(&ICUD3); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR3 + pwm_lld_serve_interrupt(&PWMD3); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR3 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc new file mode 100644 index 0000000000..dbecd46685 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc @@ -0,0 +1,135 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/at32_tmr4.inc + * @brief Shared TMR4 handler. + * + * @addtogroup AT32_TMR4_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_TMR4) +#error "AT32_HAS_TMR4 not defined in registry" +#endif + +/* Driver checks for robustness, undefined USE macros are defaulted to + FALSE. This makes this module independent from drivers implementation.*/ +#if !defined(AT32_GPT_USE_TMR4) +#define AT32_GPT_USE_TMR4 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR4) +#define AT32_ICU_USE_TMR4 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR4) +#define AT32_PWM_USE_TMR4 FALSE +#endif +#if !defined(AT32_ST_USE_TMR4) +#define AT32_ST_USE_TMR4 FALSE +#endif + +#if AT32_HAS_TMR4 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_TMR4_PRIORITY) +#error "AT32_IRQ_TMR4_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR4_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR4_PRIORITY" +#endif + +#endif /* AT32_HAS_TMR4 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tmr4_irq_init(void) { +#if defined(AT32_TMR4_IS_USED) + nvicEnableVector(AT32_TMR4_NUMBER, AT32_IRQ_TMR4_PRIORITY); +#endif +} + +static inline void tmr4_irq_deinit(void) { +#if defined(AT32_TMR4_IS_USED) + nvicDisableVector(AT32_TMR4_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_TMR4_IS_USED) || defined(__DOXYGEN__) +/** + * @brief TMR4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR4 + gpt_lld_serve_interrupt(&GPTD4); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR4 + icu_lld_serve_interrupt(&ICUD4); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR4 + pwm_lld_serve_interrupt(&PWMD4); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR4 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc new file mode 100644 index 0000000000..1f860cf007 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc @@ -0,0 +1,135 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/at32_tmr5.inc + * @brief Shared TMR5 handler. + * + * @addtogroup AT32_TMR5_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_TMR5) +#error "AT32_HAS_TMR5 not defined in registry" +#endif + +/* Driver checks for robustness, undefined USE macros are defaulted to + FALSE. This makes this module independent from drivers implementation.*/ +#if !defined(AT32_GPT_USE_TMR5) +#define AT32_GPT_USE_TMR5 FALSE +#endif +#if !defined(AT32_ICU_USE_TMR5) +#define AT32_ICU_USE_TMR5 FALSE +#endif +#if !defined(AT32_PWM_USE_TMR5) +#define AT32_PWM_USE_TMR5 FALSE +#endif +#if !defined(AT32_ST_USE_TMR5) +#define AT32_ST_USE_TMR5 FALSE +#endif + +#if AT32_HAS_TMR5 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_TMR5_PRIORITY) +#error "AT32_IRQ_TMR5_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_TMR5_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_TMR5_PRIORITY" +#endif + +#endif /* AT32_HAS_TMR5 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void tmr5_irq_init(void) { +#if defined(AT32_TMR5_IS_USED) + nvicEnableVector(AT32_TMR5_NUMBER, AT32_IRQ_TMR5_PRIORITY); +#endif +} + +static inline void tmr5_irq_deinit(void) { +#if defined(AT32_TMR5_IS_USED) + nvicDisableVector(AT32_TMR5_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_TMR5_IS_USED) || defined(__DOXYGEN__) +/** + * @brief TMR5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_GPT +#if AT32_GPT_USE_TMR5 + gpt_lld_serve_interrupt(&GPTD5); +#endif +#endif +#if HAL_USE_ICU +#if AT32_ICU_USE_TMR5 + icu_lld_serve_interrupt(&ICUD5); +#endif +#endif +#if HAL_USE_PWM +#if AT32_PWM_USE_TMR5 + pwm_lld_serve_interrupt(&PWMD5); +#endif +#endif +#if 1 +#if AT32_ST_USE_TMR5 + st_lld_serve_interrupt(); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/driver.mk b/os/hal/ports/AT32/LLD/TMRv1/driver.mk new file mode 100644 index 0000000000..8df7008c67 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/driver.mk @@ -0,0 +1,17 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1 diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c new file mode 100644 index 0000000000..c10cc749e3 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c @@ -0,0 +1,595 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/hal_gpt_lld.c + * @brief AT32 GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + * @note The driver GPTD1 allocates the complex timer TMR1 when enabled. + */ +#if AT32_GPT_USE_TMR1 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPTD2 driver identifier. + * @note The driver GPTD2 allocates the timer TMR2 when enabled. + */ +#if AT32_GPT_USE_TMR2 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPTD3 driver identifier. + * @note The driver GPTD3 allocates the timer TMR3 when enabled. + */ +#if AT32_GPT_USE_TMR3 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPTD4 driver identifier. + * @note The driver GPTD4 allocates the timer TMR4 when enabled. + */ +#if AT32_GPT_USE_TMR4 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/** + * @brief GPTD5 driver identifier. + * @note The driver GPTD5 allocates the timer TMR5 when enabled. + */ +#if AT32_GPT_USE_TMR5 || defined(__DOXYGEN__) +GPTDriver GPTD5; +#endif + +/** + * @brief GPTD9 driver identifier. + * @note The driver GPTD9 allocates the timer TMR9 when enabled. + */ +#if AT32_GPT_USE_TMR9 || defined(__DOXYGEN__) +GPTDriver GPTD9; +#endif + +/** + * @brief GPTD10 driver identifier. + * @note The driver GPTD10 allocates the timer TMR10 when enabled. + */ +#if AT32_GPT_USE_TMR10 || defined(__DOXYGEN__) +GPTDriver GPTD10; +#endif + +/** + * @brief GPTD11 driver identifier. + * @note The driver GPTD11 allocates the timer TMR11 when enabled. + */ +#if AT32_GPT_USE_TMR11 || defined(__DOXYGEN__) +GPTDriver GPTD11; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_GPT_USE_TMR1 || defined(__DOXYGEN__) +#if !defined(AT32_TMR1_SUPPRESS_ISR) +#if !defined(AT32_TMR1_OVF_HANDLER) +#error "AT32_TMR1_OVF_HANDLER not defined" +#endif +/** + * @brief TMR1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_OVF_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR1_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR1 */ + +#if AT32_GPT_USE_TMR2 || defined(__DOXYGEN__) +#if !defined(AT32_TMR2_SUPPRESS_ISR) +#if !defined(AT32_TMR2_HANDLER) +#error "AT32_TMR2_HANDLER not defined" +#endif +/** + * @brief TMR2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR2_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR2 */ + +#if AT32_GPT_USE_TMR3 || defined(__DOXYGEN__) +#if !defined(AT32_TMR3_SUPPRESS_ISR) +#if !defined(AT32_TMR3_HANDLER) +#error "AT32_TMR3_HANDLER not defined" +#endif +/** + * @brief TMR3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR3_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR3 */ + +#if AT32_GPT_USE_TMR4 || defined(__DOXYGEN__) +#if !defined(AT32_TMR4_SUPPRESS_ISR) +#if !defined(AT32_TMR4_HANDLER) +#error "AT32_TMR4_HANDLER not defined" +#endif +/** + * @brief TMR4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR4_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR4 */ + +#if AT32_GPT_USE_TMR5 || defined(__DOXYGEN__) +#if !defined(AT32_TMR5_SUPPRESS_ISR) +#if !defined(AT32_TMR5_HANDLER) +#error "AT32_TMR5_HANDLER not defined" +#endif +/** + * @brief TMR5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR5_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR5 */ + +#if AT32_GPT_USE_TMR9 || defined(__DOXYGEN__) +#if !defined(AT32_TMR9_SUPPRESS_ISR) +#error "TMR9 ISR not defined by platform" +#endif /* !defined(AT32_TMR9_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR9 */ + +#if AT32_GPT_USE_TMR10 || defined(__DOXYGEN__) +#if !defined(AT32_TMR10_SUPPRESS_ISR) +#error "TMR10 ISR not defined by platform" +#endif /* !defined(AT32_TMR10_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR10 */ + +#if AT32_GPT_USE_TMR11 || defined(__DOXYGEN__) +#if !defined(AT32_TMR11_SUPPRESS_ISR) +#error "TMR11 ISR not defined by platform" +#endif /* !defined(AT32_TMR11_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR11 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if AT32_GPT_USE_TMR1 + /* Driver initialization.*/ + gptObjectInit(&GPTD1); + GPTD1.tmr = AT32_TMR1; + GPTD1.has_plus_mode = (bool)AT32_TMR1_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR2 + /* Driver initialization.*/ + gptObjectInit(&GPTD2); + GPTD2.tmr = AT32_TMR2; + GPTD2.has_plus_mode = (bool)AT32_TMR2_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR3 + /* Driver initialization.*/ + gptObjectInit(&GPTD3); + GPTD3.tmr = AT32_TMR3; + GPTD3.has_plus_mode = (bool)AT32_TMR3_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR4 + /* Driver initialization.*/ + gptObjectInit(&GPTD4); + GPTD4.tmr = AT32_TMR4; + GPTD4.has_plus_mode = (bool)AT32_TMR4_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR5 + /* Driver initialization.*/ + gptObjectInit(&GPTD5); + GPTD5.tmr = AT32_TMR5; + GPTD5.has_plus_mode = (bool)AT32_TMR5_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR9 + /* Driver initialization.*/ + gptObjectInit(&GPTD9); + GPTD9.tmr = AT32_TMR9; + GPTD9.has_plus_mode = (bool)AT32_TMR9_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR10 + /* Driver initialization.*/ + gptObjectInit(&GPTD10); + GPTD10.tmr = AT32_TMR10; + GPTD10.has_plus_mode = (bool)AT32_TMR10_IS_32BITS; +#endif + +#if AT32_GPT_USE_TMR11 + /* Driver initialization.*/ + gptObjectInit(&GPTD11); + GPTD11.tmr = AT32_TMR11; + GPTD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint16_t div; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if AT32_GPT_USE_TMR1 + if (&GPTD1 == gptp) { + crmEnableTMR1(true); + crmResetTMR1(); +#if !defined(AT32_TMR1_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR1_OVF_NUMBER, AT32_GPT_TMR1_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_GPT_USE_TMR2 + if (&GPTD2 == gptp) { + crmEnableTMR2(true); + crmResetTMR2(); +#if !defined(AT32_TMR2_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR2_NUMBER, AT32_GPT_TMR2_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_GPT_USE_TMR3 + if (&GPTD3 == gptp) { + crmEnableTMR3(true); + crmResetTMR3(); +#if !defined(AT32_TMR3_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR3_NUMBER, AT32_GPT_TMR3_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_GPT_USE_TMR4 + if (&GPTD4 == gptp) { + crmEnableTMR4(true); + crmResetTMR4(); +#if !defined(AT32_TMR4_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR4_NUMBER, AT32_GPT_TMR4_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_GPT_USE_TMR5 + if (&GPTD5 == gptp) { + crmEnableTMR5(true); + crmResetTMR5(); +#if !defined(AT32_TMR5_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR5_NUMBER, AT32_GPT_TMR5_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_GPT_USE_TMR9 + if (&GPTD9 == gptp) { + crmEnableTMR9(true); + crmResetTMR9(); +#if !defined(AT32_TMR9_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR9_NUMBER, AT32_GPT_TMR9_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_GPT_USE_TMR10 + if (&GPTD10 == gptp) { + crmEnableTMR10(true); + crmResetTMR10(); +#if !defined(AT32_TMR10_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR10_NUMBER, AT32_GPT_TMR10_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_GPT_USE_TMR11 + if (&GPTD11 == gptp) { + crmEnableTMR11(true); + crmResetTMR11(); +#if !defined(AT32_TMR11_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR11_NUMBER, AT32_GPT_TMR11_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK2; + } +#endif + } + + /* Prescaler value calculation.*/ + div = (uint16_t)((gptp->clock / gptp->config->frequency) - 1); + osalDbgAssert(((uint32_t)(div + 1) * gptp->config->frequency) == gptp->clock, + "invalid frequency"); + + /* If timer counter is 32bits.*/ + if (gptp->has_plus_mode) { + gptp->tmr->CTRL1 = AT32_TMR_CTRL1_PMEN; + } + + /* Timer configuration.*/ + gptp->tmr->CTRL2 = gptp->config->ctrl2; + gptp->tmr->DIV = div; /* Prescaler value. */ + gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->IDEN = gptp->config->iden & /* DMA-related IDEN bits. */ + ~AT32_TMR_IDEN_IRQ_MASK; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->CTRL1 = 0; /* Timer disabled. */ + gptp->tmr->IDEN = 0; /* All IRQs disabled. */ + gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + +#if AT32_GPT_USE_TMR1 + if (&GPTD1 == gptp) { +#if !defined(AT32_TMR1_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR1_OVF_NUMBER); +#endif + crmDisableTMR1(); + } +#endif + +#if AT32_GPT_USE_TMR2 + if (&GPTD2 == gptp) { +#if !defined(AT32_TMR2_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR2_NUMBER); +#endif + crmDisableTMR2(); + } +#endif + +#if AT32_GPT_USE_TMR3 + if (&GPTD3 == gptp) { +#if !defined(AT32_TMR3_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR3_NUMBER); +#endif + crmDisableTMR3(); + } +#endif + +#if AT32_GPT_USE_TMR4 + if (&GPTD4 == gptp) { +#if !defined(AT32_TMR4_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR4_NUMBER); +#endif + crmDisableTMR4(); + } +#endif + +#if AT32_GPT_USE_TMR5 + if (&GPTD5 == gptp) { +#if !defined(AT32_TMR5_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR5_NUMBER); +#endif + crmDisableTMR5(); + } +#endif + +#if AT32_GPT_USE_TMR9 + if (&GPTD9 == gptp) { +#if !defined(AT32_TMR9_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR9_NUMBER); +#endif + crmDisableTMR9(); + } +#endif + +#if AT32_GPT_USE_TMR10 + if (&GPTD10 == gptp) { +#if !defined(AT32_TMR10_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR10_NUMBER); +#endif + crmDisableTMR10(); + } +#endif + +#if AT32_GPT_USE_TMR11 + if (&GPTD11 == gptp) { +#if !defined(AT32_TMR11_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR11_NUMBER); +#endif + crmDisableTMR11(); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->PR = (uint32_t)(interval - 1U); /* Time constant. */ + gptp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ + gptp->tmr->CVAL = 0; /* Reset counter. */ + + /* NOTE: After generating the OVFSWTR event it takes several clock cycles + before ISTS bit 0 goes to 1. This is why the clearing of CVAL has been + inserted before the clearing of ISTS, to give it some time.*/ + gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + if (NULL != gptp->config->callback) + gptp->tmr->IDEN |= AT32_TMR_IDEN_OVFIEN; /* Update Event IRQ enabled.*/ + gptp->tmr->CTRL1 |= AT32_TMR_CTRL1_PRBEN | AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->CTRL1 &= ~(AT32_TMR_CTRL1_PRBEN | AT32_TMR_CTRL1_OVFS | + AT32_TMR_CTRL1_TMREN); /* Initially stopped. */ + gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + + /* All interrupts disabled.*/ + gptp->tmr->IDEN &= ~AT32_TMR_IDEN_IRQ_MASK; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->PR = (uint32_t)(interval - 1U); /* Time constant. */ + gptp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ + gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->CTRL1 |= AT32_TMR_CTRL1_OCMEN | AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; + while (!(gptp->tmr->ISTS & AT32_TMR_ISTS_OVFIF)) + ; + gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ +} + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + * + * @notapi + */ +void gpt_lld_serve_interrupt(GPTDriver *gptp) { + uint32_t ists; + + ists = gptp->tmr->ISTS; + ists &= gptp->tmr->IDEN & AT32_TMR_IDEN_IRQ_MASK; + gptp->tmr->ISTS = ~ists; + if ((ists & AT32_TMR_ISTS_OVFIF) != 0) { + _gpt_isr_invoke_cb(gptp); + } +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h new file mode 100644 index 0000000000..d3ba5ffb65 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h @@ -0,0 +1,529 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/hal_gpt_lld.h + * @brief AT32 GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef HAL_GPT_LLD_H +#define HAL_GPT_LLD_H + +#include "at32_tmr.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR1) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR1 FALSE +#endif + +/** + * @brief GPTD2 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR2) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR2 FALSE +#endif + +/** + * @brief GPTD3 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR3) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR3 FALSE +#endif + +/** + * @brief GPTD4 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR4) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR4 FALSE +#endif + +/** + * @brief GPTD5 driver enable switch. + * @details If set to @p TRUE the support for GPTD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR5) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR5 FALSE +#endif + +/** + * @brief GPTD9 driver enable switch. + * @details If set to @p TRUE the support for GPTD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR9) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR9 FALSE +#endif + +/** + * @brief GPTD10 driver enable switch. + * @details If set to @p TRUE the support for GPTD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR10) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR10 FALSE +#endif + +/** + * @brief GPTD11 driver enable switch. + * @details If set to @p TRUE the support for GPTD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR11) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR11 FALSE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR1_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD2 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR2_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD3 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR3_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD4 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR4_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD5 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR5_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD9 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR9_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD10 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR10_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR10_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD11 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR11_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR11_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(AT32_HAS_TMR1) +#define AT32_HAS_TMR1 FALSE +#endif + +#if !defined(AT32_HAS_TMR2) +#define AT32_HAS_TMR2 FALSE +#endif + +#if !defined(AT32_HAS_TMR3) +#define AT32_HAS_TMR3 FALSE +#endif + +#if !defined(AT32_HAS_TMR4) +#define AT32_HAS_TMR4 FALSE +#endif + +#if !defined(AT32_HAS_TMR5) +#define AT32_HAS_TMR5 FALSE +#endif + +#if !defined(AT32_HAS_TMR9) +#define AT32_HAS_TMR9 FALSE +#endif + +#if !defined(AT32_HAS_TMR10) +#define AT32_HAS_TMR10 FALSE +#endif + +#if !defined(AT32_HAS_TMR11) +#define AT32_HAS_TMR11 FALSE +#endif + +#if AT32_GPT_USE_TMR1 && !AT32_HAS_TMR1 +#error "TMR1 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR2 && !AT32_HAS_TMR2 +#error "TMR2 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR3 && !AT32_HAS_TMR3 +#error "TMR3 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR4 && !AT32_HAS_TMR4 +#error "TMR4 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR5 && !AT32_HAS_TMR5 +#error "TMR5 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR9 && !AT32_HAS_TMR9 +#error "TMR9 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR10 && !AT32_HAS_TMR10 +#error "TMR10 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR11 && !AT32_HAS_TMR11 +#error "TMR11 not present in the selected device" +#endif + +#if !AT32_GPT_USE_TMR1 && !AT32_GPT_USE_TMR2 && \ + !AT32_GPT_USE_TMR3 && !AT32_GPT_USE_TMR4 && \ + !AT32_GPT_USE_TMR5 && !AT32_GPT_USE_TMR9 && \ + !AT32_GPT_USE_TMR10 && !AT32_GPT_USE_TMR11 +#error "GPT driver activated but no TMR peripheral assigned" +#endif + +/* Checks on allocation of TMRx units.*/ +#if AT32_GPT_USE_TMR1 +#if defined(AT32_TMR1_IS_USED) +#error "GPTD1 requires TMR1 but the timer is already used" +#else +#define AT32_TMR1_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR2 +#if defined(AT32_TMR2_IS_USED) +#error "GPTD2 requires TMR2 but the timer is already used" +#else +#define AT32_TMR2_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR3 +#if defined(AT32_TMR3_IS_USED) +#error "GPTD3 requires TMR3 but the timer is already used" +#else +#define AT32_TMR3_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR4 +#if defined(AT32_TMR4_IS_USED) +#error "GPTD4 requires TMR4 but the timer is already used" +#else +#define AT32_TMR4_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR5 +#if defined(AT32_TMR5_IS_USED) +#error "GPTD5 requires TMR5 but the timer is already used" +#else +#define AT32_TMR5_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR9 +#if defined(AT32_TMR9_IS_USED) +#error "GPTD9 requires TMR9 but the timer is already used" +#else +#define AT32_TMR9_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR10 +#if defined(AT32_TMR10_IS_USED) +#error "GPTD10 requires TMR10 but the timer is already used" +#else +#define AT32_TMR10_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR11 +#if defined(AT32_TMR11_IS_USED) +#error "GPTD11 requires TMR11 but the timer is already used" +#else +#define AT32_TMR11_IS_USED +#endif +#endif + +/* IRQ priority checks.*/ +#if AT32_GPT_USE_TMR1 && !defined(AT32_TMR1_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR1" +#endif + +#if AT32_GPT_USE_TMR2 && !defined(AT32_TMR2_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR2" +#endif + +#if AT32_GPT_USE_TMR3 && !defined(AT32_TMR3_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR3" +#endif + +#if AT32_GPT_USE_TMR4 && !defined(AT32_TMR4_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR4" +#endif + +#if AT32_GPT_USE_TMR5 && !defined(AT32_TMR5_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR5" +#endif + +#if AT32_GPT_USE_TMR9 && !defined(AT32_TMR9_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR9" +#endif + +#if AT32_GPT_USE_TMR10 && !defined(AT32_TMR10_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR10_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR10" +#endif + +#if AT32_GPT_USE_TMR11 && !defined(AT32_TMR11_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR11_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR11" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + * @note This callback can be set to @p NULL but in that case the + * one-shot mode cannot be used. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ + /** + * @brief TMR CTRL2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t ctrl2; + /** + * @brief TMR IDEN register initialization data. + * @note The value of this field should normally be equal to zero. + * @note Only the DMA-related bits can be specified in this field. + */ + uint32_t iden; +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Presence of plus mode. + */ + bool has_plus_mode; + /** + * @brief Pointer to the TMRx registers block. + */ + at32_tmr_t *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must be running in continuous mode. + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) \ + ((gptp)->tmr->PR = (uint32_t)((interval) - 1U)) + +/** + * @brief Returns the interval of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current interval. + * + * @notapi + */ +#define gpt_lld_get_interval(gptp) ((gptcnt_t)((gptp)->tmr->PR + 1U)) + +/** + * @brief Returns the counter value of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * @note The nature of the counter is not defined, it may count upward + * or downward, it could be continuously running or not. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current counter value. + * + * @notapi + */ +#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->tmr->CVAL) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_GPT_USE_TMR1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if AT32_GPT_USE_TMR2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if AT32_GPT_USE_TMR3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if AT32_GPT_USE_TMR4 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#if AT32_GPT_USE_TMR5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD5; +#endif + +#if AT32_GPT_USE_TMR9 && !defined(__DOXYGEN__) +extern GPTDriver GPTD9; +#endif + +#if AT32_GPT_USE_TMR10 && !defined(__DOXYGEN__) +extern GPTDriver GPTD10; +#endif + +#if AT32_GPT_USE_TMR11 && !defined(__DOXYGEN__) +extern GPTDriver GPTD11; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); + void gpt_lld_serve_interrupt(GPTDriver *gptp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* HAL_GPT_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c new file mode 100644 index 0000000000..06ad33b847 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c @@ -0,0 +1,774 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Fabio Utzig and + Xo Wang. + */ + +/** + * @file TMRv1/hal_icu_lld.c + * @brief AT32 ICU subsystem low level driver header. + * + * @addtogroup ICU + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief ICUD1 driver identifier. + * @note The driver ICUD1 allocates the complex timer TMR1 when enabled. + */ +#if AT32_ICU_USE_TMR1 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + +/** + * @brief ICUD2 driver identifier. + * @note The driver ICUD1 allocates the timer TMR2 when enabled. + */ +#if AT32_ICU_USE_TMR2 || defined(__DOXYGEN__) +ICUDriver ICUD2; +#endif + +/** + * @brief ICUD3 driver identifier. + * @note The driver ICUD1 allocates the timer TMR3 when enabled. + */ +#if AT32_ICU_USE_TMR3 || defined(__DOXYGEN__) +ICUDriver ICUD3; +#endif + +/** + * @brief ICUD4 driver identifier. + * @note The driver ICUD4 allocates the timer TMR4 when enabled. + */ +#if AT32_ICU_USE_TMR4 || defined(__DOXYGEN__) +ICUDriver ICUD4; +#endif + +/** + * @brief ICUD5 driver identifier. + * @note The driver ICUD5 allocates the timer TMR5 when enabled. + */ +#if AT32_ICU_USE_TMR5 || defined(__DOXYGEN__) +ICUDriver ICUD5; +#endif + +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the timer TMR9 when enabled. + */ +#if AT32_ICU_USE_TMR9 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + +/** + * @brief ICUD10 driver identifier. + * @note The driver ICUD10 allocates the timer TMR10 when enabled. + */ +#if AT32_ICU_USE_TMR10 || defined(__DOXYGEN__) +ICUDriver ICUD10; +#endif + +/** + * @brief ICUD11 driver identifier. + * @note The driver ICUD11 allocates the timer TMR11 when enabled. + */ +#if AT32_ICU_USE_TMR11 || defined(__DOXYGEN__) +ICUDriver ICUD11; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static bool icu_lld_wait_edge(ICUDriver *icup) { + uint32_t ists; + bool result; + + /* Polled mode so re-enabling the interrupts while the operation is + performed.*/ + osalSysUnlock(); + + /* Polling the right bit depending on the input channel.*/ + if (icup->config->channel == ICU_CHANNEL_1) { + /* Waiting for an edge.*/ + while (((ists = icup->tmr->ISTS) & + (AT32_TMR_ISTS_C1IF | AT32_TMR_ISTS_OVFIF)) == 0) + ; + } + else { + /* Waiting for an edge.*/ + while (((ists = icup->tmr->ISTS) & + (AT32_TMR_ISTS_C2IF | AT32_TMR_ISTS_OVFIF)) == 0) + ; + } + + /* Edge or overflow?*/ + result = (ists & AT32_TMR_ISTS_OVFIF) != 0 ? true : false; + + /* Done, disabling interrupts again.*/ + osalSysLock(); + + /* Resetting all flags.*/ + icup->tmr->ISTS &= ~(AT32_TMR_ISTS_C1IF | + AT32_TMR_ISTS_C2IF | + AT32_TMR_ISTS_OVFIF); + + return result; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_ICU_USE_TMR1 || defined(__DOXYGEN__) +#if !defined(AT32_TMR1_SUPPRESS_ISR) +#if !defined(AT32_TMR1_OVF_HANDLER) +#error "AT32_TMR1_OVF_HANDLER not defined" +#endif +/** + * @brief TMR1 overflow interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_OVF_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(AT32_TMR1_CH_HANDLER) +#error "AT32_TMR1_CH_HANDLER not defined" +#endif +/** + * @brief TMR1 channel interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_CH_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR1_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR1 */ + +#if AT32_ICU_USE_TMR2 || defined(__DOXYGEN__) +#if !defined(AT32_TMR2_SUPPRESS_ISR) +#if !defined(AT32_TMR2_HANDLER) +#error "AT32_TMR2_HANDLER not defined" +#endif +/** + * @brief TMR2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR2_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR2 */ + +#if AT32_ICU_USE_TMR3 || defined(__DOXYGEN__) +#if !defined(AT32_TMR3_SUPPRESS_ISR) +#if !defined(AT32_TMR3_HANDLER) +#error "AT32_TMR3_HANDLER not defined" +#endif +/** + * @brief TMR3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR3_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR3 */ + +#if AT32_ICU_USE_TMR4 || defined(__DOXYGEN__) +#if !defined(AT32_TMR4_SUPPRESS_ISR) +#if !defined(AT32_TMR4_HANDLER) +#error "AT32_TMR4_HANDLER not defined" +#endif +/** + * @brief TMR4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR4_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR4 */ + +#if AT32_ICU_USE_TMR5 || defined(__DOXYGEN__) +#if !defined(AT32_TMR5_SUPPRESS_ISR) +#if !defined(AT32_TMR5_HANDLER) +#error "AT32_TMR5_HANDLER not defined" +#endif +/** + * @brief TMR5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR5_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR5 */ + +#if AT32_ICU_USE_TMR9 || defined(__DOXYGEN__) +#if !defined(AT32_TMR9_SUPPRESS_ISR) +#error "TMR9 ISR not defined by platform" +#endif /* !defined(AT32_TMR9_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR9 */ + +#if AT32_ICU_USE_TMR10 || defined(__DOXYGEN__) +#if !defined(AT32_TMR10_SUPPRESS_ISR) +#error "TMR10 ISR not defined by platform" +#endif /* !defined(AT32_TMR10_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR10 */ + +#if AT32_ICU_USE_TMR11 || defined(__DOXYGEN__) +#if !defined(AT32_TMR11_SUPPRESS_ISR) +#error "TMR11 ISR not defined by platform" +#endif /* !defined(AT32_TMR11_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR11 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ICU driver initialization. + * + * @notapi + */ +void icu_lld_init(void) { + +#if AT32_ICU_USE_TMR1 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); + ICUD1.tmr = AT32_TMR1; + ICUD1.has_plus_mode = (bool)AT32_TMR1_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR2 + /* Driver initialization.*/ + icuObjectInit(&ICUD2); + ICUD2.tmr = AT32_TMR2; + ICUD2.has_plus_mode = (bool)AT32_TMR2_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR3 + /* Driver initialization.*/ + icuObjectInit(&ICUD3); + ICUD3.tmr = AT32_TMR3; + ICUD3.has_plus_mode = (bool)AT32_TMR3_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR4 + /* Driver initialization.*/ + icuObjectInit(&ICUD4); + ICUD4.tmr = AT32_TMR4; + ICUD4.has_plus_mode = (bool)AT32_TMR4_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR5 + /* Driver initialization.*/ + icuObjectInit(&ICUD5); + ICUD5.tmr = AT32_TMR5; + ICUD5.has_plus_mode = (bool)AT32_TMR5_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR9 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.tmr = AT32_TMR9; + ICUD9.has_plus_mode = (bool)AT32_TMR9_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR10 + /* Driver initialization.*/ + icuObjectInit(&ICUD10); + ICUD10.tmr = AT32_TMR10; + ICUD10.has_plus_mode = (bool)AT32_TMR10_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR11 + /* Driver initialization.*/ + icuObjectInit(&ICUD11); + ICUD11.tmr = AT32_TMR11; + ICUD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; +#endif +} + +/** + * @brief Configures and activates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start(ICUDriver *icup) { + uint32_t div; + + osalDbgAssert((icup->config->channel == ICU_CHANNEL_1) || + (icup->config->channel == ICU_CHANNEL_2), + "invalid input"); + + if (icup->state == ICU_STOP) { + /* Clock activation and timer reset.*/ +#if AT32_ICU_USE_TMR1 + if (&ICUD1 == icup) { + crmEnableTMR1(true); + crmResetTMR1(); +#if !defined(AT32_TMR1_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR1_OVF_NUMBER, AT32_ICU_TMR1_IRQ_PRIORITY); + nvicEnableVector(AT32_TMR1_CH_NUMBER, AT32_ICU_TMR1_IRQ_PRIORITY); +#endif + icup->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_ICU_USE_TMR2 + if (&ICUD2 == icup) { + crmEnableTMR2(true); + crmResetTMR2(); +#if !defined(AT32_TMR2_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR2_NUMBER, AT32_ICU_TMR2_IRQ_PRIORITY); +#endif + icup->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_ICU_USE_TMR3 + if (&ICUD3 == icup) { + crmEnableTMR3(true); + crmResetTMR3(); +#if !defined(AT32_TMR3_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR3_NUMBER, AT32_ICU_TMR3_IRQ_PRIORITY); +#endif + icup->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_ICU_USE_TMR4 + if (&ICUD4 == icup) { + crmEnableTMR4(true); + crmResetTMR4(); +#if !defined(AT32_TMR4_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR4_NUMBER, AT32_ICU_TMR4_IRQ_PRIORITY); +#endif + icup->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_ICU_USE_TMR5 + if (&ICUD5 == icup) { + crmEnableTMR5(true); + crmResetTMR5(); +#if !defined(AT32_TMR5_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR5_NUMBER, AT32_ICU_TMR5_IRQ_PRIORITY); +#endif + icup->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_ICU_USE_TMR9 + if (&ICUD9 == icup) { + crmEnableTMR9(true); + crmResetTMR9(); + icup->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_ICU_USE_TMR10 + if (&ICUD10 == icup) { + crmEnableTMR10(true); + crmResetTMR10(); + icup->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_ICU_USE_TMR11 + if (&ICUD11 == icup) { + crmEnableTMR11(true); + crmResetTMR11(); + icup->clock = AT32_TMRCLK2; + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + icup->tmr->CTRL1 = 0; /* Timer disabled. */ + icup->tmr->CDT[0] = 0; /* Comparator 1 disabled. */ + icup->tmr->CDT[1] = 0; /* Comparator 2 disabled. */ + icup->tmr->CVAL = 0; /* Counter reset to zero. */ + } + + /* If timer counter is 32bits.*/ + if (icup->has_plus_mode) { + icup->tmr->CTRL1 = AT32_TMR_CTRL1_PMEN; + } + + /* Timer configuration.*/ + icup->tmr->ISTS = 0; /* Clear eventual pending IRQs. */ + icup->tmr->IDEN = icup->config->iden & /* DMA-related IDEN settings. */ + ~AT32_TMR_IDEN_IRQ_MASK; + div = (icup->clock / icup->config->frequency) - 1; + osalDbgAssert((div <= 0xFFFF) && + ((div + 1) * icup->config->frequency) == icup->clock, + "invalid frequency"); + icup->tmr->DIV = div; + if (icup->config->pr == 0U) { + /* Zero is an invalid value and is turned in maximum value, also for + legacy configurations compatibility.*/ + icup->tmr->PR = 0xFFFFFFFFU; + } + else { + icup->tmr->PR = icup->config->pr; + } + + if (icup->config->channel == ICU_CHANNEL_1) { + /* Selected input 1. + CM1_C1C = 01 = CH1 Input on C1IFP1. + CM1_C2C = 10 = CH2 Input on C1IFP2.*/ + icup->tmr->CM1 = AT32_TMR_CM1_C1C(1) | AT32_TMR_CM1_C2C(2); + + /* STCTRL_STIS = 101, input is C1IF1. + STCTRL_SMSEL = 100, reset on rising edge.*/ + icup->tmr->STCTRL = AT32_TMR_STCTRL_STIS(5) | AT32_TMR_STCTRL_SMSEL(4); + + /* The CCTRL settings depend on the selected trigger mode. + ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. + ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) + icup->tmr->CCTRL = AT32_TMR_CCTRL_C1EN | + AT32_TMR_CCTRL_C2EN | AT32_TMR_CCTRL_C2P; + else + icup->tmr->CCTRL = AT32_TMR_CCTRL_C1EN | AT32_TMR_CCTRL_C1P | + AT32_TMR_CCTRL_C2EN; + + /* Direct pointers to the capture registers in order to make reading + data faster from within callbacks.*/ + icup->wccrp = &icup->tmr->CDT[1]; + icup->pccrp = &icup->tmr->CDT[0]; + } + else { + /* Selected input 2. + CM1_C1C = 10 = CH1 Input on C2IFP1. + CM1_C2C = 01 = CH2 Input on C2IFP2.*/ + icup->tmr->CM1 = AT32_TMR_CM1_C1C(2) | AT32_TMR_CM1_C2C(1); + + /* STCTRL_STIS = 110, input is C1IF2. + STCTRL_SMSEL = 100, reset on rising edge.*/ + icup->tmr->STCTRL = AT32_TMR_STCTRL_STIS(6) | AT32_TMR_STCTRL_SMSEL(4); + + /* The CCTRL settings depend on the selected trigger mode. + ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. + ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ + if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) + icup->tmr->CCTRL = AT32_TMR_CCTRL_C1EN | AT32_TMR_CCTRL_C1P | + AT32_TMR_CCTRL_C2EN; + else + icup->tmr->CCTRL = AT32_TMR_CCTRL_C1EN | + AT32_TMR_CCTRL_C2EN | AT32_TMR_CCTRL_C2P; + + /* Direct pointers to the capture registers in order to make reading + data faster from within callbacks.*/ + icup->wccrp = &icup->tmr->CDT[0]; + icup->pccrp = &icup->tmr->CDT[1]; + } +} + +/** + * @brief Deactivates the ICU peripheral. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop(ICUDriver *icup) { + + if (icup->state == ICU_READY) { + /* Clock deactivation.*/ + icup->tmr->CTRL1 = 0; /* Timer disabled. */ + icup->tmr->IDEN = 0; /* All IRQs disabled. */ + icup->tmr->ISTS = 0; /* Clear eventual pending IRQs. */ + +#if AT32_ICU_USE_TMR1 + if (&ICUD1 == icup) { +#if !defined(AT32_TMR1_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR1_OVF_NUMBER); + nvicDisableVector(AT32_TMR1_CH_NUMBER); +#endif + crmDisableTMR1(); + } +#endif + +#if AT32_ICU_USE_TMR2 + if (&ICUD2 == icup) { +#if !defined(AT32_TMR2_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR2_NUMBER); +#endif + crmDisableTMR2(); + } +#endif + +#if AT32_ICU_USE_TMR3 + if (&ICUD3 == icup) { +#if !defined(AT32_TMR3_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR3_NUMBER); +#endif + crmDisableTMR3(); + } +#endif + +#if AT32_ICU_USE_TMR4 + if (&ICUD4 == icup) { +#if !defined(AT32_TMR4_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR4_NUMBER); +#endif + crmDisableTMR4(); + } +#endif + +#if AT32_ICU_USE_TMR5 + if (&ICUD5 == icup) { +#if !defined(AT32_TMR5_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR5_NUMBER); +#endif + crmDisableTMR5(); + } +#endif + +#if AT32_ICU_USE_TMR9 + if (&ICUD9 == icup) { + crmDisableTMR9(); + } +#endif + +#if AT32_ICU_USE_TMR10 + if (&ICUD10 == icup) { + crmDisableTMR10(); + } +#endif + +#if AT32_ICU_USE_TMR11 + if (&ICUD11 == icup) { + crmDisableTMR11(); + } +#endif + } +} + +/** + * @brief Starts the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_start_capture(ICUDriver *icup) { + + /* Triggering an OVFSWTR and clearing the IRQ status.*/ + icup->tmr->SWEVT |= AT32_TMR_SWEVT_OVFSWTR; + icup->tmr->ISTS = 0; + + /* Timer is started.*/ + icup->tmr->CTRL1 |= AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; +} + +/** + * @brief Waits for a completed capture. + * @note The operation is performed in polled mode. + * @note In order to use this function notifications must be disabled. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The capture status. + * @retval false if the capture is successful. + * @retval true if a timer overflow occurred. + * + * @notapi + */ +bool icu_lld_wait_capture(ICUDriver *icup) { + + /* If the driver is still in the ICU_WAITING state then we need to wait + for the first activation edge.*/ + if (icup->state == ICU_WAITING) + if (icu_lld_wait_edge(icup)) + return true; + + /* This edge marks the availability of a capture result.*/ + return icu_lld_wait_edge(icup); +} + +/** + * @brief Stops the input capture. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_stop_capture(ICUDriver *icup) { + + /* Timer stopped.*/ + icup->tmr->CTRL1 &= ~(AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN); + + /* All interrupts disabled.*/ + icup->tmr->IDEN &= ~AT32_TMR_IDEN_IRQ_MASK; +} + +/** + * @brief Enables notifications. + * @pre The ICU unit must have been activated using @p icuStart() and the + * capture started using @p icuStartCapture(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_enable_notifications(ICUDriver *icup) { + uint32_t iden = icup->tmr->IDEN; + + /* If interrupts were already enabled then the operation is skipped. + This is done in order to avoid clearing the ISTS and risk losing + pending interrupts.*/ + if ((iden & AT32_TMR_IDEN_IRQ_MASK) == 0) { + /* Previously triggered IRQs are ignored, status cleared.*/ + icup->tmr->ISTS = 0; + + if (icup->config->channel == ICU_CHANNEL_1) { + /* Enabling periodic callback on CC1.*/ + iden |= AT32_TMR_IDEN_C1IEN; + + /* Optionally enabling width callback on CC2.*/ + if (icup->config->width_cb != NULL) + iden |= AT32_TMR_IDEN_C2IEN; + } + else { + /* Enabling periodic callback on CC2.*/ + iden |= AT32_TMR_IDEN_C2IEN; + + /* Optionally enabling width callback on CC1.*/ + if (icup->config->width_cb != NULL) + iden |= AT32_TMR_IDEN_C1IEN; + } + + /* If an overflow callback is defined then also the overflow callback + is enabled.*/ + if (icup->config->overflow_cb != NULL) + iden |= AT32_TMR_IDEN_OVFIEN; + + /* One single atomic write.*/ + icup->tmr->IDEN = iden; + } +} + +/** + * @brief Disables notifications. + * @pre The ICU unit must have been activated using @p icuStart() and the + * capture started using @p icuStartCapture(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_disable_notifications(ICUDriver *icup) { + + /* All interrupts disabled.*/ + icup->tmr->IDEN &= ~AT32_TMR_IDEN_IRQ_MASK; +} + +/** + * @brief Shared IRQ handler. + * + * @param[in] icup pointer to the @p ICUDriver object + * + * @notapi + */ +void icu_lld_serve_interrupt(ICUDriver *icup) { + uint32_t ists; + + ists = icup->tmr->ISTS; + ists &= icup->tmr->IDEN & AT32_TMR_IDEN_IRQ_MASK; + icup->tmr->ISTS = ~ists; + if (icup->config->channel == ICU_CHANNEL_1) { + if ((ists & AT32_TMR_ISTS_C2IF) != 0) + _icu_isr_invoke_width_cb(icup); + if ((ists & AT32_TMR_ISTS_C1IF) != 0) + _icu_isr_invoke_period_cb(icup); + } + else { + if ((ists & AT32_TMR_ISTS_C1IF) != 0) + _icu_isr_invoke_width_cb(icup); + if ((ists & AT32_TMR_ISTS_C2IF) != 0) + _icu_isr_invoke_period_cb(icup); + } + if ((ists & AT32_TMR_ISTS_OVFIF) != 0) + _icu_isr_invoke_overflow_cb(icup); +} + +#endif /* HAL_USE_ICU */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h new file mode 100644 index 0000000000..b101125433 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h @@ -0,0 +1,567 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/hal_icu_lld.h + * @brief AT32 ICU subsystem low level driver header. + * + * @addtogroup ICU + * @{ + */ + +#ifndef HAL_ICU_LLD_H +#define HAL_ICU_LLD_H + +#if HAL_USE_ICU || defined(__DOXYGEN__) + +#include "at32_tmr.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICUD1 driver enable switch. + * @details If set to @p TRUE the support for ICUD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR1) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR1 FALSE +#endif + +/** + * @brief ICUD2 driver enable switch. + * @details If set to @p TRUE the support for ICUD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR2) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR2 FALSE +#endif + +/** + * @brief ICUD3 driver enable switch. + * @details If set to @p TRUE the support for ICUD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR3) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR3 FALSE +#endif + +/** + * @brief ICUD4 driver enable switch. + * @details If set to @p TRUE the support for ICUD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR4) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR4 FALSE +#endif + +/** + * @brief ICUD5 driver enable switch. + * @details If set to @p TRUE the support for ICUD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR5) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR5 FALSE +#endif + +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR9) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR9 FALSE +#endif + +/** + * @brief ICUD10 driver enable switch. + * @details If set to @p TRUE the support for ICUD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR10) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR10 FALSE +#endif + +/** + * @brief ICUD11 driver enable switch. + * @details If set to @p TRUE the support for ICUD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR11) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR11 FALSE +#endif + +/** + * @brief ICUD1 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR1_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD2 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR2_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD3 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR3_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD4 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR4_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD5 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR5_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD9 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR9_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD10 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR10_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR10_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD11 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR11_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR11_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(AT32_HAS_TMR1) +#define AT32_HAS_TMR1 FALSE +#endif + +#if !defined(AT32_HAS_TMR2) +#define AT32_HAS_TMR2 FALSE +#endif + +#if !defined(AT32_HAS_TMR3) +#define AT32_HAS_TMR3 FALSE +#endif + +#if !defined(AT32_HAS_TMR4) +#define AT32_HAS_TMR4 FALSE +#endif + +#if !defined(AT32_HAS_TMR5) +#define AT32_HAS_TMR5 FALSE +#endif + +#if !defined(AT32_HAS_TMR9) +#define AT32_HAS_TMR9 FALSE +#endif + +#if !defined(AT32_HAS_TMR10) +#define AT32_HAS_TMR10 FALSE +#endif + +#if !defined(AT32_HAS_TMR11) +#define AT32_HAS_TMR11 FALSE +#endif + +#if AT32_ICU_USE_TMR1 && !AT32_HAS_TMR1 +#error "TMR1 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR2 && !AT32_HAS_TMR2 +#error "TMR2 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR3 && !AT32_HAS_TMR3 +#error "TMR3 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR4 && !AT32_HAS_TMR4 +#error "TMR4 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR5 && !AT32_HAS_TMR5 +#error "TMR5 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR9 && !AT32_HAS_TMR9 +#error "TMR9 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR10 && !AT32_HAS_TMR10 +#error "TMR10 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR11 && !AT32_HAS_TMR11 +#error "TMR11 not present in the selected device" +#endif + +#if !AT32_ICU_USE_TMR1 && !AT32_ICU_USE_TMR2 && \ + !AT32_ICU_USE_TMR3 && !AT32_ICU_USE_TMR4 && \ + !AT32_ICU_USE_TMR5 && !AT32_ICU_USE_TMR9 && \ + !AT32_ICU_USE_TMR10 && !AT32_ICU_USE_TMR11 +#error "ICU driver activated but no TMR peripheral assigned" +#endif + +/* Checks on allocation of TMRx units.*/ +#if AT32_ICU_USE_TMR1 +#if defined(AT32_TMR1_IS_USED) +#error "ICUD1 requires TMR1 but the timer is already used" +#else +#define AT32_TMR1_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR2 +#if defined(AT32_TMR2_IS_USED) +#error "ICUD2 requires TMR2 but the timer is already used" +#else +#define AT32_TMR2_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR3 +#if defined(AT32_TMR3_IS_USED) +#error "ICUD3 requires TMR3 but the timer is already used" +#else +#define AT32_TMR3_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR4 +#if defined(AT32_TMR4_IS_USED) +#error "ICUD4 requires TMR4 but the timer is already used" +#else +#define AT32_TMR4_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR5 +#if defined(AT32_TMR5_IS_USED) +#error "ICUD5 requires TMR5 but the timer is already used" +#else +#define AT32_TMR5_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR9 +#if defined(AT32_TMR9_IS_USED) +#error "ICUD9 requires TMR9 but the timer is already used" +#else +#define AT32_TMR9_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR10 +#if defined(AT32_TMR10_IS_USED) +#error "ICUD10 requires TMR10 but the timer is already used" +#else +#define AT32_TMR10_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR11 +#if defined(AT32_TMR11_IS_USED) +#error "ICUD11 requires TMR11 but the timer is already used" +#else +#define AT32_TMR11_IS_USED +#endif +#endif + +/* IRQ priority checks.*/ +#if AT32_ICU_USE_TMR1 && !defined(AT32_TMR1_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR1" +#endif + +#if AT32_ICU_USE_TMR2 && !defined(AT32_TMR2_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR2" +#endif + +#if AT32_ICU_USE_TMR3 && !defined(AT32_TMR3_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR3" +#endif + +#if AT32_ICU_USE_TMR4 && !defined(AT32_TMR4_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR4" +#endif + +#if AT32_ICU_USE_TMR5 && !defined(AT32_TMR5_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR5" +#endif + +#if AT32_ICU_USE_TMR9 && !defined(AT32_TMR9_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR9" +#endif + +#if AT32_ICU_USE_TMR10 && !defined(AT32_TMR10_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR10_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR10" +#endif + +#if AT32_ICU_USE_TMR11 && !defined(AT32_TMR11_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR11_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR11" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ICU driver mode. + */ +typedef enum { + ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */ + ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */ +} icumode_t; + +/** + * @brief ICU frequency type. + */ +typedef uint32_t icufreq_t; + +/** + * @brief ICU channel type. + */ +typedef enum { + ICU_CHANNEL_1 = 0, /**< Use TMRxCH1. */ + ICU_CHANNEL_2 = 1, /**< Use TMRxCH2. */ +} icuchannel_t; + +/** + * @brief ICU counter type. + */ +typedef uint32_t icucnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Driver mode. + */ + icumode_t mode; + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + icufreq_t frequency; + /** + * @brief Callback for pulse width measurement. + */ + icucallback_t width_cb; + /** + * @brief Callback for cycle period measurement. + */ + icucallback_t period_cb; + /** + * @brief Callback for timer overflow. + */ + icucallback_t overflow_cb; + /* End of the mandatory fields.*/ + /** + * @brief Timer input channel to be used. + * @note Only inputs TMRx 1 and 2 are supported. + */ + icuchannel_t channel; + /** + * @brief TMR IDEN register initialization data. + * @note The value of this field should normally be equal to zero. + * @note Only the DMA-related bits can be specified in this field. + */ + uint32_t iden; + /** + * @brief TMR PR register initialization data. + * @note The value of this field should normally be equal to 0xFFFFFFFFU. + */ + uint32_t pr; +} ICUConfig; + +/** + * @brief Structure representing an ICU driver. + */ +struct ICUDriver { + /** + * @brief Driver state. + */ + icustate_t state; + /** + * @brief Current configuration data. + */ + const ICUConfig *config; +#if defined(ICU_DRIVER_EXT_FIELDS) + ICU_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Presence of plus mode. + */ + bool has_plus_mode; + /** + * @brief Pointer to the TMRx registers block. + */ + at32_tmr_t *tmr; + /** + * @brief CDT register used for width capture. + */ + volatile uint32_t *wccrp; + /** + * @brief CDT register used for period capture. + */ + volatile uint32_t *pccrp; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the width of the latest pulse. + * @details The pulse width is defined as number of ticks between the start + * edge and the stop edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1) + +/** + * @brief Returns the width of the latest cycle. + * @details The cycle width is defined as number of ticks between a start + * edge and the next start edge. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The number of ticks. + * + * @notapi + */ +#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1) + +/** + * @brief Check on notifications status. + * + * @param[in] icup pointer to the @p ICUDriver object + * @return The notifications status. + * @retval false if notifications are not enabled. + * @retval true if notifications are enabled. + * + * @notapi + */ +#define icu_lld_are_notifications_enabled(icup) \ + (bool)(((icup)->tmr->IDEN & AT32_TMR_IDEN_IRQ_MASK) != 0) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_ICU_USE_TMR1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + +#if AT32_ICU_USE_TMR2 && !defined(__DOXYGEN__) +extern ICUDriver ICUD2; +#endif + +#if AT32_ICU_USE_TMR3 && !defined(__DOXYGEN__) +extern ICUDriver ICUD3; +#endif + +#if AT32_ICU_USE_TMR4 && !defined(__DOXYGEN__) +extern ICUDriver ICUD4; +#endif + +#if AT32_ICU_USE_TMR5 && !defined(__DOXYGEN__) +extern ICUDriver ICUD5; +#endif + +#if AT32_ICU_USE_TMR9 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + +#if AT32_ICU_USE_TMR10 && !defined(__DOXYGEN__) +extern ICUDriver ICUD10; +#endif + +#if AT32_ICU_USE_TMR11 && !defined(__DOXYGEN__) +extern ICUDriver ICUD11; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void icu_lld_init(void); + void icu_lld_start(ICUDriver *icup); + void icu_lld_stop(ICUDriver *icup); + void icu_lld_start_capture(ICUDriver *icup); + bool icu_lld_wait_capture(ICUDriver *icup); + void icu_lld_stop_capture(ICUDriver *icup); + void icu_lld_enable_notifications(ICUDriver *icup); + void icu_lld_disable_notifications(ICUDriver *icup); + void icu_lld_serve_interrupt(ICUDriver *icup); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ICU */ + +#endif /* HAL_ICU_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c new file mode 100644 index 0000000000..f894318dfd --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c @@ -0,0 +1,790 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/hal_pwm_lld.c + * @brief AT32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer TMR1 when enabled. + */ +#if AT32_PWM_USE_TMR1 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + * @note The driver PWMD2 allocates the timer TMR2 when enabled. + */ +#if AT32_PWM_USE_TMR2 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/** + * @brief PWMD3 driver identifier. + * @note The driver PWMD3 allocates the timer TMR3 when enabled. + */ +#if AT32_PWM_USE_TMR3 || defined(__DOXYGEN__) +PWMDriver PWMD3; +#endif + +/** + * @brief PWMD4 driver identifier. + * @note The driver PWMD4 allocates the timer TMR4 when enabled. + */ +#if AT32_PWM_USE_TMR4 || defined(__DOXYGEN__) +PWMDriver PWMD4; +#endif + +/** + * @brief PWMD5 driver identifier. + * @note The driver PWMD5 allocates the timer TMR5 when enabled. + */ +#if AT32_PWM_USE_TMR5 || defined(__DOXYGEN__) +PWMDriver PWMD5; +#endif + +/** + * @brief PWMD9 driver identifier. + * @note The driver PWMD9 allocates the timer TMR9 when enabled. + */ +#if AT32_PWM_USE_TMR9 || defined(__DOXYGEN__) +PWMDriver PWMD9; +#endif + +/** + * @brief PWMD10 driver identifier. + * @note The driver PWMD10 allocates the timer TMR10 when enabled. + */ +#if AT32_PWM_USE_TMR10 || defined(__DOXYGEN__) +PWMDriver PWMD10; +#endif + +/** + * @brief PWMD11 driver identifier. + * @note The driver PWMD11 allocates the timer TMR11 when enabled. + */ +#if AT32_PWM_USE_TMR11 || defined(__DOXYGEN__) +PWMDriver PWMD11; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_PWM_USE_TMR1 || defined(__DOXYGEN__) +#if !defined(AT32_TMR1_SUPPRESS_ISR) +#if !defined(AT32_TMR1_OVF_HANDLER) +#error "AT32_TMR1_OVF_HANDLER not defined" +#endif +/** + * @brief TMR1 overflow interrupt handler. + * @note It is assumed that this interrupt is only activated if the callback + * pointer is not equal to @p NULL in order to not perform an extra + * check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_OVF_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(AT32_TMR1_CH_HANDLER) +#error "AT32_TMR1_CH_HANDLER not defined" +#endif +/** + * @brief TMR1 channel interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR1_CH_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR1_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR1 */ + +#if AT32_PWM_USE_TMR2 || defined(__DOXYGEN__) +#if !defined(AT32_TMR2_SUPPRESS_ISR) +#if !defined(AT32_TMR2_HANDLER) +#error "AT32_TMR2_HANDLER not defined" +#endif +/** + * @brief TMR2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR2_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR2 */ + +#if AT32_PWM_USE_TMR3 || defined(__DOXYGEN__) +#if !defined(AT32_TMR3_SUPPRESS_ISR) +#if !defined(AT32_TMR3_HANDLER) +#error "AT32_TMR3_HANDLER not defined" +#endif +/** + * @brief TMR3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR3_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR3 */ + +#if AT32_PWM_USE_TMR4 || defined(__DOXYGEN__) +#if !defined(AT32_TMR4_SUPPRESS_ISR) +#if !defined(AT32_TMR4_HANDLER) +#error "AT32_TMR4_HANDLER not defined" +#endif +/** + * @brief TMR4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR4_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR4 */ + +#if AT32_PWM_USE_TMR5 || defined(__DOXYGEN__) +#if !defined(AT32_TMR5_SUPPRESS_ISR) +#if !defined(AT32_TMR5_HANDLER) +#error "AT32_TMR5_HANDLER not defined" +#endif +/** + * @brief TMR5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR5_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR5 */ + +#if AT32_PWM_USE_TMR9 || defined(__DOXYGEN__) +#if !defined(AT32_TMR9_SUPPRESS_ISR) +#error "TMR9 ISR not defined by platform" +#endif /* !defined(AT32_TMR9_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR9 */ + +#if AT32_PWM_USE_TMR10 || defined(__DOXYGEN__) +#if !defined(AT32_TMR10_SUPPRESS_ISR) +#error "TMR10 ISR not defined by platform" +#endif /* !defined(AT32_TMR10_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR10 */ + +#if AT32_PWM_USE_TMR11 || defined(__DOXYGEN__) +#if !defined(AT32_TMR11_SUPPRESS_ISR) +#error "TMR11 ISR not defined by platform" +#endif /* !defined(AT32_TMR11_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR11 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if AT32_PWM_USE_TMR1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.channels = AT32_TMR1_CHANNELS; + PWMD1.tmr = AT32_TMR1; + PWMD1.has_brk = true; + PWMD1.has_plus_mode = (bool)AT32_TMR1_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR2 + /* Driver initialization.*/ + pwmObjectInit(&PWMD2); + PWMD2.channels = AT32_TMR2_CHANNELS; + PWMD2.tmr = AT32_TMR2; + PWMD2.has_brk = false; + PWMD2.has_plus_mode = (bool)AT32_TMR2_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR3 + /* Driver initialization.*/ + pwmObjectInit(&PWMD3); + PWMD3.channels = AT32_TMR3_CHANNELS; + PWMD3.tmr = AT32_TMR3; + PWMD3.has_brk = false; + PWMD3.has_plus_mode = (bool)AT32_TMR3_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR4 + /* Driver initialization.*/ + pwmObjectInit(&PWMD4); + PWMD4.channels = AT32_TMR4_CHANNELS; + PWMD4.tmr = AT32_TMR4; + PWMD4.has_brk = false; + PWMD4.has_plus_mode = (bool)AT32_TMR4_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR5 + /* Driver initialization.*/ + pwmObjectInit(&PWMD5); + PWMD5.channels = AT32_TMR5_CHANNELS; + PWMD5.tmr = AT32_TMR5; + PWMD5.has_brk = false; + PWMD5.has_plus_mode = (bool)AT32_TMR5_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR9 + /* Driver initialization.*/ + pwmObjectInit(&PWMD9); + PWMD9.channels = AT32_TMR9_CHANNELS; + PWMD9.tmr = AT32_TMR9; + PWMD9.has_brk = false; + PWMD9.has_plus_mode = (bool)AT32_TMR9_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR10 + /* Driver initialization.*/ + pwmObjectInit(&PWMD10); + PWMD10.channels = AT32_TMR10_CHANNELS; + PWMD10.tmr = AT32_TMR10; + PWMD10.has_brk = false; + PWMD10.has_plus_mode = (bool)AT32_TMR10_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR11 + /* Driver initialization.*/ + pwmObjectInit(&PWMD11); + PWMD11.channels = AT32_TMR11_CHANNELS; + PWMD11.tmr = AT32_TMR11; + PWMD11.has_brk = false; + PWMD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t div; + uint32_t cctrl; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if AT32_PWM_USE_TMR1 + if (&PWMD1 == pwmp) { + crmEnableTMR1(true); + crmResetTMR1(); +#if !defined(AT32_TMR1_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR1_OVF_NUMBER, AT32_PWM_TMR1_IRQ_PRIORITY); + nvicEnableVector(AT32_TMR1_CH_NUMBER, AT32_PWM_TMR1_IRQ_PRIORITY); +#endif + pwmp->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_PWM_USE_TMR2 + if (&PWMD2 == pwmp) { + crmEnableTMR2(true); + crmResetTMR2(); +#if !defined(AT32_TMR2_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR2_NUMBER, AT32_PWM_TMR2_IRQ_PRIORITY); +#endif + pwmp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_PWM_USE_TMR3 + if (&PWMD3 == pwmp) { + crmEnableTMR3(true); + crmResetTMR3(); +#if !defined(AT32_TMR3_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR3_NUMBER, AT32_PWM_TMR3_IRQ_PRIORITY); +#endif + pwmp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_PWM_USE_TMR4 + if (&PWMD4 == pwmp) { + crmEnableTMR4(true); + crmResetTMR4(); +#if !defined(AT32_TMR4_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR4_NUMBER, AT32_PWM_TMR4_IRQ_PRIORITY); +#endif + pwmp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_PWM_USE_TMR5 + if (&PWMD5 == pwmp) { + crmEnableTMR5(true); + crmResetTMR5(); +#if !defined(AT32_TMR5_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR5_NUMBER, AT32_PWM_TMR5_IRQ_PRIORITY); +#endif + pwmp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_PWM_USE_TMR9 + if (&PWMD9 == pwmp) { + crmEnableTMR9(true); + crmResetTMR9(); + pwmp->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_PWM_USE_TMR10 + if (&PWMD10 == pwmp) { + crmEnableTMR10(true); + crmResetTMR10(); + pwmp->clock = AT32_TMRCLK2; + } +#endif + +#if AT32_PWM_USE_TMR11 + if (&PWMD11 == pwmp) { + crmEnableTMR11(true); + crmResetTMR11(); + pwmp->clock = AT32_TMRCLK2; + } +#endif + + /* All channels configured in PWM1 mode with preload enabled and will + stay that way until the driver is stopped.*/ + pwmp->tmr->CM1 = AT32_TMR_CM1_C1OCTRL(6) | AT32_TMR_CM1_C1OBEN | + AT32_TMR_CM1_C2OCTRL(6) | AT32_TMR_CM1_C2OBEN; + pwmp->tmr->CM2 = AT32_TMR_CM2_C3OCTRL(6) | AT32_TMR_CM2_C3OBEN | + AT32_TMR_CM2_C4OCTRL(6) | AT32_TMR_CM2_C4OBEN; + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->tmr->CTRL1 = 0; /* Timer disabled. */ + pwmp->tmr->CDT[0] = 0; /* Comparator 1 disabled. */ + pwmp->tmr->CDT[1] = 0; /* Comparator 2 disabled. */ + pwmp->tmr->CDT[2] = 0; /* Comparator 3 disabled. */ + pwmp->tmr->CDT[3] = 0; /* Comparator 4 disabled. */ + pwmp->tmr->CVAL = 0; /* Counter reset to zero. */ + } + + /* If timer counter is 32bits.*/ + if (pwmp->has_plus_mode) { + pwmp->tmr->CTRL1 = AT32_TMR_CTRL1_PMEN; + } + + /* Timer configuration.*/ + div = (pwmp->clock / pwmp->config->frequency) - 1; + osalDbgAssert((div <= 0xFFFF) && + ((div + 1) * pwmp->config->frequency) == pwmp->clock, + "invalid frequency"); + pwmp->tmr->DIV = div; + pwmp->tmr->PR = pwmp->period - 1; + pwmp->tmr->CTRL2 = pwmp->config->ctrl2; + + /* Output enables and polarities setup.*/ + cctrl = 0; + switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C1P; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C1EN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C2P; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C2EN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C3P; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C3EN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C4P; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C4EN; + /* Falls through.*/ + default: + ; + } + if (pwmp->has_brk) { + switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C1CP; + /* Falls through.*/ + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C1CEN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C2CP; + /* Falls through.*/ + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C2CEN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + cctrl |= AT32_TMR_CCTRL_C3CP; + /* Falls through.*/ + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + cctrl |= AT32_TMR_CCTRL_C3CEN; + /* Falls through.*/ + default: + ; + } + } + + pwmp->tmr->CCTRL = cctrl; + pwmp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ + pwmp->tmr->ISTS = 0; /* Clear pending IRQs. */ + pwmp->tmr->IDEN = pwmp->config->iden & /* DMA-related IDEN settings. */ + ~AT32_TMR_IDEN_IRQ_MASK; + if (pwmp->has_brk) { + pwmp->tmr->BRK = pwmp->config->brk | AT32_TMR_BRK_OEN; + } + /* Timer configured and started.*/ + pwmp->tmr->CTRL1 |= AT32_TMR_CTRL1_PRBEN | AT32_TMR_CTRL1_OVFS | + AT32_TMR_CTRL1_TMREN; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->tmr->CTRL1 = 0; /* Timer disabled. */ + pwmp->tmr->IDEN = 0; /* All IRQs disabled. */ + pwmp->tmr->ISTS = 0; /* Clear eventual pending IRQs. */ + if (pwmp->has_brk) { + pwmp->tmr->BRK = 0; + } + +#if AT32_PWM_USE_TMR1 + if (&PWMD1 == pwmp) { +#if !defined(AT32_TMR1_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR1_OVF_NUMBER); + nvicDisableVector(AT32_TMR1_CH_NUMBER); +#endif + crmDisableTMR1(); + } +#endif + +#if AT32_PWM_USE_TMR2 + if (&PWMD2 == pwmp) { +#if !defined(AT32_TMR2_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR2_NUMBER); +#endif + crmDisableTMR2(); + } +#endif + +#if AT32_PWM_USE_TMR3 + if (&PWMD3 == pwmp) { +#if !defined(AT32_TMR3_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR3_NUMBER); +#endif + crmDisableTMR3(); + } +#endif + +#if AT32_PWM_USE_TMR4 + if (&PWMD4 == pwmp) { +#if !defined(AT32_TMR4_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR4_NUMBER); +#endif + crmDisableTMR4(); + } +#endif + +#if AT32_PWM_USE_TMR5 + if (&PWMD5 == pwmp) { +#if !defined(AT32_TMR5_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR5_NUMBER); +#endif + crmDisableTMR5(); + } +#endif + +#if AT32_PWM_USE_TMR9 + if (&PWMD9 == pwmp) { + crmDisableTMR9(); + } +#endif + +#if AT32_PWM_USE_TMR10 + if (&PWMD10 == pwmp) { + crmDisableTMR10(); + } +#endif + +#if AT32_PWM_USE_TMR11 + if (&PWMD11 == pwmp) { + crmDisableTMR11(); + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + /* Changing channel duty cycle on the fly.*/ + pwmp->tmr->CDT[channel] = width; +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + pwmp->tmr->CDT[channel] = 0; + pwmp->tmr->IDEN &= ~(2 << channel); +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { + uint32_t iden = pwmp->tmr->IDEN; + + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((iden & AT32_TMR_IDEN_OVFIEN) == 0) { + pwmp->tmr->ISTS = ~AT32_TMR_ISTS_OVFIF; + pwmp->tmr->IDEN = iden | AT32_TMR_IDEN_OVFIEN; + } +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { + + pwmp->tmr->IDEN &= ~AT32_TMR_IDEN_OVFIEN; +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + uint32_t iden = pwmp->tmr->IDEN; + + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((iden & (2 << channel)) == 0) { + pwmp->tmr->ISTS = ~(2 << channel); + pwmp->tmr->IDEN = iden | (2 << channel); + } +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + + pwmp->tmr->IDEN &= ~(2 << channel); +} + +/** + * @brief Common TMR2...TMR5,TMR9 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint32_t ists; + + ists = pwmp->tmr->ISTS; + ists &= pwmp->tmr->IDEN & AT32_TMR_IDEN_IRQ_MASK; + pwmp->tmr->ISTS = ~ists; + if (((ists & AT32_TMR_ISTS_C1IF) != 0) && + (pwmp->config->channels[0].callback != NULL)) + pwmp->config->channels[0].callback(pwmp); + if (((ists & AT32_TMR_ISTS_C2IF) != 0) && + (pwmp->config->channels[1].callback != NULL)) + pwmp->config->channels[1].callback(pwmp); + if (((ists & AT32_TMR_ISTS_C3IF) != 0) && + (pwmp->config->channels[2].callback != NULL)) + pwmp->config->channels[2].callback(pwmp); + if (((ists & AT32_TMR_ISTS_C4IF) != 0) && + (pwmp->config->channels[3].callback != NULL)) + pwmp->config->channels[3].callback(pwmp); + if (((ists & AT32_TMR_ISTS_OVFIF) != 0) && (pwmp->config->callback != NULL)) + pwmp->config->callback(pwmp); +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h new file mode 100644 index 0000000000..5a40b54841 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h @@ -0,0 +1,610 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TMRv1/hal_pwm_lld.h + * @brief AT32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H +#define HAL_PWM_LLD_H + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +#include "at32_tmr.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS AT32_TMR_MAX_CHANNELS + +/** + * @name AT32-specific PWM complementary output mode macros + * @{ + */ +/** + * @brief Complementary output modes mask. + * @note This is an AT32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 + +/** + * @brief Complementary output not driven. + * @note This is an AT32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 + +/** + * @brief Complementary output, active is logic level one. + * @note This is an AT32-specific setting. + * @note This setting is only available if the timer supports the + * BRK register. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 + +/** + * @brief Complementary output, active is logic level zero. + * @note This is an AT32-specific setting. + * @note This setting is only available if the timer supports the + * BRK register. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR1) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR1 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR2) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR2 FALSE +#endif + +/** + * @brief PWMD3 driver enable switch. + * @details If set to @p TRUE the support for PWMD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR3) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR3 FALSE +#endif + +/** + * @brief PWMD4 driver enable switch. + * @details If set to @p TRUE the support for PWMD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR4) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR4 FALSE +#endif + +/** + * @brief PWMD5 driver enable switch. + * @details If set to @p TRUE the support for PWMD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR5) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR5 FALSE +#endif + +/** + * @brief PWMD9 driver enable switch. + * @details If set to @p TRUE the support for PWMD9 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR9) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR9 FALSE +#endif + +/** + * @brief PWMD10 driver enable switch. + * @details If set to @p TRUE the support for PWMD10 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR10) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR10 FALSE +#endif + +/** + * @brief PWMD11 driver enable switch. + * @details If set to @p TRUE the support for PWMD11 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR11) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR11 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD2 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD3 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD4 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR4_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD5 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR5_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD9 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR9_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD10 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR10_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR10_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD11 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR11_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR11_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if !defined(AT32_HAS_TMR1) +#define AT32_HAS_TMR1 FALSE +#endif + +#if !defined(AT32_HAS_TMR2) +#define AT32_HAS_TMR2 FALSE +#endif + +#if !defined(AT32_HAS_TMR3) +#define AT32_HAS_TMR3 FALSE +#endif + +#if !defined(AT32_HAS_TMR4) +#define AT32_HAS_TMR4 FALSE +#endif + +#if !defined(AT32_HAS_TMR5) +#define AT32_HAS_TMR5 FALSE +#endif + +#if !defined(AT32_HAS_TMR9) +#define AT32_HAS_TMR9 FALSE +#endif + +#if !defined(AT32_HAS_TMR10) +#define AT32_HAS_TMR10 FALSE +#endif + +#if !defined(AT32_HAS_TMR11) +#define AT32_HAS_TMR11 FALSE +#endif + +#if AT32_PWM_USE_TMR1 && !AT32_HAS_TMR1 +#error "TMR1 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR2 && !AT32_HAS_TMR2 +#error "TMR2 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR3 && !AT32_HAS_TMR3 +#error "TMR3 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR4 && !AT32_HAS_TMR4 +#error "TMR4 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR5 && !AT32_HAS_TMR5 +#error "TMR5 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR9 && !AT32_HAS_TMR9 +#error "TMR9 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR10 && !AT32_HAS_TMR10 +#error "TMR10 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR11 && !AT32_HAS_TMR11 +#error "TMR11 not present in the selected device" +#endif + +#if !AT32_PWM_USE_TMR1 && !AT32_PWM_USE_TMR2 && \ + !AT32_PWM_USE_TMR3 && !AT32_PWM_USE_TMR4 && \ + !AT32_PWM_USE_TMR5 && !AT32_PWM_USE_TMR9 && \ + !AT32_PWM_USE_TMR10 && !AT32_PWM_USE_TMR11 +#error "PWM driver activated but no TMR peripheral assigned" +#endif + +/* Checks on allocation of TMRx units.*/ +#if AT32_PWM_USE_TMR1 +#if defined(AT32_TMR1_IS_USED) +#error "PWMD1 requires TMR1 but the timer is already used" +#else +#define AT32_TMR1_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR2 +#if defined(AT32_TMR2_IS_USED) +#error "PWMD2 requires TMR2 but the timer is already used" +#else +#define AT32_TMR2_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR3 +#if defined(AT32_TMR3_IS_USED) +#error "PWMD3 requires TMR3 but the timer is already used" +#else +#define AT32_TMR3_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR4 +#if defined(AT32_TMR4_IS_USED) +#error "PWMD4 requires TMR4 but the timer is already used" +#else +#define AT32_TMR4_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR5 +#if defined(AT32_TMR5_IS_USED) +#error "PWMD5 requires TMR5 but the timer is already used" +#else +#define AT32_TMR5_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR9 +#if defined(AT32_TMR9_IS_USED) +#error "PWMD9 requires TMR9 but the timer is already used" +#else +#define AT32_TMR9_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR10 +#if defined(AT32_TMR10_IS_USED) +#error "PWMD10 requires TMR10 but the timer is already used" +#else +#define AT32_TMR10_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR11 +#if defined(AT32_TMR11_IS_USED) +#error "PWMD11 requires TMR11 but the timer is already used" +#else +#define AT32_TMR11_IS_USED +#endif +#endif + +/* IRQ priority checks.*/ +#if AT32_PWM_USE_TMR1 && !defined(AT32_TMR1_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR1" +#endif + +#if AT32_PWM_USE_TMR2 && !defined(AT32_TMR2_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR2" +#endif + +#if AT32_PWM_USE_TMR3 && !defined(AT32_TMR3_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR3" +#endif + +#if AT32_PWM_USE_TMR4 && !defined(AT32_TMR4_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR4" +#endif + +#if AT32_PWM_USE_TMR5 && !defined(AT32_TMR5_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR5" +#endif + +#if AT32_PWM_USE_TMR9 && !defined(AT32_TMR9_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR9" +#endif + +#if AT32_PWM_USE_TMR10 && !defined(AT32_TMR10_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR10_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR10" +#endif + +#if AT32_PWM_USE_TMR11 && !defined(AT32_TMR11_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR11_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR11" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief TMR CTRL2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t ctrl2; + /** + * @brief TMR BRK (break & dead-time) register initialization data. + * @note The value of this field should normally be equal to zero. + */ \ + uint32_t brk; + /** + * @brief TMR IDEN register initialization data. + * @note The value of this field should normally be equal to zero. + * @note Only the DMA-related bits can be specified in this field. + */ + uint32_t iden; +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Presence of BRK register. + */ + bool has_brk; + /** + * @brief Presence of plus mode. + */ + bool has_plus_mode; + /** + * @brief Pointer to the TMRx registers block. + */ + at32_tmr_t *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tmr->PR = ((period) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_PWM_USE_TMR1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if AT32_PWM_USE_TMR2 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#if AT32_PWM_USE_TMR3 && !defined(__DOXYGEN__) +extern PWMDriver PWMD3; +#endif + +#if AT32_PWM_USE_TMR4 && !defined(__DOXYGEN__) +extern PWMDriver PWMD4; +#endif + +#if AT32_PWM_USE_TMR5 && !defined(__DOXYGEN__) +extern PWMDriver PWMD5; +#endif + +#if AT32_PWM_USE_TMR9 && !defined(__DOXYGEN__) +extern PWMDriver PWMD9; +#endif + +#if AT32_PWM_USE_TMR10 && !defined(__DOXYGEN__) +extern PWMDriver PWMD10; +#endif + +#if AT32_PWM_USE_TMR11 && !defined(__DOXYGEN__) +extern PWMDriver PWMD11; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_serve_interrupt(PWMDriver *pwmp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* HAL_PWM_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc new file mode 100644 index 0000000000..c07c8ff8c6 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USART/at32_uart4.inc + * @brief Shared UART4 handler. + * + * @addtogroup AT32_UART4_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_UART4) +#error "AT32_HAS_UART4 not defined in registry" +#endif + +#if AT32_HAS_UART4 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_UART4_PRIORITY) +#error "AT32_IRQ_UART4_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_UART4_PRIORITY" +#endif + +#endif /* AT32_HAS_UART4 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void uart4_irq_init(void) { +#if defined(AT32_UART4_IS_USED) + nvicEnableVector(AT32_UART4_NUMBER, AT32_IRQ_UART4_PRIORITY); +#endif +} + +static inline void uart4_irq_deinit(void) { +#if defined(AT32_UART4_IS_USED) + nvicDisableVector(AT32_UART4_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_UART4_IS_USED) || defined(__DOXYGEN__) +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_UART4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_SERIAL +#if AT32_SERIAL_USE_UART4 + sd_lld_serve_interrupt(&SD4); +#endif +#endif + +#if HAL_USE_UART +#if AT32_UART_USE_UART4 + uart_lld_serve_interrupt(&UARTD4); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc new file mode 100644 index 0000000000..fff0dadae3 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USART/at32_uart5.inc + * @brief Shared UART5 handler. + * + * @addtogroup AT32_UART5_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_UART5) +#error "AT32_HAS_UART5 not defined in registry" +#endif + +#if AT32_HAS_UART5 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_UART5_PRIORITY) +#error "AT32_IRQ_UART5_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_UART5_PRIORITY" +#endif + +#endif /* AT32_HAS_UART5 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void uart5_irq_init(void) { +#if defined(AT32_UART5_IS_USED) + nvicEnableVector(AT32_UART5_NUMBER, AT32_IRQ_UART5_PRIORITY); +#endif +} + +static inline void uart5_irq_deinit(void) { +#if defined(AT32_UART5_IS_USED) + nvicDisableVector(AT32_UART5_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_UART5_IS_USED) || defined(__DOXYGEN__) +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_UART5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_SERIAL +#if AT32_SERIAL_USE_UART5 + sd_lld_serve_interrupt(&SD5); +#endif +#endif + +#if HAL_USE_UART +#if AT32_UART_USE_UART5 + uart_lld_serve_interrupt(&UARTD5); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc new file mode 100644 index 0000000000..f215b4f7c7 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USART/at32_usart1.inc + * @brief Shared USART1 handler. + * + * @addtogroup AT32_USART1_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_USART1) +#error "AT32_HAS_USART1 not defined in registry" +#endif + +#if AT32_HAS_USART1 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_USART1_PRIORITY) +#error "AT32_IRQ_USART1_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_USART1_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_USART1_PRIORITY" +#endif + +#endif /* AT32_HAS_USART1 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void usart1_irq_init(void) { +#if defined(AT32_USART1_IS_USED) + nvicEnableVector(AT32_USART1_NUMBER, AT32_IRQ_USART1_PRIORITY); +#endif +} + +static inline void usart1_irq_deinit(void) { +#if defined(AT32_USART1_IS_USED) + nvicDisableVector(AT32_USART1_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_USART1_IS_USED) || defined(__DOXYGEN__) +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_SERIAL +#if AT32_SERIAL_USE_USART1 + sd_lld_serve_interrupt(&SD1); +#endif +#endif + +#if HAL_USE_UART +#if AT32_UART_USE_USART1 + uart_lld_serve_interrupt(&UARTD1); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc new file mode 100644 index 0000000000..1652352b72 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USART/at32_usart2.inc + * @brief Shared USART2 handler. + * + * @addtogroup AT32_USART2_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_USART2) +#error "AT32_HAS_USART2 not defined in registry" +#endif + +#if AT32_HAS_USART2 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_USART2_PRIORITY) +#error "AT32_IRQ_USART2_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_USART2_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_USART2_PRIORITY" +#endif + +#endif /* AT32_HAS_USART2 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void usart2_irq_init(void) { +#if defined(AT32_USART2_IS_USED) + nvicEnableVector(AT32_USART2_NUMBER, AT32_IRQ_USART2_PRIORITY); +#endif +} + +static inline void usart2_irq_deinit(void) { +#if defined(AT32_USART2_IS_USED) + nvicDisableVector(AT32_USART2_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_USART2_IS_USED) || defined(__DOXYGEN__) +/** + * @brief USART2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_SERIAL +#if AT32_SERIAL_USE_USART2 + sd_lld_serve_interrupt(&SD2); +#endif +#endif + +#if HAL_USE_UART +#if AT32_UART_USE_USART2 + uart_lld_serve_interrupt(&UARTD2); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc new file mode 100644 index 0000000000..a00a1a09ad --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USART/at32_usart3.inc + * @brief Shared USART3 handler. + * + * @addtogroup AT32_USART3_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(AT32_HAS_USART3) +#error "AT32_HAS_USART3 not defined in registry" +#endif + +#if AT32_HAS_USART3 + +/* Priority settings checks.*/ +#if !defined(AT32_IRQ_USART3_PRIORITY) +#error "AT32_IRQ_USART3_PRIORITY not defined in mcuconf.h" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_USART3_PRIORITY) +#error "Invalid IRQ priority assigned to AT32_IRQ_USART3_PRIORITY" +#endif + +#endif /* AT32_HAS_USART3 */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void usart3_irq_init(void) { +#if defined(AT32_USART3_IS_USED) + nvicEnableVector(AT32_USART3_NUMBER, AT32_IRQ_USART3_PRIORITY); +#endif +} + +static inline void usart3_irq_deinit(void) { +#if defined(AT32_USART3_IS_USED) + nvicDisableVector(AT32_USART3_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(AT32_USART3_IS_USED) || defined(__DOXYGEN__) +/** + * @brief USART3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_SERIAL +#if AT32_SERIAL_USE_USART3 + sd_lld_serve_interrupt(&SD3); +#endif +#endif + +#if HAL_USE_UART +#if AT32_UART_USE_USART3 + uart_lld_serve_interrupt(&UARTD3); +#endif +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/driver.mk b/os/hal/ports/AT32/LLD/USARTv1/driver.mk new file mode 100644 index 0000000000..652a4742fe --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/driver.mk @@ -0,0 +1,13 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1 diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c new file mode 100644 index 0000000000..bbb1d2dd6f --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c @@ -0,0 +1,517 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv1/hal_serial_lld.c + * @brief AT32 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 serial driver identifier.*/ +#if AT32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** @brief USART2 serial driver identifier.*/ +#if AT32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** @brief USART3 serial driver identifier.*/ +#if AT32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/** @brief UART4 serial driver identifier.*/ +#if AT32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + +/** @brief UART5 serial driver identifier.*/ +#if AT32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +SerialDriver SD5; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = +{ + SERIAL_DEFAULT_BITRATE, + 0, + USART_CTRL2_STOPBN1_BITS, + 0 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { + uint32_t baudr; + USART_TypeDef *u = sdp->usart; + + baudr = (uint32_t)((sdp->clock + config->speed/2) / config->speed); + +#if defined(USART_CTRL1_OVER8) + /* Correcting BAUDR value when oversampling by 8 instead of 16. + Fraction is still 4 bits wide, but only lower 3 bits used. + Mantissa is doubled, but Fraction is left the same.*/ + if (config->ctrl1 & USART_CTRL1_OVER8) + baudr = ((baudr & ~7) * 2) | (baudr & 7); +#endif + + osalDbgAssert(baudr < 0x10000, "invalid BAUDR value"); + + u->BAUDR = baudr; + + /* Note that some bits are enforced.*/ + u->CTRL2 = config->ctrl2 | USART_CTRL2_BFIEN; + u->CTRL3 = config->ctrl3 | USART_CTRL3_ERRIEN; + u->CTRL1 = config->ctrl1 | USART_CTRL1_UEN | USART_CTRL1_PERRIEN | + USART_CTRL1_RDBFIEN | USART_CTRL1_TEN | + USART_CTRL1_REN; + u->STS = 0; + (void)u->STS; /* STS reset step 1.*/ + (void)u->DT; /* DT reset step 2.*/ + + /* Deciding mask to be applied on the data register on receive, this is + required in order to mask out the parity bit.*/ + if ((config->ctrl1 & (USART_CTRL1_DBN | USART_CTRL1_PEN)) == USART_CTRL1_PEN) { + sdp->rxmask = 0x7F; + } + else { + sdp->rxmask = 0xFF; + } +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] u pointer to an USART I/O block + */ +static void usart_deinit(USART_TypeDef *u) { + + u->CTRL1 = 0; + u->CTRL2 = 0; + u->CTRL3 = 0; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sts USART STS register value + */ +static void set_error(SerialDriver *sdp, uint16_t sts) { + eventflags_t status = 0; + + if (sts & USART_STS_ROERR) + status |= SD_OVERRUN_ERROR; + if (sts & USART_STS_PERR) + status |= SD_PARITY_ERROR; + if (sts & USART_STS_FERR) + status |= SD_FRAMING_ERROR; + if (sts & USART_STS_NERR) + status |= SD_NOISE_ERROR; + chnAddFlagsI(sdp, status); +} + +#if AT32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +static void notify1(io_queue_t *qp) { + + (void)qp; + USART1->CTRL1 |= USART_CTRL1_TDBEIEN | USART_CTRL1_TDCIEN; +} +#endif + +#if AT32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +static void notify2(io_queue_t *qp) { + + (void)qp; + USART2->CTRL1 |= USART_CTRL1_TDBEIEN | USART_CTRL1_TDCIEN; +} +#endif + +#if AT32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +static void notify3(io_queue_t *qp) { + + (void)qp; + USART3->CTRL1 |= USART_CTRL1_TDBEIEN | USART_CTRL1_TDCIEN; +} +#endif + +#if AT32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +static void notify4(io_queue_t *qp) { + + (void)qp; + UART4->CTRL1 |= USART_CTRL1_TDBEIEN | USART_CTRL1_TDCIEN; +} +#endif + +#if AT32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +static void notify5(io_queue_t *qp) { + + (void)qp; + UART5->CTRL1 |= USART_CTRL1_TDBEIEN | USART_CTRL1_TDCIEN; +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +#if !defined(AT32_USART1_SUPPRESS_ISR) +#if !defined(AT32_USART1_HANDLER) +#error "AT32_USART1_HANDLER not defined" +#endif +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + sd_lld_serve_interrupt(&SD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +#if AT32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +#if !defined(AT32_USART2_SUPPRESS_ISR) +#if !defined(AT32_USART2_HANDLER) +#error "AT32_USART2_HANDLER not defined" +#endif +/** + * @brief USART2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + sd_lld_serve_interrupt(&SD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +#if AT32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +#if !defined(AT32_USART3_SUPPRESS_ISR) +#if !defined(AT32_USART3_HANDLER) +#error "AT32_USART3_HANDLER not defined" +#endif +/** + * @brief USART3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + sd_lld_serve_interrupt(&SD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +#if AT32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +#if !defined(AT32_UART4_SUPPRESS_ISR) +#if !defined(AT32_UART4_HANDLER) +#error "AT32_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_UART4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + sd_lld_serve_interrupt(&SD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +#if AT32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +#if !defined(AT32_UART5_SUPPRESS_ISR) +#if !defined(AT32_UART5_HANDLER) +#error "AT32_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_UART5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + sd_lld_serve_interrupt(&SD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if AT32_SERIAL_USE_USART1 + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = USART1; + SD1.clock = AT32_PCLK2; +#if !defined(AT32_USART1_SUPPRESS_ISR) && defined(AT32_USART1_NUMBER) + nvicEnableVector(AT32_USART1_NUMBER, AT32_SERIAL_USART1_PRIORITY); +#endif +#endif + +#if AT32_SERIAL_USE_USART2 + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = USART2; + SD2.clock = AT32_PCLK1; +#if !defined(AT32_USART2_SUPPRESS_ISR) && defined(AT32_USART2_NUMBER) + nvicEnableVector(AT32_USART2_NUMBER, AT32_SERIAL_USART2_PRIORITY); +#endif +#endif + +#if AT32_SERIAL_USE_USART3 + sdObjectInit(&SD3, NULL, notify3); + SD3.usart = USART3; + SD3.clock = AT32_PCLK1; +#if !defined(AT32_USART3_SUPPRESS_ISR) && defined(AT32_USART3_NUMBER) + nvicEnableVector(AT32_USART3_NUMBER, AT32_SERIAL_USART3_PRIORITY); +#endif +#endif + +#if AT32_SERIAL_USE_UART4 + sdObjectInit(&SD4, NULL, notify4); + SD4.usart = UART4; + SD4.clock = AT32_PCLK1; +#if !defined(AT32_UART4_SUPPRESS_ISR) && defined(AT32_UART4_NUMBER) + nvicEnableVector(AT32_UART4_NUMBER, AT32_SERIAL_UART4_PRIORITY); +#endif +#endif + +#if AT32_SERIAL_USE_UART5 + sdObjectInit(&SD5, NULL, notify5); + SD5.usart = UART5; + SD5.clock = AT32_PCLK1; +#if !defined(AT32_UART5_SUPPRESS_ISR) && defined(AT32_UART5_NUMBER) + nvicEnableVector(AT32_UART5_NUMBER, AT32_SERIAL_UART5_PRIORITY); +#endif +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if AT32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + crmEnableUSART1(true); + } +#endif +#if AT32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + crmEnableUSART2(true); + } +#endif +#if AT32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + crmEnableUSART3(true); + } +#endif +#if AT32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + crmEnableUART4(true); + } +#endif +#if AT32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + crmEnableUART5(true); + } +#endif + } + usart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + usart_deinit(sdp->usart); +#if AT32_SERIAL_USE_USART1 + if (&SD1 == sdp) { + crmDisableUSART1(); + return; + } +#endif +#if AT32_SERIAL_USE_USART2 + if (&SD2 == sdp) { + crmDisableUSART2(); + return; + } +#endif +#if AT32_SERIAL_USE_USART3 + if (&SD3 == sdp) { + crmDisableUSART3(); + return; + } +#endif +#if AT32_SERIAL_USE_UART4 + if (&SD4 == sdp) { + crmDisableUART4(); + return; + } +#endif +#if AT32_SERIAL_USE_UART5 + if (&SD5 == sdp) { + crmDisableUART5(); + return; + } +#endif + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the USART + */ +void sd_lld_serve_interrupt(SerialDriver *sdp) { + USART_TypeDef *u = sdp->usart; + uint16_t ctrl1 = u->CTRL1; + uint16_t sts = u->STS; + + /* Special case, LIN break detection.*/ + if (sts & USART_STS_BFF) { + osalSysLockFromISR(); + chnAddFlagsI(sdp, SD_BREAK_DETECTED); + u->STS = ~USART_STS_BFF; + osalSysUnlockFromISR(); + } + + /* Data available.*/ + osalSysLockFromISR(); + while (sts & (USART_STS_RDBF | USART_STS_ROERR | USART_STS_NERR | USART_STS_FERR | + USART_STS_PERR)) { + uint8_t b; + + /* Error condition detection.*/ + if (sts & (USART_STS_ROERR | USART_STS_NERR | USART_STS_FERR | USART_STS_PERR)) + set_error(sdp, sts); + b = (uint8_t)u->DT & sdp->rxmask; + if (sts & USART_STS_RDBF) + sdIncomingDataI(sdp, b); + sts = u->STS; + } + osalSysUnlockFromISR(); + + /* Transmission buffer empty.*/ + if ((ctrl1 & USART_CTRL1_TDBEIEN) && (sts & USART_STS_TDBE)) { + msg_t b; + osalSysLockFromISR(); + b = oqGetI(&sdp->oqueue); + if (b < MSG_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + u->CTRL1 = ctrl1 & ~USART_CTRL1_TDBEIEN; + } + else + u->DT = b; + osalSysUnlockFromISR(); + } + + /* Physical transmission end.*/ + if ((ctrl1 & USART_CTRL1_TDCIEN) && (sts & USART_STS_TDC)) { + osalSysLockFromISR(); + if (oqIsEmptyI(&sdp->oqueue)) { + chnAddFlagsI(sdp, CHN_TRANSMISSION_END); + u->CTRL1 = ctrl1 & ~USART_CTRL1_TDCIEN; + } + osalSysUnlockFromISR(); + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h new file mode 100644 index 0000000000..41da42389e --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h @@ -0,0 +1,323 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv1/hal_serial_lld.h + * @brief AT32 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SERIAL_USE_USART1) || defined(__DOXYGEN__) +#define AT32_SERIAL_USE_USART1 FALSE +#endif + +/** + * @brief USART2 driver enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SERIAL_USE_USART2) || defined(__DOXYGEN__) +#define AT32_SERIAL_USE_USART2 FALSE +#endif + +/** + * @brief USART3 driver enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SERIAL_USE_USART3) || defined(__DOXYGEN__) +#define AT32_SERIAL_USE_USART3 FALSE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define AT32_SERIAL_USE_UART4 FALSE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define AT32_SERIAL_USE_UART5 FALSE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(AT32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART1_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(AT32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART2_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(AT32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART3_PRIORITY 12 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(AT32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART4_PRIORITY 12 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(AT32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART5_PRIORITY 12 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if AT32_SERIAL_USE_USART1 && !AT32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if AT32_SERIAL_USE_USART2 && !AT32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if AT32_SERIAL_USE_USART3 && !AT32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if AT32_SERIAL_USE_UART4 && !AT32_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if AT32_SERIAL_USE_UART5 && !AT32_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if !AT32_SERIAL_USE_USART1 && !AT32_SERIAL_USE_USART2 && \ + !AT32_SERIAL_USE_USART3 && !AT32_SERIAL_USE_UART4 && \ + !AT32_SERIAL_USE_UART5 +#error "SERIAL driver activated but no USART/UART peripheral assigned" +#endif + +#if AT32_SERIAL_USE_USART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART1_PRIORITY) +#error "Invalid IRQ priority assigned to USART1" +#endif + +#if AT32_SERIAL_USE_USART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART2_PRIORITY) +#error "Invalid IRQ priority assigned to USART2" +#endif + +#if AT32_SERIAL_USE_USART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART3_PRIORITY) +#error "Invalid IRQ priority assigned to USART3" +#endif + +#if AT32_SERIAL_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if AT32_SERIAL_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +/* Checks on allocation of USARTx units.*/ +#if AT32_SERIAL_USE_USART1 +#if defined(AT32_USART1_IS_USED) +#error "SD1 requires USART1 but it is already used" +#else +#define AT32_USART1_IS_USED +#endif +#endif + +#if AT32_SERIAL_USE_USART2 +#if defined(AT32_USART2_IS_USED) +#error "SD2 requires USART2 but it is already used" +#else +#define AT32_USART2_IS_USED +#endif +#endif + +#if AT32_SERIAL_USE_USART3 +#if defined(AT32_USART3_IS_USED) +#error "SD3 requires USART3 but it is already used" +#else +#define AT32_USART3_IS_USED +#endif +#endif + +#if AT32_SERIAL_USE_UART4 +#if defined(AT32_UART4_IS_USED) +#error "SD4 requires UART4 but it is already used" +#else +#define AT32_UART4_IS_USED +#endif +#endif + +#if AT32_SERIAL_USE_UART5 +#if defined(AT32_UART5_IS_USED) +#error "SD5 requires UART5 but it is already used" +#else +#define AT32_UART5_IS_USED +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief AT32 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct hal_serial_config { + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields.*/ + /** + * @brief Initialization value for the CTRL1 register. + */ + uint16_t ctrl1; + /** + * @brief Initialization value for the CTRL2 register. + */ + uint16_t ctrl2; + /** + * @brief Initialization value for the CTRL3 register. + */ + uint16_t ctrl3; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + USART_TypeDef *usart; \ + /* Clock frequency for the associated USART/UART.*/ \ + uint32_t clock; \ + /* Mask to be applied on received frames.*/ \ + uint8_t rxmask; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * Extra USARTs definitions here (missing from the AT header file). + */ +#define USART_CTRL2_STOPBN1_BITS (0 << 12) /**< @brief CTRL2 1 stop bit value.*/ +#define USART_CTRL2_STOPBN0P5_BITS (1 << 12) /**< @brief CTRL2 0.5 stop bit value.*/ +#define USART_CTRL2_STOPBN2_BITS (2 << 12) /**< @brief CTRL2 2 stop bit value.*/ +#define USART_CTRL2_STOPBN1P5_BITS (3 << 12) /**< @brief CTRL2 1.5 stop bit value.*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if AT32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if AT32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif +#if AT32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif +#if AT32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); + void sd_lld_serve_interrupt(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c new file mode 100644 index 0000000000..a64e692c25 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c @@ -0,0 +1,775 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv1/hal_uart_lld.c + * @brief AT32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define AT32_UART_CTRL2_CHECK_MASK \ + (USART_CTRL2_STOPBN_0 | USART_CTRL2_CLKEN | USART_CTRL2_CLKPOL | \ + USART_CTRL2_CLKPHA | USART_CTRL2_LBCP) + +#define AT32_UART_CTRL3_CHECK_MASK \ + (USART_CTRL3_CTSCFIEN | USART_CTRL3_CTSEN | USART_CTRL3_RTSEN | \ + USART_CTRL3_SCMEN | USART_CTRL3_SCNACKEN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 UART driver identifier.*/ +#if AT32_UART_USE_USART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief USART2 UART driver identifier.*/ +#if AT32_UART_USE_USART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief USART3 UART driver identifier.*/ +#if AT32_UART_USE_USART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/** @brief UART4 UART driver identifier.*/ +#if AT32_UART_USE_UART4 || defined(__DOXYGEN__) +UARTDriver UARTD4; +#endif + +/** @brief UART5 UART driver identifier.*/ +#if AT32_UART_USE_UART5 || defined(__DOXYGEN__) +UARTDriver UARTD5; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sts USART STS register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint16_t sts) { + uartflags_t status = 0; + + if (sts & USART_STS_ROERR) + status |= UART_OVERRUN_ERROR; + if (sts & USART_STS_PERR) + status |= UART_PARITY_ERROR; + if (sts & USART_STS_FERR) + status |= UART_FRAMING_ERROR; + if (sts & USART_STS_NERR) + status |= UART_NOISE_ERROR; + if (sts & USART_STS_BFF) + status |= UART_BREAK_DETECTED; + return status; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_enter_rx_idle_loop(UARTDriver *uartp) { + uint32_t mode; + + /* RX DMA channel preparation, if the char callback is defined then the + FDTIEN interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + mode = AT32_DMA_CCTRL_DTD_P2M | AT32_DMA_CCTRL_LM; + else + mode = AT32_DMA_CCTRL_DTD_P2M | AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_FDTIEN; + dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, 1); + dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | mode); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_stop(UARTDriver *uartp) { + + /* Stops RX and TX DMA channels.*/ + dmaStreamDisable(uartp->dmarx); + dmaStreamDisable(uartp->dmatx); + + /* Stops USART operations.*/ + uartp->usart->CTRL1 = 0; + uartp->usart->CTRL2 = 0; + uartp->usart->CTRL3 = 0; +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_start(UARTDriver *uartp) { + uint32_t baudr; + uint16_t ctrl1; + USART_TypeDef *u = uartp->usart; + + /* Defensive programming, starting from a clean state.*/ + usart_stop(uartp); + + /* Baud rate setting.*/ + baudr = (uint32_t)((uartp->clock + uartp->config->speed/2) / uartp->config->speed); + + /* Correcting USARTDIV when oversampling by 8 instead of 16. + Fraction is still 4 bits wide, but only lower 3 bits used. + Mantissa is doubled, but Fraction is left the same.*/ +#if defined(USART_CTRL1_OVER8) + if (uartp->config->ctrl1 & USART_CTRL1_OVER8) + baudr = ((baudr & ~7) * 2) | (baudr & 7); +#endif + u->BAUDR = baudr; + + /* Resetting eventual pending status flags.*/ + (void)u->STS; /* STS reset step 1.*/ + (void)u->DT; /* STS reset step 2.*/ + u->STS = 0; + + /* Note that some bits are enforced because required for correct driver + operations.*/ + u->CTRL2 = uartp->config->ctrl2 | USART_CTRL2_BFIEN; + u->CTRL3 = uartp->config->ctrl3 | USART_CTRL3_DMATEN | USART_CTRL3_DMAREN | + USART_CTRL3_ERRIEN; + + /* Mustn't ever set FDTIEN here - if done, it causes an immediate + interrupt.*/ + ctrl1 = USART_CTRL1_UEN | USART_CTRL1_PERRIEN | USART_CTRL1_TEN | USART_CTRL1_REN; + u->CTRL1 = uartp->config->ctrl1 | ctrl1; + + /* Starting the receiver idle loop.*/ + uart_enter_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(AT32_UART_DMA_ERROR_HOOK) + if ((flags & AT32_DMA_STS_DTERRF) != 0) { + AT32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + _uart_rx_idle_code(uartp); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + dmaStreamDisable(uartp->dmarx); + _uart_rx_complete_isr_code(uartp); + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(AT32_UART_DMA_ERROR_HOOK) + if ((flags & AT32_DMA_STS_DTERRF) != 0) { + AT32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(uartp->dmatx); + + /* A callback is generated, if enabled, after a completed transfer.*/ + _uart_tx1_isr_code(uartp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if AT32_UART_USE_USART1 || defined(__DOXYGEN__) +#if !defined(AT32_USART1_SUPPRESS_ISR) +#if !defined(AT32_USART1_HANDLER) +#error "AT32_USART1_HANDLER not defined" +#endif +/** + * @brief USART1 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + uart_lld_serve_interrupt(&UARTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* AT32_UART_USE_USART1 */ + +#if AT32_UART_USE_USART2 || defined(__DOXYGEN__) +#if !defined(AT32_USART2_SUPPRESS_ISR) +#if !defined(AT32_USART2_HANDLER) +#error "AT32_USART2_HANDLER not defined" +#endif +/** + * @brief USART2 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + uart_lld_serve_interrupt(&UARTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* AT32_UART_USE_USART2 */ + +#if AT32_UART_USE_USART3 || defined(__DOXYGEN__) +#if !defined(AT32_USART3_SUPPRESS_ISR) +#if !defined(AT32_USART3_HANDLER) +#error "AT32_USART3_HANDLER not defined" +#endif +/** + * @brief USART3 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_USART3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + uart_lld_serve_interrupt(&UARTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* AT32_UART_USE_USART3 */ + +#if AT32_UART_USE_UART4 || defined(__DOXYGEN__) +#if !defined(AT32_UART4_SUPPRESS_ISR) +#if !defined(AT32_UART4_HANDLER) +#error "AT32_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_UART4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + uart_lld_serve_interrupt(&UARTD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* AT32_UART_USE_UART4 */ + +#if AT32_UART_USE_UART5 || defined(__DOXYGEN__) +#if !defined(AT32_UART5_SUPPRESS_ISR) +#if !defined(AT32_UART5_HANDLER) +#error "AT32_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_UART5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + uart_lld_serve_interrupt(&UARTD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* AT32_UART_USE_UART5 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if AT32_UART_USE_USART1 + uartObjectInit(&UARTD1); + UARTD1.usart = USART1; + UARTD1.clock = AT32_PCLK2; + UARTD1.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD1.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD1.dmarx = NULL; + UARTD1.dmatx = NULL; +#endif + +#if AT32_UART_USE_USART2 + uartObjectInit(&UARTD2); + UARTD2.usart = USART2; + UARTD2.clock = AT32_PCLK1; + UARTD2.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD2.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD2.dmarx = NULL; + UARTD2.dmatx = NULL; +#endif + +#if AT32_UART_USE_USART3 + uartObjectInit(&UARTD3); + UARTD3.usart = USART3; + UARTD3.clock = AT32_PCLK1; + UARTD3.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD3.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD3.dmarx = NULL; + UARTD3.dmatx = NULL; +#endif + +#if AT32_UART_USE_UART4 + uartObjectInit(&UARTD4); + UARTD4.usart = UART4; + UARTD4.clock = AT32_PCLK1; + UARTD4.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD4.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD4.dmarx = NULL; + UARTD4.dmatx = NULL; +#endif + +#if AT32_UART_USE_UART5 + uartObjectInit(&UARTD5); + UARTD5.usart = UART5; + UARTD5.clock = AT32_PCLK1; + UARTD5.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD5.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; + UARTD5.dmarx = NULL; + UARTD5.dmatx = NULL; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if AT32_UART_USE_USART1 + if (&UARTD1 == uartp) { + uartp->dmarx = dmaStreamAllocI(AT32_UART_USART1_RX_DMA_STREAM, + AT32_UART_USART1_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream"); + uartp->dmatx = dmaStreamAllocI(AT32_UART_USART1_TX_DMA_STREAM, + AT32_UART_USART1_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(uartp->dmarx, AT32_UART_USART1_RX_DMAMUX_CHANNEL, AT32_DMAMUX_USART1_RX); + dmaSetRequestSource(uartp->dmatx, AT32_UART_USART1_TX_DMAMUX_CHANNEL, AT32_DMAMUX_USART1_TX); +#endif + + crmEnableUSART1(true); + nvicEnableVector(AT32_USART1_NUMBER, AT32_UART_USART1_IRQ_PRIORITY); + + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); + } +#endif + +#if AT32_UART_USE_USART2 + if (&UARTD2 == uartp) { + uartp->dmarx = dmaStreamAllocI(AT32_UART_USART2_RX_DMA_STREAM, + AT32_UART_USART2_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream"); + uartp->dmatx = dmaStreamAllocI(AT32_UART_USART2_TX_DMA_STREAM, + AT32_UART_USART2_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(uartp->dmarx, AT32_UART_USART2_RX_DMAMUX_CHANNEL, AT32_DMAMUX_USART2_RX); + dmaSetRequestSource(uartp->dmatx, AT32_UART_USART2_TX_DMAMUX_CHANNEL, AT32_DMAMUX_USART2_TX); +#endif + + crmEnableUSART2(true); + nvicEnableVector(AT32_USART2_NUMBER, AT32_UART_USART2_IRQ_PRIORITY); + + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); + } +#endif + +#if AT32_UART_USE_USART3 + if (&UARTD3 == uartp) { + uartp->dmarx = dmaStreamAllocI(AT32_UART_USART3_RX_DMA_STREAM, + AT32_UART_USART3_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream"); + uartp->dmatx = dmaStreamAllocI(AT32_UART_USART3_TX_DMA_STREAM, + AT32_UART_USART3_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(uartp->dmarx, AT32_UART_USART3_RX_DMAMUX_CHANNEL, AT32_DMAMUX_USART3_RX); + dmaSetRequestSource(uartp->dmatx, AT32_UART_USART3_TX_DMAMUX_CHANNEL, AT32_DMAMUX_USART3_TX); +#endif + + crmEnableUSART3(true); + nvicEnableVector(AT32_USART3_NUMBER, AT32_UART_USART3_IRQ_PRIORITY); + + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); + } +#endif + +#if AT32_UART_USE_UART4 + if (&UARTD4 == uartp) { + + osalDbgAssert((uartp->config->ctrl2 & AT32_UART_CTRL2_CHECK_MASK) == 0, + "specified invalid bits in UART4 CTRL2 register settings"); + osalDbgAssert((uartp->config->ctrl3 & AT32_UART_CTRL3_CHECK_MASK) == 0, + "specified invalid bits in UART4 CTRL3 register settings"); + + uartp->dmarx = dmaStreamAllocI(AT32_UART_UART4_RX_DMA_STREAM, + AT32_UART_UART4_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream"); + uartp->dmatx = dmaStreamAllocI(AT32_UART_UART4_TX_DMA_STREAM, + AT32_UART_UART4_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(uartp->dmarx, AT32_UART_UART4_RX_DMAMUX_CHANNEL, AT32_DMAMUX_UART4_RX); + dmaSetRequestSource(uartp->dmatx, AT32_UART_UART4_TX_DMAMUX_CHANNEL, AT32_DMAMUX_UART4_TX); +#endif + + crmEnableUART4(true); + nvicEnableVector(AT32_UART4_NUMBER, AT32_UART_UART4_IRQ_PRIORITY); + + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); + } +#endif + +#if AT32_UART_USE_UART5 + if (&UARTD5 == uartp) { + + osalDbgAssert((uartp->config->ctrl2 & AT32_UART_CTRL2_CHECK_MASK) == 0, + "specified invalid bits in UART5 CTRL2 register settings"); + osalDbgAssert((uartp->config->ctrl3 & AT32_UART_CTRL3_CHECK_MASK) == 0, + "specified invalid bits in UART5 CTRL3 register settings"); + + uartp->dmarx = dmaStreamAllocI(AT32_UART_UART5_RX_DMA_STREAM, + AT32_UART_UART5_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream"); + uartp->dmatx = dmaStreamAllocI(AT32_UART_UART5_TX_DMA_STREAM, + AT32_UART_UART5_IRQ_PRIORITY, + (at32_dmasts_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(uartp->dmarx, AT32_UART_UART5_RX_DMAMUX_CHANNEL, AT32_DMAMUX_UART5_RX); + dmaSetRequestSource(uartp->dmatx, AT32_UART_UART5_TX_DMAMUX_CHANNEL, AT32_DMAMUX_UART5_TX); +#endif + + crmEnableUART5(true); + nvicEnableVector(AT32_UART5_NUMBER, AT32_UART_UART5_IRQ_PRIORITY); + + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); + } +#endif + + /* Static DMA setup, the transfer size depends on the USART settings, + it is 16 bits if M=1 and PEN=0 else it is 8 bits.*/ + if ((uartp->config->ctrl1 & (USART_CTRL1_DBN | USART_CTRL1_PEN)) == USART_CTRL1_DBN) { + uartp->dmarxmode |= AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; + uartp->dmatxmode |= AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; + } + dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DT); + dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DT); + uartp->rxbuf = 0; + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + usart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + usart_stop(uartp); + dmaStreamFreeI(uartp->dmarx); + dmaStreamFreeI(uartp->dmatx); + uartp->dmarx = NULL; + uartp->dmatx = NULL; + +#if AT32_UART_USE_USART1 + if (&UARTD1 == uartp) { + nvicDisableVector(AT32_USART1_NUMBER); + crmDisableUSART1(); + return; + } +#endif + +#if AT32_UART_USE_USART2 + if (&UARTD2 == uartp) { + nvicDisableVector(AT32_USART2_NUMBER); + crmDisableUSART2(); + return; + } +#endif + +#if AT32_UART_USE_USART3 + if (&UARTD3 == uartp) { + nvicDisableVector(AT32_USART3_NUMBER); + crmDisableUSART3(); + return; + } +#endif + +#if AT32_UART_USE_UART4 + if (&UARTD4 == uartp) { + nvicDisableVector(AT32_UART4_NUMBER); + crmDisableUART4(); + return; + } +#endif + +#if AT32_UART_USE_UART5 + if (&UARTD5 == uartp) { + nvicDisableVector(AT32_UART5_NUMBER); + crmDisableUART5(); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + /* TX DMA channel preparation.*/ + dmaStreamSetMemory0(uartp->dmatx, txbuf); + dmaStreamSetTransactionSize(uartp->dmatx, n); + dmaStreamSetMode(uartp->dmatx, uartp->dmatxmode | AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_FDTIEN); + + /* Only enable TDC interrupt if there's a callback attached to it or + if called from uartSendFullTimeout(). Also we need to clear TDC flag + which could be set before.*/ +#if UART_USE_WAIT == TRUE + if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) { +#else + if (uartp->config->txend2_cb != NULL) { +#endif + uartp->usart->STS = ~USART_STS_TDC; + uartp->usart->CTRL1 |= USART_CTRL1_TDCIEN; + } + + /* Starting transfer.*/ + dmaStreamEnable(uartp->dmatx); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + dmaStreamDisable(uartp->dmatx); + + return dmaStreamGetTransactionSize(uartp->dmatx); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + /* Stopping previous activity (idle state).*/ + dmaStreamDisable(uartp->dmarx); + + /* RX DMA channel preparation.*/ + dmaStreamSetMemory0(uartp->dmarx, rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, n); + dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_FDTIEN); + + /* Starting transfer.*/ + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + size_t n; + + dmaStreamDisable(uartp->dmarx); + n = dmaStreamGetTransactionSize(uartp->dmarx); + uart_enter_rx_idle_loop(uartp); + + return n; +} + +/** + * @brief USART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +void uart_lld_serve_interrupt(UARTDriver *uartp) { + uint16_t sts; + USART_TypeDef *u = uartp->usart; + uint32_t ctrl1 = u->CTRL1; + + sts = u->STS; /* STS reset step 1.*/ + + if (sts & (USART_STS_BFF | USART_STS_ROERR | USART_STS_NERR | + USART_STS_FERR | USART_STS_PERR)) { + + (void)u->DT; /* STS reset step 2 - clear ROERR.*/ + + u->STS = ~USART_STS_BFF; + _uart_rx_error_isr_code(uartp, translate_errors(sts)); + } + + if ((sts & USART_STS_TDC) && (ctrl1 & USART_CTRL1_TDCIEN)) { + /* TDC interrupt cleared and disabled.*/ + u->STS = ~USART_STS_TDC; + u->CTRL1 = ctrl1 & ~USART_CTRL1_TDCIEN; + + /* End of transmission, a callback is generated.*/ + _uart_tx2_isr_code(uartp); + } + + /* Timeout interrupt sources are only checked if enabled in CTRL1.*/ + if ((ctrl1 & USART_CTRL1_IDLEIEN) && (sts & USART_STS_IDLEF)) { + _uart_timeout_isr_code(uartp); + } +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h new file mode 100644 index 0000000000..e47ae7c1c5 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h @@ -0,0 +1,521 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv1/hal_uart_lld.h + * @brief AT32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on USART1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_UART_USE_USART1) || defined(__DOXYGEN__) +#define AT32_UART_USE_USART1 FALSE +#endif + +/** + * @brief UART driver on USART2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_UART_USE_USART2) || defined(__DOXYGEN__) +#define AT32_UART_USE_USART2 FALSE +#endif + +/** + * @brief UART driver on USART3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_UART_USE_USART3) || defined(__DOXYGEN__) +#define AT32_UART_USE_USART3 FALSE +#endif + +/** + * @brief UART driver on UART4 enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_UART_USE_UART4) || defined(__DOXYGEN__) +#define AT32_UART_USE_UART4 FALSE +#endif + +/** + * @brief UART driver on UART5 enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_UART_USE_UART5) || defined(__DOXYGEN__) +#define AT32_UART_USE_UART5 FALSE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(AT32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_USART1_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(AT32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_USART2_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(AT32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_USART3_IRQ_PRIORITY 12 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(AT32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_UART4_IRQ_PRIORITY 12 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(AT32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_UART5_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(AT32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_USART1_DMA_PRIORITY 0 +#endif + +/** + * @brief USART2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(AT32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_USART2_DMA_PRIORITY 0 +#endif + +/** + * @brief USART3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(AT32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_USART3_DMA_PRIORITY 0 +#endif + +/** + * @brief UART4 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(AT32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_UART4_DMA_PRIORITY 0 +#endif + +/** + * @brief UART5 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(AT32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_UART_UART5_DMA_PRIORITY 0 +#endif + +/** + * @brief USART DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(AT32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if AT32_UART_USE_USART1 && !AT32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if AT32_UART_USE_USART2 && !AT32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if AT32_UART_USE_USART3 && !AT32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if AT32_UART_USE_UART4 +#if !AT32_HAS_UART4 +#error "UART4 not present in the selected device" +#endif +#endif /* AT32_UART_USE_UART4 */ + +#if AT32_UART_USE_UART5 +#if !AT32_HAS_UART5 +#error "UART5 not present in the selected device" +#endif +#endif /* AT32_UART_USE_UART5 */ + +#if !AT32_UART_USE_USART1 && !AT32_UART_USE_USART2 && \ + !AT32_UART_USE_USART3 && !AT32_UART_USE_UART4 && \ + !AT32_UART_USE_UART5 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if AT32_UART_USE_USART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART1" +#endif + +#if AT32_UART_USE_USART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART2" +#endif + +#if AT32_UART_USE_USART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to USART3" +#endif + +#if AT32_UART_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_UART4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if AT32_UART_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_UART5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if AT32_UART_USE_USART1 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_UART_USART1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART1" +#endif + +#if AT32_UART_USE_USART2 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_UART_USART2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART2" +#endif + +#if AT32_UART_USE_USART3 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_UART_USART3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to USART3" +#endif + +#if AT32_UART_USE_UART4 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_UART_UART4_DMA_PRIORITY) +#error "Invalid DMA priority assigned to UART4" +#endif + +#if AT32_UART_USE_UART5 && \ + !AT32_DMA_IS_VALID_PRIORITY(AT32_UART_UART5_DMA_PRIORITY) +#error "Invalid DMA priority assigned to UART5" +#endif + +#if !defined(AT32_DMA_REQUIRED) +#define AT32_DMA_REQUIRED +#endif + +/* Checks on allocation of USARTx units.*/ +#if AT32_UART_USE_USART1 +#if defined(AT32_USART1_IS_USED) +#error "UARTD1 requires USART1 but it is already used" +#else +#define AT32_USART1_IS_USED +#endif +#endif + +#if AT32_UART_USE_USART2 +#if defined(AT32_USART2_IS_USED) +#error "UARTD2 requires USART2 but it is already used" +#else +#define AT32_USART2_IS_USED +#endif +#endif + +#if AT32_UART_USE_USART3 +#if defined(AT32_USART3_IS_USED) +#error "UARTD3 requires USART3 but it is already used" +#else +#define AT32_USART3_IS_USED +#endif +#endif + +#if AT32_UART_USE_UART4 +#if defined(AT32_UART4_IS_USED) +#error "UARTD4 requires UART4 but it is already used" +#else +#define AT32_UART4_IS_USED +#endif +#endif + +#if AT32_UART_USE_UART5 +#if defined(AT32_UART5_IS_USED) +#error "UARTD5 requires UART5 but it is already used" +#else +#define AT32_UART5_IS_USED +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Type of an UART driver. + */ +typedef struct hal_uart_driver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Type of an UART configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct hal_uart_config { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Receiver timeout callback. + * @details Handles idle interrupts depending on configured + * flags in CR registers and supported hardware features. + */ + uartcb_t timeout_cb; + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Initialization value for the CTRL1 register. + */ + uint16_t ctrl1; + /** + * @brief Initialization value for the CTRL2 register. + */ + uint16_t ctrl2; + /** + * @brief Initialization value for the CTRL3 register. + */ + uint16_t ctrl3; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct hal_uart_driver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the USART registers block. + */ + USART_TypeDef *usart; + /** + * @brief Clock frequency for the associated USART/UART. + */ + uint32_t clock; + /** + * @brief Receive DMA mode bit mask. + */ + uint32_t dmarxmode; + /** + * @brief Send DMA mode bit mask. + */ + uint32_t dmatxmode; + /** + * @brief Receive DMA channel. + */ + const at32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const at32_dma_stream_t *dmatx; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_UART_USE_USART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if AT32_UART_USE_USART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if AT32_UART_USE_USART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#if AT32_UART_USE_UART4 && !defined(__DOXYGEN__) +extern UARTDriver UARTD4; +#endif + +#if AT32_UART_USE_UART5 && !defined(__DOXYGEN__) +extern UARTDriver UARTD5; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); + void uart_lld_serve_interrupt(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/xWDGv1/driver.mk b/os/hal/ports/AT32/LLD/xWDGv1/driver.mk new file mode 100644 index 0000000000..2f6fe0f64f --- /dev/null +++ b/os/hal/ports/AT32/LLD/xWDGv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/xWDGv1 diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c new file mode 100644 index 0000000000..79181e464d --- /dev/null +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c @@ -0,0 +1,132 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file xWDGv1/hal_wdg_lld.c + * @brief WDG Driver subsystem low level driver source. + * + * @addtogroup WDG + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define CMD_CMD_RELOAD 0xAAAAU +#define CMD_CMD_ENABLE 0xCCCCU +#define CMD_CMD_WRITE 0x5555U +#define CMD_CMD_PROTECT 0x0000U + +#if !defined(WDG) && defined(WDG1) +#define WDG WDG1 +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if AT32_WDG_USE_WDT || defined(__DOXYGEN__) +WDGDriver WDGD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level WDG driver initialization. + * + * @notapi + */ +void wdg_lld_init(void) { + +#if AT32_WDG_USE_WDT + WDGD1.state = WDG_STOP; + WDGD1.wdg = WDT; +#endif +} + +/** + * @brief Configures and activates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_start(WDGDriver *wdgp) { + + /* Enable WDG and unlock for write.*/ + wdgp->wdg->CMD = CMD_CMD_ENABLE; + wdgp->wdg->CMD = CMD_CMD_WRITE; + + /* Write configuration.*/ + wdgp->wdg->DIV = wdgp->config->div; + wdgp->wdg->RLD = wdgp->config->rld; + + /* Wait the registers to be updated.*/ + while (wdgp->wdg->STS != 0) + ; + + wdgp->wdg->CMD = CMD_CMD_RELOAD; +} + +/** + * @brief Deactivates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_stop(WDGDriver *wdgp) { + + osalDbgAssert(wdgp->state == WDG_STOP, + "WDG cannot be stopped once activated"); +} + +/** + * @brief Reloads WDG's counter. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_reset(WDGDriver * wdgp) { + + wdgp->wdg->CMD = CMD_CMD_RELOAD; +} + +#endif /* HAL_USE_WDG == TRUE */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h new file mode 100644 index 0000000000..ffd40da695 --- /dev/null +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h @@ -0,0 +1,168 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file xWDGv1/hal_wdg_lld.h + * @brief WDG Driver subsystem low level driver header. + * + * @addtogroup WDG + * @{ + */ + +#ifndef HAL_WDG_LLD_H +#define HAL_WDG_LLD_H + +#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name RLD register definitions + * @{ + */ +#define AT32_WDT_RLD_MASK (0x00000FFF << 0) +#define AT32_WDT_RLD(n) ((n) << 0) +/** @} */ + +/** + * @name DIV register definitions + * @{ + */ +#define AT32_WDT_DIV_MASK (7 << 0) +#define AT32_WDT_DIV_4 0U +#define AT32_WDT_DIV_8 1U +#define AT32_WDT_DIV_16 2U +#define AT32_WDT_DIV_32 3U +#define AT32_WDT_DIV_64 4U +#define AT32_WDT_DIV_128 5U +#define AT32_WDT_DIV_256 6U +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief WDG driver enable switch. + * @details If set to @p TRUE the support for WDG is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_WDG_USE_WDT) || defined(__DOXYGEN__) +#define AT32_WDG_USE_WDT FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if AT32_WDG_USE_WDT && !AT32_HAS_WDT +#error "WDG not present in the selected device" +#endif + +#if !AT32_WDG_USE_WDT +#error "WDG driver activated but no xWDG peripheral assigned" +#endif + +#if !defined(AT32_LICK_ENABLED) +#error "AT32_LICK_ENABLED not defined" +#endif + +#if (AT32_WDG_USE_WDT == TRUE) && (AT32_LICK_ENABLED == FALSE) +#error "WDG requires LICK clock" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an WDG driver. + */ +typedef struct WDGDriver WDGDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Configuration of the WDT_DIV register. + * @details See the AT32 reference manual for details. + */ + uint32_t div; + /** + * @brief Configuration of the WDT_RLD register. + * @details See the AT32 reference manual for details. + */ + uint32_t rld; +} WDGConfig; + +/** + * @brief Structure representing an WDG driver. + */ +struct WDGDriver { + /** + * @brief Driver state. + */ + wdgstate_t state; + /** + * @brief Current configuration data. + */ + const WDGConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the WDG registers block. + */ + WDT_TypeDef *wdg; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if AT32_WDG_USE_WDT && !defined(__DOXYGEN__) +extern WDGDriver WDGD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void wdg_lld_init(void); + void wdg_lld_start(WDGDriver *wdgp); + void wdg_lld_stop(WDGDriver *wdgp); + void wdg_lld_reset(WDGDriver *wdgp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_WDG == TRUE */ + +#endif /* HAL_WDG_LLD_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/.cproject b/testhal/AT32/AT32F415/PWM-ICU/.cproject new file mode 100644 index 0000000000..6caf490fe7 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/.cproject @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/AT32F415/PWM-ICU/.project b/testhal/AT32/AT32F415/PWM-ICU/.project new file mode 100644 index 0000000000..a94f918b02 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/.project @@ -0,0 +1,33 @@ + + + AT32F415-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/AT32/AT32F415/PWM-ICU/Makefile b/testhal/AT32/AT32F415/PWM-ICU/Makefile new file mode 100644 index 0000000000..a00e20a67f --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/Makefile @@ -0,0 +1,236 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h b/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h new file mode 100644 index 0000000000..6ae2a5be1b --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h @@ -0,0 +1,819 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h b/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h new file mode 100644 index 0000000000..099dca49da --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h b/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h new file mode 100644 index 0000000000..a8222ec634 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h @@ -0,0 +1,222 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define AT32F415_MCUCONF + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define AT32_NO_INIT FALSE +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 TRUE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 TRUE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/main.c b/testhal/AT32/AT32F415/PWM-ICU/main.c new file mode 100644 index 0000000000..4f22f79cec --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/main.c @@ -0,0 +1,145 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(IOPORT3, GPIOC_LED_GREEN); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(IOPORT3, GPIOC_LED_GREEN); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, + 0, + 0 +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + last_width = icuGetWidthX(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + last_period = icuGetPeriodX(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1, + 0U, + 0xFFFFFFFFU +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * LED initially off. + */ + palSetPad(IOPORT3, GPIOC_LED_GREEN); + + /* + * Initializes the PWM driver 1 and ICU driver 4. + */ + pwmStart(&PWMD1, &pwmcfg); + pwmEnablePeriodicNotification(&PWMD1); + palSetPadMode(IOPORT1, 8, PAL_MODE_AT32_ALTERNATE_PUSHPULL); + icuStart(&ICUD4, &icucfg); + icuStartCapture(&ICUD4); + icuEnableNotifications(&ICUD4); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); + pwmEnableChannelNotification(&PWMD1, 0); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD1, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD1, 0); + pwmStop(&PWMD1); + icuStopCapture(&ICUD4); + icuStop(&ICUD4); + palSetPad(IOPORT3, GPIOC_LED_GREEN); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/AT32/AT32F415/PWM-ICU/readme.txt b/testhal/AT32/AT32F415/PWM-ICU/readme.txt new file mode 100644 index 0000000000..831073bf7d --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/HAL - PWM/ICU driver demo for AT32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an AT-START-F415 board. + +** The Demo ** + +The application demonstrates the use of the AT32 PWM and ICU drivers. Pins +PA8 and PB6 must be connected in order to trigger the ICU input with the +PWM output. The ICU unit will measure the generated PWM. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Artery Technology and are licensed under a different license. +Also note that not all the files present in the AT library are distributed +with ChibiOS/RT, you can find the whole library on the AT web site: + + https://www.arterychip.com/en diff --git a/testhal/AT32/AT32F415/USB_CDC/.cproject b/testhal/AT32/AT32F415/USB_CDC/.cproject new file mode 100644 index 0000000000..7e9524dabe --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/AT32F415/USB_CDC/.project b/testhal/AT32/AT32F415/USB_CDC/.project new file mode 100644 index 0000000000..d38abd8218 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/.project @@ -0,0 +1,49 @@ + + + AT32F415-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS_CONTRIB/os/hal/boards/AT_START_F415 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + + + CHIBIOS_CONTRIB + file:/E:/Duc/Secrets/QMK_custom_mcu/at32_test_qmk/lib/chibios-contrib + + + diff --git a/testhal/AT32/AT32F415/USB_CDC/Makefile b/testhal/AT32/AT32F415/USB_CDC/Makefile new file mode 100644 index 0000000000..cd0e85a6dd --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/Makefile @@ -0,0 +1,238 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + usbcfg.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h b/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h new file mode 100644 index 0000000000..6ae2a5be1b --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h @@ -0,0 +1,819 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h b/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h new file mode 100644 index 0000000000..54dcee0877 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h b/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h new file mode 100644 index 0000000000..cdc11f27bf --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h @@ -0,0 +1,222 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define AT32F415_MCUCONF + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define AT32_NO_INIT FALSE +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/AT32F415/USB_CDC/main.c b/testhal/AT32/AT32F415/USB_CDC/main.c new file mode 100644 index 0000000000..6bf5791d5a --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/main.c @@ -0,0 +1,160 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" + +#include "usbcfg.h" + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/ +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { +#if 1 + /* Writing in channel mode.*/ + chnWrite(&SDU1, buf, sizeof buf - 1); +#else + /* Writing in buffer mode.*/ + (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE); + memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE); + obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE); +#endif + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(IOPORT3, GPIOC_LED_GREEN); + chThdSleepMilliseconds(time); + palSetPad(IOPORT3, GPIOC_LED_GREEN); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1000); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + if (SDU1.config->usbp->state == USB_ACTIVE) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/AT32/AT32F415/USB_CDC/readme.txt b/testhal/AT32/AT32F415/USB_CDC/readme.txt new file mode 100644 index 0000000000..a016a1945e --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/HAL - USB-CDC driver demo for AT32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an AT-START-F415 board. + +** The Demo ** + +The application demonstrates the use of the AT32 USB (OTG) driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Artery Technology and are licensed under a different license. +Also note that not all the files present in the AT library are distributed +with ChibiOS/RT, you can find the whole library on the AT web site: + + https://www.arterychip.com/en diff --git a/testhal/AT32/AT32F415/USB_CDC/usbcfg.c b/testhal/AT32/AT32F415/USB_CDC/usbcfg.c new file mode 100644 index 0000000000..b1afb386b4 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/usbcfg.c @@ -0,0 +1,344 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x2E3C, /* idVendor (AT). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'A', 0, 'r', 0, 't', 0, 'e', 0, 'r', 0, 'y', 0, ' ', 0, 'T', 0, + 'e', 0, 'c', 0, 'h', 0, 'n', 0, 'o', 0, 'l', 0, 'o', 0, 'g', 0, + 'y', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Connection event on wakeup.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/testhal/AT32/AT32F415/USB_CDC/usbcfg.h b/testhal/AT32/AT32F415/USB_CDC/usbcfg.h new file mode 100644 index 0000000000..036a822f31 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/usbcfg.h @@ -0,0 +1,28 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */