From 4ca2f6209a03adf60d4a7cf3f69bca06dc8b8187 Mon Sep 17 00:00:00 2001 From: Zonghao Li Date: Thu, 26 Oct 2023 23:34:27 -0400 Subject: [PATCH] add xschem schematics and simulation files --- xschem/analog_wrapper_tb.sch | 76 - xschem/analog_wrapper_tb.spice | 283 - xschem/current_test.spice | 86 - xschem/diff_pair.sch | 157 + xschem/diff_pair.sym | 30 + xschem/diff_pair_cascode.sch | 211 + xschem/diff_pair_cascode.sym | 29 + xschem/diff_pair_folded_cascode.sch | 278 + xschem/diff_pair_folded_cascode.sym | 33 + xschem/diff_pair_folded_cascode2.sch | 417 + xschem/diff_pair_tb.sch | 85 + xschem/example_por.sch | 297 - xschem/example_por.sym | 33 - xschem/example_por_tb.sch | 45 - xschem/example_por_tb.spice | 78 - xschem/example_por_tb.spice.orig | 88 - xschem/folded_cascode_tb.sch | 112 + xschem/ldo.sch | 94 + xschem/ldo.sym | 29 + xschem/ldo_cascode.sch | 88 + xschem/ldo_cascode.sym | 30 + xschem/ldo_cascode_tb.sch | 102 + xschem/ldo_folded_cascode.sch | 99 + xschem/ldo_folded_cascode.sym | 33 + xschem/ldo_folded_cascode_tb.sch | 377 + xschem/ldo_tb.sch | 596 + xschem/ldo_tb2.sch | 532 + xschem/ldo_tb_stb.sch | 223 + xschem/ldo_tb_stb_middlebrook.sch | 199 + xschem/{ => simulations}/.spiceinit | 0 xschem/simulations/diff_pair.spice | 25 + xschem/simulations/diff_pair_cascode.spice | 31 + .../diff_pair_folded_cascode.spice | 38 + xschem/simulations/diff_pair_tb.spice | 72 + xschem/simulations/diff_pair_tb_vars.spice | 17 + xschem/simulations/diff_pair_vars.spice | 8 + xschem/simulations/folded_cascode_tb.spice | 96 + xschem/simulations/ldo.spice | 44 + xschem/simulations/ldo_cascode.spice | 50 + xschem/simulations/ldo_cascode_tb.spice | 102 + xschem/simulations/ldo_cascode_tb_vars.spice | 16 + xschem/simulations/ldo_folded_cascode.spice | 58 + xschem/simulations/ldo_folded_cascode_tb.log | 3082 +++++ .../simulations/ldo_folded_cascode_tb.spice | 258 + xschem/simulations/ldo_folded_cascode_tb.vhdl | 828 ++ xschem/simulations/ldo_folded_cascode_tb_dc | 201 + .../ldo_folded_cascode_tb_line_reg_maxload | 10912 ++++++++++++++++ .../ldo_folded_cascode_tb_line_reg_minload | 10040 ++++++++++++++ .../ldo_folded_cascode_tb_load_reg | 10019 ++++++++++++++ .../ldo_folded_cascode_tb_loop_gain_maxload | 101 + .../ldo_folded_cascode_tb_loop_gain_minload | 101 + xschem/simulations/ldo_folded_cascode_tb_op | 1011 ++ .../ldo_folded_cascode_tb_psrr_maxload | 101 + .../ldo_folded_cascode_tb_psrr_minload | 101 + .../ldo_folded_cascode_tb_vars.spice | 20 + xschem/simulations/ldo_tb.spice | 524 + xschem/simulations/ldo_tb2.spice | 153 + xschem/simulations/ldo_tb_dc | 201 + xschem/simulations/ldo_tb_line_reg_maxload | 10033 ++++++++++++++ xschem/simulations/ldo_tb_line_reg_minload | 10033 ++++++++++++++ xschem/simulations/ldo_tb_load_reg | 10018 ++++++++++++++ xschem/simulations/ldo_tb_loop_gain | 101 + xschem/simulations/ldo_tb_loop_gain_maxload | 101 + xschem/simulations/ldo_tb_loop_gain_minload | 101 + xschem/simulations/ldo_tb_op | 551 + xschem/simulations/ldo_tb_psrr | 101 + xschem/simulations/ldo_tb_psrr_maxload | 101 + xschem/simulations/ldo_tb_psrr_minload | 101 + xschem/simulations/ldo_tb_stb.spice | 111 + .../simulations/ldo_tb_stb_middlebrook.spice | 167 + xschem/simulations/ldo_tb_vars.spice | 13 + xschem/simulations/test_gm_id.spice | 73 + xschem/simulations/test_mim_cap.raw | Bin 0 -> 34727 bytes xschem/simulations/test_mim_cap.spice | 29 + xschem/simulations/two_stage.spice | 33 + xschem/simulations/two_stage_tb.spice | 431 + xschem/simulations/two_stage_tb_op | 641 + xschem/simulations/two_stage_tb_vars.spice | 9 + xschem/simulations/two_stage_tb_vout_ac | 101 + xschem/simulations/two_stage_tb_vout_dc | 181 + xschem/test.data | 101 - xschem/test_gm_id.sch | 105 + xschem/threshold_test_tb.spice | 46 - xschem/two_stage.sch | 241 + xschem/two_stage.sym | 30 + xschem/two_stage_tb.sch | 413 + xschem/user_analog_project_wrapper.sch | 180 - xschem/user_analog_project_wrapper.spice | 202 - xschem/user_analog_project_wrapper.sym | 111 - xschem/xschemrc | 148 +- 90 files changed, 75897 insertions(+), 1660 deletions(-) delete mode 100644 xschem/analog_wrapper_tb.sch delete mode 100644 xschem/analog_wrapper_tb.spice delete mode 100644 xschem/current_test.spice create mode 100644 xschem/diff_pair.sch create mode 100644 xschem/diff_pair.sym create mode 100644 xschem/diff_pair_cascode.sch create mode 100644 xschem/diff_pair_cascode.sym create mode 100644 xschem/diff_pair_folded_cascode.sch create mode 100644 xschem/diff_pair_folded_cascode.sym create mode 100644 xschem/diff_pair_folded_cascode2.sch create mode 100644 xschem/diff_pair_tb.sch delete mode 100644 xschem/example_por.sch delete mode 100644 xschem/example_por.sym delete mode 100644 xschem/example_por_tb.sch delete mode 100644 xschem/example_por_tb.spice delete mode 100644 xschem/example_por_tb.spice.orig create mode 100644 xschem/folded_cascode_tb.sch create mode 100644 xschem/ldo.sch create mode 100644 xschem/ldo.sym create mode 100644 xschem/ldo_cascode.sch create mode 100644 xschem/ldo_cascode.sym create mode 100644 xschem/ldo_cascode_tb.sch create mode 100644 xschem/ldo_folded_cascode.sch create mode 100644 xschem/ldo_folded_cascode.sym create mode 100644 xschem/ldo_folded_cascode_tb.sch create mode 100644 xschem/ldo_tb.sch create mode 100644 xschem/ldo_tb2.sch create mode 100644 xschem/ldo_tb_stb.sch create mode 100644 xschem/ldo_tb_stb_middlebrook.sch rename xschem/{ => simulations}/.spiceinit (100%) create mode 100644 xschem/simulations/diff_pair.spice create mode 100644 xschem/simulations/diff_pair_cascode.spice create mode 100644 xschem/simulations/diff_pair_folded_cascode.spice create mode 100644 xschem/simulations/diff_pair_tb.spice create mode 100644 xschem/simulations/diff_pair_tb_vars.spice create mode 100644 xschem/simulations/diff_pair_vars.spice create mode 100644 xschem/simulations/folded_cascode_tb.spice create mode 100644 xschem/simulations/ldo.spice create mode 100644 xschem/simulations/ldo_cascode.spice create mode 100644 xschem/simulations/ldo_cascode_tb.spice create mode 100644 xschem/simulations/ldo_cascode_tb_vars.spice create mode 100644 xschem/simulations/ldo_folded_cascode.spice create mode 100644 xschem/simulations/ldo_folded_cascode_tb.log create mode 100644 xschem/simulations/ldo_folded_cascode_tb.spice create mode 100644 xschem/simulations/ldo_folded_cascode_tb.vhdl create mode 100644 xschem/simulations/ldo_folded_cascode_tb_dc create mode 100644 xschem/simulations/ldo_folded_cascode_tb_line_reg_maxload create mode 100644 xschem/simulations/ldo_folded_cascode_tb_line_reg_minload create mode 100644 xschem/simulations/ldo_folded_cascode_tb_load_reg create mode 100644 xschem/simulations/ldo_folded_cascode_tb_loop_gain_maxload create mode 100644 xschem/simulations/ldo_folded_cascode_tb_loop_gain_minload create mode 100644 xschem/simulations/ldo_folded_cascode_tb_op create mode 100644 xschem/simulations/ldo_folded_cascode_tb_psrr_maxload create mode 100644 xschem/simulations/ldo_folded_cascode_tb_psrr_minload create mode 100644 xschem/simulations/ldo_folded_cascode_tb_vars.spice create mode 100644 xschem/simulations/ldo_tb.spice create mode 100644 xschem/simulations/ldo_tb2.spice create mode 100644 xschem/simulations/ldo_tb_dc create mode 100644 xschem/simulations/ldo_tb_line_reg_maxload create mode 100644 xschem/simulations/ldo_tb_line_reg_minload create mode 100644 xschem/simulations/ldo_tb_load_reg create mode 100644 xschem/simulations/ldo_tb_loop_gain create mode 100644 xschem/simulations/ldo_tb_loop_gain_maxload create mode 100644 xschem/simulations/ldo_tb_loop_gain_minload create mode 100644 xschem/simulations/ldo_tb_op create mode 100644 xschem/simulations/ldo_tb_psrr create mode 100644 xschem/simulations/ldo_tb_psrr_maxload create mode 100644 xschem/simulations/ldo_tb_psrr_minload create mode 100644 xschem/simulations/ldo_tb_stb.spice create mode 100644 xschem/simulations/ldo_tb_stb_middlebrook.spice create mode 100644 xschem/simulations/ldo_tb_vars.spice create mode 100644 xschem/simulations/test_gm_id.spice create mode 100644 xschem/simulations/test_mim_cap.raw create mode 100644 xschem/simulations/test_mim_cap.spice create mode 100644 xschem/simulations/two_stage.spice create mode 100644 xschem/simulations/two_stage_tb.spice create mode 100644 xschem/simulations/two_stage_tb_op create mode 100644 xschem/simulations/two_stage_tb_vars.spice create mode 100644 xschem/simulations/two_stage_tb_vout_ac create mode 100644 xschem/simulations/two_stage_tb_vout_dc delete mode 100644 xschem/test.data create mode 100644 xschem/test_gm_id.sch delete mode 100644 xschem/threshold_test_tb.spice create mode 100644 xschem/two_stage.sch create mode 100644 xschem/two_stage.sym create mode 100644 xschem/two_stage_tb.sch delete mode 100644 xschem/user_analog_project_wrapper.sch delete mode 100644 xschem/user_analog_project_wrapper.spice delete mode 100644 xschem/user_analog_project_wrapper.sym diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch deleted file mode 100644 index d9b605c..0000000 --- a/xschem/analog_wrapper_tb.sch +++ /dev/null @@ -1,76 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -N 300 -290 510 -290 { lab=#net1} -N 590 -290 590 -250 { lab=#net1} -N 300 -250 430 -250 { lab=GND} -N 510 -250 510 -150 { lab=GND} -N 510 -150 780 -150 { lab=GND} -N 780 -190 780 -150 { lab=GND} -N 690 -190 690 -150 { lab=GND} -N 590 -190 590 -150 { lab=GND} -N 300 -210 400 -210 { lab=#net2} -N 480 -270 480 -210 { lab=#net2} -N 480 -270 690 -270 { lab=#net2} -N 690 -270 690 -250 { lab=#net2} -N 300 10 450 10 { lab=#net3} -N 850 -270 850 0 { lab=io_analog[4]} -N 780 -270 850 -270 { lab=io_analog[4]} -N 780 -270 780 -250 { lab=io_analog[4]} -N 300 30 470 30 { lab=#net4} -N 300 50 410 50 { lab=#net5} -N 530 10 660 10 { lab=io_analog[10:0]} -N 510 -290 590 -290 { lab=#net1} -N 430 -250 510 -250 { lab=GND} -N 400 -210 480 -210 { lab=#net2} -N 460 10 530 10 { lab=io_analog[10:0]} -N 670 0 850 -0 { lab=io_analog[4]} -N 300 -270 400 -270 { lab=#net8} -N 300 -230 400 -230 { lab=#net9} -N 300 -190 400 -190 { lab=#net10} -N 300 -190 400 -190 { lab=#net10} -N 300 -170 400 -170 { lab=#net11} -N 290 -150 390 -150 { lab=#net12} -N 290 -130 390 -130 { lab=#net13} -N 290 -110 390 -110 { lab=#net14} -N 300 -90 400 -90 { lab=#net15} -N 300 -10 400 -10 { lab=#net16} -N 300 70 400 70 { lab=#net17} -N -60 -290 -0 -290 { lab=#net18} -N -60 -270 0 -270 { lab=#net19} -N -60 -250 0 -250 { lab=#net20} -N -60 -230 0 -230 { lab=#net21} -N -60 -210 0 -210 { lab=#net22} -N -60 -210 0 -210 { lab=#net22} -N -60 -190 0 -190 { lab=#net23} -N -60 -190 0 -190 { lab=#net23} -N -60 -170 0 -170 { lab=#net24} -N -60 -150 0 -150 { lab=#net25} -N -60 -130 0 -130 { lab=#net26} -N -60 -110 0 -110 { lab=#net27} -N -60 -90 0 -90 { lab=#net28} -N -60 -70 0 -70 { lab=#net29} -N -60 -50 0 -50 { lab=#net30} -N 300 -70 400 -70 {} -N 300 -50 400 -50 {} -N 300 -30 400 -30 {} -C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1} -C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"} -C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"} -C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"} -C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]} -C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND} -C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]} -C {devices/code.sym} 920 -130 0 0 {name=TT_MODELS only_toplevel=false -format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt -.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"} -C {devices/code_shown.sym} 1100 -130 0 0 {name=s1 -only_toplevel=false -value=".control -tran 10u 20m -plot V(\\"io_out[11]\\") V(\\"io_out[12]\\") V(\\"io_out[15]\\") V(\\"io_out[16]\\") -+ V(\\"gpio_analog[3]\\") V(\\"gpio_analog[7]\\") -.endc"} diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice deleted file mode 100644 index 523a509..0000000 --- a/xschem/analog_wrapper_tb.spice +++ /dev/null @@ -1,283 +0,0 @@ -**.subckt analog_wrapper_tb -x1 net1 net6 GND net7 net2 net8 net9 net10 net16 net17 net18 net19 net20 net21[3] net21[2] net21[1] -+ net21[0] net22[31] net22[30] net22[29] net22[28] net22[27] net22[26] net22[25] net22[24] net22[23] net22[22] -+ net22[21] net22[20] net22[19] net22[18] net22[17] net22[16] net22[15] net22[14] net22[13] net22[12] net22[11] -+ net22[10] net22[9] net22[8] net22[7] net22[6] net22[5] net22[4] net22[3] net22[2] net22[1] net22[0] net23[31] -+ net23[30] net23[29] net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22] net23[21] net23[20] -+ net23[19] net23[18] net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11] net23[10] net23[9] -+ net23[8] net23[7] net23[6] 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net25[39] net25[38] -+ net25[37] net25[36] net25[35] net25[34] net25[33] net25[32] net25[31] net25[30] net25[29] net25[28] net25[27] -+ net25[26] net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16] -+ net25[15] net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5] -+ net25[4] net25[3] net25[2] net25[1] net25[0] net26[26] net26[25] net26[24] net26[23] net26[22] net26[21] -+ net26[20] net26[19] net26[18] net26[17] net26[16] net26[15] net26[14] net26[13] net26[12] net26[11] net26[10] -+ net26[9] net26[8] net26[7] net26[6] net26[5] net26[4] net26[3] net26[2] net26[1] net26[0] net27[26] -+ net27[25] net27[24] net27[23] net27[22] net27[21] net27[20] net27[19] net27[18] net27[17] net27[16] net27[15] -+ net27[14] net27[13] net27[12] net27[11] net27[10] net27[9] net27[8] net27[7] net27[6] net27[5] net27[4] -+ net27[3] net27[2] net27[1] net27[0] net29[26] net29[25] net29[24] net29[23] net29[22] net29[21] net29[20] -+ net29[19] net29[18] net29[17] net29[16] net29[15] net29[14] net29[13] net29[12] net29[11] net29[10] net29[9] -+ net29[8] net29[7] net29[6] net29[5] net29[4] net29[3] net29[2] net29[1] net29[0] net30[26] net30[25] -+ net30[24] net30[23] net30[22] net30[21] net30[20] net30[19] net30[18] net30[17] net30[16] net30[15] net30[14] -+ net30[13] net30[12] net30[11] net30[10] net30[9] net30[8] net30[7] net30[6] net30[5] net30[4] net30[3] -+ net30[2] net30[1] net30[0] net31[17] net31[16] net31[15] net31[14] net31[13] net31[12] net31[11] net31[10] -+ net31[9] net31[8] net31[7] net31[6] net31[5] net31[4] net31[3] net31[2] net31[1] net31[0] net14[17] -+ net14[16] net14[15] net14[14] net14[13] net14[12] net14[11] net14[10] net14[9] net14[8] net14[7] net14[6] -+ net14[5] net14[4] net14[3] net14[2] net14[1] net14[0] net3[10] net3[9] net3[8] net3[7] net3[6] net3[5] -+ net3[4] net3[3] net3[2] net3[1] net3[0] net4[2] net4[1] net4[0] net5[2] net5[1] net5[0] net28 net15[2] -+ net15[1] net15[0] user_analog_project_wrapper -V1 net1 GND PWL(0.0 0 400u 0 5.4m 3.3) -V2 net2 GND PWL(0.0 0 300u 0 5.3 1.8) -V3 io_analog[4] GND PWL(0.0 0 100u 0 5m 3.3) -**** begin user architecture code -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt -.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice - -.control -tran 10u 20m -plot V("io_out[11]") V("io_out[12]") V("io_out[15]") V("io_out[16]") V("gpio_analog[3]") -+ V("gpio_analog[7]") -.endc - -**** end user architecture code -**.ends - -* expanding symbol: user_analog_project_wrapper.sym # of pins=32 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sch -.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i -+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31] -+ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23] -+ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15] -+ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7] -+ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31] -+ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23] -+ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15] -+ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7] -+ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o -+ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24] -+ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16] -+ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8] -+ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0] -+ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121] -+ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114] -+ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107] -+ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100] -+ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93] -+ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86] -+ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79] -+ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72] -+ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65] -+ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58] -+ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51] -+ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44] -+ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37] -+ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30] -+ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23] -+ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16] -+ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9] -+ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1] -+ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123] -+ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117] -+ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111] -+ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105] -+ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98] -+ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91] -+ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84] -+ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77] -+ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70] -+ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63] -+ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56] -+ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49] -+ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42] -+ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35] -+ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28] -+ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21] -+ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14] -+ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7] -+ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] -+ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] -+ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] -+ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] -+ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] -+ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] -+ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] -+ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] -+ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] -+ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] -+ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] -+ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] -+ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] -+ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] -+ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] -+ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22] -+ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11] -+ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0] -+ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] -+ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] -+ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] -+ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21] -+ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11] -+ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] -+ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] -+ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] -+ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] -+ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] -+ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] -+ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] -+ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] -+ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] -+ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] -+ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2 -+ user_irq[2] user_irq[1] user_irq[0] -*.iopin vdda1 -*.iopin vdda2 -*.iopin vssa1 -*.iopin vssa2 -*.iopin vccd1 -*.iopin vccd2 -*.iopin vssd1 -*.iopin vssd2 -*.ipin wb_clk_i -*.ipin wb_rst_i -*.ipin wbs_stb_i -*.ipin wbs_cyc_i -*.ipin wbs_we_i -*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0] -*.ipin -*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0] -*.ipin -*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] -*.opin wbs_ack_o -*.opin -*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0] -*.ipin -*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0] -*.opin -*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0] -*.ipin -*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0] -*.ipin -*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] -*.ipin user_clock2 -*.opin -*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0] -*.opin -*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0] -*.iopin -*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0] -*.iopin -*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0] -*.iopin -*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] -*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] -*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0] -*.opin user_irq[2],user_irq[1],user_irq[0] -*.ipin -*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0] -x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por -x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por -R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R8 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=0.56 L=0.49 m=1 -R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=0.56 L=0.31 m=1 -R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=0.56 L=0.58 m=1 -R12 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=0.56 L=0.6 m=1 -.ends - - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1 -XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1 -XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2 -x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -.GLOBAL GND -** flattened .save nodes -.end diff --git a/xschem/current_test.spice b/xschem/current_test.spice deleted file mode 100644 index 8e4162d..0000000 --- a/xschem/current_test.spice +++ /dev/null @@ -1,86 +0,0 @@ -*--------------------------------------------------------------------------- -* SPDX-FileCopyrightText: 2020 Efabless Corporation -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* https://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -* SPDX-License-Identifier: Apache-2.0 -*--------------------------------------------------------------------------- -* Simple POR circuit for Caravel current mirror test -*------------------------------------------------------------------- - -.param mc_mm_switch=0 -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt - -* Note: 20 resistors of length 25um connected in series -Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500 -Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149 - -* voltage sources at 0V for measuring current in each branch - -Vm1 vssm1 vss DC=0 -Vm2 vdda vddm2 DC=0 -Vm3 vdda vddm3 DC=0 -Vm4 vssm4 vss DC=0 -Vm5 vssm5 vss DC=0 -Vm6 vdda vddm6 DC=0 -Vm7 vdda vddm7 DC=0 - -* D G S B -Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8 -Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7 -Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7 -Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 - -* Check branch currents in each mirror branch. -* 1st branch should be 240nA -* 2nd branch should be 30nA -* 3rd branch should be 4.3nA -* 4th branch should be 612pA -* -* Result: vin sits at 0.7590 (close to 0.7575 target) -* I(Vm1/2) = 202.80 nA -* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77 -* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70 -* I(Vm7) = 0.67 nA (should be /7) actually /6.80 - -*---------------------------- -* Testbench circuit -*---------------------------- -Vpwr vdda vss DC=3.3 -Rgnd vss 0 0.01 -Rload vcap vss 1MEG -*---------------------------- - -*---------------------------- -* Testbench control -*---------------------------- -.control -op -print V(vin) -print I(Vm1) -print I(Vm2) -print I(Vm3) -print I(Vm4) -print I(Vm5) -print I(Vm6) -print I(Vm7) -.endc - -.end - diff --git a/xschem/diff_pair.sch b/xschem/diff_pair.sch new file mode 100644 index 0000000..2d4cf02 --- /dev/null +++ b/xschem/diff_pair.sch @@ -0,0 +1,157 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 200 -150 300 -150 { +lab=#net1} +N 160 -120 160 20 { +lab=#net1} +N 340 -120 340 20 { +lab=vout} +N 160 -210 160 -180 { +lab=Vdd} +N 340 -210 340 -180 { +lab=Vdd} +N 160 -210 340 -210 { +lab=Vdd} +N 250 -230 250 -210 { +lab=Vdd} +N 160 -90 230 -90 { +lab=#net1} +N 230 -150 230 -90 { +lab=#net1} +N 160 80 160 110 { +lab=#net2} +N 160 110 340 110 { +lab=#net2} +N 340 80 340 110 { +lab=#net2} +N 250 110 250 140 { +lab=#net2} +N 250 200 250 220 { +lab=Vss} +N 160 50 340 50 { +lab=Vss} +N 250 50 250 60 { +lab=Vss} +N 140 -150 160 -150 { +lab=Vdd} +N 140 -190 140 -150 { +lab=Vdd} +N 140 -190 160 -190 { +lab=Vdd} +N 340 -150 360 -150 { +lab=Vdd} +N 360 -190 360 -150 { +lab=Vdd} +N 340 -190 360 -190 { +lab=Vdd} +N 180 170 210 170 { +lab=Vb} +N 250 170 270 170 { +lab=Vss} +N 270 170 270 210 { +lab=Vss} +N 250 210 270 210 { +lab=Vss} +N 340 -90 430 -90 { +lab=vout} +N 430 -90 470 -90 { +lab=vout} +N 250 60 250 90 { +lab=Vss} +N 250 90 310 90 { +lab=Vss} +N 310 90 310 230 { +lab=Vss} +N 250 220 250 230 { +lab=Vss} +N 440 230 440 250 { +lab=Vss} +N 440 250 440 260 { +lab=Vss} +N 250 230 440 230 { +lab=Vss} +N 100 50 120 50 { +lab=vinp} +N 380 50 400 50 { +lab=vinm} +C {devices/iopin.sym} 250 -230 0 0 {name=p1 lab=Vdd} +C {devices/ipin.sym} 400 50 2 0 {name=p2 lab=vinm} +C {devices/ipin.sym} 100 50 0 0 {name=p3 lab=vinp} +C {devices/iopin.sym} 180 170 2 0 {name=p4 lab=Vb} +C {devices/opin.sym} 470 -90 0 0 {name=p5 lab=vout} +C {devices/iopin.sym} 440 260 0 0 {name=p6 lab=Vss} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 140 50 0 0 {name=M1 +L=L_M1 +W=W_M1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 360 50 0 1 {name=M2 +L=L_M2 +W=W_M2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 320 -150 0 0 {name=M3 +L=L_M3 +W=W_M3 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 180 -150 0 1 {name=M4 +L=L_M4 +W=W_M4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 230 170 0 0 {name=M5 +L=L_M5 +W=W_M5 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} diff --git a/xschem/diff_pair.sym b/xschem/diff_pair.sym new file mode 100644 index 0000000..0cf870b --- /dev/null +++ b/xschem/diff_pair.sym @@ -0,0 +1,30 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -58.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +B 5 147.5 -32.5 152.5 -27.5 {name=Vdd dir=inout } +L 7 130 -30 150 -30 {} +T {Vdd} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vout dir=out } +L 4 130 -10 150 -10 {} +T {vout} 125 -14 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=vinp dir=in } +L 4 -150 -30 -130 -30 {} +T {vinp} -125 -34 0 0 0.2 0.2 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=vinm dir=in } +L 4 -150 -10 -130 -10 {} +T {vinm} -125 -14 0 0 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=Vb dir=inout } +L 7 130 10 150 10 {} +T {Vb} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=Vss dir=inout } +L 7 130 30 150 30 {} +T {Vss} 125 26 0 1 0.2 0.2 {} diff --git a/xschem/diff_pair_cascode.sch b/xschem/diff_pair_cascode.sch new file mode 100644 index 0000000..a39e4e1 --- /dev/null +++ b/xschem/diff_pair_cascode.sch @@ -0,0 +1,211 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 180 -420 280 -420 { +lab=#net1} +N 140 -390 140 -250 { +lab=#net1} +N 320 -390 320 -250 { +lab=vout} +N 140 -480 140 -450 { +lab=#net2} +N 320 -480 320 -450 { +lab=#net3} +N 140 -190 140 -160 { +lab=#net4} +N 140 -160 320 -160 { +lab=#net4} +N 320 -190 320 -160 { +lab=#net4} +N 230 -160 230 -130 { +lab=#net4} +N 230 -70 230 -50 { +lab=Vss} +N 140 -220 320 -220 { +lab=Vss} +N 230 -220 230 -210 { +lab=Vss} +N 120 -420 140 -420 { +lab=Vdd} +N 120 -460 120 -420 { +lab=Vdd} +N 320 -420 340 -420 { +lab=Vdd} +N 340 -460 340 -420 { +lab=Vdd} +N 160 -100 190 -100 { +lab=Vbn} +N 230 -100 250 -100 { +lab=Vss} +N 250 -100 250 -60 { +lab=Vss} +N 230 -60 250 -60 { +lab=Vss} +N 320 -360 410 -360 { +lab=vout} +N 410 -360 450 -360 { +lab=vout} +N 230 -210 230 -180 { +lab=Vss} +N 230 -180 290 -180 { +lab=Vss} +N 290 -180 290 -40 { +lab=Vss} +N 230 -50 230 -40 { +lab=Vss} +N 420 -40 420 -20 { +lab=Vss} +N 420 -20 420 -10 { +lab=Vss} +N 230 -40 420 -40 { +lab=Vss} +N 80 -220 100 -220 { +lab=vinp} +N 360 -220 380 -220 { +lab=vinm} +N 180 -580 280 -580 { +lab=#net2} +N 140 -640 140 -610 { +lab=Vdd} +N 320 -640 320 -610 { +lab=Vdd} +N 140 -640 320 -640 { +lab=Vdd} +N 230 -660 230 -640 { +lab=Vdd} +N 120 -580 140 -580 { +lab=Vdd} +N 120 -620 120 -580 { +lab=Vdd} +N 120 -620 140 -620 { +lab=Vdd} +N 320 -580 340 -580 { +lab=Vdd} +N 340 -620 340 -580 { +lab=Vdd} +N 320 -620 340 -620 { +lab=Vdd} +N 320 -550 320 -480 { +lab=#net3} +N 140 -550 140 -480 { +lab=#net2} +N 120 -580 120 -460 { +lab=Vdd} +N 340 -580 340 -460 { +lab=Vdd} +N 140 -520 210 -520 { +lab=#net2} +N 210 -580 210 -520 { +lab=#net2} +N 140 -340 210 -340 { +lab=#net1} +N 210 -420 210 -340 { +lab=#net1} +C {devices/ipin.sym} 380 -220 2 0 {name=p2 lab=vinm} +C {devices/ipin.sym} 80 -220 0 0 {name=p3 lab=vinp} +C {devices/iopin.sym} 160 -100 2 0 {name=p4 lab=Vbn} +C {devices/opin.sym} 450 -360 0 0 {name=p5 lab=vout} +C {devices/iopin.sym} 420 -10 0 0 {name=p6 lab=Vss} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 120 -220 0 0 {name=M1 +L=L_M1 +W=W_M1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 340 -220 0 1 {name=M2 +L=L_M2 +W=W_M2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 300 -420 0 0 {name=M3 +L=L_M3 +W=W_M3 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 160 -420 0 1 {name=M4 +L=L_M4 +W=W_M4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 210 -100 0 0 {name=M7 +L=L_M7 +W=W_M7 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 230 -660 0 0 {name=p7 lab=Vdd} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 300 -580 0 0 {name=M5 +L=L_M5 +W=W_M5 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 160 -580 0 1 {name=M6 +L=L_M6 +W=W_M6 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} diff --git a/xschem/diff_pair_cascode.sym b/xschem/diff_pair_cascode.sym new file mode 100644 index 0000000..bc362af --- /dev/null +++ b/xschem/diff_pair_cascode.sym @@ -0,0 +1,29 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -94.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +B 5 147.5 -32.5 152.5 -27.5 {name=Vdd dir=inout } +L 7 130 -30 150 -30 {} +T {Vdd} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vout dir=out } +L 4 130 -10 150 -10 {} +T {vout} 125 -14 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=vinm dir=in } +L 4 -150 -30 -130 -30 {} +T {vinm} -125 -34 0 0 0.2 0.2 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=vinp dir=in } +L 4 -150 -10 -130 -10 {} +T {vinp} -125 -14 0 0 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=Vbn dir=inout } +L 7 130 10 150 10 {} +T {Vbn} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=Vss dir=inout } +L 7 130 30 150 30 {} +T {Vss} 125 26 0 1 0.2 0.2 {} diff --git a/xschem/diff_pair_folded_cascode.sch b/xschem/diff_pair_folded_cascode.sch new file mode 100644 index 0000000..b0d5a0a --- /dev/null +++ b/xschem/diff_pair_folded_cascode.sch @@ -0,0 +1,278 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 670 -160 770 -160 { +lab=#net1} +N 160 -70 160 70 { +lab=#net2} +N 340 -70 340 70 { +lab=#net3} +N 630 -220 630 -190 { +lab=Vdd} +N 810 -220 810 -190 { +lab=Vdd} +N 710 -260 710 -240 { +lab=Vdd} +N 160 130 160 160 { +lab=#net4} +N 160 160 340 160 { +lab=#net4} +N 340 130 340 160 { +lab=#net4} +N 250 160 250 190 { +lab=#net4} +N 250 250 250 270 { +lab=Vss} +N 160 100 340 100 { +lab=Vss} +N 250 100 250 110 { +lab=Vss} +N 610 -160 630 -160 { +lab=Vdd} +N 610 -200 610 -160 { +lab=Vdd} +N 610 -200 630 -200 { +lab=Vdd} +N 810 -160 830 -160 { +lab=Vdd} +N 830 -200 830 -160 { +lab=Vdd} +N 810 -200 830 -200 { +lab=Vdd} +N 180 220 210 220 { +lab=Vb1} +N 250 220 270 220 { +lab=Vss} +N 270 220 270 260 { +lab=Vss} +N 250 260 270 260 { +lab=Vss} +N 250 110 250 140 { +lab=Vss} +N 250 140 310 140 { +lab=Vss} +N 310 140 310 280 { +lab=Vss} +N 250 270 250 280 { +lab=Vss} +N 440 280 440 300 { +lab=Vss} +N 440 300 440 310 { +lab=Vss} +N 250 280 440 280 { +lab=Vss} +N 100 100 120 100 { +lab=vinp} +N 380 100 400 100 { +lab=vinm} +N 670 40 770 40 { +lab=Vb2} +N 630 -20 630 10 { +lab=#net2} +N 810 -20 810 10 { +lab=#net3} +N 610 40 630 40 { +lab=Vdd} +N 810 40 830 40 { +lab=Vdd} +N 830 0 830 40 { +lab=Vdd} +N 810 -50 810 -20 { +lab=#net3} +N 810 70 810 150 { +lab=vout} +N 630 210 630 270 { +lab=Vss} +N 630 270 630 280 { +lab=Vss} +N 440 280 630 280 { +lab=Vss} +N 610 180 630 180 { +lab=Vss} +N 610 180 610 230 { +lab=Vss} +N 610 230 630 230 { +lab=Vss} +N 810 210 810 280 { +lab=Vss} +N 630 280 810 280 { +lab=Vss} +N 810 180 830 180 { +lab=Vss} +N 830 180 830 230 { +lab=Vss} +N 810 230 830 230 { +lab=Vss} +N 810 110 850 110 { +lab=vout} +N 670 180 770 180 { +lab=Vb1} +N 630 70 630 150 { +lab=#net1} +N 630 -220 810 -220 { +lab=Vdd} +N 710 -240 710 -220 { +lab=Vdd} +N 200 220 200 350 { +lab=Vb1} +N 200 350 720 350 { +lab=Vb1} +N 720 180 720 350 { +lab=Vb1} +N 630 -130 630 -20 { +lab=#net2} +N 810 -130 810 -50 { +lab=#net3} +N 690 -160 690 100 { +lab=#net1} +N 630 100 690 100 { +lab=#net1} +N 610 -160 610 40 { +lab=Vdd} +N 830 -160 830 0 { +lab=Vdd} +N 340 -70 810 -70 { +lab=#net3} +N 160 -100 160 -70 { +lab=#net2} +N 160 -100 630 -100 { +lab=#net2} +N 740 40 740 70 { +lab=Vb2} +C {devices/iopin.sym} 710 -260 0 0 {name=p1 lab=Vdd} +C {devices/ipin.sym} 400 100 2 0 {name=p2 lab=vinm} +C {devices/ipin.sym} 100 100 0 0 {name=p3 lab=vinp} +C {devices/iopin.sym} 180 220 2 0 {name=p4 lab=Vb1} +C {devices/iopin.sym} 440 310 0 0 {name=p6 lab=Vss} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 140 100 0 0 {name=M1 +L=L_M1 +W=W_M1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 360 100 0 1 {name=M2 +L=L_M2 +W=W_M2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 790 -160 0 0 {name=M4 +L=L_M4 +W=W_M4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 650 -160 0 1 {name=M3 +L=L_M3 +W=W_M3 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 230 220 0 0 {name=M9 +L=L_M9 +W=W_M9 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 790 40 0 0 {name=M6 +L=L_M6 +W=W_M6 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 650 40 0 1 {name=M5 +L=L_M5 +W=W_M5 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 650 180 0 1 {name=M7 +L=L_M7 +W=W_M7 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 790 180 0 0 {name=M8 +L=L_M8 +W=W_M8 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 740 70 1 0 {name=p7 lab=Vb2} +C {devices/opin.sym} 850 110 0 0 {name=p8 lab=vout} diff --git a/xschem/diff_pair_folded_cascode.sym b/xschem/diff_pair_folded_cascode.sym new file mode 100644 index 0000000..7eb1ae9 --- /dev/null +++ b/xschem/diff_pair_folded_cascode.sym @@ -0,0 +1,33 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -126 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +B 5 147.5 -42.5 152.5 -37.5 {name=Vdd dir=inout } +L 7 130 -40 150 -40 {} +T {Vdd} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=Vb2 dir=inout } +L 7 130 -20 150 -20 {} +T {Vb2} 125 -24 0 1 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=vinp dir=in } +L 4 -150 -40 -130 -40 {} +T {vinp} -125 -44 0 0 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=vinm dir=in } +L 4 -150 -20 -130 -20 {} +T {vinm} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=vout dir=out } +L 4 130 0 150 0 {} +T {vout} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Vb1 dir=inout } +L 7 130 20 150 20 {} +T {Vb1} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=Vss dir=inout } +L 7 130 40 150 40 {} +T {Vss} 125 36 0 1 0.2 0.2 {} diff --git a/xschem/diff_pair_folded_cascode2.sch b/xschem/diff_pair_folded_cascode2.sch new file mode 100644 index 0000000..4ab2bc2 --- /dev/null +++ b/xschem/diff_pair_folded_cascode2.sch @@ -0,0 +1,417 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 410 -110 510 -110 { +lab=#net1} +N 370 -80 370 60 { +lab=#net2} +N 550 -80 550 60 { +lab=#net3} +N 370 -170 370 -140 { +lab=Vdd} +N 550 -170 550 -140 { +lab=Vdd} +N 370 -170 550 -170 { +lab=Vdd} +N 460 -190 460 -170 { +lab=Vdd} +N 370 120 370 150 { +lab=#net4} +N 370 150 550 150 { +lab=#net4} +N 550 120 550 150 { +lab=#net4} +N 460 150 460 180 { +lab=#net4} +N 460 240 460 260 { +lab=Vss} +N 370 90 550 90 { +lab=Vss} +N 460 90 460 100 { +lab=Vss} +N 350 -110 370 -110 { +lab=Vdd} +N 350 -150 350 -110 { +lab=Vdd} +N 350 -150 370 -150 { +lab=Vdd} +N 550 -110 570 -110 { +lab=Vdd} +N 570 -150 570 -110 { +lab=Vdd} +N 550 -150 570 -150 { +lab=Vdd} +N 390 210 420 210 { +lab=#net5} +N 460 210 480 210 { +lab=Vss} +N 480 210 480 250 { +lab=Vss} +N 460 250 480 250 { +lab=Vss} +N 460 100 460 130 { +lab=Vss} +N 460 130 520 130 { +lab=Vss} +N 520 130 520 270 { +lab=Vss} +N 460 260 460 270 { +lab=Vss} +N 650 270 650 290 { +lab=Vss} +N 650 290 650 300 { +lab=Vss} +N 460 270 650 270 { +lab=Vss} +N 310 90 330 90 { +lab=vinp} +N 590 90 610 90 { +lab=vinm} +N 880 30 980 30 { +lab=#net6} +N 840 -30 840 0 { +lab=#net2} +N 1020 -30 1020 0 { +lab=#net3} +N 820 30 840 30 { +lab=Vdd} +N 1020 30 1040 30 { +lab=Vdd} +N 1040 -10 1040 30 { +lab=Vdd} +N 370 -30 840 -30 { +lab=#net2} +N 1020 -60 1020 -30 { +lab=#net3} +N 550 -60 1020 -60 { +lab=#net3} +N 840 60 840 140 { +lab=#net7} +N 1020 60 1020 140 { +lab=vout} +N 880 170 980 170 { +lab=#net7} +N 840 100 920 100 { +lab=#net7} +N 920 100 920 170 { +lab=#net7} +N 840 200 840 260 { +lab=Vss} +N 840 260 840 270 { +lab=Vss} +N 650 270 840 270 { +lab=Vss} +N 820 170 840 170 { +lab=Vss} +N 820 170 820 220 { +lab=Vss} +N 820 220 840 220 { +lab=Vss} +N 1020 200 1020 270 { +lab=Vss} +N 840 270 1020 270 { +lab=Vss} +N 1020 170 1040 170 { +lab=Vss} +N 1040 170 1040 220 { +lab=Vss} +N 1020 220 1040 220 { +lab=Vss} +N 460 -110 460 -70 { +lab=#net1} +N 260 -70 460 -70 { +lab=#net1} +N 1020 100 1060 100 { +lab=vout} +N 550 -170 820 -170 { +lab=Vdd} +N 1040 -170 1040 -10 { +lab=Vdd} +N 820 -170 1040 -170 { +lab=Vdd} +N 820 -170 820 30 { +lab=Vdd} +N 10 -170 10 -140 { +lab=Vdd} +N 10 -170 30 -170 { +lab=Vdd} +N 10 -140 10 -100 { +lab=Vdd} +N 50 -70 160 -70 { +lab=#net1} +N 10 240 10 270 { +lab=Vss} +N 10 270 30 270 { +lab=Vss} +N -20 270 10 270 { +lab=Vss} +N -20 -70 10 -70 { +lab=Vdd} +N -20 -170 -20 -70 { +lab=Vdd} +N -20 -170 10 -170 { +lab=Vdd} +N 10 -20 80 -20 { +lab=#net1} +N 80 -70 80 -20 { +lab=#net1} +N -170 270 -20 270 { +lab=Vss} +N -200 270 -170 270 { +lab=Vss} +N -170 -170 -20 -170 { +lab=Vdd} +N -340 240 -340 270 { +lab=Vss} +N -340 270 -200 270 { +lab=Vss} +N -370 210 -340 210 { +lab=Vss} +N -370 210 -370 270 { +lab=Vss} +N -370 270 -340 270 { +lab=Vss} +N -300 210 -260 210 { +lab=#net5} +N -260 160 -260 210 { +lab=#net5} +N -340 100 -340 180 { +lab=#net5} +N -340 160 -260 160 { +lab=#net5} +N 160 -70 260 -70 { +lab=#net1} +N 20 -170 370 -170 { +lab=Vdd} +N 140 210 390 210 { +lab=#net5} +N 30 270 460 270 { +lab=Vss} +N -340 -170 -340 40 { +lab=Vdd} +N -340 -170 -190 -170 { +lab=Vdd} +N -190 -170 -170 -170 { +lab=Vdd} +N 10 -40 10 -20 { +lab=#net1} +N -20 -70 -20 50 { +lab=Vdd} +N -20 50 10 50 { +lab=Vdd} +N 10 -20 10 20 { +lab=#net1} +N 50 50 930 50 { +lab=#net6} +N 930 30 930 50 { +lab=#net6} +N 10 80 10 180 { +lab=#net6} +N 10 110 80 110 { +lab=#net6} +N 80 50 80 110 { +lab=#net6} +N -260 210 -30 210 { +lab=#net5} +N 10 210 50 210 { +lab=Vss} +N 50 210 50 270 { +lab=Vss} +N -170 160 -170 210 { +lab=#net5} +N -170 160 140 160 { +lab=#net5} +N 140 160 140 210 { +lab=#net5} +C {devices/iopin.sym} 460 -190 0 0 {name=p1 lab=Vdd} +C {devices/ipin.sym} 610 90 2 0 {name=p2 lab=vinm} +C {devices/ipin.sym} 310 90 0 0 {name=p3 lab=vinp} +C {devices/iopin.sym} 650 300 0 0 {name=p6 lab=Vss} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 350 90 0 0 {name=M1 +L=L_M1 +W=W_M1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 570 90 0 1 {name=M2 +L=L_M2 +W=W_M2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 530 -110 0 0 {name=M4 +L=L_M4 +W=W_M4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 390 -110 0 1 {name=M3 +L=L_M3 +W=W_M3 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 440 210 0 0 {name=M9 +L=L_M9 +W=W_M9 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 1000 30 0 0 {name=M6 +L=L_M6 +W=W_M6 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 860 30 0 1 {name=M5 +L=L_M5 +W=W_M5 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 860 170 0 1 {name=M7 +L=L_M7 +W=W_M7 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1000 170 0 0 {name=M8 +L=L_M8 +W=W_M8 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/opin.sym} 1060 100 0 0 {name=p8 lab=vout} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 30 -70 0 1 {name=MB3 +L=L_MB3 +W=W_M3 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} -10 210 0 0 {name=MB1 +L=L_MB1 +W=W_MB1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 30 50 0 1 {name=MB2 +L=L_MB2 +W=W_MB2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} -320 210 0 1 {name=MB4 +L=L_MB4 +W=W_MB4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/isource.sym} -340 70 0 0 {name=Ibias value=100u} diff --git a/xschem/diff_pair_tb.sch b/xschem/diff_pair_tb.sch new file mode 100644 index 0000000..f259819 --- /dev/null +++ b/xschem/diff_pair_tb.sch @@ -0,0 +1,85 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 600 350 620 350 { +lab=GND} +N 620 350 620 370 { +lab=GND} +N 120 360 120 370 { +lab=GND} +N 120 290 120 300 { +lab=#net1} +N 190 290 300 290 { +lab=#net1} +N 600 290 620 290 { +lab=VDD} +N 620 270 620 290 { +lab=VDD} +N 330 570 330 580 { +lab=GND} +N 330 480 330 510 { +lab=VDD} +N 600 310 650 310 { +lab=vout} +N 680 420 680 430 { +lab=GND} +N 680 330 680 360 { +lab=#net2} +N 600 330 680 330 { +lab=#net2} +N 780 420 780 430 { +lab=GND} +N 650 310 810 310 { +lab=vout} +N 780 310 780 360 { +lab=vout} +N 250 370 250 390 { +lab=GND} +N 250 310 300 310 { +lab=#net3} +N 120 290 190 290 { +lab=#net1} +C {devices/gnd.sym} 620 370 0 0 {name=l1 lab=GND} +C {devices/gnd.sym} 250 390 0 0 {name=l2 lab=GND} +C {devices/vsource.sym} 120 330 0 0 {name=V1 value="dc Vcm ac 1"} +C {devices/gnd.sym} 120 370 0 0 {name=l3 lab=GND} +C {devices/vdd.sym} 620 270 0 0 {name=l4 lab=VDD} +C {devices/vsource.sym} 330 540 0 0 {name=V2 value=Vdd} +C {devices/gnd.sym} 330 580 0 0 {name=l5 lab=GND} +C {devices/vdd.sym} 330 480 0 0 {name=l6 lab=VDD} +C {devices/opin.sym} 810 310 0 0 {name=p1 lab=vout} +C {devices/vsource.sym} 680 390 0 0 {name=V3 value=Vb} +C {devices/gnd.sym} 680 430 0 0 {name=l7 lab=GND} +C {devices/code_shown.sym} 460 480 0 0 {name=s1 only_toplevel=false value=".lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt"} +C {devices/capa.sym} 780 390 0 0 {name=C1 +m=1 +value=100p +footprint=1206 +device="ceramic capacitor"} +C {devices/gnd.sym} 780 430 0 0 {name=l8 lab=GND} +C {devices/code_shown.sym} 460 560 0 0 {name=s2 only_toplevel=false +value=".include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/diff_pair_tb_vars.spice +"} +C {devices/vsource.sym} 250 340 0 0 {name=V4 value="dc Vcm"} +C {devices/code_shown.sym} 460 640 0 0 {name=s3 only_toplevel=false +value=" +.control +save all +set filetype=ascii +set units=degrees + +dc V1 0 3 0.01 +plot v(vout) + +ac dec 10 1 1e10 +plot mag(v(vout)) +plot vdb(vout) +plot ph(v(vout)) + +.endc +"} +C {diff_pair.sym} 450 320 0 0 {name=x1} diff --git a/xschem/example_por.sch b/xschem/example_por.sch deleted file mode 100644 index cf6e0c3..0000000 --- a/xschem/example_por.sch +++ /dev/null @@ -1,297 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -L 4 3370 -60 3390 -60 {} -L 4 3390 -60 3390 80 {} -L 4 3370 80 3390 80 {} -T {Current step-down mirror} 2270 140 0 0 0.4 0.4 {} -T {Charge accumulator} 2650 140 0 0 0.4 0.4 {} -T {Voltage divider} 1860 140 0 0 0.4 0.4 {} -T {Schmitt trigger} 2930 -200 0 0 0.4 0.4 {} -T {150 / 650 * 3.3V = 0.76V} 1860 180 0 0 0.4 0.4 {} -T {step down 8x} 2130 -430 0 0 0.4 0.4 {} -T {step down 7x} 2330 80 0 0 0.4 0.4 {} -T {step down 7x} 2520 -430 0 0 0.4 0.4 {} -T {1.8V domain outputs} 3400 0 0 0 0.4 0.4 {} -T {3.3V domain output} 3410 -140 0 0 0.4 0.4 {} -T {392 : 1} 2270 180 0 0 0.4 0.4 {} -T {Simple power-on-reset circuit -calibrated to 500us nominal delay -no temperature compensation} 1950 -570 0 0 0.6 0.6 {} -N 2500 -310 2500 -270 { lab=#net1} -N 2500 -210 2500 -100 { lab=#net2} -N 2300 -40 2300 20 { lab=#net3} -N 2300 80 2300 110 { lab=vss} -N 2360 110 2500 110 { lab=vss} -N 2500 80 2500 110 { lab=vss} -N 2400 50 2460 50 { lab=#net3} -N 2360 -400 2500 -400 { lab=vdd3v3} -N 2500 -400 2500 -370 { lab=vdd3v3} -N 2500 -400 2790 -400 { lab=vdd3v3} -N 2300 -10 2370 -10 { lab=#net3} -N 2370 -10 2370 50 { lab=#net3} -N 2500 -290 2570 -290 { lab=#net1} -N 2570 -340 2570 -290 { lab=#net1} -N 2540 -340 2570 -340 { lab=#net1} -N 2500 -190 2570 -190 { lab=#net2} -N 2570 -240 2570 -190 { lab=#net2} -N 2540 -240 2570 -240 { lab=#net2} -N 2240 110 2360 110 { lab=vss} -N 2500 110 2630 110 { lab=vss} -N 2500 50 2630 50 { lab=vss} -N 2110 110 2240 110 { lab=vss} -N 1930 60 1930 110 { lab=vss} -N 1930 -160 1930 0 { lab=#net4} -N 1930 -400 1930 -220 { lab=vdd3v3} -N 2110 -400 2360 -400 { lab=vdd3v3} -N 1880 -190 1910 -190 { lab=vss} -N 1880 -190 1880 110 { lab=vss} -N 1880 110 1930 110 { lab=vss} -N 1880 30 1910 30 { lab=vss} -N 2300 -310 2300 -270 { lab=#net5} -N 2300 -400 2300 -370 { lab=vdd3v3} -N 2300 -140 2300 -100 { lab=#net3} -N 2340 50 2400 50 { lab=#net3} -N 2300 -210 2300 -140 { lab=#net3} -N 2100 80 2100 110 { lab=vss} -N 2100 110 2110 110 { lab=vss} -N 2050 50 2060 50 { lab=#net4} -N 2050 -70 2050 50 { lab=#net4} -N 1930 -70 2050 -70 { lab=#net4} -N 1930 -400 2110 -400 { lab=vdd3v3} -N 2100 -400 2100 -370 { lab=vdd3v3} -N 2100 -310 2100 -270 { lab=#net6} -N 2100 -210 2100 20 { lab=#net7} -N 2100 50 2300 50 { lab=vss} -N 2200 50 2200 110 { lab=vss} -N 2140 -240 2260 -240 { lab=#net7} -N 2140 -340 2260 -340 { lab=#net6} -N 2100 -290 2180 -290 { lab=#net6} -N 2180 -340 2180 -290 { lab=#net6} -N 2100 -180 2180 -180 { lab=#net7} -N 2180 -240 2180 -180 { lab=#net7} -N 1930 -240 2100 -240 { lab=vdd3v3} -N 1930 -340 2100 -340 { lab=vdd3v3} -N 1930 110 2100 110 { lab=vss} -N 2300 -240 2500 -240 { lab=vdd3v3} -N 2300 -340 2500 -340 { lab=vdd3v3} -N 2400 -340 2400 -240 { lab=vdd3v3} -N 2400 -400 2400 -340 { lab=vdd3v3} -N 2570 -240 2650 -240 { lab=#net2} -N 2570 -340 2650 -340 { lab=#net1} -N 2690 -400 2690 -370 { lab=vdd3v3} -N 2790 -400 2790 -340 { lab=vdd3v3} -N 2690 -340 2790 -340 { lab=vdd3v3} -N 2690 -240 2790 -240 { lab=vdd3v3} -N 2790 -340 2790 -240 { lab=vdd3v3} -N 2690 -310 2690 -270 { lab=#net8} -N 2690 -210 2690 -150 { lab=#net9} -N 1830 30 1880 30 { lab=vss} -N 1810 60 1810 110 { lab=vss} -N 1810 110 1880 110 { lab=vss} -N 1810 -70 1810 0 { lab=vss} -N 1810 -70 1880 -70 { lab=vss} -N 2690 -150 2690 -70 { lab=#net9} -N 2820 -130 2820 -70 { lab=#net9} -N 2690 -130 2820 -130 { lab=#net9} -N 2630 110 2820 110 { lab=vss} -N 2820 -10 2820 110 { lab=vss} -N 2690 -10 2690 110 { lab=vss} -N 2820 -130 2980 -130 { lab=#net9} -N 3060 -130 3130 -130 { lab=#net10} -N 3090 -130 3090 60 { lab=#net10} -N 3090 60 3130 60 { lab=#net10} -N 3090 -40 3130 -40 { lab=#net10} -N 3210 -130 3300 -130 { lab=porb_h} -N 3210 -40 3300 -40 { lab=porb_l} -N 3210 60 3300 60 { lab=por_l} -N 2790 -400 2840 -400 { lab=vdd3v3} -N 2820 110 2870 110 { lab=vss} -N 2630 50 2690 50 { lab=vss} -N 2300 -100 2300 -40 { lab=#net3} -N 2500 -100 2500 -30 { lab=#net2} -N 2500 -30 2500 20 { lab=#net2} -C {sky130_fd_pr/cap_mim_m3_1.sym} 2690 -40 0 0 {name=C1 model=cap_mim_m3_1 W=30 L=30 MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 2 1 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -240 0 0 {name=M1 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2480 50 0 0 {name=M2 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=nfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 -190 0 0 {name=R1 -L=500 -model=res_xhigh_po_0p69 -spiceprefix=X -mult=1} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -340 0 0 {name=M4 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2320 50 0 1 {name=M5 -L=0.8 -W=14 -nf=7 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=nfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 30 0 0 {name=R2 -L=150 -model=res_xhigh_po_0p69 -spiceprefix=X -mult=1} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -240 0 1 {name=M7 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -340 0 1 {name=M8 -L=0.8 -W=14 -nf=7 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2080 50 0 0 {name=M10 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=nfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -240 0 1 {name=M9 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -340 0 1 {name=M11 -L=0.8 -W=16 -nf=8 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -340 0 0 {name=M12 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -240 0 0 {name=M13 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1810 30 0 1 {name=R3 -L=25 -model=res_xhigh_po_0p69 -spiceprefix=X -mult=2} -C {sky130_stdcells/buf_8.sym} 3170 -130 0 0 {name=x2 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__ } -C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ } -C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ } -C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt } -C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3} -C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss} -C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h} -C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l} -C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l} -C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8} diff --git a/xschem/example_por.sym b/xschem/example_por.sym deleted file mode 100644 index e3875f5..0000000 --- a/xschem/example_por.sym +++ /dev/null @@ -1,33 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -V {} -S {} -E {} -L 4 -130 -60 130 -60 {} -L 4 -130 60 130 60 {} -L 4 -130 -60 -130 60 {} -L 4 130 -60 130 60 {} -L 4 130 -30 150 -30 {} -L 4 130 0 150 0 {} -L 4 130 30 150 30 {} -L 7 -30 -80 -30 -60 {} -L 7 30 -80 30 -60 {} -L 7 0 60 0 80 {} -B 5 -32.5 -82.5 -27.5 -77.5 {name=vdd3v3 dir=inout } -B 5 27.5 -82.5 32.5 -77.5 {name=vdd1v8 dir=inout } -B 5 147.5 -32.5 152.5 -27.5 {name=porb_h dir=out } -B 5 147.5 -2.5 152.5 2.5 {name=porb_l dir=out } -B 5 147.5 27.5 152.5 32.5 {name=por_l dir=out } -B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout } -T {@symname} -47.5 -6 0 0 0.3 0.3 {} -T {@name} -25 18 0 0 0.2 0.2 {} -T {vdd3v3} -15 -54 0 1 0.2 0.2 {} -T {vdd1v8} 55 -54 0 1 0.2 0.2 {} -T {porb_h} 125 -34 0 1 0.2 0.2 {} -T {porb_l} 125 -4 0 1 0.2 0.2 {} -T {por_l} 125 26 0 1 0.2 0.2 {} -T {vss} 5 46 0 1 0.2 0.2 {} diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch deleted file mode 100644 index a24d814..0000000 --- a/xschem/example_por_tb.sch +++ /dev/null @@ -1,45 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -T {Testbench for simple POR} -350 -240 0 0 0.6 0.6 {} -N -280 60 -10 60 { lab=GND} -N -540 0 -540 60 { lab=GND} -N -330 0 -330 60 { lab=GND} -N -330 -100 -330 -60 { lab=vdd3v3} -N -330 -110 -330 -100 { lab=vdd3v3} -N -210 -110 -40 -110 { lab=vdd3v3} -N -40 -110 -40 -100 { lab=vdd3v3} -N -540 -130 -540 -60 { lab=vdd1v8} -N -280 -130 20 -130 { lab=vdd1v8} -N 20 -130 20 -100 { lab=vdd1v8} -N 140 -50 180 -50 { lab=porb_h} -N 140 -20 180 -20 { lab=porb_l} -N 140 10 180 10 { lab=por_l} -N -340 -110 -330 -110 { lab=vdd3v3} -N -500 -130 -490 -130 { lab=vdd1v8} -N -540 -130 -500 -130 { lab=vdd1v8} -N -560 -130 -540 -130 { lab=vdd1v8} -N -540 60 -490 60 { lab=GND} -N -490 -130 -280 -130 { lab=vdd1v8} -N -490 60 -330 60 { lab=GND} -N -330 60 -280 60 { lab=GND} -N -330 -110 -210 -110 { lab=vdd3v3} -C {example_por.sym} -10 -20 0 0 {name=x1} -C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND} -C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"} -C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"} -C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3} -C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8} -C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h} -C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l} -C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l} -C {devices/code.sym} -470 140 0 0 {name=TT_MODELS only_toplevel=false -format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt -.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"} -C {devices/code_shown.sym} -320 160 0 0 {name=s2 only_toplevel=false value=".control -tran 1u 20m -plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l) -.endc"} diff --git a/xschem/example_por_tb.spice b/xschem/example_por_tb.spice deleted file mode 100644 index fa82f74..0000000 --- a/xschem/example_por_tb.spice +++ /dev/null @@ -1,78 +0,0 @@ -**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l -*.opin vdd3v3 -*.opin vdd1v8 -*.opin porb_h -*.opin porb_l -*.opin por_l -x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por -V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3) -V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8) -**** begin user architecture code -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt -.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice - -.control -tran 1u 20m -plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l) -.endc - -**** end user architecture code -**.ends - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1 -XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1 -XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2 -x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -.GLOBAL GND -** flattened .save nodes -.end diff --git a/xschem/example_por_tb.spice.orig b/xschem/example_por_tb.spice.orig deleted file mode 100644 index 069c74d..0000000 --- a/xschem/example_por_tb.spice.orig +++ /dev/null @@ -1,88 +0,0 @@ -**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l -.param mc_switch=0 -*.opin vdd3v3 -*.opin vdd1v8 -*.opin porb_h -*.opin porb_l -*.opin por_l -x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por -V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3) -V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8) -**** begin user architecture code - -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt - - -.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice - -.control -tran 1u 20m -plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l) -.endc - -**** end user architecture code -**.ends - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net11 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 net11 vss sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net5 net9 net7 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net1 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net6 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1 -XM3 net3 net5 net1 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM4 net7 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net4 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM6 net5 net5 net4 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net6 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1 -XM7 net3 net3 net2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net2 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net9 net6 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net9 net9 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net8 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net10 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net11 net3 net10 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2 -x2 net12 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net12 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net12 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net11 vss vss vdd3v3 vdd3v3 net12 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -.GLOBAL GND -** flattened .save nodes -.end diff --git a/xschem/folded_cascode_tb.sch b/xschem/folded_cascode_tb.sch new file mode 100644 index 0000000..2626977 --- /dev/null +++ b/xschem/folded_cascode_tb.sch @@ -0,0 +1,112 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 480 150 500 150 { +lab=#net1} +N 480 130 500 130 { +lab=Vin} +N 320 350 320 360 { +lab=GND} +N 320 300 320 350 { +lab=GND} +N 320 180 320 240 { +lab=Vin} +N 320 130 320 180 { +lab=Vin} +N 320 130 480 130 { +lab=Vin} +N 440 350 440 360 { +lab=GND} +N 440 300 440 350 { +lab=GND} +N 440 150 440 240 { +lab=#net1} +N 440 150 480 150 { +lab=#net1} +N 1000 250 1000 260 { +lab=GND} +N 1000 200 1000 250 { +lab=GND} +N 800 130 1000 130 { +lab=#net2} +N 1000 130 1000 140 { +lab=#net2} +N 940 280 940 360 { +lab=GND} +N 870 240 870 250 { +lab=#net3} +N 870 310 870 390 { +lab=GND} +N 870 230 870 240 { +lab=#net3} +N 870 210 870 230 { +lab=#net3} +N 870 190 870 210 { +lab=#net3} +N 800 190 870 190 { +lab=#net3} +N 800 150 940 150 { +lab=#net4} +N 940 150 940 220 { +lab=#net4} +N 800 210 800 340 { +lab=GND} +N 800 340 870 340 { +lab=GND} +N 800 170 850 170 { +lab=Vout} +N 830 270 830 340 { +lab=GND} +N 830 170 830 210 { +lab=Vout} +C {sky130_fd_pr/corner.sym} 110 30 0 0 {name=CORNER only_toplevel=false corner=tt} +C {diff_pair_folded_cascode.sym} 650 170 0 0 {name=x2} +C {devices/gnd.sym} 320 360 0 0 {name=l7 lab=GND} +C {devices/vsource.sym} 320 270 0 0 {name=Vin value="ac 1 dc 1.8"} +C {devices/gnd.sym} 440 360 0 0 {name=l1 lab=GND} +C {devices/vsource.sym} 440 270 0 0 {name=Vb value="dc 1.8"} +C {devices/gnd.sym} 1000 260 0 0 {name=l2 lab=GND} +C {devices/vsource.sym} 1000 170 0 0 {name=Vdd2 value="dc 2"} +C {devices/gnd.sym} 940 360 0 0 {name=l6 lab=GND} +C {devices/vsource.sym} 940 250 0 0 {name=Vb2 value=Vb2} +C {devices/gnd.sym} 870 390 0 0 {name=l13 lab=GND} +C {devices/vsource.sym} 870 280 0 0 {name=Vb1 value=Vb1} +C {devices/opin.sym} 850 170 0 0 {name=p7 lab=Vout} +C {devices/code_shown.sym} 290 490 0 0 {name=s2 only_toplevel=false value=".include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/ldo_folded_cascode_tb_vars.spice +"} +C {devices/code_shown.sym} 290 580 0 0 {name=s4 only_toplevel=false +value=" + +.control +* high precision simulation +*.OPTIONS maxord=1 +.OPTIONS itl1=200 +.OPTIONS itl2=200 +.OPTIONS itl4=200 + +* save all voltage and current +save all +.options savecurrents +set filetype=ascii +set units=degrees + +* AC +ac dec 10 1 10G +plot vdb(Vout) vp(Vout) + +* DC sweep +dc Vin 0 3 0.01 +plot v(Vin) v(Vout) + +.endc +"} +C {devices/lab_pin.sym} 320 170 0 0 {name=p8 sig_type=std_logic lab=Vin} +C {devices/capa.sym} 830 240 0 0 {name=C1 +m=1 +value=20p +footprint=1206 +device="ceramic capacitor"} diff --git a/xschem/ldo.sch b/xschem/ldo.sch new file mode 100644 index 0000000..a5710a5 --- /dev/null +++ b/xschem/ldo.sch @@ -0,0 +1,94 @@ +v {xschem version=3.4.1 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 400 30 480 30 { +lab=#net1} +N 400 10 420 10 { +lab=Vdd} +N 420 -30 420 10 { +lab=Vdd} +N 420 -30 520 -30 { +lab=Vdd} +N 820 -30 820 0 { +lab=Vdd} +N 820 -50 820 0 { +lab=Vdd} +N 820 -60 820 -50 { +lab=Vdd} +N 520 -30 590 -30 { +lab=Vdd} +N 480 30 550 30 { +lab=#net1} +N 590 -30 820 -30 { +lab=Vdd} +N 550 30 780 30 { +lab=#net1} +N 820 60 820 110 { +lab=Vreg} +N 820 110 820 190 { +lab=Vreg} +N 820 190 940 190 { +lab=Vreg} +N 400 50 450 50 { +lab=Vb} +N 400 70 450 70 { +lab=Vss} +N 820 30 870 30 { +lab=Vdd} +N 80 30 100 30 { +lab=Vref} +N 870 -20 870 30 { +lab=Vdd} +N 820 -20 870 -20 { +lab=Vdd} +N 80 10 100 10 { +lab=Vfb} +N 560 30 560 110 { +lab=#net1} +N 560 110 600 110 { +lab=#net1} +N 760 110 820 110 { +lab=Vreg} +N 600 110 610 110 { +lab=#net1} +N 670 110 690 110 { +lab=#net2} +N 750 110 760 110 { +lab=Vreg} +N 640 130 640 150 { +lab=Vss} +N 430 150 640 150 { +lab=Vss} +N 430 70 430 150 { +lab=Vss} +C {devices/iopin.sym} 450 50 0 0 {name=p3 lab=Vb} +C {devices/iopin.sym} 450 70 0 0 {name=p4 lab=Vss} +C {devices/opin.sym} 940 190 0 0 {name=p2 lab=Vreg} +C {devices/iopin.sym} 80 30 2 0 {name=p5 lab=Vref} +C {devices/ipin.sym} 820 -60 0 0 {name=p1 lab=Vdd} +C {diff_pair.sym} 250 40 0 0 {name=x1} +C {devices/iopin.sym} 80 10 2 0 {name=p6 lab=Vfb} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 800 30 0 0 {name=M6 +L=L_pass +W=W_pass +nf=Nf_pass +mult=M_pass +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/cap_mim_m3_1.sym} 720 110 3 0 {name=Cfb model=cap_mim_m3_1 W=10 L=10 MF=M_Cfb spiceprefix=X} +C {sky130_fd_pr/res_high_po_0p35.sym} 640 110 3 0 {name=Rfb +L=3 +model=res_high_po_0p35 +spiceprefix=X +mult=M_Rfb} diff --git a/xschem/ldo.sym b/xschem/ldo.sym new file mode 100644 index 0000000..1632c40 --- /dev/null +++ b/xschem/ldo.sym @@ -0,0 +1,29 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -31.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=Vdd dir=in } +L 4 -150 -40 -130 -40 {} +T {Vdd} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=Vfb dir=inout } +L 7 130 -40 150 -40 {} +T {Vfb} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=Vref dir=inout } +L 7 130 -20 150 -20 {} +T {Vref} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=Vb dir=inout } +L 7 130 0 150 0 {} +T {Vb} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Vss dir=inout } +L 7 130 20 150 20 {} +T {Vss} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=Vreg dir=out } +L 4 130 40 150 40 {} +T {Vreg} 125 36 0 1 0.2 0.2 {} diff --git a/xschem/ldo_cascode.sch b/xschem/ldo_cascode.sch new file mode 100644 index 0000000..17dcf87 --- /dev/null +++ b/xschem/ldo_cascode.sch @@ -0,0 +1,88 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 170 -20 190 -20 { +lab=Vdd} +N 190 -60 190 -20 { +lab=Vdd} +N 190 -60 290 -60 { +lab=Vdd} +N 590 -60 590 -30 { +lab=Vdd} +N 590 -80 590 -30 { +lab=Vdd} +N 590 -90 590 -80 { +lab=Vdd} +N 290 -60 360 -60 { +lab=Vdd} +N 360 -60 590 -60 { +lab=Vdd} +N 320 0 550 0 { +lab=#net1} +N 590 30 590 80 { +lab=Vreg} +N 590 80 590 160 { +lab=Vreg} +N 590 160 710 160 { +lab=Vreg} +N 170 20 220 20 { +lab=Vbn} +N 170 40 220 40 { +lab=Vss} +N 590 0 640 0 { +lab=Vdd} +N -150 0 -130 0 { +lab=Vfb} +N 640 -50 640 0 { +lab=Vdd} +N 590 -50 640 -50 { +lab=Vdd} +N -150 -20 -130 -20 { +lab=Vref} +N 330 0 330 80 { +lab=#net1} +N 330 80 370 80 { +lab=#net1} +N 430 80 470 80 { +lab=#net2} +N 530 80 590 80 { +lab=Vreg} +N 300 0 320 -0 { +lab=#net1} +N 170 0 300 0 { +lab=#net1} +C {devices/iopin.sym} 220 20 0 0 {name=p3 lab=Vbn} +C {devices/iopin.sym} 220 40 0 0 {name=p4 lab=Vss} +C {devices/opin.sym} 710 160 0 0 {name=p2 lab=Vreg} +C {devices/iopin.sym} -150 -20 2 0 {name=p5 lab=Vref} +C {devices/ipin.sym} 590 -90 0 0 {name=p1 lab=Vdd} +C {devices/iopin.sym} -150 0 2 0 {name=p6 lab=Vfb} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 570 0 0 0 {name=M8 +L=L_pass +W=W_pass +nf=1 +mult=M_pass +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/res.sym} 400 80 3 0 {name=Rfb +value=Rfb +footprint=1206 +device=resistor +m=1} +C {devices/capa.sym} 500 80 3 0 {name=Cfb +m=1 +value=Cfb +footprint=1206 +device="ceramic capacitor"} +C {diff_pair_cascode.sym} 20 10 0 0 {name=x1} diff --git a/xschem/ldo_cascode.sym b/xschem/ldo_cascode.sym new file mode 100644 index 0000000..6d1a25e --- /dev/null +++ b/xschem/ldo_cascode.sym @@ -0,0 +1,30 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -67.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=Vdd dir=in } +L 4 -150 -40 -130 -40 {} +T {Vdd} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=Vref dir=inout } +L 7 130 -40 150 -40 {} +T {Vref} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=Vfb dir=inout } +L 7 130 -20 150 -20 {} +T {Vfb} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=Vbn dir=inout } +L 7 130 0 150 0 {} +T {Vbn} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Vss dir=inout } +L 7 130 20 150 20 {} +T {Vss} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=Vreg dir=out } +L 4 130 40 150 40 {} +T {Vreg} 125 36 0 1 0.2 0.2 {} diff --git a/xschem/ldo_cascode_tb.sch b/xschem/ldo_cascode_tb.sch new file mode 100644 index 0000000..8515114 --- /dev/null +++ b/xschem/ldo_cascode_tb.sch @@ -0,0 +1,102 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 770 -170 770 -90 { +lab=GND} +N 480 -230 650 -230 { +lab=#net1} +N 700 -230 700 -220 { +lab=#net1} +N 700 -160 700 -140 { +lab=GND} +N 480 -210 500 -210 { +lab=GND} +N 510 0 510 20 { +lab=GND} +N 480 -190 510 -190 { +lab=Vreg} +N 580 0 580 10 { +lab=GND} +N 510 10 580 10 { +lab=GND} +N 510 -190 580 -190 { +lab=Vreg} +N 580 -190 600 -190 { +lab=Vreg} +N 130 -80 130 -70 { +lab=GND} +N 650 -230 700 -230 { +lab=#net1} +N 130 -130 130 -80 { +lab=GND} +N 130 -250 130 -190 { +lab=Vdd} +N 130 -270 180 -270 { +lab=Vdd} +N 130 -270 130 -250 { +lab=Vdd} +N 510 -190 510 -160 { +lab=Vreg} +N 580 -190 580 -160 { +lab=Vreg} +N 580 -100 580 -90 { +lab=GND} +N 580 -30 580 0 { +lab=GND} +N 510 -100 510 0 { +lab=GND} +N 580 -90 580 -30 { +lab=GND} +N 580 -250 580 -190 { +lab=Vreg} +N 480 -270 770 -270 { +lab=Vref} +N 770 -270 770 -230 { +lab=Vref} +N 480 -250 580 -250 { +lab=Vreg} +C {devices/gnd.sym} 770 -90 0 0 {name=l1 lab=GND} +C {devices/vsource.sym} 770 -200 0 0 {name=Vref value="ac 0 dc Vref"} +C {devices/vsource.sym} 700 -190 0 0 {name=Vb value=Vbn} +C {devices/gnd.sym} 700 -140 0 0 {name=l3 lab=GND} +C {devices/gnd.sym} 500 -210 3 0 {name=l4 lab=GND} +C {devices/gnd.sym} 510 20 0 0 {name=l5 lab=GND} +C {devices/isource.sym} 580 -130 0 0 {name=IL value="dc IL PWL(0 0 50u 10m)"} +C {devices/opin.sym} 600 -190 0 0 {name=p7 lab=Vreg} +C {devices/gnd.sym} 130 -70 0 0 {name=l7 lab=GND} +C {devices/vsource.sym} 130 -160 0 0 {name=Vdd value="ac 1 dc Vdd sin(0 Vamp f_Vdd)"} +C {devices/lab_pin.sym} 130 -250 0 0 {name=p8 sig_type=std_logic lab=Vdd} +C {devices/lab_pin.sym} 770 -250 2 0 {name=p9 sig_type=std_logic lab=Vref} +C {devices/code_shown.sym} 110 260 0 0 {name=s1 only_toplevel=false value=".lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt"} +C {devices/code_shown.sym} 110 420 0 0 {name=s4 only_toplevel=false +value=" +.control +save all +set filetype=ascii +set units=degrees + +* DC sweep +dc Vdd 0 3 0.01 +plot v(Vdd) v(Vreg) + +* PSRR with max load +alter Vdd ac=1 +alter Vref ac=0 +ac dec 10 1 10G +plot vdb(Vreg) + +* PSRR with min load +alter IL dc=100u +ac dec 10 1 10G +plot vdb(Vreg) + +.endc +"} +C {devices/code_shown.sym} 110 340 0 0 {name=s2 only_toplevel=false value=".include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/ldo_cascode_tb_vars.spice +"} +C {sky130_fd_pr/cap_mim_m3_1.sym} 510 -130 0 0 {name=CL model=cap_mim_m3_1 W=30 L=30 MF=M_CL spiceprefix=X} +C {ldo_cascode.sym} 330 -230 0 0 {name=x1} diff --git a/xschem/ldo_folded_cascode.sch b/xschem/ldo_folded_cascode.sch new file mode 100644 index 0000000..f669fe8 --- /dev/null +++ b/xschem/ldo_folded_cascode.sch @@ -0,0 +1,99 @@ +v {xschem version=3.4.1 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 400 10 420 10 { +lab=Vdd} +N 420 -30 420 10 { +lab=Vdd} +N 420 -30 520 -30 { +lab=Vdd} +N 820 -30 820 0 { +lab=Vdd} +N 820 -50 820 0 { +lab=Vdd} +N 820 -60 820 -50 { +lab=Vdd} +N 520 -30 590 -30 { +lab=Vdd} +N 590 -30 820 -30 { +lab=Vdd} +N 820 60 820 110 { +lab=Vreg} +N 820 110 820 190 { +lab=Vreg} +N 820 190 940 190 { +lab=Vreg} +N 820 30 870 30 { +lab=Vdd} +N 80 30 100 30 { +lab=Vref} +N 870 -20 870 30 { +lab=Vdd} +N 820 -20 870 -20 { +lab=Vdd} +N 80 10 100 10 { +lab=Vfb} +N 400 110 400 130 { +lab=Vss} +N 400 130 430 130 { +lab=Vss} +N 490 130 490 160 { +lab=Vss} +N 430 130 490 130 { +lab=Vss} +N 690 30 780 30 { +lab=#net1} +N 400 30 470 30 { +lab=Vb2} +N 400 70 470 70 { +lab=Vb1} +N 560 30 560 70 { +lab=#net1} +N 560 30 690 30 { +lab=#net1} +N 490 130 650 130 { +lab=Vss} +N 650 90 650 130 { +lab=Vss} +N 680 70 700 70 { +lab=#net2} +N 760 70 820 70 { +lab=Vreg} +N 560 70 620 70 { +lab=#net1} +N 400 50 560 50 { +lab=#net1} +N 400 90 400 110 { +lab=Vss} +C {devices/iopin.sym} 490 160 1 0 {name=p4 lab=Vss} +C {devices/opin.sym} 940 190 0 0 {name=p2 lab=Vreg} +C {devices/iopin.sym} 80 30 2 0 {name=p5 lab=Vref} +C {devices/ipin.sym} 820 -60 0 0 {name=p1 lab=Vdd} +C {devices/iopin.sym} 80 10 2 0 {name=p6 lab=Vfb} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 800 30 0 0 {name=M10 +L=L_pass +W=W_pass +nf=1 +mult=M_pass +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {diff_pair_folded_cascode.sym} 250 50 0 0 {name=x1} +C {devices/iopin.sym} 470 30 0 0 {name=p7 lab=Vb2} +C {devices/iopin.sym} 470 70 0 0 {name=p8 lab=Vb1} +C {sky130_fd_pr/cap_mim_m3_1.sym} 730 70 3 0 {name=Cfb model=cap_mim_m3_1 W=10 L=10 MF=M_Cfb spiceprefix=X} +C {sky130_fd_pr/res_high_po_0p35.sym} 650 70 3 0 {name=Rfb +L=3 +model=res_high_po_0p35 +spiceprefix=X +mult=M_Rfb} diff --git a/xschem/ldo_folded_cascode.sym b/xschem/ldo_folded_cascode.sym new file mode 100644 index 0000000..f7492a6 --- /dev/null +++ b/xschem/ldo_folded_cascode.sym @@ -0,0 +1,33 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -99 -6 0 0 0.3 0.3 {} +T {@name} 135 -72 0 0 0.2 0.2 {} +L 4 -130 -60 130 -60 {} +L 4 -130 60 130 60 {} +L 4 -130 -60 -130 60 {} +L 4 130 -60 130 60 {} +B 5 -152.5 -52.5 -147.5 -47.5 {name=Vdd dir=in } +L 4 -150 -50 -130 -50 {} +T {Vdd} -125 -54 0 0 0.2 0.2 {} +B 5 147.5 -52.5 152.5 -47.5 {name=Vfb dir=inout } +L 7 130 -50 150 -50 {} +T {Vfb} 125 -54 0 1 0.2 0.2 {} +B 5 147.5 -32.5 152.5 -27.5 {name=Vb2 dir=inout } +L 7 130 -30 150 -30 {} +T {Vb2} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=Vref dir=inout } +L 7 130 -10 150 -10 {} +T {Vref} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=Vb1 dir=inout } +L 7 130 10 150 10 {} +T {Vb1} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=Vss dir=inout } +L 7 130 30 150 30 {} +T {Vss} 125 26 0 1 0.2 0.2 {} +B 5 147.5 47.5 152.5 52.5 {name=Vreg dir=out } +L 4 130 50 150 50 {} +T {Vreg} 125 46 0 1 0.2 0.2 {} diff --git a/xschem/ldo_folded_cascode_tb.sch b/xschem/ldo_folded_cascode_tb.sch new file mode 100644 index 0000000..4a5e2fe --- /dev/null +++ b/xschem/ldo_folded_cascode_tb.sch @@ -0,0 +1,377 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 690 -260 690 -250 { +lab=Vref} +N 690 -190 690 -110 { +lab=GND} +N 260 -300 430 -300 { +lab=#net1} +N 260 -240 280 -240 { +lab=GND} +N 290 20 290 40 { +lab=GND} +N 360 20 360 30 { +lab=GND} +N 290 30 360 30 { +lab=GND} +N 300 -200 370 -200 { +lab=Vreg} +N 370 -200 390 -200 { +lab=Vreg} +N -170 -150 -170 -140 { +lab=GND} +N 430 -300 480 -300 { +lab=#net1} +N -170 -200 -170 -150 { +lab=GND} +N -170 -320 -170 -260 { +lab=Vdd} +N 690 -270 690 -260 { +lab=Vref} +N 360 -80 360 -70 { +lab=#net2} +N 360 -10 360 20 { +lab=GND} +N 290 -80 290 20 { +lab=GND} +N 270 -200 300 -200 { +lab=Vreg} +N 280 -240 390 -240 { +lab=GND} +N 2030 -260 2030 -250 { +lab=Vref1} +N 2030 -190 2030 -110 { +lab=GND} +N 1470 -240 1490 -240 { +lab=GND} +N 1500 20 1500 40 { +lab=GND} +N 1570 20 1570 30 { +lab=GND} +N 1500 30 1570 30 { +lab=GND} +N 1500 -200 1570 -200 { +lab=Vreg1} +N 1570 -200 1590 -200 { +lab=Vreg1} +N 1040 -150 1040 -140 { +lab=GND} +N 1040 -200 1040 -150 { +lab=GND} +N 1040 -320 1040 -260 { +lab=Vdd1} +N 2030 -270 2030 -260 { +lab=Vref1} +N 1570 -80 1570 -70 { +lab=#net3} +N 1570 -10 1570 20 { +lab=GND} +N 1500 -80 1500 20 { +lab=GND} +N 1470 -200 1500 -200 { +lab=Vreg1} +N 1490 -240 1600 -240 { +lab=GND} +N 1570 -570 1570 -430 { +lab=probe} +N 1520 -490 1570 -490 { +lab=probe} +N 1440 -490 1460 -490 { +lab=GND} +N 1570 -640 1570 -630 { +lab=#net4} +N 1690 -360 1690 -340 { +lab=#net4} +N 290 -200 290 -180 { +lab=Vreg} +N 260 -200 270 -200 { +lab=Vreg} +N 260 -280 470 -280 { +lab=Vref} +N -170 -320 -40 -320 { +lab=Vdd} +N 1040 -320 1170 -320 { +lab=Vdd1} +N 1500 -160 1500 -140 { +lab=Vreg1} +N 2030 -280 2030 -270 { +lab=Vref1} +N 1470 -320 1690 -320 { +lab=#net4} +N 1690 -340 1690 -320 { +lab=#net4} +N 260 -320 480 -320 { +lab=Vreg} +N 1570 -640 1580 -640 { +lab=#net4} +N 1690 -640 1690 -360 { +lab=#net4} +N 1590 -640 1610 -640 { +lab=#net4} +N 1580 -640 1590 -640 { +lab=#net4} +N 360 -200 360 -180 { +lab=Vreg} +N 1500 -200 1500 -180 { +lab=Vreg1} +N 290 -180 290 -140 { +lab=Vreg} +N 360 -180 360 -140 { +lab=Vreg} +N 470 -280 690 -280 { +lab=Vref} +N 690 -280 690 -270 { +lab=Vref} +N 550 -190 550 -110 { +lab=GND} +N 360 -420 360 -200 { +lab=Vreg} +N 480 -230 480 -220 { +lab=#net5} +N 480 -160 480 -80 { +lab=GND} +N 480 -240 480 -230 { +lab=#net5} +N 1500 -180 1500 -160 { +lab=Vreg1} +N 1570 -370 1570 -140 { +lab=Vreg1} +N 1780 -260 1780 -250 { +lab=#net6} +N 1780 -190 1780 -110 { +lab=GND} +N 1710 -230 1710 -220 { +lab=#net7} +N 1710 -160 1710 -80 { +lab=GND} +N 1710 -240 1710 -230 { +lab=#net7} +N 1470 -280 2030 -280 { +lab=Vref1} +N 260 -220 260 -200 { +lab=Vreg} +N 480 -260 480 -240 { +lab=#net5} +N 260 -260 480 -260 { +lab=#net5} +N 480 -300 550 -300 { +lab=#net1} +N 550 -300 550 -250 { +lab=#net1} +N 1470 -300 1780 -300 { +lab=#net6} +N 1780 -300 1780 -260 { +lab=#net6} +N 1470 -260 1710 -260 { +lab=#net7} +N 1710 -260 1710 -240 { +lab=#net7} +N 1470 -220 1470 -200 { +lab=Vreg1} +N 360 -420 480 -420 { +lab=Vreg} +N 480 -420 480 -320 { +lab=Vreg} +N 1610 -640 1690 -640 { +lab=#net4} +C {devices/gnd.sym} 690 -110 0 0 {name=l1 lab=GND} +C {devices/vsource.sym} 690 -220 0 0 {name=Vref value=Vref} +C {devices/gnd.sym} 390 -240 3 0 {name=l4 lab=GND} +C {devices/gnd.sym} 290 40 0 0 {name=l5 lab=GND} +C {devices/isource.sym} 360 -110 0 0 {name=IL value="dc IL PULSE(10u IL 0 10n 10n 50u 100u 0)"} +C {devices/opin.sym} 390 -200 0 0 {name=p7 lab=Vreg} +C {devices/gnd.sym} -170 -140 0 0 {name=l7 lab=GND} +C {devices/vsource.sym} -170 -230 0 0 {name=Vdd value="ac 1 dc Vdd"} +C {devices/lab_pin.sym} -170 -320 0 0 {name=p8 sig_type=std_logic lab=Vdd} +C {devices/lab_pin.sym} 690 -270 2 0 {name=p9 sig_type=std_logic lab=Vref} +C {sky130_fd_pr/cap_mim_m3_1.sym} 290 -110 0 0 {name=CL model=cap_mim_m3_1 W=30 L=30 MF=M_CL spiceprefix=X} +C {devices/res.sym} 360 -40 0 0 {name=Rdummy +value=1 +footprint=1206 +device=resistor +m=1} +C {ldo_folded_cascode.sym} 110 -270 0 0 {name=x1} +C {devices/code_shown.sym} -190 90 0 0 {name=s2 only_toplevel=false value=".include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/ldo_folded_cascode_tb_vars.spice +"} +C {devices/code_shown.sym} -200 250 0 0 {name=s4 only_toplevel=false +value=" +.nodeset v(Vreg)=1.8 +.nodeset v(Vreg1)=1.8 + +.control +* high precision simulation +*.OPTIONS maxord=1 +.OPTIONS itl1=200 +.OPTIONS itl2=200 +.OPTIONS itl4=200 + +* save all voltage and current +save all +.options savecurrents +set filetype=ascii +set units=degrees + +* Loop stability +alter IL1 dc=10u +let runs=2 +let run=0 + +alter @Vprobe1[acmag]=1 +alter @Iprobe1[acmag]=0 + +dowhile run quit +ngspice-38+ done diff --git a/xschem/simulations/ldo_folded_cascode_tb.spice b/xschem/simulations/ldo_folded_cascode_tb.spice new file mode 100644 index 0000000..40d19bf --- /dev/null +++ b/xschem/simulations/ldo_folded_cascode_tb.spice @@ -0,0 +1,258 @@ +** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/ldo_folded_cascode_tb.sch +**.subckt ldo_folded_cascode_tb Vreg Vreg1 +*.opin Vreg +*.opin Vreg1 +Vref Vref GND Vref +.save i(vref) +IL Vreg net2 dc IL PULSE(10u IL 0 10n 10n 50u 100u 0) +Vdd Vdd GND ac 1 dc Vdd +.save i(vdd) +XCL Vreg GND sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=M_CL m=M_CL +Rdummy net2 GND 1 m=1 +x1 Vdd Vreg net1 Vref net5 GND Vreg ldo_folded_cascode +Vref1 Vref1 GND Vref +.save i(vref1) +IL1 Vreg1 net3 dc IL PULSE(10u IL 0 10n 10n 50u 100u 0) +Vdd2 Vdd1 GND Vdd +.save i(vdd2) +XCL1 Vreg1 GND sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=M_CL m=M_CL +Rdummy1 net3 GND 1 m=1 +x2 Vdd1 net4 net6 Vref1 net7 GND Vreg1 ldo_folded_cascode +Vprobe2 probe net4 dc 0 +.save i(vprobe2) +Vprobe1 probe Vreg1 dc 0 ac 1 +.save i(vprobe1) +Iprobe1 GND probe dc 0 ac 0 +Vb2 net1 GND Vb2 +.save i(vb2) +Vb1 net5 GND Vb1 +.save i(vb1) +Vb4 net6 GND Vb2 +.save i(vb4) +Vb3 net7 GND Vb1 +.save i(vb3) +**** begin user architecture code + +.include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/ldo_folded_cascode_tb_vars.spice + + + + +.nodeset v(Vreg)=1.8 +.nodeset v(Vreg1)=1.8 + +.control +* high precision simulation +*.OPTIONS maxord=1 +.OPTIONS itl1=200 +.OPTIONS itl2=200 +.OPTIONS itl4=200 + +* save all voltage and current +save all +.options savecurrents +set filetype=ascii +set units=degrees + +* Loop stability +alter IL1 dc=10u +let runs=2 +let run=0 + +alter @Vprobe1[acmag]=1 +alter @Iprobe1[acmag]=0 + +dowhile run Vref +) +port map ( + p => Vref , + m => GND +); + +IL : isource +generic map ( + value => dc IL PULSE(10u IL 0 10n 10n 50u 100u 0) +) +port map ( + p => Vreg , + m => net2 +); + +Vdd : vsource +generic map ( + value => ac 1 dc Vdd +) +port map ( + p => Vdd , + m => GND +); + +CL : cap_mim_m3_1 +generic map ( + model => cap_mim_m3_1 , + W => 30 , + L => 30 , + MF => M_CL , + spiceprefix => X +) +port map ( + c0 => Vreg , + c1 => GND +); + +Rdummy : res +generic map ( + value => 1 , + footprint => 1206 , + device => resistor , + m => 1 +) +port map ( + P => net2 , + M => GND +); + +x1 : ldo_folded_cascode +port map ( + Vdd => Vdd , + Vfb => net7 , + Vb3 => net1 , + Vref => Vref , + Vb2 => net10 , + Vb1 => net11 , + Vss => GND , + Vreg => Vreg +); + +Vref1 : vsource +generic map ( + value => Vref +) +port map ( + p => Vref1 , + m => GND +); + +IL1 : isource +generic map ( + value => dc IL PULSE(10u IL 0 10n 10n 50u 100u 0) +) +port map ( + p => Vreg1 , + m => net4 +); + +Vdd2 : vsource +generic map ( + value => Vdd +) +port map ( + p => Vdd1 , + m => GND +); + +CL1 : cap_mim_m3_1 +generic map ( + model => cap_mim_m3_1 , + W => 30 , + L => 30 , + MF => M_CL , + spiceprefix => X +) +port map ( + c0 => Vreg1 , + c1 => GND +); + +Rdummy1 : res +generic map ( + value => 1 , + footprint => 1206 , + device => resistor , + m => 1 +) +port map ( + P => net4 , + M => GND +); + +x2 : ldo_folded_cascode +port map ( + Vdd => Vdd1 , + Vfb => net6 , + Vb3 => net3 , + Vref => Vref1 , + Vb2 => net12 , + Vb1 => net13 , + Vss => GND , + Vreg => Vreg1 +); + +Vprobe2 : vsource +generic map ( + value => dc 0 +) +port map ( + p => probe , + m => net5 +); + +Vprobe1 : vsource +generic map ( + value => dc 0 ac 1 +) +port map ( + p => probe , + m => Vreg1 +); + +Iprobe1 : isource +generic map ( + value => dc 0 ac 0 +) +port map ( + p => GND , + m => probe +); + +Vb3 : vsource +generic map ( + value => Vb3 +) +port map ( + p => net1 , + m => GND +); + +Vb2 : vsource +generic map ( + value => Vb2 +) +port map ( + p => net10 , + m => GND +); + +Vb1 : vsource +generic map ( + value => Vb1 +) +port map ( + p => net11 , + m => GND +); + +Vb4 : vsource +generic map ( + value => Vb3 +) +port map ( + p => net3 , + m => GND +); + +Vb5 : vsource +generic map ( + value => Vb2 +) +port map ( + p => net12 , + m => GND +); + +Vb6 : vsource +generic map ( + value => Vb1 +) +port map ( + p => net13 , + m => GND +); + +R1 : res_xhigh_po_0p35 +generic map ( + L => 20 , + model => res_xhigh_po_0p35 , + spiceprefix => X , + mult => 1 +) +port map ( + M => net8 , + P => GND , + B => GND +); + +R2 : res_xhigh_po_0p35 +generic map ( + L => 20 , + model => res_xhigh_po_0p35 , + spiceprefix => X , + mult => 1 +) +port map ( + M => net7 , + P => net8 , + B => GND +); + +R3 : res_xhigh_po_0p35 +generic map ( + L => 20 , + model => res_xhigh_po_0p35 , + spiceprefix => X , + mult => 1 +) +port map ( + M => Vreg , + P => net7 , + B => GND +); + +R4 : res_xhigh_po_0p35 +generic map ( + L => 20 , + model => res_xhigh_po_0p35 , + spiceprefix => X , + mult => 1 +) +port map ( + M => net9 , + P => GND , + B => GND +); + +R5 : res_xhigh_po_0p35 +generic map ( + L => 20 , + model => res_xhigh_po_0p35 , + spiceprefix => X , + mult => 1 +) +port map ( + M => net6 , + P => net9 , + B => GND +); + +R6 : res_xhigh_po_0p35 +generic map ( + L => 20 , + model => res_xhigh_po_0p35 , + spiceprefix => X , + mult => 1 +) +port map ( + M => net5 , + P => net6 , + B => GND +); + +.include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/ldo_folded_cascode_tb_vars.spice + + +.nodeset v(Vreg)=1.8 +.nodeset v(Vreg1)=1.8 + +.control +* high precision simulation +*.OPTIONS maxord=1 +*.OPTIONS itl1=1000 +*.OPTIONS itl2=1000 +*.OPTIONS itl4=1000 + +* save all voltage and current +save all +.options savecurrents +set filetype=ascii +set units=degrees + +* Loop stability +alter IL1 dc=10u +let runs=2 +let run=0 + +alter @Vprobe1[acmag]=1 +alter @Iprobe1[acmag]=0 + +dowhile run L_pass , + W => W_pass , + nf => 1 , + mult => M_pass , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => pfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => Vreg , + G => net1 , + S => Vdd , + B => Vdd +); + +x1 : diff_pair_folded_cascode +port map ( + Vdd => Vdd , + Vb3 => Vb3 , + Vb2 => Vb2 , + vinp => Vfb , + vinm => Vref , + vout => net1 , + Vb1 => Vb1 , + Vss => Vss +); + +C1 : capa +generic map ( + m => 1 , + value => 1.0e-11 , + footprint => 1206 , + device => ceramic capacitor +) +port map ( + p => net2 , + m => Vreg +); + +R1 : res +generic map ( + value => 10000 , + footprint => 1206 , + device => resistor , + m => 1 +) +port map ( + P => net1 , + M => net2 +); + +end arch_ldo_folded_cascode ; + + +-- expanding symbol: diff_pair_folded_cascode.sym # of pins=8 +-- sym_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/diff_pair_folded_cascode.sym +-- sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/diff_pair_folded_cascode.sch +entity diff_pair_folded_cascode is +port ( + Vdd : inout std_logic ; + Vb3 : inout std_logic ; + Vb2 : inout std_logic ; + vinp : in std_logic ; + vinm : in std_logic ; + vout : out std_logic ; + Vb1 : inout std_logic ; + Vss : inout std_logic +); +end diff_pair_folded_cascode ; + +architecture arch_diff_pair_folded_cascode of diff_pair_folded_cascode is + + +signal net1 : std_logic ; +signal net2 : std_logic ; +signal net3 : std_logic ; +signal net4 : std_logic ; +begin +M1 : nfet_g5v0d10v5 +generic map ( + L => L_M1 , + W => W_M1 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => nfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net1 , + G => vinp , + S => net3 , + B => Vss +); + +M2 : nfet_g5v0d10v5 +generic map ( + L => L_M2 , + W => W_M2 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => nfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net2 , + G => vinm , + S => net3 , + B => Vss +); + +M4 : pfet_g5v0d10v5 +generic map ( + L => L_M4 , + W => W_M4 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => pfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net2 , + G => Vb2 , + S => Vdd , + B => Vdd +); + +M3 : pfet_g5v0d10v5 +generic map ( + L => L_M3 , + W => W_M3 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => pfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net1 , + G => Vb2 , + S => Vdd , + B => Vdd +); + +M9 : nfet_g5v0d10v5 +generic map ( + L => L_M9 , + W => W_M9 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => nfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net3 , + G => Vb1 , + S => Vss , + B => Vss +); + +M6 : pfet_g5v0d10v5 +generic map ( + L => L_M6 , + W => W_M6 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => pfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => vout , + G => Vb3 , + S => net2 , + B => Vdd +); + +M5 : pfet_g5v0d10v5 +generic map ( + L => L_M5 , + W => W_M5 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => pfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net4 , + G => Vb3 , + S => net1 , + B => Vdd +); + +M7 : nfet_g5v0d10v5 +generic map ( + L => L_M7 , + W => W_M7 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => nfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => net4 , + G => net4 , + S => Vss , + B => Vss +); + +M8 : nfet_g5v0d10v5 +generic map ( + L => L_M8 , + W => W_M8 , + nf => 1 , + mult => 1 , + ad => 'int((nf+1)/2) * W/nf * 0.29' , + pd => '2*int((nf+1)/2) * (W/nf + 0.29)' , + as => 'int((nf+2)/2) * W/nf * 0.29' , + ps => '2*int((nf+2)/2) * (W/nf + 0.29)' , + nrd => '0.29 / W' , + nrs => '0.29 / W' , + sa => 0 , + sb => 0 , + sd => 0 , + model => nfet_g5v0d10v5 , + spiceprefix => X +) +port map ( + D => vout , + G => net4 , + S => Vss , + B => Vss +); + +end arch_diff_pair_folded_cascode ; + diff --git a/xschem/simulations/ldo_folded_cascode_tb_dc b/xschem/simulations/ldo_folded_cascode_tb_dc new file mode 100644 index 0000000..59e4fce --- /dev/null +++ b/xschem/simulations/ldo_folded_cascode_tb_dc @@ -0,0 +1,201 @@ + 1.00000000e+00 -6.20524494e+00 + 1.01000000e+00 -6.03513307e+00 + 1.02000000e+00 -5.85808363e+00 + 1.03000000e+00 -5.67060297e+00 + 1.04000000e+00 -5.46824337e+00 + 1.05000000e+00 -5.24447198e+00 + 1.06000000e+00 -4.98933584e+00 + 1.07000000e+00 -4.68744316e+00 + 1.08000000e+00 -4.31645513e+00 + 1.09000000e+00 -3.85403085e+00 + 1.10000000e+00 -3.30832803e+00 + 1.11000000e+00 -2.73180458e+00 + 1.12000000e+00 -2.16674580e+00 + 1.13000000e+00 -1.62931846e+00 + 1.14000000e+00 -1.12737789e+00 + 1.15000000e+00 -6.68230711e-01 + 1.16000000e+00 -2.59858026e-01 + 1.17000000e+00 9.08697092e-02 + 1.18000000e+00 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b/xschem/simulations/ldo_folded_cascode_tb_line_reg_maxload new file mode 100644 index 0000000..9438aa7 --- /dev/null +++ b/xschem/simulations/ldo_folded_cascode_tb_line_reg_maxload @@ -0,0 +1,10912 @@ + 0.00000000e+00 1.97962612e+00 + 1.00000000e-10 1.97963709e+00 + 2.00000000e-10 1.97965615e+00 + 4.00000000e-10 1.97970893e+00 + 8.00000000e-10 1.97988787e+00 + 1.60000000e-09 1.98043470e+00 + 3.20000000e-09 1.98186514e+00 + 6.40000000e-09 1.98503855e+00 + 1.00000000e-08 1.98864497e+00 + 1.06400000e-08 1.98928443e+00 + 1.19200000e-08 1.99056380e+00 + 1.44800000e-08 1.99312365e+00 + 1.96000000e-08 1.99824381e+00 + 2.96000000e-08 2.00824406e+00 + 3.96000000e-08 2.01824435e+00 + 4.96000000e-08 2.02824463e+00 + 5.96000000e-08 2.03824492e+00 + 6.96000000e-08 2.04824520e+00 + 7.96000000e-08 2.05824549e+00 + 8.96000000e-08 2.06824578e+00 + 9.96000000e-08 2.07824606e+00 + 1.09600000e-07 2.08824635e+00 + 1.19600000e-07 2.09824663e+00 + 1.29600000e-07 2.10824692e+00 + 1.39600000e-07 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7.94328235e+09 2.20411621e-06 7.94328235e+09 -3.32216851e+01 + 1.00000000e+10 1.99003604e-06 1.00000000e+10 -3.76938302e+01 diff --git a/xschem/simulations/ldo_folded_cascode_tb_op b/xschem/simulations/ldo_folded_cascode_tb_op new file mode 100644 index 0000000..ef44cab --- /dev/null +++ b/xschem/simulations/ldo_folded_cascode_tb_op @@ -0,0 +1,1011 @@ +Title: ** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/ldo_folded_cascode_tb.sch +Date: Thu Jul 27 21:28:15 2023 +Plotname: Operating Point +Flags: real +No. Variables: 501 +No. Points: 1 +Variables: + 0 v(vref) voltage + 1 gmbs_m1 notype + 2 gm_m1 notype + 3 gds_m1 notype + 4 vdsat_m1 notype + 5 vth_m1 notype + 6 i(id_m1) current + 7 ibd_m1 notype + 8 ibs_m1 notype + 9 gbd_m1 notype + 10 gbs_m1 notype + 11 isub_m1 notype + 12 igidl_m1 notype + 13 igisl_m1 notype + 14 igs_m1 notype + 15 igd_m1 notype + 16 igb_m1 notype + 17 igcs_m1 notype + 18 vbs_m1 notype + 19 vgs_m1 notype + 20 vds_m1 notype + 21 cgg_m1 notype + 22 cgs_m1 notype + 23 cgd_m1 notype + 24 cbg_m1 notype + 25 cbd_m1 notype + 26 cbs_m1 notype + 27 cdg_m1 notype + 28 cdd_m1 notype + 29 cds_m1 notype + 30 csg_m1 notype + 31 csd_m1 notype + 32 css_m1 notype + 33 cgb_m1 notype + 34 cdb_m1 notype + 35 csb_m1 notype + 36 cbb_m1 notype + 37 capbd_m1 notype + 38 capbs_m1 notype + 39 qg_m1 notype + 40 qb_m1 notype + 41 qs_m1 notype + 42 qinv_m1 notype + 43 qdef_m1 notype + 44 gcrg_m1 notype + 45 gtau_m1 notype + 46 gmbs_m2 notype + 47 gm_m2 notype + 48 gds_m2 notype + 49 vdsat_m2 notype + 50 vth_m2 notype + 51 i(id_m2) current + 52 ibd_m2 notype + 53 ibs_m2 notype + 54 gbd_m2 notype + 55 gbs_m2 notype + 56 isub_m2 notype + 57 igidl_m2 notype + 58 igisl_m2 notype + 59 igs_m2 notype + 60 igd_m2 notype + 61 igb_m2 notype + 62 igcs_m2 notype + 63 vbs_m2 notype + 64 vgs_m2 notype + 65 vds_m2 notype + 66 cgg_m2 notype + 67 cgs_m2 notype + 68 cgd_m2 notype + 69 cbg_m2 notype + 70 cbd_m2 notype + 71 cbs_m2 notype + 72 cdg_m2 notype + 73 cdd_m2 notype + 74 cds_m2 notype + 75 csg_m2 notype + 76 csd_m2 notype + 77 css_m2 notype + 78 cgb_m2 notype + 79 cdb_m2 notype + 80 csb_m2 notype + 81 cbb_m2 notype + 82 capbd_m2 notype + 83 capbs_m2 notype + 84 qg_m2 notype + 85 qb_m2 notype + 86 qs_m2 notype + 87 qinv_m2 notype + 88 qdef_m2 notype + 89 gcrg_m2 notype + 90 gtau_m2 notype + 91 gmbs_m3 notype + 92 gm_m3 notype + 93 gds_m3 notype + 94 vdsat_m3 notype + 95 vth_m3 notype + 96 i(id_m3) current + 97 ibd_m3 notype + 98 ibs_m3 notype + 99 gbd_m3 notype + 100 gbs_m3 notype + 101 isub_m3 notype + 102 igidl_m3 notype + 103 igisl_m3 notype + 104 igs_m3 notype + 105 igd_m3 notype + 106 igb_m3 notype + 107 igcs_m3 notype + 108 vbs_m3 notype + 109 vgs_m3 notype + 110 vds_m3 notype + 111 cgg_m3 notype + 112 cgs_m3 notype + 113 cgd_m3 notype + 114 cbg_m3 notype + 115 cbd_m3 notype + 116 cbs_m3 notype + 117 cdg_m3 notype + 118 cdd_m3 notype + 119 cds_m3 notype + 120 csg_m3 notype + 121 csd_m3 notype + 122 css_m3 notype + 123 cgb_m3 notype + 124 cdb_m3 notype + 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174 qg_m4 notype + 175 qb_m4 notype + 176 qs_m4 notype + 177 qinv_m4 notype + 178 qdef_m4 notype + 179 gcrg_m4 notype + 180 gtau_m4 notype + 181 gmbs_m5 notype + 182 gm_m5 notype + 183 gds_m5 notype + 184 vdsat_m5 notype + 185 vth_m5 notype + 186 i(id_m5) current + 187 ibd_m5 notype + 188 ibs_m5 notype + 189 gbd_m5 notype + 190 gbs_m5 notype + 191 isub_m5 notype + 192 igidl_m5 notype + 193 igisl_m5 notype + 194 igs_m5 notype + 195 igd_m5 notype + 196 igb_m5 notype + 197 igcs_m5 notype + 198 vbs_m5 notype + 199 vgs_m5 notype + 200 vds_m5 notype + 201 cgg_m5 notype + 202 cgs_m5 notype + 203 cgd_m5 notype + 204 cbg_m5 notype + 205 cbd_m5 notype + 206 cbs_m5 notype + 207 cdg_m5 notype + 208 cdd_m5 notype + 209 cds_m5 notype + 210 csg_m5 notype + 211 csd_m5 notype + 212 css_m5 notype + 213 cgb_m5 notype + 214 cdb_m5 notype + 215 csb_m5 notype + 216 cbb_m5 notype + 217 capbd_m5 notype + 218 capbs_m5 notype + 219 qg_m5 notype + 220 qb_m5 notype + 221 qs_m5 notype + 222 qinv_m5 notype + 223 qdef_m5 notype + 224 gcrg_m5 notype + 225 gtau_m5 notype + 226 gmbs_m6 notype + 227 gm_m6 notype + 228 gds_m6 notype + 229 vdsat_m6 notype + 230 vth_m6 notype + 231 i(id_m6) current + 232 ibd_m6 notype + 233 ibs_m6 notype + 234 gbd_m6 notype + 235 gbs_m6 notype + 236 isub_m6 notype + 237 igidl_m6 notype + 238 igisl_m6 notype + 239 igs_m6 notype + 240 igd_m6 notype + 241 igb_m6 notype + 242 igcs_m6 notype + 243 vbs_m6 notype + 244 vgs_m6 notype + 245 vds_m6 notype + 246 cgg_m6 notype + 247 cgs_m6 notype + 248 cgd_m6 notype + 249 cbg_m6 notype + 250 cbd_m6 notype + 251 cbs_m6 notype + 252 cdg_m6 notype + 253 cdd_m6 notype + 254 cds_m6 notype + 255 csg_m6 notype + 256 csd_m6 notype + 257 css_m6 notype + 258 cgb_m6 notype + 259 cdb_m6 notype + 260 csb_m6 notype + 261 cbb_m6 notype + 262 capbd_m6 notype + 263 capbs_m6 notype + 264 qg_m6 notype + 265 qb_m6 notype + 266 qs_m6 notype + 267 qinv_m6 notype + 268 qdef_m6 notype + 269 gcrg_m6 notype + 270 gtau_m6 notype + 271 gmbs_m7 notype + 272 gm_m7 notype + 273 gds_m7 notype + 274 vdsat_m7 notype + 275 vth_m7 notype + 276 i(id_m7) current + 277 ibd_m7 notype + 278 ibs_m7 notype + 279 gbd_m7 notype + 280 gbs_m7 notype + 281 isub_m7 notype + 282 igidl_m7 notype + 283 igisl_m7 notype + 284 igs_m7 notype + 285 igd_m7 notype + 286 igb_m7 notype + 287 igcs_m7 notype + 288 vbs_m7 notype + 289 vgs_m7 notype + 290 vds_m7 notype + 291 cgg_m7 notype + 292 cgs_m7 notype + 293 cgd_m7 notype + 294 cbg_m7 notype + 295 cbd_m7 notype + 296 cbs_m7 notype + 297 cdg_m7 notype + 298 cdd_m7 notype + 299 cds_m7 notype + 300 csg_m7 notype + 301 csd_m7 notype + 302 css_m7 notype + 303 cgb_m7 notype + 304 cdb_m7 notype + 305 csb_m7 notype + 306 cbb_m7 notype + 307 capbd_m7 notype + 308 capbs_m7 notype + 309 qg_m7 notype + 310 qb_m7 notype + 311 qs_m7 notype + 312 qinv_m7 notype + 313 qdef_m7 notype + 314 gcrg_m7 notype + 315 gtau_m7 notype + 316 gmbs_m8 notype + 317 gm_m8 notype + 318 gds_m8 notype + 319 vdsat_m8 notype + 320 vth_m8 notype + 321 i(id_m8) current + 322 ibd_m8 notype + 323 ibs_m8 notype + 324 gbd_m8 notype + 325 gbs_m8 notype + 326 isub_m8 notype + 327 igidl_m8 notype + 328 igisl_m8 notype + 329 igs_m8 notype + 330 igd_m8 notype + 331 igb_m8 notype + 332 igcs_m8 notype + 333 vbs_m8 notype + 334 vgs_m8 notype + 335 vds_m8 notype + 336 cgg_m8 notype + 337 cgs_m8 notype + 338 cgd_m8 notype + 339 cbg_m8 notype + 340 cbd_m8 notype + 341 cbs_m8 notype + 342 cdg_m8 notype + 343 cdd_m8 notype + 344 cds_m8 notype + 345 csg_m8 notype + 346 csd_m8 notype + 347 css_m8 notype + 348 cgb_m8 notype + 349 cdb_m8 notype + 350 csb_m8 notype + 351 cbb_m8 notype + 352 capbd_m8 notype + 353 capbs_m8 notype + 354 qg_m8 notype + 355 qb_m8 notype + 356 qs_m8 notype + 357 qinv_m8 notype + 358 qdef_m8 notype + 359 gcrg_m8 notype + 360 gtau_m8 notype + 361 gmbs_m9 notype + 362 gm_m9 notype + 363 gds_m9 notype + 364 vdsat_m9 notype + 365 vth_m9 notype + 366 i(id_m9) current + 367 ibd_m9 notype + 368 ibs_m9 notype + 369 gbd_m9 notype + 370 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notype + 419 igs_m10 notype + 420 igd_m10 notype + 421 igb_m10 notype + 422 igcs_m10 notype + 423 vbs_m10 notype + 424 vgs_m10 notype + 425 vds_m10 notype + 426 cgg_m10 notype + 427 cgs_m10 notype + 428 cgd_m10 notype + 429 cbg_m10 notype + 430 cbd_m10 notype + 431 cbs_m10 notype + 432 cdg_m10 notype + 433 cdd_m10 notype + 434 cds_m10 notype + 435 csg_m10 notype + 436 csd_m10 notype + 437 css_m10 notype + 438 cgb_m10 notype + 439 cdb_m10 notype + 440 csb_m10 notype + 441 cbb_m10 notype + 442 capbd_m10 notype + 443 capbs_m10 notype + 444 qg_m10 notype + 445 qb_m10 notype + 446 qs_m10 notype + 447 qinv_m10 notype + 448 qdef_m10 notype + 449 gcrg_m10 notype + 450 gtau_m10 notype + 451 dc_vb1 notype + 452 acmag_vb1 notype + 453 acphase_vb1 notype + 454 acreal_vb1 notype + 455 acimag_vb1 notype + 456 i_vb1 notype + 457 p_vb1 notype + 458 dc_vb2 notype + 459 acmag_vb2 notype + 460 acphase_vb2 notype + 461 acreal_vb2 notype + 462 acimag_vb2 notype + 463 i_vb2 notype + 464 p_vb2 notype + 465 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3.98107171e+09 3.05788530e-03 3.98107171e+09 -4.92569721e-01 + 5.01187234e+09 3.05751847e-03 5.01187234e+09 -3.60952242e-01 + 6.30957344e+09 3.05795840e-03 6.30957344e+09 -2.54347580e-01 + 7.94328235e+09 3.05893292e-03 7.94328235e+09 -1.71960681e-01 + 1.00000000e+10 3.06016482e-03 1.00000000e+10 -1.11747775e-01 diff --git a/xschem/simulations/ldo_folded_cascode_tb_vars.spice b/xschem/simulations/ldo_folded_cascode_tb_vars.spice new file mode 100644 index 0000000..111d552 --- /dev/null +++ b/xschem/simulations/ldo_folded_cascode_tb_vars.spice @@ -0,0 +1,20 @@ +.param W_M1=12.286908000707626 L_M1=1.7774289548397064 +.param W_M2=W_M1 L_M2=L_M1 +.param W_M3=36.89915242791176 L_M3=0.5515819191932678 +.param W_M4=W_M3 L_M4=L_M3 +.param W_M5=12.32991936802864 L_M5=0.502713143825531 +.param W_M6=W_M5 L_M6=L_M5 +.param W_M7=91.40523833036423 L_M7=1.717549979686737 +.param W_M8=W_M7 L_M8=L_M7 +.param W_M9=32.27177633345127 L_M9=0.557290107011795 +.param W_pass=11.55021220445633 L_pass=0.5032543540000916 M_pass=275 +.param Vb1=0.9951694101095199 +.param Vb2=0.02523776888847351 +.param M_Rfb=1 +.param M_Cfb=9 +.param M_CL=239 +.param Vdd=2 +.param Vref=1.8 +.param IL=10m + + diff --git a/xschem/simulations/ldo_tb.spice b/xschem/simulations/ldo_tb.spice new file mode 100644 index 0000000..090c9ba --- /dev/null +++ b/xschem/simulations/ldo_tb.spice @@ -0,0 +1,524 @@ +** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/ldo_tb.sch +**.subckt ldo_tb Vreg Vreg1 +*.opin Vreg +*.opin Vreg1 +Vref Vref GND Vref +.save i(vref) +Vb net1 GND Vb +.save i(vb) +IL Vreg net2 dc IL PULSE(10u IL 0 10n 10n 50u 100u 0) +Vdd Vdd GND ac 1 dc Vdd +.save i(vdd) +x1 Vdd Vreg Vref net1 GND Vreg ldo +XCL Vreg GND sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=M_CL m=M_CL +Rdummy net2 GND 1 m=1 +Vref1 Vref1 GND Vref +.save i(vref1) +Vb1 net3 GND Vb +.save i(vb1) +IL1 Vreg1 GND IL +Vdd1 Vdd1 GND Vdd +.save i(vdd1) +x2 Vdd1 net4 Vref1 net3 GND Vreg1 ldo +XCL1 Vreg1 GND sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=M_CL m=M_CL +Vprobe2 probe net4 dc 0 +.save i(vprobe2) +Vprobe1 probe Vreg1 dc 0 ac 1 +.save i(vprobe1) +Iprobe1 GND probe dc 0 ac 0 +**** begin user architecture code + + +*.OPTIONS maxord=1 +.OPTIONS itl1=200 +.OPTIONS itl2=200 +.OPTIONS itl4=200 + +.control +* save all voltage and current +save all +.options savecurrents +set filetype=ascii +set units=degrees + +* Loop stability +alter IL1 dc=10u +let runs=2 +let run=0 + +alter @Vprobe1[acmag]=1 +alter @Iprobe1[acmag]=0 + +dowhile runcjvkU2vt$vj1-k`QG|nKQ*UXPzSw z5=F>7Prs}0_r5>-e*K>3`QzOFuwG|dZ`ay;?Y-8z);VaJJ6M`Xvhne;*&Cbb+ZZ~S zNwNt#+S>_QS{oZ$3fh|)+L;L2+_Vt1w{Q^>IcX?pX>MeH!okGYOwbvGiPgV;pzmN} z?_e+Z_q)E8xs|@Lq0I^SIn8-P2l(|@O>VL&Ia;!@iLnWtmJ}9}6h6tuCVWy@ghtKM z+To6&71YtRGrVJOZgR(gP4VFQXS)1Q+fLG!|qBQsqX{b+9JD6LU{LeQUY9Z>oJf^(VcdacQ3{6dFsD=N&7XFU| zB5=UY<%p`rj|?-{rp!m;G-!E%~q4{}ja~-8}ewWPHl^m}K{4 z(TAMh!;@sEv6VJc+2cjBW1?yv&=c|@+4a)RG%fi0lI-FR?E4rz=tr_MW8`GN(mXXa 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zAh>lu&;1Mlr!^yaYELZ+@D<2RFN;KwTVMgAB*)3knVX zXQbHYx)i+c{F}chbPFvZim}(N6%!kQ7$}H_Z%MZU9a?OS8v? zyAvs?ujEar8^%|4D|ZJ567I23{fYK8aCc2NbAx-gzEgf9IM0fL9C4ve^fEHy*WB}A z9B^0UYo#mU62lZkob$kCwbZzY`*e^Y M2wXUg<@EsEe@M;*v;Y7A literal 0 HcmV?d00001 diff --git a/xschem/simulations/test_mim_cap.spice b/xschem/simulations/test_mim_cap.spice new file mode 100644 index 0000000..762f757 --- /dev/null +++ b/xschem/simulations/test_mim_cap.spice @@ -0,0 +1,29 @@ +** sch_path: /usr/local/share/pdk/sky130A/libs.tech/xschem/sky130_tests/test_mim_cap.sch +**.subckt test_mim_cap +I1 0 G pwl 0 0 1000n 0 1010n 100n +R1 G REF 1G m=1 +I3 0 G2 pwl 0 0 1000n 0 1010n 100n +R3 G2 REF 1G m=1 +C1 G2 0 0.205p m=2 +V1 REF 0 -2 +.save i(v1) +XC2 G 0 sky130_fd_pr__cap_mim_m3_2 W=10 L=10 MF=2 m=2 +**** begin user architecture code + + +.control +save all +tran 10n 6u +plot g g2 +write test_mim_cap.raw +.endc + + + +** opencircuitdesign pdks install +.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt + + +**** end user architecture code +**.ends +.end diff --git a/xschem/simulations/two_stage.spice b/xschem/simulations/two_stage.spice new file mode 100644 index 0000000..baf3457 --- /dev/null +++ b/xschem/simulations/two_stage.spice @@ -0,0 +1,33 @@ +** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/two_stage.sch +**.subckt two_stage Vdd vinm vinp Vb vout Vss +*.iopin Vdd +*.ipin vinm +*.ipin vinp +*.iopin Vb +*.opin vout +*.iopin Vss +XM1 net1 vinp net3 Vss sky130_fd_pr__nfet_01v8 L=L_M1 W=W_M1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM2 net3 vinm net2 Vss sky130_fd_pr__nfet_01v8 L=L_M2 W=W_M2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM3 net2 net1 Vdd Vdd sky130_fd_pr__pfet_01v8 L=L_M3 W=W_M3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM4 net1 net1 Vdd Vdd sky130_fd_pr__pfet_01v8 L=L_M4 W=W_M4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM5 net3 Vb Vss Vss sky130_fd_pr__nfet_01v8 L=L_M5 W=W_M5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM6 vout net2 Vdd Vdd sky130_fd_pr__pfet_01v8 L=L_M6 W=W_M6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM7 Vss Vb vout Vss sky130_fd_pr__nfet_01v8 L=L_M7 W=W_M7 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +R1 net2 net4 Rfb m=1 +C1 net4 vout Cfb m=1 +**.ends +.end diff --git a/xschem/simulations/two_stage_tb.spice b/xschem/simulations/two_stage_tb.spice new file mode 100644 index 0000000..86148bc --- /dev/null +++ b/xschem/simulations/two_stage_tb.spice @@ -0,0 +1,431 @@ +** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/two_stage_tb.sch +**.subckt two_stage_tb vout +*.opin vout +V1 net1 GND dc Vcm ac 1 +.save i(v1) +V2 VDD GND 1.8 +.save i(v2) +V3 net2 GND Vb +.save i(v3) +C1 vout GND 2p m=1 +V4 net3 GND dc Vcm +.save i(v4) +x1 VDD vout net1 net3 net2 GND two_stage +**** begin user architecture code + +.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt + + + +.control +save all +set filetype=ascii +set units=degrees + +dc V1 0 1.8 0.01 +plot v(vout) +wrdata two_stage_tb_vout_dc v(vout) + +ac dec 10 1 1e10 +plot mag(v(vout)) +plot vdb(vout) +plot ph(v(vout)) +wrdata two_stage_tb_vout_ac mag(v(vout)) ph(v(vout)) + +op +let gmbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gm] +let gds_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vth] +let id_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[id] +let ibd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gbs] +let isub_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[isub] +let igidl_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igisl] +let igs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igs] +let igd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igd] +let igb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igb] +let igcs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vgs] +let vds_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vds] +let cgg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cdd] +let cds_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cds] +let csg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[csg] +let csd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[csd] +let css_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[css] +let cgb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cdb] +let csb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[csb] +let cbb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[capbs] +let qg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qg] +let qb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qb] +let qs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qs] +let qinv_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gtau] + +let gmbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gm] +let gds_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vth] +let id_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[id] +let ibd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gbs] +let isub_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[isub] +let igidl_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igisl] +let igs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igs] +let igd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igd] +let igb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igb] +let igcs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vgs] +let vds_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vds] +let cgg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cdd] +let cds_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cds] +let csg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[csg] +let csd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[csd] +let css_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[css] +let cgb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cdb] +let csb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[csb] +let cbb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[capbs] +let qg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qg] +let qb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qb] +let qs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qs] +let qinv_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gtau] + +let gmbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gmbs] +let gm_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gm] +let gds_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gds] +let vdsat_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vdsat] +let vth_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vth] +let id_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[id] +let ibd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[ibd] +let ibs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[ibs] +let gbd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gbd] +let gbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gbs] +let isub_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[isub] +let igidl_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igidl] +let igisl_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igisl] +let igs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igs] +let igd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igd] +let igb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igb] +let igcs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igcs] +let vbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vbs] +let vgs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vgs] +let vds_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vds] +let cgg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgg] +let cgs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgs] +let cgd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgd] +let cbg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbg] +let cbd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbd] +let cbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbs] +let cdg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cdg] +let cdd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cdd] +let cds_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cds] +let csg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[csg] +let csd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[csd] +let css_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[css] +let cgb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgb] +let cdb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cdb] +let csb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[csb] +let cbb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbb] +let capbd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[capbd] +let capbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[capbs] +let qg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qg] +let qb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qb] +let qs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qs] +let qinv_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qinv] +let qdef_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qdef] +let gcrg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gcrg] +let gtau_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gtau] + +let gmbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gmbs] +let gm_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gm] +let gds_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gds] +let vdsat_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vdsat] +let vth_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vth] +let id_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[id] +let ibd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[ibd] +let ibs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[ibs] +let gbd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gbd] +let gbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gbs] +let isub_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[isub] +let igidl_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igidl] +let igisl_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igisl] +let igs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igs] +let igd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igd] +let igb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igb] +let igcs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igcs] +let vbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vbs] +let vgs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vgs] +let vds_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vds] +let cgg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgg] +let cgs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgs] +let cgd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgd] +let cbg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbg] +let cbd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbd] +let cbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbs] +let cdg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cdg] +let cdd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cdd] +let cds_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cds] +let csg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[csg] +let csd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[csd] +let css_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[css] +let cgb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgb] +let cdb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cdb] +let csb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[csb] +let cbb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbb] +let capbd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[capbd] +let capbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[capbs] +let qg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qg] +let qb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qb] +let qs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qs] +let qinv_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qinv] +let qdef_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qdef] +let gcrg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gcrg] +let gtau_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gtau] + +let gmbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gm] +let gds_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vth] +let id_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[id] +let ibd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gbs] +let isub_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[isub] +let igidl_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igisl] +let igs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igs] +let igd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igd] +let igb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igb] +let igcs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vgs] +let vds_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vds] +let cgg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cdd] +let cds_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cds] +let csg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[csg] +let csd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[csd] +let css_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[css] +let cgb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cdb] +let csb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[csb] +let cbb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[capbs] +let qg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qg] +let qb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qb] +let qs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qs] +let qinv_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gtau] + +let gmbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gmbs] +let gm_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gm] +let gds_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gds] +let vdsat_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vdsat] +let vth_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vth] +let id_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[id] +let ibd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[ibd] +let ibs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[ibs] +let gbd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gbd] +let gbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gbs] +let isub_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[isub] +let igidl_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igidl] +let igisl_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igisl] +let igs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igs] +let igd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igd] +let igb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igb] +let igcs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igcs] +let vbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vbs] +let vgs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vgs] +let vds_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vds] +let cgg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgg] +let cgs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgs] +let cgd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgd] +let cbg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbg] +let cbd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbd] +let cbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbs] +let cdg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cdg] +let cdd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cdd] +let cds_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cds] +let csg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[csg] +let csd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[csd] +let css_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[css] +let cgb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgb] +let cdb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cdb] +let csb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[csb] +let cbb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbb] +let capbd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[capbd] +let capbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[capbs] +let qg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qg] +let qb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qb] +let qs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qs] +let qinv_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qinv] +let qdef_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qdef] +let gcrg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gcrg] +let gtau_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gtau] + +let gmbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gm] +let gds_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vth] +let id_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[id] +let ibd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gbs] +let isub_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[isub] +let igidl_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igisl] +let igs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igs] +let igd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igd] +let igb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igb] +let igcs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vgs] +let vds_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vds] +let cgg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cdd] +let cds_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cds] +let csg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[csg] +let csd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[csd] +let css_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[css] +let cgb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cdb] +let csb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[csb] +let cbb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[capbs] +let qg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qg] +let qb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qb] +let qs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qs] +let qinv_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gtau] + +print gmbs_M1 gm_M1 gds_M1 +write two_stage_tb_op gmbs_M1 gm_M1 gds_M1 vdsat_M1 vth_M1 id_M1 ibd_M1 ibs_M1 gbd_M1 gbs_M1 isub_M1 ++ igidl_M1 igisl_M1 igs_M1 igd_M1 igb_M1 igcs_M1 vbs_M1 vgs_M1 vds_M1 cgg_M1 cgs_M1 cgd_M1 cbg_M1 cbd_M1 ++ cbs_M1 cdg_M1 cdd_M1 cds_M1 csg_M1 csd_M1 css_M1 cgb_M1 cdb_M1 csb_M1 cbb_M1 capbd_M1 capbs_M1 qg_M1 qb_M1 ++ qs_M1 qinv_M1 qdef_M1 gcrg_M1 gtau_M1 gmbs_M2 gm_M2 gds_M2 vdsat_M2 vth_M2 id_M2 ibd_M2 ibs_M2 gbd_M2 ++ gbs_M2 isub_M2 igidl_M2 igisl_M2 igs_M2 igd_M2 igb_M2 igcs_M2 vbs_M2 vgs_M2 vds_M2 cgg_M2 cgs_M2 cgd_M2 ++ cbg_M2 cbd_M2 cbs_M2 cdg_M2 cdd_M2 cds_M2 csg_M2 csd_M2 css_M2 cgb_M2 cdb_M2 csb_M2 cbb_M2 capbd_M2 ++ capbs_M2 qg_M2 qb_M2 qs_M2 qinv_M2 qdef_M2 gcrg_M2 gtau_M2 gmbs_M3 gm_M3 gds_M3 vdsat_M3 vth_M3 id_M3 ibd_M3 ++ ibs_M3 gbd_M3 gbs_M3 isub_M3 igidl_M3 igisl_M3 igs_M3 igd_M3 igb_M3 igcs_M3 vbs_M3 vgs_M3 vds_M3 cgg_M3 ++ cgs_M3 cgd_M3 cbg_M3 cbd_M3 cbs_M3 cdg_M3 cdd_M3 cds_M3 csg_M3 csd_M3 css_M3 cgb_M3 cdb_M3 csb_M3 cbb_M3 ++ capbd_M3 capbs_M3 qg_M3 qb_M3 qs_M3 qinv_M3 qdef_M3 gcrg_M3 gtau_M3 gmbs_M4 gm_M4 gds_M4 vdsat_M4 vth_M4 ++ id_M4 ibd_M4 ibs_M4 gbd_M4 gbs_M4 isub_M4 igidl_M4 igisl_M4 igs_M4 igd_M4 igb_M4 igcs_M4 vbs_M4 vgs_M4 ++ vds_M4 cgg_M4 cgs_M4 cgd_M4 cbg_M4 cbd_M4 cbs_M4 cdg_M4 cdd_M4 cds_M4 csg_M4 csd_M4 css_M4 cgb_M4 cdb_M4 ++ csb_M4 cbb_M4 capbd_M4 capbs_M4 qg_M4 qb_M4 qs_M4 qinv_M4 qdef_M4 gcrg_M4 gtau_M4 gmbs_M5 gm_M5 gds_M5 ++ vdsat_M5 vth_M5 id_M5 ibd_M5 ibs_M5 gbd_M5 gbs_M5 isub_M5 igidl_M5 igisl_M5 igs_M5 igd_M5 igb_M5 igcs_M5 ++ vbs_M5 vgs_M5 vds_M5 cgg_M5 cgs_M5 cgd_M5 cbg_M5 cbd_M5 cbs_M5 cdg_M5 cdd_M5 cds_M5 csg_M5 csd_M5 css_M5 ++ cgb_M5 cdb_M5 csb_M5 cbb_M5 capbd_M5 capbs_M5 qg_M5 qb_M5 qs_M5 qinv_M5 qdef_M5 gcrg_M5 gtau_M5 gmbs_M6 ++ gm_M6 gds_M6 vdsat_M6 vth_M6 id_M6 ibd_M6 ibs_M6 gbd_M6 gbs_M6 isub_M6 igidl_M6 igisl_M6 igs_M6 igd_M6 ++ igb_M6 igcs_M6 vbs_M6 vgs_M6 vds_M6 cgg_M6 cgs_M6 cgd_M6 cbg_M6 cbd_M6 cbs_M6 cdg_M6 cdd_M6 cds_M6 csg_M6 ++ csd_M6 css_M6 cgb_M6 cdb_M6 csb_M6 cbb_M6 capbd_M6 capbs_M6 qg_M6 qb_M6 qs_M6 qinv_M6 qdef_M6 gcrg_M6 ++ gtau_M6 gmbs_M7 gm_M7 gds_M7 vdsat_M7 vth_M7 id_M7 ibd_M7 ibs_M7 gbd_M7 gbs_M7 isub_M7 igidl_M7 igisl_M7 ++ igs_M7 igd_M7 igb_M7 igcs_M7 vbs_M7 vgs_M7 vds_M7 cgg_M7 cgs_M7 cgd_M7 cbg_M7 cbd_M7 cbs_M7 cdg_M7 cdd_M7 ++ cds_M7 csg_M7 csd_M7 css_M7 cgb_M7 cdb_M7 csb_M7 cbb_M7 capbd_M7 capbs_M7 qg_M7 qb_M7 qs_M7 qinv_M7 ++ qdef_M7 gcrg_M7 gtau_M7 + + +.endc + + + +.include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/two_stage_tb_vars.spice + + +**** end user architecture code +**.ends + +* expanding symbol: two_stage.sym # of pins=6 +** sym_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/two_stage.sym +** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/two_stage.sch +.subckt two_stage Vdd vout vinp vinm Vb Vss +*.iopin Vdd +*.ipin vinm +*.ipin vinp +*.iopin Vb +*.opin vout +*.iopin Vss +XM1 net1 vinp net3 Vss sky130_fd_pr__nfet_01v8 L=L_M1 W=W_M1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM2 net3 vinm net2 Vss sky130_fd_pr__nfet_01v8 L=L_M2 W=W_M2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM3 net2 net1 Vdd Vdd sky130_fd_pr__pfet_01v8 L=L_M3 W=W_M3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM4 net1 net1 Vdd Vdd sky130_fd_pr__pfet_01v8 L=L_M4 W=W_M4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM5 net3 Vb Vss Vss sky130_fd_pr__nfet_01v8 L=L_M5 W=W_M5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM6 vout net2 Vdd Vdd sky130_fd_pr__pfet_01v8 L=L_M6 W=W_M6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +XM7 Vss Vb vout Vss sky130_fd_pr__nfet_01v8 L=L_M7 W=W_M7 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' ++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' ++ sa=0 sb=0 sd=0 mult=1 m=1 +R1 net2 net4 Rfb m=1 +C1 net4 vout Cfb m=1 +.ends + +.GLOBAL GND +.GLOBAL VDD +.end diff --git a/xschem/simulations/two_stage_tb_op b/xschem/simulations/two_stage_tb_op new file mode 100644 index 0000000..ebca581 --- /dev/null +++ b/xschem/simulations/two_stage_tb_op @@ -0,0 +1,641 @@ +Title: ** sch_path: /fs1/eecg/tcc/lizongh2/sky130_ldo/xschem/two_stage_tb.sch +Date: Mon Dec 5 20:35:01 2022 +Plotname: Operating Point +Flags: real +No. Variables: 316 +No. Points: 1 +Variables: + 0 v(net1) voltage + 1 gmbs_m1 notype + 2 gm_m1 notype + 3 gds_m1 notype + 4 vdsat_m1 notype + 5 vth_m1 notype + 6 id_m1 notype + 7 ibd_m1 notype + 8 ibs_m1 notype + 9 gbd_m1 notype + 10 gbs_m1 notype + 11 isub_m1 notype + 12 igidl_m1 notype + 13 igisl_m1 notype + 14 igs_m1 notype + 15 igd_m1 notype + 16 igb_m1 notype + 17 igcs_m1 notype + 18 vbs_m1 notype + 19 vgs_m1 notype + 20 vds_m1 notype + 21 cgg_m1 notype + 22 cgs_m1 notype + 23 cgd_m1 notype + 24 cbg_m1 notype + 25 cbd_m1 notype + 26 cbs_m1 notype + 27 cdg_m1 notype + 28 cdd_m1 notype + 29 cds_m1 notype + 30 csg_m1 notype + 31 csd_m1 notype + 32 css_m1 notype + 33 cgb_m1 notype + 34 cdb_m1 notype + 35 csb_m1 notype + 36 cbb_m1 notype + 37 capbd_m1 notype + 38 capbs_m1 notype + 39 qg_m1 notype + 40 qb_m1 notype + 41 qs_m1 notype + 42 qinv_m1 notype + 43 qdef_m1 notype + 44 gcrg_m1 notype + 45 gtau_m1 notype + 46 gmbs_m2 notype + 47 gm_m2 notype + 48 gds_m2 notype + 49 vdsat_m2 notype + 50 vth_m2 notype + 51 id_m2 notype + 52 ibd_m2 notype + 53 ibs_m2 notype + 54 gbd_m2 notype + 55 gbs_m2 notype + 56 isub_m2 notype + 57 igidl_m2 notype + 58 igisl_m2 notype + 59 igs_m2 notype + 60 igd_m2 notype + 61 igb_m2 notype + 62 igcs_m2 notype + 63 vbs_m2 notype + 64 vgs_m2 notype + 65 vds_m2 notype + 66 cgg_m2 notype + 67 cgs_m2 notype + 68 cgd_m2 notype + 69 cbg_m2 notype + 70 cbd_m2 notype + 71 cbs_m2 notype + 72 cdg_m2 notype + 73 cdd_m2 notype + 74 cds_m2 notype + 75 csg_m2 notype + 76 csd_m2 notype + 77 css_m2 notype + 78 cgb_m2 notype + 79 cdb_m2 notype + 80 csb_m2 notype + 81 cbb_m2 notype + 82 capbd_m2 notype + 83 capbs_m2 notype + 84 qg_m2 notype + 85 qb_m2 notype + 86 qs_m2 notype + 87 qinv_m2 notype + 88 qdef_m2 notype + 89 gcrg_m2 notype + 90 gtau_m2 notype + 91 gmbs_m3 notype + 92 gm_m3 notype + 93 gds_m3 notype + 94 vdsat_m3 notype + 95 vth_m3 notype + 96 id_m3 notype + 97 ibd_m3 notype + 98 ibs_m3 notype + 99 gbd_m3 notype + 100 gbs_m3 notype + 101 isub_m3 notype + 102 igidl_m3 notype + 103 igisl_m3 notype + 104 igs_m3 notype + 105 igd_m3 notype + 106 igb_m3 notype + 107 igcs_m3 notype + 108 vbs_m3 notype + 109 vgs_m3 notype + 110 vds_m3 notype + 111 cgg_m3 notype + 112 cgs_m3 notype + 113 cgd_m3 notype + 114 cbg_m3 notype + 115 cbd_m3 notype + 116 cbs_m3 notype + 117 cdg_m3 notype + 118 cdd_m3 notype + 119 cds_m3 notype + 120 csg_m3 notype + 121 csd_m3 notype + 122 css_m3 notype + 123 cgb_m3 notype + 124 cdb_m3 notype + 125 csb_m3 notype + 126 cbb_m3 notype + 127 capbd_m3 notype + 128 capbs_m3 notype + 129 qg_m3 notype + 130 qb_m3 notype + 131 qs_m3 notype + 132 qinv_m3 notype + 133 qdef_m3 notype + 134 gcrg_m3 notype + 135 gtau_m3 notype + 136 gmbs_m4 notype + 137 gm_m4 notype + 138 gds_m4 notype + 139 vdsat_m4 notype + 140 vth_m4 notype + 141 id_m4 notype + 142 ibd_m4 notype + 143 ibs_m4 notype + 144 gbd_m4 notype + 145 gbs_m4 notype + 146 isub_m4 notype + 147 igidl_m4 notype + 148 igisl_m4 notype + 149 igs_m4 notype + 150 igd_m4 notype + 151 igb_m4 notype + 152 igcs_m4 notype + 153 vbs_m4 notype + 154 vgs_m4 notype + 155 vds_m4 notype + 156 cgg_m4 notype + 157 cgs_m4 notype + 158 cgd_m4 notype + 159 cbg_m4 notype + 160 cbd_m4 notype + 161 cbs_m4 notype + 162 cdg_m4 notype + 163 cdd_m4 notype + 164 cds_m4 notype + 165 csg_m4 notype + 166 csd_m4 notype + 167 css_m4 notype + 168 cgb_m4 notype + 169 cdb_m4 notype + 170 csb_m4 notype + 171 cbb_m4 notype + 172 capbd_m4 notype + 173 capbs_m4 notype + 174 qg_m4 notype + 175 qb_m4 notype + 176 qs_m4 notype + 177 qinv_m4 notype + 178 qdef_m4 notype + 179 gcrg_m4 notype + 180 gtau_m4 notype + 181 gmbs_m5 notype + 182 gm_m5 notype + 183 gds_m5 notype + 184 vdsat_m5 notype + 185 vth_m5 notype + 186 id_m5 notype + 187 ibd_m5 notype + 188 ibs_m5 notype + 189 gbd_m5 notype + 190 gbs_m5 notype + 191 isub_m5 notype + 192 igidl_m5 notype + 193 igisl_m5 notype + 194 igs_m5 notype + 195 igd_m5 notype + 196 igb_m5 notype + 197 igcs_m5 notype + 198 vbs_m5 notype + 199 vgs_m5 notype + 200 vds_m5 notype + 201 cgg_m5 notype + 202 cgs_m5 notype + 203 cgd_m5 notype + 204 cbg_m5 notype + 205 cbd_m5 notype + 206 cbs_m5 notype + 207 cdg_m5 notype + 208 cdd_m5 notype + 209 cds_m5 notype + 210 csg_m5 notype + 211 csd_m5 notype + 212 css_m5 notype + 213 cgb_m5 notype + 214 cdb_m5 notype + 215 csb_m5 notype + 216 cbb_m5 notype + 217 capbd_m5 notype + 218 capbs_m5 notype + 219 qg_m5 notype + 220 qb_m5 notype + 221 qs_m5 notype + 222 qinv_m5 notype + 223 qdef_m5 notype + 224 gcrg_m5 notype + 225 gtau_m5 notype + 226 gmbs_m6 notype + 227 gm_m6 notype + 228 gds_m6 notype + 229 vdsat_m6 notype + 230 vth_m6 notype + 231 id_m6 notype + 232 ibd_m6 notype + 233 ibs_m6 notype + 234 gbd_m6 notype + 235 gbs_m6 notype + 236 isub_m6 notype + 237 igidl_m6 notype + 238 igisl_m6 notype + 239 igs_m6 notype + 240 igd_m6 notype + 241 igb_m6 notype + 242 igcs_m6 notype + 243 vbs_m6 notype + 244 vgs_m6 notype + 245 vds_m6 notype + 246 cgg_m6 notype + 247 cgs_m6 notype + 248 cgd_m6 notype + 249 cbg_m6 notype + 250 cbd_m6 notype + 251 cbs_m6 notype + 252 cdg_m6 notype + 253 cdd_m6 notype + 254 cds_m6 notype + 255 csg_m6 notype + 256 csd_m6 notype + 257 css_m6 notype + 258 cgb_m6 notype + 259 cdb_m6 notype + 260 csb_m6 notype + 261 cbb_m6 notype + 262 capbd_m6 notype + 263 capbs_m6 notype + 264 qg_m6 notype + 265 qb_m6 notype + 266 qs_m6 notype + 267 qinv_m6 notype + 268 qdef_m6 notype + 269 gcrg_m6 notype + 270 gtau_m6 notype + 271 gmbs_m7 notype + 272 gm_m7 notype + 273 gds_m7 notype + 274 vdsat_m7 notype + 275 vth_m7 notype + 276 id_m7 notype + 277 ibd_m7 notype + 278 ibs_m7 notype + 279 gbd_m7 notype + 280 gbs_m7 notype + 281 isub_m7 notype + 282 igidl_m7 notype + 283 igisl_m7 notype + 284 igs_m7 notype + 285 igd_m7 notype + 286 igb_m7 notype + 287 igcs_m7 notype + 288 vbs_m7 notype + 289 vgs_m7 notype + 290 vds_m7 notype + 291 cgg_m7 notype + 292 cgs_m7 notype + 293 cgd_m7 notype + 294 cbg_m7 notype + 295 cbd_m7 notype + 296 cbs_m7 notype + 297 cdg_m7 notype + 298 cdd_m7 notype + 299 cds_m7 notype + 300 csg_m7 notype + 301 csd_m7 notype + 302 css_m7 notype + 303 cgb_m7 notype + 304 cdb_m7 notype + 305 csb_m7 notype + 306 cbb_m7 notype + 307 capbd_m7 notype + 308 capbs_m7 notype + 309 qg_m7 notype + 310 qb_m7 notype + 311 qs_m7 notype + 312 qinv_m7 notype + 313 qdef_m7 notype + 314 gcrg_m7 notype + 315 gtau_m7 notype +Values: + 0 7.723338312726121e-01 + 2.141097459555219e-04 + 9.284282723969212e-04 + 7.953271504472411e-06 + 1.461436174764639e-01 + 5.598394893972528e-01 + 7.543231132900733e-05 + -4.791353729866920e-13 + -9.253371682237202e-14 + 1.000002490002458e-12 + 1.211643411967278e-12 + 2.768151687576077e-20 + 0.000000000000000e+00 + 0.000000000000000e+00 + 0.000000000000000e+00 + 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8.949356570308050e-14 + -4.044330510768772e-15 + -3.152006083601405e-14 + -3.152006104798086e-14 + 6.708445239476369e-14 + 8.740743479005839e-15 + 8.740743377380464e-15 + 2.023615295778441e-13 + -9.468994103165117e-14 + -5.383579480609112e-14 + 0.000000000000000e+00 + 0.000000000000000e+00 + 0.000000000000000e+00 + 0.000000000000000e+00 + diff --git a/xschem/simulations/two_stage_tb_vars.spice b/xschem/simulations/two_stage_tb_vars.spice new file mode 100644 index 0000000..bcbc1a0 --- /dev/null +++ b/xschem/simulations/two_stage_tb_vars.spice @@ -0,0 +1,9 @@ +.param W_M1=42.118154872134696 L_M1=1.7111959807328843 +.param W_M2=42.118154872134696 L_M2=1.7111959807328843 +.param W_M3=51.286530610841616 L_M3=2.5157359362276224 +.param W_M4=51.286530610841616 L_M4=2.5157359362276224 +.param W_M5=29.075754347959045 L_M5=1.6114024596504857 +.param W_M6=57.71043983361096 L_M6=4.794129763236112 +.param W_M7=13.16 L_M7=2.469795719604986 +.param Rfb=2595.4894470684503 Cfb=1.837914159484712e-12 +.param Vcm=0.7723338312726121 Vb=0.854368816484408 diff --git a/xschem/simulations/two_stage_tb_vout_ac b/xschem/simulations/two_stage_tb_vout_ac new file mode 100644 index 0000000..c2c80aa --- /dev/null +++ b/xschem/simulations/two_stage_tb_vout_ac @@ -0,0 +1,101 @@ + 1.00000000e+00 8.77330339e-11 1.00000000e+00 8.99985146e+01 + 1.25892541e+00 1.10449346e-10 1.25892541e+00 8.99987711e+01 + 1.58489319e+00 1.39047488e-10 1.58489319e+00 8.99989621e+01 + 1.99526231e+00 1.75050416e-10 1.99526231e+00 8.99990979e+01 + 2.51188643e+00 2.20375417e-10 2.51188643e+00 8.99991856e+01 + 3.16227766e+00 2.77436213e-10 3.16227766e+00 8.99992299e+01 + 3.98107171e+00 3.49271499e-10 3.98107171e+00 8.99992333e+01 + 5.01187234e+00 4.39706766e-10 5.01187234e+00 8.99991958e+01 + 6.30957344e+00 5.53558021e-10 6.30957344e+00 8.99991154e+01 + 7.94328235e+00 6.96888259e-10 7.94328235e+00 8.99989880e+01 + 1.00000000e+01 8.77330339e-10 1.00000000e+01 8.99988067e+01 + 1.25892541e+01 1.10449346e-09 1.25892541e+01 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1.25892541e+09 1.68868486e+00 + 1.58489319e+09 2.96994576e-03 1.58489319e+09 2.24914136e+00 + 1.99526231e+09 2.89652864e-03 1.99526231e+09 3.24057524e+00 + 2.51188643e+09 2.85549235e-03 2.51188643e+09 4.57023330e+00 + 3.16227766e+09 2.83895475e-03 3.16227766e+09 6.21268422e+00 + 3.98107171e+09 2.84356407e-03 3.98107171e+09 8.18240044e+00 + 5.01187234e+09 2.86990562e-03 5.01187234e+09 1.05093152e+01 + 6.30957344e+09 2.92233133e-03 6.30957344e+09 1.32141531e+01 + 7.94328235e+09 3.00902738e-03 7.94328235e+09 1.62799737e+01 + 1.00000000e+10 3.14201354e-03 1.00000000e+10 1.96203379e+01 diff --git a/xschem/simulations/two_stage_tb_vout_dc b/xschem/simulations/two_stage_tb_vout_dc new file mode 100644 index 0000000..2ce6a1b --- /dev/null +++ b/xschem/simulations/two_stage_tb_vout_dc @@ -0,0 +1,181 @@ + 0.00000000e+00 1.18682670e-08 + 1.00000000e-02 1.21696351e-08 + 2.00000000e-02 1.56546957e-08 + 3.00000000e-02 1.63103680e-08 + 4.00000000e-02 1.67794420e-08 + 5.00000000e-02 1.70622225e-08 + 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-2.78093044e-07 7.66000000e-01 7.66000000e-01 - 7.67000000e-01 -2.82879650e-07 7.67000000e-01 7.67000000e-01 - 7.68000000e-01 -2.87745826e-07 7.68000000e-01 7.68000000e-01 - 7.69000000e-01 -2.92692776e-07 7.69000000e-01 7.69000000e-01 - 7.70000000e-01 -2.97721660e-07 7.70000000e-01 7.70000000e-01 - 7.71000000e-01 -3.02833688e-07 7.71000000e-01 7.71000000e-01 - 7.72000000e-01 -3.08030053e-07 7.72000000e-01 7.72000000e-01 - 7.73000000e-01 -3.13311974e-07 7.73000000e-01 7.73000000e-01 - 7.74000000e-01 -3.18680710e-07 7.74000000e-01 7.74000000e-01 - 7.75000000e-01 -3.24137468e-07 7.75000000e-01 7.75000000e-01 - 7.76000000e-01 -3.29683509e-07 7.76000000e-01 7.76000000e-01 - 7.77000000e-01 -3.35320078e-07 7.77000000e-01 7.77000000e-01 - 7.78000000e-01 -3.41048451e-07 7.78000000e-01 7.78000000e-01 - 7.79000000e-01 -3.46869908e-07 7.79000000e-01 7.79000000e-01 - 7.80000000e-01 -3.52785731e-07 7.80000000e-01 7.80000000e-01 - 7.81000000e-01 -3.58797218e-07 7.81000000e-01 7.81000000e-01 - 7.82000000e-01 -3.64905663e-07 7.82000000e-01 7.82000000e-01 - 7.83000000e-01 -3.71112381e-07 7.83000000e-01 7.83000000e-01 - 7.84000000e-01 -3.77418703e-07 7.84000000e-01 7.84000000e-01 - 7.85000000e-01 -3.83825919e-07 7.85000000e-01 7.85000000e-01 - 7.86000000e-01 -3.90335390e-07 7.86000000e-01 7.86000000e-01 - 7.87000000e-01 -3.96948455e-07 7.87000000e-01 7.87000000e-01 - 7.88000000e-01 -4.03666461e-07 7.88000000e-01 7.88000000e-01 - 7.89000000e-01 -4.10490750e-07 7.89000000e-01 7.89000000e-01 - 7.90000000e-01 -4.17422681e-07 7.90000000e-01 7.90000000e-01 - 7.91000000e-01 -4.24463629e-07 7.91000000e-01 7.91000000e-01 - 7.92000000e-01 -4.31614946e-07 7.92000000e-01 7.92000000e-01 - 7.93000000e-01 -4.38878017e-07 7.93000000e-01 7.93000000e-01 - 7.94000000e-01 -4.46254218e-07 7.94000000e-01 7.94000000e-01 - 7.95000000e-01 -4.53744916e-07 7.95000000e-01 7.95000000e-01 - 7.96000000e-01 -4.61351506e-07 7.96000000e-01 7.96000000e-01 - 7.97000000e-01 -4.69075369e-07 7.97000000e-01 7.97000000e-01 - 7.98000000e-01 -4.76917893e-07 7.98000000e-01 7.98000000e-01 - 7.99000000e-01 -4.84880471e-07 7.99000000e-01 7.99000000e-01 - 8.00000000e-01 -4.92964482e-07 8.00000000e-01 8.00000000e-01 diff --git a/xschem/test_gm_id.sch b/xschem/test_gm_id.sch new file mode 100644 index 0000000..70b70da --- /dev/null +++ b/xschem/test_gm_id.sch @@ -0,0 +1,105 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 320 -210 320 -160 { +lab=GND} +N 320 -320 360 -320 { +lab=GND} +N 360 -320 360 -270 { +lab=GND} +N 320 -270 360 -270 { +lab=GND} +N 250 -320 280 -320 { +lab=#net1} +N 320 -450 320 -410 { +lab=#net2} +N 320 -450 440 -450 { +lab=#net2} +N 440 -450 440 -410 { +lab=#net2} +N 440 -350 440 -320 { +lab=GND} +N 320 -410 320 -350 { +lab=#net2} +N 200 -190 200 -160 { +lab=GND} +N 320 -290 320 -210 { +lab=GND} +N 200 -320 200 -250 { +lab=#net1} +N 200 -320 250 -320 { +lab=#net1} +C {devices/gnd.sym} 320 -160 0 0 {name=l13 lab=GND} +C {devices/vsource.sym} 440 -380 0 0 {name=VDD value=VD} +C {devices/gnd.sym} 440 -320 0 0 {name=l1 lab=GND} +C {sky130_fd_pr/corner.sym} 0 -450 0 0 {name=CORNER only_toplevel=false corner=tt} +C {devices/code_shown.sym} 570 -450 0 0 {name=s1 only_toplevel=false +value=" + +* some initial params +.param W_sweep=10 +.param L_sweep=0.18 +.param ID=10u +.param VD=1.8 +.param VG=1 +.param M_sweep=1 + +* high precision simulation +.options savecurrents +.OPTIONS maxord=1 +.OPTIONS itl1=200 +.OPTIONS itl2=200 +.OPTIONS itl4=200 + +.control +* save all voltage and current +save all +set filetype=ascii +set units=degrees + +* save transistor gm +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] +save @m.xm1.msky130_fd_pr__nfet_01v8_lvt[id] +let gm=@m.xm1.msky130_fd_pr__nfet_01v8_lvt[gm] +let gds=@m.xm1.msky130_fd_pr__nfet_01v8_lvt[gds] +let id=@m.xm1.msky130_fd_pr__nfet_01v8_lvt[id] + +* parameteric sweep +dc VGS 0 2 0.2 +plot gm +alterparam L_sweep=0.36 +reset +dc VGS 0 2 0.2 +plot gm +alterparam L_sweep=0.5 +reset +dc VGS 0 2 0.2 +plot gm +alterparam L_sweep=1 +reset +dc VGS 0 2 0.2 +plot gm + +.endc +"} +C {devices/vsource.sym} 200 -220 0 0 {name=VGS value=VG} +C {devices/gnd.sym} 200 -160 0 0 {name=l2 lab=GND} +C {sky130_fd_pr/nfet_01v8_lvt.sym} 300 -320 0 0 {name=M1 +L=L_sweep +W=W_sweep +nf=1 +mult=M_sweep +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8_lvt +spiceprefix=X +} diff --git a/xschem/threshold_test_tb.spice b/xschem/threshold_test_tb.spice deleted file mode 100644 index 3e9804c..0000000 --- a/xschem/threshold_test_tb.spice +++ /dev/null @@ -1,46 +0,0 @@ -*--------------------------------------------------------------------------- -* SPDX-FileCopyrightText: 2020 Efabless Corporation -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* https://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -* SPDX-License-Identifier: Apache-2.0 -*--------------------------------------------------------------------------- -* Threshold test for POR circuit -* Determine gate voltage at which the HV NFET draws 240nA nominal -* -* Result: 0.7575V -*------------------------------------------------------------------- - -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt - -*---------------------------- -* Testbench circuit -*---------------------------- -Rtest vdda mir1 1MEG -Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 - -Vgate vin vss DC=0 -Vpwr vdda vss DC=3.3 -Rgnd vss 0 0.1 - -*---------------------------- -* Testbench control -*---------------------------- -.control -* DC sweep from 0.7 to 0.8V -dc Vgate 0.7 0.8 0.001 -wrdata test.data Vpwr#branch vin - -.endc - -.end - diff --git a/xschem/two_stage.sch b/xschem/two_stage.sch new file mode 100644 index 0000000..26b5906 --- /dev/null +++ b/xschem/two_stage.sch @@ -0,0 +1,241 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 310 -180 410 -180 { +lab=#net1} +N 270 -150 270 -10 { +lab=#net1} +N 450 -150 450 -10 { +lab=#net2} +N 270 -240 270 -210 { +lab=Vdd} +N 450 -240 450 -210 { +lab=Vdd} +N 270 -240 450 -240 { +lab=Vdd} +N 360 -260 360 -240 { +lab=Vdd} +N 270 -120 340 -120 { +lab=#net1} +N 340 -180 340 -120 { +lab=#net1} +N 270 50 270 80 { +lab=#net3} +N 270 80 450 80 { +lab=#net3} +N 450 50 450 80 { +lab=#net3} +N 360 80 360 110 { +lab=#net3} +N 360 170 360 190 { +lab=Vss} +N 270 20 450 20 { +lab=Vss} +N 360 20 360 30 { +lab=Vss} +N 250 -180 270 -180 { +lab=Vdd} +N 250 -220 250 -180 { +lab=Vdd} +N 250 -220 270 -220 { +lab=Vdd} +N 450 -180 470 -180 { +lab=Vdd} +N 470 -220 470 -180 { +lab=Vdd} +N 450 -220 470 -220 { +lab=Vdd} +N 210 20 230 20 { +lab=vinp} +N 490 20 510 20 { +lab=#net4} +N 290 140 320 140 { +lab=Vb} +N 360 140 380 140 { +lab=Vss} +N 380 140 380 180 { +lab=Vss} +N 360 180 380 180 { +lab=Vss} +N 450 -240 660 -240 { +lab=Vdd} +N 720 -240 720 -210 { +lab=Vdd} +N 720 -180 740 -180 { +lab=Vdd} +N 740 -220 740 -180 { +lab=Vdd} +N 720 -220 740 -220 { +lab=Vdd} +N 450 -120 540 -120 { +lab=#net2} +N 540 -180 540 -120 { +lab=#net2} +N 540 -180 620 -180 { +lab=#net2} +N 660 -240 720 -240 { +lab=Vdd} +N 620 -180 680 -180 { +lab=#net2} +N 720 -150 720 -10 { +lab=vout} +N 720 -10 720 110 { +lab=vout} +N 720 170 720 190 { +lab=Vss} +N 720 140 740 140 { +lab=Vss} +N 740 140 740 180 { +lab=Vss} +N 720 180 740 180 { +lab=Vss} +N 450 140 680 140 { +lab=Vb} +N 450 100 450 140 { +lab=Vb} +N 300 100 450 100 { +lab=Vb} +N 300 100 300 140 { +lab=Vb} +N 540 -120 560 -120 { +lab=#net2} +N 620 -120 640 -120 { +lab=#net5} +N 700 -120 720 -120 { +lab=vout} +N 720 0 760 -0 { +lab=vout} +N 360 30 360 60 { +lab=Vss} +N 360 60 420 60 { +lab=Vss} +N 420 60 420 200 { +lab=Vss} +N 360 190 360 200 { +lab=Vss} +N 360 200 720 200 { +lab=Vss} +N 720 190 720 200 { +lab=Vss} +N 550 200 550 220 { +lab=Vss} +N 550 220 550 230 { +lab=Vss} +C {sky130_fd_pr/nfet_01v8.sym} 250 20 0 0 {name=M1 +L=L_M1 +W=W_M1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 470 20 2 0 {name=M2 +L=L_M2 +W=W_M2 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 430 -180 0 0 {name=M3 +L=L_M3 +W=W_M3 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 290 -180 0 1 {name=M4 +L=L_M4 +W=W_M4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 340 140 0 0 {name=M5 +L=L_M5 +W=W_M5 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {devices/iopin.sym} 360 -260 0 0 {name=p1 lab=Vdd} +C {devices/ipin.sym} 510 20 2 0 {name=p1 lab=vinm} +C {devices/ipin.sym} 210 20 0 0 {name=p1 lab=vinp} +C {devices/iopin.sym} 290 140 2 0 {name=p1 lab=Vb} +C {sky130_fd_pr/pfet_01v8.sym} 700 -180 0 0 {name=M6 +L=L_M6 +W=W_M6 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 700 140 2 1 {name=M7 +L=L_M7 +W=W_M7 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {devices/res.sym} 590 -120 3 0 {name=R1 +value=Rfb +footprint=1206 +device=resistor +m=1} +C {devices/capa.sym} 670 -120 3 0 {name=C1 +m=1 +value=Cfb +footprint=1206 +device="ceramic capacitor"} +C {devices/opin.sym} 760 0 0 0 {name=p1 lab=vout} +C {devices/iopin.sym} 550 230 0 0 {name=p1 lab=Vss} diff --git a/xschem/two_stage.sym b/xschem/two_stage.sym new file mode 100644 index 0000000..0cf870b --- /dev/null +++ b/xschem/two_stage.sym @@ -0,0 +1,30 @@ +v {xschem version=3.1.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -58.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +B 5 147.5 -32.5 152.5 -27.5 {name=Vdd dir=inout } +L 7 130 -30 150 -30 {} +T {Vdd} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vout dir=out } +L 4 130 -10 150 -10 {} +T {vout} 125 -14 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=vinp dir=in } +L 4 -150 -30 -130 -30 {} +T {vinp} -125 -34 0 0 0.2 0.2 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=vinm dir=in } +L 4 -150 -10 -130 -10 {} +T {vinm} -125 -14 0 0 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=Vb dir=inout } +L 7 130 10 150 10 {} +T {Vb} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=Vss dir=inout } +L 7 130 30 150 30 {} +T {Vss} 125 26 0 1 0.2 0.2 {} diff --git a/xschem/two_stage_tb.sch b/xschem/two_stage_tb.sch new file mode 100644 index 0000000..9357684 --- /dev/null +++ b/xschem/two_stage_tb.sch @@ -0,0 +1,413 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +N 640 310 660 310 { +lab=GND} +N 660 310 660 330 { +lab=GND} +N 160 320 160 330 { +lab=GND} +N 160 250 160 260 { +lab=#net1} +N 230 250 340 250 { +lab=#net1} +N 640 250 660 250 { +lab=VDD} +N 660 230 660 250 { +lab=VDD} +N 330 570 330 580 { +lab=GND} +N 330 480 330 510 { +lab=VDD} +N 640 270 690 270 { +lab=vout} +N 720 380 720 390 { +lab=GND} +N 720 290 720 320 { +lab=#net2} +N 640 290 720 290 { +lab=#net2} +N 820 380 820 390 { +lab=GND} +N 690 270 850 270 { +lab=vout} +N 820 270 820 320 { +lab=vout} +N 290 330 290 350 { +lab=GND} +N 290 270 340 270 { +lab=#net3} +N 160 250 230 250 { +lab=#net1} +C {devices/gnd.sym} 660 330 0 0 {name=l1 lab=GND} +C {devices/gnd.sym} 290 350 0 0 {name=l1 lab=GND} +C {devices/vsource.sym} 160 290 0 0 {name=V1 value="dc Vcm ac 1"} +C {devices/gnd.sym} 160 330 0 0 {name=l1 lab=GND} +C {devices/vdd.sym} 660 230 0 0 {name=l1 lab=VDD} +C {devices/vsource.sym} 330 540 0 0 {name=V2 value=1.8} +C {devices/gnd.sym} 330 580 0 0 {name=l1 lab=GND} +C {devices/vdd.sym} 330 480 0 0 {name=l1 lab=VDD} +C {devices/opin.sym} 850 270 0 0 {name=p1 lab=vout} +C {devices/vsource.sym} 720 350 0 0 {name=V3 value=Vb} +C {devices/gnd.sym} 720 390 0 0 {name=l1 lab=GND} +C {devices/code_shown.sym} 460 480 0 0 {name=s1 only_toplevel=false value=".lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt"} +C {devices/code_shown.sym} 460 640 0 0 {name=s3 only_toplevel=false value=" +.control +save all +set filetype=ascii +set units=degrees + +dc V1 0 1.8 0.01 +plot v(vout) +wrdata two_stage_tb_vout_dc v(vout) + +ac dec 10 1 1e10 +plot mag(v(vout)) +plot vdb(vout) +plot ph(v(vout)) +wrdata two_stage_tb_vout_ac mag(v(vout)) ph(v(vout)) + +op +let gmbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gm] +let gds_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vth] +let id_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[id] +let ibd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gbs] +let isub_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[isub] +let igidl_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igisl] +let igs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igs] +let igd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igd] +let igb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igb] +let igcs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vgs] +let vds_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[vds] +let cgg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cdd] +let cds_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cds] +let csg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[csg] +let csd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[csd] +let css_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[css] +let cgb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cdb] +let csb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[csb] +let cbb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[capbs] +let qg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qg] +let qb_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qb] +let qs_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qs] +let qinv_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M1=@m.x1.XM1.msky130_fd_pr__nfet_01v8[gtau] + +let gmbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gm] +let gds_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vth] +let id_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[id] +let ibd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gbs] +let isub_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[isub] +let igidl_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igisl] +let igs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igs] +let igd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igd] +let igb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igb] +let igcs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vgs] +let vds_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[vds] +let cgg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cdd] +let cds_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cds] +let csg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[csg] +let csd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[csd] +let css_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[css] +let cgb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cdb] +let csb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[csb] +let cbb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[capbs] +let qg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qg] +let qb_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qb] +let qs_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qs] +let qinv_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M2=@m.x1.XM2.msky130_fd_pr__nfet_01v8[gtau] + +let gmbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gmbs] +let gm_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gm] +let gds_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gds] +let vdsat_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vdsat] +let vth_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vth] +let id_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[id] +let ibd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[ibd] +let ibs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[ibs] +let gbd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gbd] +let gbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gbs] +let isub_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[isub] +let igidl_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igidl] +let igisl_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igisl] +let igs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igs] +let igd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igd] +let igb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igb] +let igcs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[igcs] +let vbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vbs] +let vgs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vgs] +let vds_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[vds] +let cgg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgg] +let cgs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgs] +let cgd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgd] +let cbg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbg] +let cbd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbd] +let cbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbs] +let cdg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cdg] +let cdd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cdd] +let cds_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cds] +let csg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[csg] +let csd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[csd] +let css_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[css] +let cgb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cgb] +let cdb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cdb] +let csb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[csb] +let cbb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[cbb] +let capbd_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[capbd] +let capbs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[capbs] +let qg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qg] +let qb_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qb] +let qs_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qs] +let qinv_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qinv] +let qdef_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[qdef] +let gcrg_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gcrg] +let gtau_M3=@m.x1.XM3.msky130_fd_pr__pfet_01v8[gtau] + +let gmbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gmbs] +let gm_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gm] +let gds_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gds] +let vdsat_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vdsat] +let vth_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vth] +let id_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[id] +let ibd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[ibd] +let ibs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[ibs] +let gbd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gbd] +let gbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gbs] +let isub_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[isub] +let igidl_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igidl] +let igisl_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igisl] +let igs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igs] +let igd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igd] +let igb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igb] +let igcs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[igcs] +let vbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vbs] +let vgs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vgs] +let vds_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[vds] +let cgg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgg] +let cgs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgs] +let cgd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgd] +let cbg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbg] +let cbd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbd] +let cbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbs] +let cdg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cdg] +let cdd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cdd] +let cds_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cds] +let csg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[csg] +let csd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[csd] +let css_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[css] +let cgb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cgb] +let cdb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cdb] +let csb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[csb] +let cbb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[cbb] +let capbd_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[capbd] +let capbs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[capbs] +let qg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qg] +let qb_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qb] +let qs_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qs] +let qinv_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qinv] +let qdef_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[qdef] +let gcrg_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gcrg] +let gtau_M4=@m.x1.XM4.msky130_fd_pr__pfet_01v8[gtau] + +let gmbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gm] +let gds_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vth] +let id_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[id] +let ibd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gbs] +let isub_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[isub] +let igidl_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igisl] +let igs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igs] +let igd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igd] +let igb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igb] +let igcs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vgs] +let vds_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[vds] +let cgg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cdd] +let cds_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cds] +let csg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[csg] +let csd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[csd] +let css_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[css] +let cgb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cdb] +let csb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[csb] +let cbb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[capbs] +let qg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qg] +let qb_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qb] +let qs_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qs] +let qinv_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M5=@m.x1.XM5.msky130_fd_pr__nfet_01v8[gtau] + +let gmbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gmbs] +let gm_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gm] +let gds_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gds] +let vdsat_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vdsat] +let vth_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vth] +let id_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[id] +let ibd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[ibd] +let ibs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[ibs] +let gbd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gbd] +let gbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gbs] +let isub_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[isub] +let igidl_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igidl] +let igisl_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igisl] +let igs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igs] +let igd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igd] +let igb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igb] +let igcs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[igcs] +let vbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vbs] +let vgs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vgs] +let vds_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[vds] +let cgg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgg] +let cgs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgs] +let cgd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgd] +let cbg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbg] +let cbd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbd] +let cbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbs] +let cdg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cdg] +let cdd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cdd] +let cds_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cds] +let csg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[csg] +let csd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[csd] +let css_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[css] +let cgb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cgb] +let cdb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cdb] +let csb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[csb] +let cbb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[cbb] +let capbd_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[capbd] +let capbs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[capbs] +let qg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qg] +let qb_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qb] +let qs_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qs] +let qinv_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qinv] +let qdef_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[qdef] +let gcrg_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gcrg] +let gtau_M6=@m.x1.XM6.msky130_fd_pr__pfet_01v8[gtau] + +let gmbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gmbs] +let gm_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gm] +let gds_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gds] +let vdsat_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vdsat] +let vth_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vth] +let id_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[id] +let ibd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[ibd] +let ibs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[ibs] +let gbd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gbd] +let gbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gbs] +let isub_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[isub] +let igidl_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igidl] +let igisl_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igisl] +let igs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igs] +let igd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igd] +let igb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igb] +let igcs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[igcs] +let vbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vbs] +let vgs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vgs] +let vds_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[vds] +let cgg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgg] +let cgs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgs] +let cgd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgd] +let cbg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbg] +let cbd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbd] +let cbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbs] +let cdg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cdg] +let cdd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cdd] +let cds_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cds] +let csg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[csg] +let csd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[csd] +let css_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[css] +let cgb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cgb] +let cdb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cdb] +let csb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[csb] +let cbb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[cbb] +let capbd_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[capbd] +let capbs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[capbs] +let qg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qg] +let qb_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qb] +let qs_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qs] +let qinv_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qinv] +let qdef_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[qdef] +let gcrg_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gcrg] +let gtau_M7=@m.x1.XM7.msky130_fd_pr__nfet_01v8[gtau] + +print gmbs_M1 gm_M1 gds_M1 +write two_stage_tb_op gmbs_M1 gm_M1 gds_M1 vdsat_M1 vth_M1 id_M1 ibd_M1 ibs_M1 gbd_M1 gbs_M1 isub_M1 igidl_M1 igisl_M1 igs_M1 igd_M1 igb_M1 igcs_M1 vbs_M1 vgs_M1 vds_M1 cgg_M1 cgs_M1 cgd_M1 cbg_M1 cbd_M1 cbs_M1 cdg_M1 cdd_M1 cds_M1 csg_M1 csd_M1 css_M1 cgb_M1 cdb_M1 csb_M1 cbb_M1 capbd_M1 capbs_M1 qg_M1 qb_M1 qs_M1 qinv_M1 qdef_M1 gcrg_M1 gtau_M1 gmbs_M2 gm_M2 gds_M2 vdsat_M2 vth_M2 id_M2 ibd_M2 ibs_M2 gbd_M2 gbs_M2 isub_M2 igidl_M2 igisl_M2 igs_M2 igd_M2 igb_M2 igcs_M2 vbs_M2 vgs_M2 vds_M2 cgg_M2 cgs_M2 cgd_M2 cbg_M2 cbd_M2 cbs_M2 cdg_M2 cdd_M2 cds_M2 csg_M2 csd_M2 css_M2 cgb_M2 cdb_M2 csb_M2 cbb_M2 capbd_M2 capbs_M2 qg_M2 qb_M2 qs_M2 qinv_M2 qdef_M2 gcrg_M2 gtau_M2 gmbs_M3 gm_M3 gds_M3 vdsat_M3 vth_M3 id_M3 ibd_M3 ibs_M3 gbd_M3 gbs_M3 isub_M3 igidl_M3 igisl_M3 igs_M3 igd_M3 igb_M3 igcs_M3 vbs_M3 vgs_M3 vds_M3 cgg_M3 cgs_M3 cgd_M3 cbg_M3 cbd_M3 cbs_M3 cdg_M3 cdd_M3 cds_M3 csg_M3 csd_M3 css_M3 cgb_M3 cdb_M3 csb_M3 cbb_M3 capbd_M3 capbs_M3 qg_M3 qb_M3 qs_M3 qinv_M3 qdef_M3 gcrg_M3 gtau_M3 gmbs_M4 gm_M4 gds_M4 vdsat_M4 vth_M4 id_M4 ibd_M4 ibs_M4 gbd_M4 gbs_M4 isub_M4 igidl_M4 igisl_M4 igs_M4 igd_M4 igb_M4 igcs_M4 vbs_M4 vgs_M4 vds_M4 cgg_M4 cgs_M4 cgd_M4 cbg_M4 cbd_M4 cbs_M4 cdg_M4 cdd_M4 cds_M4 csg_M4 csd_M4 css_M4 cgb_M4 cdb_M4 csb_M4 cbb_M4 capbd_M4 capbs_M4 qg_M4 qb_M4 qs_M4 qinv_M4 qdef_M4 gcrg_M4 gtau_M4 gmbs_M5 gm_M5 gds_M5 vdsat_M5 vth_M5 id_M5 ibd_M5 ibs_M5 gbd_M5 gbs_M5 isub_M5 igidl_M5 igisl_M5 igs_M5 igd_M5 igb_M5 igcs_M5 vbs_M5 vgs_M5 vds_M5 cgg_M5 cgs_M5 cgd_M5 cbg_M5 cbd_M5 cbs_M5 cdg_M5 cdd_M5 cds_M5 csg_M5 csd_M5 css_M5 cgb_M5 cdb_M5 csb_M5 cbb_M5 capbd_M5 capbs_M5 qg_M5 qb_M5 qs_M5 qinv_M5 qdef_M5 gcrg_M5 gtau_M5 gmbs_M6 gm_M6 gds_M6 vdsat_M6 vth_M6 id_M6 ibd_M6 ibs_M6 gbd_M6 gbs_M6 isub_M6 igidl_M6 igisl_M6 igs_M6 igd_M6 igb_M6 igcs_M6 vbs_M6 vgs_M6 vds_M6 cgg_M6 cgs_M6 cgd_M6 cbg_M6 cbd_M6 cbs_M6 cdg_M6 cdd_M6 cds_M6 csg_M6 csd_M6 css_M6 cgb_M6 cdb_M6 csb_M6 cbb_M6 capbd_M6 capbs_M6 qg_M6 qb_M6 qs_M6 qinv_M6 qdef_M6 gcrg_M6 gtau_M6 gmbs_M7 gm_M7 gds_M7 vdsat_M7 vth_M7 id_M7 ibd_M7 ibs_M7 gbd_M7 gbs_M7 isub_M7 igidl_M7 igisl_M7 igs_M7 igd_M7 igb_M7 igcs_M7 vbs_M7 vgs_M7 vds_M7 cgg_M7 cgs_M7 cgd_M7 cbg_M7 cbd_M7 cbs_M7 cdg_M7 cdd_M7 cds_M7 csg_M7 csd_M7 css_M7 cgb_M7 cdb_M7 csb_M7 cbb_M7 capbd_M7 capbs_M7 qg_M7 qb_M7 qs_M7 qinv_M7 qdef_M7 gcrg_M7 gtau_M7 + + +.endc +"} +C {devices/capa.sym} 820 350 0 0 {name=C1 +m=1 +value=2p +footprint=1206 +device="ceramic capacitor"} +C {devices/gnd.sym} 820 390 0 0 {name=l1 lab=GND} +C {devices/code_shown.sym} 460 560 0 0 {name=s2 only_toplevel=false +value=".include /autofs/fs1.ece/fs1.eecg.tcc/lizongh2/sky130_ldo/xschem/simulations/two_stage_tb_vars.spice +"} +C {devices/vsource.sym} 290 300 0 0 {name=V4 value="dc Vcm"} +C {two_stage.sym} 490 280 0 0 {name=x1} diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch deleted file mode 100644 index e3cbcec..0000000 --- a/xschem/user_analog_project_wrapper.sch +++ /dev/null @@ -1,180 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -N 3830 -460 3830 -390 { lab=vdda1} -N 3730 -460 3830 -460 { lab=vdda1} -N 3860 -230 3860 -180 { lab=vssa1} -N 3770 -180 3860 -180 { lab=vssa1} -N 3890 -460 3890 -390 { lab=vccd1} -N 3890 -460 3960 -460 { lab=vccd1} -N 3890 -130 3890 -60 { lab=vccd1} -N 3890 -130 3950 -130 { lab=vccd1} -N 3830 -130 3830 -60 { lab=io_analog[4]} -N 3790 -130 3830 -130 { lab=io_analog[4]} -N 3860 100 3860 150 { lab=vssa1} -N 3800 150 3860 150 { lab=vssa1} -N 4010 -10 4110 -10 { lab=gpio_analog[7]} -N 4010 20 4110 20 { lab=io_out[15]} -N 4010 50 4110 50 { lab=io_out[16]} -N 4010 -340 4130 -340 { lab=gpio_analog[3]} -N 4010 -310 4130 -310 { lab=io_out[11]} -N 4010 -280 4130 -280 { lab=io_out[12]} -N 3670 300 3670 340 { lab=io_clamp_low[2]} -N 3670 400 3670 420 { lab=vssa1} -N 3670 440 3670 460 { lab=io_clamp_high[2]} -N 3670 520 3670 530 { lab=vssa1} -N 3670 570 3670 590 { lab=io_clamp_low[1]} -N 3670 650 3670 670 { lab=vssa1} -N 4160 300 4160 330 { lab=io_clamp_high[1]} -N 4160 390 4160 410 { lab=vssa1} -N 4160 440 4160 460 { lab=io_clamp_low[0]} -N 4160 520 4160 530 { lab=vssa1} -N 4160 550 4160 560 { lab=io_clamp_high[0]} -N 4160 620 4160 640 { lab=io_analog[4]} -N 3630 300 3670 300 { lab=io_clamp_low[2]} -N 3630 420 3670 420 { lab=vssa1} -N 3630 440 3670 440 { lab=io_clamp_high[2]} -N 3630 530 3670 530 { lab=vssa1} -N 3630 570 3670 570 { lab=io_clamp_low[1]} -N 3630 670 3670 670 { lab=vssa1} -N 4130 300 4160 300 { lab=io_clamp_high[1]} -N 4130 410 4160 410 { lab=vssa1} -N 4130 440 4160 440 { lab=io_clamp_low[0]} -N 4130 530 4160 530 { lab=vssa1} -N 4130 550 4160 550 { lab=io_clamp_high[0]} -N 4130 640 4160 640 { lab=io_analog[4]} -N 3670 710 3670 750 { lab=io_oeb[12]} -N 3670 810 3670 830 { lab=vssd1} -N 3670 850 3670 870 { lab=io_oeb[16]} -N 3670 930 3670 940 { lab=vssd1} -N 4160 710 4160 740 { lab=io_oeb[11]} -N 4160 800 4160 820 { lab=vssd1} -N 4160 850 4160 870 { lab=#net1} -N 4160 930 4160 940 { lab=vssd1} -N 3630 710 3670 710 { lab=io_oeb[12]} -N 3630 830 3670 830 { lab=vssd1} -N 3630 850 3670 850 { lab=io_oeb[16]} -N 3630 940 3670 940 { lab=vssd1} -N 4130 710 4160 710 { lab=io_oeb[11]} -N 4130 820 4160 820 { lab=vssd1} -N 4130 850 4160 850 { lab=#net1} -N 4130 940 4160 940 { lab=vssd1} -C {example_por.sym} 3860 -310 0 0 {name=x1} -C {example_por.sym} 3860 20 0 0 {name=x2} -C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1} -C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2} -C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1} -C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2} -C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1} -C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2} -C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1} -C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2} -C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i} -C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i} -C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i} -C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i} -C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i} -C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]} -C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]} -C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]} -C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o} -C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]} -C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]} -C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]} -C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]} -C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]} -C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2} -C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]} -C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]} -C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]} -C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]} -C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]} -C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]} -C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]} -C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]} -C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]} -C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1} -C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1} -C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1} -C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]} -C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]} -C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]} -C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]} -C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]} -C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]} -C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]} -C {sky130_fd_pr/res_generic_m1.sym} 3670 370 0 0 {name=R1 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 3670 490 0 0 {name=R2 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 3670 620 0 0 {name=R4 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 360 0 0 {name=R5 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 490 0 0 {name=R6 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 590 0 0 {name=R7 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {devices/lab_pin.sym} 3630 300 0 0 {name=l13 sig_type=std_logic lab=io_clamp_low[2]} -C {devices/lab_pin.sym} 3630 440 0 0 {name=l14 sig_type=std_logic lab=io_clamp_high[2]} -C {devices/lab_pin.sym} 3630 570 0 0 {name=l15 sig_type=std_logic lab=io_clamp_low[1]} -C {devices/lab_pin.sym} 4130 300 0 0 {name=l16 sig_type=std_logic lab=io_clamp_high[1]} -C {devices/lab_pin.sym} 4130 440 0 0 {name=l17 sig_type=std_logic lab=io_clamp_low[0]} -C {devices/lab_pin.sym} 3630 420 0 0 {name=l18 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 3630 530 0 0 {name=l19 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 410 0 0 {name=l20 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 530 0 0 {name=l21 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 3630 670 0 0 {name=l22 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 550 0 0 {name=l23 sig_type=std_logic lab=io_clamp_high[0]} -C {devices/lab_pin.sym} 4130 640 0 0 {name=l24 sig_type=std_logic lab=io_analog[4]} -C {sky130_fd_pr/res_generic_m1.sym} 3670 780 0 0 {name=R8 -W=0.56 -L=0.49 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 3670 900 0 0 {name=R9 -W=0.56 -L=0.31 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 770 0 0 {name=R11 -W=0.56 -L=0.58 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 900 0 0 {name=R12 -W=0.56 -L=0.6 -model=res_generic_m3 -mult=1} -C {devices/lab_pin.sym} 4130 850 0 0 {name=l25 sig_type=std_logic lab=io_oeb[15]} -C {devices/lab_pin.sym} 3630 850 0 0 {name=l26 sig_type=std_logic lab=io_oeb[16]} -C {devices/lab_pin.sym} 4130 710 0 0 {name=l27 sig_type=std_logic lab=io_oeb[11]} -C {devices/lab_pin.sym} 3630 710 0 0 {name=l28 sig_type=std_logic lab=io_oeb[12]} -C {devices/lab_pin.sym} 3630 830 0 0 {name=l29 sig_type=std_logic lab=vssd1} -C {devices/lab_pin.sym} 3630 940 0 0 {name=l30 sig_type=std_logic lab=vssd1} -C {devices/lab_pin.sym} 4130 820 0 0 {name=l31 sig_type=std_logic lab=vssd1} -C {devices/lab_pin.sym} 4130 940 0 0 {name=l32 sig_type=std_logic lab=vssd1} diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice deleted file mode 100644 index 0dc2d20..0000000 --- a/xschem/user_analog_project_wrapper.spice +++ /dev/null @@ -1,202 +0,0 @@ -.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i -+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31] -+ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23] -+ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15] -+ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7] -+ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31] -+ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23] -+ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15] -+ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7] -+ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o -+ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24] -+ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16] -+ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8] -+ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0] -+ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121] -+ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114] -+ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107] -+ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100] -+ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93] -+ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86] -+ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79] -+ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72] -+ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65] -+ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58] -+ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51] -+ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44] -+ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37] -+ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30] -+ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23] -+ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16] -+ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9] -+ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1] -+ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123] -+ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117] -+ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111] -+ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105] -+ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98] -+ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91] -+ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84] -+ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77] -+ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70] -+ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63] -+ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56] -+ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49] -+ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42] -+ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35] -+ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28] -+ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21] -+ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14] -+ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7] -+ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] io_in[26] -+ io_in[25] io_in[24] io_in[23] io_in[22] io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] -+ io_in[14] io_in[13] io_in[12] io_in[11] io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] -+ io_in[3] io_in[2] io_in[1] io_in[0] io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] -+ io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] -+ io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] -+ io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] user_clock2 io_out[26] io_out[25] -+ io_out[24] io_out[23] io_out[22] io_out[21] io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] -+ io_out[14] io_out[13] io_out[12] io_out[11] io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] -+ io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] -+ io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] -+ io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] -+ io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] gpio_analog[15] gpio_analog[14] gpio_analog[13] -+ gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] gpio_analog[8] gpio_analog[7] gpio_analog[6] -+ gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] gpio_analog[1] gpio_analog[0] gpio_noesd[17] -+ gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] -+ gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] -+ gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[5] -+ io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] io_clamp_high[2] io_clamp_high[1] -+ io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_irq[2] user_irq[1] user_irq[0] la_oenb[127] -+ la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] la_oenb[119] -+ la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] la_oenb[111] -+ la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] la_oenb[103] -+ la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] la_oenb[94] -+ la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] la_oenb[85] -+ la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] la_oenb[76] -+ la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] la_oenb[67] -+ la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] la_oenb[58] -+ la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] la_oenb[49] -+ la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] la_oenb[40] -+ la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] la_oenb[31] -+ la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] la_oenb[22] -+ la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] la_oenb[13] -+ la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] la_oenb[4] -+ la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] -*.iopin vdda1 -*.iopin vdda2 -*.iopin vssa1 -*.iopin vssa2 -*.iopin vccd1 -*.iopin vccd2 -*.iopin vssd1 -*.iopin vssd2 -*.ipin wb_clk_i -*.ipin wb_rst_i -*.ipin wbs_stb_i -*.ipin wbs_cyc_i -*.ipin wbs_we_i -*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0] -*.ipin -*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0] -*.ipin -*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] -*.opin wbs_ack_o -*.opin -*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0] -*.ipin -*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0] -*.opin -*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0] -*.ipin -*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0] -*.ipin -*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] -*.ipin user_clock2 -*.opin -*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0] -*.opin -*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0] -*.iopin -*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0] -*.iopin -*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0] -*.iopin -*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] -*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] -*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0] -*.opin user_irq[2],user_irq[1],user_irq[0] -*.ipin -*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0] -x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por -x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por -R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R3 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1 -R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R8 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R10 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1 -R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R12 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -.ends - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1 -XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1 -XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2 -x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -** flattened .save nodes -.end diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym deleted file mode 100644 index a561ba9..0000000 --- a/xschem/user_analog_project_wrapper.sym +++ /dev/null @@ -1,111 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -V {} -S {} -E {} -L 4 -130 -190 130 -190 {} -L 4 -130 190 130 190 {} -L 4 -130 -190 -130 190 {} -L 4 130 -190 130 190 {} -L 4 -150 -180 -130 -180 {} -L 4 -150 -160 -130 -160 {} -L 4 -150 -140 -130 -140 {} -L 4 -150 -120 -130 -120 {} -L 4 -150 -100 -130 -100 {} -L 4 -150 -80 -130 -80 {} -L 4 -150 -60 -130 -60 {} -L 4 -150 -40 -130 -40 {} -L 4 130 -20 150 -20 {} -L 4 130 0 150 0 {} -L 4 -150 -20 -130 -20 {} -L 4 130 20 150 20 {} -L 4 -150 0 -130 0 {} -L 4 -150 20 -130 20 {} -L 4 -150 40 -130 40 {} -L 4 130 40 150 40 {} -L 4 130 60 150 60 {} -L 4 -150 60 -130 60 {} -L 4 130 180 150 180 {} -L 7 130 -180 150 -180 {} -L 7 130 -160 150 -160 {} -L 7 130 -140 150 -140 {} -L 7 130 -120 150 -120 {} -L 7 130 -100 150 -100 {} -L 7 130 -80 150 -80 {} -L 7 130 -60 150 -60 {} -L 7 130 -40 150 -40 {} -L 7 130 80 150 80 {} -L 7 130 100 150 100 {} -L 7 130 120 150 120 {} -L 7 130 140 150 140 {} -L 7 130 160 150 160 {} -B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout } -B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout } -B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout } -B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout } -B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout } -B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout } -B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout } -B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout } -B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in } -B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in } -B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in } -B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in } -B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in } -B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in } -B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in } -B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in } -B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out } -B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out } -B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in } -B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out } -B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in } -B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in } -B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in } -B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out } -B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out } -B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout } -B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout } -B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout } -B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout } -B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout } -B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in } -B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out } -T {@symname} -119.5 114 0 0 0.3 0.3 {} -T {@name} 135 -202 0 0 0.2 0.2 {} -T {vdda1} 125 -184 0 1 0.2 0.2 {} -T {vdda2} 125 -164 0 1 0.2 0.2 {} -T {vssa1} 125 -144 0 1 0.2 0.2 {} -T {vssa2} 125 -124 0 1 0.2 0.2 {} -T {vccd1} 125 -104 0 1 0.2 0.2 {} -T {vccd2} 125 -84 0 1 0.2 0.2 {} -T {vssd1} 125 -64 0 1 0.2 0.2 {} -T {vssd2} 125 -44 0 1 0.2 0.2 {} -T {wb_clk_i} -125 -184 0 0 0.2 0.2 {} -T {wb_rst_i} -125 -164 0 0 0.2 0.2 {} -T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {} -T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {} -T {wbs_we_i} -125 -104 0 0 0.2 0.2 {} -T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {} -T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {} -T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {} -T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {} -T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {} -T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {} -T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {} -T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {} -T {io_in[26:0]} -125 16 0 0 0.2 0.2 {} -T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {} -T {io_out[26:0]} 125 36 0 1 0.2 0.2 {} -T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {} -T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {} -T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {} -T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {} -T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {} -T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {} -T {user_clock2} -125 56 0 0 0.2 0.2 {} -T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {} diff --git a/xschem/xschemrc b/xschem/xschemrc index ca6e33e..87de784 100644 --- a/xschem/xschemrc +++ b/xschem/xschemrc @@ -25,17 +25,12 @@ # /home/schippes/share/doc/xschem/pcb # /home/schippes/share/doc/xschem/rom8k -#### Allow user environment to override the path to the PDK -if {[catch {set PDKPATH $env(PDKPATH)}]} { - set PDKPATH "/usr/share/pdk/sky130A" -} #### Flush any previous definition set XSCHEM_LIBRARY_PATH {} #### include devices/*.sym append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library #### include skywater libraries. Here i use [pwd]. This works if i start xschem from here. append XSCHEM_LIBRARY_PATH :$env(PWD) -append XSCHEM_LIBRARY_PATH :$PDKPATH/libs.tech/xschem # append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem #### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem) append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library @@ -66,7 +61,23 @@ set XSCHEM_START_WINDOW {sky130_tests/top.sch} ########################################################################### #### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations) # set netlist_dir $env(HOME)/.xschem/simulations -set netlist_dir . +set netlist_dir ~/sky130_ldo/xschem/simulations + +########################################################################### +#### NETLIST AND HIERARCHICAL PRINT EXCLUDE PATTERNS +########################################################################### +#### xschem_libs is a list of patterns of cells to exclude from netlisting. +#### Matching is done as regular expression on full cell path +#### Example: +#### set xschem_libs { {/cmoslib/} {/analoglib/.*pass} buffer } +#### in this case all schematic cells of directory cmoslib and cells containing +#### /analoglib/...pass and buffer will be excluded from netlisting +#### default value: empty +# set xschem_libs {} +#### noprint_libs is a list with same rules as for xschem_libs. This +#### variable controls hierarchical print +#### default value: empty +# set noprint_libs {} ########################################################################### #### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS @@ -84,7 +95,6 @@ set netlist_dir . # set netlist_type spice #### Some netlisting options (these are the defaults) -# set hspice_netlist 1 # set verilog_2001 1 #### to use a fixed line with set change_lw to 0 and set some value to line_width @@ -113,6 +123,10 @@ set netlist_dir . #### default: 0 # set persistent_command 1 +#### if set to 1 a wire is inserted when separating components that are +#### connected by pins. Default: not enabled (0) +# set connect_by_kissing 1 + #### if set to 1 automatically join/trim wires while editing #### this may slow down on rally big designs. Can be disabled via menu #### default: 0 @@ -142,6 +156,17 @@ set netlist_dir . # set to_pdf ps2pdf set to_pdf {ps2pdf -dAutoRotatePages=/None} +########################################################################### +#### UNDO: SAVE ON DISK OR KEEP IN MEMORY +########################################################################### +#### Alloved: 'disk'or 'memory'. +#### Saving undo on disk is safer but slower on extremely big schematics. +#### In most cases you won't notice any delay. Undo on disk allows previous +#### state recovery in case of crashes. In-memory undo is extremely fast +#### but should a crash occur everything is lost. +#### It is highly recommended to keep undo on disk. +#### Default: disk +# set undo_type disk ########################################################################### #### CUSTOM GRID / SNAP VALUE SETTINGS @@ -231,14 +256,6 @@ set to_pdf {ps2pdf -dAutoRotatePages=/None} #### default: 0 (can be enabled by menu) # set show_infowindow 0 -########################################################################### -#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS -########################################################################### -#### RTDA NC -# set computerfarm {nc run -Il} -#### LSF BSUB -# set computerfarm {bsub -Is} - ########################################################################### #### TCP CONNECTION WITH GAW ########################################################################### @@ -258,39 +275,102 @@ set to_pdf {ps2pdf -dAutoRotatePages=/None} #### set bespice wave listening port; default: not enabled set bespice_listen_port 2022 - - -########################################################################### -#### UTILE SPICE STIMULI DESCRIPTION LANGUAGE AND TRANSLATOR -########################################################################### -#### default paths are set as shown here: -# set utile_gui_path ${XSCHEM_SHAREDIR}/utile/utile3 -# set utile_cmd_path ${XSCHEM_SHAREDIR}/utile/utile - ########################################################################### #### TCL FILES TO LOAD AT STARTUP ########################################################################### #### list of tcl files to preload. # lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl -lappend tcl_files $PDKPATH/libs.tech/xschem/scripts/sky130_models.tcl + ########################################################################### #### XSCHEM TOOLBAR ########################################################################### #### default: not enabled. -# set toolbar_visible 1 +set toolbar_visible 1 # set toolbar_horiz 1 +########################################################################### +#### TABBED WINDOWS +########################################################################### +# default: not enabled. Interface can be changed runtime if only one window +# or tab is open. +set tabbed_interface 1 + +########################################################################### +#### CASE INSENSITIVE SYMBOL LOOKUP +########################################################################### +## this option might be useful on filesystems that are case insensitive and +## on designs ported from windows where case of file names does not matter. +## if this option is set symbol lookup will be case insensitive, +## so a symbol reference 'AMPLI.SYM' will match with 'ampli.sym' or +## Amply.sym on disk. File system must be case insensitive for this to work, +## like FAT32 or NTFS. +## Do not set this option if you don't know what you are doing. +## Default: not enabled (0) +# set case_insensitive 1 + +########################################################################### +#### HIDE GRAPHS IF NO SPICE DATA LOADED +########################################################################### +## if enabled graphs will be hidden if no data is loaded. +## default: not enabled (0) +# set hide_empty_graphs 0 + +########################################################################### +#### SHOW HIDDEN TEXTS +########################################################################### +## This option shows text objects even if they have attribute 'hide=true' set +## default: 0 (not set) +# set show_hidden_texts 1 + +########################################################################### +#### LIVE BACKANNOTATION OF DATA AT CURSOR 2 (B) POSITION +########################################################################### +## if enabled will backannotate values in schematic at cursor 'b' position +## in graph. Default: not enabled (0) +# set live_cursor2_backannotate 1 + ########################################################################### #### SKYWATER PDK SPECIFIC VARIABLES ########################################################################### -## (spice patched) skywater-pdk install -# set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest -# set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest +## check if env var PDK_ROOT exists, and use it for building open_pdks paths +if { [info exists env(PDK_ROOT)] && $env(PDK_ROOT) ne {} } { + ## found variable, set tcl PDK_ROOT var + if {![file isdir $env(PDK_ROOT)]} { + puts stderr "Warning: PDK_ROOT environment variable is set but path not found on the system." + } + set PDK_ROOT $env(PDK_ROOT) +} else { + ## not existing or empty. + puts stderr "Warning: PDK_ROOT env. var. not found or empty, trying to find an open_pdks install" + if {[file isdir /usr/share/pdk]} {set PDK_ROOT /usr/share/pdk + } elseif {[file isdir /usr/local/share/pdk]} {set PDK_ROOT /usr/local/share/pdk + } elseif {[file isdir $env(HOME)/share/pdk]} {set PDK_ROOT $env(HOME)/share/pdk + } else { + puts stderr {No open_pdks installation found, set PDK_ROOT env. var. and restart xschem} + } +} + +if {[info exists PDK_ROOT]} { + ## get process variant + if {[info exists env(PDK)]} { + set PDK $env(PDK) + } else { + set PDK sky130A + } + set SKYWATER_MODELS ${PDK_ROOT}/${PDK}/libs.tech/ngspice + set SKYWATER_STDCELLS ${PDK_ROOT}/${PDK}/libs.ref/sky130_fd_sc_hd/spice + puts stderr "open_pdks installation: using $PDK_ROOT" + puts stderr "SKYWATER_MODELS: $SKYWATER_MODELS" + puts stderr "SKYWATER_STDCELLS: $SKYWATER_STDCELLS" +} + + +# open_pdks specific: +# Set variables after ${PDK_ROOT} is known +# This overrides some of the variables set above. + +set XSCHEM_START_WINDOW ${PDK_ROOT}/${PDK}/libs.tech/xschem/sky130_tests/top.sch +append XSCHEM_LIBRARY_PATH :${PDK_ROOT}/${PDK}/libs.tech/xschem -## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation -# set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice -# set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice -set SKYWATER_MODELS $PDKPATH/libs.tech/ngspice -set SKYWATER_STDCELLS $PDKPATH/libs.ref/sky130_fd_sc_hd/spice