Add LoongArch SX SIMD extenstion implementation #981
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−0
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Add LoongArch SX SIMD extension support to xxHash, which is a new RISC ISA just like RISC-V. The code itself is basically a rewritten of the SSE2 one, tested on Loongson 3A6000 processor, here are the results.
Scalar
LoongArch SX
Reference
LoongArch Intrinsics Document: https://jia.je/unofficial-loongarch-intrinsics-guide/
Resolve
loongson-community/discussions#72