VGA_Debug.bld

Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -sd ipcore_dir -nt timestamp -uc /home/dan/ECE368-Lab/Lab
4/VGA_Debug/vga_debug.ucf -p xc3s500e-fg320-4 VGA_Debug.ngc VGA_Debug.ngd

Reading NGO file "/home/dan/Lab4/VGA_Debug.ngc" ...
Loading design module "ipcore_dir/DEBUG_RAM.ngc"...
Loading design module "ipcore_dir/VGA_BUFFER_RAM.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "/home/dan/ECE368-Lab/Lab
4/VGA_Debug/vga_debug.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem - The Period constraint <NET "CLK" PERIOD = 20.0ns HIGH
   50%;> [/home/dan/ECE368-Lab/Lab 4/VGA_Debug/vga_debug.ucf(17)], is specified
   using the Net Period method which is not recommended. Please use the Timespec
   PERIOD method.

Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 396624 kilobytes

Writing NGD file "VGA_Debug.ngd" ...
Total REAL time to NGDBUILD completion:  2 sec
Total CPU time to NGDBUILD completion:   2 sec

Writing NGDBUILD log file "VGA_Debug.bld"...