-
Notifications
You must be signed in to change notification settings - Fork 0
/
VGA_Debug.par
220 lines (139 loc) · 8.74 KB
/
VGA_Debug.par
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
XPS-15:: Fri Feb 26 15:41:27 2016
par -w -intstyle ise -ol high -t 1 VGA_Debug_map.ncd VGA_Debug.ncd
VGA_Debug.pcf
Constraints file: VGA_Debug.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"VGA_Debug" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
Device speed data version: "PRODUCTION 1.27 2013-10-13".
Design Summary Report:
Number of External IOBs 23 out of 232 9%
Number of External Input IOBs 13
Number of External Input IBUFs 13
Number of LOCed External Input IBUFs 13 out of 13 100%
Number of External Output IOBs 10
Number of External Output IOBs 10
Number of LOCed External Output IOBs 10 out of 10 100%
Number of External Bidir IOBs 0
Number of BUFGMUXs 2 out of 24 8%
Number of DCMs 1 out of 4 25%
Number of MULT18X18SIOs 1 out of 20 5%
Number of RAMB16s 4 out of 20 20%
Number of Slices 142 out of 4656 3%
Number of SLICEMs 0 out of 2328 0%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:62e28c8c) REAL time: 1 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:62e28c8c) REAL time: 1 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:62e28c8c) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:7aa0d7b4) REAL time: 1 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:7aa0d7b4) REAL time: 1 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:7aa0d7b4) REAL time: 1 secs
Phase 7.8 Global Placement
.....................................
....
Phase 7.8 Global Placement (Checksum:dbfb108b) REAL time: 3 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:dbfb108b) REAL time: 3 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:db866f2a) REAL time: 3 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:db866f2a) REAL time: 3 secs
Total REAL time to Placer completion: 3 secs
Total CPU time to Placer completion: 3 secs
Writing design to file VGA_Debug.ncd
Starting Router
Phase 1 : 1075 unrouted; REAL time: 6 secs
Phase 2 : 941 unrouted; REAL time: 6 secs
Phase 3 : 111 unrouted; REAL time: 6 secs
Phase 4 : 111 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 6 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 6 secs
Updating file: VGA_Debug.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 7 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 7 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 7 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 7 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 7 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:152, Component Switching Limit:0) REAL time: 7 secs
Phase 12 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 13 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Total REAL time to Router completion: 7 secs
Total CPU time to Router completion: 7 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_IBUFG | BUFGMUX_X2Y11| No | 84 | 0.074 | 0.191 |
+---------------------+--------------+------+------+------------+-------------+
| U1/PCLK | BUFGMUX_X1Y10| No | 13 | 0.043 | 0.163 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "CLK_IBUFG1" PERIOD = 20 ns HIGH 50% | SETUP | 5.936ns| 14.064ns| 0| 0
| HOLD | 0.432ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "U1/PCLK1" derive | SETUP | 11.018ns| 17.964ns| 0| 0
d from NET "CLK_IBUFG1" PERIOD = 20 ns H | HOLD | 1.609ns| | 0| 0
IGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for CLK_IBUFG1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|CLK_IBUFG1 | 20.000ns| 14.064ns| 8.982ns| 0| 0| 2806| 561|
| U1/PCLK1 | 40.000ns| 17.964ns| N/A| 0| 0| 561| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 7 secs
Total CPU time to PAR completion: 7 secs
Peak Memory Usage: 577 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file VGA_Debug.ncd
PAR done!