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DMUL rd, rs, rt and DDIV rd, rs, rt not implemented #867

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eduardz1 opened this issue Nov 7, 2023 · 1 comment · May be fixed by #871
Open

DMUL rd, rs, rt and DDIV rd, rs, rt not implemented #867

eduardz1 opened this issue Nov 7, 2023 · 1 comment · May be fixed by #871
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@lupino3
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component:core priority:1 type:feature-request

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@eduardz1
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eduardz1 commented Nov 7, 2023

When trying to run code with the DDIV instructions it errors out, expecting me to use DDIV rs, rt with the result placed in LO / HI

When trying to run code with the DMUL instruction it probably expects me to use the DMULT rs, rt instead, based on the changelog for version 0.1.4

image

However both seem valid based on the MIPS architecture specification, supporting them would be helpful due to them being the only option for winmips64, still standard in some universities like the Polytechnic University of Turin
@lupino3
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lupino3 commented Nov 7, 2023

Hi, thanks for reporting this issue.

I can see both instruction in the ISA. I think there will be no issues implementing DMUL, while for DDIV it may be more complex, as I don't think we have internally a way to "overload" instructions based on their signature: we would have two DDIV instructions with different parameter types and we'd need a way to disambiguate.

I'll investigate. Thanks again for the bug report!

@lupino3 lupino3 self-assigned this Nov 7, 2023
@lupino3 lupino3 changed the title DMUL rd, rs, rt and DDIV rd, rs, rt not implemented or not valid DMUL rd, rs, rt and DDIV rd, rs, rt not implemented Nov 7, 2023
@lupino3 lupino3 linked a pull request Nov 12, 2023 that will close this issue
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Add DMUL and DDIV overload EduMIPS64/edumips64
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@lupino3 @eduardz1