-
Notifications
You must be signed in to change notification settings - Fork 6
/
pci.c
executable file
·295 lines (269 loc) · 8.46 KB
/
pci.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
/*
* pci.c
*
* Created on: 10.03.2013
* Author: pascal
*/
#include "pci.h"
#include "config.h"
#include "util.h"
#include "stdbool.h"
#include "display.h"
#include "stdio.h"
#include "stdlib.h"
#define CONFIG_ADDRESS 0xCF8
#define CONFIG_DATA 0xCFC
#define PCI_VENDOR_ID 0x00 // length: 0x02 reg: 0x00 offset: 0x00
#define PCI_DEVICE_ID 0x02 // length: 0x02 reg: 0x00 offset: 0x02
#define PCI_COMMAND 0x04
#define PCI_STATUS 0x06
#define PCI_REVISION 0x08
#define PCI_CLASS 0x0B
#define PCI_SUBCLASS 0x0A
#define PCI_PROG_IF 0x09
#define PCI_HEADERTYPE 0x0E
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_BAR2 0x18
#define PCI_BAR3 0x1C
#define PCI_BAR4 0x20
#define PCI_BAR5 0x24
#define PCI_CAPLIST 0x34
#define PCI_IRQLINE 0x3C
#define PCIBUSES 256
#define PCISLOTS 32
#define PCIFUNCS 8
//Aufbau des Kommandoregisters
/*
* Bits | 15-11 | 10 | 9 | 8 | 7 | 6 |
* | Reserved | Interupt Disable | Fast Back-to-Back Enable | SERR# Enable | Reserved | Parity Error Response |
*
* Bits | 5 | 4 | 3 | 2 | 1 | 0
* | VGA Palette Snoop | Memory Write and Invalidate Enable | Special Cycles | Bus Master | Memory Space | I/O Space
*/
//Aufbau des Statusregisters
/*
* Bits | 15 | 14 | 13 | 12 | 11 |
* | Detected Parity Error | Signaled System Error | Received Master Abort | Received Target Abort | Signaled Target Abort |
*
* Bits | 10 + 9 | 8 | 7 | 6 | 5 | 4
* | DEVSEL Timing | Master Data Parity Error | Fast Back-to-Back Capable | Reserved | 66 MHz Capable | Capabilities List
*
* Bits | 3 | 2-0
* | Interrupt Status | Reserved
*/
list_t pciDevices;
static bool checkDevice(uint8_t bus, uint8_t slot, uint8_t func)
{
//Wenn VendorID != 0xFFFF, dann ist ein Gerät vorhanden
if(pci_readConfig(bus, slot, func, PCI_VENDOR_ID, 2) != 0xFFFF) return true;
return false;
}
static pciDevice_t *initDevice(uint8_t bus, uint8_t slot, uint8_t func)
{
pciDevice_t *pciDevice;
//Wenn kein Gerät vorhanden, Initialierung abbrechen
if(!checkDevice(bus, slot, func))
return NULL;
//Ansonsten neue Struktur anlegen
pciDevice = malloc(sizeof(pciDevice_t));
if(pciDevice == NULL)
return NULL;
//Daten auslesen
pciDevice->Bus = bus;
pciDevice->Slot = slot;
pciDevice->Function = func;
pciDevice->DeviceID = pci_readConfig(bus, slot, func, PCI_DEVICE_ID, 2);
pciDevice->VendorID = pci_readConfig(bus, slot, func, PCI_VENDOR_ID, 2);
pciDevice->ClassCode = pci_readConfig(bus, slot, func, PCI_CLASS, 1);
pciDevice->Subclass = pci_readConfig(bus, slot, func, PCI_SUBCLASS, 1);
pciDevice->ProgIF = pci_readConfig(bus, slot, func, PCI_PROG_IF, 1);
pciDevice->RevisionID = pci_readConfig(bus, slot, func, PCI_REVISION, 1);
pciDevice->HeaderType = pci_readConfig(bus, slot, func, PCI_HEADERTYPE, 1);
pciDevice->irq = pci_readConfig(bus, slot, func, PCI_IRQLINE, 1);
if((pciDevice->HeaderType & ~0x80) == 0x00 || (pciDevice->HeaderType & ~0x80) == 0x01)
{
uint8_t maxBars = 6 - (pciDevice->HeaderType * 4);
uint8_t Bar;
for(Bar = 0; Bar < maxBars; Bar++)
{
//Offset der aktuellen Bar
uint32_t BarOffset = 0x10 + (Bar * 4);
uint32_t Data = pci_readConfig(bus, slot, func, BarOffset, 4);
//prüfen, ob Speicher oder IO
if((Data & 0x1) == 0)
{
//Speicherressource:
switch((Data & 0x6) >> 1)
{
case 0x0: //32-Bit BAR
//Mit lauter 1en überschreiben
pci_writeConfig(bus, slot, func, BarOffset, 4, 0xFFFFFFF0);
//und zurück lesen
uint32_t tmp = pci_readConfig(bus, slot, func, BarOffset, 4);
//Daten zurückschreiben
pci_writeConfig(bus, slot, func, BarOffset, 4, Data);
if(tmp == 0) //Es muss immer mind. ein Bit beschreibbar sein
pciDevice->BAR[Bar].Type = BAR_UNUSED;
else
{
pciDevice->BAR[Bar].Type = BAR_32;
pciDevice->BAR[Bar].Address = Data & 0xFFFFFFF0;
pciDevice->BAR[Bar].Size = ~(tmp & 0xFFFFFFF0) + 1;
}
break;
case 0x2: //64-Bit BAR
//prüfen, ob ein 64-Bit-BAR an der aktuellen Position überhaupt möglich ist
if(Bar >= (maxBars - 1))
pciDevice->BAR[Bar].Type = BAR_INVALID;
else
{
//Werte zwischenspeichern
uint32_t tmp_high = pci_readConfig(bus, slot, func, BarOffset + 4, 4);
//Mit lauter 1en überschreiben
pci_writeConfig(bus, slot, func, BarOffset, 4, 0xFFFFFFF0);
pci_writeConfig(bus, slot, func, BarOffset + 4, 4, 0xFFFFFFFF);
uint64_t tmp = pci_readConfig(bus, slot, func, BarOffset, 4) | ((uint64_t)pci_readConfig(bus, slot, func, BarOffset + 4, 4) << 32);
//Daten zurückschreiben
pci_writeConfig(bus, slot, func, BarOffset, 4, Data);
pci_writeConfig(bus, slot, func, BarOffset + 4, 4, tmp_high);
if(tmp == 0) //Es muss immer mindestens ein Bit beschreibbar sein
pciDevice->BAR[Bar].Type = pciDevice->BAR[Bar + 1].Type = BAR_UNUSED;
else
{
pciDevice->BAR[Bar].Type = BAR_64LO;
pciDevice->BAR[Bar].Address = Data & 0xFFFFFFF0;
Bar++; //Bar erhöhen, da die nachfolgende die oberen 32 Bit enthält
pciDevice->BAR[Bar].Type = BAR_64HI;
pciDevice->BAR[Bar].Address = tmp_high;
pciDevice->BAR[Bar].Size = ~(tmp & ~0xF) + 1;
}
}
break;
default:
pciDevice->BAR[Bar].Type = BAR_INVALID;
}
}
else
{
//IO
//Mit lauter 1en überschreiben
pci_writeConfig(bus, slot, func, BarOffset, 4, 0xFFFFFFFC);
//und wieder zurücklesen
uint32_t tmp = pci_readConfig(bus, slot, func, BarOffset, 4);
//Anfangszustand wiederherstellen
pci_writeConfig(bus, slot, func, BarOffset, 4, Data);
if(tmp == 0) //Es muss immer mind. ein Bit gesetzt bzw. beschreibbar sein
pciDevice->BAR[Bar].Type = BAR_UNUSED;
else
{
pciDevice->BAR[Bar].Type = BAR_IO;
pciDevice->BAR[Bar].Address = Data & 0xFFFFFFFC;
pciDevice->BAR[Bar].Size = ~(tmp & 0xFFFFFFFC) + 1;
}
}
}
//Die restlichen BARs als nicht definiert markieren
uint8_t i;
if(pciDevice->HeaderType == 0x1)
for(i = 2; i < 6; i++)
pciDevice->BAR[Bar].Type = BAR_UNDEFINED;
if(pciDevice->HeaderType == 0x2)
for(i = 0; i < 6; i++)
pciDevice->BAR[Bar].Type = BAR_UNDEFINED;
}
return pciDevice;
}
static void patchDevice(pciDevice_t *pciDevice)
{
//JMicron 2xSATA/1xIDE Card
if(pciDevice->VendorID == 0x197B && pciDevice->DeviceID == 0x2363)
{
uint32_t conf = pci_readConfig(pciDevice->Bus, pciDevice->Slot, pciDevice->Function, 0x40, 4);
conf |= 0x00C2A1B3;
pci_writeConfig(pciDevice->Bus, pciDevice->Slot, pciDevice->Function, 0x40, 4, conf);
//Update pciDevice
pciDevice->HeaderType = pci_readConfig(pciDevice->Bus, pciDevice->Slot, pciDevice->Function, PCI_HEADERTYPE, 1);
}
}
static void checkSlot(uint8_t bus, uint8_t slot)
{
pciDevice_t *pciDevice = initDevice(bus, slot, 0);
if(pciDevice != NULL)
{
patchDevice(pciDevice);
list_push(pciDevices, pciDevice);
if(pciDevice->HeaderType & 0x80) //Mehrere Funktionen werden unterstützt
{
//Überprüfe jede Funktion
uint8_t func;
for(func = 1; func < PCIFUNCS; func++)
{
pciDevice = initDevice(bus, slot, func);
if(pciDevice != NULL)
list_push(pciDevices, pciDevice);
}
}
}
}
void pci_Init()
{
pciDevices = list_create();
printf(" =>PCI:\n");
uint16_t bus;
uint8_t slot;
for(bus = 0; bus < PCIBUSES; bus++)
for(slot = 0; slot < PCISLOTS; slot++)
checkSlot(bus, slot);
SysLog("PCI", "Initialisierung abgeschlossen");
printf("%u Geraete gefunden\n", list_size(pciDevices));
}
uint32_t pci_readConfig(uint8_t bus, uint8_t slot, uint8_t func, uint8_t reg, uint8_t length)
{
uint32_t Data = 0;
//Adressse generieren und schreiben
outd(CONFIG_ADDRESS,
(bus << 16)
| (slot << 11)
| (func << 8)
| (reg & 0xFC)
| 0x80000000);
//Daten einlesen
Data = ind(CONFIG_DATA) >> ((reg & ~0xFC) * 8);
switch(length)
{
case 1:
Data &= 0xFF;
break;
case 2:
Data &= 0xFFFF;
break;
case 4:
Data &= 0xFFFFFFFF;
break;
}
return Data;
}
void pci_writeConfig(uint8_t bus, uint8_t slot, uint8_t func, uint8_t reg, uint8_t length, uint32_t Data)
{
//Adressse generieren und schreiben
outd(CONFIG_ADDRESS,
(bus << 16)
| (slot << 11)
| (func << 8)
| (reg & 0xFC)
| 0x80000000);
//Daten schreiben
switch(length)
{
case 1:
outb(CONFIG_DATA + (reg & 0x3), Data);
break;
case 2:
outw(CONFIG_DATA + (reg & 0x2), Data);
break;
case 4:
outd(CONFIG_DATA, Data);
break;
}
}