diff --git a/.github/workflows/template-cleanup.yml b/.github/workflows/template-cleanup.yml new file mode 100644 index 0000000..8c394eb --- /dev/null +++ b/.github/workflows/template-cleanup.yml @@ -0,0 +1,62 @@ +# Workflow to cleanup projects created from this template +# Adapted from workflow of the same name in https://github.com/JetBrains/intellij-platform-plugin-template +# SPDX-License-Identifier: Apache-2.0 + +name: Template Cleanup +on: + push: + branches: [main] + +jobs: + # Triggered on first push to repos created from the template + template-cleanup: + name: Template Cleanup + permissions: + contents: write + runs-on: ubuntu-latest + if: github.event.repository.name != 'chisel-template' + steps: + + - name: Checkout + uses: actions/checkout@v4 + with: + # These are needed to make ad-m/github-push-action work + # https://github.com/ad-m/github-push-action/tree/d91a481090679876dfc4178fef17f286781251df#example-workflow-file + persist-credentials: false + fetch-depth: 0 + + - name: Cleanup + run: | + export LC_CTYPE=C + export LANG=C + + # Prepare variables + NAME="${GITHUB_REPOSITORY##*/}" + ORG="$GITHUB_REPOSITORY_OWNER" + SAFE_ORG=$(echo $ORG | sed 's/[^a-zA-Z0-9]//g' | tr '[:upper:]' '[:lower:]') + GROUP="com.github.$SAFE_ORG" + + # Replace placeholders + sed -i "s/%NAME%/$NAME/g" build.sbt build.sc README.md src/test/scala/gcd/* + sed -i "s/%REPOSITORY%/${GITHUB_REPOSITORY/\//\\/}/g" README.md + sed -i "s/%ORGANIZATION%/$GROUP/g" build.sbt + + # Remove lines marked with #REMOVE-ON-CLEANUP# + sed -i '/#REMOVE-ON-CLEANUP#/d' README.md + + rm -rf \ + .github/workflows/template-cleanup.yml \ + LICENSE + + - name: Commit + run: | + git config --local user.email "action@github.com" + git config --local user.name "GitHub Action" + git add . + git commit -m "Template cleanup" + + - name: Push changes + uses: ad-m/github-push-action@v0.8.0 + with: + branch: main + github_token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 0000000..cbd456f --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,59 @@ +name: Continuous Integration + +on: + push: + tags: ['*'] + branches: ['main'] + pull_request: + workflow_dispatch: + +env: + verilator-version: v5.012 + verilator-install-dir: verilator-install + +jobs: + ci: + name: ci + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v4 + - name: Cleanup + run: sed -i "s/%NAME%/test/g" build.sc + - name: Cache Scala + uses: coursier/cache-action@v6 + - name: Setup Scala + uses: coursier/setup-action@v1 + with: + jvm: adopt:11 + apps: sbt mill + - name: Setup Dependencies + run: | + sudo apt-get install ccache + - name: Get Cached Verilator + id: get-cached-verilator + uses: actions/cache@v4 + with: + path: ${{ env.verilator-install-dir }} + key: verilator-${{ env.verilator-version }} + - name: Install Verilator + if: steps.get-cached-verilator.outputs.cache-hit != 'true' + run: | + sudo apt-get install git help2man perl python3 make autoconf g++ flex bison numactl perl-doc libfl-dev + git clone https://github.com/verilator/verilator + unset VERILATOR_ROOT + cd verilator + git checkout ${{ env.verilator-version }} + autoconf + ./configure --prefix=$(pwd)/../${{ env.verilator-install-dir }} + make + make install + - name: Set PATH + run: | + echo "$(pwd)/${{ env.verilator-install-dir }}/bin" >> $GITHUB_PATH + echo VERILATOR_ROOT="$(pwd)/${{ env.verilator-install-dir }}/share/verilator" >> $GITHUB_ENV + ln -sf $(pwd)/${{ env.verilator-install-dir }}/bin/verilator_bin $(pwd)/${{ env.verilator-install-dir }}/share/verilator/verilator_bin + - name: SBT Test + run: sbt test + - name: mill Test + run: mill _.test diff --git a/.gitignore b/.gitignore index 6f33875..12033d3 100644 --- a/.gitignore +++ b/.gitignore @@ -1,7 +1,6 @@ -# Created by https://www.toptal.com/developers/gitignore/api/xilinxise -# Edit at https://www.toptal.com/developers/gitignore?templates=xilinxise - -### XilinxISE ### +### Project Specific stuff +test_run_dir/* +### XilinxISE template # intermediate build files *.bgn *.bit @@ -46,16 +45,6 @@ *_usage.xml *_xst.xrpt -# iMPACT generated files -_impactbatch.log -impact.xsl -impact_impact.xwbt -ise_impact.cmd -webtalk_impact.xml - -# Core Generator generated files -xaw2verilog.log - # project-wide generated files *.gise par_usage_statistics.html @@ -65,10 +54,288 @@ webtalk_pn.xml # generated folders iseconfig/ -isim/ xlnx_auto_0_xdb/ xst/ _ngo/ _xmsgs/ +### Eclipse template +*.pydevproject +.metadata +.gradle +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.settings/ +.loadpath + +# Eclipse Core +.project + +# External tool builders +.externalToolBuilders/ + +# Locally stored "Eclipse launch configurations" +*.launch + +# CDT-specific +.cproject + +# JDT-specific (Eclipse Java Development Tools) +.classpath + +# Java annotation processor (APT) +.factorypath + +# PDT-specific +.buildpath + +# sbteclipse plugin +.target + +# TeXlipse plugin +.texlipse +### C template +# Object files +*.o +*.ko +*.obj +*.elf + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +### SBT template +# Simple Build Tool +# http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control + +target/ +lib_managed/ +src_managed/ +project/boot/ +.history +.cache +### Emacs template +# -*- mode: gitignore; -*- +*~ +\#*\# +/.emacs.desktop +/.emacs.desktop.lock +*.elc +auto-save-list +tramp +.\#* + +# Org-mode +.org-id-locations +*_archive + +# flymake-mode +*_flymake.* + +# eshell files +/eshell/history +/eshell/lastdir + +# elpa packages +/elpa/ + +# reftex files +*.rel + +# AUCTeX auto folder +/auto/ + +# cask packages +.cask/ +### Vim template +[._]*.s[a-w][a-z] +[._]s[a-w][a-z] +*.un~ +Session.vim +.netrwhist +*~ +### JetBrains template +# Covers JetBrains IDEs: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio + +*.iml + +## Directory-based project format: +.idea/ +# if you remove the above rule, at least ignore the following: + +# User-specific stuff: +# .idea/workspace.xml +# .idea/tasks.xml +# .idea/dictionaries + +# Sensitive or high-churn files: +# .idea/dataSources.ids +# .idea/dataSources.xml +# .idea/sqlDataSources.xml +# .idea/dynamic.xml +# .idea/uiDesigner.xml + +# Gradle: +# .idea/gradle.xml +# .idea/libraries + +# Mongo Explorer plugin: +# .idea/mongoSettings.xml + +## File-based project format: +*.ipr +*.iws + +## Plugin-specific files: + +# IntelliJ +/out/ + +# mpeltonen/sbt-idea plugin +.idea_modules/ + +# JIRA plugin +atlassian-ide-plugin.xml + +# Crashlytics plugin (for Android Studio and IntelliJ) +com_crashlytics_export_strings.xml +crashlytics.properties +crashlytics-build.properties +### C++ template +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app +### OSX template +.DS_Store +.AppleDouble +.LSOverride + +# Icon must end with two \r +Icon + +# Thumbnails +._* + +# Files that might appear in the root of a volume +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns + +# Directories potentially created on remote AFP share +.AppleDB +.AppleDesktop +Network Trash Folder +Temporary Items +.apdisk +### Xcode template +# Xcode +# +# gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore + +## Build generated +build/ +DerivedData + +## Various settings +*.pbxuser +!default.pbxuser +*.mode1v3 +!default.mode1v3 +*.mode2v3 +!default.mode2v3 +*.perspectivev3 +!default.perspectivev3 +xcuserdata + +## Other +*.xccheckout +*.moved-aside +*.xcuserstate +### Scala template +*.class +*.log +/.bsp + +# sbt specific +.cache +.history +.lib/ +dist/* +target/ +lib_managed/ +src_managed/ +project/boot/ +project/plugins/project/ + +# Scala-IDE specific +.scala_dependencies +.worksheet +### Java template +*.class + +# Mobile Tools for Java (J2ME) +.mtj.tmp/ + +# Package Files # +*.jar +*.war +*.ear + +# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml +hs_err_pid* -# End of https://www.toptal.com/developers/gitignore/api/xilinxise diff --git a/.mill-version b/.mill-version new file mode 100644 index 0000000..62d5dbd --- /dev/null +++ b/.mill-version @@ -0,0 +1 @@ +0.11.5 diff --git a/LICENSE b/LICENSE index f288702..68a49da 100644 --- a/LICENSE +++ b/LICENSE @@ -1,674 +1,24 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. + +In jurisdictions that recognize copyright laws, the author or authors +of this software dedicate any and all copyright interest in the +software to the public domain. We make this dedication for the benefit +of the public at large and to the detriment of our heirs and +successors. We intend this dedication to be an overt act of +relinquishment in perpetuity of all present and future rights to this +software under copyright law. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +For more information, please refer to diff --git a/README.md b/README.md index 356e05e..db79f5a 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,111 @@ -# clkr -HyperDbg's HDL module for hardware-level debugging +Chisel Project Template +======================= + +You've done the [Chisel Bootcamp](https://github.com/freechipsproject/chisel-bootcamp), and now you +are ready to start your own Chisel project. The following procedure should get you started +with a clean running [Chisel3](https://www.chisel-lang.org/) project. + +## Make your own Chisel3 project + +### Dependencies + +#### JDK 8 or newer + +We recommend LTS releases Java 8 and Java 11. You can install the JDK as your operating system recommends, or use the prebuilt binaries from [AdoptOpenJDK](https://adoptopenjdk.net/). + +#### SBT or mill + +SBT is the most common build tool in the Scala community. You can download it [here](https://www.scala-sbt.org/download.html). +mill is another Scala/Java build tool without obscure DSL like SBT. You can download it [here](https://github.com/com-lihaoyi/mill/releases) + +#### Verilator + +The test with `svsim` needs Verilator installed. +See Verilator installation instructions [here](https://verilator.org/guide/latest/install.html). + +### How to get started + +#### Create a repository from the template + +This repository is a Github template. You can create your own repository from it by clicking the green `Use this template` in the top right. +Please leave `Include all branches` **unchecked**; checking it will pollute the history of your new repository. +For more information, see ["Creating a repository from a template"](https://docs.github.com/en/free-pro-team@latest/github/creating-cloning-and-archiving-repositories/creating-a-repository-from-a-template). + +#### Wait for the template cleanup workflow to complete + +After using the template to create your own blank project, please wait a minute or two for the `Template cleanup` workflow to run which will removes some template-specific stuff from the repository (like the LICENSE). +Refresh the repository page in your browser until you see a 2nd commit by `actions-user` titled `Template cleanup`. + + +#### Clone your repository + +Once you have created a repository from this template and the `Template cleanup` workflow has completed, you can click the green button to get a link for cloning your repository. +Note that it is easiest to push to a repository if you set up SSH with Github, please see the [related documentation](https://docs.github.com/en/free-pro-team@latest/github/authenticating-to-github/connecting-to-github-with-ssh). SSH is required for pushing to a Github repository when using two-factor authentication. + +```sh +git clone git@github.com:%REPOSITORY%.git +cd %NAME% +``` +(The variables wrapped in `%` will be filled in by the template cleanup) + +#### Set project organization and name in build.sbt + +The cleanup workflow will have attempted to provide sensible defaults for `ThisBuild / organization` and `name` in the `build.sbt`. +Feel free to use your text editor of choice to change them as you see fit. + +#### Clean up the README.md file + +Again, use you editor of choice to make the README specific to your project. + +#### Add a LICENSE file + +It is important to have a LICENSE for open source (or closed source) code. +This template repository has the Unlicense in order to allow users to add any license they want to derivative code. +The Unlicense is stripped when creating a repository from this template so that users do not accidentally unlicense their own work. + +For more information about a license, check out the [Github Docs](https://docs.github.com/en/free-pro-team@latest/github/building-a-strong-community/adding-a-license-to-a-repository). + +#### Commit your changes +```sh +git commit -m 'Starting %NAME%' +git push origin main +``` + +### Did it work? + +You should now have a working Chisel3 project. + +You can run the included test with: +```sh +sbt test +``` + +Alternatively, if you use Mill: +```sh +mill %NAME%.test +``` + +You should see a whole bunch of output that ends with something like the following lines +``` +[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0 +[info] All tests passed. +[success] Total time: 5 s, completed Dec 16, 2020 12:18:44 PM +``` +If you see the above then... + +### It worked! + +You are ready to go. We have a few recommended practices and things to do. + +* Use packages and following conventions for [structure](https://www.scala-sbt.org/1.x/docs/Directories.html) and [naming](http://docs.scala-lang.org/style/naming-conventions.html) +* Package names should be clearly reflected in the testing hierarchy +* Build tests for all your work +* Read more about testing in SBT in the [SBT docs](https://www.scala-sbt.org/1.x/docs/Testing.html) +* This template includes a [test dependency](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html#Per-configuration+dependencies) on [ScalaTest](https://www.scalatest.org/). This, coupled with `svsim` (included with Chisel) and `verilator`, are a starting point for testing Chisel generators. + * You can remove this dependency in the build.sbt file if you want to +* Change the name of your project in the build.sbt file +* Change your README.md + +## Problems? Questions? + +Check out the [Chisel Users Community](https://www.chisel-lang.org/community.html) page for links to get in contact! diff --git a/build.sbt b/build.sbt new file mode 100644 index 0000000..9742b43 --- /dev/null +++ b/build.sbt @@ -0,0 +1,24 @@ +// See README.md for license details. + +ThisBuild / scalaVersion := "2.13.12" +ThisBuild / version := "0.1.0" +ThisBuild / organization := "%ORGANIZATION%" + +val chiselVersion = "6.0.0" + +lazy val root = (project in file(".")) + .settings( + name := "%NAME%", + libraryDependencies ++= Seq( + "org.chipsalliance" %% "chisel" % chiselVersion, + "org.scalatest" %% "scalatest" % "3.2.16" % "test", + ), + scalacOptions ++= Seq( + "-language:reflectiveCalls", + "-deprecation", + "-feature", + "-Xcheckinit", + "-Ymacro-annotations", + ), + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), + ) diff --git a/build.sc b/build.sc new file mode 100644 index 0000000..0addcbe --- /dev/null +++ b/build.sc @@ -0,0 +1,30 @@ +// import Mill dependency +import mill._ +import mill.define.Sources +import mill.modules.Util +import mill.scalalib.TestModule.ScalaTest +import scalalib._ +// support BSP +import mill.bsp._ + +object %NAME% extends SbtModule { m => + override def millSourcePath = os.pwd + override def scalaVersion = "2.13.12" + override def scalacOptions = Seq( + "-language:reflectiveCalls", + "-deprecation", + "-feature", + "-Xcheckinit", + ) + override def ivyDeps = Agg( + ivy"org.chipsalliance::chisel:6.0.0", + ) + override def scalacPluginIvyDeps = Agg( + ivy"org.chipsalliance:::chisel-plugin:6.0.0", + ) + object test extends SbtModuleTests with TestModule.ScalaTest { + override def ivyDeps = m.ivyDeps() ++ Agg( + ivy"org.scalatest::scalatest::3.2.16" + ) + } +} diff --git a/clkr/RAM.vhd b/clkr/RAM.vhd deleted file mode 100644 index c5c43de..0000000 --- a/clkr/RAM.vhd +++ /dev/null @@ -1,74 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - --- A 128x8 single-port RAM in VHDL -ENTITY RAM IS - PORT ( - RAM_ADDR : IN std_logic_vector(6 DOWNTO 0); -- Address to write/read RAM - RAM_DATA_IN : IN std_logic_vector(7 DOWNTO 0); -- Data to write into RAM - RAM_WR : IN std_logic; -- Write enable - RAM_CLOCK : IN std_logic; -- clock input for RAM - RAM_DATA_OUT : OUT std_logic_vector(7 DOWNTO 0) -- Data output of RAM - ); -END RAM; - -ARCHITECTURE Behavioral OF RAM IS - - -- define the new type for the 128x8 RAM - TYPE RAM_ARRAY IS ARRAY (0 TO 127) OF std_logic_vector (7 DOWNTO 0); - - -- initial values in the RAM - SIGNAL RAM : RAM_ARRAY := ( - x"55", x"66", x"77", x"67", -- 0x00: - x"99", x"00", x"00", x"11", -- 0x04: - x"00", x"00", x"00", x"00", -- 0x08: - x"00", x"00", x"00", x"00", -- 0x0C: - x"00", x"00", x"00", x"00", -- 0x10: - x"00", x"00", x"00", x"00", -- 0x14: - x"00", x"00", x"00", x"00", -- 0x18: - x"00", x"00", x"00", x"00", -- 0x1C: - x"00", x"00", x"00", x"00", -- 0x20: - x"00", x"00", x"00", x"00", -- 0x24: - x"00", x"00", x"00", x"00", -- 0x28: - x"00", x"00", x"00", x"00", -- 0x2C: - x"00", x"00", x"00", x"00", -- 0x30: - x"00", x"00", x"00", x"00", -- 0x34: - x"00", x"00", x"00", x"00", -- 0x38: - x"00", x"00", x"00", x"00", -- 0x3C: - x"00", x"00", x"00", x"00", -- 0x40: - x"00", x"00", x"00", x"00", -- 0x44: - x"00", x"00", x"00", x"00", -- 0x48: - x"00", x"00", x"00", x"00", -- 0x4C: - x"00", x"00", x"00", x"00", -- 0x50: - x"00", x"00", x"00", x"00", -- 0x54: - x"00", x"00", x"00", x"00", -- 0x58: - x"00", x"00", x"00", x"00", -- 0x5C: - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00", - x"00", x"00", x"00", x"00" - ); -BEGIN - - PROCESS (RAM_CLOCK) - BEGIN - IF (rising_edge(RAM_CLOCK)) THEN - IF (RAM_WR = '1') THEN -- when write enable = 1, - -- write input data into RAM at the provided address - RAM(to_integer(unsigned(RAM_ADDR))) <= RAM_DATA_IN; - - -- The index of the RAM array type needs to be integer so - -- converts RAM_ADDR from std_logic_vector -> Unsigned -> Interger using numeric_std library - END IF; - END IF; - END PROCESS; - - -- Data to be read out - RAM_DATA_OUT <= RAM(to_integer(unsigned(RAM_ADDR))); - -END Behavioral; \ No newline at end of file diff --git a/clkr/RAM_INIT_isim_beh.exe b/clkr/RAM_INIT_isim_beh.exe deleted file mode 100644 index fb891a9..0000000 Binary files a/clkr/RAM_INIT_isim_beh.exe and /dev/null differ diff --git a/clkr/REGISTER_FILE_isim_beh.exe b/clkr/REGISTER_FILE_isim_beh.exe deleted file mode 100644 index fb891a9..0000000 Binary files a/clkr/REGISTER_FILE_isim_beh.exe and /dev/null differ diff --git a/clkr/RamInit.vhd b/clkr/RamInit.vhd deleted file mode 100644 index d6861d2..0000000 --- a/clkr/RamInit.vhd +++ /dev/null @@ -1,34 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_TEXTIO.ALL; - -LIBRARY STD; - -USE STD.TEXTIO.ALL; - -ENTITY RAM_INIT IS - PORT ( - CLK : IN STD_LOGIC; - PERFORM_INIT : IN STD_LOGIC - ); -END RAM_INIT; - -ARCHITECTURE Behavioral OF RAM_INIT IS - - FILE FIN : TEXT OPEN READ_MODE IS "input.dat"; - -BEGIN - - PROCESS (CLK) - VARIABLE RD_LINE : LINE; - VARIABLE HEX : STD_LOGIC_VECTOR(3 DOWNTO 0); - BEGIN - IF PERFORM_INIT = '1' THEN - WHILE NOT ENDFILE(FIN) LOOP - readline(FIN, RD_LINE); - hread(RD_LINE, HEX); - END LOOP; - END IF; - END PROCESS; - -END Behavioral; \ No newline at end of file diff --git a/clkr/RegFile.vhd b/clkr/RegFile.vhd deleted file mode 100644 index 9d6aaa1..0000000 --- a/clkr/RegFile.vhd +++ /dev/null @@ -1,43 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY REGISTER_FILE IS - PORT ( - OUT_REG_A : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - OUT_REG_B : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - INPUT_VAL : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - WRITE_ENABLE : IN STD_LOGIC; - SEL_REG_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - SEL_REG_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - WRITE_REG_SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - CLK : IN STD_LOGIC - ); -END REGISTER_FILE; - -ARCHITECTURE Behavioral OF REGISTER_FILE IS - TYPE REGISTER_FILE_TYPE IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL REGISTERS : REGISTER_FILE_TYPE; -BEGIN - - RegFile : PROCESS (CLK) IS - BEGIN - IF rising_edge(CLK) THEN - - -- Read A and B before bypass - OUT_REG_A <= registers(to_integer(unsigned(SEL_REG_A))); - OUT_REG_B <= registers(to_integer(unsigned(SEL_REG_B))); - - -- Write and bypass - IF WRITE_ENABLE = '1' THEN - registers(to_integer(unsigned(WRITE_REG_SEL))) <= INPUT_VAL; -- Write - IF SEL_REG_A = WRITE_REG_SEL THEN -- Bypass for read A - OUT_REG_A <= INPUT_VAL; - END IF; - IF SEL_REG_B = WRITE_REG_SEL THEN -- Bypass for read B - OUT_REG_B <= INPUT_VAL; - END IF; - END IF; - END IF; - END PROCESS; -END Behavioral; \ No newline at end of file diff --git a/clkr/TOP_isim_beh1.wdb b/clkr/TOP_isim_beh1.wdb deleted file mode 100644 index 6f8bfa7..0000000 Binary files a/clkr/TOP_isim_beh1.wdb and /dev/null differ diff --git a/clkr/Top.vhd b/clkr/Top.vhd deleted file mode 100644 index 4b89c41..0000000 --- a/clkr/Top.vhd +++ /dev/null @@ -1,72 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; - -ENTITY TOP IS - PORT (INPUT_CLK : IN STD_LOGIC_VECTOR (0 DOWNTO 0)); -END TOP; - -ARCHITECTURE Behavioral OF TOP IS - - -- RAM signals - SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000100"; - SIGNAL RAM_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL RAM_WR : STD_LOGIC; - SIGNAL RAM_CLOCK : STD_LOGIC; - SIGNAL RAM_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- RAM initialization signal - SIGNAL IS_RAM_INITALIZED : STD_LOGIC := '0'; - SIGNAL PERFORM_RAM_INIT : STD_LOGIC := '0'; - - -- Clock signal for testing purposes - SIGNAL CLK : STD_LOGIC := '0'; - - -- Instantiate components - COMPONENT RAM - PORT ( - RAM_ADDR : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- Address to write/read RAM - RAM_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data to write into RAM - RAM_WR : IN STD_LOGIC; -- Write enable - RAM_CLOCK : IN STD_LOGIC; -- clock input for RAM - RAM_DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Data output of RAM - ); - END COMPONENT; - - COMPONENT RAM_INIT - PORT ( - CLK : IN STD_LOGIC; - PERFORM_INIT : IN STD_LOGIC - ); - END COMPONENT; - -BEGIN - - -- Using RAM - RAM_UNT: RAM PORT MAP (RAM_ADDR => RAM_ADDR, - RAM_DATA_IN => RAM_DATA_IN, - RAM_WR => RAM_WR, - RAM_CLOCK => CLK, - RAM_DATA_OUT => RAM_DATA_OUT - ); - - -- Initialize RAM - RAM_INITIALIZE: RAM_INIT PORT MAP (CLK => CLK, - PERFORM_INIT => PERFORM_RAM_INIT - ); - - PROCESS - BEGIN - IF IS_RAM_INITALIZED = '0' - THEN - PERFORM_RAM_INIT <= '1'; - END IF; - END PROCESS; - - -- Create testing signal - PROCESS - BEGIN - CLK <= NOT CLK; - WAIT FOR 1 ns; - END PROCESS; - -END Behavioral; \ No newline at end of file diff --git a/clkr/Top_isim_beh.exe b/clkr/Top_isim_beh.exe deleted file mode 100644 index fb891a9..0000000 Binary files a/clkr/Top_isim_beh.exe and /dev/null differ diff --git a/clkr/Top_isim_beh.wdb b/clkr/Top_isim_beh.wdb deleted file mode 100644 index 3fdede4..0000000 Binary files a/clkr/Top_isim_beh.wdb and /dev/null differ diff --git a/clkr/clkr.xise b/clkr/clkr.xise deleted file mode 100644 index 4dad1b3..0000000 --- a/clkr/clkr.xise +++ /dev/null @@ -1,352 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/clkr/fuse.log b/clkr/fuse.log deleted file mode 100644 index 344577e..0000000 --- a/clkr/fuse.log +++ /dev/null @@ -1,25 +0,0 @@ -Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe -prj C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_beh.prj work.TOP -ISim P.20131013 (signature 0x7708f090) -Number of CPUs detected in this system: 8 -Turning on mult-threading, number of parallel sub-compilation jobs: 16 -Determining compilation order of HDL files -Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/RamInit.vhd" into library work -Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/RAM.vhd" into library work -Parsing VHDL file "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" into library work -WARNING:HDLCompiler:1369 - "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" Line 57: Possible infinite loop; process does not have a wait statement -Starting static elaboration -Completed static elaboration -Compiling package standard -Compiling package std_logic_1164 -Compiling package numeric_std -Compiling package textio -Compiling package std_logic_textio -Compiling architecture behavioral of entity RAM [ram_default] -Compiling architecture behavioral of entity RAM_INIT [ram_init_default] -Compiling architecture behavioral of entity top -Time Resolution for simulation is 1ps. -Waiting for 1 sub-compilation(s) to finish... -Compiled 10 VHDL Units -Built simulation executable C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe -Fuse Memory Usage: 36456 KB -Fuse CPU Usage: 640 ms diff --git a/clkr/fuse.xmsgs b/clkr/fuse.xmsgs deleted file mode 100644 index a20abda..0000000 --- a/clkr/fuse.xmsgs +++ /dev/null @@ -1,12 +0,0 @@ - - - -"C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" Line 57: Possible infinite loop; process does not have a wait statement - - - - diff --git a/clkr/fuseRelaunch.cmd b/clkr/fuseRelaunch.cmd deleted file mode 100644 index 32e102a..0000000 --- a/clkr/fuseRelaunch.cmd +++ /dev/null @@ -1 +0,0 @@ --intstyle "ise" -incremental -o "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.exe" -prj "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_beh.prj" "work.TOP" diff --git a/clkr/input.dat b/clkr/input.dat deleted file mode 100644 index 87e7edb..0000000 --- a/clkr/input.dat +++ /dev/null @@ -1,5 +0,0 @@ -55 -85 -69 -55 -55 \ No newline at end of file diff --git a/clkr/isim.cmd b/clkr/isim.cmd deleted file mode 100644 index fff18e8..0000000 --- a/clkr/isim.cmd +++ /dev/null @@ -1,3 +0,0 @@ -onerror {resume} -wave add / -run 1000 ns; diff --git a/clkr/isim.log b/clkr/isim.log deleted file mode 100644 index 8592119..0000000 --- a/clkr/isim.log +++ /dev/null @@ -1,30 +0,0 @@ -ISim log file -Running: C:\Users\sina\Desktop\HyperDbg\clkr\clkr\TOP_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/sina/Desktop/HyperDbg/clkr/clkr/TOP_isim_beh.wdb -ISim P.20131013 (signature 0x7708f090) ----------------------------------------------------------------------- -INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set. -INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set. -INFO:Security:68a - user is sina, on host DESKTOP-8H0ML4R. -WARNING:Security:43 - No license file was found in the standard Xilinx license directory. -WARNING:Security:44 - Since no license file was found, - please run the Xilinx License Configuration Manager - (xlcm or "Manage Xilinx Licenses") - to assist in obtaining a license. -ERROR:Security:14 - No feature was available for 'ISIM'. - -No such feature exists. -Feature: ISIM -License path: C:/.Xilinx;C:\Xilinx\14.7\ISE_DS\ISE\/coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE\/coregen/core_licenses\XilinxFree.lic;C:\Xilinx\14.7\ISE_DS\EDK/data/core_licenses\Xilinx.lic; -FLEXnet Licensing error:-5,357 -For further information, refer to the FLEXnet Licensing documentation, -available at "www.flexerasoftware.com". ----------------------------------------------------------------------- -WARNING: A full ISim License cannot be checked out due to the issues listed above. Please use Xilinx License Configuration Manager to fix these issues in order to check out a full ISim license. -WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. -This is a Lite version of ISim. -Time resolution is 1 ps -# onerror resume -# wave add / -# run 1000 ns -Simulator is doing circuit initialization process. -Stopped at time : 0 fs : File "C:/Users/sina/Desktop/HyperDbg/clkr/clkr/Top.vhd" Line 59 diff --git a/clkr/xilinxsim.ini b/clkr/xilinxsim.ini deleted file mode 100644 index 600496d..0000000 --- a/clkr/xilinxsim.ini +++ /dev/null @@ -1 +0,0 @@ -work=isim/work diff --git a/project/build.properties b/project/build.properties new file mode 100644 index 0000000..b19d4e1 --- /dev/null +++ b/project/build.properties @@ -0,0 +1 @@ +sbt.version = 1.9.7 diff --git a/project/plugins.sbt b/project/plugins.sbt new file mode 100644 index 0000000..5708f81 --- /dev/null +++ b/project/plugins.sbt @@ -0,0 +1 @@ +logLevel := Level.Warn diff --git a/src/main/scala/gcd/DecoupledGCD.scala b/src/main/scala/gcd/DecoupledGCD.scala new file mode 100644 index 0000000..1cd2993 --- /dev/null +++ b/src/main/scala/gcd/DecoupledGCD.scala @@ -0,0 +1,73 @@ +// See README.md for license details. + +package gcd + +import chisel3._ +import chisel3.util.Decoupled + +class GcdInputBundle(val w: Int) extends Bundle { + val value1 = UInt(w.W) + val value2 = UInt(w.W) +} + +class GcdOutputBundle(val w: Int) extends Bundle { + val value1 = UInt(w.W) + val value2 = UInt(w.W) + val gcd = UInt(w.W) +} + +/** + * Compute Gcd using subtraction method. + * Subtracts the smaller from the larger until register y is zero. + * value input register x is then the Gcd. + * Unless first input is zero then the Gcd is y. + * Can handle stalls on the producer or consumer side + */ +class DecoupledGcd(width: Int) extends Module { + val input = IO(Flipped(Decoupled(new GcdInputBundle(width)))) + val output = IO(Decoupled(new GcdOutputBundle(width))) + + val xInitial = Reg(UInt()) + val yInitial = Reg(UInt()) + val x = Reg(UInt()) + val y = Reg(UInt()) + val busy = RegInit(false.B) + val resultValid = RegInit(false.B) + + input.ready := ! busy + output.valid := resultValid + output.bits := DontCare + + when(busy) { + when(x > y) { + x := x - y + }.otherwise { + y := y - x + } + when(x === 0.U || y === 0.U) { + when(x === 0.U) { + output.bits.gcd := y + }.otherwise { + output.bits.gcd := x + } + + output.bits.value1 := xInitial + output.bits.value2 := yInitial + resultValid := true.B + + when(output.ready && resultValid) { + busy := false.B + resultValid := false.B + } + } + }.otherwise { + when(input.valid) { + val bundle = input.deq() + x := bundle.value1 + y := bundle.value2 + xInitial := bundle.value1 + yInitial := bundle.value2 + busy := true.B + } + } +} diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala new file mode 100644 index 0000000..07e434c --- /dev/null +++ b/src/main/scala/gcd/GCD.scala @@ -0,0 +1,34 @@ +// See README.md for license details. + +package gcd + +import chisel3._ + +/** + * Compute GCD using subtraction method. + * Subtracts the smaller from the larger until register y is zero. + * value in register x is then the GCD + */ +class GCD extends Module { + val io = IO(new Bundle { + val value1 = Input(UInt(16.W)) + val value2 = Input(UInt(16.W)) + val loadingValues = Input(Bool()) + val outputGCD = Output(UInt(16.W)) + val outputValid = Output(Bool()) + }) + + val x = Reg(UInt()) + val y = Reg(UInt()) + + when(x > y) { x := x - y } + .otherwise { y := y - x } + + when(io.loadingValues) { + x := io.value1 + y := io.value2 + } + + io.outputGCD := x + io.outputValid := y === 0.U +} diff --git a/src/test/scala/gcd/GCDSpec.scala b/src/test/scala/gcd/GCDSpec.scala new file mode 100644 index 0000000..e8c7ce8 --- /dev/null +++ b/src/test/scala/gcd/GCDSpec.scala @@ -0,0 +1,68 @@ +// See README.md for license details. + +package gcd + +import chisel3._ +import chisel3.experimental.BundleLiterals._ +import chisel3.simulator.EphemeralSimulator._ +import org.scalatest.freespec.AnyFreeSpec +import org.scalatest.matchers.must.Matchers + +/** + * This is a trivial example of how to run this Specification + * From within sbt use: + * {{{ + * testOnly gcd.GCDSpec + * }}} + * From a terminal shell use: + * {{{ + * sbt 'testOnly gcd.GCDSpec' + * }}} + * Testing from mill: + * {{{ + * mill %NAME%.test.testOnly gcd.GCDSpec + * }}} + */ +class GCDSpec extends AnyFreeSpec with Matchers { + + "Gcd should calculate proper greatest common denominator" in { + simulate(new DecoupledGcd(16)) { dut => + val testValues = for { x <- 0 to 10; y <- 0 to 10} yield (x, y) + val inputSeq = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) } + val resultSeq = testValues.map { case (x, y) => + (new GcdOutputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U) + } + + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + dut.clock.step() + + var sent, received, cycles: Int = 0 + while (sent != 100 && received != 100) { + assert(cycles <= 1000, "timeout reached") + + if (sent < 100) { + dut.input.valid.poke(true.B) + dut.input.bits.value1.poke(testValues(sent)._1.U) + dut.input.bits.value2.poke(testValues(sent)._2.U) + if (dut.input.ready.peek().litToBoolean) { + sent += 1 + } + } + + if (received < 100) { + dut.output.ready.poke(true.B) + if (dut.output.valid.peekValue().asBigInt == 1) { + dut.output.bits.gcd.expect(BigInt(testValues(received)._1).gcd(testValues(received)._2)) + received += 1 + } + } + + // Step the simulation forward. + dut.clock.step() + cycles += 1 + } + } + } +}