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<span class="title">01 June 2024 <span class="count">(1 messages)</span></span>
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OK,thank you
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Joined.
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Joined.
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Joined.
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<span class="title">04 June 2024 <span class="count">(75 messages)</span></span>
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<span class="date">09:30 AM, 04 Jun 2024</span>
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Joined.
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<a class="id" href="#6420">#6420</a>
<span class="date">12:57 PM, 04 Jun 2024</span>
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Guys,
<br />Has anyone previously seen any sample of setting up a TSS (Task State Segment) for a hypervisor?
<br />
<br />https://github.com/HyperDbg/HyperDbg/blob/834b43ece965c75bd65761386384a539bd1a3973/hyperdbg/hprdbghv/code/memory/Segmentation.c#L123C5-L123C6
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<a class="reply" href="2024-06.html#6420">↶ Reply to #6420</a>
<a class="id" href="#6421">#6421</a>
<span class="date">12:58 PM, 04 Jun 2024</span>
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<div class="text">
Been working on setting a separate TSS (instead of Windows TSS) for HyperDbg, but not sure if I correctly implemented it since the interrupt stack is not within the range. 🤔
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<a class="reply" href="2024-06.html#6420">↶ Reply to #6420</a>
<a class="id" href="#6422">#6422</a>
<span class="date">01:00 PM, 04 Jun 2024</span>
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It still perfectly works but if we're unsure about the correctness of the implementation, it probably causes weird problems in the future.
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<a class="id" href="#6423">#6423</a>
<span class="date">01:01 PM, 04 Jun 2024</span>
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(05:19:52.472 - core : 0 - vmx-root? no) [+] Information (SegmentPrepareHostGdt:123) | Host Interrupt Stack, from: ffffe58189199000, to: ffffe5818919cff0
<br />(05:19:52.472 - core : 1 - vmx-root? no) [+] Information (SegmentPrepareHostGdt:123) | Host Interrupt Stack, from: ffffe581891ab000, to: ffffe581891aeff0
<br />(05:19:52.472 - core : 3 - vmx-root? no) [+] Information (SegmentPrepareHostGdt:123) | Host Interrupt Stack, from: ffffe581891cf000, to: ffffe581891d2ff0
<br />(05:19:52.472 - core : 2 - vmx-root? no) [+] Information (SegmentPrepareHostGdt:123) | Host Interrupt Stack, from: ffffe581891bd000, to: ffffe581891c0ff0
<br />
<br />(05:24:27.278 - core : 0 - vmx-root? yes) [+] Information (IdtEmulationhandleHostInterrupt:177) | Host exception, RIP=fffff804383f5a8e, RSP=ffffe58189192ed0, Vector=3
<br />(05:24:27.333 - core : 1 - vmx-root? yes) [+] Information (IdtEmulationhandleHostInterrupt:177) | Host exception, RIP=fffff804383f5a8e, RSP=ffffe581891a4ed0, Vector=3
<br />(05:24:27.259 - core : 2 - vmx-root? yes) [+] Information (IdtEmulationhandleHostInterrupt:177) | Host exception, RIP=fffff804383f5a8e, RSP=ffffe581891b6ed0, Vector=3
<br />(05:24:27.278 - core : 3 - vmx-root? yes) [+] Information (IdtEmulationhandleHostInterrupt:177) | Host exception, RIP=fffff804383f5a8e, RSP=ffffe581891c8ed0, Vector=3
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<a class="id" href="#6424">#6424</a>
<span class="date">01:01 PM, 04 Jun 2024</span>
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<a class="id" href="#6425">#6425</a>
<span class="date">01:03 PM, 04 Jun 2024</span>
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@honorary_bot do have any idea about this?
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<a class="id" href="#6426">#6426</a>
<span class="date">01:08 PM, 04 Jun 2024</span>
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The problem here is that the exception stack is not within the core's allocated range.
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<a class="id" href="#6427">#6427</a>
<span class="date">01:08 PM, 04 Jun 2024</span>
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I don’t remember from top of my head, gonna have to recheck in the evening. So you’ve set up tss stack pointers, but the exception stack is switched to something different in exception?
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<a class="id" href="#6428">#6428</a>
<span class="date">01:08 PM, 04 Jun 2024</span>
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Yes, exactly
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<a class="id" href="#6429">#6429</a>
<span class="date">01:09 PM, 04 Jun 2024</span>
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As stack grows downward, probably I should put the latest (aligned byte address) of the stack. But it seems that Intel didn't mention it. So, not sure whether I should put the base address or the end of the stack.
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<a class="id" href="#6430">#6430</a>
<span class="date">01:09 PM, 04 Jun 2024</span>
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It’s likely just a misconfiguration, but I’ll check how I do that
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