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Layouts contain multi-fingered MOS devices, so CDL and SPICE netlists should be fixed to align with layout
.SUBCKT sg13g2_inv_2 A VDD VSS Y *.PININFO A:I Y:O VDD:B VSS:B MX1 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2 MX0 Y A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2 .ENDS
.SUBCKT sg13g2_inv_2 A VDD VSS Y *.PININFO A:I Y:O VDD:B VSS:B MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1 MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1 .ENDS
There is a check uploaded: https://github.com/IHP-GmbH/IHP-Open-PDK/blob/dev/ihp-sg13g2/libs.qa/stdcells/check_multiplier.sh
The text was updated successfully, but these errors were encountered:
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Layouts contain multi-fingered MOS devices, so CDL and SPICE netlists should be fixed to align with layout
Expected Behavior
Actual Behavior
There is a check uploaded: https://github.com/IHP-GmbH/IHP-Open-PDK/blob/dev/ihp-sg13g2/libs.qa/stdcells/check_multiplier.sh
The text was updated successfully, but these errors were encountered: