Replies: 25 comments
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:-)
Take a look at the full report:
I know is cryptic, but it will collect all schematic and PCB layers generated in SVG format (from Of course you can create a template that is more selective and adds only the SVGs you want (and in the order you want). But the default will generate a good enough report.
Interesting. Does this component have lines in the Edge.Cuts layer? Can you share a small PCB with such a component?
Ok, but we currently don't call Pandoc, so I don't know how can we help here.
Why not? Makefiles can scan files, i.e. by their extension.
Use a special extension, lets say
I'm tempted to create such an image. Not sure if it will be simple. |
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And this is how the sea level risen 1 µm and a couple of insects got extint :-)))
This is from the |
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Thanks for adding this - I started updating a sample project but got interrupted by my son. Regarding the report, I did select the "full" report but did not get any images in the report - I'll check differently. I'll follow up here with a sample project. |
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Here is a testcase with a component representing the board edges. The design is in designs. This is in a github repository . The project yaml is in ./designs/tc5/tc5.kibot.yaml. The report indicates: The measured size is 59.230x26.550mm : And you can see the holes in the boards, also in this 3D view:: |
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Remmember that the template collects SVGs, not PDFs, this is related to the size + quality we already discussed. |
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I hoped so 😉 (and I know). I just get a report not referencing any image, so I need to check into that. |
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The last patch solves it. |
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Now you can play with the |
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The Eurocircuits class for the test case above also needs some tweaking. I uploaded this : I'll be playing more with the report generation as soon as I can. |
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I need a test case. May be you have some pad that has 0 copper, is all drilled, and it generates the problem. |
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I am going to check the reason behind the classification differences. A suggestion:
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I added the last line in the following code in out_report.py: # Drill class
self.drill_class_min = get_drill_class(self.via_drill_min)
self.drill_class = get_drill_class(self.via_drill)
self.drill_class_d = get_drill_class(self.via_drill_d)
logger.debug("Drill class: %s:%s %s:%s %s:%s", self.via_drill_min, self.drill_class_min, self.via_drill, self.drill_class, self.via_drill_d, self.drill_class_d) Which resulted in:
The reports indicates "3F" and Eurocircuits validates the board as 3A . This explains the classification as determined by KiBot of the board I examined. For another board I got "Drill class: 500000:B 500000:B 500000:B " and it is validated by Eurocircuits as a class A as well. (KiBot says it's a 10B board, and its a 4A board). |
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I'm not sure about it. In KiCad you specify the size of the tool, not the size of the hole. KiCad generates drill files using the size you selected. Are you implying that the manufacturer will add 0.1 mm to all the tools in the drill file? The rest: too much words, no example, I can't do anything. |
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For the second board I checked, the TC-2030 footprint I got has some "rounding" differences: 0.991 vs 0.996 for instance. After fixing those, I got:
through the log messages I added like this: # Pattern class
self.pattern_class_min = get_pattern_class(self.track_min, self.clearance, self.oar_min)
logger.debug("Pattern class min: %s %s %s -> %s", self.track_min, self.clearance, self.oar_min, self.pattern_class_min)
self.pattern_class = get_pattern_class(self.track, self.clearance, self.oar)
logger.debug("Pattern class: %s %s %s -> %s", self.track, self.clearance, self.oar, self.pattern_class)
self.pattern_class_d = get_pattern_class(self.track_d, self.clearance, self.oar_d)
logger.debug("Pattern class d: %s %s %s -> %s", self.track_d, self.clearance, self.oar_d, self.pattern_class)
``
And the report mentionned "4B" for the class, so the "4" is correct after fixing the footprint, the "B" has to be "A" for reasons mentionned before. |
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Are you sure the manufacturer will change it? If don't then adding 0.1 mm is not a good idea. |
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For a plated via, the hole specified is the final diameter. To make the plated hole, the manufacturer drills it with a +0.10mm tool, then plates it with copper. So for the plated holes, the manufacturer has to drill bigger, for the non plated holes the specified drill applies. |
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Ok, we are using Eurocircuits classification and Eurocircuits clearly does it. So now by default we assume the manufacturer will add 0.1 mm to all plated drills. I'm adding a global option This changed some stuff in the logic, so now the _1 members doesn't exist and we have _real members. The |
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Got closer to the target: 10A ;-). 👍 Small typo for 'meassured' in out_report.py
lines above that , and apprently "Patter " is missing an 'n' according to the log:
Now I have to find where OAR 0 is coming from (and track 0.0?): # Important sizes
Clearance: 0.2 mm (8 mils)
Track width: 0.25 mm (10 mils)
- By design rules: 0.0 mm (0 mils)
Drill: 0.6 mm (24 mils)
- Vias: 0.6 mm (24 mils) [Design: 0.6 mm (24 mils)]
- Pads: 0.9 mm (35 mils)
- The above values are real drill sizes, they add 0.1 mm (4 mils) to plated holes (PTH)
Via: 1.0/0.5 mm (39/20 mils)
- By design rules: 1.0/0.5 mm (39/20 mils)
- Micro via: no [0.25/0.1 mm (10/4 mils)]
- Burried/blind via: no
Outer Annular Ring: 0.0 mm (0 mils)
- By design rules: 0.0 mm (0 mils)
Eurocircuits class: 10A
Edit: Edit2: Edit3: |
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You have 3 classes:
So 1 and 3 must depend on the design rules. The reports uses 2.
Ok. What produced it? I think we should add a warning |
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@set-soft Here is a test case - it's basically https://github.com/mdeweerd/kibot-testcases/blob/main/designs/tc5/tc5.pretty/TC5.kicad_mod causing that. |
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@mdeweerd, looking at Eurocircuits again I think we are computing the OAR wrongly. The OAR must be computed using the TOOL_SIZE, not the Finished size. Their drawing is confusing because they use an example where both are the same, but the text (and common sense) says you must use the TOOL_SIZE. |
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Ok now we will know the faulty pads. |
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https://www.eurocircuits.com/faq/annular-ring-oar-iar/ I agree that the drawing is very misleading, the text on the first link is clear. Here they indicate that PHD is the same as Toolsize (I guess the drawing was not made by a PhD 😃 ). I did not want to mention it, but rounding also comes in play - https://www.eurocircuits.com/pcb-design-guidelines/drilled-holes/ . |
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:-) I added the rounding stuff. Also added a mechanism to list the real drill tools needed for the board, and the oval holes. |
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I added an option to specify the target and a warning that explains why we are failing |
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I just had a go at the report generation.
Before going onto expressing some critics, this is overall great and the list of data provided is more that I expected.
Regarding the templates: at some point you showed results with schematics, and PCB. Do you have a template in progress to start from?
My board size is 123.50x70.60mm and it's reported as 40.38x95.89 mm (1.59x3.78 inches) .
I think there are two potential reasons for this:
I ran the report through pandoc:
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