Stop Mode on other families beside Py32f002B

[garudaonekh]

Hi,
I try to adapt your code to other families but I have to remark two lines out as it's only available on Py32F002B and it goes to 12ua,

/* STOP mode with deep low power regulator ON */
  //LL_PWR_SetLprMode(LL_PWR_LPR_MODE_LDPR);

  /* SRAM retention voltage aligned with digital LDO output */
  //LL_PWR_SetStopModeSramVoltCtrl(LL_PWR_SRAM_RETENTION_VOLT_CTRL_LDO);

https://github.com/IOsetting/py32f0-template/blob/main/Examples/PY32F002B/LL/PWR/PWR_DeepStop/main.c

I try the OpenPuya git and I can only get 8ua.

I use Py32f002a and Py32f030

[IOsetting]

For F002A, F003 and F030, use the following code to enter stop mode

LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
/*
 * Set STOP voltage to 1.0V (default 1.2V)
 * For PY32F030 1.0V -> 4.5uA~4.8uA, 1.2V -> 6uA ~ 7uA
 */
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
/*
 * Enable low power mode, SET_BIT(PWR->CR1, PWR_CR1_LPR)
 */
LL_PWR_EnableLowPowerRunMode();
/*
 * Enable deep stop, SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 */
LL_LPM_EnableDeepSleep();
 
/*
 * Wait event 
 * Change the following to __WFI() if waiting for interrupt
 */
__SEV();
__WFE();
__WFE();
 
/*
 * Return to sleep mode
 * CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk))
 */
LL_LPM_EnableSleep();