diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a053ead --- /dev/null +++ b/.gitignore @@ -0,0 +1,148 @@ +# This list of files to ignore includes common, tool- or user-specific files that +# are typically not checked into a version control system (VCS). It is a superset +# of such files. You may want to add others, especially if you use a tool not listed +# here. You can remove those that do not apply to you. +# +# The .gitignore file is intended for the git VCS. For another VCS you would specify +# which files to ignore in whatever form your VCS requires. If you do not check your +# code into a VCS, you can ignore the .gitignore file. + +# ModusToolbox library repos or information about library dependencies +libs/ + +# Eclipse IDE for ModusToolbox files +.metadata/ +# .cyignore +# .settings/ +# .cproject +# .project +# .mtbLaunchConfigs/ + +# ModusToolbox Configurator generated code +GeneratedSource/ + +# ModusToolbox build system output +build/ +Debug/ +Release/ +*_build/ + +# Visual Studio Code +openocd.tcl +.vscode/ +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json + +# IAR Embedded Workbench files + +# IAR Project file. +# *.ewp + +# IAR Settings +/settings/ + +# Uncomment this if not using project connections +# *.ipcf + +# Comment this out if using custom argument variables +*.custom_argvars + +# IAR Debugger Settings +# *.ewd + +# Comment this out if you use C-Stat or C-Run to compile/analyze your project +*.ewt + +# IAR Workspace files +# *.eww + +# IAR Debug Exe +/Debug/Exe/ + +# IAR Debug List +/Debug/List + +# IAR Debug Obj +/Obj/*.pbd +/Obj/*.pbd.* +/Obj/*.pbi +/Obj/*.pbi.* + +# Log files +*.log + +# IAR backup files +Backup* + +# IAR dependency files +*.dep + +# Compiled Binaries +*.bin +*.elf +*.hex +*.map + +# Trash files +*.bak + + +# Keil uVision files + +# Project and package description files +*.cpdsc +*.gpdsc + +# uVision Project file (generated by uVision). Uncomment this if do not want to track the Keil uVision project file +# *.uvprojx (is used to build the project from scratch) + +# Project options file (contains information about the debugger and trace configuration) +# *.uvoptx + +# Project file for multi-project workspaces +# *.uvmpw + +# Project screen layout file +*.uvguix.* + +# Configuration files for the run-time environment +# RTE/ + +# Generated output files +*.lst +*.map + +# Eclipse workspace/user-specific files/settings/caches +.metadata/ +# .settings/ + +# Vi and Emacs backup files +*~ +\#*\# +[._]*.s[a-v][a-z] +[._]*.sw[a-p] +[._]s[a-rt-v][a-z] +[._]ss[a-gi-z] +[._]sw[a-p] + +# Created by git when using merge tools for conflicts +*.BACKUP.* +*.BASE.* +*.LOCAL.* +*.REMOTE.* +*_BACKUP_*.txt +*_BASE_*.txt +*_LOCAL_*.txt +*_REMOTE_*.txt + +# macOS Finder incidental files +.DS_Store + +# Windows Explorer incidental files +Thumbs.db +Thumbs.db:encryptable +ehthumbs.db +ehthumbs_vista.db +[Dd]esktop.ini diff --git a/COMPONENT_bsp_design_modus/design.modus b/COMPONENT_bsp_design_modus/design.modus new file mode 100644 index 0000000..f60ccc7 --- /dev/null +++ b/COMPONENT_bsp_design_modus/design.modus @@ -0,0 +1,237 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CYW30739B2-P5-EVK01.mk b/CYW30739B2-P5-EVK01.mk new file mode 100644 index 0000000..b0c6023 --- /dev/null +++ b/CYW30739B2-P5-EVK01.mk @@ -0,0 +1,185 @@ +# +# Copyright 2016-2021, Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation. All rights reserved. +# +# This software, including source code, documentation and related +# materials ("Software") is owned by Cypress Semiconductor Corporation +# or one of its affiliates ("Cypress") and is protected by and subject to +# worldwide patent protection (United States and foreign), +# United States copyright laws and international treaty provisions. +# Therefore, you may use this Software only as provided in the license +# agreement accompanying the software package from which you +# obtained this Software ("EULA"). +# If no EULA applies, Cypress hereby grants you a personal, non-exclusive, +# non-transferable license to copy, modify, and compile the Software +# source code solely for use in connection with Cypress's +# integrated circuit products. Any reproduction, modification, translation, +# compilation, or representation of this Software except as specified +# above is prohibited without the express written permission of Cypress. +# +# Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress +# reserves the right to make changes to the Software without notice. Cypress +# does not assume any liability arising out of the application or use of the +# Software or any product or circuit described in the Software. Cypress does +# not authorize its products for use in any products where a malfunction or +# failure of the Cypress product may reasonably be expected to result in +# significant property damage, injury or death ("High Risk Product"). By +# including Cypress's product in a High Risk Product, the manufacturer +# of such system or application assumes all risk of such use and in doing +# so agrees to indemnify Cypress against all liability. +# + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# Device definition +# +DEVICE=CYW30739B2KUMLG +CHIP=30739 +CHIP_REV=B2 +BLD=A + +# CSP baselib and BSP path variables +CY_TARGET_DEVICE?=$(CHIP)$(CHIP_REV) +CY_APP_PATCH_LIBS+=$(CY_$(CY_TARGET_DEVICE)_APP_PATCH_LIBS) +COMPONENTS+=$(CY_TARGET_DEVICE) $(COMPONENTS_$(CY_TARGET_DEVICE)) +ifeq ($(SEARCH_$(CY_TARGET_DEVICE)),) +# internal only - app deploys will always initialize this in mtb.mk +SEARCH_$(CY_TARGET_DEVICE)?=$(IN_REPO_BTSDK_ROOT)/wiced_btsdk/dev-kit/baselib/$(CY_TARGET_DEVICE) +SEARCH+=$(SEARCH_$(CY_TARGET_DEVICE)) +endif +CY_BSP_PATH?=$(SEARCH_TARGET_$(TARGET)) +# ensure the baselib has been instantiated (in case make getlibs had already been performed, but for a BSP with a different CSP +ifneq ("$(wildcard $(SEARCH_$(CY_TARGET_DEVICE))/COMPONENT_$(CY_TARGET_DEVICE))","") +CY_BASELIB_PATH?=$(SEARCH_$(CY_TARGET_DEVICE))/COMPONENT_$(CY_TARGET_DEVICE) +CY_BASELIB_CORE_PATH?=$(SEARCH_core-make) +CY_INTERNAL_BASELIB_PATH?=$(patsubst %/,%,$(CY_BASELIB_PATH)) +override CY_DEVICESUPPORT_SEARCH_PATH:=$(call CY_MACRO_SEARCH,devicesupport.xml,$(CY_INTERNAL_BASELIB_PATH)) +endif + +# declare which stack version to use in COMPONENT folders +COMPONENTS+=btstack_v1 + +# +# Define the features for this target +# + +# Begin address of flash0, on-chip flash +CY_FLASH0_BEGIN_ADDR=0x00500000 +# Available flash = 1024k +CY_FLASH0_LENGTH=0x00100000 +# Entry-point symbol for application +CY_CORE_APP_ENTRY:=spar_crt_setup + +# +# TARGET UART parameters +# +# Max. supported baudrate by this platform +CY_CORE_DEFINES+=-DHCI_UART_MAX_BAUD=4000000 +# default baud rate is 3M, that is the max supported on macOS +CY_CORE_DEFINES+=-DHCI_UART_DEFAULT_BAUD=3000000 + +# +# pins supporting SWD hardware debugging +# +CY_CORE_DEFINES+=-DCY_PLATFORM_SWDCK=WICED_P02 +CY_CORE_DEFINES+=-DCY_PLATFORM_SWDIO=WICED_P03 + +# +# Patch variables +# +CY_CORE_PATCH=$(CY_INTERNAL_BASELIB_PATH)/internal/30739B2/patches_CYW30739B2_P5_EVK01/patch.elf +CY_CORE_PATCH_CFLAGS=$(CY_INTERNAL_BASELIB_PATH)/internal/30739B2/gcc/30739B2.cflag +CY_CORE_PATCH_LIB_PATH=libraries/prebuilt + +# +# Variables for pre-build and post-build processing +# +CY_CORE_HDF=$(CY_INTERNAL_BASELIB_PATH)/internal/30739B2/configdef30739B2.hdf +CY_CORE_HCI_ID=$(CY_INTERNAL_BASELIB_PATH)/platforms/IDFILE.txt +CY_CORE_BTP=$(CY_INTERNAL_BASELIB_PATH)/platforms/flash.btp +CY_CORE_MINIDRIVER=$(CY_INTERNAL_BASELIB_PATH)/platforms/minidriver.hex +CY_CORE_CGSLIST=\ + $(CY_INTERNAL_BASELIB_PATH)/internal/30739B2/patches_CYW30739B2_P5_EVK01/patch.cgs\ + $(CY_INTERNAL_BASELIB_PATH)/platforms/platform.cgs + +# +# read in BTP file as single source of flash layout information +# +define \n + + +endef + +define extract_btp_file_value +$(patsubst $1=%,%,$(filter $1%,$2)) +endef + +# these make targets do not need this data and don't work if importing an app +# that has not yet run make getlibs, so skip it +ifeq ($(filter import_deps getlibs get_app_info,$(MAKECMDGOALS)),) + +# override core-make buggy CY_SPACE till it's fixed +CY_EMPTY= +CY_SPACE=$(CY_EMPTY) $(CY_EMPTY) + +# split up btp file into "x=y" text +CY_BT_FILE_TEXT:=$(shell cat -e $(CY_CORE_BTP)) +CY_BT_FILE_TEXT:=$(subst $(CY_SPACE),,$(CY_BT_FILE_TEXT)) +CY_BT_FILE_TEXT:=$(subst ^M,,$(CY_BT_FILE_TEXT)) +CY_BT_FILE_TEXT:=$(patsubst %$(\n),% ,$(CY_BT_FILE_TEXT)) +CY_BT_FILE_TEXT:=$(subst $$,$(CY_SPACE),$(CY_BT_FILE_TEXT)) + +ifeq ($(CY_BT_FILE_TEXT),) +$(error Failed to parse BTP variables from file: $(CY_CORE_BTP)) +endif + +SS_LOCATION = $(call extract_btp_file_value,DLConfigSSLocation,$(CY_BT_FILE_TEXT)) +VS_LOCATION = $(call extract_btp_file_value,DLConfigVSLocation,$(CY_BT_FILE_TEXT)) +VS_LENGTH = $(call extract_btp_file_value,DLConfigVSLength,$(CY_BT_FILE_TEXT)) +DS_LOCATION = $(call extract_btp_file_value,ConfigDSLocation,$(CY_BT_FILE_TEXT)) +DS2_LOCATION = $(call extract_btp_file_value,ConfigDS2Location,$(CY_BT_FILE_TEXT)) +XIP_DS_OFFSET = 0x0001e000 + +endif # end filter import_deps getlibs get_app_info + +# OTA +ifeq ($(OTA_FW_UPGRADE),1) +CY_APP_OTA=OTA +CY_APP_OTA_DEFINES=-DOTA_FW_UPGRADE=1 +ifeq ($(CY_APP_SECURE_OTA_FIRMWARE_UPGRADE),1) +CY_APP_OTA_DEFINES+=-DOTA_SECURE_FIRMWARE_UPGRADE +endif +CY_CORE_DS2_OBJ = +endif + +# use flash offset and length to limit xip range +ifneq ($(CY_FLASH0_BEGIN_ADDR),) +CY_CORE_LD_DEFS+=FLASH0_BEGIN_ADDR=$(CY_FLASH0_BEGIN_ADDR) +endif +ifneq ($(CY_FLASH0_LENGTH),) +CY_CORE_LD_DEFS+=FLASH0_LENGTH=$(CY_FLASH0_LENGTH) +endif + +ifeq ($(XIP),xip) +CY_CORE_APP_XIP_EXTRA=_XIP_ +CY_CORE_DEFINES+=-DXIP_DS_OFFSET=$(XIP_DS_OFFSET) +CY_CORE_LD_DEFS+=XIP_DS_OFFSET=$(XIP_DS_OFFSET) +CY_CORE_LD_DEFS+=XIP_LEN=0x$(shell env printf "%08x" $$(($(DS2_LOCATION) - $(DS_LOCATION) - $(XIP_DS_OFFSET)))) +CY_CORE_CGSLIST+=$(CY_INTERNAL_BASELIB_PATH)/platforms/platform_xip.cgs +endif + +# defines necessary for flash layout +CY_CORE_DEFINES+=-DSS_LOCATION=$(SS_LOCATION) -DVS_LOCATION=$(VS_LOCATION) -DDS_LOCATION=$(DS_LOCATION) -DDS2_LOCATION=$(DS2_LOCATION) + +CY_CORE_LD_DEFS+=\ + SRAM_BEGIN_ADDR=0x00200000 \ + SRAM_LENGTH=0x00070000 \ + AON_AREA_END=0x00284000 \ + ISTATIC_BEGIN=0x500C00 \ + ISTATIC_LEN=0x400 \ + NUM_PATCH_ENTRIES=256 diff --git a/LICENSE.txt b/LICENSE.txt new file mode 100644 index 0000000..f7eec35 --- /dev/null +++ b/LICENSE.txt @@ -0,0 +1,210 @@ +CYPRESS (AN INFINEON COMPANY) END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE +DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING +DOCUMENTATION. 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Any notice to Cypress +will be deemed effective when actually received and must be sent to Cypress +Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San +Jose, CA 95134 USA. diff --git a/version.xml b/version.xml new file mode 100644 index 0000000..cb310e3 --- /dev/null +++ b/version.xml @@ -0,0 +1 @@ +3.2.0.20467 diff --git a/wiced_platform.h b/wiced_platform.h new file mode 100644 index 0000000..9258aa4 --- /dev/null +++ b/wiced_platform.h @@ -0,0 +1,37 @@ +/* + * Copyright 2016-2023, Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. All rights reserved. + * + * This software, including source code, documentation and related + * materials ("Software") is owned by Cypress Semiconductor Corporation + * or one of its affiliates ("Cypress") and is protected by and subject to + * worldwide patent protection (United States and foreign), + * United States copyright laws and international treaty provisions. + * Therefore, you may use this Software only as provided in the license + * agreement accompanying the software package from which you + * obtained this Software ("EULA"). + * If no EULA applies, Cypress hereby grants you a personal, non-exclusive, + * non-transferable license to copy, modify, and compile the Software + * source code solely for use in connection with Cypress's + * integrated circuit products. Any reproduction, modification, translation, + * compilation, or representation of this Software except as specified + * above is prohibited without the express written permission of Cypress. + * + * Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress + * reserves the right to make changes to the Software without notice. Cypress + * does not assume any liability arising out of the application or use of the + * Software or any product or circuit described in the Software. Cypress does + * not authorize its products for use in any products where a malfunction or + * failure of the Cypress product may reasonably be expected to result in + * significant property damage, injury or death ("High Risk Product"). By + * including Cypress's product in a High Risk Product, the manufacturer + * of such system or application assumes all risk of such use and in doing + * so agrees to indemnify Cypress against all liability. + */ + +#pragma once + +/*! IEEE 802.15.4 PHY ED Threshold Value used for CCA. */ +#define WICED_PLATFORM_I15DOT4_PHY_ED_THRESHOLD (-70)