From af0aea3cbd68252da089c41e1d7b174293df6194 Mon Sep 17 00:00:00 2001 From: Valentin Churavy Date: Sun, 11 Jul 2021 10:52:53 +0200 Subject: [PATCH] [LLVM] add 12.0.1 --- L/LLVM/LLVM_full@12.0.1/build_tarballs.jl | 6 + .../libcxx_patches/7005_libcxx_musl.patch | 22 + .../0016-llvm7-revert-D44485.patch | 94 ++++ .../0032-llvm-12-D75072-SCEV-add-type.patch | 425 ++++++++++++++++++ .../0045-llvm-11-D93154-globalisel-as.patch | 88 ++++ .../0050-llvm-julia-tsan-custom-as.patch | 28 ++ .../0052-llvm-11-D94813-mergeicmps.patch | 111 +++++ ...0060-llvm-invalid-addrspacecast-sink.patch | 116 +++++ ...71-llvm-12-D97435-AArch64-movaddrreg.patch | 164 +++++++ .../9999-llvm-symver-jlprefix.patch | 18 + .../0050-unique_function_clang-sa.patch | 28 ++ .../patches/0100-llvm-12-musl-bb.patch | 37 ++ .../0100-revert-sdk-requirement-tsan.patch | 33 ++ .../0101-fix-darwin-tsan-on-old-sdks.patch | 66 +++ .../patches/0101-llvm-12-musl-bb-32.patch | 25 ++ .../bundled/patches/0702-apple-codesign.patch | 13 + .../bundled/patches/0703-apple-10..12.patch | 25 ++ .../patches/0705-D97571-AArch64-loh.patch | 101 +++++ .../patches/0706-aarch64-addrspace.patch | 31 ++ .../0707-PR49357-AArch64-FastIsel-bug.patch | 50 +++ ...-Do-not-patch-FDE-symbols-on-AArch64.patch | 158 +++++++ ...-Force-.eh_frame-emission-on-AArch64.patch | 31 ++ L/LLVM/common.jl | 1 + L/LLVM/libLLVM@9.0.1/build_tarballs.jl | 2 +- 24 files changed, 1672 insertions(+), 1 deletion(-) create mode 100644 L/LLVM/LLVM_full@12.0.1/build_tarballs.jl create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/libcxx_patches/7005_libcxx_musl.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0016-llvm7-revert-D44485.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0032-llvm-12-D75072-SCEV-add-type.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0045-llvm-11-D93154-globalisel-as.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0050-llvm-julia-tsan-custom-as.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0052-llvm-11-D94813-mergeicmps.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0060-llvm-invalid-addrspacecast-sink.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0071-llvm-12-D97435-AArch64-movaddrreg.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/9999-llvm-symver-jlprefix.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0050-unique_function_clang-sa.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-llvm-12-musl-bb.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-revert-sdk-requirement-tsan.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-fix-darwin-tsan-on-old-sdks.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-llvm-12-musl-bb-32.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0702-apple-codesign.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0703-apple-10..12.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0705-D97571-AArch64-loh.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0706-aarch64-addrspace.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0707-PR49357-AArch64-FastIsel-bug.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0708-Do-not-patch-FDE-symbols-on-AArch64.patch create mode 100644 L/LLVM/LLVM_full@12.0.1/bundled/patches/0709-Force-.eh_frame-emission-on-AArch64.patch diff --git a/L/LLVM/LLVM_full@12.0.1/build_tarballs.jl b/L/LLVM/LLVM_full@12.0.1/build_tarballs.jl new file mode 100644 index 00000000000..2f7d5ddd1a7 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/build_tarballs.jl @@ -0,0 +1,6 @@ +version = v"12.0.1" + +include("../common.jl") + +build_tarballs(ARGS, configure_build(ARGS, version; experimental_platforms=true)...; + preferred_gcc_version=v"7", preferred_llvm_version=v"9", julia_compat="1.7") diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/libcxx_patches/7005_libcxx_musl.patch b/L/LLVM/LLVM_full@12.0.1/bundled/libcxx_patches/7005_libcxx_musl.patch new file mode 100644 index 00000000000..86978bf72f1 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/libcxx_patches/7005_libcxx_musl.patch @@ -0,0 +1,22 @@ +diff --git a/include/locale b/include/locale +index 2043892fa2d..4af51464208 100644 +--- a/include/locale ++++ b/include/locale +@@ -737,7 +737,7 @@ __num_get_signed_integral(const char* __a, const char* __a_end, + typename remove_reference::type __save_errno = errno; + errno = 0; + char *__p2; +- long long __ll = strtoll_l(__a, &__p2, __base, _LIBCPP_GET_C_LOCALE); ++ long long __ll = strtoll(__a, &__p2, __base); + typename remove_reference::type __current_errno = errno; + if (__current_errno == 0) + errno = __save_errno; +@@ -777,7 +777,7 @@ __num_get_unsigned_integral(const char* __a, const char* __a_end, + typename remove_reference::type __save_errno = errno; + errno = 0; + char *__p2; +- unsigned long long __ll = strtoull_l(__a, &__p2, __base, _LIBCPP_GET_C_LOCALE); ++ unsigned long long __ll = strtoull(__a, &__p2, __base); + typename remove_reference::type __current_errno = errno; + if (__current_errno == 0) + errno = __save_errno; diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0016-llvm7-revert-D44485.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0016-llvm7-revert-D44485.patch new file mode 100644 index 00000000000..121e1974f5f --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0016-llvm7-revert-D44485.patch @@ -0,0 +1,94 @@ +From 4370214628487ac8495f963ae05960b5ecc31103 Mon Sep 17 00:00:00 2001 +From: Jameson Nash +Date: Thu, 12 Sep 2019 11:45:07 -0400 +Subject: [PATCH] Revert "[MC] Always emit relocations for same-section + function references" + +This reverts commit 9232972575cafac29c3e4817c8714c9aca0e8585. +--- + lib/MC/WinCOFFObjectWriter.cpp | 12 +++++------- + test/MC/COFF/diff.s | 25 ++++++++----------------- + 2 files changed, 13 insertions(+), 24 deletions(-) + +diff --git a/lib/MC/WinCOFFObjectWriter.cpp b/lib/MC/WinCOFFObjectWriter.cpp +index 9ffecd99df6..0214161e03c 100644 +--- a/lib/MC/WinCOFFObjectWriter.cpp ++++ b/lib/MC/WinCOFFObjectWriter.cpp +@@ -690,14 +690,12 @@ void WinCOFFObjectWriter::executePostLayoutBinding(MCAssembler &Asm, + bool WinCOFFObjectWriter::isSymbolRefDifferenceFullyResolvedImpl( + const MCAssembler &Asm, const MCSymbol &SymA, const MCFragment &FB, + bool InSet, bool IsPCRel) const { +- // Don't drop relocations between functions, even if they are in the same text +- // section. Multiple Visual C++ linker features depend on having the +- // relocations present. The /INCREMENTAL flag will cause these relocations to +- // point to thunks, and the /GUARD:CF flag assumes that it can use relocations +- // to approximate the set of all address taken functions. LLD's implementation +- // of /GUARD:CF also relies on the existance of these relocations. ++ // MS LINK expects to be able to replace all references to a function with a ++ // thunk to implement their /INCREMENTAL feature. Make sure we don't optimize ++ // away any relocations to functions. + uint16_t Type = cast(SymA).getType(); +- if ((Type >> COFF::SCT_COMPLEX_TYPE_SHIFT) == COFF::IMAGE_SYM_DTYPE_FUNCTION) ++ if (Asm.isIncrementalLinkerCompatible() && ++ (Type >> COFF::SCT_COMPLEX_TYPE_SHIFT) == COFF::IMAGE_SYM_DTYPE_FUNCTION) + return false; + return MCObjectWriter::isSymbolRefDifferenceFullyResolvedImpl(Asm, SymA, FB, + InSet, IsPCRel); +diff --git a/test/MC/COFF/diff.s b/test/MC/COFF/diff.s +index f89e4ed8901..d68e628577b 100644 +--- a/test/MC/COFF/diff.s ++++ b/test/MC/COFF/diff.s +@@ -1,14 +1,19 @@ + // RUN: llvm-mc -filetype=obj -triple i686-pc-mingw32 %s | llvm-readobj -s -sr -sd | FileCheck %s + +-// COFF resolves differences between labels in the same section, unless that +-// label is declared with function type. +- + .section baz, "xr" ++ .def X ++ .scl 2; ++ .type 32; ++ .endef + .globl X + X: + mov Y-X+42, %eax + retl + ++ .def Y ++ .scl 2; ++ .type 32; ++ .endef + .globl Y + Y: + retl +@@ -25,11 +30,6 @@ _foobar: # @foobar + # %bb.0: + ret + +- .globl _baz +-_baz: +- calll _foobar +- retl +- + .data + .globl _rust_crate # @rust_crate + .align 4 +@@ -39,15 +39,6 @@ _rust_crate: + .long _foobar-_rust_crate + .long _foobar-_rust_crate + +-// Even though _baz and _foobar are in the same .text section, we keep the +-// relocation for compatibility with the VC linker's /guard:cf and /incremental +-// flags, even on mingw. +- +-// CHECK: Name: .text +-// CHECK: Relocations [ +-// CHECK-NEXT: 0x12 IMAGE_REL_I386_REL32 _foobar +-// CHECK-NEXT: ] +- + // CHECK: Name: .data + // CHECK: Relocations [ + // CHECK-NEXT: 0x4 IMAGE_REL_I386_DIR32 _foobar +-- +2.17.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0032-llvm-12-D75072-SCEV-add-type.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0032-llvm-12-D75072-SCEV-add-type.patch new file mode 100644 index 00000000000..c74cd70b20e --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0032-llvm-12-D75072-SCEV-add-type.patch @@ -0,0 +1,425 @@ +From 4827d22b3e297b82c7689f0fb06b38e67d92b578 Mon Sep 17 00:00:00 2001 +From: Keno Fischer +Date: Wed, 21 Apr 2021 12:25:07 -0400 +Subject: [PATCH] [SCEV] Record NI types in add exprs + +This fixes a case where loop-reduce introduces ptrtoint/inttoptr for +non-integral address space pointers. Over the past several years, we +have gradually improved the SCEVExpander to actually do something +sensible for non-integral pointer types. However, that obviously +relies on the expander knowing what the type of the SCEV expression is. +That is usually the case, but there is one important case where it's +not: The type of an add expression is just the type of the last operand, +so if the non-integral pointer is not the last operand, later uses of +that SCEV may not realize that the given add expression contains +non-integral pointers and may try to expand it as integers. + +One interesting observation is that we do get away with this scheme in +shockingly many cases. The reason for this is that SCEV expressions +often have an `scUnknown` pointer base, which our sort order on the +operands of add expressions sort behind basically everything else, +so it usually ends up as the last operand. + +One situation where this fails is included as a test case. This test +case was bugpoint-reduced from the issue reported at +https://github.com/JuliaLang/julia/issues/31156. What happens here +is that the pointer base is an scAddRec from an outer loop, plus an +scUnknown integer offset. By our sort order, the scUnknown gets sorted +after the scAddRec pointer base, thus making an add expression of these +two operands have integer type. This then confuses the expander, into +attempting to expand the whole thing as integers, which will obviously +fail when reaching the non-integral pointer. + +I considered a few options to solve this, but here's what I ended up +settling on: The AddExpr class gains a new subclass that explicitly +stores the type of the expression. This subclass is used whenever one +of the operands is a non-integral pointer. To reduce the impact for the +regular case (where the SCEV expression contains no non-integral +pointers), a bit flag is kept in each flag expression to indicate +whether it is of non-integral pointer type (this should give the same +answer as asking if getType() is non-integral, but performing that +query may involve a pointer chase and requires the DataLayout). For +add expressions that flag is also used to indicate whether we're using +the subclass or not. This is slightly inefficient, because it uses +the subclass even in the (not uncommon) case where the last operand +does actually accurately reflect the non-integral pointer type. However, +it didn't seem worth the extra flag bit and complexity to do this +micro-optimization. + +I had hoped that we could additionally restrict mul exprs from +containing any non-integral pointers, and also require add exprs to +only have one operand containg such pointers (but not more), but this +turned out not to work. The reason for this is that SCEV wants to +form differences between pointers, which it represents as `A + B*-1`, +so we need to allow both multiplication by `-1` and addition with +multiple non-integral pointer arguments. I'm not super happy with +that situation, but I think it exposes a more general problem with +non-integral pointers in LLVM. We don't actually have a way to express +the difference between two non-integral pointers at the IR level. +In theory this is a problem for SCEV, because it means that we can't +materialize such SCEV expression. However, in practice, these +expressions generally have the same base pointer, so SCEV will +appropriately simplify them to just the integer components. +Nevertheless it is a bit unsatisfying. Perhaps we could have an +intrinsic that takes the byte difference between two pointers to the +same allocated object (in the same sense as is used in getelementptr), +which should be a sensible operation even for non-integral pointers. +However, given the practical considerations above, that's a project +for another time. For now, simply allowing the existing pointer-diff +pattern for non-integral pointers seems to work ok. + +Differential Revision: https://reviews.llvm.org/D75072 +--- + llvm/include/llvm/Analysis/ScalarEvolution.h | 21 ++++- + .../Analysis/ScalarEvolutionExpressions.h | 81 ++++++++++++++++--- + llvm/lib/Analysis/ScalarEvolution.cpp | 41 +++++++--- + .../LoopStrengthReduce/nonintegral.ll | 35 +++++++- + 4 files changed, 155 insertions(+), 23 deletions(-) + +diff --git llvm/include/llvm/Analysis/ScalarEvolution.h llvm/include/llvm/Analysis/ScalarEvolution.h +index b3f199de2cfa..d98fbeb5dcf7 100644 +--- llvm/include/llvm/Analysis/ScalarEvolution.h ++++ llvm/include/llvm/Analysis/ScalarEvolution.h +@@ -120,6 +120,19 @@ public: + NoWrapMask = (1 << 3) - 1 + }; + ++ /// HasNonIntegralPointerFlag are bitfield indices into SubclassData. ++ /// ++ /// When constructing SCEV expressions for LLVM expressions with non-integral ++ /// pointer types, some additional processing is required to ensure that we ++ /// don't introduce any illegal transformations. However, non-integral pointer ++ /// types are a very rarely used feature, so we want to make sure to only do ++ /// such processing if they are actually used. To ensure minimal performance ++ /// impact, we memoize that fact in using these flags. ++ enum HasNonIntegralPointerFlag { ++ FlagNoNIPointers = 0, ++ FlagHasNIPointers = (1 << 3) ++ }; ++ + explicit SCEV(const FoldingSetNodeIDRef ID, SCEVTypes SCEVTy, + unsigned short ExpressionSize) + : FastID(ID), SCEVType(SCEVTy), ExpressionSize(ExpressionSize) {} +@@ -156,6 +169,10 @@ public: + return ExpressionSize; + } + ++ bool hasNonIntegralPointers() const { ++ return SubclassData & FlagHasNIPointers; ++ } ++ + /// Print out the internal representation of this scalar to the specified + /// stream. This should really only be used for debugging purposes. + void print(raw_ostream &OS) const; +@@ -745,7 +762,7 @@ public: + const BasicBlock *ExitingBlock); + + /// The terms "backedge taken count" and "exit count" are used +- /// interchangeably to refer to the number of times the backedge of a loop ++ /// interchangeably to refer to the number of times the backedge of a loop + /// has executed before the loop is exited. + enum ExitCountKind { + /// An expression exactly describing the number of times the backedge has +@@ -758,7 +775,7 @@ public: + }; + + /// Return the number of times the backedge executes before the given exit +- /// would be taken; if not exactly computable, return SCEVCouldNotCompute. ++ /// would be taken; if not exactly computable, return SCEVCouldNotCompute. + /// For a single exit loop, this value is equivelent to the result of + /// getBackedgeTakenCount. The loop is guaranteed to exit (via *some* exit) + /// before the backedge is executed (ExitCount + 1) times. Note that there +diff --git llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h +index 37e675f08afc..6e532b22f5b3 100644 +--- llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h ++++ llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h +@@ -228,6 +228,13 @@ class Type; + return getNoWrapFlags(FlagNW) != FlagAnyWrap; + } + ++ void setHasNIPtr(bool HasNIPtr) { ++ if (HasNIPtr) ++ SubclassData |= FlagHasNIPointers; ++ else ++ SubclassData &= ~FlagHasNIPointers; ++ } ++ + /// Methods for support type inquiry through isa, cast, and dyn_cast: + static bool classof(const SCEV *S) { + return S->getSCEVType() == scAddExpr || S->getSCEVType() == scMulExpr || +@@ -264,19 +271,16 @@ class Type; + + Type *Ty; + ++ protected: + SCEVAddExpr(const FoldingSetNodeIDRef ID, const SCEV *const *O, size_t N) + : SCEVCommutativeExpr(ID, scAddExpr, O, N) { +- auto *FirstPointerTypedOp = find_if(operands(), [](const SCEV *Op) { +- return Op->getType()->isPointerTy(); +- }); +- if (FirstPointerTypedOp != operands().end()) +- Ty = (*FirstPointerTypedOp)->getType(); +- else +- Ty = getOperand(0)->getType(); ++ + } + + public: +- Type *getType() const { return Ty; } ++ // Returns the type of the add expression, by looking either at the last operand ++ // or deferring to the SCEVAddNIExpr subclass. ++ Type *getType() const; + + /// Methods for support type inquiry through isa, cast, and dyn_cast: + static bool classof(const SCEV *S) { +@@ -284,6 +288,46 @@ class Type; + } + }; + ++ /// This node represents an addition of some number of SCEVs, one which ++ /// is a non-integral pointer type, requiring us to know the type exactly for ++ /// correctness. ++ class SCEVAddNIExpr : public SCEVAddExpr { ++ friend class ScalarEvolution; ++ PointerType *NIType; ++ ++ SCEVAddNIExpr(const FoldingSetNodeIDRef ID, const SCEV *const *O, size_t N, ++ PointerType *NIType) ++ : SCEVAddExpr(ID, O, N), NIType(NIType) { ++ SubclassData |= FlagHasNIPointers; ++ } ++ ++ public: ++ Type *getType() const { return NIType; } ++ ++ /// Methods for support type inquiry through isa, cast, and dyn_cast: ++ static bool classof(const SCEV *S) { ++ return S->getSCEVType() == scAddExpr && S->hasNonIntegralPointers(); ++ } ++ }; ++ ++ inline Type *SCEVAddExpr::getType() const { ++ // In general, use the type of the last operand, which is likely to be a ++ // pointer type, if there is one. This doesn't usually matter, but it can ++ // help reduce casts when the expressions are expanded. In the (unusual) ++ // case that we're working with non-integral pointers, we have a subclass ++ // that stores that type explicitly. ++ if (hasNonIntegralPointers()) ++ return cast(this)->getType(); ++ ++ auto *FirstPointerTypedOp = find_if(operands(), [](const SCEV *Op) { ++ return Op->getType()->isPointerTy(); ++ }); ++ if (FirstPointerTypedOp != operands().end()) ++ return (*FirstPointerTypedOp)->getType(); ++ else ++ return getOperand(0)->getType(); ++ } ++ + /// This node represents multiplication of some number of SCEVs. + class SCEVMulExpr : public SCEVCommutativeExpr { + friend class ScalarEvolution; +@@ -293,6 +337,18 @@ class Type; + : SCEVCommutativeExpr(ID, scMulExpr, O, N) {} + + public: ++ Type *getType() const { ++ // In general, we can't form SCEVMulExprs with non-integral pointer types, ++ // but for the moment we need to allow a special case: Multiplying by ++ // -1 to be able express the difference between two pointers. In order ++ // to maintain the invariant that SCEVs with the NI flag set should have ++ // a type corresponding to the contained NI ptr, we need to return the ++ // type of the pointer here. ++ if (hasNonIntegralPointers()) ++ return getOperand(getNumOperands() - 1)->getType(); ++ return SCEVCommutativeExpr::getType(); ++ } ++ + /// Methods for support type inquiry through isa, cast, and dyn_cast: + static bool classof(const SCEV *S) { + return S->getSCEVType() == scMulExpr; +@@ -531,9 +587,12 @@ class Type; + /// instances owned by a ScalarEvolution. + SCEVUnknown *Next; + +- SCEVUnknown(const FoldingSetNodeIDRef ID, Value *V, +- ScalarEvolution *se, SCEVUnknown *next) : +- SCEV(ID, scUnknown, 1), CallbackVH(V), SE(se), Next(next) {} ++ SCEVUnknown(const FoldingSetNodeIDRef ID, Value *V, ScalarEvolution *se, ++ SCEVUnknown *next, bool ValueIsNIPtr) ++ : SCEV(ID, scUnknown, 1), CallbackVH(V), SE(se), Next(next) { ++ if (ValueIsNIPtr) ++ SubclassData |= FlagHasNIPointers; ++ } + + // Implement CallbackVH. + void deleted() override; +diff --git llvm/lib/Analysis/ScalarEvolution.cpp llvm/lib/Analysis/ScalarEvolution.cpp +index fe9d8297d679..1fa7b8ce1451 100644 +--- llvm/lib/Analysis/ScalarEvolution.cpp ++++ llvm/lib/Analysis/ScalarEvolution.cpp +@@ -389,12 +389,13 @@ Type *SCEV::getType() const { + case scSignExtend: + return cast(this)->getType(); + case scAddRecExpr: +- case scMulExpr: + case scUMaxExpr: + case scSMaxExpr: + case scUMinExpr: + case scSMinExpr: + return cast(this)->getType(); ++ case scMulExpr: ++ return cast(this)->getType(); + case scAddExpr: + return cast(this)->getType(); + case scUDivExpr: +@@ -2679,16 +2680,27 @@ ScalarEvolution::getOrCreateAddExpr(ArrayRef Ops, + SCEV::NoWrapFlags Flags) { + FoldingSetNodeID ID; + ID.AddInteger(scAddExpr); +- for (const SCEV *Op : Ops) +- ID.AddPointer(Op); ++ bool HasNIPtr = false; ++ PointerType *NIPtrType = nullptr; ++ for (unsigned i = 0, e = Ops.size(); i != e; ++i) { ++ ID.AddPointer(Ops[i]); ++ if (Ops[i]->hasNonIntegralPointers()) { ++ HasNIPtr = true; ++ NIPtrType = cast(Ops[i]->getType()); ++ } ++ } + void *IP = nullptr; + SCEVAddExpr *S = + static_cast(UniqueSCEVs.FindNodeOrInsertPos(ID, IP)); + if (!S) { + const SCEV **O = SCEVAllocator.Allocate(Ops.size()); + std::uninitialized_copy(Ops.begin(), Ops.end(), O); +- S = new (SCEVAllocator) +- SCEVAddExpr(ID.Intern(SCEVAllocator), O, Ops.size()); ++ if (HasNIPtr) ++ S = new (SCEVAllocator) ++ SCEVAddNIExpr(ID.Intern(SCEVAllocator), O, Ops.size(), NIPtrType); ++ else ++ S = new (SCEVAllocator) ++ SCEVAddExpr(ID.Intern(SCEVAllocator), O, Ops.size()); + UniqueSCEVs.InsertNode(S, IP); + addToLoopUseLists(S); + } +@@ -2701,8 +2713,10 @@ ScalarEvolution::getOrCreateAddRecExpr(ArrayRef Ops, + const Loop *L, SCEV::NoWrapFlags Flags) { + FoldingSetNodeID ID; + ID.AddInteger(scAddRecExpr); +- for (unsigned i = 0, e = Ops.size(); i != e; ++i) ++ for (unsigned i = 0, e = Ops.size(); i != e; ++i) { ++ assert(i == 0 || !Ops[i]->hasNonIntegralPointers()); + ID.AddPointer(Ops[i]); ++ } + ID.AddPointer(L); + void *IP = nullptr; + SCEVAddRecExpr *S = +@@ -2716,6 +2730,7 @@ ScalarEvolution::getOrCreateAddRecExpr(ArrayRef Ops, + addToLoopUseLists(S); + } + setNoWrapFlags(S, Flags); ++ S->setHasNIPtr(Ops[0]->hasNonIntegralPointers()); + return S; + } + +@@ -2724,8 +2739,11 @@ ScalarEvolution::getOrCreateMulExpr(ArrayRef Ops, + SCEV::NoWrapFlags Flags) { + FoldingSetNodeID ID; + ID.AddInteger(scMulExpr); +- for (unsigned i = 0, e = Ops.size(); i != e; ++i) ++ bool HasNIPtr = false; ++ for (unsigned i = 0, e = Ops.size(); i != e; ++i) { ++ HasNIPtr |= Ops[i]->hasNonIntegralPointers(); + ID.AddPointer(Ops[i]); ++ } + void *IP = nullptr; + SCEVMulExpr *S = + static_cast(UniqueSCEVs.FindNodeOrInsertPos(ID, IP)); +@@ -2738,6 +2756,7 @@ ScalarEvolution::getOrCreateMulExpr(ArrayRef Ops, + addToLoopUseLists(S); + } + S->setNoWrapFlags(Flags); ++ S->setHasNIPtr(HasNIPtr); + return S; + } + +@@ -3615,8 +3634,11 @@ const SCEV *ScalarEvolution::getMinMaxExpr(SCEVTypes Kind, + return ExistingSCEV; + const SCEV **O = SCEVAllocator.Allocate(Ops.size()); + std::uninitialized_copy(Ops.begin(), Ops.end(), O); +- SCEV *S = new (SCEVAllocator) ++ SCEVMinMaxExpr *S = new (SCEVAllocator) + SCEVMinMaxExpr(ID.Intern(SCEVAllocator), Kind, O, Ops.size()); ++ // For MinMaxExprs it's sufficient to see if the first Op has NI data, as the ++ // operands all need to be of the same type. ++ S->setHasNIPtr(Ops[0]->hasNonIntegralPointers()); + + UniqueSCEVs.InsertNode(S, IP); + addToLoopUseLists(S); +@@ -3716,8 +3738,9 @@ const SCEV *ScalarEvolution::getUnknown(Value *V) { + "Stale SCEVUnknown in uniquing map!"); + return S; + } ++ bool ValueIsNIPtr = getDataLayout().isNonIntegralPointerType(V->getType()); + SCEV *S = new (SCEVAllocator) SCEVUnknown(ID.Intern(SCEVAllocator), V, this, +- FirstUnknown); ++ FirstUnknown, ValueIsNIPtr); + FirstUnknown = cast(S); + UniqueSCEVs.InsertNode(S, IP); + return S; +diff --git llvm/test/Transforms/LoopStrengthReduce/nonintegral.ll llvm/test/Transforms/LoopStrengthReduce/nonintegral.ll +index 5648e3aa74af..6936521f3a64 100644 +--- llvm/test/Transforms/LoopStrengthReduce/nonintegral.ll ++++ llvm/test/Transforms/LoopStrengthReduce/nonintegral.ll +@@ -2,7 +2,7 @@ + + ; Address Space 10 is non-integral. The optimizer is not allowed to use + ; ptrtoint/inttoptr instructions. Make sure that this doesn't happen +-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12" ++target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13" + target triple = "x86_64-unknown-linux-gnu" + + define void @japi1__unsafe_getindex_65028(i64 addrspace(10)* %arg) { +@@ -43,3 +43,36 @@ if38: ; preds = %L119 + done: ; preds = %if38 + ret void + } ++ ++; This is a bugpoint-reduced regression test - It doesn't make too much sense by itself, ++; but creates the correct SCEV expressions to reproduce the issue. See ++; https://github.com/JuliaLang/julia/issues/31156 for the original bug report. ++define void @"japi1_permutedims!_4259"(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i1 %g, i8 addrspace(13)* %base) #0 { ++; CHECK-NOT: inttoptr ++; CHECK-NOT: ptrtoint ++; CHECK: getelementptr i8, i8 addrspace(13)* {{.*}}, i64 {{.*}} ++top: ++ br label %L42.L46_crit_edge.us ++ ++L42.L46_crit_edge.us: ; preds = %L82.us.us.loopexit, %top ++ %value_phi11.us = phi i64 [ %a, %top ], [ %2, %L82.us.us.loopexit ] ++ %0 = sub i64 %value_phi11.us, %b ++ %1 = add i64 %0, %c ++ %spec.select = select i1 %g, i64 %d, i64 0 ++ br label %L62.us.us ++ ++L82.us.us.loopexit: ; preds = %L62.us.us ++ %2 = add i64 %e, %value_phi11.us ++ br label %L42.L46_crit_edge.us ++ ++L62.us.us: ; preds = %L62.us.us, %L42.L46_crit_edge.us ++ %value_phi21.us.us = phi i64 [ %6, %L62.us.us ], [ %spec.select, %L42.L46_crit_edge.us ] ++ %3 = add i64 %1, %value_phi21.us.us ++ %4 = getelementptr inbounds i8, i8 addrspace(13)* %base, i64 %3 ++ %5 = load i8, i8 addrspace(13)* %4, align 1 ++ %6 = add i64 %f, %value_phi21.us.us ++ br i1 %g, label %L82.us.us.loopexit, label %L62.us.us, !llvm.loop !1 ++} ++ ++!1 = distinct !{!1, !2} ++!2 = !{!"llvm.loop.isvectorized", i32 1} +-- +2.31.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0045-llvm-11-D93154-globalisel-as.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0045-llvm-11-D93154-globalisel-as.patch new file mode 100644 index 00000000000..7b5575e05c0 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0045-llvm-11-D93154-globalisel-as.patch @@ -0,0 +1,88 @@ +From af809ec100ef60cdeeef776e54c123e4fc8f1071 Mon Sep 17 00:00:00 2001 +From: Jameson Nash +Date: Tue, 15 Dec 2020 10:04:08 -0500 +Subject: [PATCH] GlobalISel: remove assert that memcpy Src and Dst addrspace + must be identical + +The LangRef does not require these arguments to have the same type. + +Differential Revision: https://reviews.llvm.org/D93154 +--- + .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 27 +++++++++++-------- + 1 file changed, 16 insertions(+), 11 deletions(-) + +diff --git llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +index 79f74a47d83c..7bd6f8f52c8b 100644 +--- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp ++++ llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +@@ -1240,7 +1240,6 @@ bool CombinerHelper::optimizeMemcpy(MachineInstr &MI, Register Dst, + // of that value loaded. This can result in a sequence of loads and stores + // mixed types, depending on what the target specifies as good types to use. + unsigned CurrOffset = 0; +- LLT PtrTy = MRI.getType(Src); + unsigned Size = KnownLen; + for (auto CopyTy : MemOps) { + // Issuing an unaligned load / store pair that overlaps with the previous +@@ -1258,15 +1257,20 @@ bool CombinerHelper::optimizeMemcpy(MachineInstr &MI, Register Dst, + Register LoadPtr = Src; + Register Offset; + if (CurrOffset != 0) { +- Offset = MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset) +- .getReg(0); +- LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0); ++ LLT LoadTy = MRI.getType(Src); ++ Offset = ++ MIB.buildConstant(LLT::scalar(LoadTy.getSizeInBits()), CurrOffset) ++ .getReg(0); ++ LoadPtr = MIB.buildPtrAdd(LoadTy, Src, Offset).getReg(0); + } + auto LdVal = MIB.buildLoad(CopyTy, LoadPtr, *LoadMMO); + + // Create the store. +- Register StorePtr = +- CurrOffset == 0 ? Dst : MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); ++ Register StorePtr = Dst; ++ if (CurrOffset != 0) { ++ LLT StoreTy = MRI.getType(Dst); ++ StorePtr = MIB.buildPtrAdd(StoreTy, Dst, Offset).getReg(0); ++ } + MIB.buildStore(LdVal, StorePtr, *StoreMMO); + CurrOffset += CopyTy.getSizeInBytes(); + Size -= CopyTy.getSizeInBytes(); +@@ -1343,7 +1347,6 @@ bool CombinerHelper::optimizeMemmove(MachineInstr &MI, Register Dst, + // Apart from that, this loop is pretty much doing the same thing as the + // memcpy codegen function. + unsigned CurrOffset = 0; +- LLT PtrTy = MRI.getType(Src); + SmallVector LoadVals; + for (auto CopyTy : MemOps) { + // Construct MMO for the load. +@@ -1353,9 +1356,10 @@ bool CombinerHelper::optimizeMemmove(MachineInstr &MI, Register Dst, + // Create the load. + Register LoadPtr = Src; + if (CurrOffset != 0) { ++ LLT LoadTy = MRI.getType(Src); + auto Offset = +- MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset); +- LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0); ++ MIB.buildConstant(LLT::scalar(LoadTy.getSizeInBits()), CurrOffset); ++ LoadPtr = MIB.buildPtrAdd(LoadTy, Src, Offset).getReg(0); + } + LoadVals.push_back(MIB.buildLoad(CopyTy, LoadPtr, *LoadMMO).getReg(0)); + CurrOffset += CopyTy.getSizeInBytes(); +@@ -1370,9 +1374,10 @@ bool CombinerHelper::optimizeMemmove(MachineInstr &MI, Register Dst, + + Register StorePtr = Dst; + if (CurrOffset != 0) { ++ LLT StoreTy = MRI.getType(Dst); + auto Offset = +- MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset); +- StorePtr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); ++ MIB.buildConstant(LLT::scalar(StoreTy.getSizeInBits()), CurrOffset); ++ StorePtr = MIB.buildPtrAdd(StoreTy, Dst, Offset).getReg(0); + } + MIB.buildStore(LoadVals[I], StorePtr, *StoreMMO); + CurrOffset += CopyTy.getSizeInBytes(); +-- +2.29.2 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0050-llvm-julia-tsan-custom-as.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0050-llvm-julia-tsan-custom-as.patch new file mode 100644 index 00000000000..a6f8a42ad2e --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0050-llvm-julia-tsan-custom-as.patch @@ -0,0 +1,28 @@ +From bd41be423127b8946daea805290ad2eb19e66be4 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Sat, 19 May 2018 11:56:55 -0400 +Subject: [PATCH] [TSAN] Allow for custom address spaces + +Julia uses addressspaces for GC and we want these to be sanitized as well. +--- + lib/Transforms/Instrumentation/ThreadSanitizer.cpp | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/lib/Transforms/Instrumentation/ThreadSanitizer.cpp b/lib/Transforms/Instrumentation/ThreadSanitizer.cpp +index ec6904486e1..9d673353f43 100644 +--- a/lib/Transforms/Instrumentation/ThreadSanitizer.cpp ++++ b/lib/Transforms/Instrumentation/ThreadSanitizer.cpp +@@ -296,7 +296,9 @@ static bool shouldInstrumentReadWriteFromAddress(const Module *M, Value *Addr) { + // with them. + if (Addr) { + Type *PtrTy = cast(Addr->getType()->getScalarType()); +- if (PtrTy->getPointerAddressSpace() != 0) ++ auto AS = PtrTy->getPointerAddressSpace(); ++ // Allow for custom addresspaces ++ if (AS != 0 && AS < 10) + return false; + } + +-- +2.17.0 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0052-llvm-11-D94813-mergeicmps.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0052-llvm-11-D94813-mergeicmps.patch new file mode 100644 index 00000000000..5eb98be41cb --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0052-llvm-11-D94813-mergeicmps.patch @@ -0,0 +1,111 @@ +From 5fda6724d697d428136266a61159a46c5da092f0 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Sat, 16 Jan 2021 17:36:09 -0500 +Subject: [PATCH] [MergeICmps] Don't merge icmps derived from pointers with + addressspaces + +IIUC we can't emit `memcmp` between pointers in addressspaces, +doing so will trigger an assertion since the signature of the memcmp +will not match it's arguments (https://bugs.llvm.org/show_bug.cgi?id=48661). + +This PR disables the attempt to merge icmps, +when the pointer is in an addressspace. + +Differential Revision: https://reviews.llvm.org/D94813 +--- + llvm/lib/Transforms/Scalar/MergeICmps.cpp | 4 ++ + .../Transforms/MergeICmps/addressspaces.ll | 67 +++++++++++++++++++ + 2 files changed, 71 insertions(+) + create mode 100644 llvm/test/Transforms/MergeICmps/addressspaces.ll + +diff --git llvm/lib/Transforms/Scalar/MergeICmps.cpp llvm/lib/Transforms/Scalar/MergeICmps.cpp +index 1559e7a41a7c..621c9e504398 100644 +--- llvm/lib/Transforms/Scalar/MergeICmps.cpp ++++ llvm/lib/Transforms/Scalar/MergeICmps.cpp +@@ -154,6 +154,10 @@ BCEAtom visitICmpLoadOperand(Value *const Val, BaseIdentifier &BaseId) { + return {}; + } + Value *const Addr = LoadI->getOperand(0); ++ if (Addr->getType()->getPointerAddressSpace() != 0) { ++ LLVM_DEBUG(dbgs() << "from non-zero AddressSpace\n"); ++ return {}; ++ } + auto *const GEP = dyn_cast(Addr); + if (!GEP) + return {}; +diff --git llvm/test/Transforms/MergeICmps/addressspaces.ll llvm/test/Transforms/MergeICmps/addressspaces.ll +new file mode 100644 +index 000000000000..9a74b4a5b2ca +--- /dev/null ++++ llvm/test/Transforms/MergeICmps/addressspaces.ll +@@ -0,0 +1,67 @@ ++; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ++; RUN: opt < %s -mergeicmps -S | FileCheck %s ++ ++source_filename = "==" ++target datalayout = "e-m:e-i64:64-n32:64" ++target triple = "powerpc64le-unknown-linux-gnu" ++ ++define void @juliaAS([2 x [5 x i64]] addrspace(11)* nocapture nonnull readonly align 8 dereferenceable(80) %0, [2 x [5 x i64]] addrspace(11)* nocapture nonnull readonly align 8 dereferenceable(80) %1) { ++; CHECK-LABEL: @juliaAS( ++; CHECK-NEXT: top: ++; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* [[TMP0:%.*]], i64 0, i64 1, i64 2 ++; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* [[TMP0]], i64 0, i64 1, i64 3 ++; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* [[TMP0]], i64 0, i64 1, i64 4 ++; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* [[TMP1:%.*]], i64 0, i64 1, i64 2 ++; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* [[TMP1]], i64 0, i64 1, i64 3 ++; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* [[TMP1]], i64 0, i64 1, i64 4 ++; CHECK-NEXT: [[TMP8:%.*]] = load i64, i64 addrspace(11)* [[TMP2]], align 8 ++; CHECK-NEXT: [[TMP9:%.*]] = load i64, i64 addrspace(11)* [[TMP5]], align 8 ++; CHECK-NEXT: [[DOTNOT17:%.*]] = icmp eq i64 [[TMP8]], [[TMP9]] ++; CHECK-NEXT: br i1 [[DOTNOT17]], label [[L70:%.*]], label [[L90:%.*]] ++; CHECK: L70: ++; CHECK-NEXT: [[TMP10:%.*]] = load i64, i64 addrspace(11)* [[TMP3]], align 8 ++; CHECK-NEXT: [[TMP11:%.*]] = load i64, i64 addrspace(11)* [[TMP6]], align 8 ++; CHECK-NEXT: [[DOTNOT18:%.*]] = icmp eq i64 [[TMP10]], [[TMP11]] ++; CHECK-NEXT: br i1 [[DOTNOT18]], label [[L74:%.*]], label [[L90]] ++; CHECK: L74: ++; CHECK-NEXT: [[TMP12:%.*]] = load i64, i64 addrspace(11)* [[TMP4]], align 8 ++; CHECK-NEXT: [[TMP13:%.*]] = load i64, i64 addrspace(11)* [[TMP7]], align 8 ++; CHECK-NEXT: [[DOTNOT19:%.*]] = icmp eq i64 [[TMP12]], [[TMP13]] ++; CHECK-NEXT: br label [[L90]] ++; CHECK: L90: ++; CHECK-NEXT: [[VALUE_PHI2_OFF0:%.*]] = phi i1 [ false, [[TOP:%.*]] ], [ [[DOTNOT19]], [[L74]] ], [ false, [[L70]] ] ++; CHECK-NEXT: ret void ++; ++top: ++ %2 = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* %0, i64 0, i64 1, i64 2 ++ %3 = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* %0, i64 0, i64 1, i64 3 ++ %4 = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* %0, i64 0, i64 1, i64 4 ++ %5 = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* %1, i64 0, i64 1, i64 2 ++ %6 = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* %1, i64 0, i64 1, i64 3 ++ %7 = getelementptr inbounds [2 x [5 x i64]], [2 x [5 x i64]] addrspace(11)* %1, i64 0, i64 1, i64 4 ++ %8 = load i64, i64 addrspace(11)* %2, align 8 ++ %9 = load i64, i64 addrspace(11)* %5, align 8 ++ %.not17 = icmp eq i64 %8, %9 ++ br i1 %.not17, label %L70, label %L90 ++ ++L70: ; preds = %top ++ %10 = load i64, i64 addrspace(11)* %3, align 8 ++ %11 = load i64, i64 addrspace(11)* %6, align 8 ++ %.not18 = icmp eq i64 %10, %11 ++ br i1 %.not18, label %L74, label %L90 ++ ++L74: ; preds = %L70 ++ %12 = load i64, i64 addrspace(11)* %4, align 8 ++ %13 = load i64, i64 addrspace(11)* %7, align 8 ++ %.not19 = icmp eq i64 %12, %13 ++ br label %L90 ++ ++L90: ; preds = %L74, %L70, %top ++ %value_phi2.off0 = phi i1 [ false, %top ], [ %.not19, %L74 ], [ false, %L70 ] ++ ret void ++} ++ ++!llvm.module.flags = !{!0} ++ ++!0 = !{i32 1, !"Debug Info Version", i32 3} ++ +-- +2.30.0 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0060-llvm-invalid-addrspacecast-sink.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0060-llvm-invalid-addrspacecast-sink.patch new file mode 100644 index 00000000000..5e6dd196cd3 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0060-llvm-invalid-addrspacecast-sink.patch @@ -0,0 +1,116 @@ +commit 291f2c3c30ab667b7dd39fbf162b737d64f56492 +Author: Tim Besard +Date: Fri Nov 27 09:19:40 2020 +0100 + + Don't sink ptrtoint/inttoptr sequences into non-noop addrspacecasts. + + Differential Revision: https://reviews.llvm.org/D92210 + +diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp +index 40e92b9e0a..0b90c9c0fc 100644 +--- a/lib/CodeGen/CodeGenPrepare.cpp ++++ b/lib/CodeGen/CodeGenPrepare.cpp +@@ -5041,18 +5041,29 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, + WeakTrackingVH SunkAddrVH = SunkAddrs[Addr]; + + Value * SunkAddr = SunkAddrVH.pointsToAliveValue() ? SunkAddrVH : nullptr; ++ Type *IntPtrTy = DL->getIntPtrType(Addr->getType()); + if (SunkAddr) { + LLVM_DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode + << " for " << *MemoryInst << "\n"); +- if (SunkAddr->getType() != Addr->getType()) +- SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType()); ++ if (SunkAddr->getType() != Addr->getType()) { ++ // Even though we only considered no-op addrspacecasts, ++ // semantically-meaningful conversions may still be present due to ++ // ptrtoint/inttoptr sequences. ++ if (SunkAddr->getType()->getPointerAddressSpace() != ++ Addr->getType()->getPointerAddressSpace() && ++ !DL->isNonIntegralPointerType(Addr->getType())) { ++ SunkAddr = Builder.CreatePtrToInt(SunkAddr, IntPtrTy, "sunkaddr"); ++ SunkAddr = ++ Builder.CreateIntToPtr(SunkAddr, Addr->getType(), "sunkaddr"); ++ } else ++ SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType()); ++ } + } else if (AddrSinkUsingGEPs || (!AddrSinkUsingGEPs.getNumOccurrences() && + SubtargetInfo->addrSinkUsingGEPs())) { + // By default, we use the GEP-based method when AA is used later. This + // prevents new inttoptr/ptrtoint pairs from degrading AA capabilities. + LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode + << " for " << *MemoryInst << "\n"); +- Type *IntPtrTy = DL->getIntPtrType(Addr->getType()); + Value *ResultPtr = nullptr, *ResultIndex = nullptr; + + // First, find the pointer. +@@ -5181,8 +5192,19 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, + : Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr"); + } + +- if (SunkAddr->getType() != Addr->getType()) +- SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType()); ++ if (SunkAddr->getType() != Addr->getType()) { ++ // Even though we only considered no-op addrspacecasts, ++ // semantically-meaningful conversions may still be present due to ++ // ptrtoint/inttoptr sequences. ++ if (SunkAddr->getType()->getPointerAddressSpace() != ++ Addr->getType()->getPointerAddressSpace() && ++ !DL->isNonIntegralPointerType(Addr->getType())) { ++ SunkAddr = Builder.CreatePtrToInt(SunkAddr, IntPtrTy, "sunkaddr"); ++ SunkAddr = ++ Builder.CreateIntToPtr(SunkAddr, Addr->getType(), "sunkaddr"); ++ } else ++ SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType()); ++ } + } + } else { + // We'd require a ptrtoint/inttoptr down the line, which we can't do for +diff --git a/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll b/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll +new file mode 100644 +index 0000000000..39e50241c9 +--- /dev/null ++++ b/test/Transforms/CodeGenPrepare/NVPTX/dont-introduce-addrspacecast.ll +@@ -0,0 +1,43 @@ ++; RUN: opt -S -codegenprepare < %s | FileCheck %s ++ ++target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" ++target triple = "nvptx64-nvidia-cuda" ++ ++ ++; ptrtoint/inttoptr combinations can introduce semantically-meaningful address space casts ++; which we can't sink into an addrspacecast ++ ++; CHECK-LABEL: @test ++define void @test(i8* %input_ptr) { ++ ; CHECK-LABEL: l1: ++ ; CHECK-NOT: addrspacecast ++ %intptr = ptrtoint i8* %input_ptr to i64 ++ %ptr = inttoptr i64 %intptr to i32 addrspace(3)* ++ ++ br label %l1 ++l1: ++ ++ store atomic i32 1, i32 addrspace(3)* %ptr unordered, align 4 ++ ret void ++} ++ ++ ++; we still should be able to look through multiple sequences of inttoptr/ptrtoint ++ ++; CHECK-LABEL: @test2 ++define void @test2(i8* %input_ptr) { ++ ; CHECK-LABEL: l2: ++ ; CHECK: bitcast ++ ; CHECK-NEXT: store ++ %intptr = ptrtoint i8* %input_ptr to i64 ++ %ptr = inttoptr i64 %intptr to i32 addrspace(3)* ++ ++ %intptr2 = ptrtoint i32 addrspace(3)* %ptr to i64 ++ %ptr2 = inttoptr i64 %intptr2 to i32* ++ ++ br label %l2 ++l2: ++ ++ store atomic i32 1, i32* %ptr2 unordered, align 4 ++ ret void ++} diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0071-llvm-12-D97435-AArch64-movaddrreg.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0071-llvm-12-D97435-AArch64-movaddrreg.patch new file mode 100644 index 00000000000..01d49a85f10 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/0071-llvm-12-D97435-AArch64-movaddrreg.patch @@ -0,0 +1,164 @@ +From 3adadbab531e0d7dc17499a6570b129e87f00c77 Mon Sep 17 00:00:00 2001 +From: Keno Fischer +Date: Wed, 21 Apr 2021 12:38:40 -0400 +Subject: [PATCH] [Aarch64] Correct register class for pseudo instructions + +This constrains the Mov* and similar pseudo instruction to take +GPR64common register classes rather than GPR64. GPR64 includs XZR +which is invalid here, because this pseudo instructions expands +into an adrp/add pair sharing a destination register. XZR is invalid +on add and attempting to encode it will instead increment the stack +pointer causing crashes (downstream report at [1]). The test case +there reproduces on LLVM11, but I do not have a test case that +reaches this code path on main, since it is being masked by +improved dead code elimination introduced in D91513. Nevertheless, +this seems like a good thing to fix in case there are other cases +that dead code elimination doesn't clean up (e.g. if `optnone` is +used and the optimization is skipped). + +I think it would be worth auditing uses of GPR64 in pseudo +instructions to see if there are any similar issues, but I do not +have a high enough view of the backend or knowledge of the +Aarch64 architecture to do this quickly. + +[1] https://github.com/JuliaLang/julia/issues/39818 + +Reviewed By: t.p.northover + +Differential Revision: https://reviews.llvm.org/D97435 +--- + .../AArch64/AArch64ExpandPseudoInsts.cpp | 1 + + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 32 +++++++++---------- + .../GlobalISel/select-blockaddress.mir | 5 +-- + .../select-jump-table-brjt-constrain.mir | 2 +- + .../GlobalISel/select-jump-table-brjt.mir | 2 +- + 5 files changed, 22 insertions(+), 20 deletions(-) + +diff --git llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +index e57650ae60b1..612fbeb5f531 100644 +--- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp ++++ llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +@@ -886,6 +886,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB, + case AArch64::MOVaddrEXT: { + // Expand into ADRP + ADD. + Register DstReg = MI.getOperand(0).getReg(); ++ assert(DstReg != AArch64::XZR); + MachineInstrBuilder MIB1 = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg) + .add(MI.getOperand(1)); +diff --git llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/lib/Target/AArch64/AArch64InstrInfo.td +index 171d3dbaa814..6fe0bd1ef168 100644 +--- llvm/lib/Target/AArch64/AArch64InstrInfo.td ++++ llvm/lib/Target/AArch64/AArch64InstrInfo.td +@@ -656,40 +656,40 @@ let isReMaterializable = 1, isCodeGenOnly = 1 in { + // removed, along with the AArch64Wrapper node. + + let AddedComplexity = 10 in +-def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr), +- [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, ++def LOADgot : Pseudo<(outs GPR64common:$dst), (ins i64imm:$addr), ++ [(set GPR64common:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, + Sched<[WriteLDAdr]>; + + // The MOVaddr instruction should match only when the add is not folded + // into a load or store address. + def MOVaddr +- : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), ++ : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low), ++ [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), + tglobaladdr:$low))]>, + Sched<[WriteAdrAdr]>; + def MOVaddrJT +- : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), ++ : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low), ++ [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), + tjumptable:$low))]>, + Sched<[WriteAdrAdr]>; + def MOVaddrCP +- : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), ++ : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low), ++ [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), + tconstpool:$low))]>, + Sched<[WriteAdrAdr]>; + def MOVaddrBA +- : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), ++ : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low), ++ [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), + tblockaddress:$low))]>, + Sched<[WriteAdrAdr]>; + def MOVaddrTLS +- : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi), ++ : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low), ++ [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi), + tglobaltlsaddr:$low))]>, + Sched<[WriteAdrAdr]>; + def MOVaddrEXT +- : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi), ++ : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low), ++ [(set GPR64common:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi), + texternalsym:$low))]>, + Sched<[WriteAdrAdr]>; + // Normally AArch64addlow either gets folded into a following ldr/str, +@@ -697,8 +697,8 @@ def MOVaddrEXT + // might appear without either of them, so allow lowering it into a plain + // add. + def ADDlowTLS +- : Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low), +- [(set GPR64:$dst, (AArch64addlow GPR64:$src, ++ : Pseudo<(outs GPR64sp:$dst), (ins GPR64sp:$src, i64imm:$low), ++ [(set GPR64sp:$dst, (AArch64addlow GPR64sp:$src, + tglobaltlsaddr:$low))]>, + Sched<[WriteAdr]>; + +diff --git llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir +index 45012f23de62..70cb802ed3a3 100644 +--- llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir ++++ llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir +@@ -30,9 +30,10 @@ registers: + body: | + ; CHECK-LABEL: name: test_blockaddress + ; CHECK: bb.0 (%ir-block.0): +- ; CHECK: [[MOVaddrBA:%[0-9]+]]:gpr64 = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block) ++ ; CHECK: [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block) + ; CHECK: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr +- ; CHECK: STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store 8 into @addr) ++ ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]] ++ ; CHECK: STRXui [[COPY]], [[MOVaddr]], 0 :: (store 8 into @addr) + ; CHECK: BR [[MOVaddrBA]] + ; CHECK: bb.1.block (address-taken): + ; CHECK: RET_ReallyLR +diff --git llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir +index 440a03173c83..59b8dea2d0ce 100644 +--- llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir ++++ llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir +@@ -30,7 +30,7 @@ body: | + ; CHECK: Bcc 8, %bb.3, implicit $nzcv + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) +- ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 ++ ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 + ; CHECK: early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0 + ; CHECK: BR %6 + ; CHECK: bb.2: +diff --git llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +index 6b84c6d10843..b8c9a6c881da 100644 +--- llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir ++++ llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +@@ -65,7 +65,7 @@ body: | + ; CHECK: bb.1.entry: + ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) + ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr +- ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 ++ ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 + ; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0 + ; CHECK: BR %18 + ; CHECK: bb.2.sw.bb: +-- +2.31.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/9999-llvm-symver-jlprefix.patch b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/9999-llvm-symver-jlprefix.patch new file mode 100644 index 00000000000..bdfb8e52366 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/llvm_patches/9999-llvm-symver-jlprefix.patch @@ -0,0 +1,18 @@ +From f23277bb91a4925ba8763337137a3123a7600557 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Tue, 16 Jan 2018 17:29:05 -0500 +Subject: [PATCH] add JL prefix to all LLVM version suffixes + +--- + tools/llvm-shlib/simple_version_script.map.in | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/llvm-shlib/simple_version_script.map.in b/tools/llvm-shlib/simple_version_script.map.in +index e9515fe7862..af082581627 100644 +--- a/tools/llvm-shlib/simple_version_script.map.in ++++ b/tools/llvm-shlib/simple_version_script.map.in +@@ -1 +1 @@ +-LLVM_@LLVM_VERSION_MAJOR@ { global: *; }; ++JL_LLVM_@LLVM_VERSION_MAJOR@.@LLVM_VERSION_MINOR@ { global: *; }; +-- +2.15.1 diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0050-unique_function_clang-sa.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0050-unique_function_clang-sa.patch new file mode 100644 index 00000000000..68bd11ef940 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0050-unique_function_clang-sa.patch @@ -0,0 +1,28 @@ +From 1fa6efaa946243004c45be92e66b324dc980df7d Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Thu, 17 Sep 2020 23:22:45 +0200 +Subject: [PATCH] clang-sa can't determine that !RHS implies !LHS + +--- + llvm/include/llvm/ADT/FunctionExtras.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/llvm/include/llvm/ADT/FunctionExtras.h b/llvm/include/llvm/ADT/FunctionExtras.h +index 121aa527a5d..b9b6d829b14 100644 +--- a/llvm/include/llvm/ADT/FunctionExtras.h ++++ b/llvm/include/llvm/ADT/FunctionExtras.h +@@ -193,9 +193,11 @@ public: + // Copy the callback and inline flag. + CallbackAndInlineFlag = RHS.CallbackAndInlineFlag; + ++#ifndef __clang_analyzer__ + // If the RHS is empty, just copying the above is sufficient. + if (!RHS) + return; ++#endif + + if (!isInlineStorage()) { + // The out-of-line case is easiest to move. +-- +2.28.0 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-llvm-12-musl-bb.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-llvm-12-musl-bb.patch new file mode 100644 index 00000000000..f47ba8b433c --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-llvm-12-musl-bb.patch @@ -0,0 +1,37 @@ +From f1901de14ff1f1abcc729c4adccfbd5017e30357 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Fri, 7 May 2021 13:54:41 -0400 +Subject: [PATCH] [Compiler-RT] Fix compilation on musl + +--- + compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp | 1 + + .../lib/sanitizer_common/sanitizer_platform_limits_posix.cpp | 1 - + 2 files changed, 1 insertion(+), 1 deletion(-) + +diff --git a/compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp b/compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp +index b87798603fda..452a08aafe0e 100644 +--- a/compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp ++++ b/compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp +@@ -26,6 +26,7 @@ + + #include + #include ++#include + #include // for dlsym() + + static void *getFuncAddr(const char *name, uintptr_t wrapper_addr) { +diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp +index 12dd39e674ac..bb0f7a2daa8c 100644 +--- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp ++++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp +@@ -69,7 +69,6 @@ + #include + #include + #include +-#include + #include + #include + #include +-- +2.31.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-revert-sdk-requirement-tsan.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-revert-sdk-requirement-tsan.patch new file mode 100644 index 00000000000..0296e930f72 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0100-revert-sdk-requirement-tsan.patch @@ -0,0 +1,33 @@ +From 2c3903ec175d21759d5eaaa297356a55f500c749 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Thu, 1 Oct 2020 00:06:09 -0400 +Subject: [PATCH 1/2] Revert "[TSan] Add CMake check for minimal SDK + requirements on Darwin" + +This reverts commit 3bf3996cd4ef2d4898b32d4cef52d6549bbe6820. +--- + compiler-rt/lib/tsan/CMakeLists.txt | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/compiler-rt/lib/tsan/CMakeLists.txt b/compiler-rt/lib/tsan/CMakeLists.txt +index c99b16d8aaa..9fd3e2d7792 100644 +--- a/compiler-rt/lib/tsan/CMakeLists.txt ++++ b/compiler-rt/lib/tsan/CMakeLists.txt +@@ -114,14 +114,6 @@ set(TSAN_RUNTIME_LIBRARIES) + add_compiler_rt_component(tsan) + + if(APPLE) +- # Ideally we would check the SDK version for the actual platform we are +- # building for here. To make our lifes easier we assume the host SDK setup is +- # sane and use the macOS SDK version as a proxy for aligned SDKs. +- find_darwin_sdk_version(macosx_sdk_version "macosx") +- if ("${macosx_sdk_version}" VERSION_LESS 10.12) +- message(FATAL_ERROR "Building the TSan runtime requires at least macOS SDK 10.12 (or aligned SDK on other platforms)") +- endif() +- + add_asm_sources(TSAN_ASM_SOURCES rtl/tsan_rtl_amd64.S rtl/tsan_rtl_aarch64.S) + + set(TSAN_LINK_LIBS ${SANITIZER_COMMON_LINK_LIBS}) +-- +2.28.0 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-fix-darwin-tsan-on-old-sdks.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-fix-darwin-tsan-on-old-sdks.patch new file mode 100644 index 00000000000..2278f5b54a4 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-fix-darwin-tsan-on-old-sdks.patch @@ -0,0 +1,66 @@ +From 36d2fc022bb0437333276db8c75fb43b338da343 Mon Sep 17 00:00:00 2001 +From: Julian Lettner +Date: Wed, 5 Feb 2020 08:17:06 -0800 +Subject: [PATCH 2/2] [TSan] Ensure we can compile the runtime with older SDKs + +One of my changes [1] included in this release silently bumped the +minimal macOS SDK required for building the TSan runtime to SDK 10.12. +Let's ensure release 10 does not unexpectedly break builders with old +SDKs and add proper minimal SDK checking in CMake for subsequent +releases. + +This fix `#ifdef`s out interceptors for newer APIs. Note that the +resulting TSan runtime is less complete: when these newer APIs are used +TSan will report false positives. + +Fixes llvm 10 release blocker: #44682 +https://bugs.llvm.org/show_bug.cgi?id=44682 + +[1] 894abb46f891cba2e0ef581650f27f512a7824b4 + +Reviewed By: dmajor + +Differential Revision: https://reviews.llvm.org/D74059 +--- + compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp b/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp +index aa29536d861..91584914d86 100644 +--- a/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp ++++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp +@@ -23,9 +23,12 @@ + #include + #include + #include +-#include + #include + ++#if defined(__has_include) && __has_include() ++#include ++#endif ++ + #if defined(__has_include) && __has_include() + #include + #endif // #if defined(__has_include) && __has_include() +@@ -247,6 +250,8 @@ TSAN_INTERCEPTOR(void, os_lock_unlock, void *lock) { + REAL(os_lock_unlock)(lock); + } + ++#if defined(__has_include) && __has_include() ++ + TSAN_INTERCEPTOR(void, os_unfair_lock_lock, os_unfair_lock_t lock) { + if (!cur_thread()->is_inited || cur_thread()->is_dead) { + return REAL(os_unfair_lock_lock)(lock); +@@ -286,6 +291,8 @@ TSAN_INTERCEPTOR(void, os_unfair_lock_unlock, os_unfair_lock_t lock) { + REAL(os_unfair_lock_unlock)(lock); + } + ++#endif // #if defined(__has_include) && __has_include() ++ + #if defined(__has_include) && __has_include() + + TSAN_INTERCEPTOR(void, xpc_connection_set_event_handler, +-- +2.28.0 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-llvm-12-musl-bb-32.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-llvm-12-musl-bb-32.patch new file mode 100644 index 00000000000..fe3b9f2e86d --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0101-llvm-12-musl-bb-32.patch @@ -0,0 +1,25 @@ +From f9c402508d17d5d7c4c12eb3af743cf7995682d8 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Fri, 7 May 2021 20:13:52 -0400 +Subject: [PATCH] [Compiler-RT] Fix compilation on musl 32 + +--- + .../lib/sanitizer_common/sanitizer_platform_limits_posix.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h +index 836b178c131b..e5ff490074e7 100644 +--- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h ++++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h +@@ -475,7 +475,7 @@ struct __sanitizer_dirent { + unsigned short d_reclen; + // more fields that we don't care about + }; +-#elif SANITIZER_ANDROID || defined(__x86_64__) ++#elif SANITIZER_ANDROID || defined(__x86_64__) || !defined(__GLIBC__) + struct __sanitizer_dirent { + unsigned long long d_ino; + unsigned long long d_off; +-- +2.31.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0702-apple-codesign.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0702-apple-codesign.patch new file mode 100644 index 00000000000..6d2be98ef0d --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0702-apple-codesign.patch @@ -0,0 +1,13 @@ +diff --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake b/compiler-rt/cmake/Modules/AddCompilerRT.cmake +--- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake ++++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake +@@ -321,7 +321,7 @@ + set_target_properties(${libname} PROPERTIES IMPORT_PREFIX "") + set_target_properties(${libname} PROPERTIES IMPORT_SUFFIX ".lib") + endif() +- if(APPLE) ++ if(IOS) + # Ad-hoc sign the dylibs + add_custom_command(TARGET ${libname} + POST_BUILD + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0703-apple-10..12.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0703-apple-10..12.patch new file mode 100644 index 00000000000..f3d5a72e6ce --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0703-apple-10..12.patch @@ -0,0 +1,25 @@ +From 9ca484f80dc51bc76665c7af1dbd87e46a93a2f7 Mon Sep 17 00:00:00 2001 +From: Valentin Churavy +Date: Mon, 21 Sep 2020 08:12:39 -0400 +Subject: [PATCH] disable OSX 10.12 optimization + +--- + llvm/lib/Support/Unix/Path.inc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/llvm/lib/Support/Unix/Path.inc b/llvm/lib/Support/Unix/Path.inc +index 2a03dc682bc..a15a52c430c 100644 +--- a/llvm/lib/Support/Unix/Path.inc ++++ b/llvm/lib/Support/Unix/Path.inc +@@ -1222,7 +1222,7 @@ namespace fs { + /// implementation. + std::error_code copy_file(const Twine &From, const Twine &To) { + uint32_t Flag = COPYFILE_DATA; +-#if __has_builtin(__builtin_available) && defined(COPYFILE_CLONE) ++#if __has_builtin(__builtin_available) && defined(COPYFILE_CLONE) && 0 + if (__builtin_available(macos 10.12, *)) { + bool IsSymlink; + if (std::error_code Error = is_symlink_file(From, IsSymlink)) +-- +2.28.0 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0705-D97571-AArch64-loh.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0705-D97571-AArch64-loh.patch new file mode 100644 index 00000000000..352a9504652 --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0705-D97571-AArch64-loh.patch @@ -0,0 +1,101 @@ +From 84eff6b2defb7f2d847d5bac165d6a44472b9ddf Mon Sep 17 00:00:00 2001 +From: Keno Fischer +Date: Mon, 1 Mar 2021 16:38:19 -0500 +Subject: [PATCH 2/4] [AArch64] Fix emitting an AdrpAddLdr LOH when there's a + potential clobber of the def of the adrp before the ldr. + +Apparently this pass used to have liveness analysis but it was removed for scompile time reasons. This workaround prevents the LOH from being emitted unless the ADD and LDR are adjacent. + +Fixes https://github.com/JuliaLang/julia/issues/39820 + +Reviewed By: loladiro, qcolombet + +Differential Revision: https://reviews.llvm.org/D97571 +--- + llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 26 +++++++++++++++- + .../AArch64/loh-adrp-add-ldr-clobber.mir | 30 +++++++++++++++++++ + 2 files changed, 55 insertions(+), 1 deletion(-) + create mode 100644 llvm/test/CodeGen/AArch64/loh-adrp-add-ldr-clobber.mir + +diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +index efdb1131abc9..ac243347b24d 100644 +--- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp ++++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +@@ -419,13 +419,37 @@ static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI, + ++NumADRPToLDR; + } + break; +- case MCLOH_AdrpAddLdr: ++ case MCLOH_AdrpAddLdr: { ++ // There is a possibility that the linker may try to rewrite: ++ // adrp x0, @sym@PAGE ++ // add x1, x0, @sym@PAGEOFF ++ // [x0 = some other def] ++ // ldr x2, [x1] ++ // ...into... ++ // adrp x0, @sym ++ // nop ++ // [x0 = some other def] ++ // ldr x2, [x0] ++ // ...if the offset to the symbol won't fit within a literal load. ++ // This causes the load to use the result of the adrp, which in this ++ // case has already been clobbered. ++ // FIXME: Implement proper liveness tracking for all registers. For now, ++ // don't emit the LOH if there are any instructions between the add and ++ // the ldr. ++ MachineInstr *AddMI = const_cast(Info.MI1); ++ const MachineInstr *LdrMI = Info.MI0; ++ auto AddIt = MachineBasicBlock::iterator(AddMI); ++ auto EndIt = AddMI->getParent()->end(); ++ if (AddMI->getIterator() == EndIt || LdrMI != &*next_nodbg(AddIt, EndIt)) ++ break; ++ + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" + << '\t' << MI << '\t' << *Info.MI1 << '\t' + << *Info.MI0); + AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0}); + ++NumADDToLDR; + break; ++ } + case MCLOH_AdrpAddStr: + if (Info.MI1 != nullptr) { + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" +diff --git a/llvm/test/CodeGen/AArch64/loh-adrp-add-ldr-clobber.mir b/llvm/test/CodeGen/AArch64/loh-adrp-add-ldr-clobber.mir +new file mode 100644 +index 000000000000..e1e893c6383a +--- /dev/null ++++ b/llvm/test/CodeGen/AArch64/loh-adrp-add-ldr-clobber.mir +@@ -0,0 +1,30 @@ ++# RUN: llc -o /dev/null %s -mtriple=aarch64-apple-ios -run-pass=aarch64-collect-loh -debug-only=aarch64-collect-loh 2>&1 | FileCheck %s ++--- | ++ @sym2 = local_unnamed_addr global [10000000 x i32] zeroinitializer, align 8 ++ @sym = local_unnamed_addr global i32 zeroinitializer, align 8 ++ ++ define i32 @main() { ++ ret i32 0 ++ } ++ ++... ++--- ++name: main ++alignment: 4 ++tracksRegLiveness: true ++liveins: ++ - { reg: '$x22', virtual-reg: '' } ++ - { reg: '$x21', virtual-reg: '' } ++body: | ++ bb.0: ++ liveins: $x21, $x22 ++ ; Check we don't emit an loh here because there's a clobbering def of x8 before the ldr. ++ ; CHECK-LABEL: main ++ ; CHECK-NOT: MCLOH_AdrpAddLdr ++ renamable $x8 = ADRP target-flags(aarch64-page) @sym ++ renamable $x9 = ADDXri killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @sym, 0 ++ renamable $x8 = ADDXri killed renamable $x22, 1, 0 ++ $x9 = LDRXui $x9, 0 ++ RET undef $lr ++ ++... +-- +2.25.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0706-aarch64-addrspace.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0706-aarch64-addrspace.patch new file mode 100644 index 00000000000..f046a5000ed --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0706-aarch64-addrspace.patch @@ -0,0 +1,31 @@ +From a1178fdd072b7addcf56c2f6e2298165263040bb Mon Sep 17 00:00:00 2001 +From: Tim Northover +Date: Thu, 25 Feb 2021 10:13:59 +0000 +Subject: [PATCH 3/4] AArch64: relax address-space assertion in FastISel. + +Some people are using alternative address spaces to track GC data, but +otherwise they behave exactly the same. This is the only place in the backend +we even try to care about it so it's really not achieving anything. +--- + llvm/lib/Target/AArch64/AArch64FastISel.cpp | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp +index 0f63f4ca62e5..cf3ebed6ef19 100644 +--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp ++++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp +@@ -526,10 +526,7 @@ unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) { + MVT VT = CEVT.getSimpleVT(); + // arm64_32 has 32-bit pointers held in 64-bit registers. Because of that, + // 'null' pointers need to have a somewhat special treatment. +- if (const auto *CPN = dyn_cast(C)) { +- (void)CPN; +- assert(CPN->getType()->getPointerAddressSpace() == 0 && +- "Unexpected address space"); ++ if (isa(C)) { + assert(VT == MVT::i64 && "Expected 64-bit pointers"); + return materializeInt(ConstantInt::get(Type::getInt64Ty(*Context), 0), VT); + } +-- +2.25.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0707-PR49357-AArch64-FastIsel-bug.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0707-PR49357-AArch64-FastIsel-bug.patch new file mode 100644 index 00000000000..5ab5e96c37a --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0707-PR49357-AArch64-FastIsel-bug.patch @@ -0,0 +1,50 @@ +From d82434785ecab16223a0bd4ec8ede020bf244003 Mon Sep 17 00:00:00 2001 +From: Keno Fischer +Date: Mon, 1 Mar 2021 16:42:05 -0500 +Subject: [PATCH 4/4] AArch64: Remove Bad optimization + +Removes the code responsible for causing https://bugs.llvm.org/show_bug.cgi?id=49357. +A fix is in progress upstream, but I don't think it's easy, so this +fixes the bug in the meantime. The optimization it does is minor. +--- + llvm/lib/Target/AArch64/AArch64FastISel.cpp | 24 --------------------- + 1 file changed, 24 deletions(-) + +diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp +index cf3ebed6ef19..6908a51c47d6 100644 +--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp ++++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp +@@ -4600,30 +4600,6 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) { + + // Try to optimize already sign-/zero-extended values from function arguments. + bool IsZExt = isa(I); +- if (const auto *Arg = dyn_cast(I->getOperand(0))) { +- if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { +- if (RetVT == MVT::i64 && SrcVT != MVT::i64) { +- unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); +- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, +- TII.get(AArch64::SUBREG_TO_REG), ResultReg) +- .addImm(0) +- .addReg(SrcReg, getKillRegState(SrcIsKill)) +- .addImm(AArch64::sub_32); +- SrcReg = ResultReg; +- } +- // Conservatively clear all kill flags from all uses, because we are +- // replacing a sign-/zero-extend instruction at IR level with a nop at MI +- // level. The result of the instruction at IR level might have been +- // trivially dead, which is now not longer true. +- unsigned UseReg = lookUpRegForValue(I); +- if (UseReg) +- MRI.clearKillFlags(UseReg); +- +- updateValueMap(I, SrcReg); +- return true; +- } +- } +- + unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); + if (!ResultReg) + return false; +-- +2.25.1 + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0708-Do-not-patch-FDE-symbols-on-AArch64.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0708-Do-not-patch-FDE-symbols-on-AArch64.patch new file mode 100644 index 00000000000..c62e65765ae --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0708-Do-not-patch-FDE-symbols-on-AArch64.patch @@ -0,0 +1,158 @@ +From 7133a3d3b0bd639d36d9d40f1135159442ab73c7 Mon Sep 17 00:00:00 2001 +From: Cody Tapscott +Date: Mon, 24 May 2021 15:11:39 -0700 +Subject: [PATCH] Do not patch FDE symbols in RuntimeDyld, on targets that use + non-absolute symbol relocations in `.eh_frame` + +Since processFDE adds a delta to the values in the FDE, it assumes that the relocations for the .eh_frame section have not been applied by RuntimeDyld. It expects instead that only the relocation addend has been written to the symbol locations, and that the section-to-section offset needs to be added. + +However, there are platform differences that interfere with this: +1) X86-64 has DwarfFDESymbolsUseAbsDiff enabled in its AsmInfo, causing an absolute symbol to be emitted for the FDE pcStart. Absolute symbols are skipped as a relocation by RuntimeDyld, so the processFDE function in RuntimeDyldMachO.cpp calculates the relocation correctly. +2) AArch64 has DwarfFDESymbolsUseAbsDiff disabled, so a relocation is emitted in the eh_frame section. Since this isn't absolute, the relocation is applied by RuntimeDyld. This means that processFDE ends up adding an additional section-to-section offset to the pcStart field, generating an incorrect FDE + +Differential Revision: https://reviews.llvm.org/D103052 +--- + .../RuntimeDyld/RuntimeDyldMachO.cpp | 37 +++++++++++-------- + .../RuntimeDyld/RuntimeDyldMachO.h | 8 +++- + .../Targets/RuntimeDyldMachOAArch64.h | 2 + + .../RuntimeDyld/Targets/RuntimeDyldMachOARM.h | 2 + + .../Targets/RuntimeDyldMachOI386.h | 2 + + .../Targets/RuntimeDyldMachOX86_64.h | 2 + + 6 files changed, 35 insertions(+), 18 deletions(-) + +diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp +index 9ca76602ea18..e61bfd1bd31c 100644 +--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp ++++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp +@@ -272,9 +272,9 @@ RuntimeDyldMachOCRTPBase::finalizeLoad(const ObjectFile &Obj, + } + + template +-unsigned char *RuntimeDyldMachOCRTPBase::processFDE(uint8_t *P, +- int64_t DeltaForText, +- int64_t DeltaForEH) { ++unsigned char *RuntimeDyldMachOCRTPBase::patchFDERelocations(uint8_t *P, ++ int64_t DeltaForText, ++ int64_t DeltaForEH) { + typedef typename Impl::TargetPtrT TargetPtrT; + + LLVM_DEBUG(dbgs() << "Processing FDE: Delta for text: " << DeltaForText +@@ -324,19 +324,24 @@ void RuntimeDyldMachOCRTPBase::registerEHFrames() { + continue; + SectionEntry *Text = &Sections[SectionInfo.TextSID]; + SectionEntry *EHFrame = &Sections[SectionInfo.EHFrameSID]; +- SectionEntry *ExceptTab = nullptr; +- if (SectionInfo.ExceptTabSID != RTDYLD_INVALID_SECTION_ID) +- ExceptTab = &Sections[SectionInfo.ExceptTabSID]; +- +- int64_t DeltaForText = computeDelta(Text, EHFrame); +- int64_t DeltaForEH = 0; +- if (ExceptTab) +- DeltaForEH = computeDelta(ExceptTab, EHFrame); +- +- uint8_t *P = EHFrame->getAddress(); +- uint8_t *End = P + EHFrame->getSize(); +- while (P != End) { +- P = processFDE(P, DeltaForText, DeltaForEH); ++ ++ // If the FDE includes absolute symbol relocations (not supported ++ // by RuntimeDyld), we need to manually patch-up the values ++ if (doDwarfFDESymbolsUseAbsDiff()) { ++ SectionEntry *ExceptTab = nullptr; ++ if (SectionInfo.ExceptTabSID != RTDYLD_INVALID_SECTION_ID) ++ ExceptTab = &Sections[SectionInfo.ExceptTabSID]; ++ ++ int64_t DeltaForText = computeDelta(Text, EHFrame); ++ int64_t DeltaForEH = 0; ++ if (ExceptTab) ++ DeltaForEH = computeDelta(ExceptTab, EHFrame); ++ ++ uint8_t *P = EHFrame->getAddress(); ++ uint8_t *End = P + EHFrame->getSize(); ++ while (P != End) { ++ P = patchFDERelocations(P, DeltaForText, DeltaForEH); ++ } + } + + MemMgr.registerEHFrames(EHFrame->getAddress(), EHFrame->getLoadAddress(), +diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h +index 650e7b79fbb8..a7e5c9cb56e8 100644 +--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h ++++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h +@@ -43,6 +43,10 @@ protected: + SID ExceptTabSID; + }; + ++ // Returns true if the FDE section includes absolute symbol relocations ++ // on this platform. ++ virtual bool doDwarfFDESymbolsUseAbsDiff() = 0; ++ + // When a module is loaded we save the SectionID of the EH frame section + // in a table until we receive a request to register all unregistered + // EH frame sections with the memory manager. +@@ -147,8 +151,8 @@ private: + Impl &impl() { return static_cast(*this); } + const Impl &impl() const { return static_cast(*this); } + +- unsigned char *processFDE(uint8_t *P, int64_t DeltaForText, +- int64_t DeltaForEH); ++ unsigned char *patchFDERelocations(uint8_t *P, int64_t DeltaForText, ++ int64_t DeltaForEH); + + public: + RuntimeDyldMachOCRTPBase(RuntimeDyld::MemoryManager &MemMgr, +diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h +index f2ee1b06d494..90a9a4c44c84 100644 +--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h ++++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h +@@ -30,6 +30,8 @@ public: + + unsigned getStubAlignment() override { return 8; } + ++ bool doDwarfFDESymbolsUseAbsDiff() override { return false; } ++ + /// Extract the addend encoded in the instruction / memory location. + Expected decodeAddend(const RelocationEntry &RE) const { + const SectionEntry &Section = Sections[RE.SectionID]; +diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h +index a76958a9e2c2..7281249d25bf 100644 +--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h ++++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h +@@ -33,6 +33,8 @@ public: + + unsigned getStubAlignment() override { return 4; } + ++ bool doDwarfFDESymbolsUseAbsDiff() override { return false; } ++ + Expected getJITSymbolFlags(const SymbolRef &SR) override { + auto Flags = RuntimeDyldImpl::getJITSymbolFlags(SR); + if (!Flags) +diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h +index 523deb29b723..755bc13afeb4 100644 +--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h ++++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h +@@ -30,6 +30,8 @@ public: + + unsigned getStubAlignment() override { return 1; } + ++ bool doDwarfFDESymbolsUseAbsDiff() override { return true; } ++ + Expected + processRelocationRef(unsigned SectionID, relocation_iterator RelI, + const ObjectFile &BaseObjT, +diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h +index 28febbdb948c..9854da24a2ce 100644 +--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h ++++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h +@@ -30,6 +30,8 @@ public: + + unsigned getStubAlignment() override { return 8; } + ++ bool doDwarfFDESymbolsUseAbsDiff() override { return true; } ++ + Expected + processRelocationRef(unsigned SectionID, relocation_iterator RelI, + const ObjectFile &BaseObjT, +-- +2.30.1 (Apple Git-130) + diff --git a/L/LLVM/LLVM_full@12.0.1/bundled/patches/0709-Force-.eh_frame-emission-on-AArch64.patch b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0709-Force-.eh_frame-emission-on-AArch64.patch new file mode 100644 index 00000000000..aff55f35e7b --- /dev/null +++ b/L/LLVM/LLVM_full@12.0.1/bundled/patches/0709-Force-.eh_frame-emission-on-AArch64.patch @@ -0,0 +1,31 @@ +From 026f3518c4713e388a8ed06fa032e0925d35c6f5 Mon Sep 17 00:00:00 2001 +From: Cody Tapscott +Date: Mon, 24 May 2021 16:36:06 -0700 +Subject: [PATCH] Force `.eh_frame` emission on AArch64 + +We need to force the emission of the EH Frame section (currently done via SupportsCompactUnwindWithoutEHFrame in the MCObjectFileInfo for the target), since libunwind doesn't yet support dynamically registering compact unwind information at run-time. +--- + llvm/lib/MC/MCObjectFileInfo.cpp | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp +index 1a448f040b3b..e12154deca5f 100644 +--- a/llvm/lib/MC/MCObjectFileInfo.cpp ++++ b/llvm/lib/MC/MCObjectFileInfo.cpp +@@ -57,9 +57,10 @@ void MCObjectFileInfo::initMachOMCObjectFileInfo(const Triple &T) { + MachO::S_ATTR_STRIP_STATIC_SYMS | MachO::S_ATTR_LIVE_SUPPORT, + SectionKind::getReadOnly()); + +- if (T.isOSDarwin() && +- (T.getArch() == Triple::aarch64 || T.getArch() == Triple::aarch64_32)) +- SupportsCompactUnwindWithoutEHFrame = true; ++ // Disabled for now, since we need to emit EH Frames for stack unwinding in the JIT ++ // if (T.isOSDarwin() && ++ // (T.getArch() == Triple::aarch64 || T.getArch() == Triple::aarch64_32)) ++ // SupportsCompactUnwindWithoutEHFrame = true; + + if (T.isWatchABI()) + OmitDwarfIfHaveCompactUnwind = true; +-- +2.30.1 (Apple Git-130) + diff --git a/L/LLVM/common.jl b/L/LLVM/common.jl index 1c33f54d397..03bb106491d 100644 --- a/L/LLVM/common.jl +++ b/L/LLVM/common.jl @@ -13,6 +13,7 @@ const llvm_tags = Dict( v"11.0.0" => "176249bd6732a8044d457092ed932768724a6f06", v"11.0.1" => "43ff75f2c3feef64f9d73328230d34dac8832a91", v"12.0.0" => "d28af7c654d8db0b68c175db5ce212d74fb5e9bc", + v"12.0.1" => "fed41342a82f5a3a9201819a82bf7a48313e296b", ) const buildscript = raw""" diff --git a/L/LLVM/libLLVM@9.0.1/build_tarballs.jl b/L/LLVM/libLLVM@9.0.1/build_tarballs.jl index ee8beab249a..55118a1275d 100644 --- a/L/LLVM/libLLVM@9.0.1/build_tarballs.jl +++ b/L/LLVM/libLLVM@9.0.1/build_tarballs.jl @@ -1,5 +1,5 @@ name = "libLLVM" -version = v"9.0.1+4" +version = v"9.0.1+5" # Include common tools include("../common.jl")