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div.cmp
26 lines (24 loc) · 1.07 KB
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div.cmp
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--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
component div
PORT
(
clock : IN STD_LOGIC ;
denom : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (13 DOWNTO 0)
);
end component;