HW assignment of Testing and Fault Tolerance course, BIST module for RiscV core.
bist folder
core rtl
synthesis scripts and netlists
core rtl tbs
tmp scripts
scan chains insertion script starting from synthesized netlist insert scan chains and generate a dft netlist a nd the relative STIL procedure (for TMAX script)
synthesis script
Synthesized netlists can be found in syn/standalone folder, it's possible to add dft features directly on the "clean" netlist or on the one with clock gating scan cells (used by default).
TMAX script for fault testing purposes.
The purpose of this project is to design a Logic-BIST for testing a RISCV core trough the adoption of some testing techniques presented during the course (Here is presented an example of the Test-per-scan technique, with some differences) and usage of industrial tools (TetraMax, Modelsim, DesignCompiler).
The constraints in terms of test coverage, are at least 70% of coverage for the Stuck-At fault model