experimental_results.tex

\chapter{Experimental Results}
The aim of this Chapter is to show the results obtained from the design choices implemented. In particular, the specifications of the systems are evaluated as well as the FPGA resource usage, which is very useful to know in order to evaluate which future extensions to implement.

Starting from the specifications, as anticipated, the purpose of this project was to design a simple, modular, and extensible microcontroller able to provide all I/O functionalities to support its usage in a realistic environment. All tests performed have shown that the system fulfils all of the requirements. In fact, MC2101 is able to interface correctly with all of the interconnected hardware components of the DE1-SoC. The infrastructure built for bridging the communications between the UART and a Terminal Emulator allows the user to interact correctly with the system by using any platform that have a USB driver inside. Assessed that also the interrupt mechanism fully responds to external triggers, the system requirements have been fully fulfilled.

Thanks to the fact that the main memory has been designed to be synthesised in the embedded M10K blocks of the Cyclone-V FPGA, it is possible to extend the available RAM without wasting LUTs. Considering that only 3\% of the M10K blocks available on the target FPGA are currently used, and that the architecture actually takes advantage of a very small portion of the addressable space there is plenty of room for future developments.

\begin{table}
\centering
\begin{tabular}{| p{3cm} | p{2cm} | p{2cm} | p{2cm} |}
 \hline
 \textbf{Resource Name} & \textbf{Used Amount} & \textbf{Total Amount} & \textbf{Percentage Used}\\ \hline
 \hline\hline
 ALM & 2628 & 32070 & 8\% \\ 
 \hline
 FF & 3443 & 64140  & 5\% \\
 \hline
 PIN & 36 & 457  & 8\% \\
 \hline
 M10K Bit & 131072 & 4065280 & 3\% \\
 \hline
 RAM Block & 16 & 397 & 4\% \\
 \hline
\end{tabular}
\caption{MC2101 resource usage on Cyclone-V FPGA.}
\label{tab:res} % \ref{tab:res}
\end{table}

More details about FPGA resource usage are reported in Table \ref{tab:res}. It is possible to see that the architecture of MC2101 takes advantage of a very small percentage of the available resources on the Cyclone-V, which allows a great deal of freedom for future extensions.

To conclude the discussion, it is useful also to compare the results of the MC2101 synthesis with those of PULPino, which has been the reference architecture and will still be source of inspiration for future developments. Unfortunately, following several attempts, was not possible to correctly synthesize PULPino on the Cyclone-V using Quartus software.

This is due to the outdated release of the software, that does not support some of the SystemVerilog HDL structures coded inside PULPino. For instance, the memories in PULPino are designed to be synthesized within Vivado HLS for Xilix FPGAs that are not supported in Quartus. Because it was not possible to synthesize PULPino using MC2101 synthesis environment, the two architectures have been synthesized using Vivado HLS in order to have a report generated by the same synthesis software and also in order to have a comparison between the architecture that is useful to understand what results to expect from future developments of our microcontroller.

\begin{table}
\centering
\begin{tabular}{| p{3cm} | p{2cm} | p{2cm} | p{2cm} |}
 \hline
 \textbf{Resource Name} & \textbf{PULPino Usage} & \textbf{MC2101 Usage}\\ \hline
 \hline\hline
  LUT & 15657  & 3440\\ 
 \hline
 FF & 9883  & 3253 \\
 \hline
 PINS & 143 & 36 \\
 \hline
 BRAM & 16 & 4 \\
 \hline
\end{tabular}
\caption{PULPino and MC2101 resource usage comparison on Artix-7 FPGA.}
\label{tab:res2} % \ref{tab:res2}
\end{table}

Table \ref{tab:res2} shows the resource usage of both MC2101 and PULPino synthesized on the Artix-7 FPGA using Vivado HLS. As expected, because PULPino implements a typical AMBA-based full-featured design, it is a much more complex embedded system than the current MC2101 and so the resources required for the synthesis are much higher. The memory blocks for instance are 16 instead of 4 because PULPino makes use of 64 KB memory, divided into instruction RAM and data RAM, while MC2101 only uses one 16 KB single port memory. The higher number of peripherals, the pipelined architecture of the processor and the higher complexity of the bus infrastructure are the reasons of which PULPino needs more sequential elements (FF) as well as LUT to implement all the logic required.