From 1d7960fadffae69b2fdbd09b107660971799edda Mon Sep 17 00:00:00 2001 From: Lucas Steuernagel <38472950+LucasSte@users.noreply.github.com> Date: Thu, 21 Dec 2023 00:29:39 -0300 Subject: [PATCH] [SOL] Remove LE byte swap and input buffers (#75) This PR addressed two more items in solana-labs/solana#34250. It removes the little endian byte swap instructions (solana-labs/rbpf#493) and the input buffers related instructions (solana-labs/rbpf#251). --- .../SBF/Disassembler/SBFDisassembler.cpp | 59 ++++++++----------- llvm/lib/Target/SBF/SBFInstrInfo.td | 40 ------------- llvm/test/CodeGen/SBF/ninline_asm.ll | 4 -- llvm/test/MC/Disassembler/SBF/sbf-alu.txt | 6 -- llvm/test/MC/Disassembler/SBF/sbf-ldst.txt | 14 ----- llvm/test/MC/SBF/sbf-alu.s | 9 --- llvm/test/MC/SBF/sbf-ldst.s | 21 ------- 7 files changed, 24 insertions(+), 129 deletions(-) diff --git a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp index 042776f28bb25f..c5f454c783f903 100644 --- a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp +++ b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp @@ -44,12 +44,7 @@ class SBFDisassembler : public MCDisassembler { SBF_ALU64 = 0x7 }; - enum SBF_SIZE { - SBF_W = 0x0, - SBF_H = 0x1, - SBF_B = 0x2, - SBF_DW = 0x3 - }; + enum SBF_SIZE { SBF_W = 0x0, SBF_H = 0x1, SBF_B = 0x2, SBF_DW = 0x3 }; enum SBF_MODE { SBF_IMM = 0x0, @@ -82,7 +77,6 @@ static MCDisassembler *createSBFDisassembler(const Target &T, return new SBFDisassembler(STI, Ctx); } - extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSBFDisassembler() { // Register the disassembler. TargetRegistry::RegisterMCDisassembler(getTheSBFXTarget(), @@ -90,8 +84,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSBFDisassembler() { } static const unsigned GPRDecoderTable[] = { - SBF::R0, SBF::R1, SBF::R2, SBF::R3, SBF::R4, SBF::R5, - SBF::R6, SBF::R7, SBF::R8, SBF::R9, SBF::R10, SBF::R11}; + SBF::R0, SBF::R1, SBF::R2, SBF::R3, SBF::R4, SBF::R5, + SBF::R6, SBF::R7, SBF::R8, SBF::R9, SBF::R10, SBF::R11}; static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, @@ -105,8 +99,8 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, } static const unsigned GPR32DecoderTable[] = { - SBF::W0, SBF::W1, SBF::W2, SBF::W3, SBF::W4, SBF::W5, - SBF::W6, SBF::W7, SBF::W8, SBF::W9, SBF::W10, SBF::W11}; + SBF::W0, SBF::W1, SBF::W2, SBF::W3, SBF::W4, SBF::W5, + SBF::W6, SBF::W7, SBF::W8, SBF::W9, SBF::W10, SBF::W11}; static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, @@ -146,12 +140,15 @@ static DecodeStatus readInstruction64(ArrayRef Bytes, uint64_t Address, Size = 8; if (IsLittleEndian) { - Hi = (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8); - Lo = (Bytes[4] << 0) | (Bytes[5] << 8) | (Bytes[6] << 16) | (Bytes[7] << 24); + Hi = + (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8); + Lo = + (Bytes[4] << 0) | (Bytes[5] << 8) | (Bytes[6] << 16) | (Bytes[7] << 24); } else { - Hi = (Bytes[0] << 24) | ((Bytes[1] & 0x0F) << 20) | ((Bytes[1] & 0xF0) << 12) | - (Bytes[2] << 8) | (Bytes[3] << 0); - Lo = (Bytes[4] << 24) | (Bytes[5] << 16) | (Bytes[6] << 8) | (Bytes[7] << 0); + Hi = (Bytes[0] << 24) | ((Bytes[1] & 0x0F) << 20) | + ((Bytes[1] & 0xF0) << 12) | (Bytes[2] << 8) | (Bytes[3] << 0); + Lo = + (Bytes[4] << 24) | (Bytes[5] << 16) | (Bytes[6] << 8) | (Bytes[7] << 0); } Insn = Make_64(Hi, Lo); @@ -167,7 +164,8 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, DecodeStatus Result; Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); - if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; uint8_t InstClass = getInstClass(Insn); uint8_t InstMode = getInstMode(Insn); @@ -178,10 +176,11 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, Result = decodeInstruction(DecoderTableSBFALU3264, Instr, Insn, Address, this, STI); else - Result = decodeInstruction(DecoderTableSBF64, Instr, Insn, Address, this, - STI); + Result = + decodeInstruction(DecoderTableSBF64, Instr, Insn, Address, this, STI); - if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; switch (Instr.getOpcode()) { case SBF::LD_imm64: @@ -192,25 +191,15 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } Size = 16; if (IsLittleEndian) - Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) | (Bytes[15] << 24); + Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) | + (Bytes[15] << 24); else - Hi = (Bytes[12] << 24) | (Bytes[13] << 16) | (Bytes[14] << 8) | (Bytes[15] << 0); - auto& Op = Instr.getOperand(1); + Hi = (Bytes[12] << 24) | (Bytes[13] << 16) | (Bytes[14] << 8) | + (Bytes[15] << 0); + auto &Op = Instr.getOperand(1); Op.setImm(Make_64(Hi, Op.getImm())); break; } - case SBF::LD_ABS_B: - case SBF::LD_ABS_H: - case SBF::LD_ABS_W: - case SBF::LD_IND_B: - case SBF::LD_IND_H: - case SBF::LD_IND_W: { - auto Op = Instr.getOperand(0); - Instr.clear(); - Instr.addOperand(MCOperand::createReg(SBF::R6)); - Instr.addOperand(Op); - break; - } } return Result; diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index c91a7fbe9bed50..f2e5888fdb05a4 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -896,48 +896,8 @@ let Constraints = "$dst = $src" in { def BE32 : BSWAP<32, "be32", SBF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; def BE64 : BSWAP<64, "be64", SBF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>; } - let Predicates = [SBFIsBigEndian] in { - def LE16 : BSWAP<16, "le16", SBF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>; - def LE32 : BSWAP<32, "le32", SBF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; - def LE64 : BSWAP<64, "le64", SBF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>; - } -} - -let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1, - hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in { -class LOAD_ABS - : TYPE_LD_ST { - bits<32> imm; - - let Inst{31-0} = imm; - let SBFClass = SBF_LD; } -class LOAD_IND - : TYPE_LD_ST { - bits<4> val; - - let Inst{55-52} = val; - let SBFClass = SBF_LD; -} -} - -def LD_ABS_B : LOAD_ABS; -def LD_ABS_H : LOAD_ABS; -def LD_ABS_W : LOAD_ABS; - -def LD_IND_B : LOAD_IND; -def LD_IND_H : LOAD_IND; -def LD_IND_W : LOAD_IND; - let isCodeGenOnly = 1 in { def MOV_32_64 : ALU_RR