From f6895abf0a3d6c05fd1b87c9de21d251ffa43887 Mon Sep 17 00:00:00 2001
From: chuanqizhang <legend.z@qq.com>
Date: Wed, 14 Apr 2021 12:25:10 +0800
Subject: [PATCH] add patch for new version of zcu102 kit

---
 fpga/README.md                                |  3 +-
 ...0001-patch-for-new-version-of-zcu102.patch | 37 +++++++++++++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 fpga/board/zcu102/patch/0001-patch-for-new-version-of-zcu102.patch

diff --git a/fpga/README.md b/fpga/README.md
index f154c25d..46037885 100644
--- a/fpga/README.md
+++ b/fpga/README.md
@@ -81,7 +81,8 @@ It may cost about one hour (it depends on the performance of your host) to boot
 
 ### Build a Vivado project
 
-* Install Vivado 2017.4, and source the setting of Vivado and SDK
+* note: if you are using new version of zcu102 (Please refer to the description of [this link](https://www.xilinx.com/support/answers/71961.html)), you need to apply the patch from [board/zcu102/patch/0001-patch-for-new-version-of-zcu102.patch](board/zcu102/patch/0001-patch-for-new-version-of-zcu102.patch)
+* Install Vivado 2019.1, and source the setting of Vivado and SDK
 * Run the following command to build a Vivado project
 ```
 make project PRJ=myproject BOARD=zcu102
diff --git a/fpga/board/zcu102/patch/0001-patch-for-new-version-of-zcu102.patch b/fpga/board/zcu102/patch/0001-patch-for-new-version-of-zcu102.patch
new file mode 100644
index 00000000..a595d9ed
--- /dev/null
+++ b/fpga/board/zcu102/patch/0001-patch-for-new-version-of-zcu102.patch
@@ -0,0 +1,37 @@
+From d3211ce94e3c3e477991f1dd1a38e1399fbf50fc Mon Sep 17 00:00:00 2001
+From: chuanqizhang <legend.z@qq.com>
+Date: Wed, 14 Apr 2021 12:08:12 +0800
+Subject: [PATCH] patch for new version of zcu102
+
+---
+ fpga/board/zcu102/bd/prm.tcl | 2 +-
+ fpga/board/zcu102/mk.tcl     | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/fpga/board/zcu102/bd/prm.tcl b/fpga/board/zcu102/bd/prm.tcl
+index b8c336a5..d562fe53 100644
+--- a/fpga/board/zcu102/bd/prm.tcl
++++ b/fpga/board/zcu102/bd/prm.tcl
+@@ -924,7 +924,7 @@ proc create_root_design { parentCell } {
+    CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
+    CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
+    CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+-   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
++   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \
+    CONFIG.PSU_MIO_0_DIRECTION {inout} \
+    CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
+    CONFIG.PSU_MIO_10_DIRECTION {inout} \
+diff --git a/fpga/board/zcu102/mk.tcl b/fpga/board/zcu102/mk.tcl
+index 5edfde8f..22af30d4 100644
+--- a/fpga/board/zcu102/mk.tcl
++++ b/fpga/board/zcu102/mk.tcl
+@@ -1,5 +1,5 @@
+ set device xczu9eg-ffvb1156-2-e
+-set board xilinx.com:zcu102:part0:3.1
++set board xilinx.com:zcu102:part0:3.3
+ 
+ set script_dir  [file dirname [info script]]
+ 
+-- 
+2.20.1
+