diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs
index 69faa94f851..7e2416ada27 100644
--- a/esp-hal/src/interrupt/riscv.rs
+++ b/esp-hal/src/interrupt/riscv.rs
@@ -770,9 +770,7 @@ mod classic {
     #[no_mangle]
     #[link_section = ".trap"]
     pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
-        unsafe {
-            riscv::interrupt::disable();
-        }
+        riscv::interrupt::disable();
         let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
         intr.cpu_int_thresh().write(|w| w.bits(stored_prio));
     }
@@ -903,9 +901,7 @@ mod plic {
     #[no_mangle]
     #[link_section = ".trap"]
     pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
-        unsafe {
-            riscv::interrupt::disable();
-        }
+        riscv::interrupt::disable();
         let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32;
         thresh_reg.write_volatile(stored_prio);
     }
diff --git a/examples/src/bin/direct_vectoring.rs b/examples/src/bin/direct_vectoring.rs
index e88db506173..ab09e5836f1 100644
--- a/examples/src/bin/direct_vectoring.rs
+++ b/examples/src/bin/direct_vectoring.rs
@@ -1,6 +1,5 @@
 #![no_main]
 #![no_std]
-#![feature(naked_functions)]
 
 //% CHIPS: esp32c2 esp32c3 esp32c6 esp32h2
 //% FEATURES: direct-vectoring
@@ -21,6 +20,15 @@ static SWINT: Mutex<RefCell<Option<SoftwareInterruptControl>>> = Mutex::new(RefC
 #[entry]
 fn main() -> ! {
     let peripherals = Peripherals::take();
+    cfg_if::cfg_if! {
+        if #[cfg(any(feature = "esp32c6", feature = "esp32h2"))] {
+            let cpu_intr = &peripherals.INTPRI;
+        } else {
+            let cpu_intr = &peripherals.SYSTEM;
+        }
+    }
+    let sw0_trigger_addr = cpu_intr.cpu_intr_from_cpu_0() as *const _ as u32;
+
     let system = peripherals.SYSTEM.split();
     let sw_int = system.software_interrupt_control;
 
@@ -42,17 +50,17 @@ fn main() -> ! {
         );
     }
 
-    esp_println::println!("MPC:{}", unsafe { fetch_performance_timer() });
-
     // interrupt is raised from assembly for max timer granularity.
     unsafe {
         asm!(
             "
-        li t0, 0x600C5090 #FROM_CPU_INTR0 address
-        li t1, 1    #Flip flag
-        csrrwi x0, 0x7e1, 1 #enable timer
-        sw t1, 0(t0) #trigger FROM_CPU_INTR0
-        "
+        li {bit}, 1                   # Flip flag (bit 0)
+        csrrwi x0, 0x7e1, 1           # enable timer
+        sw {bit}, 0({addr})           # trigger FROM_CPU_INTR0
+        ",
+        options(nostack),
+        addr = in(reg) sw0_trigger_addr,
+        bit = out(reg) _,
         )
     }
     esp_println::println!("Returned");
@@ -70,17 +78,16 @@ fn cpu_int_1_handler() {
             .unwrap()
             .reset(SoftwareInterrupt::SoftwareInterrupt0);
     });
-    esp_println::println!("Performance counter:{}", unsafe {
-        fetch_performance_timer()
-    });
-}
-#[naked]
-unsafe extern "C" fn fetch_performance_timer() -> i32 {
-    asm!(
-        "
-    csrr a0, 0x7e2
-    jr ra
-    ",
-        options(noreturn)
-    );
+
+    let mut perf_counter: u32 = 0;
+    unsafe {
+        asm!(
+            "
+            csrr {x}, 0x7e2
+            ",
+            options(nostack),
+            x = inout(reg) perf_counter,
+        )
+    };
+    esp_println::println!("Performance counter:{}", perf_counter);
 }