-
Notifications
You must be signed in to change notification settings - Fork 38
/
hal_ll_spi_master.c
1044 lines (862 loc) · 46.8 KB
/
hal_ll_spi_master.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/****************************************************************************
**
** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** This file is part of the mikroSDK package
**
** Commercial License Usage
**
** Licensees holding valid commercial NECTO compilers AI licenses may use this
** file in accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and The MikroElektronika Company.
** For licensing terms and conditions see
** https://www.mikroe.com/legal/software-license-agreement.
** For further information use the contact form at
** https://www.mikroe.com/contact.
**
**
** GNU Lesser General Public License Usage
**
** Alternatively, this file may be used for
** non-commercial projects under the terms of the GNU Lesser
** General Public License version 3 as published by the Free Software
** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
**
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**
****************************************************************************/
/*!
* @file hal_ll_spi_master.c
* @brief SPI Master HAL LOW LEVEL layer implementation.
*/
#include "hal_ll_spi_master.h"
#include "hal_ll_spi_master_pin_map.h"
#include "hal_ll_rcc.h"
/*!< @brief Local handle list */
static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false};
// Defines constant value arrays for the baud rate pre-scaler and scaler divider values
static const uint32_t baudrate_prescaler[] = { 2, 3, 5, 7 };
static const uint32_t baudrate_scaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768 };
static const uint32_t delay_prescaler[] = { 1, 3, 5, 7 };
static const uint32_t delay_scaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 };
// ------------------------------------------------------------- PRIVATE MACROS
/*!< @brief Helper macro for getting hal_ll_module_state address */
#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle)
/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle
/*!< @brief Helper macro for getting module specific control register structure */
#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle)
/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\
(((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base
/*!< Enable constants. */
#define HAL_LL_SPI0_MASTER_ENABLE (12)
#define HAL_LL_SPI1_MASTER_ENABLE (13)
#define HAL_LL_SPI2_MASTER_ENABLE (12)
#define MIN_DIFF (0xFFFFFFFFUL)
/*!< @brief Default SPI Master bit-rate if no speed is set */
#define HAL_LL_SPI_MASTER_SPEED_100K (100000)
/*!< @brief Macros used for module pin checking */
#define HAL_LL_SPI_SCK_PIN (0)
#define HAL_LL_SPI_MISO_PIN (1)
#define HAL_LL_SPI_MOSI_PIN (2)
#define HAL_LL_SPI_MODULE_PIN_COUNT (3)
#define SPI_MASTER_CFG_CMD_CTCNT_CLEAR (0x04000000)
#define SPI_MASTER_CTAR_BR_MASK (0xF)
#define SPI_MASTER_CTAR_BR_3BITS_MASK (0x7)
#define SPI_MASTER_CTAR_BR_SHIFT (0)
#define SPI_MASTER_CTAR_PBR_MASK (0x30000UL)
#define SPI_MASTER_CTAR_PBR_SHIFT (16)
#define SPI_MASTER_CTAR_DBR_MASK (0x80000000UL)
#define SPI_MASTER_CTAR_DBR_SHIFT (31)
#define SPI_MASTER_CTAR_DEFAULT (0x78000000UL)
#define SPI_MASTER_CTAR_PCSSCK_SHIFT (22U)
#define SPI_MASTER_CTAR_PCSSCK_MASK (0xC00000UL)
#define SPI_MASTER_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_MASTER_CTAR_PCSSCK_SHIFT)) & SPI_MASTER_CTAR_PCSSCK_MASK)
#define SPI_MASTER_CTAR_CSSCK_SHIFT (12U)
#define SPI_MASTER_CTAR_CSSCK_MASK (0xF000UL)
#define SPI_MASTER_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_MASTER_CTAR_CSSCK_SHIFT)) & SPI_MASTER_CTAR_CSSCK_MASK)
#define SPI_MASTER_CTAR_PASC_SHIFT (20U)
#define SPI_MASTER_CTAR_PASC_MASK (0x300000UL)
#define SPI_MASTER_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_MASTER_CTAR_PASC_SHIFT)) & SPI_MASTER_CTAR_PASC_MASK)
#define SPI_MASTER_CTAR_ASC_SHIFT (8U)
#define SPI_MASTER_CTAR_ASC_MASK (0xF00UL)
#define SPI_MASTER_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_MASTER_CTAR_ASC_SHIFT)) & SPI_MASTER_CTAR_ASC_MASK)
#define SPI_MASTER_CTAR_PDT_SHIFT (18U)
#define SPI_MASTER_CTAR_PDT_MASK (0xC0000UL)
#define SPI_MASTER_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MASTER_CTAR_PDT_SHIFT)) & SPI_MASTER_CTAR_PDT_MASK)
#define SPI_MASTER_CTAR_DT_SHIFT (4U)
#define SPI_MASTER_CTAR_DT_MASK (0xF0UL)
#define SPI_MASTER_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MASTER_CTAR_DT_SHIFT)) & SPI_MASTER_CTAR_DT_MASK)
#define SPI_MASTER_MCR_CLR_RXF_MASK (0x400UL)
#define SPI_MASTER_MCR_CLR_TXF_MASK (0x800UL)
#define SPI_MASTER_MCR_HALT_SHIFT (0)
#define SPI_MASTER_MCR_CLR_RXF_SHIFT (10)
#define SPI_MASTER_MCR_CLR_TXF_SHIFT (11)
#define SPI_MASTER_MCR_DIS_RXF_SHIFT (12)
#define SPI_MASTER_MCR_DIS_TXF_SHIFT (13)
#define SPI_MASTER_MCR_MDIS_SHIFT (14)
#define SPI_MASTER_MCR_MSTR_SHIFT (31)
#define SPI_MASTER_SR_RFDF_MASK (0x20000UL)
#define SPI_MASTER_SR_RFOF_MASK (0x80000UL)
#define SPI_MASTER_SR_TFFF_MASK (0x2000000UL)
#define SPI_MASTER_SR_TFUF_MASK (0x8000000UL)
#define SPI_MASTER_SR_EOQF_MASK (0x10000000UL)
#define SPI_MASTER_SR_TCF_MASK (0x80000000UL)
#define SPI_MASTER_SR_TCF_SHIFT (31)
#define SPI_MASTER_SR_RFDF_SHIFT (17)
#define SPI_MASTER_CTAR0_LSBFE_SHIFT (24)
#define SPI_MASTER_CTAR0_FMSZ_4BIT_SHIFT (30)
#define SPI_MASTER_CTAR0_FMSZ_3BITS_MASK (0x38000000UL)
#define SPI_MASTER_RSER_TCF_RE_BIT (31)
#define SPI_MASTER_RSER_TCF_RE_MASK (1UL << SPI_MASTER_RSER_TCF_RE_BIT)
#define SPI_MASTER_RSER_EOQF_RE_BIT (28)
#define SPI_MASTER_RSER_EOQF_RE_MASK (1UL << SPI_MASTER_RSER_EOQF_RE_BIT)
#define SPI_MASTER_RSER_TFUF_RE_BIT (27)
#define SPI_MASTER_RSER_TFUF_RE_MASK (1UL << SPI_MASTER_RSER_TFUF_RE_BIT)
#define SPI_MASTER_RSER_TFFF_RE_BIT (25)
#define SPI_MASTER_RSER_TFFF_RE_MASK (1UL << SPI_MASTER_RSER_TFFF_RE_BIT)
#define SPI_MASTER_RSER_TFFF_DIRS_BIT (24)
#define SPI_MASTER_RSER_TFFF_DIRS_MASK (1UL << SPI_MASTER_RSER_TFFF_DIRS_BIT)
#define SPI_MASTER_RSER_RFOF_RE_BIT (19)
#define SPI_MASTER_RSER_RFOF_RE_MASK (1UL << SPI_MASTER_RSER_RFOF_RE_BIT)
#define SPI_MASTER_RSER_RFDF_RE_BIT (17)
#define SPI_MASTER_RSER_RFDF_RE_MASK (1UL << SPI_MASTER_RSER_RFDF_RE_BIT)
#define SPI_MASTER_RSER_RFDF_DIRS_BIT (16)
#define SPI_MASTER_RSER_RFDF_DIRS_MASK (1UL << SPI_MASTER_RSER_RFDF_DIRS_BIT)
#define SPI_MASTER_RSER_FULL_MASK (SPI_MASTER_RSER_TCF_RE_MASK | \
SPI_MASTER_RSER_EOQF_RE_MASK | \
SPI_MASTER_RSER_TFUF_RE_MASK | \
SPI_MASTER_RSER_TFFF_RE_MASK | \
SPI_MASTER_RSER_TFFF_DIRS_MASK | \
SPI_MASTER_RSER_RFOF_RE_MASK | \
SPI_MASTER_RSER_RFDF_RE_MASK | \
SPI_MASTER_RSER_RFDF_DIRS_MASK)
#define SPI_MASTER_TCR_TCNT_MASK (0x0000FFFFUL)
#define HAL_LL_SPI_MASTER_CLK_POLARITY (26)
#define HAL_LL_SPI_MASTER_CLK_PHASE (25)
// -------------------------------------------------------------- PRIVATE TYPES
typedef struct {
uint32_t mcr; /**< Module Configuration Register, offset: 0x0 */
uint32_t __unused1;
uint32_t tcr; /**< Transfer Count Register, offset: 0x8 */
uint32_t ctar0; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC */
uint32_t ctar1; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0x10 */
uint32_t __unused2[ 6 ];
uint32_t sr; /**< Status Register, offset: 0x2C */
uint32_t rser; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
uint32_t pushr; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
uint32_t popr; /**< POP RX FIFO Register, offset: 0x38 */
/* Commented out for memory optimization;
* Uncomment if needed.
*/
// uint32_t txfr0; /**< Transmit FIFO Registers, offset: 0x3C */
// uint32_t txfr1; /**< Transmit FIFO Registers, offset: 0x40 */
// uint32_t txfr2; /**< Transmit FIFO Registers, offset: 0x44 */
// uint32_t txfr3; /**< Transmit FIFO Registers, offset: 0x48 */
// uint32_t __unused3[12];
// uint32_t rxfr0; /**< Receive FIFO Registers, offset: 0x7C */
// uint32_t rxfr1; /**< Receive FIFO Registers, offset: 0x80 */
// uint32_t rxfr2; /**< Receive FIFO Registers, offset: 0x84 */
// uint32_t rxfr3; /**< Receive FIFO Registers, offset: 0x88 */
} hal_ll_spi_master_base_handle_t;
/*!< @brief SPI Master hardware specific structure */
typedef struct {
hal_ll_base_addr_t base;
uint8_t module_index;
hal_ll_spi_master_pins_t pins;
uint8_t dummy_data;
uint32_t speed;
uint32_t hw_actual_speed;
hal_ll_spi_master_mode_t mode;
} hal_ll_spi_master_hw_specifics_map_t;
/*!< @brief SPI hw specific module values */
typedef struct
{
uint16_t pin_sck;
uint16_t pin_miso;
uint16_t pin_mosi;
} hal_ll_spi_pin_id;
/*!< @brief SPI Master hw specific error values */
typedef enum
{
HAL_LL_SPI_MASTER_SUCCESS = 0,
HAL_LL_SPI_MASTER_WRONG_PINS,
HAL_LL_SPI_MASTER_MODULE_ERROR,
HAL_LL_SPI_MASTER_ERROR = (-1)
} hal_ll_spi_master_err_t;
/*! @brief SPI delay type selection. */
typedef enum
{
HAL_LL_SPI_PCSTOSCK = 0, /*!< Pcs-to-SCK delay. */
HAL_LL_SPI_LASTSCKTOPCS, /*!< The last SCK edge to Pcs delay. */
HAL_LL_SPI_BETWEENTRANSFER /*!< Delay between transfers. */
} hal_ll_spi_delay_type_t;
// ------------------------------------------------------------------ VARIABLES
/*!< @brief SPI Master hardware specific info */
static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[SPI_MODULE_COUNT + 1] = {
#ifdef SPI_MODULE_0
{HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT},
#endif
#ifdef SPI_MODULE_1
{HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT},
#endif
#ifdef SPI_MODULE_2
{HAL_LL_SPI2_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT},
#endif
{HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0, 0}
};
/*!< @brief Global handle variables used in functions */
static volatile hal_ll_spi_master_handle_register_t *low_level_handle;
static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local;
// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
/**
* @brief Check if pins are adequate.
*
* Checks SCK, MISO and MOSI pins the user has passed with pre-defined
* pins in SCK, MISO and MOSI maps. Take into consideration that module
* index numbers have to be the same for both pins.
*
* @param[in] sck - SCK pre-defined pin name.
* @param[in] miso - MISO pre-defined pin name.
* @param[in] mosi - MOSI pre-defined pin name.
* @param[in] *index_list - Index list address
* @return hal_ll_pin_name_t Module index based on pins.
*
* Returns pre-defined module index from pin maps, if pins
* are adequate.
*/
static hal_ll_pin_name_t _hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map);
/**
* @brief Sets SPI Master pin alternate function state.
*
* Sets adequate value for alternate function settings.
* This function must be called if SPI is to work.
* Based on value of hal_ll_state, alternate functions can be
* set or cleared.
*
* @param[in] *map - Object specific context handler.
* @param[in] hal_ll_state - Init/De-init
*/
static void _hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state);
/**
* @brief Maps new-found module specific values.
*
* Maps pin names and alternate function values for
* SPI SCK, MISO and MOSI pins.
*
* @param[in] module_index SPI HW module index -- 0,1,2...
* @param[in] *index_list Array with SCK, MISO and MOSI map index values
*
* @return None
*/
static void _hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list);
/**
* @brief Get local hardware specific map.
*
* Checks handle value and returns address of adequate
* hal_ll_spi_master_hw_specifics_map array index.
*
* @param[in] handle - Object specific context handler.
* @return hal_ll_spi_master_hw_specifics_map_t Map address.
*
* Returns pre-defined map index address based on handle value,
* if handle is adequate.
*/
static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics(handle_t handle);
/**
* @brief Set CTAR register.
*
* Calculate Baud Rate Prescaler, Baud Rate Scaler, Double Baud Rate
*
* @param[in] *map - Object specific context handler.
*/
static void _hal_ll_spi_master_get_speed(hal_ll_spi_master_hw_specifics_map_t *map);
/**
* @brief Perform a write on the SPI Master bus.
*
* Initializes SPI Master module on hardware level, if not initialized beforehand
* and continues to perform a write operation on the bus.
*
* @param[in] map - Object specific context handler.
* @param[in] *write_data_buffer - Pointer to data buffer.
* @param[in] write_data_length - Number of data to be written.
* @return hal_ll_err_t Module specific error values.
*
* Returns one of pre-defined error values.
* Take into consideration that this is hardware specific.
*/
static void _hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *write_data_buffer, size_t write_data_length);
/**
* @brief Perform a read on the SPI Master bus.
*
* Initializes SPI Master module on hardware level, if not initialized beforehand
* and continues to perform a read operation on the bus.
*
* @param[in] *map - Object specific context handler.
* @param[in] *read_data_buffer - Pointer to data buffer.
* @param[in] read_data_length - Number of data to be read.
* @param[in] dummy_data - Data required for read procedure.
* @return hal_ll_err_t Module specific error values.
*/
static void _hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data);
/**
* @brief Enable clock for SPI module on hardware level.
*
* Initializes SPI module clock on hardware level, based on beforehand
* set configuration and module handler.
*
* @param[in] *map - Object specific context handler.
* @param[in] hal_ll_state - True(enable clock)/False(disable clock).
* @return None
*/
static void _hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state);
/**
* @brief Initialize hardware SPI module.
*
* @param[in] *map - Object specific context handler.
* @return None
*
* Returns one of pre-defined error values.
* Take into consideration that this is hardware specific.
*/
static void _hal_ll_spi_master_hw_init(hal_ll_spi_master_hw_specifics_map_t *map);
/**
* @brief Full SPI Master module initialization procedure.
*
* Initializes SPI Master module on hardware level, based on beforehand
* set configuration and module handler. Sets adequate pin alternate functions.
* Initializes module clock.
*
* @param[in] *map - Object specific context handler.
* @return hal_ll_err_t Module specific values.
*
* Returns one of pre-defined values.
* Take into consideration that this is hardware specific.
*/
static void _hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_t *map);
/**
* @brief Sets the delay prescaler and scaler based on the desired
* delay input in nanoseconds.
*
* @param[in] *hal_ll_hw_reg - Module specific register handler.
* @param[in] best_delay_prescaler - Calculated delay prescaler value.
* @param[in] best_delay_scaler - Calculated delay scaler value.
* @param[in] delay - Delay input in nanoseconds.
*
* @return None.
*/
static void set_delay_scaler(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint32_t best_delay_prescaler,
uint32_t best_delay_scaler, hal_ll_spi_delay_type_t delay);
/**
* @brief Calculates the delay prescaler and scaler based on the desired
* delay input in nanoseconds.
*
* This function calculates the values for the following:
* PCS to SCK delay pre-scaler (PCSSCK) and scaler (CSSCK), or
* After SCK delay pre-scaler (PASC) and scaler (ASC), or
* Delay after transfer pre-scaler (PDT) and scaler (DT).
*
* @param[in] *hal_ll_hw_reg - Module specific register handler.
* @param[in] speed - Desired module baudrate.
* @param[in] delay - Delay input in nanoseconds.
*
* @return None.
*/
static void calculate_delay_scaler(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint32_t speed, hal_ll_spi_delay_type_t delay);
// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id) {
hal_ll_spi_pin_id index_list[SPI_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC,HAL_LL_PIN_NC};
uint16_t pin_check_result;
// Check user-defined pins.
if ((pin_check_result = _hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map)) == HAL_LL_PIN_NC) {
return HAL_LL_SPI_MASTER_WRONG_PINS;
};
// If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure
// will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false.
if ((hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.sck.pin_name != sck) ||
(hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.miso.pin_name != miso) ||
(hal_ll_spi_master_hw_specifics_map[pin_check_result].pins.mosi.pin_name != mosi) ) {
_hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], false);
_hal_ll_spi_master_map_pins(pin_check_result, &index_list);
_hal_ll_spi_master_alternate_functions_set_state(&hal_ll_spi_master_hw_specifics_map[pin_check_result], true);
handle_map[pin_check_result].init_ll_state = false;
}
// Return id of the SPI module that is going to be used.
*hal_module_id = pin_check_result;
// Insert current module into hal_ll_module_state map.
hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base;
// Return the same info about module one level up ( into the HAL level ).
handle_map[pin_check_result].hal_ll_spi_master_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle;
return HAL_LL_SPI_MASTER_SUCCESS;
}
hal_ll_err_t hal_ll_module_configure_spi(handle_t *handle) {
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
hal_ll_spi_master_handle_register_t *hal_handle = (hal_ll_spi_master_handle_register_t *)*handle;
uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index;
_hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local);
hal_ll_module_state[pin_check_result].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[pin_check_result].base;
hal_ll_module_state[pin_check_result].init_ll_state = true;
hal_handle->init_ll_state = true;
return HAL_LL_SPI_MASTER_SUCCESS;
}
void hal_ll_spi_master_set_default_write_data(handle_t *handle, uint8_t dummy_data) {
// Get appropriate hw specifics map.
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
if(hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) {
hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data;
}
}
hal_ll_err_t hal_ll_spi_master_write(handle_t *handle, uint8_t *write_data_buffer, size_t length_data) {
// Get low level HAL handle.
low_level_handle = hal_ll_spi_master_get_handle;
// Get appropriate hw specifics map.
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
// Check for module error.
if(low_level_handle->hal_ll_spi_master_handle == NULL) {
return HAL_LL_SPI_MASTER_MODULE_ERROR;
}
_hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local, write_data_buffer, length_data);
return HAL_LL_SPI_MASTER_SUCCESS;
}
hal_ll_err_t hal_ll_spi_master_read(handle_t *handle, uint8_t *read_data_buffer, size_t length_data) {
// Get low level HAL handle.
low_level_handle = hal_ll_spi_master_get_handle;
// Get appropriate hw specifics map.
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
if(low_level_handle->hal_ll_spi_master_handle == NULL) {
return HAL_LL_SPI_MASTER_MODULE_ERROR;
}
_hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data);
return HAL_LL_SPI_MASTER_SUCCESS;
}
hal_ll_err_t hal_ll_spi_master_write_then_read(handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data) {
// Get low level HAL handle.
low_level_handle = hal_ll_spi_master_get_handle;
// Get appropriate hw specifics map.
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
if(low_level_handle->hal_ll_spi_master_handle == NULL) {
return HAL_LL_SPI_MASTER_MODULE_ERROR;
}
_hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_local, write_data_buffer, length_write_data);
_hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_local, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data);
return HAL_LL_SPI_MASTER_SUCCESS;
}
uint32_t hal_ll_spi_master_set_speed(handle_t *handle, uint32_t speed) {
// Get low level HAL handle.
low_level_handle = hal_ll_spi_master_get_handle;
// Get appropriate hw specifics map.
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
low_level_handle->init_ll_state = false;
// Insert user-defined baud rate into local map.
hal_ll_spi_master_hw_specifics_map_local->speed = speed;
// Init once again, but with updated SPI Master baud rate value.
_hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local);
low_level_handle->init_ll_state = true;
// Return value of the SPI Master baud rate value.
return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed;
}
hal_ll_err_t hal_ll_spi_master_set_mode(handle_t *handle, hal_ll_spi_master_mode_t mode) {
// Get low level HAL handle.
low_level_handle = hal_ll_spi_master_get_handle;
// Get appropriate hw specifics map.
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
if(low_level_handle->hal_ll_spi_master_handle == NULL) {
return HAL_LL_SPI_MASTER_MODULE_ERROR;
}
low_level_handle->init_ll_state = false;
// Insert user-defined mode into local map.
hal_ll_spi_master_hw_specifics_map_local->mode = mode;
// Init once again, but with updated SPI Master mode value.
_hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local);
low_level_handle->init_ll_state = true;
return HAL_LL_SPI_MASTER_SUCCESS;
}
void hal_ll_spi_master_close(handle_t* handle) {
uint32_t dummy;
low_level_handle = hal_ll_spi_master_get_handle;
hal_ll_spi_master_hw_specifics_map_local = _hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
if(low_level_handle->hal_ll_spi_master_handle != NULL) {
low_level_handle->hal_ll_spi_master_handle = NULL;
low_level_handle->hal_drv_spi_master_handle = NULL;
low_level_handle->init_ll_state = false;
hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT;
hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K;
hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0;
hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0;
_hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, true);
_hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_local, false);
_hal_ll_spi_master_set_clock(hal_ll_spi_master_hw_specifics_map_local, false);
hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC;
hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC;
hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC;
hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0;
hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0;
hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0;
}
}
// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
static hal_ll_pin_name_t _hal_ll_spi_master_check_pins(hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map) {
static const uint16_t sck_map_size = (sizeof(_spi_sck_map)) / (sizeof(hal_ll_spi_master_pin_map_t));
static const uint16_t miso_map_size = (sizeof(_spi_miso_map)) / (sizeof(hal_ll_spi_master_pin_map_t));
static const uint16_t mosi_map_size = (sizeof(_spi_mosi_map)) / (sizeof(hal_ll_spi_master_pin_map_t));
uint8_t hal_ll_module_id = 0;
uint8_t index_counter = 0;
uint16_t miso_index;
uint16_t mosi_index;
uint16_t sck_index;
if ( (HAL_LL_PIN_NC == sck_pin) || (HAL_LL_PIN_NC == miso_pin) || (HAL_LL_PIN_NC == mosi_pin) ) {
return HAL_LL_PIN_NC;
}
// Check pins from the specific pin maps with the user defined pins.
for (sck_index = 0; sck_index < sck_map_size; sck_index++) {
if (_spi_sck_map[sck_index].pin == sck_pin) {
for (miso_index = 0; miso_index < miso_map_size; miso_index++) {
if (_spi_miso_map[miso_index].pin == miso_pin) {
if (_spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index) {
for (mosi_index = 0; mosi_index < mosi_map_size; mosi_index++) {
if (_spi_mosi_map[mosi_index ].pin == mosi_pin) {
if (_spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index) {
// Get module number
hal_ll_module_id = _spi_sck_map[ sck_index ].module_index;
// Map pin names
index_list[hal_ll_module_id].pin_sck = sck_index;
index_list[hal_ll_module_id].pin_miso = miso_index;
index_list[hal_ll_module_id].pin_mosi = mosi_index;
// Check if module is taken
if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) {
return hal_ll_module_id;
} else if ( SPI_MODULE_COUNT == ++index_counter ) {
return --index_counter;
}
}
}
}
}
}
}
}
}
if ( index_counter ) {
return hal_ll_module_id;
} else {
return HAL_LL_PIN_NC;
}
}
static void _hal_ll_spi_master_alternate_functions_set_state(hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state) {
module_struct module;
uint32_t spi_config;
if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) {
module.pins[0] = VALUE(map->pins.sck.pin_name, map->pins.sck.pin_af);
module.pins[1] = VALUE(map->pins.miso.pin_name, map->pins.miso.pin_af);
module.pins[2] = VALUE(map->pins.mosi.pin_name, map->pins.mosi.pin_af);
module.pins[3] = GPIO_MODULE_STRUCT_END;
spi_config = GPIO_CFG_MODE_ALT_FUNCTION;
module.configs[0] = spi_config;
module.configs[1] = spi_config;
module.configs[2] = spi_config;
module.configs[3] = GPIO_MODULE_STRUCT_END;
hal_ll_gpio_module_struct_init(&module, hal_ll_state);
}
}
static void _hal_ll_spi_master_map_pins(uint8_t module_index, hal_ll_spi_pin_id *index_list) {
// If every single pin is OK, insert them into this new map, and use this map in all low level functions.
hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_name = _spi_sck_map[index_list[module_index].pin_sck].pin;
hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_name = _spi_miso_map[index_list[module_index].pin_miso].pin;
hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_name = _spi_mosi_map[index_list[module_index].pin_mosi].pin;
// SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s.
hal_ll_spi_master_hw_specifics_map[module_index].pins.sck.pin_af = _spi_sck_map[index_list[module_index].pin_sck].af;
hal_ll_spi_master_hw_specifics_map[module_index].pins.miso.pin_af = _spi_miso_map[index_list[module_index].pin_miso].af;
hal_ll_spi_master_hw_specifics_map[module_index].pins.mosi.pin_af = _spi_mosi_map[index_list[module_index].pin_mosi].af;
}
static hal_ll_spi_master_hw_specifics_map_t *_hal_ll_get_specifics(handle_t handle) {
uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t));
static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof( hal_ll_spi_master_handle_register_t));
while (hal_ll_module_count--) {
if (hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[hal_ll_module_count].base) {
return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_count];
}
}
return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error];
}
static void _hal_ll_spi_master_get_speed(hal_ll_spi_master_hw_specifics_map_t *map){
SIM_ClocksTypeDef sim_clocks;
uint32_t prescaler, best_prescaler;
uint32_t scaler, best_scaler;
uint32_t dbr, best_dbr;
uint32_t real_baudrate, best_baudrate;
uint32_t diff, min_diff;
uint32_t baudrate_prescaler_size, baudrate_scaler_size;
uint32_t baudrate = map->speed;
hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base;
// Get clocks.
SIM_GetClocksFrequency(&sim_clocks);
// Find combination of prescaler and scaler resulting in baudrate closest to the requested value.
min_diff = MIN_DIFF;
best_prescaler = 0;
best_scaler = 0;
best_dbr = 1;
best_baudrate = 0;
baudrate_prescaler_size = sizeof(baudrate_prescaler)/sizeof(uint32_t);
baudrate_scaler_size = sizeof(baudrate_scaler)/sizeof(uint32_t);
// In all for loops, if min_diff = 0, the exit for loop.
for (prescaler = 0; min_diff && (prescaler < baudrate_prescaler_size); prescaler++)
{
for (scaler = 0; min_diff && (scaler < baudrate_scaler_size); scaler++)
{
for (dbr = 1; min_diff && (dbr < 3); dbr++)
{
#ifdef HAL_LL_RCC_CLOCK_OUTPUT
real_baudrate = (sim_clocks.fast_peripheral_frequency * dbr) /
(baudrate_prescaler[prescaler] * (baudrate_scaler[scaler]));
#else
real_baudrate = (sim_clocks.busclock_frequency * dbr) /
(baudrate_prescaler[prescaler] * (baudrate_scaler[scaler]));
#endif
if (baudrate >= real_baudrate)
{
diff = baudrate-real_baudrate;
if (min_diff > diff)
{
min_diff = diff;
best_prescaler = prescaler;
best_scaler = scaler;
best_baudrate = real_baudrate;
best_dbr = dbr;
}
}
}
}
}
// Write the best dbr, prescaler, and baud rate scaler to the CTAR.
hal_ll_hw_reg->ctar0 &= ~((uint32_t)(SPI_MASTER_CTAR_DBR_MASK | SPI_MASTER_CTAR_PBR_MASK | SPI_MASTER_CTAR_BR_MASK));
hal_ll_hw_reg->ctar0 |= (best_dbr - 1) << SPI_MASTER_CTAR_DBR_SHIFT;
hal_ll_hw_reg->ctar0 |= (best_prescaler << SPI_MASTER_CTAR_PBR_SHIFT) & SPI_MASTER_CTAR_PBR_MASK;
hal_ll_hw_reg->ctar0 |= (best_scaler << SPI_MASTER_CTAR_BR_SHIFT) & SPI_MASTER_CTAR_BR_MASK;
map->hw_actual_speed = best_baudrate;
}
static void _hal_ll_spi_master_write_bare_metal(hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *write_data_buffer, size_t write_data_length){
hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base;
size_t loop_counter = 0;
/* Clear all interrupts. */
hal_ll_hw_reg->rser &= ~(SPI_MASTER_RSER_FULL_MASK);
for (loop_counter = 0; loop_counter < write_data_length; loop_counter++ ){
/* Flush TXFIFO. */
hal_ll_hw_reg->mcr |= ( 1UL << SPI_MASTER_MCR_DIS_TXF_SHIFT );
hal_ll_hw_reg->sr = 1UL << SPI_MASTER_SR_TCF_SHIFT;
hal_ll_hw_reg->pushr = SPI_MASTER_CFG_CMD_CTCNT_CLEAR | ((uint32_t) write_data_buffer[loop_counter]);
while((hal_ll_hw_reg->sr & SPI_MASTER_SR_TCF_MASK) == 0)
{
}
hal_ll_hw_reg->mcr &= ~( 1UL << SPI_MASTER_MCR_DIS_TXF_SHIFT );
}
}
static void _hal_ll_spi_master_read_bare_metal(hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data){
hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base;
size_t i = 0;
/* Clear all interrupts. */
hal_ll_hw_reg->rser &= ~(SPI_MASTER_RSER_FULL_MASK);
for( i=0; i < read_data_length; i++ ) {
set_reg_bit(&hal_ll_hw_reg->mcr, SPI_MASTER_MCR_HALT_SHIFT);
hal_ll_hw_reg->mcr = ( hal_ll_hw_reg->mcr & ( ~( SPI_MASTER_MCR_CLR_RXF_MASK | SPI_MASTER_MCR_CLR_TXF_MASK ) ) ) |
( 1UL << SPI_MASTER_MCR_CLR_RXF_SHIFT ) | ( 1UL << SPI_MASTER_MCR_CLR_TXF_SHIFT );
/* Flush RXFIFO. */
hal_ll_hw_reg->mcr |= ( 1UL << SPI_MASTER_MCR_DIS_RXF_SHIFT );
clear_reg_bit( &hal_ll_hw_reg->mcr,SPI_MASTER_MCR_HALT_SHIFT );
hal_ll_hw_reg->sr = SPI_MASTER_SR_TCF_MASK | SPI_MASTER_SR_EOQF_MASK | SPI_MASTER_SR_TFUF_MASK |
SPI_MASTER_SR_TFFF_MASK | SPI_MASTER_SR_RFOF_MASK | SPI_MASTER_SR_RFDF_MASK;
/* Set to 0 always, because one byte is transferred. */
hal_ll_hw_reg->tcr &= SPI_MASTER_TCR_TCNT_MASK;
hal_ll_hw_reg->mcr &= ~( 1UL << SPI_MASTER_MCR_DIS_RXF_SHIFT );
clear_reg_bit( &hal_ll_hw_reg->mcr,SPI_MASTER_MCR_HALT_SHIFT );
_hal_ll_spi_master_write_bare_metal( map, &dummy_data, sizeof( dummy_data ) );
// Wait for RFDF to be set.
while((hal_ll_hw_reg->sr & SPI_MASTER_SR_RFDF_MASK) == 0);
read_data_buffer[ i ] = (uint8_t)hal_ll_hw_reg->popr;
hal_ll_hw_reg->sr = 1UL << SPI_MASTER_SR_RFDF_SHIFT;
}
}
static void _hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) {
switch ( map->module_index ) {
#if defined( SPI_MODULE_0 )
case ( hal_ll_spi_master_module_num( SPI_MODULE_0 ) ):
if( hal_ll_state ) {
set_reg_bit( _SIM_SCGC6, HAL_LL_SPI0_MASTER_ENABLE );
} else {
clear_reg_bit( _SIM_SCGC6, HAL_LL_SPI0_MASTER_ENABLE );
}
break;
#endif
#if defined( SPI_MODULE_1 )
case ( hal_ll_spi_master_module_num( SPI_MODULE_1 ) ):
if( hal_ll_state ) {
set_reg_bit( _SIM_SCGC6, HAL_LL_SPI1_MASTER_ENABLE );
} else {
clear_reg_bit( _SIM_SCGC6, HAL_LL_SPI1_MASTER_ENABLE );
}
break;
#endif
#if defined( SPI_MODULE_2 )
case ( hal_ll_spi_master_module_num( SPI_MODULE_2 ) ):
if( hal_ll_state ) {
set_reg_bit( _SIM_SCGC3, HAL_LL_SPI2_MASTER_ENABLE );
} else {
clear_reg_bit( _SIM_SCGC3, HAL_LL_SPI2_MASTER_ENABLE );
}
break;
#endif
}
}
static void set_delay_scaler(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint32_t best_delay_prescaler,
uint32_t best_delay_scaler, hal_ll_spi_delay_type_t delay) {
switch (delay)
{
case HAL_LL_SPI_PCSTOSCK:
hal_ll_hw_reg->ctar0 = (hal_ll_hw_reg->ctar0 & (~SPI_MASTER_CTAR_PCSSCK_MASK) & (~SPI_MASTER_CTAR_CSSCK_MASK)) |
SPI_MASTER_CTAR_PCSSCK(best_delay_prescaler) | SPI_MASTER_CTAR_CSSCK(best_delay_scaler);
break;
case HAL_LL_SPI_LASTSCKTOPCS:
hal_ll_hw_reg->ctar0 = (hal_ll_hw_reg->ctar0 & (~SPI_MASTER_CTAR_PASC_MASK) & (~SPI_MASTER_CTAR_ASC_MASK)) |
SPI_MASTER_CTAR_PASC(best_delay_prescaler) | SPI_MASTER_CTAR_ASC(best_delay_scaler);
break;
case HAL_LL_SPI_BETWEENTRANSFER:
hal_ll_hw_reg->ctar0 = (hal_ll_hw_reg->ctar0 & (~SPI_MASTER_CTAR_PDT_MASK) & (~SPI_MASTER_CTAR_DT_MASK)) |
SPI_MASTER_CTAR_PDT(best_delay_prescaler) | SPI_MASTER_CTAR_DT(best_delay_scaler);
break;
default:
/* All cases have been listed above, the default clause should not be reached. */
break;
}
}
static void calculate_delay_scaler(hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint32_t speed, hal_ll_spi_delay_type_t delay) {
uint32_t prescaler, best_prescaler;
uint32_t scaler, best_scaler;
uint32_t real_delay, best_delay;
uint32_t diff, min_diff;
uint32_t initial_delay_nano_sec;
uint32_t clock_source_value = 0;
uint32_t delay_prescaler_size, delay_scaler_size;
SIM_ClocksTypeDef sim_clocks;
delay_prescaler_size = sizeof(delay_prescaler)/sizeof(uint32_t);
delay_scaler_size = sizeof(delay_scaler)/sizeof(uint32_t);
// Get clocks.
SIM_GetClocksFrequency(&sim_clocks);
#ifdef HAL_LL_RCC_CLOCK_OUTPUT
clock_source_value = sim_clocks.fast_peripheral_frequency;
#else
clock_source_value = sim_clocks.busclock_frequency;
#endif
/**
* Find combination of prescaler and scaler resulting in the delay closest to the
* requested value.
*/
min_diff = 0xFFFFFFFFUL;
/* Initialize prescaler and scaler to their max values to generate the max delay. */
best_prescaler = 0x3;
best_scaler = 0xF;
best_delay = (((1000000000UL * 4U) / clock_source_value ) * delay_prescaler[best_prescaler] * delay_scaler[best_scaler]) / 4U;
/* First calculate the initial, default delay. */
initial_delay_nano_sec = 1000000000UL / clock_source_value * 2U;
/**
* If the initial, default delay is already greater than the desired delay, then
* set the delays to their initial value (0) and return the delay. In other words,
* there is no way to decrease the delay value further.
*/
if (initial_delay_nano_sec >= (1000000000UL / speed))
set_delay_scaler(hal_ll_hw_reg, 0, 0, delay);
/* In all for loops, if min_diff = 0, then exit for loop */
for (prescaler = 0; prescaler < delay_prescaler_size; prescaler++) {
for (scaler = 0; scaler < delay_scaler_size; scaler++) {
real_delay = ((4000000000UL / clock_source_value) * delay_prescaler[prescaler] * delay_scaler[scaler]) / 4U;
/**
* Calculate the delay difference based on the conditional statement
* that states that the calculated delay must not be less then the desired delay.
*/
if (real_delay >= (1000000000UL / speed)) {
diff = real_delay - (1000000000UL / speed);
if (min_diff > diff) {
/* A better match found. */
min_diff = diff;
best_prescaler = prescaler;
best_scaler = scaler;
best_delay = real_delay;
}
}
if (0U == min_diff)
break;
}
if (0U == min_diff)
break;
}
/* Write the best dbr, prescaler, and baud rate scaler to the CTAR. */
set_delay_scaler(hal_ll_hw_reg, best_prescaler, best_scaler, delay);
}
static void _hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) {
hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base;
// First, make sure the module is enabled to allow writes to certain registers.
clear_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_MDIS_SHIFT);
// Halt all transfers.
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_HALT_SHIFT);
hal_ll_hw_reg->sr = SPI_MASTER_SR_TCF_MASK | SPI_MASTER_SR_EOQF_MASK | SPI_MASTER_SR_TFUF_MASK | SPI_MASTER_SR_TFFF_MASK | SPI_MASTER_SR_RFOF_MASK | SPI_MASTER_SR_RFDF_MASK;
hal_ll_hw_reg->tcr = 0;
hal_ll_hw_reg->ctar0 = SPI_MASTER_CTAR_DEFAULT;
hal_ll_hw_reg->ctar1 = SPI_MASTER_CTAR_DEFAULT;
hal_ll_hw_reg->rser = 0;
hal_ll_hw_reg->pushr = 0;
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_CLR_RXF_SHIFT);
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_CLR_TXF_SHIFT);
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_MDIS_SHIFT);
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_HALT_SHIFT);
// Set master mode.
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_MSTR_SHIFT);
// Disable FIFO.
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_DIS_RXF_SHIFT);
set_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_DIS_TXF_SHIFT);
// Enable spi module.
clear_reg_bit(&(hal_ll_hw_reg->mcr),SPI_MASTER_MCR_MDIS_SHIFT);
hal_ll_hw_reg->ctar0 |= SPI_MASTER_CTAR_BR_3BITS_MASK;