{"payload":{"header_redesign_enabled":false,"results":[{"id":"526942989","archived":false,"color":"#b2b7f8","followers":2,"has_funding_file":false,"hl_name":"MuballighHossain/Moore_Machine_VLSI","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":526942989,"name":"Moore_Machine_VLSI","owner_id":65614878,"owner_login":"MuballighHossain","updated_at":"2022-08-20T14:02:10.886Z","has_issues":true}},"sponsorable":false,"topics":["verilog","vlsi","verilog-hdl","vlsi-physical-design","moore-machine","moore","vlsi-circuits","vlsi-design"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":49,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AMuballighHossain%252FMoore_Machine_VLSI%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/MuballighHossain/Moore_Machine_VLSI/star":{"post":"4Z-tvCLV5StkzMfBlhPYdJ0h7iu2cr-3-P2TOUjNSfKHk3Li63YDvh696LJskTvrdbvD6S-4awUXLMi7HOu0Yw"},"/MuballighHossain/Moore_Machine_VLSI/unstar":{"post":"8ASRaS8Rf3leGeoqJ_lhOmrHK2skgqlDkxHny7Y9PWklT9GhFXdYgBclfeTEvrg-jRLjT4MpgP46Cmfci2rxWw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"reAsSCBlX3eRC4XIMXSpU8Hddv90tA9Jds5hc0MnWAFZAxTe8U_0wIQ1ZpTnSHD8ifYE_sPE_11R5ODWApY33Q"}}},"title":"Repository search results"}