Variable length encoding of address modes and operands

[hippietrail]

There's still a few things in Sleigh that I don't grasp after reading the docs a few times, looking at the slaspec of CPUs I have some familiarity with, and hands-on experimentation with my own processor definition.

The language I'm working on has an operand type the manual refers to as gdest which works like this:

• If the first byte is < 0x80 (high bit not set) then use it as 7-bit "CPU RAM direct"
• If the high bit is set, the high nybble specify the addressing mode of the following bytes:
• High nybble 0x8 to 0xB are different addressing modes that use the now nybble of the first byte and the following byte
• High nybble 0xC to 0xF are the same indexed versions of the previous four addressing modes where the index is in the third byte

So far I've just been making a new entry in my slaspec for each combination of opcode and addressing mode as I run into them in the sample binaries I'm disassembling.
But it's getting unwieldy, especially when some opcodes can take two gdest operands.

I feel like there must be a way to define this gdest once that can handle all three lengths, that I can refer to from any opcode as needed.

But I'm stuck with where to look to proceed. The closest I can think of is opcodes involving a prefix byte on some CPUs, but that seems too different.

Is it even possible?

[GhidorahRex]

It's absolutely possible, although it might be complicated if the second gdest scenario has non-contiguous bytes, but that can be dealt with as well.

I would suggest looking at the m68000 module's addressing modes, or x86's memory operands. Essentially, what you need is ellipses.

Imagine you have a add instruction with an opcode of 0x4. So you might have:add gdest is (opcode=0x4) & ... gdest but not knowing the exact syntax, I'm just hazarding a guess there. The ellipses is telling sleigh that the subconstructor gdest has a variable length and it's right-justified. If instead you had :add gdest is (opcode=0x4) ... & gdestThat would indicate that it was left-justified. The memory operands for x86 have to deal with multiple sizes. Therm32 and rm64 subconstructors have to deal with this.

[hippietrail]

Aha. The ellipsis section is a part of the Sleigh doc I read several times and still couldn't understand when looking at some processor definitions using it. Maybe now I have more additional context to get further with it.