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.gitmodules
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.gitmodules
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[submodule "FPGA/cores/aes"]
path = FPGA/cores/aes
url = ../aes.git
[submodule "FPGA/cores/aes-siv"]
path = FPGA/cores/aes-siv
url = ../aes-siv.git
[submodule "FPGA/cores/cmac"]
path = FPGA/cores/cmac
url = ../cmac.git
[submodule "FPGA/cores/md5"]
path = FPGA/cores/md5
url = ../md5.git
[submodule "FPGA/cores/sha1"]
path = FPGA/cores/sha1
url = ../sha1.git
[submodule "FPGA/cores/siphash"]
path = FPGA/cores/siphash
url = ../siphash.git
[submodule "FPGA/cores/api_extension"]
path = FPGA/network_path/api_extension
url = ../api_extension.git
[submodule "FPGA/cores/keymem"]
path = FPGA/network_path/keymem
url = ../keymem.git
[submodule "FPGA/cores/nts"]
path = FPGA/network_path/nts
url = ../nts.git
[submodule "FPGA/cores/nts_noncegen"]
path = FPGA/network_path/nts_noncegen
url = ../nts_noncegen.git
[submodule "FPGA/cores/rosc_entropy"]
path = FPGA/cores/rosc_entropy
url = ../rosc_entropy
[submodule "FPGA/cores/verilog-ethernet"]
path = FPGA/cores/verilog-ethernet
url = ../verilog-ethernet
[submodule "FPGA/cores/verilog-i2c"]
path = FPGA/cores/verilog-i2c
url = ../verilog-i2c
[submodule "FPGA/cores/neorv32"]
path = FPGA/cores/neorv32
url = ../neorv32