The channels element provides channels for streaming data directly between kernel and I/O. Each channel (implemented using Avalon-ST specification) must be connected to the kernel via the interface attribute. The channel interface only supports data, and valid and ready Avalon-ST signals. The I/O channel defaults to 8-bit symbols and big-endian ordering at the interface level.
-Figure 2-10 shows an example of channels element for a single channel with a width of 64 bits. The chan_id attribute identified helps identify the port in the generated kernel_system. Refer to section 2.1.4 for more information about the interface attribute parameters. Additional interface attributes can be added for additional channels.
+Figure 2-10 shows an example of channels element for a single channel with a width of 64 bits. The chan_id attribute identified helps identify the port in the generated kernel_system. Refer to section 2.1.4 for more information about the interface attribute parameters. Additional interface attributes can be added for additional channels.
Figure 2-10: channels Element Example
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For more information about kernel development using channels, refer to I/O Pipes section in FPGA Optimization Guide for Intel® oneAPI Toolkits.
2.2 board_env.xml File
@@ -3471,6 +3509,8 @@ 2.2 board_env.xml FileThe board_env.xml file is used by the oneAPI toolkit to set up the board installation that enables the compiler to target a specific accelerator platform. The board_env.xml file must be located in the top most level of the oneAPI ASP for each platform. For example, the board_env.xml for oneAPI ASP for OFS reference platforms is located in the oneapi-asp/Platform-Name folder, where Platform-Name is n6001 for Agilex OFS and d5005 for Stratix 10 OFS.
A sample board_env.xml file is shown below. Table 2-9 explains the elements of this file.
Figure 2-11: board_env.xml File Structure
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Table 2-9: Specifications of XML Elements and Attributes in the board_env.xml File
@@ -3499,7 +3539,7 @@ 2.2 board_env.xml File
| linkflags |
-A string that specifies the linker flags necessary for linking with the MMD layer available with the board
> Note: You can use %b to reference your oneAPI ASP directory and provide path relative to oneAPI ASP directory, for example, if MMD library is located inside linux64/lib folder in oneAPI ASP, the path would be %b/linux64/lib. |
+A string that specifies the linker flags necessary for linking with the MMD layer available with the board
> Note: You can use %b to reference your oneAPI ASP directory and provide path relative to oneAPI ASP directory, for example, if MMD library is located inside linux64/lib folder in oneAPI ASP, the path would be %b/linux64/lib. |
| linklibs |
@@ -3544,7 +3584,11 @@ 3.1.1 OpenCL Memory Bank Divider
The OpenCL™ Memory Bank Divider is a Platform Designer component that takes an incoming request from the host interface on the Avalon®-MM agent port and routes it to the appropriate bank host port. This component must reside on the path between the host and the global memory interfaces. In addition, it must reside outside of the path between the kernel and the global memory interfaces.
Figure 3-1: OpenCL Memory Bank Divider IP
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Table 3-1: Parameter Settings for the OpenCL Memory Bank Divider Component
@@ -3642,10 +3686,14 @@ 3.2.1 OpenCL Kernel InterfaceThe OpenCL Kernel Interface is a Platform Designer component that allows the host interface to access and control the oneAPI kernel.
Figure 3-2: OpenCL Kernel Interface IP
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-*Note: OpenCL Kernel Interface IPs are device specific. There are different IPs for Intel® Stratix 10® FPGA and Intel® Agilex® 7 FPGA device families. Please refer to hardware designs for oneAPI ASP for OFS reference platforms to view device specific instantiations for OpenCL Kernel Interface IPs.
* Stratix 10
