From e43578427fc5b91364dfc27d8f5e1fb1036fa8ef Mon Sep 17 00:00:00 2001 From: DavidbrOFS <101847651+DavidbrOFS@users.noreply.github.com> Date: Tue, 6 Feb 2024 14:22:08 -0600 Subject: [PATCH] Delete sw directory this folder is not longer required Signed-off-by: DavidbrOFS <101847651+DavidbrOFS@users.noreply.github.com> --- sw/build_chain/fpga_api/api_build/index.html | 1827 ----------- .../fpga_driver/driver_build/index.html | 1801 ----------- sw/drv_arch/Driver_Organization.png | Bin 58991 -> 0 bytes sw/drv_arch/FPGA_PCIe_Device.png | Bin 3976 -> 0 bytes sw/drv_arch/FPGA_PCIe_Device_SRIOV.png | Bin 4487 -> 0 bytes sw/drv_arch/drv_arch/index.html | 2209 ------------- sw/drv_arch/fme_init_flow.mscgen | 12 - sw/drv_arch/fme_init_flow.png | Bin 4999 -> 0 bytes sw/drv_arch/pci_init_flow.mscgen | 39 - sw/drv_arch/port_init_flow.mscgen | 12 - sw/drv_arch/port_init_flow.png | Bin 4919 -> 0 bytes sw/fpga_api/fpga_api/index.html | 2402 --------------- sw/fpga_api/fpga_cxx_api/index.html | 2255 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sw/fpga_tools/fpgaflash/superrsu/index.html | 2153 ------------- sw/fpga_tools/fpgainfo/fpgainfo/index.html | 2087 ------------- sw/fpga_tools/fpgamux/fpgamux/index.html | 1918 ------------ sw/fpga_tools/fpgaport/fpgaport/index.html | 1860 ----------- .../fpgasupdate/fpgasupdate/index.html | 1920 ------------ .../host_exerciser/host_exerciser/index.html | 2076 ------------- sw/fpga_tools/hssi/hssi/index.html | 1981 ------------ sw/fpga_tools/hssi_config/readme/index.html | 2083 ------------- .../hssi_ethernet/hssiloopback/index.html | 1917 ------------ .../hssi_ethernet/hssimac/index.html | 1915 ------------ .../hssi_ethernet/hssistats/index.html | 1913 ------------ sw/fpga_tools/hssi_loopback/readme/index.html | 1906 ------------ sw/fpga_tools/mem_tg/mem_tg/index.html | 1990 ------------ sw/fpga_tools/mmlink/mmlink/index.html | 1943 ------------ sw/fpga_tools/ofs.uio/ofs.uio/index.html | 2167 ------------- sw/fpga_tools/opae.io/opae.io/index.html | 2135 ------------- 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sw/include/opae/version.h | 79 - sw/include/opae/vfio.h | 542 ---- .../installation_guide/index.html | 2452 --------------- sw/pyopae/python_bindings/index.html | 2034 ------------ sw/samples/hello_events/CMakeLists.txt | 46 - sw/samples/hello_events/hello_events.c | 345 --- sw/samples/hello_fpga/CMakeLists.txt | 46 - sw/samples/hello_fpga/hello_fpga.c | 544 ---- sw/tod/tod/index.html | 2012 ------------ 99 files changed, 100972 deletions(-) delete mode 100644 sw/build_chain/fpga_api/api_build/index.html delete mode 100644 sw/build_chain/fpga_driver/driver_build/index.html delete mode 100644 sw/drv_arch/Driver_Organization.png delete mode 100644 sw/drv_arch/FPGA_PCIe_Device.png delete mode 100644 sw/drv_arch/FPGA_PCIe_Device_SRIOV.png delete mode 100644 sw/drv_arch/drv_arch/index.html delete mode 100644 sw/drv_arch/fme_init_flow.mscgen delete mode 100644 sw/drv_arch/fme_init_flow.png delete mode 100644 sw/drv_arch/pci_init_flow.mscgen delete mode 100644 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Steps

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  1. Fetch the OPAE SDK source tree
    2. -
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    3. -
  3. Build OPAE SDK targets
    4. -
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The example below lists commands that can be used to fetch and build OPAE SDK.

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# fetch the source
-git clone https://github.com/OPAE/opae-sdk.git
-cd opae-sdk
-# configure CMake
-cmake ..
-# build
-make
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For a list of targets that can be built, type make help from the build -directory.

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CMake options that may be set during the configuration include the following:

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|----------------------------|-----------------------|-------------------------------------|---------------------------------------|----------------|
-| cmake flag                 | Optional or Mandatory | Purpose                             | Valid values                          | Default value  |
-|----------------------------|-----------------------|-------------------------------------|---------------------------------------|----------------|
-| -DCMAKE_BUILD_TYPE         | Optional              | Set compiler flags                  | Debug/Release/Coverage/RelWithDebInfo | RelWithDebInfo |
-| -DOPAE_BUILD_LEGACY        | Optional              | Enable/disable opae-legacy.git      | ON/OFF                                | OFF            |
-| -DOPAE_BUILD_SPHINX_DOC    | Optional              | Enable/disable documentation build  | ON/OFF                                | OFF            |
-| -DOPAE_BUILD_TESTS         | Optional              | Enable/disable building unit tests  | ON/OFF                                | OFF            |
-| -DOPAE_INSTALL_RPATH       | Optional              | Enable/disable rpath for install    | ON/OFF                                | OFF            |
-| -DOPAE_BUILD_LIBOPAE_CXX   | Optional              | Enable/disable OPAE C++ bindings    | ON/OFF                                | ON             | 
-| -DOPAE_WITH_PYBIND11       | Optional              | Enable/disable pybind11 binaries    | ON/OFF                                | ON             |
-| -DOPAE_BUILD_PYTHON_DIST   | Optional              | Enable/disable Python Distribution  | ON/OFF                                | OFF            |
-| -DOPAE_ENABLE_MOCK         | Optional              | Enable/disable mocks for unit tests | ON/OFF                                | OFF            |
-| -DOPAE_BUILD_SIM           | Optional              | Enable/disable opae-sim.git         | ON/OFF                                | OFF            |
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Building the OPAE Intel FPGA driver (out-of-tree)

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The Intel FPGA driver included with OPAE SDK releases is packaged as an RPM or -DEB package as well as a source tarball. Starting with OPAE SDK release of 1.4, -the driver can be built from source out-of-tree but requires the following -packages:

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For RPM package managers (Red Hat, CentOS, Fedora, etc.) -* kernel-headers -* kernel-devel -* gcc -* make

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For DEB package managers (Debian, Ubuntu, etc.) -* kernel-headers-generic -* gcc -* make

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After installation of necessary distribution packages, follow the steps in the -example below to build the Intel Kernel driver. -NOTE The example below references Intel FPGA Kernel driver version 2.0.2. but -can be applied to later versions.

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tar zxf opae-intel-fpga-driver-2.0.2-1.tar.gz
-cd opae-intel-fpga-driver-2.0.2
-make
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Open Programmable Accelerator Engine (OPAE) Linux Device Driver Architecture

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The OPAE FPGA Linux Device Driver provides interfaces for user-space applications to -configure, enumerate, open, and access FPGA accelerators on platforms equipped -with Intel FPGA solutions. The OPAE FPGA driver also enables system-level management functions such -as FPGA reconfiguration and virtualization.

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Hardware Architecture

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The Linux Operating System treats the FPGA hardware as a PCIe* device. A predefined data structure, -Device Feature List (DFL), allows for dynamic feature discovery in an Intel -FPGA solution.

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FPGA PCIe Device

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The Linux Device Driver implements PCIe Single Root I/O Virtualization (SR-IOV) for the creation of -Virtual Functions (VFs). The device driver can release individual accelerators -for assignment to virtual machines (VMs).

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Virtualized FPGA PCIe Device

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FPGA Management Engine (FME)

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The FPGA Management Engine provides error reporting, reconfiguration, performance reporting, and other -infrastructure functions. Each FPGA has one FME which is always accessed through the Physical -Function (PF). The Intel Xeon® Processor with Integrated FPGA also performs power and thermal management. -These functions are not available on the Intel Programmable Acceleration Card (PAC).

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User-space applications can acquire exclusive access to the FME using open(), -and release it using close(). Device access may be managed by standard Linux -interfaces and tools.

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If an application terminates without freeing the FME or Port resources, Linux closes all file descriptors owned by the terminating process, freeing those resources.

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Port

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A Port represents the interface between two components: -* The FPGA Interface Manager (FIM) which is part of the static FPGA fabric -* The Accelerator Function Unit (AFU) which is the partially reconfigurable region

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The Port controls the communication from software to the AFU and makes features such as reset and debug available.

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Accelerator Function Unit (AFU)

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An AFU attaches to a Port. The AFU provides a 256 KB memory mapped I/O (MMIO) region for accelerator-specific control registers.

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  • Use open() on the Port device to acquire access to an AFU associated with the Port device.
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  • Use close()on the Port device to release the AFU associated with the Port device.
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  • Use mmap() on the Port device to map accelerator MMIO regions.
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Partial Reconfiguration (PR)

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Use PR to reconfigure an AFU from a bitstream file. Successful reconfiguration has the following requirement:

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  • You must generate the reconfiguration AFU for the exact FIM. The AFU and FIM are compatible if their interface IDs match. -You can verify this match by comparing the interface ID in the bitstream header against the interface ID that is -exported by the driver in sysfs.
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In all other cases PR fails and may cause system instability.

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Platforms that support 512-bit Partial Reconfiguration require binutils >= version 2.25.

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Close any software programs accessing the FPGA, including those running in a virtualized host before -initiating PR. For virtualized environments, the recommended sequence is as -follows:

-
    -
  1. Unload the driver from the guest
    2. -
  2. Release the VF from the guest
    3. -
-
-

Releasing the VF from the guest while an application on the guest is still accessing its resources may lead to VM instabilities. We recommend closing all applications accessing the VF in the guest before releasing the VF.

-
-
    -
  1. Disable SR-IOV
    2. -
  2. Perform PR
    3. -
  3. Enable SR-IOV
    4. -
  4. Assign the VF to the guest
    5. -
  5. Load the driver in the guest
    6. -
-

FPGA Virtualization

-

To enable accelerator access from applications running on a VM, create a VF for -the port using the following process:

-
    -
  1. -

    Release the Port from the PF using the associated ioctl on the FME device.

    -
    2. -
  2. -

    Use the following command to enable SR-IOV and VFs. Each VF can own a single Port with an AFU. In the following command, -N is the number of Port released from the PF.

    -
    3. -
-
    echo N > $PCI_DEVICE_PATH/sriov_numvfs
-
-
-

The number, 'N', cannot be greater than the number of supported VFs. This can be read from $PCI_DEVICE_PATH/sriov_totalvfs.

-
-
    -
  1. -

    Pass the VFs through to VMs using hypervisor interfaces.

    -
    2. -
  2. -

    Access the AFU on a VF from applications running on the VM using the same driver inside the VM.

    -
    3. -
-
-

Creating VFs is only supported for port devices. Consequently, PR and other management functions are only available through the PF.

-
-


-
-

If assigning multiple devices to the same VM on a guest IOMMU, you may need to increase the hard_limit option in order to avoid hitting a limit of pinned memory. The hard limit should be more than (VM memory size x Number of PCIe devices).

-
-

Driver Organization

-

PCIe Module Device Driver

-

Driver Organization

-

FPGA devices appear as a PCIe devices. Once enumeration detects a PCIe PF or VF, the Linux OS loads the FPGA PCIe -device driver. The device driver performs the following functions:

-
    -
  1. Walks through the Device Feature List in PCIe device base address register (BAR) memory to discover features -and their sub-features and creates necessary platform devices.
    2. -
  2. Enables SR-IOV.
    3. -
  3. Introduces the feature device infrastructure, which abstracts operations for sub-features and provides common functions -to feature device drivers.
    4. -
-

PCIe Module Device Driver Functions

-

The PCIe Module Device Driver performs the following functions:

-
    -
  1. PCIe discovery, device enumeration, and feature discovery.
    2. -
  2. Creates sysfs directories for the device, FME, and Port.
    3. -
  3. Creates the platform driver instances, causing the Linux kernel to load their respective drivers.
    4. -
-

FME Platform Module Device Driver

-

The FME Platform Module Device Driver loads automatically after the PCIe driver creates the -FME Platform Module. It provides the following features for FPGA management:

-
    -
  1. -

    Power and thermal management, error reporting, performance reporting, and other infrastructure functions. You can access -these functions via sysfs interfaces the FME driver provides.

    -
    2. -
  2. -

    Partial Reconfiguration. During PR sub-feature initialization, the FME driver registers the FPGA Manager framework -to support PR. When the FME receives the relevant ioctl request from user-space, it invokes the common interface -function from the FPGA Manager to reconfigure the AFU using PR.

    -
    3. -
  3. -

    Port management for virtualization (releasing/assigning port device).

    -
    4. -
-

After a port device is released, you can use the PCIe driver SR-IOV interfaces to create/destroy VFs.

-

For more information, refer to "FPGA Virtualization".

-

FME Platform Module Device Driver Functions

-

The FME Platform Module Device Driver performs the the following functions:

-
    -
  • Creates the FME character device node.
    • -
  • Creates the FME sysfs files and implements the FME sysfs file accessors.
    • -
  • Implements the FME private feature sub-drivers.
    • -
  • FME private feature sub-drivers: - * FME Header - * Partial Reconfiguration - * Global Error - * Global Performance
    • -
-

Port Platform Module Device Driver

-

After the PCIe Module Device Driver creates the Port Platform Module device, -the FPGA Port and AFU driver are loaded. This module provides an -interface for user-space applications to access the individual -accelerators, including basic reset control on the Port, AFU MMIO region -export, DMA buffer mapping service, and remote debug functions.

-

Port Platform Module Device Driver Functions

-

The Port Platform Module Device Driver performs the the following functions:

-
    -
  • Creates the Port character device node.
    • -
  • Creates the Port sysfs files and implements the Port sysfs file accessors.
    • -
  • Implements the following Port private feature sub-drivers. - * Port Header - * AFU - * Port Error - * Signal Tap
    • -
-

OPAE FPGA Driver Interface

-

The user-space interface consists of a sysfs hierarchy and ioctl requests. Most -kernel attributes can be accessed/modified via sysfs nodes in this hierarchy. -More complex I/O operations are controlled via ioctl requests. The OPAE API -implementation, libopae-c, has been designed to use this interface to -interact with the OPAE FPGA kernel drivers.

- - - - - - -
-
- - -
- - - -
- - - -
-
-
-
- - - - - - - - - \ No newline at end of file diff --git a/sw/drv_arch/fme_init_flow.mscgen b/sw/drv_arch/fme_init_flow.mscgen deleted file mode 100644 index a8f836cf0..000000000 --- a/sw/drv_arch/fme_init_flow.mscgen +++ /dev/null @@ -1,12 +0,0 @@ -msc { - hscale = "2"; - - fme_probe,fme_dev_init,fpga_dev_feature_init,feature_instance_init,fpga_register_dev_ops; - - fme_probe=>fme_dev_init; - - fme_probe=>fpga_dev_feature_init; - fpga_dev_feature_init=>feature_instance_init; - - fme_probe=>fpga_register_dev_ops; -} diff --git a/sw/drv_arch/fme_init_flow.png b/sw/drv_arch/fme_init_flow.png deleted file mode 100644 index 9fd6167e8095a13ba432a4834e00fc238306d3df..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4999 zcmc&&2{hDg-~LyMG%{_Ev8zOjkX@E3L?Vhj$TF6C#=eKa%#<3EwS^EP30WegOvaMz z*|J3084PKLEMptyyGNb(`=0N6&-u=GzVn`U&YAh&Gjp%k@4Bwvecut6jP!W81-Kyy z;?X~^V*)`OuRuAOYb*FvQj_QdkDXrUEqx(qcMbc!CH};2K?vHXs;_hQN?;0Yz}xB3 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index 71c579f99..000000000 --- a/sw/drv_arch/pci_init_flow.mscgen +++ /dev/null @@ -1,39 +0,0 @@ -msc { - hscale = "1"; - - ccidrv_init,b,c,d,e,cci_pci_probe,f,g,h,i,j,k,l,m,n,o,p,q,r,s; - -// parse_feature_list,parse_feature,parse_feature_afus,parse_feature_fme, -// build_info_create_dev,h,create_feature_instance,build_info_add_sub_feature, -// i,j,k; - - -// idr_init,alloc_chrdev_region,class_create,pci_register_driver, -// cci_pci_probe,create_init_drvdata,cci_pci_create_feature_devs, -// build_info_alloc_and_init,parse_feature_list,parse_feature,parse_feature_afus, -// parse_feature_fme,build_info_create_dev,idr_alloc,create_feature_instance,build_info_add_sub_feature, -// feature_platform_data_add,parse_ports_from_fme,build_info_commit_dev; - - ccidrv_init=>b [ label="idr_init" ]; - ccidrv_init=>c [ label="alloc_chrdev_region" ]; - ccidrv_init=>d [ label="class_create" ]; - ccidrv_init=>e [ label="pci_register_driver" ]; - - cci_pci_probe=>f [ label="create_init_drvdata" ]; - cci_pci_probe=>g [ label="cci_pci_create_feature_devs" ]; - - g=>h [ label="build_info_alloc_and_init" ]; - g=>i [ label="parse_feature_list" ]; - - i=>j [ label="parse_feature" ]; - j=>k [ label="parse_feature_afus" ]; - k=>l [ label="parse_feature_fme" ]; - l=>m [ label="build_info_create_dev" ]; - m=>n [ label="idr_alloc" ]; - k=>o [ label="create_feature_instance" ]; - o=>p [ label="build_info_add_sub_feature" ]; - p=>q [ label="feature_platform_data_add" ]; - - g=>r [ label="parse_ports_from_fme" ]; - g=>s [ label="build_info_commit_dev" ]; -} diff --git a/sw/drv_arch/port_init_flow.mscgen b/sw/drv_arch/port_init_flow.mscgen deleted file mode 100644 index 7394f7291..000000000 --- a/sw/drv_arch/port_init_flow.mscgen +++ /dev/null @@ -1,12 +0,0 @@ -msc { - hscale = "2"; - - afu_probe,afu_dev_init,fpga_dev_feature_init,feature_instance_init,fpga_register_dev_ops; - - afu_probe=>afu_dev_init; - - afu_probe=>fpga_dev_feature_init; - fpga_dev_feature_init=>feature_instance_init; - - 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zy~^X?vX=nZA!s`Pl6kLlGWm(SfuV>L>&04)3@~&8e|@uy7MaNNpRt%# ZWO5>%4Xu)!1hxX5Gq`xBQ152&zW^>oWPtzx diff --git a/sw/fpga_api/fpga_api/index.html b/sw/fpga_api/fpga_api/index.html deleted file mode 100644 index 8f674d628..000000000 --- a/sw/fpga_api/fpga_api/index.html +++ /dev/null @@ -1,2402 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - OPAE C API Reference - OFS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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OPAE C API Reference

-

The reference documentation for the OPAE C API is grouped into the following sections:

- -

Types

-

The OPAE C API defines a number of types; most prominent are the types fpga_token, fpga_handle, and fpga_properties. All regular types are defined in types.h, while the values of enumeration types are defined in types_enum.h.

-

types.h

-

types.h

-

types_enum.h

-

types_enum.h

-

Enumeration API

-

The OPAE enumeration API allows selective discovery of FPGA resources. When enumerating resources, a list of filter criteria can be passed to the respective function to select a subset of all resources in the system. The fpgaEnumerate() function itself then returns a list of fpga_tokens denoting resources, which can be used in subsequent API calls.

-

Filter criteria are specified using one or more fpga_properties object. These objects need to be created using fpgaGetProperties() (defined in ) before being passed to fpgaEnumerate(). Individual attributes of an fpga_properties object are set using specific accessors, which are also defined in .

-

enum.h

-

enum.h

-

properties.h

-

properties.h

-

Access API

-

The access API provides functions for opening and closing FPGA resources. Opening a resource yields an fpga_handle, which denotes ownership and can be used in subsequent API calls to interact with a specific resource. Ownership can be exclusive or shared.

-

access.h

-

access.h

-

Event API

-

The event API provides functions and types for handling asynchronous events such as errors or accelerator interrupts.

-

To natively support asynchronous event, the driver for the FPGA platform needs to support events natively (in which case the OPAE C library will register the event directly with the driver). For some platforms that do not support interrupt-driven event delivery, you need to run the FPGA Daemon (fpgad) to enable asynchronous OPAE events. fpgad will act as a proxy for the application and deliver asynchronous notifications for registered events.

-

event.h

-

event.h

-

MMIO and Shared Memory APIs

-

These APIs feature functions for mapping and accessing control registers through memory-mapped IO (mmio.h), allocating and sharing system memory buffers with an accelerator (buffer.h), and using low-latency notifications (umsg.h).

-

mmio.h

-

mmio.h

-

buffer.h

-

buffer.h

-

umsg.h

-

umsg.h

-

Management API

-

The management APIs define functions for reconfiguring an FPGA (writing new partial bitstreams) as well as assigning accelerators to host interfaces.

-

manage.h

-

manage.h

-

Metrics API

-

The metrics APIs define functions for discovery/enumeration of metrics information and reading metrics values.

-

metrics.h

-

metrics.h

-

SysObject

-

The SysObject API can be used to get system objects by name. Names used with the SysObject API are driver-specific and may not be compatible across plugins and/or drivers. For example, SysObject names used with the xfpga plugin will apply to the OPAE Linux Kernel driver and refer to sysfs nodes under the sysfs tree for the resource used with the SysObject API.

-

sysobject.h

-

sysobject.h

-

Utilities

-

Functions for mapping fpga_result values to meaningful error strings are provided by the utilities API.

-

utils.h

-

utils.h

-

Samples

-

Code samples demonstrate how to use OPAE C API.

-

hello_fpga.c

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hello_fpga.c

-

hello_events.c

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hello_events.c

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OPAE C++ Core API Reference

-

The reference documentation for the OPAE C++ Core API is grouped into the following sections:

- -

Overview

-

The OPAE C++ API enables C++ developers with the means to use FPGA resources by integrating the OPAE software stack into C++ applications.

-

Goals

-

Simplicity

-

Keep the API as small and lightweight as possible. Although features such as system validation and orchestration are beyond the scope of this API, using this API for their development should be relatively easy.

-

Extensibility and Interoperability

-

While keeping to the goal of simplicity, the OPAE C++ API is designed to allow for better reuse by either extending the API or by integrating with other languages.

-

Modern C++ Coding Practices

-

The OPAE C++ API uses the C++ 11 standard library and makes use of its features whenever practical. The OPAE C++ API is also designed to require the minimum number of third-party libraries/dependencies.

-

Error Handling

-

The OPAE C++ API is designed to throw exceptions when appropriate. The structure of OPAE C++ exceptions is similar to the error codes in the OPAE C API. This gives users of the API more freedom on error handling while providing better debug information in cases of failure.

-

Coding Style

-

For formatting of the OPAE C++ API complies with most of the recommendations of the Google C++ style. For example, the OPAE C++ API uses:

-
    -
  • opening braces on the same line as their scope definition
    • -
  • spaces instead of tabs for indentation
    • -
  • indentation of two spaces
    • -
-

Fundamental Types

-

Basic types for the OPAE C++ API are found in the opae::fpga::types namespace. They serve as an adapter layer between the OPAE C API and the OPAE C++ layer. Aside from providing a C++ binding to the C fundamental types, these types also:

-
    -
  • manage the lifetime and scope of the corresponding C struct.
    • -
-
-
    -
  • For example a C++ destructor will take care of calling the appropriate C function to release the data structure being wrapped.
    • -
-
-
    -
  • provide a friendly syntax for using the OPAE C type.
    • -
-

Most classes in this namespace have a c_type() method that returns the C data structure being wrapped, making it easy to use the OPAE C++ type with the OPAE C API. Alternatively, most classes in this namespace have implicit conversion operators that enable interoperability with the OPAE C API.

-

Properties

-

C++ class properties wraps fpga_properties and uses pvalue and guid_t to get and set properties stored in an instance of an fpga_properties. pvalue and guid_t are designed to call an accessor method in the OPAE C API to either read property values or write them. Most accessor methods in the OPAE C API share a similar signature, so pvalue generalizes them into common operations that translate into calling the corresponding C API function. guid_t follows similar patterns when reading or assigning values.

-

pvalue.h

-

pvalue.h

-

properties.h

-

properties.h

-

Resource Classes

-

The token, handle, and shared_buffer classes are used to enumerate and access FPGA resources. properties are used to narrow the search space for token's. Before enumerating the accelerator resources in the system, applications can produce one or more properties objects whose values are set to the desired characteristics for the resource. For example, an application may search for an accelerator resource based on its guid.

-

Once one or more token's have been enumerated, the application must choose which token's to request. The token is then converted to a handle by requesting that a handle object be allocated and opened for it.

-

Once a handle has been successfully opened, the application can read and write the associated configuration and status space. Additionally, the application may use the handle to allocate shared_buffer's or to register event's. The shared_buffer and event objects retain a reference to their owning handle so that the handle does not lose scope before freeing the shared_buffer and event objects.

-

token.h

-

token.h

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handle.h

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handle.h

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shared_buffer.h

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shared_buffer.h

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errors.h

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errors.h

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events.h

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events.h

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sysobject.h

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sysobject.h

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Exceptions

-

When the OPAE C++ API encounters an error from the OPAE C API, it captures the current source code location and the error code into an object of type except, then throws the except. Applications should implement the appropriate catch blocks required to respond to runtime exceptions.

-

except.h

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except.h

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Misc

-

The version class wraps the OPAE C version API.

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version.h

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version.h

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Plugin Developer's Guide

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Overview

-

Beginning with OPAE C library version 1.2.0, OPAE implements a plugin-centric -model. This guide serves as a reference to define the makeup of an OPAE C API -plugin and to describe a sequence of steps that one may follow when constructing -an OPAE C API plugin.

-

Plugin Required Functions

-

An OPAE C API plugin is a runtime-loadable shared object library, also known as -a module. On Linux systems, the dl family of APIs from libdl are used to -interact with shared objects. Refer to "man dlopen" and "man dlsym" for examples -of using the libdl API.

-

An OPAE C API plugin implements one required function. This function is required -to have C linkage, so that its name is not mangled.

-
    int opae_plugin_configure(opae_api_adapter_table *table, const char *config);
-
-

During initialization, the OPAE plugin manager component loads each plugin, -searching for its opae_plugin_configure function. If none is found, then -the plugin manager rejects that plugin. When it is found, opae_plugin_configure -is called passing a pointer to a freshly-created opae_api_adapter_table and -a buffer consisting of configuration data for the plugin.

-

The job of the opae_plugin_configure function is to populate the given adapter -table with each of the plugin's API entry points and to consume and comprehend -the given configuration data in preparation for initialization.

-

OPAE API Adapter Table

-

The adapter table is a data structure that contains function pointer entry points -for each of the OPAE APIs implemented by a plugin. In this way, it adapts the -plugin-specific behavior to the more general case of a flat C API. Note that -OPAE applications are only required to link with opae-c. In other words, the -name of the plugin library should not appear on the linker command line. In this -way, plugins are truly decoupled from the OPAE C API, and they are required to -adapt to the strict API specification by populating the adapter table only. No -other linkage is required nor recommended.

-

adapter.h contains the definition of the opae_api_adapter_table. An abbreviated -version is depicted below, along with supporting type opae_plugin:

-
    typedef struct _opae_plugin {
-        char *path;
-        void *dl_handle;
-    } opae_plugin;
-
-    typedef struct _opae_api_adapter_table {
-
-        struct _opae_api_adapater_table *next;
-        opae_plugin plugin;
-
-        fpga_result (*fpgaOpen)(fpga_token token, fpga_handle *handle,
-                                int flags);
-
-        fpga_result (*fpgaClose)(fpga_handle handle);
-
-        ...
-
-        fpga_result (*fpgaEnumerate)(const fpga_properties *filters,
-                                     uint32_t num_filters, fpga_token *tokens,
-                                     uint32_t max_tokens,
-                                     uint32_t *num_matches);
-
-        ...
-
-        // configuration functions
-        int (*initialize)(void);
-        int (*finalize)(void);
-
-        // first-level query
-        bool (*supports_device)(const char *device_type);
-        bool (*supports_host)(const char *hostname);
-
-    } opae_api_adapter_table;
-
-

Some points worth noting are that the adapter tables are organized in memory by -adding them to a linked list data structure. This is the use of the next -structure member. (The list management is handled by the plugin manager.) -The plugin structure member contains the handle to the shared object instance, -as created by dlopen. This handle is used in the plugin's opae_plugin_configure -to load plugin entry points. A plugin need only implement the portion of the -OPAE C API that a target application needs. Any API entry points that are not -supported should be left as NULL pointers (the default) in the adapter table. -When an OPAE API that has no associated entry point in the adapter table is -called, the result for objects associated with that plugin will be -FPGA_NOT_SUPPORTED.

-

The following code illustrates a portion of the opae_plugin_configure for -a theoretical OPAE C API plugin libfoo.so:

-
    /* foo_plugin.c */
-
-    int opae_plugin_configure(opae_api_adapter_table *table, const char *config)
-    {
-        adapter->fpgaOpen = dlsym(adapter->plugin.dl_handle, "foo_fpgaOpen");
-        adapter->fpgaClose =
-                dlsym(adapter->plugin.dl_handle, "foo_fpgaClose");
-
-        ...
-
-        adapter->fpgaEnumerate =
-                dlsym(adapter->plugin.dl_handle, "foo_fpgaEnumerate");
-
-        ...
-
-        return 0;
-    }
-
-

Notice that the implementations of the API entry points for plugin libfoo.so -are prefixed with foo_. This is the recommended practice to avoid name -collisions and to enhance the debugability of the application. Upon successful -configuration, opae_plugin_configure returns 0 to indicate success. A -non-zero return value indicates failure and causes the plugin manager to -reject the plugin from futher consideration.

-

Plugin Optional Functions

-

Once the plugin manager loads and configures each plugin, it uses the adapter -table to call back into the plugin so that it can be made ready for runtime. -This is the job of the opae_plugin_initialize entry point, whose signature -is defined as:

-
    int opae_plugin_initialize(void);
-
-

The function takes no parameters, as the configuration data was already given -to the plugin by opae_plugin_configure. opae_plugin_initialize returns 0 -if no errors were encountered during initialization. A non-zero return code -indicates that plugin initialization failed. A plugin makes its -opae_plugin_initialize available to the plugin manager by populating the -adapter table's initialize entry point as shown:

-
    /* foo_plugin.c */
-
-    int foo_plugin_initialize(void)
-    {
-        ...
-
-        return 0; /* success */
-    }
-
-    int opae_plugin_configure(opae_api_adapter_table *table, const char *config)
-    {
-        ... 
-
-        adapter->initialize =
-                dlsym(adapter->plugin.dl_handle, "foo_plugin_initialize");
-
-        ...
-
-        return 0;
-    }
-
-

If a plugin does not implement an opae_plugin_initialize entry point, then -the initialize member of the adapter table should be left uninitialized. -During plugin initialization, if a plugin has no opae_plugin_initialize -entry in its adapter table, the plugin initialization step will be skipped, -and the plugin will be considered to have initialized successfully.

-

Once plugin initialization is complete for all loaded plugins, the system -is considered to be running and fully functional.

-

During teardown, the plugin manager uses the adapter table to call into each -plugin's opae_plugin_finalize entry point, whose signature is defined as:

-
    int opae_plugin_finalize(void);
-
-

opae_plugin_finalize returns 0 if no errors were encountered during teardown. -A non-zero return code indicates that plugin teardown failed. A plugin makes -its opae_plugin_finalize available to the plugin manager by populating the -adapter table's finalize entry point as shown:

-
    /* foo_plugin.c */
-
-    int foo_plugin_finalize(void)
-    {
-        ...
-
-        return 0; /* success */
-    }
-
-    int opae_plugin_configure(opae_api_adapter_table *table, const char *config)
-    {
-        ... 
-
-        adapter->finalize =
-                dlsym(adapter->plugin.dl_handle, "foo_plugin_finalize");
-
-        ...
-
-        return 0;
-    }
-
-

If a plugin does not implement an opae_plugin_finalize entry point, then -the finalize member of the adapter table should be left uninitialized. -During plugin cleanup, if a plugin has no opae_plugin_finalize entry -point in its adapter table, the plugin finalize step will be skipped, and -the plugin will be considered to have finalized successfully.

-

In addition to initialize and finalize, an OPAE C API plugin has two -further optional entry points that relate to device enumeration. During -enumeration, when a plugin is being considered for a type of device, the -plugin may provide input on that decision by exporting an -opae_plugin_supports_device entry point in the adapter table:

-
    bool opae_plugin_supports_device(const char *device_type);
-
-

opae_plugin_supports_device returns true if the given device type is -supported and false if it is not. A false return value from -opae_plugin_supports_device causes device enumeration to skip the -plugin.

-

Populating the opae_plugin_supports_device is done as:

-
    /* foo_plugin.c */
-
-    bool foo_plugin_supports_device(const char *device_type)
-    {
-        if (/* device_type is supported */)
-            return true;
-
-        ...
-
-        return false;
-    }
-
-    int opae_plugin_configure(opae_api_adapter_table *table, const char *config)
-    {
-        ... 
-
-        adapter->supports_device =
-                dlsym(adapter->plugin.dl_handle, "foo_plugin_supports_device");
-
-        ...
-
-        return 0;
-    }
-
-
.. note::
-    The `opae_plugin_supports_device` mechanism serves as a placeholder only.
-    It is not implemented in the current version of the OPAE C API.
-
-

Similarly to determining whether a plugin supports a type of device, a plugin -may also answer questions about network host support by populating an -opae_plugin_supports_host entry point in the adapter table:

-
    bool opae_plugin_supports_host(const char *hostname);
-
-

opae_plugin_supports_host returns true if the given hostname is supported -and false if it is not. A false return value from opae_plugin_supports_host -causes device enumeration to skip the plugin.

-

Populating the opae_plugin_supports_host is done as:

-
    /* foo_plugin.c */
-
-    bool foo_plugin_supports_host(const char *hostname)
-    {
-        if (/* hostname is supported */)
-            return true;
-
-        ...
-
-        return false;
-    }
-
-    int opae_plugin_configure(opae_api_adapter_table *table, const char *config)
-    {
-        ... 
-
-        adapter->supports_host =
-                dlsym(adapter->plugin.dl_handle, "foo_plugin_supports_host");
-
-        ...
-
-        return 0;
-    }
-
-
.. note::
-    The `opae_plugin_supports_host` mechanism serves as a placeholder only.
-    It is not implemented in the current version of the OPAE C API.
-
-

Plugin Construction

-

The steps required to implement an OPAE C API plugin, libfoo.so, are:

-
    -
  • Create foo_plugin.c: implements opae_plugin_configure, -opae_plugin_initialize, opae_plugin_finalize, opae_plugin_supports_device, -and opae_plugin_supports_host as described in the previous sections.
    • -
  • Create foo_plugin.h: implements function prototypes for each of the -plugin-specific OPAE C APIs.
    • -
-
    /* foo_plugin.h */
-
-    fpga_result foo_fpgaOpen(fpga_token token, fpga_handle *handle,
-                             int flags);
-
-    fpga_result foo_fpgaClose(fpga_handle handle);
-
-    ...
-
-    fpga_result foo_fpgaEnumerate(const fpga_properties *filters,
-                                  uint32_t num_filters, fpga_token *tokens,
-                                  uint32_t max_tokens,
-                                  uint32_t *num_matches);
-    ...
-
-
    -
  • Create foo_types.h: implements plugin-specific types for opaque data -structures.
    • -
-
    /* foo_types.h */
-
-    struct _foo_token {
-        ...
-    };
-
-    struct _foo_handle {
-        ...
-    };
-
-    struct _foo_event_handle {
-        ...
-    };
-
-    struct _foo_object {
-        ...
-    };
-
-
    -
  • Create foo_enum.c: implements foo_fpgaEnumerate, -foo_fpgaCloneToken, and foo_fpgaDestroyToken.
    • -
  • Create foo_open.c: implements foo_fpgaOpen.
    • -
  • Create foo_close.c: implements foo_fpgaClose.
    • -
  • Create foo_props.c: implements foo_fpgaGetProperties, -foo_fpgaGetPropertiesFromHandle, foo_fpgaUpdateProperties
    • -
  • Create foo_mmio.c: implements foo_fpgaMapMMIO, foo_fpgaUnmapMMIO -foo_fpgaWriteMMIO64, foo_fpgaReadMMIO64, foo_fpgaWriteMMIO32, -foo_fpgaReadMMIO32.
    • -
  • Create foo_buff.c: implements foo_fpgaPrepareBuffer, -foo_fpgaReleaseBuffer, foo_fpgaGetIOAddress.
    • -
  • Create foo_error.c: implements foo_fpgaReadError, foo_fpgaClearError, -foo_fpgaClearAllErrors, foo_fpgaGetErrorInfo.
    • -
  • Create foo_event.c: implements foo_fpgaCreateEventHandle, -foo_fpgaDestroyEventHandle, foo_fpgaGetOSObjectFromEventHandle, -foo_fpgaRegisterEvent, foo_fpgaUnregisterEvent.
    • -
  • Create foo_reconf.c: implements foo_fpgaReconfigureSlot.
    • -
  • Create foo_obj.c: implements foo_fpgaTokenGetObject, -foo_fpgaHandleGetObject, foo_fpgaObjectGetObject, -foo_fpgaDestroyObject, foo_fpgaObjectGetSize, foo_fpgaObjectRead, -foo_fpgaObjectRead64, foo_fpgaObjectWrite64.
    • -
  • Create foo_clk.c: implements foo_fpgaSetUserClock, -foo_fpgaGetUserClock.
    • -
- - - - - - -
-
- - -
- - - -
- - - -
-
-
-
- - - - - - - - - \ No newline at end of file diff --git a/sw/fpga_api/prog_guide/FPGA-lib-1.png b/sw/fpga_api/prog_guide/FPGA-lib-1.png deleted file mode 100644 index f815ca6ada34aef78cb14b596d3b32fdd95419c5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 65857 zcmd?RWmHsA*fxxSgwi0=h_rNrFoXfp3MeTxbcfVX5`wf6GaxX4lpu|CNse?$Bc0OS z@b2+>*0);KxrJSl921aSj-Aj|(;61+63td+X46=9V zpIb8)jGh=6H`$8MO$$#8OTEpc=>HWX`9$wY}!_IbRXJ zfpB$Q9XVZK9r<)8B6p1_wR3a(MZbl|#aU`OyJXx%5)z5r_WOSQ`j7P*zg#SfVr&*B zEzgU6~T)~Qmv)nElb`m0qQ>v5c;nkP_OnhRM8KSReN=|n%3zE zu3{6cmiqX^pnQ3nkYfl`vBqmP)uRRcbKhee{BIZIUZL$+kqP*t+V(3$@VPERRs-p~ zhr{Zj%LpUs8U=8W*ZD#OU(40WEaUN{ZSfMra(kmE`hGR$siRrZFFsg`!_hZ>4>_*` z-o|Qqf=~MIcfc5!qt2cDpGN*y_h$Sqwsy}qibIQ=t{=bKo|aG%>J`q=E;clYRb*3S z7^$7{zqxX1zo#9{=zl4|-FUiSl4K6Y&y2FDQxG{d*r{1X?hZU9{!rRM!&Oi@X=Aco zv#NHjoj@aO_0scvJ-2ngn=fse8N`E>?_T@;`Rj`vV(+aAZI_sRQ}LpK+%!KLHJPhJ zr|YxT(0=I)?wS)uXtadI+HkJ=xNAS8_0jhNGI>Vd!zF*3h?gE~8KEJ}F;apvNUxP7 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OPAE C API Programming Guide

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Overview

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The OPAE C library (libopae-c) is a lightweight user-space library that -provides abstractions for FPGA resources in a compute environment. The OPAE C library -builds on the driver stack that supports the FPGA device, abstracting -hardware- and OS-specific details. It provides access to the underlying FPGA -resources as a set of features available to software programs -running on the host. These features include the acceleration logic -preconfigured on the FPGA and functions to manage and reconfigure -the FPGA. The library enables your applications to -transparently and seamlessly benefit from FPGA-based acceleration.

-

Layered architecture

-

By providing a unified C API, the library supports different FPGA -integration and deployment models, ranging from single-node systems with one or -a few FPGA devices to large-scale FPGA deployments in a data center. -At one end of the spectrum, the API supports a simple application using a PCIe link to reconfigure -the FPGA with different accelerator functions. At the other end of the spectrum, resource -management and orchestration services in a data center can use this API to -discover and select FPGA resources and then allocate them for use by acceleration workloads.

-

OPAE Role

-

The OPAE provides a common base layer for a wide range of -applications without sacrificing performance or efficiency. The abstraction layer limits -the details of the FPGA hardware that software applications must handle.

-

The OPAE provides consistent interfaces to crucial components of the platform. The OPAE does not constrain -frameworks and applications by making optimizations with limited applicability. When the OPAE does -provide convenience functions or optimizations, they are optional.

-

For example, the OPAE provides an interface to allocate physically contiguous -buffers in system memory that user-space software and an accelerator can share. -This interface enables the most basic feature set of -allocating and sharing a large page of memory in one API call. However, it -does not provide a malloc()-like interface backed by a memory pool or slab -allocator. Higher layers of the software stack can make such -domain-specific optimizations.

-

Intel Accelerator Stack Hardware Terminology

-

The following terms define the hardware and hardware processes involved in creating an accelerator function.

-
    -
  • FPGA: Field Programmable Gate Array -is a discrete or integrated device connecting to a host CPU via PCIe or other type of interconnects.
    • -
  • Accelerator Function Unit (AFU): The AFU is the supplied implementation of an accelerator, typically -in HDL. AFUs implement a function such as compression, encryption, or mathematical operations. -The Quartus Prime Pro software synthesizes the RTL logic into a bitstream.
    • -
  • Accelerator Function (AF): The AF is the compiled binary for an AFU. An AF is a raw binary file (.rbf) -bitstream. A tool (fpgaconf) reconfigures the FPGA using an AF bitstream.
    • -
  • Reconfiguration: The process of reprogramming the FPGA with a different AF.
    • -
-

OPAE Software Concepts Reflected in the C API

-

The following OPAE data structures and functions integrate AFUs into the OPAE environment. -The OPAE C API models these data structures and functions. For more information on the object -models refer to the Object model section.

-
    -
  • Accelerator: An accelerator is an allocable accelerator function implemented in an FPGA. -An accelerator tracks the ownership of an AFU (or part of it) for a process that uses it. -Multiple processes can share an accelerator.
    • -
  • Device: The OPAE enumerates and models two device types: the FPGA and the AFU.
    • -
  • Events: Events are asynchronous notifications. The FPGA driver -triggers particular events to indicate error conditions. Accelerator logic can also -define its own events. User applications can choose to be -notified when particular events occur and respond appropriately.
    • -
  • Shared memory buffers: Software allocates shared memory buffers in user process memory -on the host. Shared memory buffers facilitate data transfers between the user process and the -accelerator that it owns.
    • -
-

OPAE Library

-

Linking with this library is straightforward. -Code using the OPAE library should include the header file fpga.h. Taking the GCC -compiler on Linux as an example, here is the simplest compile and link command:

-

gcc myprog.c -I</path/to/fpga.h> -L</path/to/libopae-c.so> -lopae-c -luuid -ljson-c -lpthread

-

.. note::

-
The OPAE library uses the third-party `libuuid` and `libjson-c` libraries that are not distributed with 
-the OPAE library. Make sure to install these libraries.
-
-

Sample Code

-

The library source includes two code samples. Use these samples -to learn how to call functions in the library. Build and run these samples -to determine if your installation and environment are set up properly.

-

Refer to the Running the Hello FPGA Example chapter in the Intel® Acceleration Stack -Quick Start Guide for for Intel Programmable Acceleration Card with Intel Arria® 10 GX FPGA for more information about using the sample code.

-

High-Level Directory Structure

-

Building and installing the OPAE library results in the following directory structure on the Linux OS. -Windows and MacOS have similar directories and files.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Directory & FilesContents
include/opaeDirectory containing all header files
include/opae/fpga.hTop-level header for user code to include
include/opae/access.hHeader file for accelerator acquire/release, MMIO, memory management, event handling, and so on
include/opae/bitstream.hHeader file for bitstream manipulation functions
include/opae/common.hHeader file for error reporting functions
include/opae/enum.hHeader file for AFU enumeration functions
include/opae/manage.hHeader file for FPGA management functions
include/opae/types.hVarious type definitions
libDirectory containing shared library files
lib/libopae-c.soThe shared dynamic library for linking with the user application
docDirectory containing API documentation
doc/htmlDirectory for documentation of HTML format
doc/latexDirectory for documentation of LaTex format
doc/manDirectory for documentation of Unix man page format
-

Basic Application Flow

-

The figure below shows the basic application flow from the -viewpoint of a user-process.

-

Basic flow

-

API Components

-

The API object model abstracts the physical FPGA device and -available functions. It is a generalized model and extends to -describe any FPGA type.

-

Object Models

-
    -
  • fpga_objtype: An enum type that represents the type of an FPGA resource, either FPGA_DEVICE or FPGA_ACCELERATOR. -An FPGA_DEVICE object corresponds to a physical FPGA device. Only FPGA_DEVICE objects can invoke management functions. -The FPGA_ACCELERATOR represents an instance of an AFU.
    • -
  • fpga_token: An opaque type that represents a resource known to, but not -necessarily owned by, the calling process. The calling process must own a -resource before it can invoke functions of the resource.
    • -
  • fpga_handle: An opaque type that represents a resource owned by the -calling process. The API functions fpgaOpen() and fpgaClose() acquire and release ownership of a resource that an fpga_handle represents. (Refer to the Functions section for more information.)
    • -
  • fpga_properties: An opaque type for a properties object. Your -applications use these properties to query and search for appropriate resources. The -FPGA Resource Properties section documents properties visible to your -applications.
    • -
  • fpga_event_handle: An opaque handle the FPGA driver uses to notify your -application about an event.
    • -
  • fpga_event_type: An enum type that represents the types of events. The following are valid values: -FPGA_EVENT_INTERRUPT, FPGA_EVENT_ERROR, and FPGA_EVENT_POWER_THERMAL. (The Intel Programmable Acceleration Card (PAC) with -Intel Arria 10 GX FPGA does not handle thermal and power events.)
    • -
  • fpga_result: An enum type to represent the result of an API function. If the -function returns successfully the result is FPGA_OK. Otherwise, the result is -the appropriate error codes. Function fpgaErrStr() translates an error code -into human-readable strings.
    • -
-

Functions

-

The table below groups important API calls by their functionality. For more information about each of the functions, refer to the -OPAE C API reference manual.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FunctionalityAPI CallFPGAAcceleratorDescription
EnumerationfpgaEnumerate()YesYesQuery FPGA resources that match certain properties
Enumeration: Propertiesfpga[Get, Update, Clear, Clone, Destroy Properties]()YesYesManage fpga_properties life cycle
fpgaPropertiesGet[Prop]()YesYesGet the specified property Prop, from the FPGA Resource Properties table
fpgaPropertiesSet[Prop]()YesYesSet the specified property Prop, from the FPGA Resource Properties table
Access: Ownershipfpga[Open, Close]()YesYesAcquire/release ownership
Access: ResetfpgaReset()YesYesReset an accelerator
Access: Event handlingfpga[Register, Unregister]Event()YesYesRegister/unregister an event to be notified about
fpga[Create, Destroy]EventHandle()YesYesManage fpga_event_handle life cycle
Access: MMIOfpgaMapMMIO(), fpgaUnMapMMIO()YesYesMap/unmap MMIO space
fpgaGetMMIOInfo()YesYesGet information about the specified MMIO space
fpgaReadMMIO[32, 64]()YesYesRead a 32-bit or 64-bit value from MMIO space
fpgaWriteMMIO[32, 64]()YesYesWrite a 32-bit or 64-bit value to MMIO space
Memory management: Shared memoryfpga[Prepare, Release]Buffer()YesYesManage memory buffer shared between the calling process and an accelerator
fpgaGetIOAddress()YesYesReturn the device I/O address of a shared memory buffer
Management: ReconfigurationfpgaReconfigureSlot()YesNoReplace an existing AFU with a new one
Error reportfpgaErrStr()YesYesMap an error code to a human readable string
-

.. note::

-
The UMsg APIs are not supported for the Intel(R) PAC cards. They will be deprecated in a future release.
-
-

FPGA Resource Properties

-

Applications query resource properties by specifying the property name for Prop in the -fpgaPropertiesGet[Prop]() and fpgaPropertiesSet[Prop]() functions. The FPGA and Accelerator -columns state whether or not the Property is available for the FPGA or Accelerator objects.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PropertyFPGAAcceleratorDescription
ParentNoYesfpga_token of the parent object
ObjectTypeYesYesThe type of the resource: either FPGA_DEVICE or FPGA_ACCELERATOR
BusYesYesThe bus number
DeviceYesYesThe PCI device number
FunctionYesYesThe PCI function number
SocketIdYesYesThe socket ID
DeviceIdYesYesThe device ID
NumSlotsYesNoNumber of AFU slots available on an FPGA_DEVICE resource
BBSIDYesNoThe FPGA Interface Manager (FIM) ID of an FPGA_DEVICE resource
BBSVersionYesNoThe FIM version of an FPGA_DEVICE resource
VendorIdYesNoThe vendor ID of an FPGA_DEVICE resource
GUIDYesYesThe GUID of an FPGA_DEVICE or FPGA_ACCELERATOR resource
NumMMIONoYesThe number of MMIO space of an FPGA_ACCELERATOR resource
NumInterruptsNoYesThe number of interrupts of an FPGA_ACCELERATOR resource
AcceleratorStateNoYesThe state of an FPGA_ACCELERATOR resource: either FPGA_ACCELERATOR_ASSIGNED or FPGA_ACCELERATOR_UNASSIGNED
-

OPAE C API Return Codes

-

The OPAE C library returns a code for every exported public API function. FPGA_OK indicates successful completion -of the requested operation. Any return code other than FPGA_OK indicates an error or unexpected -behavior. When using the OPAE C API, always check the API return codes.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Error CodeDescription
FPGA_OKOperation completed successfully
FPGA_INVALID_PARAMInvalid parameter supplied
FPGA_BUSYResource is busy
FPGA_EXCEPTIONAn exception occurred
FPGA_NOT_FOUNDA required resource was not found
FPGA_NO_MEMORYNot enough memory to complete operation
FPGA_NOT_SUPPORTEDRequested operation is not supported
FPGA_NO_DRIVERDriver is not loaded
FPGA_NO_DAEMONFPGA Daemon (fpgad) is not running
FPGA_NO_ACCESSInsufficient privileges or permissions
FPGA_RECONF_ERRORError while reconfiguring FPGA
-

Usage Models

-

Query and Search for a Resource

-

The user-code first populates an fpga_properties object with the required properties. -Then, fpgaEnumerate() searches for matching resources. fpgaEnumerate() may return more -than one matching resource.

-
#include "fpga/fpga.h"
-
-fpga_guid               guid;
-fpga_properties         filter = NULL;
-fpga_result             res;
-fpga_token              tokens[MAX_NUM_TOKENS];
-uint32_t                num_matches = 0;
-
-/* Start with an empty properties object */
-res = fpgaGetProperties(NULL, &filter);
-
-/* Populate the properties object with required values.
-   In this case, search for accelerators that matches 
-   the specified GUID.
-*/
-uuid_parse(GUID, guid);
-res = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR);
-res = fpgaPropertiesSetGuid(filter, guid);
-
-/* Query the number of matching resources */
-res = fpgaEnumerate(&filter, 1, NULL, 1, &num_matches);
-
-/* Return tokens for all matching resources */
-res = fpgaEnumerate(&filter, 1, tokens, num_matches, &num_matches);
-
-/* Destroy the properties object */
-res = fpgaDestroyProperties(&filter);
-
-/* More code */
-......
-
-/* Destroy tokens */
-for (uint32_t i = 0; i < num_matches; ++i) {
-    res = fpgaDestroyToken(tokens[i]);
-}
-
-

The fpgaEnumerate() function can take multiple fpga_propertiesobjects in an array. In such cases, -the function performs a logical OR of the properties object and returns resources that match any of -the multiple properties. The fpga_token objects that fpgaEnumerate() returns, do not signify -ownership. To acquire ownership of a resource represented by a token, pass the token to fpgaOpen().

-

Acquire and Release a Resource

-

Use fpgaOpen() and fpgaClose() to acquire and release ownership of a resource. -The calling process must own the resource before it can initiate MMIO, access share memory buffers, -and use functions offered by the resource.

-
    #include "fpga/fpga.h"
-
-    fpga_handle             handle;
-    fpga_result             res;
-
-    /* Acquire ownership of a resource that 
-    `fpgaEnumerate()` previously returned as a token */
-
-    res = fpgaOpen(token, &handle);
-
-    /* More code */
-    ......
-
-    /* Release the ownership */
-    res = fpgaClose(handle);
-
-

Shared Memory Buffer

-

This code snippet shows how to prepare a memory buffer to be shared between the -calling process and an accelerator.

-
    #include "fpga/fpga.h"
-
-    fpga_handle             handle;
-    fpga_result             res;
-
-    /* Hint for the virtual address of the buffer */
-    volatile uint64_t       *addr_hint;
-    /* An ID we can use to reference the buffer later */
-    uint32_t                bufid;
-    /* Flag to indicate whether or not the buffer is preallocated */
-    int                     flag = 0;
-
-    /* Allocate (if necessary), pin, and map a buffer to be accessible
-       by an accelerator
-    */
-    res = fpgaPrepareBuffer(handle, BUF_SIZE, (void **) &addr_hint,
-                            &bufid, flag);
-
-    /* The actual address mapped to the buffer */
-    uint64_t                iova;
-    /* Get the IO virtual address for the buffer */
-    res = fpgaGetIOAddress(handle, bufid, &iova);
-
-    /* Inform the accelerator about the virtual address by writing to its mapped
-       register file
-    */
-    ......
-
-    /* More code */
-    ......
-
-    /* Release the shared buffer */
-    res = fpgaReleaseBuffer(handle, bufid);
-
-

.. note::

-
The `flag` variable can take a constant `FPGA_BUF_PREALLOCATED` to
-indicate that the calling process has already allocated the address space
-that `addr_hint` points to.
-
-

MMIO

-

This code snippet shows how to map and unmap the register file of an accelerator into the -calling process's virtual memory space.

-
    #include "fpga/fpga.h"
-
-    fpga_handle             handle;
-    fpga_result             res;
-
-    /* Index of the MMIO space. There might be multiple spaces on an accelerator */
-    uint32_t                mmio_num = 0;
-    /* Mapped address */
-    uint64_t                mmio_addr;
-
-    /* Map MMIO */
-    res = fpgaMapMMIO(handle, mmio_num, &mmio_addr);
-
-    /* Write to a 32-bit value to the mapped register file at a certain byte
-       offset.
-
-       CSR_CTL is the offset in the mapped space to where the value will be
-       written. It's defined elsewhere.
-    */
-    res = fpgaWriteMMIO32(handle, mmio_num, CSR_CTL, value);
-
-    /* More code */
-    ......
-
-    /* Unmap MMIO */
-    res = fpgaUnmapMMIO(handle, mmio_num);
-
-

.. Note::

-
Every AFU has its own register adress space and its own protocol to control operation through 
-the registers. 
-
- - - - - - -
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Quick Start Guide

-

Overview

-

The OPAE C library is a lightweight user-space library that provides -an abstraction for FPGA resources in a compute environment. Built on top of the -OPAE Intel® FPGA driver stack that supports Intel® FPGA platforms, the library -abstracts away hardware-specific and OS-specific details and exposes the -underlying FPGA resources as a set of features accessible from within -software programs running on the host.

-

These features include the acceleration logic preconfigured on the -device, as well as functions to manage and reconfigure the -device. Hence, the library can enable user applications to -transparently and seamlessly leverage FPGA-based acceleration.

-

In this document, we will explore the initial steps on how to set up -the required libraries and utilities to use the FPGA devices.

-

If you do not have access to an Intel® Xeon® processor with integrated -FPGA, or a programmable FPGA acceleration card for Intel® Xeon® -processors, you will not be able to run the examples below. However, you can -still make use of the AFU simulation environment (ASE) to develop and test -accelerator RTL with OPAE applications.

-

The source for the OPAE SDK Linux device drivers is available at the -OPAE Linux DFL drivers repository.

-

Build the OPAE Linux device drivers from the source

-

For building the OPAE kernel and kernel driver, the kernel development environment is required. So before you build the kernel, you must install the required packages. Run the following commands (we are using Fedora 32 as an example):

-
sudo yum install gcc gcc-c++ make kernel-headers kernel-devel elfutils-libelf-devel ncurses-devel openssl-devel bison flex
-
-

Download the OPAE upstream kernel tree from GitHub:

-
git clone https://github.com/OPAE/linux-dfl.git -b fpga-upstream-dev-5.8.0
-
-

Configure the kernel:

-
cd linux-dfl
-cp /boot/config-`uname -r` .config
-cat configs/n3000_d5005_defconfig >> .config 
-echo 'CONFIG_LOCALVERSION="-dfl"' >> .config
-echo 'CONFIG_LOCALVERSION_AUTO=y' >> .config
-make olddefconfig
-
-

Compile and install the new kernel:

-
make -j
-sudo make modules_install
-sudo make install
-
-

After the installation finishes, reboot your system. -Log back into the system, and confirm the correct version for the kernel:

-
$ uname -a
-Linux localhost.localdomain 5.8.0-rc1-dfl-g73e16386cda0 #6 SMP Wed Aug 19 08:38:32 EDT 2020 x86_64 x86_64 x86_64 GNU/Linux
-
-

Building and installing the OPAE SDK from the source

-

Download the OPAE SDK source package:

-
    -
  1. Go to the section corresponding to the desired release on -GitHub:
    2. -
  2. Click the Source code (tar.gz) link under the section's Assets.
    3. -
  3. -

    On the command line, go through the following steps to install it:

    -
    # Unpack
-tar xfvz opae-sdk-<release>.tar.gz
-# Configure
-cd opae-sdk-<release>
-mkdir build
-cd build
-# The default installation prefix is `/usr/local`;
-# You have the option to configure for a different location
-cmake [-DCMAKE_INSTALL_PREFIX=<prefix>] ..
-# Compile
-make
-# Install: you need system administration privileges (`sudo`)
-# if you have elected to install in the default location
-[sudo] make install
-
    -
    4. -
-

The remainder of this guide assumes you installed into /usr/local.

-

Configuring the FPGA (loading an FPGA AFU)

-

The fpgaconf tool exercises the AFU reconfiguration -functionality. It shows how to read a bitstream from a disk file, -check its validity and compatibility, and then injects it into FPGA to -be configured as a new AFU, which can then be discovered and used by -user applications.

-

For this step, you require a valid green bitstream (GBS) file. To -reconfigure the FPGA slot, you can issue the following command as system -administrator:

-
sudo fpgaconf -b 0x5e <filename>.gbs
-
-

The -b option to fpgaconf indicates the target bus number of the -FPGA slot to be reconfigured. Alternatively, you can also specify the -target socket number of the FPGA using the -s option.

-
$ sudo fpgaconf --help
-Usage:
-        fpgaconf [-hvn] [-b <bus>] [-d <device>] [-f <function>] [-s <socket>] <gbs>
-
-                -h,--help           Print this help
-                -v,--verbose        Increase verbosity
-                -n,--dry-run        Don't actually perform actions
-                -b,--bus            Set target bus number
-                -d,--device         Set target device number
-                -f,--function       Set target function number
-                -s,--socket         Set target socket number
-
-
The sample application on the Building a Sample Application
-section requires loading of an AFU called "Native Loopback
-Adapter" (NLB) on the FPGA. Please refer to the NLB documentation
-for the location of the NLB's green bitstream. You also can verify
-if the NLB green bitstream has already been loaded into the FPGA
-slot by typing the following command and checking the output
-matches the following:
-
-```bash
-$ cat /sys/class/fpga_region/region0/dfl-port.0/afu_id
-d8424dc4a4a3c413f89e433683f9040b
-```
-
-
The fpgaconf tool is not available for the Intel PAC N3000. The NLB is
-already included in the AFU.
-
-

Building a sample application

-

The library source includes code samples. Use these samples to learn -how to call functions in the library. Build and run these samples as -quick sanity checks to determine if your installation and environment -are set up properly.

-

In this guide, we will build hello_fpga.c. This is the "Hello -World!" example of using the library. This code searches for a -predefined and known AFU called "Native Loopback Adapter" on the -FPGA. If found, it acquires ownership and then interacts with the AFU -by sending it a 2MB message and waiting for the message to be echoed -back. This code exercises all major components of the API except for -AFU reconfiguration: AFU search, enumeration, access, MMIO, and memory -management.

-

You can also find the source for hello_fpga in the samples directory of the -OPAE SDK repository on GitHub.

-
    int main(int argc, char *argv[])
-    {
-        fpga_properties    filter = NULL;
-        fpga_token         afu_token;
-        fpga_handle        afu_handle;
-        fpga_guid          guid;
-        uint32_t           num_matches;
-
-        volatile uint64_t *dsm_ptr    = NULL;
-        volatile uint64_t *status_ptr = NULL;
-        volatile uint64_t *input_ptr  = NULL;
-        volatile uint64_t *output_ptr = NULL;
-
-        uint64_t        dsm_wsid;
-        uint64_t        input_wsid;
-        uint64_t        output_wsid;
-        fpga_result     res = FPGA_OK;
-
-        if (uuid_parse(NLB0_AFUID, guid) < 0) {
-            fprintf(stderr, "Error parsing guid '%s'\n", NLB0_AFUID);
-            goto out_exit;
-        }
-
-        /* Look for accelerator by its "afu_id" */
-        res = fpgaGetProperties(NULL, &filter);
-        ON_ERR_GOTO(res, out_exit, "creating properties object");
-
-        res = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR);
-        ON_ERR_GOTO(res, out_destroy_prop, "setting object type");
-
-        res = fpgaPropertiesSetGuid(filter, guid);
-        ON_ERR_GOTO(res, out_destroy_prop, "setting GUID");
-
-        /* TODO: Add selection via BDF / device ID */
-
-        res = fpgaEnumerate(&filter, 1, &afu_token, 1, &num_matches);
-        ON_ERR_GOTO(res, out_destroy_prop, "enumerating accelerators");
-
-        if (num_matches < 1) {
-            fprintf(stderr, "accelerator not found.\n");
-            res = fpgaDestroyProperties(&filter);
-            return FPGA_INVALID_PARAM;
-        }
-
-        /* Open accelerator and map MMIO */
-        res = fpgaOpen(afu_token, &afu_handle, 0);
-        ON_ERR_GOTO(res, out_destroy_tok, "opening accelerator");
-
-        res = fpgaMapMMIO(afu_handle, 0, NULL);
-        ON_ERR_GOTO(res, out_close, "mapping MMIO space");
-
-        /* Allocate buffers */
-        res = fpgaPrepareBuffer(afu_handle, LPBK1_DSM_SIZE,
-                    (void **)&dsm_ptr, &dsm_wsid, 0);
-        ON_ERR_GOTO(res, out_close, "allocating DSM buffer");
-
-        res = fpgaPrepareBuffer(afu_handle, LPBK1_BUFFER_ALLOCATION_SIZE,
-                   (void **)&input_ptr, &input_wsid, 0);
-        ON_ERR_GOTO(res, out_free_dsm, "allocating input buffer");
-
-        res = fpgaPrepareBuffer(afu_handle, LPBK1_BUFFER_ALLOCATION_SIZE,
-                   (void **)&output_ptr, &output_wsid, 0);
-        ON_ERR_GOTO(res, out_free_input, "allocating output buffer");
-
-        printf("Running Test\n");
-
-        /* Initialize buffers */
-        memset((void *)dsm_ptr,    0,    LPBK1_DSM_SIZE);
-        memset((void *)input_ptr,  0xAF, LPBK1_BUFFER_SIZE);
-        memset((void *)output_ptr, 0xBE, LPBK1_BUFFER_SIZE);
-
-        cache_line *cl_ptr = (cache_line *)input_ptr;
-        for (uint32_t i = 0; i < LPBK1_BUFFER_SIZE / CL(1); ++i) {
-            cl_ptr[i].uint[15] = i+1; /* set the last uint in every cacheline */
-        }
-
-        /* Reset accelerator */
-        res = fpgaReset(afu_handle);
-        ON_ERR_GOTO(res, out_free_output, "resetting accelerator");
-
-        /* Program DMA addresses */
-        uint64_t iova;
-        res = fpgaGetIOAddress(afu_handle, dsm_wsid, &iova);
-        ON_ERR_GOTO(res, out_free_output, "getting DSM IOVA");
-
-        res = fpgaWriteMMIO64(afu_handle, 0, CSR_AFU_DSM_BASEL, iova);
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_AFU_DSM_BASEL");
-
-        res = fpgaWriteMMIO32(afu_handle, 0, CSR_CTL, 0);
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG");
-        res = fpgaWriteMMIO32(afu_handle, 0, CSR_CTL, 1);
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG");
-
-        res = fpgaGetIOAddress(afu_handle, input_wsid, &iova);
-        ON_ERR_GOTO(res, out_free_output, "getting input IOVA");
-        res = fpgaWriteMMIO64(afu_handle, 0, CSR_SRC_ADDR, CACHELINE_ALIGNED_ADDR(iova));
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_SRC_ADDR");
-
-        res = fpgaGetIOAddress(afu_handle, output_wsid, &iova);
-        ON_ERR_GOTO(res, out_free_output, "getting output IOVA");
-        res = fpgaWriteMMIO64(afu_handle, 0, CSR_DST_ADDR, CACHELINE_ALIGNED_ADDR(iova));
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_DST_ADDR");
-
-        res = fpgaWriteMMIO32(afu_handle, 0, CSR_NUM_LINES, LPBK1_BUFFER_SIZE / CL(1));
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_NUM_LINES");
-        res = fpgaWriteMMIO32(afu_handle, 0, CSR_CFG, 0x42000);
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG");
-
-        status_ptr = dsm_ptr + DSM_STATUS_TEST_COMPLETE/8;
-
-        /* Start the test */
-        res = fpgaWriteMMIO32(afu_handle, 0, CSR_CTL, 3);
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG");
-
-        /* Wait for test completion */
-        while (0 == ((*status_ptr) & 0x1)) {
-            usleep(100);
-        }
-
-        /* Stop the device */
-        res = fpgaWriteMMIO32(afu_handle, 0, CSR_CTL, 7);
-        ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG");
-
-        /* Check output buffer contents */
-        for (uint32_t i = 0; i < LPBK1_BUFFER_SIZE; i++) {
-            if (((uint8_t*)output_ptr)[i] != ((uint8_t*)input_ptr)[i]) {
-                fprintf(stderr, "Output does NOT match input "
-                    "at offset %i!\n", i);
-                break;
-            }
-        }
-
-        printf("Done Running Test\n");
-
-        /* Release buffers */
-    out_free_output:
-        res = fpgaReleaseBuffer(afu_handle, output_wsid);
-        ON_ERR_GOTO(res, out_free_input, "releasing output buffer");
-    out_free_input:
-        res = fpgaReleaseBuffer(afu_handle, input_wsid);
-        ON_ERR_GOTO(res, out_free_dsm, "releasing input buffer");
-    out_free_dsm:
-        res = fpgaReleaseBuffer(afu_handle, dsm_wsid);
-        ON_ERR_GOTO(res, out_unmap, "releasing DSM buffer");
-
-        /* Unmap MMIO space */
-    out_unmap:
-        res = fpgaUnmapMMIO(afu_handle, 0);
-        ON_ERR_GOTO(res, out_close, "unmapping MMIO space");
-
-        /* Release accelerator */
-    out_close:
-        res = fpgaClose(afu_handle);
-        ON_ERR_GOTO(res, out_destroy_tok, "closing accelerator");
-
-        /* Destroy token */
-    out_destroy_tok:
-        res = fpgaDestroyToken(&afu_token);
-        ON_ERR_GOTO(res, out_destroy_prop, "destroying token");
-
-        /* Destroy properties object */
-    out_destroy_prop:
-        res = fpgaDestroyProperties(&filter);
-        ON_ERR_GOTO(res, out_exit, "destroying properties object");
-
-    out_exit:
-        return res;
-
-    }
-
-

Linking with the OPAE library is straightforward. Code using this library -should include the header file fpga.h. Taking the GCC compiler on -Linux as an example, the minimalist compile and link line should look -like:

-
gcc -std=c99 hello_fpga.c -I/usr/local/include -L/usr/local/lib -lopae-c -luuid -ljson-c -lpthread -o hello_fpga
-
-
The API uses some features from the C99 language standard. The
-`-std=c99` switch is required if the compiler does not support C99 by
-default.
-
-
Third-party library dependency: The library internally uses
-`libuuid` and `libjson-c`. But they are not distributed as part of the
-library. Make sure you have these libraries properly installed.
-
-
The layout of AFU is different between the N3000 card and Rush Creek/Darby Creek.
-In the N3000 card, the NLB and DMA are contained in the AFU, so we need to do
-enumeration again in AFU to discover the NLB.
-To run the hello_fpga application on the N3000 card, it should use the `-c`
-option to support the N3000 card:
-
-```bash
-$ sudo ./hello_fpga -c
-Running Test
-Running on bus 0x08.
-AFU NLB0 found @ 28000
-Done Running Test
-```
-
-

To run the hello_fpga application; just issue:

-
$ sudo ./hello_fpga
-Running Test
-Done
-
-

Setup IOFS Release1 Bitstream on FPGA PCIe card

-

Program IOFS Release1 bitstream on the FPGA D5005 or N6000 cards and reboot the system.

-

Run this command:

-
$ lspci | grep acc
-3b:00.0 Processing accelerators: Intel Corporation Device af00 (rev 01)
-
-

Number of virtual functions supported by bitstream:

-
$ cat /sys/bus/pci/devices/0000:3b:00.0/sriov_totalvfs 
-output: 3
-
-

Enable FPGA virtual functions:

-
sudo sh -c "echo 3 > /sys/bus/pci/devices/0000:3b:00.0/sriov_numvfs"
-
-

List of FPGA PF and VF's:

-
Physical Functions (PFs):
-  3b:00.0 Processing accelerators: Intel Corporation Device af00 (rev 01)
-
-Virtual Functions (VFs).
-  3b:00.1 Processing accelerators: Intel Corporation Device af01 (rev 01)
-  3b:00.2 Processing accelerators: Intel Corporation Device af01 (rev 01)
-  3b:00.3 Processing accelerators: Intel Corporation Device af01 (rev 01)
-
-

Bind vfio-pcie driver to FPGA virtual functions:

-
sudo opaevfio  -i 0000:3b:00.1 -u userid -g groupid
-sudo opaevfio  -i 0000:3b:00.2 -u userid -g groupid
-sudo opaevfio  -i 0000:3b:00.3 -u userid -g groupid
-
-

List of fpga accelerators:

-
$ fpgainfo port
-
-  //****** PORT ******//
-  Object Id                        : 0x600D000000000000
-  PCIe s:b:d.f                     : 0000:3b:00.3
-  Device Id                        : 0xAF00
-  Socket Id                        : 0xFF
-  Accelerator Id                   : 43425ee6-92b2-4742-b03a-bd8d4a533812
-  Accelerator GUID                 : 43425ee6-92b2-4742-b03a-bd8d4a533812
-  //****** PORT ******//
-  Object Id                        : 0x400D000000000000
-  PCIe s:b:d.f                     : 0000:3b:00.2
-  Device Id                        : 0xAF00
-  Socket Id                        : 0xFF
-  Accelerator Id                   : 8568AB4E-6bA5-4616-BB65-2A578330A8EB
-  Accelerator GUID                 : 8568AB4E-6bA5-4616-BB65-2A578330A8EB
-  //****** PORT ******//
-  Object Id                        : 0x200D000000000000
-  PCIe s:b:d.f                     : 0000:3b:00.1
-  Device Id                        : 0xAF00
-  Socket Id                        : 0xFF
-  Accelerator Id                   : 56e203e9-864f-49a7-b94b-12284c31e02b
-  Accelerator GUID                 : 56e203e9-864f-49a7-b94b-12284c31e02b
-
-FPGA VF1/3b:00.1/Host Exerciser Loopback Accelerator GUID: 56E203E9-864F-49A7-B94B-12284C31E02B
-FPGA VF2/3b:00.2/Host Exerciser Memory Accelerator GUID: 8568AB4E-6bA5-4616-BB65-2A578330A8EB
-FPGA VF3/3b:00.3/Host Exerciser HSSI Accelerator GUID: 43425ee6-92b2-4742-b03a-bd8d4a533812
-
-

Unbind pcie-vfio dirver to FPGA virtual functions:

-
sudo opaevfio  -r 0000:3b:00.1
-
-

Host Exerciser Loopback (HE-LBK) AFU can move data between host memory and FPGA:

-
$ host_exerciser lpbk
-
-  [lpbk] [info] starting test run, count of 1
-  Input Config:0
-  Allocate SRC Buffer
-  Allocate DST Buffer
-  Allocate DSM Buffer
-  Start Test
-  Test Completed
-  Host Exerciser swtest msg:0
-  Host Exerciser numReads:32
-  Host Exerciser numWrites:32
-  Host Exerciser numPendReads:0
-  Host Exerciser numPendWrites:0
-  [lpbk] [info] Test lpbk(1): PASS
-
-
  In order to successfully run hello\_fpga, the user needs to configure
-  system hugepage to reserve 2M-hugepages.
-  For example, the command below reserves 20 2M-hugepages:
-
-  ```bash
-  echo 20 | sudo tee /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages
-  ```
-
-  For x86_64 architecture CPU, user can use the following command to find out available huge page sizes:
-
-  ```bash
-  $ grep pse /proc/cpuinfo | uniq
-  flags : ... pse ...
-  ```
-
-  If this command returns a non-empty string, 2MB pages are supported:
-
-  ```bash
-  $ grep pse /proc/cpuinfo | uniq
-  flags : ... pdpe1gb ...
-  ```
-
-  If this commands returns a non-empty string, 1GB pages are supported.
-  ````
-
-````{note}
-The default configuration for many Linux distributions currently sets a
-relatively low limit for pinned memory allocations per process 
-(RLIMIT_MEMLOCK, often set to a default of 64kiB).
-
-To run an OPAE application that attempts to share more memory than specified
-by this limit between software and an accelerator, you can either:
-
-* Run the application as root, or
-* Increase the limit for locked memory via `ulimit`:
-
-```bash
-ulimit -l unlimited
-```
-
-See the Installation Guide for how to permanently adjust the memlock limit.
-
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- - - - - - - -

Enable OPAE on FPGA PCIe drivers

-
.. toctree::
-.. highlight:: c
-.. highlight:: console
-
-

FPGA PCIe driver for PCIe-based Field-Programmable Gate Array (FPGA) solutions which implement -the Device Feature List (DFL). This driver provides interfaces for user space applications to -configure, enumerate, open and access FPGA accelerators on the FPGA DFL devices. additionally, it -also enables system level management functions such as FPGA partial reconfiguration, power management, -virtualization with DFL framework and DFL feature device drivers.

-

OPAE 1.4.0 release supports both FPGA Intel Linux driver as well as Linux FPGA DFL driver patch set2. -Linux PCIe FPGA DFL driver supports Intel FPGA devices.

-

FPGA DFL Linux driver source code patchset2 available -https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers?h=linux-5.4.y

-

FPGA DFL Linux driver source code patchset1 available -https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=v4.19.14

-

FPGA PCIe driver Architecture

- - - - - - -
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coreidle

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coreidle [-v] [-B <bus>] [-D <device>] [-F <function>] [-S <socket>] [-G <GBS path>]

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DESCRIPTION

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coreidle parses the Accelerator Function Unit (AFU) metadata and extracts power information. coreidle calculates -the FPGA power and calculates the number of online and idle cores. It moves threads from idle cores to online cores. -coreidle is only available the Integrated FPGA Platform. You cannot run coreidle on the PCIe Accelerator Card (PAC).

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EXAMPLES

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./coreidle -B 0x5e -G /home/lab/gbs/mode0.gbs

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Idle cores to run online cores at maximum capacity.

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OPTIONS

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-v,--version Prints version information and exit.

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-B,--bus FPGA bus number.

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-D,--device FPGA device number.

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-F,--functio FPGA function number.

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-S,--socket FPGA socket number.

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-G,--gbs Green bitstream file path.

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fecmode (N3000 specific tool)

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SYNOPSIS

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fecmode [<mode>][<args>]
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DESCRIPTION

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Fecmode changes FEC mode of external ethernet PHY, this tool only support on N3000 Card.

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POSITIONAL ARGUMENTS

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--segment, -S

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segment number of the PCIe device.

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--bus, -B

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bus number of the PCIe device.

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--device, -D

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device number of the PCIe device.

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--function, -F -function number of the PCIe device

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--rsu, -r -reboot card only if mode is not configured

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--debug, -d -output debug information

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FEC Mode

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no -no FEC.

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kr -BaseR FEC (Fire-Code) correction – 4 orders

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rs -Reed-Solomon FEC correction – 7 orders

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This command change FEC mode to “kr”: -

# fecmode -B 0x25 kr
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This command reboot card (no need to specify bus number if there is only one card): -

# fecmode -r
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# fecmode
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fpgabist

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SYNOPSIS

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fpgabist [-h] [-i device_id] [-b bus] [-d device] [-f function] [path_to_gbs1 path_to_gbs2 ...]
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DESCRIPTION

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The fpgabist tool performs self-diagnostic tests on supported FPGA platforms.

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The tool accepts one or more Accelerator Function (AF) binaries from a predetermined set of AFs. Depending on the available binaries, -the tool runs appropriate tests and reports hardware issues.

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fpgabist always uses fpgainfo to report system information before running any hardware tests.

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Currently, fpgabist accepts the following AFs: - 1. nlb_mode_3: The native loopback (NLB) test implements a loopback from TX to RX. Use it to verify basic functionality - and to measure bandwidth. - 2. dma_afu: The direct memory access (DMA) AFU test transfers data from host memory to FPGA-attached local memory.

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The installation includes the AF files, but you can also compile the AFs from the source.

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If there are multiple PCIe® devices, use -b, -d, -f to specify the BDF for the specific PCIe® device.

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POSITIONAL ARGUMENTS

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[path_to_gbs1 path_to_gbs2 ...]

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Paths to Accelerator Function (AF) files.

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OPTIONAL ARGUMENTS

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You can use the single letter or the full parameter name for the command line arguments.

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-h, --help

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Prints usage information

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-i device_id, --device-id device_id

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Device ID for Intel FPGA. Default is: 0x09c4

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-B bus, --bus bus

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Bus number for specific FPGA

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-D device, --device device

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Device number for specific FPGA

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-F function, --function function

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Function number for specific FPGA

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EXAMPLES

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fpgabist <path_to_gbs_files>/dma_afu.gbs <path_to_gbs_files>/nlb_3.gbs

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Runs fpgabist on any platform in the system that matches the default device ID. This command runs both the DMA and - NLB_MODE_3 tests.

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fpgabist -i 09c4 -b 5 <path to gbs>/dma_afu.gbs

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Runs fpgabist the DMA test on the PCIe® Endpoint with device_id 09c4 on bus 5.

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fpgaconf

-

SYNOPSIS

-

fpgaconf [-hvVn] [-S <segment>] [-B <bus>] [-D <device>] [-F <function>] [PCI_ADDR] <gbs>

-

DESCRIPTION

-

fpgaconf configures the FPGA with the accelerator function (AF). It also checks the AF for compatibility with -the targeted FPGA and the FPGA Interface Manager (FIM). fpgaconf takes the following arguments:

-

-h, --help

-
Prints usage information.
-
-

-v, --version

-
Prints version information and exits.
-
-

-V, --verbose

-
Prints more verbose messages while enumerating and configuring. Can be
-requested more than once.
-
-

-n, --dry-run

-
Performs enumeration. Skips any operations with side-effects such as the
-actual AF configuration.
-
-

-S, --segment

-
PCIe segment number of the target FPGA.
-
-

-B, --bus

-
PCIe bus number of the target FPGA.
-
-

-D, --device

-
PCIe device number of the target FPGA.
-
-

-F, --function

-
PCIe function number of the target FPGA.
-
-

--force

-
Reconfigure the AFU even if it is in use.
-
-

fpgaconf enumerates available FPGA devices in the system and selects -compatible FPGAs for configuration. If more than one FPGA is -compatible with the AF, fpgaconf exits and asks you to be -more specific in selecting the target FPGAs by specifying a -a PCIe BDF.

-

EXAMPLES

-

fpgaconf my_af.gbs

-
Program "my_af.gbs" to a compatible FPGA.
-
-

fpgaconf -V -B 0x3b my_af.gbs

-
Program "my_af.gbs" to the FPGA in bus 0x3b, if compatible,
-while printing out slightly more verbose information.
-
-

fpgaconf 0000:3b:00.0 my_af.gbs

-
Program "my_af.gbs" to the FPGA at address 0000:3b:00.0.
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fpgad

-

SYNOPSIS

-

fpgad --daemon [--version] [--directory=<dir>] [--logfile=<file>] [--pidfile=<file>] [--umask=<mode>] [--socket=<sock>] [--null-bitstream=<file>] -fpgad [--socket=<sock>] [--null-bitstream=<file>]

-

DESCRIPTION

-

fpgad monitors the device sensors, checking for sensor values that are out of the prescribed range.

-

When any of the sensors is detected to be out of bounds, fpgad will focus on keeping the server from rebooting by masking PCIE AER, and send a message to system administrator. System administrator can take further actions like stop the application and stop the FPGA, but fpgad just focus on monitor the sensors and will not take any cooling actions.

-

Note: fpgad must be running (as root) and actively monitoring devices when a sensor anomaly occurs in order to initiate Graceful Shutdown. If fpgad is not loaded during such a sensor anomaly, the out-of-bounds scenario will not be detected, and the resulting effect on the hardware is undefined.

-

ARGUMENTS

-

-v, --version

-
Prints version information and exits.
-
-

-d, --daemon

-
When specified, fpgad executes as a system daemon process.
-
-

-D, --directory <dir>

-
When running in daemon mode, run from the specified directory.
-If omitted when daemonizing, `fpgad` uses /tmp.
-
-

-l, --logfile <file>

-
When running in daemon mode, send output to file. When not in daemon mode, the output goes to stdout.
-If omitted when daemonizaing, fpgad uses /tmp/fpgad.log.
-
-

-p, --pidfile <file>

-
When running in daemon mode, write the daemon's process id to a file.
-If omitted when daemonizing, fpgad uses /tmp/fpgad.pid.
-
-

-m, --umask <mode>

-
When running in daemon mode, use the mode value as the file mode creation mask passed to umask.
-If omitted when daemonizing, fpgad uses 0.
-
-

-s, --socket <sock>

-
Listen for event API registration requests on the UNIX domain socket on the specified path. 
-The default=/tmp/fpga_event_socket.
-
-

-n, --null-bitstream <file>

-
Specify the NULL bitstream to program when an AP6 event occurs. This option may be specified multiple
-times. The AF, if any, that matches the FPGA's PR interface ID is programmed when an AP6
-event occurs.
-
-

TROUBLESHOOTING

-

If you encounter any issues, you can get debug information in two ways:

-
    -
  1. By examining the log file when in daemon mode.
    2. -
  2. By running in non-daemon mode and viewing stdout.
    3. -
-

EXAMPLES

-

fpgad --daemon --null-bitstream=my_null_bits.gbs

-

This command starts fpgad as a system daemon process: -

sudo systemctl start fpgad
-

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fpgadiag

-

SYNOPSIS

-
fpgadiag [-m | --mode=] <mode> [-t | --target=] <target> [options]
-
-

DESCRIPTION

-

Includes several tests to diagnose, test, and report on the FPGA hardware.

-

<mode> chooses which test to run. -<target> specifies the platform that runs the test. -<target> can be either fpga or ase where ase. -<ase> is the abbreviation for Accelerator Simulation Environment.

-

The <mode> selects from the following tests:

-

lpbk1

-

This test runs a loopback test on the number of cachelines specified with -the BEGIN option. fpgadiag sets up source and destination buffers in -main memory. The FPGA then performs a memcpy from a source buffer to the -destination buffer, one cacheline at a time.

-

A cacheline is 64 bytes. When BEGIN = END, the test performs one iteration. When -BEGIN = END + x, the test performs x iterations. The first iteration consists -of copying BEGIN cachelines; the second iteration consists of copying -BEGIN+1 cache lines. The third iteration consists of copying BEGIN+2 -cache lines, and so on.

-

The latency is shown as the number of clock cycles.

-

When you specify MULTI-CL, you copy MULTI-CL cache lines at a time. -The WR-FENCE chooses on which virtual channel the WrFence occurs.

-

If you specify continuous mode with --cont, the program iterates -until the timeout specified in TIMEOUT completes.

-

read

-

This test performs reads. Use this test to measure read bandwidth.

-

write

-

This test performs writes. Use it to measure write bandwidth.

-

trput

-

This test measures both read and write bandwidth by performing 50% read and -50% write tests.

-

sw

-

This is a send-and-respond (ping-pong) test. One side sends data and -waits for response.

-

Each test requires a particular AF. Before running a test, -make sure the required AF is properly configured -on the platform.

-
    -
  • The lpbk1 test requires the nlb mode 0 AF.
    • -
  • The trput test requires the nlb mode 3 AF.
    • -
  • The sw test requires the nlb mode 7 AF. This AF is only available for the integrated FPGA platform. - You cannot run it on the PCIe accelerator card (PAC).
    • -
-

fpgalpbk

-

This enable/disable FPGA loopback.

-

fpgastats

-

This get fpga mac statistics.

-

mactest

-

This compare mac addresses that read from MAC ROM with mac addresses read from Host side.

-

OPTIONS

-

Common options

-

--help, -h

-
Print help information and exit.
-
-

--target=, -t

-
This switch specifies fpga (hardware) or ase (simulation). The default=fpga.
-
-

--mode=, -m

-
The test to run. The valid values are `lpbk1`, `read`,
-`write`, `trput`, and `sw`.
-
-

--config=, -c

-
A configuration file in the JSON format that specifies options for a test.
-If an option is specified both in the configuration file and on the command 
-line, the value in the configuration file takes precedence.
-
-

--dsm-timeout-usec

-
Timeout in microseconds for test completion. The test fails if not completed by 
-specified timeout. The default=1000000.
-
-

--socket-id=, -s

-
Socket ID encoded in FPGA Interface Manager (FIM). The default=0.
-
-

--bus=, -B

-
Bus number of the PCIe device. The default=0.
-
-

--device=, -D

-
Device number of the PCIe device. The default=0.
-
-

--function=, -F

-
Function number of the PCIe device. The default=0.
-
-

--freq=, -T

-
Clock frequency (in Hz) used for bandwidth calculation. The default=400000000 Hz (400 MHz).
-
-

eval_rst -.. note:: - This frequency is used only when the software cannot infer the frequency from the accelerator.

-

--suppress-hdr, -S

-
Suppress column headers for text output. The default=off.
-
-

--csv, -V

-
Comma separated value format. The default=off.
-
-

--suppress-stats

-
Suppress statistics output at the end of test. The default=off.
-
-

lpbk1 test options

-

--guid=, -g

-
AFU ID to enumerate. The default=D8424DC4-A4A3-C413-F89E-433683F9040B.
-
-

--begin=B, -b

-
1 <= B <= 65535. The default=1, B = number of cache lines.
-
-

--end=E, -e

-
1 <= E <= 65535. The default=B, B and E designate number of cache lines.
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. The default=1.
-
-

--cont, -L

-
Continuous mode. The default=off.
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode. The default for all options is 0.
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I The default=wrline-M.
-
-

--cache-hint=, -i

-
Can be rdline-I or rdline-S. The default=rdline-I.
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random. The default=auto.
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random. The default=auto.
-
-

--wrfence-vc=, -f

-
Can be auto, vl0, vh0, vh1. The default=auto.
-
-

read test options

-

--guid=, -g

-
AFU ID to enumerate. The default=F7DF405C-BD7A-CF72-22F1-44B0B93ACD18.
-
-

--begin=B, -b

-
1 <= B <= 65535. The default=1, B = number of cache lines.
-
-

--end=E, -e

-
1 <= E <= 65535. The default=B, B and E designate number of cache lines.
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. The default=1.
-
-

--strided-access=S, -a

-
1<= S <= 64. The default=1.
-
-

--cont, -L

-
Continuous mode. The default=off.
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode. The default for all options is 0.
-
-

--cache-hint=, -i

-
Can be rdline-I or rdline-S. The default=rdline-I.
-
-

--warm-fpga-cache -H; --cool-fpga-cache -M

-
Try to prime the cache with hits. The default=off. Try to prime the 
-cache with misses. The default=off.
-
-

--cool-cpu-cache, -C

-
Try to prime the cpu cache with misses. The default=off.
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random. The default=auto
-
-

write test options

-

--guid=, -g

-
AFU ID to enumerate. The default=F7DF405C-BD7A-CF72-22F1-44B0B93ACD18
-
-

--begin=B, -b

-
1 <= E <= 65535. The default=B, B and E designate number of cache lines.
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. The default=1.
-
-

--strided-access=S, -a

-
1<= S <= 64. The default=1.
-
-

--cont, -L

-
Continuous mode. The default=off.
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode. The default for all options is 0.
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I The default=wrline-M
-
-

--warm-fpga-cache -H; --cool-fpga-cache -M

-
Try to prime the cache with hits. The default=off. Try to prime the 
-cache with misses. The default=off.
-
-

--cool-cpu-cache, -C

-
Try to prime the cpu cache with misses. The default=off.
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random. The default=auto.
-
-

--wrfence-vc=, -f

-
Can be auto, vl0, vh0, vh1, random. The default=`WRITE-VC`.
-
-

--alt-wr-pattern, -l

-
Alternate Write Pattern. The default=off.
-
-

trput test options

-

--guid=, -g

-
AFU ID to enumerate. The default=F7DF405C-BD7A-CF72-22F1-44B0B93ACD18.
-
-

--begin=B, -b

-
1 <= B <= 65535. The default=1, B = number of cache lines.
-
-

--end=E, -e

-
1 <= E <= 65535. The default=B, B and E designate number of cache lines.
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. The default=1.
-
-

--strided-access=S, -a

-
1<= S <= 64. The default=1
-
-

--cont, -L

-
Continuous mode. The default=off.
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode. The default for all options is 0.
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I The default=wrline-M.
-
-

--cache-hint=, -i

-
Can be rdline-I or rdline-S. The default=rdline-I.
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random. The default=auto.
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random. The default=auto.
-
-

--wrfence-vc=, -f

-
Can be  auto, vl0, vh0, vh1. The default=`WRITE-VC`.
-
-

sw test options

-

--guid=, -g

-
AFU ID to enumerate. The default=7BAF4DEA-A57C-E91E-168A-455D9BDA88A3.
-
-

--begin=B, -b

-
1 <= B <= 65535. The default=1, B = number of cache lines.
-
-

--end=E, -e

-
1 <= E <= 65535. The default=B, B and E designate number of cache lines.
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I. The default=wrline-M.
-
-

--cache-hint= -i

-
Can be rdline-I or rdline-S. The default=rdline-I.
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random The default=auto.
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random The default=auto.
-
-

--wrfence-vc=, -f

-
Can be auto, vl0, vh0, vh1. The default=`WRITE-VC`.
-
-

--notice=, -N

-
Can be poll or csr-write. The default=poll.
-
-

Enable FPGA N3000 Ethernet group VFIO mdev

-

FPGA DFL driver does not support any ioctls to read/write ethernet group info and registers. -Users can read/write eth group registers by enabling VFIO mdev. Unbind the dfl_eth_group driver and bind vfio-mdev-dfl -driver for ethernet group dfl-device; then userspace can take full control of ethernet group feature id 10.

-

Ethernet group must be enabled before running fpgalpbk, mactest tools.

-

Steps to enable/create vfio mdev

-
unbind eth group feature id 10:
-    echo dfl-fme.0.8 > /sys/bus/dfl/drivers/dfl-eth-group/unbind
-    echo dfl-fme.0.7 > /sys/bus/dfl/drivers/dfl-eth-group/unbind
-bind to vfio-mdev-dfl:
-    echo vfio-mdev-dfl > /sys/bus/dfl/devices/dfl-fme.0.7/driver_override
-    echo vfio-mdev-dfl > /sys/bus/dfl/devices/dfl-fme.0.8/driver_override
-load vfio driver:
-    modprobe vfio_pci
-    modprobe vfio_iommu_type1
-    modprobe vfio_mdev
-    modprobe vfio_mdev_dfl
-trigger mdev:
-    echo dfl-fme.0.7 >/sys/bus/dfl/drivers_probe
-    echo dfl-fme.0.8 >/sys/bus/dfl/drivers_probe
-    echo 83b8f4f2-509f-382f-3c1e-e6bfe0fa1001 > /sys/bus/dfl/devices/dfl-fme.0.7/mdev_supported_types/vfio-mdev-dfl-1/create
-    echo 83b8f4f2-509f-382f-3c1e-e6bfe0fa1002 > /sys/bus/dfl/devices/dfl-fme.0.8/mdev_supported_types/vfio-mdev-dfl-1/create
-
-linux kerenl msg after enabling mdev:
-    i40e 0000:b3:00.0 eth1: NIC Link is Down
-    i40e 0000:b1:00.1 eth0: NIC Link is Down
-    vfio-mdev-dfl dfl-fme.2.7: MDEV: Registered
-    vfio-mdev-dfl dfl-fme.2.8: MDEV: Registered
-    vfio_mdev 83b8f4f2-509f-382f-3c1e-e6bfe0fa1005: Adding to iommu group 140
-    vfio_mdev 83b8f4f2-509f-382f-3c1e-e6bfe0fa1005: MDEV: group_id = 140
-    vfio_mdev 83b8f4f2-509f-382f-3c1e-e6bfe0fa1006: Adding to iommu group 141
-    vfio_mdev 83b8f4f2-509f-382f-3c1e-e6bfe0fa1006: MDEV: group_id = 141
-
-

Remove vfio mdev

-
    echo 1 | sudo tee /sys/bus/mdev/devices/83b8f4f2-509f-382f-3c1e-e6bfe0fa1002/remove
-    echo 1 | sudo tee /sys/bus/mdev/devices/83b8f4f2-509f-382f-3c1e-e6bfe0fa1001/remove
-
-    rmmod vfio_mdev_dfl
-    modprobe dfl_eth_group
-
-    echo dfl-fme.0.7 >/sys/bus/dfl/drivers_probe
-    echo dfl-fme.0.8 >/sys/bus/dfl/drivers_probe
-
-    echo dfl-eth-group > /sys/bus/dfl/devices/dfl-fme.0.7/driver_override
-    echo dfl-eth-group > /sys/bus/dfl/devices/dfl-fme.0.8/driver_override
-
-

fpgalpbk test options

-

--enable

-
Enable fpga phy loopback.
-
-

--disable

-
Disable fpga phy loopback.
-
-

--direction

-
Can be local, remote.
-
-

--type

-
Can be serial, precdr, postcdr.
-
-

--side

-
Can be line, host.
-
-

--port

-
0 <= port <= 7, the default is all.
-
-

mactest test options

-

--offset

-
Read mac addresses from an offset, The default=0.
-
-

EXAMPLES

-

This command starts a lpbk1 test for the FPGA on bus 0x5e. The test -copies 57535, 57536, 57537 ... up to 65535 cache lines, one line at a time. -The test prints output in the comma separated values (CSV) format with the -header suppressed. -

./fpgadiag --mode=lpbk1 --target=fpga -V --bus=0x5e --begin=57535
---end=65535 --cache-hint=rdline-I --cache-policy=wrpush-I --multi-cl=1
---write-vc=vl0 --read-vc=vh1 --wrfence-vc=auto
-

-

This command starts a read test on the FPGA located on bus 0xbe. The test -reads 2045 cache lines in the continuous mode with a 15-second timeout period. -The reads use a strided pattern with a 10-byte stride length. -

./fpgadiag --mode=read --target=fpga -V --bus=0xbe --begin=2045 --cont
---timeout-sec=15 --cache-hint=rdline-I --multi-cl=1 -a=10 
---read-vc=auto --wrfence-vc=auto
-

-

This command starts a sw test on the FPGA located on bus 0xbe. The test -signals completion using a CSR write. -

./fpgadiag --mode=sw --target=fpga -V --bus=0xbe --begin=4 --end=8192
---cache-hint=rdline-I --cache-policy=wrline-I --notice=csr-write --write-vc=vl0
---wrfence-vc=auto --read-vc=random 
-

-

This command enable a fpgalpbk on the FPGA located on bus 0xbe. -

./fpgadiag -m fpgalpbk --bus 0xbe --enable --direction local --type postcdr
---side host
-

-

This command show fpgastats on the FPGA located on bus 0xbe. -

./fpgadiag -m fpgastats --bus 0xbe
-

-

TROUBLESHOOTING

-

When a test fails to run or gives errors, check the following:

-
    -
  • Is the Intel FPGA driver properly installed? -See Installation Guide -for driver installation instructions.
    • -
  • Are FPGA port permissions set properly? Check the permission bits of the -port, for example, /dev/intel-fpga-port-0. You need READ and WRITE -permissions to run fpgadiag tests.
    • -
  • Is hugepage properly configured on the system? -See Installation Guide -for hugepage configuration steps. In particular, fpgadiag requires a few 1 GB -pages.
    • -
  • Is the required AFU loaded? See DESCRIPTION for -information about what AFU the test requires.
    • -
  • Are --begin and --end values set properly? --end must be larger -than the --begin. Also, --begin must be a multiple of the ---multi-cl value.
    • -
  • The --warm-fpga-cache and --cool-fpga-cache options in the read -and write tests are mutually exclusive.
    • -
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- - - - - - - - - \ No newline at end of file diff --git a/sw/fpga_tools/fpgaflash/fpgaflash/index.html b/sw/fpga_tools/fpgaflash/fpgaflash/index.html deleted file mode 100644 index 931a1003b..000000000 --- a/sw/fpga_tools/fpgaflash/fpgaflash/index.html +++ /dev/null @@ -1,1848 +0,0 @@ - - - - - - - - - - - - - - - - - - fpgaflash # - OFS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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fpgaflash

-

SYNOPSIS

-
fpgaflash [-h] {user,factory} file [bdf]
-
-

DESCRIPTION

-

fpgaflash updates the static FIM image loaded from flash at power-on.

-

If there are multiple devices in the system, fpgaflash must specify a BDF to select the correct device. If no BDF is specified, fpgaflash prints out the BDFs of any compatible devices.

-

POSITIONAL ARGUMENTS

-

{user, factory}

-

Specifies the type of flash programming.

-

user

-

Only reprograms the user image in flash.

-

factory

-

Reprograms the entire flash. A catastrophic failure during a factory update such as a power outage - requires a USB cable and quartus_pgm to recover.

-

file

-

Specifies the Raw Programming Data File (rpd) to program into flash.

-

bdf

-

Specifies the bus, device and function (BDF) of device to program such as 04:00.0 or 0000:04:00.0. This flag -is optional when there is a single device in the system.

-

OPTIONAL ARGUMENTS

-

-h, --help

-

Print usage information.

-

EXAMPLE

-

fpgaflash user new_image.rpd 0000:04:00.0

-

Programs new_image.rpd to flash of device with BDF 0000:04:00.0.

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- - - - - - - - - \ No newline at end of file diff --git a/sw/fpga_tools/fpgaflash/superrsu/index.html b/sw/fpga_tools/fpgaflash/superrsu/index.html deleted file mode 100644 index a212fba36..000000000 --- a/sw/fpga_tools/fpgaflash/superrsu/index.html +++ /dev/null @@ -1,2153 +0,0 @@ - - - - - - - - - - - - - - - - - - super-rsu # - OFS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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super-rsu

-

SYNOPSIS

-
super-rsu [-h] [-n] [--verify] | [ [--log-level {trace,debug,error,warn,info,notset}]
-          [--log-file <filename>] [--rsu-only] [--with-rsu] [--force-flash] ]
-      rsu_config
-
-

DESCRIPTION

-

super-rsu is a tool that can be used for flashing image files and commanding an -Intel PAC device to perform RSU (remote system update - or a board reboot). -Performing an RSU on an Intel PAC device will cause it to reload any firmware -or programmable logic and restart its execution, a requirement for any updated -firmware or programmable logic to take effect.

-

At the core of super-rsu is its configuration file (referred to in this -document as 'rsu_config') which is essentially a manifest file for -identifying both the target device and the binary images (and their versions) -to be flashed.

-

At a high level, the flow of super-rsu should be: -1. Read and parse rsu_config file -2. Use product identifiers (like vendor, device and any additional vendor, device - pairs that may be present in the PCIe bus) to locate all compatible - devices on the PCIe bus. -3. For every device found on the system, update the device using the flash - images defined in the "flash" section in the rsu_config data (or nvmupdate - section). - Each item in the "flash" section is a "flash spec" that contains: - * The flash type ("user", "bmc_fw", "bmc_img", ...) - * The filename of the image to flash. super-rsu will look for this file - first in the same directory of the rsu_config file, and then look in the - current working directory. - * The version of the image. - * An optional "force" indicator - * An optional "requires" indicator - The "nvmupdate" section is used to describe an Ethernet firmware file and - its version. -4. Using the data in the "nvmupdate" and "flash" sections, the update routine - involves: - * If an "nvmupdate" section is present: - 1. Locate the file on the file system to use to flash the Ethernet device. - 2. Call nvmupdate to get an "inventory" of devices matching the vendor and - device id in this section. - 3. Use this data to dynamically generate an nvmupdate compatible - configuration file. - 4. Call nvmupdate with the generated configuration file to flash the - Ethernet interfaces in the Vista Creek card (if version reported by - system does not match the version in this section). - * For each spec in the "flash" section: - 1. Locate the file on the file system to use to flash. - 2. Compare the version listed in the "flash spec" to version reported by - the target component. - 3. Create a task to call fpgaflash if either of the following conditions is - met (and the revision specified is compatible): - * The "force" indicator is present and set to true. - * The version in the spec does not match the version reported by the - system OR the flash type is factory type. - * For each task created from the "flash" section: - 1. Call fpgaflash with the command line arguments that correspond to the - flash type and the file name in the spec used to create the task. - This opens and controls the execution of fpgaflash in another process.

-

NOTE: If the system reports a revision for one of the components -being flashed, this revision must be in the set of revisions listed -in the manifest. -Example: if the system reports 'a' for bmc_img and the manifest includes -'ab', then the image will be flashed.

-

NOTE: Each update routine is run in a thread specific to a device located -on the PCIe bus. Every task in an update routine involves opening a new process -that is controlled and managed by its update routine thread. -If a task includes a timeout and the timeout is reached, a termination request -will be sent to its process and it will be counted as a failure. If a global -timeout is reached in the main thread, a termination request will be sent to each -thread performing the update. Consequently, the update routine will give the -current task extra time before terminating the process. -The RSU operation will only be performed if requested with either --with-rsu -command line argument or with the --rsu-only command line argument. -The former will perform the RSU command upon successful completion of flash -operations. The latter will skip the process of version matching and flashing -images and will only perform the RSU command. It is recommended that super-rsu -be executed again if any flash operation is interrupted.

-

POSITIONAL ARGUMENTS

-

rsu config

-

Specifies the name of the file containing the RSU configuration (in JSON -format)

-

OPTIONAL ARGUMENTS

-

-h, --help

-

Print usage information.

-

--verify

-

Compare versions of flashable components on the system against the manifest. - Return non-zero exit if compatible components are not up to date.

-

-n, --dry-run

-

Don't perform any updates, just a dry run. - This will print out commands that can be executed - in a Linux shell.

-

--log-level {trace,debug,error,warn,info,notset}

-

Log level to use. Default is 'info'.

-

`--log-file (default: /tmp/super-rsu.log)

-

Emit log messages (with DEBUG level) to filename - NOTE: The default log file (/tmp/super-rsu.log) is set to rollover every - time super-rsu is executed. This will create numbered backups before - truncating the log file. The maximum number of backups is 50.

-

--rsu-only

-

Only perform the RSU command.

-

--with-rsu

-

Perform RSU after updating flash components(experimental)

-

--force-flash

-

Flash all images regardless of versions matching or not.

-

CONFIGURATION

-

The following is the JSON schema expected by super-rsu. Any deviance from -this schema may result in errors executing super-rsu.

-
{
-  "definitions": {},
-  "$schema": "http://json-schema.org/draft-07/schema#",
-  "$id": "http://example.com/root.json",
-  "type": "object",
-  "title": "The Root Schema",
-  "required": [
-    "product",
-    "vendor",
-    "device",
-    "flash"
-  ],
-  "optional": [
-    "nvmupdate",
-  ],
-  "properties": {
-    "product": {
-      "$id": "#/properties/product",
-      "type": "string",
-      "title": "The Product Schema",
-      "default": "",
-      "examples": [
-        "n3000"
-      ],
-      "pattern": "^(.*)$"
-    },
-    "vendor": {
-      "$id": "#/properties/vendor",
-      "type": "string",
-      "title": "The Vendor Schema",
-      "default": "",
-      "examples": [
-        "0x8086"
-      ],
-      "pattern": "^((0x)?[A-Fa-f0-9]{4})$"
-    },
-    "device": {
-      "$id": "#/properties/device",
-      "type": "string",
-      "title": "The Device Schema",
-      "default": "",
-      "examples": [
-        "0x0b30"
-      ],
-      "pattern": "^((0x)?[A-Fa-f0-9]{4})$"
-    },
-    "nvmupdate": {
-      "$id": "#/properties/nvmupdate",
-      "type": "object",
-      "title": "The nvmupdate Schema",
-      "required": [
-        "vendor",
-        "device",
-        "filename",
-        "version"
-      ],
-      "optional": [
-        "interfaces"
-      ],
-      "properties": {
-        "vendor": {
-          "$id": "#/properties/nvmupdate/vendor",
-          "type": "string",
-          "title": "The nvmupdate Vendor Schema",
-          "default": "",
-          "examples": [
-             "0x8086"
-          ],
-          "pattern": "^((0x)?[A-Fa-f0-9]{4})$"
-        },
-        "device": {
-          "$id": "#/properties/nvmupdate/device",
-          "type": "string",
-          "title": "The nvmupdate Device Schema",
-          "default": "",
-          "examples": [
-            "0x0d58"
-          ],
-          "pattern": "^((0x)?[A-Fa-f0-9]{4})$"
-        },
-        "interfaces": {
-          "$id": "#/properties/nvmupdate/interfaces",
-          "type": "number",
-          "title": "The nvmupdate Interfaces Schema",
-          "default": "1",
-          "examples": [
-            2, 4
-          ]
-        },
-        "filename": {
-          "$id": "#/properties/nvmupdate/filename",
-          "type": "string",
-          "title": "The nvmupdate Filename Schema",
-          "default": "",
-          "examples": [
-            "PSG_XL710_6p80_XLAUI_NCSI_CFGID2p61_Dual_DID_0D58_800049C6.bin"
-          ],
-          "pattern": "^(.*)$"
-        },
-        "version": {
-          "$id": "#/properties/nvmupdate/version",
-          "type": "string",
-          "title": "The nvmupdate Version Schema",
-          "default": "",
-          "examples": [
-            "800049C6"
-          ],
-          "pattern": "^((0x)?[A-Fa-f0-9]{8})$"
-        },
-        "timeout": {
-          "$id": "#/properties/nvmupdate/timeout",
-          "type": "string",
-          "title": "The Timeout Schema",
-          "default": "",
-          "examples": [
-            "10m"
-          ],
-          "pattern": "^([0-9]+(\\.[0-9]+)?([dhms]))+$"
-        }
-      }
-    },
-    "flash": {
-      "$id": "#/properties/flash",
-      "type": "array",
-      "title": "The Flash Schema",
-      "items": {
-        "$id": "#/properties/flash/items",
-        "type": "object",
-        "title": "The Items Schema",
-        "required": [
-          "filename",
-          "type",
-          "version",
-          "revision"
-        ],
-    "optional": [
-          "enabled",
-          "force",
-      "timeout",
-      "requires"
-    ],
-        "properties": {
-      "enabled": {
-            "$id": "#/properties/flash/items/properties/enabled",
-        "type": "boolean",
-        "title": "The Enabled Schema",
-        "default": "true"
-      },
-          "filename": {
-            "$id": "#/properties/flash/items/properties/filename",
-            "type": "string",
-            "title": "The Filename Schema",
-            "default": "",
-            "examples": [
-              "vista_creek_qspi_xip_v1.0.6.ihex"
-            ],
-            "pattern": "^(.*)$"
-          },
-          "type": {
-            "$id": "#/properties/flash/items/properties/type",
-            "type": "string",
-            "title": "The Type Schema",
-            "default": "",
-            "examples": [
-              "bmc_fw"
-            ],
-            "enum": ["user", "bmc_fw", "bmc_img", "dtb", "factory_only",
-        "phy_eeprom"]
-          },
-          "version": {
-            "$id": "#/properties/flash/items/properties/version",
-            "type": "string",
-            "title": "The Version Schema",
-            "default": "",
-            "examples": [
-              "1.0.6"
-            ],
-            "pattern": "^\\d+\\.\\d+\\.\\d+$"
-          },
-          "force": {
-            "$id": "#/properties/flash/items/properties/force",
-            "type": "boolean",
-            "title": "The Force Schema",
-            "default": false,
-            "examples": [
-              true
-            ]
-          },
-          "revision": {
-            "$id": "#/properties/flash/items/properties/revision",
-            "type": "string",
-            "title": "The Revision Schema",
-            "default": "",
-            "examples": [
-              "C"
-            ],
-            "pattern": "^([A-Za-z])$"
-          },
-          "timeout": {
-            "$id": "#/properties/nvmupdate/timeout",
-            "type": "string",
-            "title": "The Timeout Schema",
-            "default": "",
-            "examples": [
-              "10m"
-            ],
-            "pattern": "^([0-9]+(\.[0-9]+)?([dhms]))+$"
-          },
-          "requires": {
-            "$id": "#/properties/flash/items/properties/requires",
-            "type": "string",
-            "title": "The Requires Schema",
-            "default": "",
-            "examples": [
-              "bmc_img >= 1.0.12"
-            ],
-            "pattern": "^(([a-z_]+) ((<>!=)?=) ([0-9a-z\\.]+)$"
-          }
-        }
-      }
-    }
-  }
-}
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fpgainfo

-

SYNOPSIS

-
   fpgainfo [-h] [-S <segment>] [-B <bus>] [-D <device>] [-F <function>] [PCI_ADDR]
-            {errors,power,temp,fme,port,bmc,mac,phy,security}
-
-

DESCRIPTION

-

fpgainfo displays FPGA information derived from sysfs files. The command argument is one of the following: -errors, power, temp, port, fme, bmc, phy or mac,security,events. -Some commands may also have other arguments or options that control their behavior.

-

For systems with multiple FPGA devices, you can specify the BDF to limit the output to the FPGA resource -with the corresponding PCIe configuration. If not specified, information displays for all resources for -the given command.

-

FPGAINFO COMMANDS

-

errors

-

Show/clear errors of an FPGA resource that the first argument specifies. -fpgainfo displays information in human readable form.

-

power

-

Show total the power in watts that the FPGA hardware consumes.

-

temp

-

Show FPGA temperature values in degrees Celcius.

-

port

-

Show information about the port such as the AFU ID of currently loaded AFU.

-

fme

-

Show information about the FPGA platform including the partial reconfiguration (PR) Interface ID, the OPAE version, -and the FPGA Interface Manager (FIM) ID.

-

bmc

-

Show all Board Management Controller sensor values for the FPGA resource, if available.

-

phy

-

Show information about the PHY integrated in the FPGA, if available.

-

mac

-

Show information about the MAC address in ROM attached to the FPGA, if available.

-

security

-

Show information about the security keys, hashs and flash count, if available.

-

events

-

Show information about events and sensors, if available.

-

OPTIONAL ARGUMENTS

-

--help, -h

-

Prints help information and exit.

-

--version, -v

-

Prints version information and exit.

-

COMMON ARGUMENTS

-

The following arguments are common to all commands and are optional.

-

-S, --segment

-

PCIe segment number of resource.

-

-B, --bus

-

PCIe bus number of resource.

-

-D, --device

-

PCIe device number of resource.

-

-F, --function

-

PCIe function number of resource.

-

ERRORS ARGUMENTS

-

The first argument to the errors command specifies the resource type. It must be one of the following: - fme,port,all

-

fme

-

Show/clear FME errors.

-

port

-

Show/clear PORT errors.

-

all

-

Show/clear errors for all resources.

-

The optional <command-args> arguments are:

-

--clear, -c

-

Clear errors for the given FPGA resource.

-

PHY ARGUMENTS

-

The optional <command-args> argument is:

-

--group, -G

-

Select which PHY group(s) information to show.

-

EVENTS ARGUMENTS

-

The optional <command-args> argument is:

-

--list,-l

-

List boots (implies --all).

-

--boot,-b

-

Boot index to use, i.e: -    0 for current boot (default). -    1 for previous boot, etc.

-

--count,-c

-

Number of events to print.

-

--all,-a

-

Print all events.

-

--sensors,-s

-

Print sensor data too.

-

--bits,-i

-

Print bit values too.

-

--help,-h

-

Print this help.

-

EXAMPLES

-

This command shows the current power telemetry: -

./fpgainfo power
-

-

This command shows the current temperature readings: -

./fpgainfo temp
-

-

This command shows FME resource errors: -

./fpgainfo errors fme
-
-This command clears all errors on all resources: -
./fpgainfo errors all -c
-
-This command shows information of the FME on bus 0x5e -
./fpgainfo fme -B 0x5e
-
-This command shows information of the FPGA security on bus 0x5e -
./fpgainfo security -B 0x5e
-
-This command shows all events and sensors information including sensor bits: -
./fpgainfo events -asi
-

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fpgamux

-

SYNOPSIS

-
fpgamux [-h] [-S|--socket-id SOCKET_ID] [-B|--bus-number BUS] [-D|--device DEVICE] [-F|--function FUNCTION]
-        [-G|--guid GUID] -m|--muxfile <filepath.json>
-
-

DESCRIPTION

-

fpgamux tests multiple AFUs that are synthesized into a single AFU along with -the CCIP-MUX basic building block (BBB). The CCIP-MUX uses the upper bits in the MMIO addresses to route MMIO -reads and writes to the AFU running on the corresponding CCIP-MUX port. fpgamux uses a configuration file that -lists the software components and correct configuration. fpgamux only runs on the Integrated FPGA Platform. -You cannot run it on the PCIe accelerator card (PAC).

-

.. note::

-
  The OPAE driver discovers only the first AFU. The first software component in the configuration 
-  determines the GUID to use for enumeration. Use the -G|--guid option to override the GUID
-  for the first software component.
-
-

OPTIONS

-

-S SOCKET_ID, --socket-id SOCKET_ID

-

socket id of FPGA resource.

-

-B BUS, --bus BUS

-

bus id of FPGA resource.

-

-D DEVICE, --device DEVICE

-

The device id of FPGA resource.

-

-F FUNCTION, --function FUNCTION

-

The function id of FPGA resource.

-

-G, --guid

-

Specifies the GUID to use for the resource enumeration.

-

-m, --muxfile <filepath.json>

-

The path to the fpgamux configuration file. This file must be in JSON format following the -schema described below.

-

CONFIGURATION

-

fpgamux uses a configuration file (in JSON format) to determine what software components to instantiate and -how to configure them to work with the AFUs. The schema includes the following elements:

-
    [
-        {
-            "app" : "fpga_app",
-            "name" : "String",
-            "config" : "Object"
-        }
-    ]
-
-

EXAMPLES

-

The following example shows a configuration with two components: -

    [
-        {
-            "app" : "nlb0",
-            "name" : "nlb0",
-            "config" :
-            {
-                "begin" : 1,
-                "end" : 1,
-                "multi-cl" : 1,
-                "cont" : false,
-                "cache-policy" : "wrline-M",
-                "cache-hint" : "rdline-I",
-                "read-vc" : "vh0",
-                "write-vc" : "vh1",
-                "wrfence-vc" : "write-vc",
-                "timeout-usec" : 0,
-                "timeout-msec" : 0,
-                "timeout-sec" : 1,
-                "timeout-min" : 0,
-                "timeout-hour" : 0,
-                "freq" : 400000000
-            }
-        },
-        {
-            "app" : "nlb3",
-            "name" : "nlb3",
-            "config" :
-            {
-                "mode" : "read",
-                "begin" : 1,
-                "end" : 1,
-                "multi-cl" : 1,
-                "strided-access" : 1,
-                "cont" : false,
-                "warm-fpga-cache" : false,
-                "cool-fpga-cache" : false,
-                "cool-cpu-cache" : false,
-                "cache-policy" : "wrline-M",
-                "cache-hint" : "rdline-I",
-                "read-vc" : "vh0",
-                "write-vc" : "vh1",
-                "wrfence-vc" : "write-vc",
-                "alt-wr-pattern" : false,
-                "timeout-usec" : 0,
-                "timeout-msec" : 0,
-                "timeout-sec" : 1,
-                "timeout-min" : 0,
-                "timeout-hour" : 0,
-                "freq" : 400000000
-            }
-        }
-    ]
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fpgaport

-

SYNOPSIS

-
fpgaport [-h] [-N NUMVFS] [-X] [--debug] {assign,release} device [port]
-
-

DESCRIPTION

-

The fpgaport enables and disables virtualization. It assigns -and releases control of the port to the virtual function (VF). By default, the driver -assigns the port to the physical function (PF) in the non-virtualization use case.

-

POSITIONAL ARGUMENTS

-

{assign, release}

-
Action to perform.
-
-

device

-
The FPGA device being targeted with this action.
-
-

port

-
The number of the port.
-
-

OPTIONAL ARGUMENTS

-

-N NUMVFS, --numvfs NUMVFS

-
Create NUMVFS virtual functions. The typical value is 1.
-
-

-X, --destroy-vfs

-
Destroy all virtual functions prior to assigning.
-
-

--debug

-
Display additional log information.
-
-

-h, --help

-
Print usage information.
-
-

EXAMPLE

-

fpgaport release /dev/dfl-fme.0 0

-
Release port 0 from physical function control.
-
-

fpgaport assign /dev/dfl-fme.0 0

-
Assign port 0 to physical function control.
-
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fpgasupdate

-

SYNOPSIS

-

fpgasupdate [--log-level=<level>] file [bdf]

-

DESCRIPTION

-

The fpgasupdate command implements a secure firmware update for the following programmable accelerator cards (PACs): -* Intel® PAC with Intel Arria® 10 GX FPGA -* Intel FPGA PAC D5005 -* Intel PAC N3000

-

--log-level <level>

-
Specifies the `log-level` which is the level of information output to your command tool.
-The following seven levels  are available: `state`, `ioctl`, `debug`, `info`, `warning`,
-`error`, `critical`. Setting `--log-level=state` provides the most verbose output.
-Setting `--log-level=ioctl` provides the second most information, and so on. The default
-level is `info`.
-
-

file

-
Specifies the secure update firmware file to be programmed. This file may be to program a
-static region (SR), programmable region (PR), root entry hash, key cancellation, or other
-device-specific firmware.
-
-

bdf

-
The PCIe&reg; address of the PAC to program. `bdf` is of the form `[ssss:]bb:dd:f`,
-corresponding to PCIe segment, bus, device, function. The segment is optional. If
-you do not specify a segment, the segment defaults to `0000`. If the system has only
-one PAC you can omit the `bdf` and let `fpgasupdate`  determine the address
-automatically.
-
-

TROUBLESHOOTING

-

To gather more debug output, decrease the --log-level parameter.

-

EXAMPLES

-

fpgasupdate firmware.bin
-fpgasupdate firmware.bin 05:00.0
-fpgasupdate firmware.bin 0001:04:02.0 --log-level=ioctl

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host_exerciser

-

SYNOPSIS

-
Usage: host_exerciser [OPTIONS] SUBCOMMAND
-
-
-Options:
-  -h,--help                   Print this help message and exit
-  -p,--pci-address TEXT       [<domain>:]<bus>:<device>.<function>
-  -l,--log-level TEXT:{trace,debug,info,warning,error,critical,off}=warning
-                              stdout logging level
-  -s,--shared                 open in shared mode, default is off
-  -t,--timeout UINT=60000     test timeout (msec)
-  -m,--mode UINT:value in {lpbk->0,read->1,trput->3,write->2} OR {0,1,3,2}=lpbk
-                              host exerciser mode {lpbk,read, write, trput}
-  --cls UINT:value in {cl_1->0,cl_2->1,cl_4->2,cl_8->3} OR {0,1,2,3}=cl_1
-                              number of CLs per request{cl_1, cl_2, cl_4, cl_8}
-  --continuousmode BOOLEAN=false
-                              test rollover or test termination
-  --atomic UINT:value in {cas_4->9,cas_8->11,fadd_4->1,fadd_8->3,off->0,swap_4->5,swap_8->7} OR {9,11,1,3,0,5,7}=off
-                              atomic requests (only permitted in combination with lpbk/cl_1)
-  --encoding UINT:value in {default->0,dm->1,pu->2,random->3} OR {0,1,2,3}=default
-                              data mover or power user encoding -- random interleaves both in the same stream
-  -d,--delay BOOLEAN=false    Enables random delay insertion between requests
-  --interleave UINT=0         Interleave requests pattern to use in throughput mode {0, 1, 2}
-                              indicating one of the following series of read/write requests:
-                              0: rd-wr-rd-wr
-                              1: rd-rd-wr-wr
-                              2: rd-rd-rd-rd-wr-wr-wr-wr
-  --interrupt UINT:INT in [0 - 3]
-                              The Interrupt Vector Number for the device
-  --contmodetime UINT=1       Continuous mode time in seconds
-  --testall BOOLEAN=false     Run all tests
-  --clock-mhz UINT=0          Clock frequency (MHz) -- when zero, read the frequency from the AFU
-
-Subcommands:
-  lpbk                        run simple loopback test
-  mem                         run simple mem test
-
-

DESCRIPTION

-

The host exerciser used to exercise and characterize the various host-FPGA -interactions eg. MMIO, Data transfer from host to FPGA , PR, host to FPGA memory etc.

-

Host Exerciser Loopback (HE-LBK)

-

HE-LB is responsible for generating traffic with the intention of exercising the -path from the AFU to the Host at full bandwidth. -Host Exerciser Loopback (HE-LBK) AFU can move data between host memory and FPGA.

-

HE-LBK supports: -1. Latency (AFU to Host memory read) -2. MMIO latency (Write+Read) -3. MMIO BW (64B MMIO writes) -4. BW (Read/Write, Read only, Wr only)

-

Host Exerciser Memory (HE-MEM)

-

HE-MEM is used to exercise use of FPGA connected DDR; data read from the host is -written to DDR, and the same data is read from DDR before sending it back to the -host. HE-MEM uses external DDR memory (i.e. EMIF) to store data. It has a customized -version of the AVMM interface to communicate with the EMIF memory controller.

-

Execution of these exercisors requires the user to bind specific VF endpoint to vfio-pci -Bind the correct endpoint for a device with B/D/F 0000:b1:00.0

-

[user@localhost]: sudo opae.io init -d 0000:b1:00.2 user:user

-

HOST EXERCISER SUB COMMANDS

-

lpbk

-

run host exerciser loopback test

-

mem

-

run host exerciser memory test

-

OPTIONAL ARGUMENTS

-

--help, -h

-

Prints help information and exit.

-

COMMON ARGUMENTS / OPTIONS

-

The following arguments are common to all commands and are optional.

-

-p,--pci-address

-

PCIe domain, bus, device, function number of fpga resource.

-

-l,--log-level

-

set host exerciser tool log level, trace, debug, info, warning, error, critical, off

-

-s,--shared

-

open FPGA PCIe resource in shared mode

-

-t,--timeout

-

host exerciser tool time out, by default time out 60000

-

-m,--mode

-

host exerciser test modes are lpbk, read, write, trput

-

--cls

-

Number of cachelines per request 1, 2, 3, 4.

-

--continuousmode

-

Configures test rollover or test termination mode.

-

--atomic

-

atomic requests.

-

--encoding

-

select data mover mode or power user mode or random.

-

-d,--delay

-

Enables random delay insertion between requests.

-

--interleave

-

Enables interleave requests in throughput mode. -Value:3'b000-Rd,Wr,Rd,Wr -Value:3'b001-Rd,Rd,Wr,Wr -Value:3'b010-Rd,Rd,Rd,Rd,Wr,Wr,Wr,Wr -Value:3'b011-Not supported

-

--interrupt

-

Accelerator interrupt vector Number.

-

--contmodetime

-

Continuous mode time in seconds.

-

--testall

-

Run all host exerciser tests.

-

--clock-mhz

-

pcie clock frequency, default value 350Mhz.

-

EXAMPLES

-

This command exerciser Loopback afu: -

host_exerciser lpbk
-

-

This command exerciser memory afu: -

host_exerciser mem
-

-

This command exerciser Loopback afu on pcie 000:3b:00.0: -

host_exerciser --pci-address 000:3b:00.0    lpbk
-

-

This command exerciser Loopback afu on pcie 000:3b:00.0 and run in write mode: -

host_exerciser --pci-address 000:3b:00.0   --mode write lpbl
-

-

This command exerciser Loopback afu on pcie 000:3b:00.0 and run 2 cache lines per request: -

host_exerciser --pci-address 000:3b:00.0   --cls cl_2  lpbk
-

-

This command exerciser Loopback afu on pcie 000:3b:00.0 and run continuous mode for 10 seconds: -

host_exerciser --pci-address 000:3b:00.0   -cls cl_1   -m 0 --continuousmode true --contmodetime 10 lpbk
-

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hssi

-

SYNOPSIS

-

hssi COMMON_OPTIONS MODE MODE_OPTIONS

-

DESCRIPTION

-

The hssi application provides a means of interacting with the 10G and -with the 100G HE-HSSI AFUs. In both 10G and 100G operating modes, the application -initializes the AFU and completes the desired transfer as described by the mode- -specific options.

-

COMMON_OPTIONS - application options common to both 10G and 100G modes.

-

-h, --help

-
Display common command-line help and exit.
-
-

-p, --pci-address ADDR

-
The PCIe address of the desired accelerator in ssss:bb:dd.f format.
-
-

-s, --shared on|off

-
Whether to open the accelerator in shared mode. The default is off.
-
-

-t, --timeout VALUE

-
The application timeout value in milliseconds. The default timeout is 60000 msec.
-
-

MODE - select AFU. Valid values are hssi_10g and hssi_100g.

-

MODE_OPTIONS [hssi_10g] - application options specific to the 10G AFU.

-

-h, --help

-
Display 10G AFU specific command-line help and exit.
-
-

--port PORT

-
Select the QSFP port in the range 0-7. The default is port 0.
-
-

--eth-loopback on|off

-
Whether to enable loopback on the ethernet interface. Valid values are
-on and off. The default is on.
-
-

--num-packets PACKETS

-
The number of packets to transfer. The default is 1 packet.
-
-

--random-length fixed|random

-
Specify packet length randomization. Valid values are fixed and
-random. The default is fixed (no randomization).
-
-

--random-payload incremental|random

-
Specify payload randomization. Valid values are incremental and
-random. The default is incremental.
-
-

--packet-length LENGTH

-
Specify packet length. The default is 64 bytes.
-
-

--src-addr ADDR

-
Specify the source MAC address. The default value is 11:22:33:44:55:66.
-
-

--dest-addr ADDR

-
Specify the destination MAC address. The default value is 77:88:99:aa:bb:cc.
-
-

--rnd-seed0 SEED0

-
Specify the prbs generator bits [31:0]. The default is 1592590336.
-
-

--rnd-seed1 SEED1

-
Specify the prbs generator bits [47:32]. The default is 1592590337.
-
-

--rnd-seed2 SEED2

-
Specify the prbs generator bits [91:64]. The default is 155373.
-
-

MODE_OPTIONS [hssi_100g] - application options specific to the 100G AFU.

-

--port PORT

-
Select the QSFP port in the range 0-7. The default is port 0.
-
-

--eth-loopback on|off

-
Whether to enable loopback on the ethernet interface. Valid values are
-on and off. The default is on.
-
-

--num-packets PACKETS

-
The number of packets to transfer. The default is 1 packet.
-
-

--gap random|none

-
Inter-packet gap. Valid values are random and none. The default is none.
-
-

--pattern random|fixed|increment

-
Pattern mode. Valid values are random, fixed, or increment. The default
-is random.
-
-

--src-addr ADDR

-
Specify the source MAC address. The default value is 11:22:33:44:55:66.
-
-

--dest-addr ADDR

-
Specify the destination MAC address. The default value is 77:88:99:aa:bb:cc.
-
-

--start-size SIZE

-
Specify the packet size in bytes, or the first packet size for --pattern increment.
-
-

--end-size SIZE

-
Specify the end packet size in bytes.
-
-

--end-select pkt_num|gen_idle

-
Specify packet generation end mode.
-
-

MODE_OPTIONS [pkt_filt_10g] - application options specific to the Packet Filter 10G AFU.

-

--dfl-dev DFL_DEV

-
Packet Filter DFL device, eg --dfl-dev dfl_dev.0
-
-

MODE_OPTIONS [pkt_filt_100g] - application options specific to the Packet Filter 100G AFU.

-

--dfl-dev DFL_DEV

-
Packet Filter DFL device, eg --dfl-dev dfl_dev.1
-
-

EXAMPLES

-

hssi -h
-hssi hssi_10g -h
-sudo hssi --pci-address=0000:3b:00.0 hssi_10g --eth-loopback=on --num-packets=500
-sudo hssi --pci-address=0000:3b:00.0 hssi_100g --pattern=increment

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hssi_config

-

Synopsis

-

hssi_config reads or writes HSSI registers on either on an Intel® FPGA using the -FPGA Interface Manager (FIM) or on an HSSI retimer card attached to the board. -hssi_config is only available for the Integrated FPGA Platform. You cannot run it -on the PCIe accelerator card (PAC).

-

Usage

-

hssi_config [--resource|-r <sysfs resource>] [--socket-id|s 0|1] command [command options]

-

Where command is one of the following:

-
    dump [outfile.csv] [--input-file inputfile.csv]
-    iread instance (0,1) device-addr byte-address byte-count
-    iwrite instance (0,1) device-addr byte-address byte1 [byte2 [byte3...]]
-    load [inputfile.csv] [--c-header]
-    read lane(0-15) reg-address
-    rread device(0x30, 0x32, 0x34, 0x36) channel(0-3) address
-    rwrite device(0x30, 0x32, 0x34, 0x36) channel(0-3) address value
-    test (rd|rw) inputfile.csv [--acktimes] [--repeat N]
-    write lane(0-15) reg-address value
-
-

The first argument is the command and any additional arguments are command arguments. -The following options and commands are available:

-

Options

-

[--resource|-r <sysfs resource path>

-

The resource path in the sysfs pseudo-filesystem. -Example: - /sys/devices/pci0000\:5e/0000\:5e\:00.0/resource0

-

[--socket-id 0|1]

-

The socket id of the target FPGA. -Required on two-socket systems to differentiate between the two possible target FPGAs.

-

Commands

-

dump [outfile.csv] [--input-file inputfile.csv]

-

Dump registers to stdout or to a file, if provided. hssi_config has a built-in set of registers to -dump. The first argument is the path to a file to write. The command dumps to stdout if you do not -specify a file name. Use the --input-file option to specify a different set of registers.

-

load [inputfile.csv] [--c-header]

-

Load a set of register values from either stdin or an input file, if provided. The first argument -is the path to a file containing the registers to load. Loads from stdin if omitted.

-

Use --c-header to generate a C header file with an array of 64-bit numbers to write to the -HSSI_CTRL register. This header file can substitute for the input file. -NOTE: You must perform the acknowledge routine after each write.

-

read lane(0-15) reg-address

-

Read from a single XCVR (transceiver) register. -The first command argument is the XCVR lane. Use -1 to specify a read from all lanes. -The second argument is the XCVR address (offset).

-

write lane(0-15) reg-address value

-

Write to a single XCVR register. -The first argument is the XCVR lane. -The second argument is the XCVR address(offset). -The third argument is the value to write to the register.

-

rread device(0x30, 0x32, 0x34, 0x36) channel(0-3) address

-

Read from a single retimer register. -The first argument is the I2C device address. -The second argument is the channel. -The third argument is the register address (or I2C byte address).

-

rwrite device(0x30, 0x32, 0x34, 0x36) channel(0-3) address value

-

Write to a single retimer register. -The first argument is the I2C device address. -The second argument is the channel. -The third argument is the register address (or I2C byte address). -The fourth argument is the value to write.

-

iread instance (0,1) device-addr byte-address byte-count

-

Read from a device on the I2C bus. -The first argument is the I2C controller instance (0 or 1). -The second argument is the device address to read from. -The third argument is the byte address of the register to read from the device. -The fourth argument is the number of bytes to read.

-

iwrite instance (0,1) device-addr byte-address byte1 [byte2 [byte3...]]

-

Write to a device on the I2C bus. -The first argument is the I2C controller instance (0 or 1). -The second argument is the device address to read from. -The third argument is the byte address of the register to read from the device. -All subsequent arguments are the bytes to write to the device.

-

test (rd|rw) inputfile.csv [--acktimes]

-

Perform built-in test for reading or writing XCVR registers. -The first argument is the path to a file containing the registers to test.

-

Overview

-

The hssi_config utility reads or writes hssi equalization parameters stored in either -the transceiver (XCVR) registers or the registers of the retimer on the I2C bus. To access registers, -the hssi controller writes to the HSSI_CTRL register and reads from the HSSI_STAT -register in the FPGA Management Engine (FME). These two registers implement the HSSI AUX bus -mailbox protocol to access devices on other buses. Because hssi_config maps the FME MMIO -space directly, the FPGA driver is not required.

-

Locating the FME Device

-

The FME reads and writes the HSSI_CTRL and HSSI_STAT registers on the NIOS device. -The FME maps the MMIO address space of the FME identified by its resource in the sysfs psuedo-filesystem -in Linux operating systems. To identify resource paths, use the lspci utility to query for Intel -devices with device id of bcc0.

-

Example:

-

lspci -d 8086:bcc0

-

This command should print out at least one line like the following example:

-

5e:00.0 Processing accelerators: Intel Corporation Device bcc0

-

Use the first three numbers (bus:device.function) to locate the device resource -in the sysfs filesystem:

-

/sys/devices/pci0000\:<bus>/0000\:<bus>\:<device>.<function>/resource0

-

For example, the example above with bus of 5e, device of 00 and function of 0 would -use a resource path as follows:

-

/sys/devices/pci0000\:5e/0000\:5e\:00.0/resource0

-

CSV File Format

-

Any CSV file parsed by hssi_config must meet have at least four columns. The following table provides -the column specifications:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ColumnNameDescription
1Register type.Can be either FPGA_RX, FPGA_TX, RTMR_RX, RTMR_TX (or their corresponding numeric values, 1-4).
2Lane or Channel0-15 for XCVR lanes on FPGA, 0-3 for retimer channels. -1 to designate all lanes or channels.
3Device address (on I2C bus)Only applies to retimer registers. 0 - 3, -1 to designate all devices.
4Register address (or offset)Examples: 0x213, 0x100.
5Register value to writeExamples: 0x1, 1, 0. Applies only when loading or writing registers.
-

Examples of Commands

-

Dumping Registers

-

Dump default register set to stdout:

-

>hssi_config dump

-

Dump default registers to a file, data.csv:

-

>hssi_config dump data.csv

-

Dump to an output file, data.csv, Registers specified in an input file, regspec.csv:

-

>hssi_config dump data.csv --input-file regspec.csv

-

Reading Single Registers

-

Read register from XCVR at 0x2e1 on lane 0:

-

>hssi_config read 0 0x2e1

-

Read register 0x109 from retimer on channel 0, device 0x30, channel 1:

-

>hssi_config rread 0 0x30 0x109

-

Loading Registers

-

Load registers specified in an input file called data.csv:

-

>hssi_config load data.csv

-

Load registers specified from stdin:

-

>hssi_config load

-
FPGA_RX,1,-1,0x213,0
-FPGA_RX,2,-1,0x213,0
-FPGA_RX,3,-1,0x213,0
-<CTRL-D>
-
-

Writing Single Registers

-

Write 1 to XCVR register at 0x2e1 on lane 0:

-

>hssi_config write 0 0x2e1 1

-

Read register 0x109 from retimer on channel 0, device 0x30, channel 1:

-

>hssi_config rread 0 0x30 0x109

-

Testing HSSI Read and Write

-

> test (rd|rw) register-file.csv [--acktimes]

-

rd|wr

-

Specifies either a rd or wr of transceiver registers. For writes, -every register in the file is read from and written to in the following sequence:

-

1. Read the register, save the value - 2. Write 1 to the register - 3. Read the register, verify that the register value is 1 - 4. Write 0 to the register - 5. Read the register, verify that the register value is 0 - 6. Write the original value to the register - 7. Read the register, assert it is the original value

-

register=file.csv

-

Specifies the path to a file containing the set of registers to test.

-

--acktimes

-

Specifies the time spent in the ack routine. When measured, a summary of ack times prints -to stdout. This argument is optional.

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HSSI ethernet loopback

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SYNOPSIS

-
hssiloopback [-h] [--pcie-address PCIE_ADDRESS, -P PCIE_ADDRESS] --loopback [{enable,disable}]
-
-

DESCRIPTION

-

The hssiloopback tool enables and disable ethernet loopback.

-

OPTIONAL ARGUMENTS

-

-h, --help

-

Prints usage information

-

--pcie-address PCIE_ADDRESS, -P PCIE_ADDRESS

-

The PCIe address of the desired fpga in ssss:bb:dd.f format. sbdf of device to program (e.g. 04:00.0 or 0000:04:00.0). Optional when one device in system.

-

--loopback [{enable,disable}]

-

Ethernet enable or disable loopback.

-

EXAMPLES

-

hssiloopback --pcie-address 0000:04:00.0 --loopback enable

-

Enables ethernet loopback

-

hssiloopback --pcie-address 0000:04:00.0 --loopback disable

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Disable ethernet loopback

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HSSI ethernet mac

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SYNOPSIS

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hssimac [-h] --pcie-address PCIE_ADDRESS [--port PORT]
-
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DESCRIPTION

-

The hssimac tool provides Maximum TX and RX frame size.

-

OPTIONAL ARGUMENTS

-

-h, --help

-

Prints usage information

-

--pcie-address PCIE_ADDRESS, -P PCIE_ADDRESS

-

The PCIe address of the desired fpga in ssss:bb:dd.f format. sbdf of device to program (e.g. 04:00.0 or 0000:04:00.0).

-

--port PORT

-

hssi port number.

-

EXAMPLES

-

hssimac --pcie-address 0000:04:00.0 --port 1

-

prints Maximum TX and RX frame size for port 1.

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HSSI ethernet statistics

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SYNOPSIS

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hssistats [-h] [--pcie-address PCIE_ADDRESS, -P PCIE_ADDRESS]
-
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DESCRIPTION

-

The hssistats tool provides the MAC statistics.

-

OPTIONAL ARGUMENTS

-

-h, --help

-

Prints usage information

-

--pcie-address PCIE_ADDRESS, -P PCIE_ADDRESS

-

The PCIe address of the desired fpga in ssss:bb:dd.f format. sbdf of device to program (e.g. 04:00.0 or 0000:04:00.0). Optional when one device in system.

-

EXAMPLES

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hssistats --pcie-address 0000:04:00.0

-

prints the MAC statistics

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hssi_loopback

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NAME

-

hssi_loopback - Software utility to run HSSI loopback tests on FPGA

-

SYNOPSIS

-

hssi_loopback [[--bus|-b <bus number>] [--device | -d <device number>] [--function | -f <function number>]]|[--socket-id <socket-id>] - [--mode|-m auto|e40|e10] - [send [<source port> [<destination port>] [--packet-count|-c <count>] [--packet-delay|-d <delay>] [--packet-length|-l <length>]] |status [clear] | stop | readmacs

-

DESCRIPTION

-

The hssi_loopback utility works in conjunction with a packet generator accelerator function unit (AFU) -to test high-speed serial interface (HSSI) cards. The hssi_loopback utility tests both external and internal loopbacks. -hssi_loopback runs an external loopback test when the command line arguments include both source and destination ports. -hssi_loopback runs an internal loopback test when command line arguments include a single port. hssi_loopback -only runs on the Intel Xeon with Arria 10 FPGA. You cannot run it on the Intel PAC (programmable accelerator card).

-

NOTE: The following limitations apply to the current version of hssi_loopback:

-
    -
  • For the external loopback the two port arguments can be the same. For the e10 design, the ports should be the same.
    • -
  • The hssi_loopback test supports only the e40 and e10 E2E AFUs. The e10 E2E AFU tests HSSI with a retimer card.
    • -
  • The hssi_loopback test uses the control and status registers (CSRs) defined in the AFU.
    • -
-

OPTIONS

-

-S SOCKET_ID, --socket-id SOCKET_ID

-

Socket ID FPGA resource.

-

-B BUS, --bus BUS

-

Bus ID of FPGA resource.

-

-D DEVICE, --device DEVICE

-

Device ID of FPGA resource.

-

-F FUNCTION, --function FUNCTION

-

Function ID of FPGA resource.

-

-G, --guid

-

Specifies guid for the resource enumeration.

-

-m, --mode

-

One of the following: [auto, e40, e10] -auto is the default and indicates that the software runs the mode based on the first accelerator functional -unit it identifies.

-

-t, --timeout

-

Timeout (in seconds) before the application terminates in continuous mode. Continuous mode is the default -when you do not specify the number of packets.

-

-y, --delay

-

Delay (in seconds) between printing out a simple status line. Default is 0.100 seconds (100 milliseconds).

-

-c, --packet-count

-

The number of packets to send.

-

-d, --packet-delay

-

The delay in between packets. This delay is the number of 100 MHz clock cycles, roughly 10 nanoseconds.

-

-s, --packet-size

-

The packet size to send. The minimum is 46 bytes and the maximum is 1500 bytes. The default is 46 bytes.

-

COMMANDS

-

send <source port> [<destination port>] [--packet-count|-c <count>] [--packet-delay|-d <delay>] [--packet-length|-l <length>]

-

Send packets from one port to the other. If the command line does not specify a destination port, the test runs an internal -loopback. Otherwise, the test runs an external loopback from the source port to the destination port.

-

status [clear]

-

Read and interpret the status registers and print to the screen. clear clears the status registers.

-

stop

-

Issue a stop command to all Ethernet controllers in the AFU.

-

readmacs

-

Read and display the port MAC addresses. An EEPROM stores the MAC addresses.

-

EXIT CODES

-

0 Success - Number of packets received are equal to the number of packets sent and no errors - are reported.

-

-1 Loopback failure - Either number of packets does not match or the test detected errors.

-

-2 Errors parsing arguments.

-

EXAMPLES

-

Read the MAC addresses of the AFU loaded on bus 0x5e:

-
>sudo hssi_loopback readmacs -B 0x5e
-
-

Run an external loopback, sending 100 packets from port 0 to port 1. The AFU is on bus 0x5e:

-
>sudo hssi_loopback -B 0x5e send 0 1 -c 100
-
-

Run an internal loopback until a timeout of 5 seconds is reached. The AFU is on bus 0x5e:

-
>sudo hssi_loopback -B 0x5e send 0 -t 5
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mem_tg

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SYNOPSIS

-
Usage: mem_tg [OPTIONS] SUBCOMMAND
-
-Options:
-  -h,--help                   Print this help message and exit
-  -g,--guid TEXT=4DADEA34-2C78-48CB-A3DC-5B831F5CECBB
-                              GUID
-  -p,--pci-address TEXT       [<domain>:]<bus>:<device>.<function>
-  -l,--log-level TEXT:{trace,debug,info,warning,error,critical,off}=info
-                              stdout logging level
-  -s,--shared                 open in shared mode, default is off
-  -t,--timeout UINT=60000     test timeout (msec)
-  -m,--mem-channel UINT=0     Target memory bank for test to run on (0 indexed)
-  --loops UINT=1              Number of read/write loops to be run
-  -w,--writes UINT=1          Number of unique write transactions per loop
-  -r,--reads UINT=1           Number of unique read transactions per loop
-  -b,--bls UINT=1             Burst length of each request
-  --stride UINT=1             Address stride for each sequential transaction
-  --data UINT:value in {fixed->0,prbs15->2,prbs31->3,prbs7->1,rot1->3} OR {0,2,3,1,3}=fixed
-                              Memory traffic data pattern: fixed, prbs7, prbs15, prbs31, rot1
-  -f,--mem-frequency UINT=0   Memory traffic clock frequency in MHz
-
-Subcommands:
-  tg_test                     configure & run mem traffic generator test
-
-

DESCRIPTION

-

The memory traffic generator (TG) used to exercise and test available memory channels -with a configurable traffic pattern.

-

Execution of this application requires the user to bind the specific VF endpoint containing the mem_tg AFU id to vfio-pci

-

In the TG, read responses are checked against a specified pattern. If the application is configured to perform a read only test on a region of memory that has not previously been initialized to contain that pattern it will flag a test failure.

-

OPTIONAL ARGUMENTS

-

--help, -h

-

Prints help information and exit.

-

COMMON ARGUMENTS / OPTIONS

-

The following arguments are common to all commands and are optional.

-

-p,--pci-address

-

PCIe domain, bus, device, function number of fpga resource.

-

-l,--log-level

-

set application log level, trace, debug, info, warning, error, critical, off

-

-s,--shared

-

open FPGA PCIe resource in shared mode

-

-t,--timeout

-

mem_tg application time out, by default time out 60000

-

-m,--mem-channel

-

Target memory bank for test to run on (0 indexed) -default: 0

-

--loops

-

Number of read/write loops to be run -default: 1

-

-w,--writes

-

Number of unique write transactions per loop. -default: 1

-

-r,--reads

-

Number of unique read transactions per loop -default: 1

-

-b,--bls

-

AXI4 burst length of each request. Supports 1-256 transfers beginning from 0. -default: 0

-

--stride

-

Address stride for each sequential transaction (>= burst length) -default: 1

-

--data

-

Memory traffic data pattern. -0 = fixed {0xFF, 0x00} -1 = prbs7 -2 = prbs15 -3 = prbs31 -4 = rot1

-

default: fixed

-

-f, --mem-frequency

-

Memory traffic clock frequency in MHz -default: 300 MHz

-

EXAMPLES

-

This command will run a basic read/write test on the channel 0 traffic generator: -

mem_tg tg_test
-

-

This command will run the application for an afu on pcie 000:b1:00.7: -

mem_tg --pci-address 000:b1:00.7 tg_test
-

-

This command will test channel 2 write bandwidth: -

mem_tg -loops 1000 -w 1000 -r 0 -m 2 tg_test
-

-

This command will perform a read bandwidth test with a burst of 16 on channel 1 and perform a data comparison with the prbs7 pattern: -

mem_tg -loops 1000 -w 0 -r 1000 -b 0xF --data prbs7 -m 1 tg_test
-

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This command will perform a read/write test with 1 MB strided access to channel 0 memory: -

mem_tg -loops 10000 --stride 0x100000 tg_test
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mmlink

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Synopsis

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mmlink [-v] [-B <bus>] [-D <device>] [-F <function>] [-S <socket>] [-P <TCP port>] [-I <IP Address>]

-

Description

-

The Remote Signal Tap logic analyzer provides real-time hardware debugging for the Accelerator Function Unit (AFU). -It provides a signal trace capability that the Quartus Prime software adds to the AFU. The Remote Signal Tap logic -analyzer provides access to the Remote Signal Tap part of the Port MMIO space and then runs the remote protocol.

-

Examples

-

./mmlink -B 0x5e -P 3333

-

MMLink app starts and listens for connection.

-

Options

-

-v,--version

-

Prints version information and exits.

-

-B,--bus

-

FPGA Bus number.

-

-D,--device

-

FPGA Device number.

-

-F,--function

-

FPGA function number.

-

-S,--socket

-

FPGA socket number.

-

-P,--port

-

TCP port number.

-

-I,--ip

-

IP address of FPGA system.

-

Notes

-

Driver privilege:

-

Change AFU driver privilege to user:

-
$ chmod 777 /dev/intel-fpga-port.0
-
-

Change locked memory size:

-

edit the file /etc/security/limits.conf

-
$ sudo vi /etc/security/limits.conf
-
-user    hard   memlock           10000
-
-user    soft   memlock           10000
-
-

Exit terminal and log into a new terminal.

-

Verify that the locked memory is now set: -``` -$ ulimit -l 10000

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ofs.uio

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SYNOPSIS

-

ofs.uio [-h] [--pcie-address PCIE_ADDRESS] [--uio uiox] [--feature-id FEATURE_ID] [--region-index REGION_INDEX] - [--mailbox-cmdcsr offset] [--bit-size {8,16,32,64}] [--peek offset] [--poke offset value] - [--mailbox-read offset] [--mailbox-dump address size] [--mailbox-write address value]

-

ofs.uio [--uio uiox] [--peek offset]
-ofs.uio [--uio uiox] [--poke offset value]
-ofs.uio [--uio uiox] [--mailbox-read address]
-ofs.uio [--uio uiox] [--mailbox-write address value]
-ofs.uio [--uio uiox] [--mailbox-dump address size]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--peek offset]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--poke offset value]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--mailbox-read address]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--mailbox-write address value]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--mailbox-dump address size]

-

DESCRIPTION

-

ofs.uio is a tool that provides user space access to DFL UIO devices, -command line options like peek, poke, mailbox-read, mailbox-write, mailbox-dump to -access Configuration and Status Registers (CSRs).

-

OPTIONS

-

Peek

-

Peek/Read UIO CSR offset
-ofs.uio [--uio uio] [--peek offset]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--peek offset]

-

Poke

-

Poke/Write value to UIO CSR offset
-ofs.uio [--uio uio] [--poke offset value]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--poke offset value]

-

Mailbox Read

-

Read CSR address using mailbox
-ofs.uio [--uio uio] [--mailbox-read address]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--mailbox-read address]

-

Mailbox Write

-

Write value to CSR address using mailbox
-ofs.uio [--uio uio] [--mailbox-write address value]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--mailbox-write address value]

-

Mailbox Dump

-

Reads/Dumps block size of CSR address using mailbox
-ofs.uio [--uio uio] [--mailbox-dump address size]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--mailbox-dump address size]

-

Bit size

-

Read/Write bit-field 8,16,32,64 sizes
-ofs.uio [--uio uio] --bit-size 8 [--peek offset]
-ofs.uio [--uio uio] --bit-size 32 [--peek offset]

-

PCIe Address

-

PCIE_ADDR PCIe address of FPGA device
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] [--peek offset]

-

UIO region index

-

UIO region index, default region index is 0
-ofs.uio [--uio uio] --region-index 0 [--peek offset]
-ofs.uio [--uio uio] --region-index 1 [--peek offset]

-

Mailbox command status csr offset

-

Mailbox command status csr offset, -default value set to dfl pcie subsystem system feature mailbox command status register offset 0x28
-ofs.uio [--uio uio] --mailbox-cmdcsr 0xa8 [--mailbox-read address]
-ofs.uio [--pcie-address PCIE_ADDRESS] [--feature-id FEATURE_ID] --mailbox-cmdcsr 0xa8 [--mailbox-read address]

-

EXAMPLES

-

Peek/Read -

ofs.uio --uio uio0 --peek 0x0
-peek(0x0): 0x3000000010002015
-
-ofs.uio --uio uio6 --peek 0x0
-peek(0x0): 0x3000000100000020
-
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x15 --peek 0x0
-peek(0x0): 0x3000000010002015
-
-ofs.uio --uio uio0 --peek 0x0 --bit-size 32
-peek(0x0): 0x10002015
-

-

Poke/Write -

ofs.uio --uio uio6 --peek 0x8
-peek(0x8): 0x0
-ofs.uio --uio uio6 --poke  0x8 0xabcdd12345
-poke(0x8):0xabcdd12345
-
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x15 --peek 0x0
-peek(0x8): 0x0
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x15 --poke  0x8 0x1234
-poke(0x8):0x1234
-

-

Mailbox Read -

ofs.uio --uio uio6 --mailbox-read 0x0
-MailboxRead(0x0): 0x1000000
-ofs.uio --uio uio6 --mailbox-read 0x8
-MailboxRead(0x8): 0x110c000
-
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x20 --mailbox-read 0x0
-MailboxRead(0x0): 0x1000000
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x20 --mailbox-read 0x8 
-MailboxRead(0x8): 0x110c000
-

-

Mailbox Write -

ofs.uio --uio uio6 --mailbox-write 0x0 0x1234
-MailboxWrite(0x0):0x1234
-ofs.uio --uio uio6 --mailbox-read 0x0
-MailboxRead(0x0):0x1234
-
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x20 --mailbox-write 0x0 0x1234
-MailboxWrite(0x0):0x1234
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x20 --mailbox-read 0x0 
-MailboxRead(0x0):0x1234
-

-

Mailbox Dump -

ofs.uio --uio uio6 --mailbox-dump 0x0 0x10
-MailboxDump(0x0): 0x1000000
-MailboxDump(0x4): 0x1000000
-MailboxDump(0x8): 0x110c000
-MailboxDump(0xc): 0x110c000
-MailboxDump(0x10): 0x0
-MailboxDump(0x14): 0x0
-MailboxDump(0x18): 0x0
-MailboxDump(0x1c): 0x0
-MailboxDump(0x20): 0x0
-MailboxDump(0x24): 0x0
-MailboxDump(0x28): 0x0
-MailboxDump(0x2c): 0x0
-MailboxDump(0x30): 0x0
-MailboxDump(0x34): 0x0
-MailboxDump(0x38): 0x0
-MailboxDump(0x3c): 0x0
-
-
-
-ofs.uio --pcie-address 0000:b1:00.0 --feature-id 0x20 --mailbox-dump 0x0 0x10
-MailboxDump(0x0): 0x1000000
-MailboxDump(0x4): 0x1000000
-MailboxDump(0x8): 0x110c000
-MailboxDump(0xc): 0x110c000
-MailboxDump(0x10): 0x0
-MailboxDump(0x14): 0x0
-MailboxDump(0x18): 0x0
-MailboxDump(0x1c): 0x0
-MailboxDump(0x20): 0x0
-MailboxDump(0x24): 0x0
-MailboxDump(0x28): 0x0
-MailboxDump(0x2c): 0x0
-MailboxDump(0x30): 0x0
-MailboxDump(0x34): 0x0
-MailboxDump(0x38): 0x0
-MailboxDump(0x3c): 0x0
-

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opae.io

-

SYNOPSIS

-

opae.io ls [-v,--viddid VID:DID]
-opae.io init [-d PCI_ADDR USER[:GROUP]]
-opae.io release [-d PCI_ADDR]
-opae.io [-d PCI_ADDR] [-r REGION] walk OFFSET [-u,--show-uuid]
-opae.io [-d PCI_ADDR] [-r REGION] peek OFFSET
-opae.io [-d PCI_ADDR] [-r REGION] poke OFFSET VALUE
-opae.io [-d PCI_ADDR] [-r REGION] SCRIPT ARG1 ARG2 ... ARGN
-opae.io [-d PCI_ADDR] [-r REGION]

-

DESCRIPTION

-

opae.io is an interactive Python environment packaged on top of -libopaevfio.so, which provides user space access to PCIe devices -via the vfio-pci driver. The main feature of opae.io is its built-in -Python command interpreter, along with some Python bindings that provide -a means to access Configuration and Status Registers (CSRs) that reside -on the PCIe device.

-

opae.io has two operating modes: command line mode and interactive -mode.

-

COMMAND LINE MODE

-

To view the accelerator devices that are present on the system, opae.io -provides the ls command option.

-

opae.io ls [-v,--viddid VID:DID]

-

Each accelerator device is listed along with the PCIe address, the -PCIe vendor/device ID, a brief description of the device, and the -driver to which the device is currently bound.

-

opae.io provide an option to initialize a PCIe device for use with -the vfio-pci driver. In order for the device CSRs to be accessed from -user space, the device must first be bound to the vfio-pci driver. This -is the job of the init command option.

-

opae.io init [-d PCI_ADDR USER:[GROUP]]

-

The init command unbinds the specified device from its current -driver and binds it to vfio-pci. This creates a new vfio group under -/dev/vfio. This group path is then used by the libopaevfio.so -library to interact with the device.

-

To release the PCIe device from vfio-pci and return it to use with its -previous driver, the release command option is used.

-

opae.io release [-d PCI_ADDR]

-

The release command option reverses the actions of the last -init command, releasing the device from vfio-pci and binding -it to the driver which was bound at the time the init command -was issued.

-

The walk command option traverses and displays the Device -Feature List of the given region.

-

opae.io walk [-d PCI_ADDR] [-r REGION] [OFFSET] [-u,--show-uuid]

-

The various fields of each Device Feature Header are displayed. The ---show-uuid option additionally displays the GUID for each feature. -OFFSET can be used to specify the beginning of the DFL in the MMIO -region.

-

The peek command option reads and displays a CSR value.

-

opae.io peek [-d PCI_ADDR] [-r REGION] OFFSET

-

The poke command option writes a given value to a CSR.

-

opae.io poke [-d PCI_ADDR] [-r REGION] OFFSET VALUE

-

opae.io can also execute Python scripts from the command line. -These Python scripts may contain calls to the device built-in -functions that are available during an interactive session. Refer -to the description of interactive mode for details.

-

opae.io [-d PCI_ADDR] [-r REGION] myscript.py a b c

-

In order to enter the interactive mode of opae.io, simply -invoke it and optionally pass the desired device address and -MMIO region options.

-

opae.io [-d PCI_ADDR] [-r REGION]

-

INTERACTIVE MODE

-

Upon entering interactive mode, opae.io begins a Python -interpreter session and displays the command prompt shown below:

-

0000:3f:00.0[0]>>

-

The first portion of the prompt shows the address of the active -PCIe device, here 0000:3f:00.0. The part in square brackets shows -the active MMIO region, here [0].

-

The interpreter waits for a valid Python command, then attempts -to execute the given command in the usual way. The only -differences between the traditional Python command intepreter and -opae.io are that opae.io provides 1) the notion of an active -PCIe device and MMIO region and 2) several built-in functions and -objects that allow manipulating the active device and MMIO region.

-

BUILT-IN FUNCTIONS

-

The opae.io built-in functions assume an active device and -MMIO region. Attempting to use the built-in functions without first -opening a device and region will result in errors.

-

peek(OFFSET)

-

The peek built-in function reads and displays a CSR value from -the active device and region, at the offset supplied by its argument.

-

0000:3f:00.0[0]>> peek(0x28)
-0xdeadbeef

-

poke(OFFSET, VALUE)

-

The poke built-in function writes the given VALUE to the current -MMIO region at the given OFFSET.

-

0000:3f:00.0[0]>> poke(0x28, 0xdeadbeef)

-

read_csr(OFFSET)

-

The read_csr built-in function returns the value of the CSR at -the active MMIO region and the given OFFSET.

-

0000:3f:00.0[0]>> print('0x{:0x}'.format(read_csr(0x28)))
-0xdeadbeef

-

write_csr(OFFSET, VALUE)

-

The write_csr built-in function writes the given VALUE to -the current MMIO region at the given OFFSET.

-

0000:3f:00.0[0]>> write_csr(0x28, 0xdeadbeef)

-

device(PCI_ADDR)

-

The device built-in function allows changing the active -PCIe device.

-

0000:3f:00.0[0]>> device('0000:2b:00.0')
-0000:2b:00.0>>

-

region(REGION)

-

The region built-in function allows changing the active -MMIO region.

-

0000:2b:00.0>> region(0)
-0000:2b:00.0[0]>>

-

allocate_buffer(SIZE)

-

The allocate_buffer built-in function creates and returns -a DMA buffer object. The underlying buffer will be SIZE bytes -in length.

-

0000:2b:00.0[0]>> b1 = allocate_buffer(4096)
-0000:2b:00.0[0]>> print(b1.size, '0x{:0x}'.format(b1.address), b1.io_address)
-4096 0x7f9361c66000 0

-

version()

-

The version built-in function returns a tuple containing -the four components used to identify the opae.io version:

-

0000:2b:00.0[0]>> print(version())
-('opae.io', 0, 2, 0)

-

BUILT-IN OBJECTS

-

opae.io interactive mode provides two global objects -corresponding to the current device and that device's current -MMIO region. These objects are referred to by global variables -the_device and the_region, respectively.

-

The device class:

-

the_device.descriptor() : method that returns the integer file -descriptor of the VFIO container.

-

0000:2b:00.0[0]>> print(the_device.descriptor())
-5

-

the_device.repr() : method that is invoked when a device -object is printed.

-

0000:2b:00.0[0]>> print(the_device)
-0000:2b:00.0

-

the_device.allocate(SIZE) : method that allocates and returns a -system_buffer object. The buffer will be mapped into the -DMA space of the_device.

-

0000:2b:00.0[0]>> b1 = the_device.allocate(4096)

-

the_device.pci_address() : read-only property that returns the -PCIe address of the_device.

-

0000:2b:00.0[0]>> print(the_device.pci_address)
-0000:2b:00.0

-

the_device.num_regions : read-only property that returns the -number of MMIO regions in the_device.

-

0000:2b:00.0[0]>> print(the_device.num_regions)
-2

-

the_device.regions : read-only property that returns a list -of the active MMIO regions of the_device:

-

0000:2b:00.0[0]>> print(the_device.regions)
-[0, 2]

-

The region class:

-

the_region.write32(OFFSET, VALUE) : method that writes a -32-bit VALUE to the CSR at OFFSET.

-

the_region.read32(OFFSET) : method that returns a 32-bit -CSR at the given OFFSET.

-

0000:2b:00.0[0]>> the_region.write32(0x28, 0xdeadbeef)
-0000:2b:00.0[0]>> print('0x{:0x}'.format(the_region.read32(0x28)))
-0xdeadbeef

-

the_region.write64(OFFSET, VALUE): method that writes a -64-bit VALUE to the CSR at OFFSET.

-

the_region.read64(OFFSET): method that returns a 64-bit -CSR at the given OFFSET.

-

0000:2b:00.0[0]>> the_region.write64(0x28, 0xbaddecaf)
-0000:2b:00.0[0]>> print('0x{:0x}'.format(the_region.read64(0x28)))
-0xbaddecaf

-

the_region.index(): method that returns the MMIO index -of the_region.

-

0000:2b:00.0[0]>> print(the_region.index())
-0

-

the_region.repr(): method that is invoked when a region -object is printed.

-

0000:2b:00.0[0]>> print(the_region)
-0

-

the_region.len(): method that is invoked to determine the -MMIO region size.

-

0000:2b:00.0[0]>> print(len(the_region))
-524288

-

The allocate_buffer() built-in function and the -device.allocate() method return objects of type system_buffer.

-

The system_buffer class is as follows:

-

buf.size: read-only property that gives the buffer size.

-

0000:2b:00.0[0]>> print(b1.size)
-4096

-

buf.address: read-only property that gives the buffer's -user mode virtual address.

-

0000:2b:00.0[0]>> print('0x{:0x}'.format(b1.address))
-0x7f2c15d8200

-

buf.io_address: read-only property that gives the buffer's -IO address.

-

0000:2b:00.0[0]>> print('0x{:0x}'.format(b1.io_address))
-0x0

-

buf.__getitem__ and buf.__setitem__: indexing get/set -of 64-bit data item.

-

0000:2b:00.0[0]>> b1[0] = 0xdecafbad
-0000:2b:00.0[0]>> print('0x{:0x}'.format(b1[0]))
-0xdecafbad

-

buf.read8(OFFSET)
-buf.read16(OFFSET)
-buf.read32(OFFSET)
-buf.read64(OFFSET) : methods that read the given size -data item from the given buffer OFFSET.

-

buf.fill8(VALUE)
-buf.fill16(VALUE)
-buf.fill32(VALUE)
-buf.fill64(VALUE) : methods that fill the buffer with -the given VALUE, using the given size.

-

b1.compare(b2): method that compares buffers. -The method returns the index of the first byte that miscompares, -or the length of b1.

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opaeuio

-

SYNOPSIS

-

opaeuio [-h] [-i] [-r] [-d DRIVER] [-u USER] [-g GROUP] [-v] [device]

-

DESCRIPTION

-

The opaeuio command enables the binding/unbinding of a DFL device -to/from the dfl-uio-pdev device driver. -See https://kernel.org/doc/html/v4.14/driver-api/uio-howto.html for a -description of uio.

-

OPTIONS

-

device - The DFL device name, eg dfl_dev.10

-

-h, --help

-
Display command-line help and exit.
-
-

-i, --init

-
Specifies binding mode operation - initialize the given device for uio.
-Used in conjunction with -u, -g, and -d.
-
-

-r, --release

-
Specifies unbinding mode operation - release the given device from uio.
-
-

-d DRIVER, --driver DRIVER

-
Specifies the device driver to bind to when binding to uio.
-The default value is dfl-uio-pdev.
-
-

-u USER, --user USER

-
The user ID to assign when binding to uio. A new device node is created in
-/dev when the device is bound to uio. Use this option to specify
-the new device owner.
-
-

-g GROUP, --group GROUP

-
The group ID to assign when binding to uio. Use this option to specify the
-new device group for the device created in /dev.
-
-

-v, --version

-
Display script version information and exit.
-
-

EXAMPLES

-

opaeuio -h
-opaeuio -v
-sudo opaeuio -i -u lab -g labusers dfl_dev.10
-sudo opaeuio -r dfl_dev.10

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opaevfio

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SYNOPSIS

-

opaevfio [-h] [-i] [-r] [-d DRIVER] [-u USER] [-g GROUP] [-n] [-v] [addr]

-

DESCRIPTION

-

The opaevfio command enables the binding/unbinding of a PCIe device -to/from the vfio-pci device driver. See https://kernel.org/doc/Documentation/vfio.txt -for a description of vfio-pci.

-

OPTIONS

-

addr - The PCIe address of the device in ssss:bb:dd.f format, eg 0000:7f:00.0

-

-h, --help

-
Display command-line help and exit.
-
-

-i, --init

-
Specifies binding mode operation - initialize the given addr for vfio.
-Used in conjunction with -u, -g, and -n.
-
-

-r, --release

-
Specifies unbinding mode operation - release the given addr from vfio.
-Used in conjunction with -d.
-
-

-d DRIVER, --driver DRIVER

-
Specifies the device driver to bind to when releasing from vfio.
-When omitted, the device is not rebound to a driver (default).
-
-

-u USER, --user USER

-
The user ID to assign when binding to vfio. A new device node is created in
-/dev/vfio when the device is bound to vfio-pci. Use this option to specify
-the new device owner.
-
-

-g GROUP, --group GROUP

-
The group ID to assign when binding to vfio. Use this option to specify the
-new device group for the device created in /dev/vfio.
-
-

-n, --no-sriov

-
Do not enable SR-IOV when binding to vfio. The default value for this option
-is FALSE, ie the script should specify SR-IOV functionality when binding to
-the vfio-pci driver. When omitted, the modprobe command which loads the vfio-pci
-driver will contain the `enable_sriov=1` option. When given, it will not.
-
-

-v, --version

-
Display script version information and exit.
-
-

EXAMPLES

-

opaevfio -h
-opaevfio -v
-sudo opaevfio -i -u lab -g labusers 0000:7f:00.0
-sudo opaevfio -r 0000:7f:00.0

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Pac hssi config

- -
# pac_hssi_config #
-
-## SYNOPSIS ##
-```console
-pac_hssi_config.py [-h] subcommand [subarg] [bdf]
-
-

DESCRIPTION

-

The pac_hssi_config.py tool exercises the Ethernet 10 Gbps (10GbE) and 40GbE transceivers for designs using the -Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA. This tool does not support the -Intel Xeon® Processor with Integrated FPGA.

-

PAC Ethernet Block Diagram

-

The two required arguments to the pac_hssi_config.py tool specify the subcommand and bus, device, and function (BDF) -for the PCIe device under test. You must provide the BDF parameter for systems with more than one PCIe card.

-
.. note::
-    If you do not provide the BDF when required, the command prints a list of valid BDFs for the system. You can also
-    determine the BDF using the ``lspci`` command.
-
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For usage help, type the following at a command prompt:

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pac_hssi_config.py [-h|--help]

-

To configure the network ports, send data, and read statistics, use the following form of the pac_hssi_config.py script:

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pac_hssi_config.py subcommand [subarg] [bdf]

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Only a subset of subcommand arguments support subarg.

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Table 1. General Subcommands

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SubcommandSubargDescription
statN/APrints high speed serial interface (HSSI) controller statistics.
eepromN/AReads the 128-bit unique board ID, MAC address, and board-specific IDs from EEPROM.
-

Table 2. 10/40 GbE Traffic Generation Subcommands

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SubcommandSubargDescription
e10init and e40initN/AInitializes HSSI PHY to 10GbE or 40GbE mode. Clears statistics and enable internal HSSI transceiver loopback.
e10loop and e40loopOn/OffTurns on or off internal HSSI transceiver loopback.
e10reset and e40resetOn/OffAsserts or deasserts AFU reset. Clears packet statistics and disables internal HSSI transceiver loopback.
e10send and e40sendN/ASends 1,000,000 1500-byte packets. For 10GbE sends packets on all four ports. 40GbE has a single port.
e10stat and e40statN/APrints packet statistics.
e10statclr and e40statclrN/AClears packet statistics. Use this command after switching loopback modes to clear any transient statistics accumulated during the mode switch.
-

The transceiver equalization eqwrite and eqread subcommands write and read transceiver equalization settings. -These subcommands require you to specify the transceiver channel, the equalization setting, and the value (for writes). -Use the following form for the eqwrite command:

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pac_hssi_config.py eqwrite [transceiver channel number] [equalization setting] [equalization value] [bdf]

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Use the following form for the eqreadcommand:

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pac_hssi_config.py eqread [transceiver channel number] [equalization setting] [bdf]

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Table 3. Transceiver Equalization Subcommands

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SubcommandChannel NumberEqualization SettingValue
eqwrite0-30 = Continuous time-linear equalization (CTLE)
1 = Variable gain amplifier (VGA)
2 = DCGAIN
3 = Pre-emphasis first post-tap
4 = Pre-emphasis second post-tap
5 = Pre-emphasis first pre-tap
6 = Pre-emphasis second pre-tap
7 = Differential output voltage (VOD)		Specifies the value for the specified equalization setting.
eqread0-30 = Continuous time-linear equalization (CTLE)
1 = Variable gain amplifier (VGA)
2 = DCGAIN
3 = Pre-emphasis first post-tap
4 = Pre-emphasis second post-tap
5 = Pre-emphasis first pre-tap
6 = Pre-emphasis second pre-tap
7 = Differential output voltage (VOD)		N/A
-

For more information about reconfiguring transceiver analog parameter settings In Arria® 10 devices, refer to "Changing PMA Analog -Parameters" in the -Intel® Arria® 10 Transceiver PHY User Guide.

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zW!h;BEXSM}=2@)UtngKHNx{!4!p@2gVlunyEd7rKSOAF&+aLX?^ZqkC6*x&saFN-e d`~UydXPg(DIeXGed*Hz@44$rjF6*2UngFbIOb`G7 diff --git a/sw/fpga_tools/packager/packager/index.html b/sw/fpga_tools/packager/packager/index.html deleted file mode 100644 index 66b8e0c77..000000000 --- a/sw/fpga_tools/packager/packager/index.html +++ /dev/null @@ -1,2019 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - packager - OFS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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packager

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SYNOPSIS

-

packager <cmd> [arguments]

-

Description

-

The packager provides tools that Accelerator Functional Unit (AFU) developers use to create Accelerator Function (AF) -files. The AF file is the programming file for an AFU on Intel® FPGA platforms. The packager tool concatenates -the metadata from the JSON file to a raw binary file (.rbf) that the Intel Quartus® Prime software generates.

-

The packager's only function is to create an AF file. Refer to Packager Command Syntax for more information -about invoking the packager. The packager depends on a JSON file to describe AFU metadata. Refer to -Accelerator Description File for more information about the JSON file.

-

The packager requires Python 2.7.1 and Python 2.7.3. The tool indicates if it is being called with a compatible -of Python.

-

Packager Command Syntax

-

The packager is a command line tool with the following syntax:

-

$ packager <cmd> [arguments]

-

The following table describes the <CMD> arguments:

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CommandArgumentsDescription
create-gbs--rbf=<RBF_PATH>
--afu=<AFU_JSON_PATH>
--gbs=<GBS_PATH>
--set-value=<key>.<value>		Creates the AF file. The engineering name for this file is the green bit stream, abbreviated gbs. The --rbf and --afu arguments are required. <RBF_PATH> is the path to the RBF file for the AFU. The Quartus® Prime software generates this RBF by compiling the AFU design. <AFU_JSON_PATH> is the path to the Accelerator Description file. This is a JSON file that describes the metadata that create-gbs appends to the RBF. <GBS_PATH> is the path to the RBF file for the FPGA Interface Manager (FIM) that contains the FPGA interface unit and other interfaces. If you do not specify the --gbs, the command defaults to <rbf_name>.gbs. You can use the optional --set-value=<key>.<value> argument to set values for JSON metadata. To set more than one JSON value, list a series of <key>.<value> pairs.
modify-gbs--gbs=<gbs_PATH>Modifies the AF file. The --input-gbsargument is required. If you do not provide the --output-gbs argument, modify-gbs overwrites the --input-gbs file. Use the --set-value=<key>.<value> argument to set values for JSON metadata. To set more than one JSON value, list a series of <key>.<value> pairs.
gbs-info--input-gbs=<gbs_PATH>Prints information about the AF file. The --input-gbs argument is required.
get-rbf--gbs=<GBS_PATH>
--rbf=<RBF_PATH>		Creates the RBF by extracting it from the AF file. The --gbsargument is required. If you do not specify the --rbf argument, the command defaults to <gbs_name.rbf .
None, or any <CMD>--helpSummarizes the <CMD> options. Typing packager --help gives a list of <CMD> values. Typing packager <CMD> --help provides detailed help for <CMD>
-

Examples

-

To generate an AF file, run:

-

$ packager create-gbs --rbf=<RBF_PATH> --afu=<AFU_JSON_PATH> --gbs=<GBS_PATH>

-

TIP: JSON files are very particular about syntax such as trailing commas. If you are getting errors, use jsonlint.com to -validate that your JSON is formatted correctly.

-

To modify metadata in an existing AF, run the following command:

-

$ packager modify-gbs --input-gbs=<PATH_TO_GBS_TO_BE_MODIFIED> --outputgbs=<NAME_FOR_NEW_GBS> --set-value <key>:<value>

-

You can pass in a number of : pairs with --set-value to update values in an AF.

-

To print the metadata of an existing AF:

-

$ packager get-info --gbs=<GBS_PATH>

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To extract the RBF from the AF:

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$ packager get-rbf --gbs=<GBS_PATH> --rbf=<NAME_FOR_RBF>

-

Accelerator Description File

-

The Accelerator Description File is a JSON file that describes the metadata associated with an AFU. -The Open Progammable Accelerator Engine (OPAE) uses this metadata during reconfiguration. Here is an example file:

-

{
-   "version": 1,
-   "platform-name": "DCP",
-   "afu-image": {
-      "magic-no": 488605312,
-      "interface-uuid": "01234567-89AB-CDEF-0123-456789ABCDEF",
-      "power": 0,
-      "accelerator-clusters": [{
-         "name": "dma_test_afu",
-         "total-contexts": 1,   
-         "accelerator-type-uuid": "331DB30C-9885-41EA-9081-F88B8F655CAA"
-      }
-      ]  
-   }
-}
-
-The packager stores these parameter values in the resultant AF. After reprogramming the AFU using partial reconfiguration (PR), the -software driver reconfigures the PLLs by writing the clock-frequency-high and clock-frequency-low values (if present) over the -PCIe® and CCI interfaces.

-

.. note:: -

The JSON file format may change as the architecture evolves. Any changes to the current format trigger an update
-to the version number.  
-

-

CATEGORY | NAME | TYPE | DESCRIPTION | MANDATORY ----------|------|------|-------------|:----------:| -Per-AFU | version | Integer | Version of the metadata format. | Yes -Per-AFU | magic-no (to be deprecated)| Integer | Magic no. Associated with the FPGA Interface Manager. | No -Per-AFU | platform-name | String | Name of the platform for which the metadata is intended. The field value is “DCP” for Intel Acceleration Stack for FPGAs. | No -Per-AFU | interface-uuid | UUID | Interface id associated with the FPGA Interface Manager. | Yes -Per-AFU | power | Integer | Accelerator Function power consumption, in watts. Set to 0 for Intel Acceleration Stack for FPGAs platforms. | Yes -Per-AFU | clock-frequency-low | Float | Clock frequency for 1st PLL (Clock network)1 in MHz. | No -Per-AFU | clock-frequency-high | Float | Clock frequency for 2nd PLL (0 if absent) in MHz. | No -Per-AFC Cluster | total-contexts | Integer | Number of AFCs in this cluster. Always be 1 in current architectures. | Yes -Per-AFC Cluster | afc-type-uuid | UUID | AFC type = AFU ID in current architectures. | Yes -Per-AFC Cluster | name | string | AFC name = AFU name in current architectures. | Yes

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DateIntel Acceleration Stack VersionChanges Made
2018.05.21DCP 1.1 Beta (works with Quartus Prime Pro 17.1.1)Fixed typos.
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pci_device

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SYNOPSIS

-

pci_device [-h] [-E] device-filter [{aer,bind,plug,remove,rescan,topology,unbind,unplug,vf}]

-

DESCRIPTION

-

pci_device is a tool to aid in common operations for managing PCIe devices and -drivers.

-

OPTIONS

-

POSITIONAL ARGUMENTS

-
`device filter`
-
-PCIe address of a device or vendor/device ID pair.
-The PCIe address follows the format of [segment:]bus:device.function
-while the vendor/device ID pair follows the format [vendor ID]:[device ID]
-where at least one of these must be present.
-
-`{aer,bind,plug,remove,rescan,topology,unbind,unplug,vf}`
-
-action to perform on device
-
-`aer`
-Perform AER (Advanced Error Reporting) operations.
-The aer action has its own sub-commands which are listed below:
-
-* `dump` sub-command will print out the AER error counters as reported
-   by the sysfs files for the device.
-* `mask` can either print out the current AER mask bits or set them
-  * If `show` or `print` (or nothing) is given after the `mask`
-    command, it will show the current mask bits for AER.
-By default output will be written in stdout but can be written to an
-output file if `-o|--output FILENAME` argument is given.
-  * If `all` is given after the `mask` command, it will mask all bits
-    (by setting the values to 0xffffffff and 0xffffffff).
-  * If `off` is given after the `mask` command, it will unmask all
-    bits (by setting the values to 0x0 and 0x0).
-  * If two numbers are present after the `mask` command, those two
-    numbers will be used to set the mask bits.
-Values for setting the mask can also be read in from an input file if
-`-i|--input FILENAME` argument is given.
-
-_NOTE_: mask related operations require root privileges
-
-`bind`
-
-Associate a device with its driver.
-
-`plug`
-
-Restore a device that was previously given to `pci_device <device> unplug`
-
-`remove`
-
-Remove the pci device from the pci bus
-
-`rescan`
-
-Rescan the bus as identified by the bus component of the PCIe device address
-
-'topology`
-
-Print the PCIe topology from the root port to the PCIe device.
-This shows the PCIe tree rooted at the PCIe root port.
-Each line shows the the PCIe address, vendor ID, and device ID along with
-the driver bound to the device. The indentnation is used to show
-parent/child relationship of devices.
-
-The line listing the target PCIe device as identified by the given PCIe
-address will be highlighted in green while the endpoints will be
-highlighted in cyan.
-
-The example below shows the topology of an N3000 device with eight virtual
-functions created from one of the Ethernet controllers:
-
-```console
-[pci_address(0000:3a:00.0), pci_id(0x8086, 0x2030)] (pcieport)
-    [pci_address(0000:3b:00.0), pci_id(0x10b5, 0x8747)] (pcieport)
-        [pci_address(0000:3c:09.0), pci_id(0x10b5, 0x8747)] (pcieport)
-            [pci_address(0000:3f:00.0), pci_id(0x8086, 0x0b30)] (dfl-pci)
-        [pci_address(0000:3c:11.0), pci_id(0x10b5, 0x8747)] (pcieport)
-            [pci_address(0000:43:00.0), pci_id(0x8086, 0x0b32)] (no driver)
-    [pci_address(0000:3c:08.0), pci_id(0x10b5, 0x8747)] (pcieport)
-            [pci_address(0000:3d:02.0), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:00.1), pci_id(0x8086, 0x0d58)] (i40e)
-            [pci_address(0000:3d:02.7), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:02.5), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:02.3), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:02.1), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:00.0), pci_id(0x8086, 0x0d58)] (i40e)
-            [pci_address(0000:3d:02.6), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:02.4), pci_id(0x8086, 0x154c)] (iavf)
-            [pci_address(0000:3d:02.2), pci_id(0x8086, 0x154c)] (iavf)
-        [pci_address(0000:3c:10.0), pci_id(0x10b5, 0x8747)] (pcieport)
-            [pci_address(0000:41:00.0), pci_id(0x8086, 0x0d58)] (i40e)
-            [pci_address(0000:41:00.1), pci_id(0x8086, 0x0d58)] (i40e)
-
-```
-
-`unbind`
-
-Unbind the driver bound to the device.
-
-`unplug`
-
-Remove device from PCI bus in anticipation of a RSU event by configuring its root port and associated endpoints.
-
-`vf`
-
-Create/destroy VFs (virtual functions) by setting the number here.
-The number given here will be written to sriov_numvfs sysfs file triggering
-the PCIe subsystem to create/destroy VFs so that the current number of VFs
-will be equal to the given number. If the number given is outside of the total VFs supported, an error message will be displayed to indicate this.
-
-

OPTIONAL ARGUMENTS

-
`-h, --help`
-
-show this help message and exit
-
-`-E, --other-endpoints`
-
-perform action on peer PCIe devices
-
-

EXAMPLES

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pci_device 0000:3d:00.0 remove
-pci_device 0000:3d:00.0 rescan
-pci_device 3d:00.0 topology
-pci_device :0b30 topology
-pci_device :0b30 aer
-pci_device :0b30 aer mask
-pci_device :0b30 aer mask all
-pci_device :0b30 aer mask -o mask.dat
-pci_device :0b30 aer mask -i mask.dat
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fpga_tools

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fpgainfo

-

NAME

-

fpgainfo - FPGA information tool

-

SYNOPSIS

-
fpgainfo [-h | --help] [-s | --socket-id] <command> [<args>]
-
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DESCRIPTION

-

fpgainfo is a tool to show FPGA information derived from sysfs files. The command argument -is one of the following: errors, power, temp and is used to specify what type of information -to report. Some commands may also have other arguments/options that can be used to control the -behavior of that command.

-

COMMON OPTIONS

-

--help, -h

-
Print help information and exit.
-
-

--socket-id, -s

-
Socket ID encoded in BBS. Default=0
-
-

FPGAINFO COMMANDS

-

errors

-
Show/clear errors of an FPGA resource as specified by the first argument.
-Error information is parsed to display in human readable form.
-
-

power

-
Show total power consumed by the FPGA hardware in watts
-
-

temp

-
Show FPGA temperature values in degrees Farenheit
-
-

ERRORS OPTIONS

-

--clear, -c

-
Clear errors for the given FPGA resource
-
-

ERRORS ARGUMENTS

-

The first argument to the errors command is used to specify what kind of -resource to act on. It must be one of the following: -fme,port,first_error,pcie0,pcie1,bbs,gbs,all -More details on the errors reported for the resource can be found below:

-

ERRORS RESOURCES

-

fme

-
Show/clear errors pertaining to the FME
-
-

port

-
Show/clear errors pertaining to the PORT
-
-

first_error

-
Show/clear first errors encountered by the FPGA
-
-

pcie0

-
Show/clear errors pertaining to the PCIE0 lane
-
-

pcie1

-
Show/clear errors pertaining to the PCIE1 lane
-
-

bbs

-
Show/clear errors pertaining to the BBS (blue bitstream)
-
-

gbs

-
Show/clear errors pertaining to the GBS (green bitstream)
-
-

all

-
Show/clear errors for all resources
-
-

EXAMPLES

-

This command shows the current power consumtion: -

./fpgainfo power
-

-

This command shows the current temperature reading: -

./fpgainfo temp
-

-

This command shows the errors for the FME resource: -

./fpgainfo errors fme
-
-This command clears all the errors on all resources: -
./fpgainfo errors all -c
-

-

fpgaconf

-

NAME

-

fpgadiag - Configure a green bitstream to an FPGA

-

SYNOPSIS

-

fpgaconf [-hvn] [-b <bus>] [-d <device>] [-f <function>] [-s <socket>] <gbs>

-

DESCRIPTION

-

fpgaconf writes accelerator configuration bitstreams (also referred to as "green -bitstreams" to an FPGA device recognized by OPAE. In the process, it also checks -the green bitstream file for compatibility with the targeted FPGA and its -current infrastructure bitstream (the "blue bistream"). fpgaconf takes the -following arguments:

-

-h, --help

-
Print usage information
-
-

-v, --verbose

-
Print more verbose messages while enumerating and configuring. Can be
-given more than once
-
-

-n, --dry-run

-
Perform enumeration, but skip any operations with side-effects (like the
-actual configuration of the bitstream
-
-

-b, --bus

-
PCI bus number of the FPGA to target
-
-

-d, --device

-
PCI device number of the FPGA to target
-
-

-f, --function

-
PCI function number of the FPGA to target
-
-

-s, --socket

-
Socket number of the FPGA to target
-
-

fpgaconf will enumerate available FPGA devices in the system and select -compatible FPGAs for configuration. If there are more than one candidate FPGAs -that are compatible with the given green bitstream, fpgaconf will exit and ask -you to be more specific in selecting the target FPGAs (e.g. by specifying a -socket number, or a PCIe bus/device/function).

-

EXAMPLES

-

fpgaconf my_green_bitstream.gbs

-
Program "my_green_bitstream.gbs" to a compatible FPGA
-
-

fpgaconf -v -s 0 my_green_bitstream.gbs

-
Program "my_green_bitstream.gbs" to the FPGA in socket 0, if compatible,
-while printing out slightly more verbose information
-
-

fpgad

-

NAME

-

fpgad - log errors and generate events

-

SYNOPSIS

-

fpgad --daemon [--directory=<dir>] [--logfile=<file>] [--pidfile=<file>] [--umask=<mode>] [--socket=<sock>] [--null-bitstream=<file>] -fpgad [--socket=<sock>] [--null-bitstream=<file>]

-

DESCRIPTION

-

Periodically monitors/reports the error status reflected in the device driver's error status sysfs files. -Establishes the channel by which events are communicated to the OPAE application. Programs a NULL bitstream -in response to AP6 event.

-

fpgad is required to be running before API calls fpgaRegisterEvent and fpgaUnregisterEvent will succeed.

-

Use SIGINT to stop fpgad.

-

-d, --daemon

-
When given, fpgad executes as a system demon process.
-
-

-D, --directory <dir>

-
When running in daemon mode, execute from the given directory.
-If omitted when daemonizing, /tmp is used.
-
-

-l, --logfile <file>

-
When running in daemon mode, send output to file. When not in daemon mode, the output is sent to stdout.
-If omitted when daemonizaing, /tmp/fpgad.log is used.
-
-

-p, --pidfile <file>

-
When running in daemon mode, write the daemon's process id to file.
-If omitted when daemonizing, /tmp/fpgad.pid is used.
-
-

-m, --umask <mode>

-
When running in daemon mode, use the mode value as the file mode creation mask passed to umask.
-If omitted when daemonizing, 0 is used.
-
-

-s, --socket <sock>

-
Listen for event API registration requests on sock. The default socket value used by the API is
-/tmp/fpga_event_socket.
-
-

-n, --null-bitstream <file>

-
Specify the NULL bitstream to program when an AP6 event occurs. This option may be given multiple
-times. The bitstream, if any, that matches the FPGA's PR interface id will be programmed when AP6
-is detected.
-
-

TROUBLESHOOTING

-

If any issues are encountered, try the following for additional debug information:

-
    -
  1. Examine the log file when in daemon mode.
    2. -
  2. Run in non-daemon mode and view stdout.
    3. -
-

EXAMPLES

-

fpgad --daemon --null-bitstream=my_null_bits.gbs

-

SEE ALSO

-

umask

-

fpgadiag

-

NAME

-

fpgadiag - FPGA diagnosis and testing tool.

-

SYNOPSIS

-
fpgadiag [-m | --mode=] <mode> [-t | --target=] <target> [options]
-
-

DESCRIPTION

-

fpgadiag includes several tests to diagnose, test and report on the FPGA hardware.

-

<mode> chooses which test to run. <target> specifies on what platform to -run the test. <target> can be either fpga or ase, where ase stands for -"AFU Simulation Environment".

-

The tests that can be selected by <mode> include:

-

lpbk1

-
The test performs loopback test on the number of cachelines specified with 
-the `BEGIN` option. _fpgadiag_ sets up source and  destination buffers in 
-main memory. The FPGA then performs a memcpy from a source buffer to the 
-destination buffer, one cacheline at a time.
-
-A cacheline is 64 bytes. When `BEGIN = END`, you perform one iteration. When 
-`BEGIN = END + x`, you perform `x` iterations. The first iteration consists 
-of copying `BEGIN` cachelines; the second iteration consists of copying 
-`BEGIN+1` cache lines; the third iteration consists of copying `BEGIN+3` 
-cache lines, etc.
-
-The latency is shown as the number of clock ticks.
-
-When you specify `MULTI-CL`, you copy `MULTI-CL` cache lines at a time.
-There is always a WrFence. `WR-FENCE` chooses what virtual channel the 
-WrFence occurs on.
-
-If you specify continuous mode with `--cont`, the program runs an iteration
-until the timeout specified in `TIMEOUT` completes.
-
-

read

-
This test performs only a read, not a memcpy. It is used to measure read 
-bandwidth.
-
-

write

-
This test is used to measure write bandwidth.
-
-

trput

-
This test measures both read and write bandwidth by performing 50% read and 
-50% write tests.
-
-

sw

-
This is a send-and-respond (ping-pong) test where one side sends data and 
-waits for answer.
-
-

Each test requires presence of one of these bitstreams, as documented below. -Before running a test, make sure its required bitstream is properly configured -on the platform.

-
    -
  • nlb mode 0 for the lpbk1 test.
    • -
  • nlb mode 3 for the trput, read, and write tests.
    • -
  • nlb mode 7 for the sw test.
    • -
-

OPTIONS

-

Common options

-

--help, -h

-
Print help information and exit.
-
-

--target=, -t

-
Values accepted for this switch are fpga or ase. Default=fpga
-
-

--mode=, -m

-
The test to run. Values accepted for this switch are `lpbk1`, `read`,
-`write`, `trput`, `sw`
-
-

--config=, -c

-
A configuration file in the JSON format that specifies options for a test.
-If an option is specified both in the configuration file and on the command 
-line, the value in the configuration file prevails
-
-

--socket-id=, -s

-
Socket ID encoded in BBS. Default=0
-
-

--bus-number=, -B

-
Bus number of the PCIe device. Default=0
-
-

--device=, -D

-
Device number of the PCIe device. Default=0
-
-

--function=, -F

-
Function number of the PCIe device. Default=0
-
-

--freq=, -T

-
Clock frequency in Hz. Default=400 MHz
-
-

--suppress-hdr, -S

-
Suppress column headers for text output. Default=off
-
-

--csv, -V

-
Comma separated value format. Default=off
-
-

lpbk1 test options

-

--guid=, -g

-
Accelerator ID to enumerate. Default=D8424DC4-A4A3-C413-F89E-433683F9040B
-
-

--begin=B, -b

-
1 <= B <= 65535. Default=1, B = number of cache lines
-
-

--end=E, -e

-
1 <= E <= 65535. Default=B, B and E designate number of cache lines
-
-

--multi-cl=M, -U

-
M can equal 1, 2, or 4. Default=1
-
-

--cont, -L

-
Continuous mode. Default=off
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode (microseconds portion default=0; milliseconds 
-portion default=0; seconds portion default=1; minutes portion default=0;
-hours portion default=0)
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I Default=wrline-M
-
-

--cache-hint=, -i

-
Can be rdline-I or rdline-S. Default=rdline-I
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random. Default=auto
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random. Default=auto
-
-

--wrfence-vc=, -f

-
Can be auto, vl0, vh0, vh1. Default=auto
-
-

read test options

-

--guid=, -g

-
Accelerator ID to enumerate. Default=F7DF405C-BD7A-CF72-22F1-44B0B93ACD18
-
-

--begin=B, -b

-
1 <= B <= 65535. Default=1, B = number of cache lines
-
-

--end=E, -e

-
1 <= E <= 65535. Default=B, B and E designate number of cache lines
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. Default=1
-
-

--strided-access=S, -a

-
1<= S <= 64. Default=1
-
-

--cont, -L

-
Continuous mode. Default=off
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode (microseconds portion default=0; milliseconds 
-portion default=0; seconds portion default=1; minutes portion default=0;
-hours portion default=0)
-
-

--cache-hint=, -i

-
Can be rdline-I or rdline-S. Default=rdline-I
-
-

--warm-fpga-cache -H; --cool-fpga-cache -M

-
Attempt to prime the cache with hits. Default=off, Attempt to prime the 
-cache with misses. Default=off
-
-

--cool-cpu-cache, -C

-
Attempt to prime the cpu cache with misses. Default=off
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random. Default=auto
-
-

write test options

-

--guid=, -g

-
Accelerator ID to enumerate. Default=F7DF405C-BD7A-CF72-22F1-44B0B93ACD18
-
-

--begin=B, -b

-
1 <= E <= 65535. Default=B, B and E designate number of cache lines
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. Default=1
-
-

--strided-access=S, -a

-
1<= S <= 64. Default=1
-
-

--cont, -L

-
Continuous mode. Default=off
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode (microseconds portion default=0; milliseconds 
-portion default=0; seconds portion default=1; minutes portion default=0;
-hours portion default=0)
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I Default=wrline-M
-
-

--warm-fpga-cache -H; --cool-fpga-cache -M

-
Attempt to prime the cache with hits. Default=off, Attempt to prime the 
-cache with misses. Default=off
-
-

--cool-cpu-cache, -C

-
Attempt to prime the cpu cache with misses. Default=off
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random. Default=auto
-
-

--wrfence-vc=, -f

-
Can be auto, vl0, vh0, vh1, random. Default=`WRITE-VC`
-
-

--alt-wr-pattern, -l

-
Alternate Write Pattern. Default=off
-
-

trput test options

-

--guid=, -g

-
Accelerator ID to enumerate. Default=F7DF405C-BD7A-CF72-22F1-44B0B93ACD18
-
-

--begin=B, -b

-
1 <= B <= 65535. Default=1, B = number of cache lines
-
-

--end=E, -e

-
1 <= E <= 65535. Default=B, B and E designate number of cache lines
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. Default=1
-
-

--strided-access=S, -a

-
1<= S <= 64. Default=1
-
-

--cont, -L

-
Continuous mode. Default=off
-
-

--timeout-usec=, --timeout-msec=, --timeout-sec=, --timeout-min=, --timeout-hour=

-
timeout for --cont mode (microseconds portion default=0; milliseconds 
-portion default=0; seconds portion default=1; minutes portion default=0;
-hours portion default=0)
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I Default=wrline-M
-
-

--cache-hint=, -i

-
Can be rdline-I or rdline-S. Default=rdline-I
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random. Default=auto
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random. Default=auto
-
-

--wrfence-vc=, -f

-
Can be  auto, vl0, vh0, vh1. Default=`WRITE-VC`
-
-

sw test options

-

--guid=, -g

-
Accelerator ID to enumerate. Default=7BAF4DEA-A57C-E91E-168A-455D9BDA88A3
-
-

--begin=B, -b

-
1 <= B <= 65535. Default=1, B = number of cache lines
-
-

--end=E, -e

-
1 <= E <= 65535. Default=B, B and E designate number of cache lines
-
-

--multi-cl=M, -u

-
M can equal 1, 2, or 4. Default=1
-
-

--strided-access=S, -a

-
1<= S <= 64. Default=1
-
-

--cache-policy=, -p

-
Can be wrline-I, wrline-M, or wrpush-I. Default=wrline-M
-
-

--cache-hint= -i

-
Can be rdline-I or rdline-S. Default=rdline-I
-
-

--read-vc=, -r

-
Can be auto, vl0, vh0, vh1, random Default=auto
-
-

--write-vc=, -w

-
Can be auto, vl0, vh0, vh1, random Default=auto
-
-

--wrfence-vc=, -f

-
Can be auto, vl0, vh0, vh1. Default=`WRITE-VC`
-
-

--notice=, -N

-
Can be poll, csr-write, umsg-data, or umsg-hint. Default=poll
-
-

EXAMPLES

-

This command starts an lpbk1 test on the FPGA on bus 0x5e. The test -copies 57535, 57536, 57537, ..., up to 65535 cache lines, one line at a time. -The test output is printed in the CSV format with header suppressed. -

./fpgadiag --mode=lpbk1 --target=fpga -SV --bus-number=0x5e --begin=57535
---end=65535 --cache-hint=rdline-I --cache-policy=wrpush-I --multi-cl=1
---write-vc=vl0 --read-vc=vh1 --wrfence-vc=auto
-

-

This command starts a read test on the FPGA located on bus 0xbe. The test -reads 2045 cache lines in the continuous mode with a 15-second timeout period. -Data is accessed with a strided pattern with a 10-byte stride length. -

./fpgadiag --mode=read --target=fpga -SV --bus-number=0xbe --begin=2045 --cont
---timeout-sec=15   --cache-hint=rdline-I --multi-cl=1 -a=10 --write-vc=vh1
---read-vc=auto --wrfence-vc=auto
-

-

This command starts an sw test on the FPGA located on bus 0xbe. The test -notifies completion using a CSR write. -

./fpgadiag --mode=sw --target=fpga -SV --bus-number=0xbe --begin=4 --end=8192
---cache-hint=rdline-I --cache-policy=wrline-I --notice=csr-write --write-vc=vl0
---wrfence-vc=auto --read-vc=random 
-

-

TROUBLESHOOTING

-

When a test fails to run or gives errors, check the following:

-
    -
  • Is Intel FPGA driver properly installed? -See Installation Guide -for driver installation instructions.
    • -
  • Are FPGA port permissions set properly? Check the permission bits of the -port, for example, /dev/intel-fpga-port-0. Users need READ and WRITE -permissions to run fpgadiag tests.
    • -
  • Is hugepage properly configured on the system? -See Installation Guide -for hugepage configuration steps.
    • -
  • Is the required bitstream loaded? See DESCRIPTION for -information about what bitstream is required by which test.
    • -
  • Are --begin and --end values set properly? --end must be no -smaller than the --begin. Also, --begin must be a multiple of the ---multi-cl value.
    • -
  • The --warm-fpga-cache and --cool-fpga-cache options in the read -and write tests are mutually exclusive.
    • -
  • The timeout options are only meaningful for the continuous mode -(with the --cont option).
    • -
-

mmlink

-

NAME

-

MMLink - Debugging RTL.

-

SYNOPSIS

-

mmlink [-B <bus>] [-D <device>] [-F <function>] [-S <socket>] [-P <TCP port>] [-I <IP Address>]

-

DESCRIPTION

-

Remote signaltap is software tool used for debug RTL (AFU), effectively a signal trace capability that Quartus places into a green bitstream. -Remote Signal Tap provides access the RST part of the Port MMIO space, and then runs the remote protocol on top.

-

EXAMPLES

-

./mmlink -B 0x5e -P 3333

-

MMLink app starts and listens for connection.

-

OPTIONS

-

-B,--bus FPGA Bus number.

-

-D,--device FPGA Device number.

-

-F,--functio FPGA function number.

-

-S,--socket FPGA socket number.

-

-P,--port TCP port number.

-

-I,--ip IP address of FPGA system.

-

NOTES

-

Driver privilege:

-

Change AFU driver privilege to user .

-

command: chmod 777 /dev/intel-fpga-port.0

-

set memlock:

-

command: ulimit -l 10000

-

coreidle

-

NAME

-

coreidle - idles cores for shared TDP sockets to run online cores at maximum capacity.

-

SYNOPSIS

-

coreidle [-B <bus>] [-D <device>] [-F <function>] [-S <socket>] [-G <GBS path>]

-

DESCRIPTION

-

This tools parses input GBS, extracts power from metadata ,calculates fpga power, number of online and idle cores. -It moves threads from idle cores to online cores.

-

EXAMPLES

-

./coreidle -B 0x5e -G /home/lab/gbs/mode0.gbs

-

Idle cores to run online cores at maximum capacity.

-

OPTIONS

-

-B,--bus FPGA Bus number.

-

-D,--device FPGA Device number.

-

-F,--functio FPGA function number.

-

-S,--socket FPGA socket number.

-

-G,--gbs Green bitstream file path.

-

fpgamux

-

NAME

-
fpgamux - Software MUX for running multiple AFU (accelerator functional unit) tests in one GBS (green bitsream)
-
-

SYNOPSIS

-
fpgamux [-h] [-S|--socket-id SOCKET_ID] [-B|--bus-number BUS] [-D|--device DEVICE] [-F|--function FUNCTION]
-          [-G|--guid GUID] -m|--muxfile MUXFILE.json
-
-

DESCRIPTION

-

fpgamux is a testing tool to interact with multiple AFUs that have been synthesized into one GBS along with -the CCIP-MUX BBB (basic building block). The CCIP-MUX uses upper bits in the MMIO addresses to route MMIO -reads/writes to the AFU running on the corresponding CCIP-MUX port. fpgamux uses a configuration file that -lists the software components and configuration to use.

-

.. note::

-
  Only one (the first) AFU is discoverable by the OPAE driver. Enumerating acceleration on an FPGA will find
-  the accelerator associated with the first AFU only. The first software component in the configuration will
-  be used to determine the GUID to use for enumeration. This can be overridden with the -G|--guid option.
-
-

OPTIONS

-
-S SOCKET_ID, --socket-id SOCKET_ID
-   socket id of FPGA resource
-
--B BUS, --bus BUS
-   bus id of FPGA resource
-
--D DEVICE, --device DEVICE
-   device id of FPGA resource
-
-
--F FUNCTION, --function FUNCTION
-   function id of FPGA resource
-
--G, --guid
-   specify what guid to use for the accelerator enumeration
-
-

CONFIGURATION

-

fpgamux uses a configuration file (in JSON format) to determine what software components to instantiate and -how to configure them for interacting with the AFUs in the GBS. This schema for this is listed below:

-
[
-    {
-        "app" : "fpga_app",
-        "name" : "String",
-        "config" : "Object"
-    }
-]
-
-

EXAMPLES

-

An example configuration with two components is listed below:

-
[
-    {
-        "app" : "nlb0",
-        "name" : "nlb0",
-        "config" :
-        {
-            "begin" : 1,
-            "end" : 1,
-            "multi-cl" : 1,
-            "cont" : false,
-            "cache-policy" : "wrline-M",
-            "cache-hint" : "rdline-I",
-            "read-vc" : "vh0",
-            "write-vc" : "vh1",
-            "wrfence-vc" : "write-vc",
-            "timeout-usec" : 0,
-            "timeout-msec" : 0,
-            "timeout-sec" : 1,
-            "timeout-min" : 0,
-            "timeout-hour" : 0,
-            "freq" : 400000000
-        }
-    },
-    {
-        "app" : "nlb3",
-        "name" : "nlb3",
-        "config" :
-        {
-            "mode" : "read",
-            "begin" : 1,
-            "end" : 1,
-            "multi-cl" : 1,
-            "strided-access" : 1,
-            "cont" : false,
-            "warm-fpga-cache" : false,
-            "cool-fpga-cache" : false,
-            "cool-cpu-cache" : false,
-            "cache-policy" : "wrline-M",
-            "cache-hint" : "rdline-I",
-            "read-vc" : "vh0",
-            "write-vc" : "vh1",
-            "wrfence-vc" : "write-vc",
-            "alt-wr-pattern" : false,
-            "timeout-usec" : 0,
-            "timeout-msec" : 0,
-            "timeout-sec" : 1,
-            "timeout-min" : 0,
-            "timeout-hour" : 0,
-            "freq" : 400000000
-        }
-    }
-]
-
-

userclk

-

NAME

-

userclk - to set afu high and low clock frequency.

-

SYNOPSIS

-

userclk [-B <bus>] [-D <device>] [-F <function>] [-S <socket>] [-P <Port id>] [-H <User clock high frequency>] -L <User clock low frequency>]

-

DESCRIPTION

-

userclk tool used to set high and low clock frequency to acceleration function unit.

-

EXAMPLES

-

./userclk -B 0x5e -H 400 -L 200

-

Sets AFU frequency.

-

OPTIONS

-

-B,--bus FPGA Bus number.

-

-D,--device FPGA Device number.

-

-F,--functio FPGA function number.

-

-S,--socket FPGA socket number.

-

-P,--port Port id.

-

-H,--freq-high User clock high frequency.

-

-L,--freq-low User clock low frequency.

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rsu

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SYNOPSIS

-
rsu [-h] [-d] {bmc,bmcimg,retimer,fpga,sdm,fpgadefault} [PCIE_ADDR]
-
-

DESCRIPTION

-

Mode 1: RSU

-
rsu bmc --page=(user|factory) [PCIE_ADDR]
-rsu retimer [PCIE_ADDR]
-rsu fpga --page=(user1|user2|factory) [PCIE_ADDR]
-rsu sdm --type=(sr|pr|sr_cancel|pr_cancel) [PCIE_ADDR]
-
-

Perform RSU (remote system update) operation on PAC device -given its PCIe address. -An RSU operation sends an instruction to the device to trigger -a power cycle of the card only. This will force reconfiguration -from flash for either BMC, Retimer, SDM, (on devices that support these) -or the FPGA.

-

Mode 2: Default FPGA Image

-
rsu fpgadefault --page=(user1|user2|factory) --fallback=<csv> [PCIE_ADDR]
-
-

Set the default FPGA boot sequence. The --page option determines -the primary FPGA boot image. The --fallback option allows a comma-separated -list of values to specify fallback images.

-

POSITIONAL ARGUMENTS

-

{bmc,bmcimg,retimer,fpga,sdm,fpgadefault}

-

type of RSU operation or set Default FPGA Image operation.

-

PCIE_ADDR -PCIe address of device to do rsu (e.g. 04:00.0 or 0000:04:00.0)

-

OPTIONAL ARGUMENTS

-

-h, --help -show this help message and exit

-

-d, --debug -log debug statements

-

--force -force rsu operation

-

EXAMPLE

-
# rsu bmc --page=user 25:00.0
-
-

Triggers a boot of the BMC image (user page) for the device with PCIe - address 25:00.0.

-
# rsu bmc --page=factory 25:00.0
-
-

Triggers a factory boot of the BMC image for the device with - PCIe address 25:00.0.

-
# rsu fpga --page=user2 25:00.0
-
-

Triggers a reconfiguration of the FPGA (user2 page) for the - device with PCIe address 25:00.0.

-
# rsu --force fpga --page=user2 25:00.0
-
-

Forces a reconfiguration of the FPGA (user2 page) for the - device with PCIe address 25:00.0. Default behavior is to not perform - the rsu operation if DPC (downstream port containment) is not supported - and AER (advanced error reporting) is also not supported. Using --force - changes this behavior to perform rsu operation regardless but may result - in a surprise removal of pci devices which may cause the Linux kernel - to panic.

-
# rsu fpga --page=factory 25:00.0
-
-

Triggers a factory reconfiguration of the FPGA for the device - with PCIe address 25:00.0.

-
# rsu sdm --type=sr 25:00.0
-
-

Triggers Static Region key programming for the device with - PCIE address 25:00.0.

-
# rsu fpgadefault --page=factory --fallback=user1,user2 25:00.0
-
-

Sets the FPGA boot sequence to factory with fallbacks user1, user2.

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Super Remote System Update User Guide

-
.. toctree::
-.. highlight:: c
-.. highlight:: console
-
-

Overview

-

Intel Programmable Acceleration Card (PAC) devices are comprised of multiple processors -and controllers that execute firmware. Maintaining and updating these firmware images -manually is error-prone and does not scale well within the Data Center. The solution -described here is derived with the following goals in mind:

-
    -
  • The ability to update one or more (possibly all) firwmare images with a single package.
    • -
  • The ability to complete all firmware updates within a stipulated time window.
    • -
  • The ability to update each PAC in the server, all servers in a Data Center, and multiple -Data Centers remotely.
    • -
  • The ability to remotely initiate download of the package and its installation with a -single command per server instance.
    • -
  • The ability to roll back firmware to a previous revision.
    • -
-

Implementation

-

A single package containing firmware images for all programmable parts on a PAC is delivered -as an RPM, eg opae-super-rsu-n3000.M.m.p-r.noarch.rpm. The RPM revision will sequentially increase -with every update.

-

Installing or upgrading the RPM invokes the complete update of all programmable parts on all -PAC boards in the system.

-

The standard RPM dependency framework ensures that correct versions of dependecy packages -opae-intel-fpga-driver and fpga-tools-extra are installed on the system.

-

Rolling back is achieved by uninstalling the current version and re-installing a previous -version of the RPM.

-

.. note:: -

Note: once Secure Update is deployed, roll back restrictions shall be implemented to prevent
-rollback attacks.
-

-

RPM management on remote systems is standard practice, requiring no new infrastructure/training.

-

Details

-

The post-install hook of the opae-super-rsu-n3000 RPM is leveraged to call out to the super-rsu -Python script to update all PAC boards. super-rsu uses the manifest file packaged within -opae-super-rsu-n3000 to associate a firmware image with its version. Each of the firmware images -contained in opae-super-rsu-n3000 is placed on the target system in /usr/share/opae/n3000.

-

Algorithm

-
    -
  • Acquire the current firmware versions of all programmable parts.
    • -
  • For each programmable image, if the installed version of firmware does not equal the version -provided in the RPM manifest file, then update the firmware image, and set image_updated to True.
    • -
  • After all updates, if image_updated, then initiate a safe reboot of all boards in the system.
    • -
  • After safe reboot, verify that the reported firmware versions match those of the RPM manifest. -If they do not match, then RPM installation exits with a failing status.
    • -
  • Run board self test. If the self test fails, then the RPM installation exits with a failing status.
    • -
  • If all of the above checks is successful, then RPM installation exits with a success status.
    • -
-

Dependencies

-
    -
  • The standard Python package for the distro (version 2.7).
    • -
  • The opae-intel-fpga-driver RPM. (version determined by opae-super-rsu-n3000)
    • -
  • The opae-tools-extra RPM. (version determined by opae-super-rsu-n3000)
    • -
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userclk

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SYNOPSIS

-

userclk [-hv] [-S <segment>] [-B <bus>] [-D <device>] [-F <function>] [PCI_ADDR] [-H <User clock high frequency>] -L <User clock low frequency>]

-

DESCRIPTION

-

userclk sets the frequency range for an AFU.

-

EXAMPLES

-

./userclk -B 0x5e -H 400 -L 200

-

Sets AFU frequency.

-

OPTIONS

-

-v,--version

-

Prints version information and exits.

-

-S,--segment

-

FPGA segment number.

-

-B,--bus

-

FPGA Bus number.

-

-D,--device

-

FPGA Device number.

-

-F,--function

-

FPGA function number.

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-H,--freq-high

-

User clock high frequency.

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-L,--freq-low

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User clock low frequency.

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DateIntel Acceleration Stack VersionChanges Made
2018.05.21DCP 1.1 Beta (works with Quartus Prime Pro 17.1.1)Fixed typos.
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vabtool

-

SYNOPSIS

-

vabtool [-r RETRIES] [-d] [-y] [-v] <ACTION>

-

Where ACTION is defined as one of the following:

-

vabtool sr_key_provision PCIE_ADDRESS SR_RKH_FILE FPGA_IMG_FILE
-vabtool sr_status PCIE_ADDRESS
-vabtool pr_key_provision PCIE_ADDRESS PR_AUTH_CERT_FILE PR_RKH_FILE
-vabtool pr_status PCIE_ADDRESS
-vabtool sr_key_cancel PCIE_ADDRESS SR_RKH_CANCEL_FILE
-vabtool sr_cancel_status PCIE_ADDRESS
-vabtool pr_key_cancel PCIE_ADDRESS PR_RKH_CANCEL_FILE
-vabtool pr_cancel_status PCIE_ADDRESS

-

DESCRIPTION

-

The vabtool command helps perform Vendor Authenticated Boot -provisioning of Static Region and Partial Reconfiguration Region key -hashes and helps perform SR and PR hash cancellation and status reporting.

-

OPTIONS

-

-r RETRIES, --retries RETRIES

-
Specifies the number of times a failed SR or PR key provision is to be
-retried. The default value for RETRIES is 3.
-
-

-d, --dry-run

-
Don't execute the actual fpgasupdate and rsu commands, but only print
-the commands that would be executed during a normal run of the script.
-
-

-y, --yes

-
The tool will respond with an automatic Yes answer to all confirmation
-prompts posed by the sub-tools.
-
-

-v, --version

-
Display script version information and exit.
-
-

EXAMPLES

-

sudo vabtool -y sr_key_provision 0000:bc:00.0 my_sr_rkh.bin my_fpga.bin
-sudo vabtool sr_status 0000:bc:00.0
-sudo vabtool -y pr_key_provision 0000:bc:00.0 pr_auth_cert.bin my_pr_rkh.bin
-sudo vabtool pr_status 0000:bc:00.0
-sudo vabtool sr_key_cancel 0000:bc:00.0 my_sr_rhk_cancel.bin
-sudo vabtool sr_cancel_status 0000:bc:00.0
-sudo vabtool pr_key_cancel 0000:bc:00.0 my_pr_rhk_cancel.bin
-sudo vabtool pr_cancel_status 0000:bc:00.0

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- - - - - - - - - \ No newline at end of file diff --git a/sw/include/opae/access.h b/sw/include/opae/access.h deleted file mode 100644 index 6518ccc8f..000000000 --- a/sw/include/opae/access.h +++ /dev/null @@ -1,108 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file access.h - * @brief Functions to acquire, release, and reset OPAE FPGA resources - */ - -#ifndef __FPGA_ACCESS_H__ -#define __FPGA_ACCESS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Open an FPGA object - * - * Acquires ownership of the FPGA resource referred to by 'token'. - * - * Most often this will be used to open an accelerator object to directly interact - * with an accelerator function, or to open an FPGA object to perform - * management functions. - * - * @param[in] token Pointer to token identifying resource to acquire - * ownership of - * @param[out] handle Pointer to preallocated memory to place a handle in. - * This handle will be used in subsequent API calls. - * @param[in] flags One of the following flags: - * * FPGA_OPEN_SHARED allows the resource to be opened - * multiple times (not supported in ASE) - * Shared resources (including buffers) are released - * when all associated handles have been closed - * (either explicitly with fpgaClose() or by process - * termination). - * @returns FPGA_OK on success. FPGA_NOT_FOUND if the resource for - * 'token' could not be found. FPGA_INVALID_PARAM if - * 'token' does not refer to a resource that can be - * opened, or if either argument is NULL or invalid. - * FPGA_EXCEPTION if an internal exception occurred while - * creating the handle. FPGA_NO_DRIVER if the driver is - * not loaded. FPGA_BUSY if trying to open a resource that - * has already been opened in exclusive mode. - * FPGA_NO_ACCESS if the current process' privileges are - * not sufficient to open the resource. - */ -fpga_result fpgaOpen(fpga_token token, fpga_handle *handle, - int flags); - -/** - * Close a previously opened FPGA object - * - * Relinquishes ownership of a previously fpgaOpen()ed resource. This enables - * others to acquire ownership if the resource was opened exclusively. - * Also deallocates / unmaps MMIO and UMsg memory areas. - * - * @param[in] handle Handle to previously opened FPGA object - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does - * not refer to an acquired resource, or if handle is NULL. - * FPGA_EXCEPTION if an internal error occurred while - * accessing the handle. - */ -fpga_result fpgaClose(fpga_handle handle); - -/** - * Reset an FPGA object - * - * Performs an accelerator reset. - * - * @param[in] handle Handle to previously opened FPGA object - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does - * not refer to an acquired resource or to a resource that - * cannot be reset. FPGA_EXCEPTION if an internal error - * occurred while trying to access the handle or resetting - * the resource. - */ -fpga_result fpgaReset(fpga_handle handle); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_ACCESS_H__ diff --git a/sw/include/opae/buffer.h b/sw/include/opae/buffer.h deleted file mode 100644 index bd200cfef..000000000 --- a/sw/include/opae/buffer.h +++ /dev/null @@ -1,142 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file buffer.h - * @brief Functions for allocating and sharing system memory with an FPGA - * accelerator - * - * To share memory between a software application and an FPGA accelerator, - * these functions set up system components (e.g. an IOMMU) to allow - * accelerator access to a provided memory region. - * - * There are a number of restrictions on what memory can be shared, depending - * on platform capabilities. Usually, FPGA accelerators to not have access to - * virtual address mappings of the CPU, so they can only access physical - * addresses. To support this, the OPAE C library on Linux uses hugepages to - * allocate large, contiguous pages of physical memory that can be shared with - * an accelerator. It also supports sharing memory that has already been - * allocated by an application, as long as that memory satisfies the - * requirements of being physically contigous and page-aligned. - */ - -#ifndef __FPGA_BUFFER_H__ -#define __FPGA_BUFFER_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Prepare a shared memory buffer - * - * Prepares a memory buffer for shared access between an accelerator and the calling - * process. This may either include allocation of physical memory, or - * preparation of already allocated memory for sharing. The latter case is - * indicated by supplying the FPGA_BUF_PREALLOCATED flag. - * - * This function will ask the driver to pin the indicated memory (make it - * non-swappable), and program the IOMMU to allow access from the accelerator. If the - * buffer was not pre-allocated (flag FPGA_BUF_PREALLOCATED), the function - * will also allocate physical memory of the requested size and map the - * memory into the caller's process' virtual address space. It returns in - * 'wsid' an fpga_buffer object that can be used to program address registers - * in the accelerator for shared access to the memory. - * - * When using FPGA_BUF_PREALLOCATED, the input len must be a non-zero multiple - * of the page size, else the function returns FPGA_INVALID_PARAM. When not - * using FPGA_BUF_PREALLOCATED, the input len is rounded up to the nearest - * multiple of page size. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] len Length of the buffer to allocate/prepare in bytes - * @param[inout] buf_addr Virtual address of buffer. Contents may be NULL (OS - * will choose mapping) or non-NULL (OS will take - * contents as a hint for the virtual address). - * @param[out] wsid Handle to the allocated/prepared buffer to be used - * with other functions - * @param[in] flags Flags. FPGA_BUF_PREALLOCATED indicates that memory - * pointed at in '*buf_addr' is already allocated an - * mapped into virtual memory. FPGA_BUF_READ_ONLY - * pins pages with only read access from the FPGA. - * @returns FPGA_OK on success. FPGA_NO_MEMORY if the requested memory could - * not be allocated. FPGA_INVALID_PARAM if invalid parameters were provided, or - * if the parameter combination is not valid. FPGA_EXCEPTION if an internal - * exception occurred while trying to access the handle. - * - * @note As a special case, when FPGA_BUF_PREALLOCATED is present in flags, - * if len == 0 and buf_addr == NULL, then the function returns FPGA_OK if - * pre-allocated buffers are supported. In this case, a return value other - * than FPGA_OK indicates that pre-allocated buffers are not supported. - */ -fpga_result fpgaPrepareBuffer(fpga_handle handle, - uint64_t len, - void **buf_addr, uint64_t *wsid, int flags); - -/** - * Release a shared memory buffer - * - * Releases a previously prepared shared buffer. If the buffer was allocated - * using fpgaPrepareBuffer (FPGA_BUF_PREALLOCATED was not specified), this call - * will deallocate/free that memory. Otherwise, it will only be returned to - * it's previous state (pinned/unpinned, cached/non-cached). - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] wsid Handle to the allocated/prepared buffer - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if invalid parameters were - * provided, or if the parameter combination is not valid. FPGA_EXCEPTION if an - * internal exception occurred while trying to access the handle. - */ -fpga_result fpgaReleaseBuffer(fpga_handle handle, uint64_t wsid); - -/** - * Retrieve base IO address for buffer - * - * This function is used to acquire the physical base address (on some platforms - * called IO Virtual Address or IOVA) for a shared buffer identified by wsid. - * - * @note This function will disappear once the APIs for secure sharing of - * buffer addresses is implemented. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] wsid Buffer handle / workspace ID referring to the buffer for - * which the IO address is requested - * @param[out] ioaddr Pointer to memory where the IO address will be returned - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if invalid parameters were - * provided, or if the parameter combination is not valid. FPGA_EXCEPTION if an - * internal exception occurred while trying to access the handle. - * FPGA_NOT_FOUND if `wsid` does not refer to a previously shared buffer. - */ -fpga_result fpgaGetIOAddress(fpga_handle handle, uint64_t wsid, - uint64_t *ioaddr); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_BUFFER_H__ diff --git a/sw/include/opae/cxx/core.h b/sw/include/opae/cxx/core.h deleted file mode 100644 index 458c584a8..000000000 --- a/sw/include/opae/cxx/core.h +++ /dev/null @@ -1,35 +0,0 @@ -// Copyright(c) 2020, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include -#include -#include -#include -#include -#include -#include -#include diff --git a/sw/include/opae/cxx/core/errors.h b/sw/include/opae/cxx/core/errors.h deleted file mode 100644 index 814b8d35b..000000000 --- a/sw/include/opae/cxx/core/errors.h +++ /dev/null @@ -1,101 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once - -#include -#include - -#include - -namespace opae { -namespace fpga { -namespace types { - -/** - * @brief An error object represents an error register for a resource. - * This is used to read out the raw value in the register. No parsing is - * done by this class. - */ -class error { - public: - typedef std::shared_ptr ptr_t; - - error(const error &e) = delete; - - error &operator=(const error &e) = delete; - - /** - * @brief Factory function for creating an error object. - * - * @param tok The token object representing a resource. - * @param num The index of the error register. This must be lower than the - * num_errors property of the resource. - * - * @return A shared_ptr containing the error object - */ - static error::ptr_t get(token::ptr_t tok, uint32_t num); - - /** - * @brief Get the error register name. - * - * @return A std::string object set to the error name. - */ - std::string name() { return error_info_.name; } - - /** - * @brief Indicates whether an error register can be cleared. - * - * @return A boolean value indicating if the error register can be cleared. - */ - bool can_clear() { return error_info_.can_clear; } - - /** - * @brief Read the raw value contained in the associated error register. - * - * @return A 64-bit value (unparsed) read from the error register - */ - uint64_t read_value(); - - ~error() {} - - /** - * @brief Get the C data structure - * - * @return The fpga_error_info that contains the name and the can_clear - * boolean. - */ - fpga_error_info c_type() const { return error_info_; } - - private: - error(token::ptr_t token, uint32_t num); - token::ptr_t token_; - fpga_error_info error_info_; - uint32_t error_num_; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/events.h b/sw/include/opae/cxx/core/events.h deleted file mode 100644 index 481e31ca2..000000000 --- a/sw/include/opae/cxx/core/events.h +++ /dev/null @@ -1,112 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once - -#include -#include - -#include - -namespace opae { -namespace fpga { -namespace types { - -/** - * @brief Wraps fpga event routines in OPAE C - */ -class event { - public: - typedef std::shared_ptr ptr_t; - - /** - * @brief Destroy event and associated resources - */ - virtual ~event(); - - /** - * @brief C++ struct that is interchangeable with fpga_event_type enum - */ - struct type_t { - type_t(fpga_event_type c_type) : type_(c_type) {} - - operator fpga_event_type() { return type_; } - - static constexpr fpga_event_type interrupt = FPGA_EVENT_INTERRUPT; - static constexpr fpga_event_type error = FPGA_EVENT_ERROR; - static constexpr fpga_event_type power_thermal = FPGA_EVENT_POWER_THERMAL; - - private: - fpga_event_type type_; - }; - - /** - * @brief Get the fpga_event_handle contained in this object - * - * @return The fpga_event_handle contained in this object - */ - fpga_event_handle get() { return event_handle_; } - - /** - * @brief Coversion operator for converting to fpga_event_handle objects - * - * @return The fpga_event_handle contained in this object - */ - operator fpga_event_handle(); - - /** - * @brief Factory function to create event objects - * - * @param h A shared ptr of a resource handle - * @param t The resource type - * @param flags Event registration flags passed on to fpgaRegisterEvent - * - * @return A shared ptr to an event object - */ - static event::ptr_t register_event(handle::ptr_t h, event::type_t t, - int flags = 0); - - /** - * @brief Get OS Object from the event object - * - * Get an OS specific object from the event which can be used to subscribe for - * events. On Linux, the object corresponds to a file descriptor that can be - * used with select/poll/epoll calls. - * - * @return An integer object representing the OS object - */ - int os_object() const; - - private: - event(handle::ptr_t h, event::type_t t, fpga_event_handle event_h); - handle::ptr_t handle_; - event::type_t type_; - fpga_event_handle event_handle_; - int os_object_; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/except.h b/sw/include/opae/cxx/core/except.h deleted file mode 100644 index 36e185a29..000000000 --- a/sw/include/opae/cxx/core/except.h +++ /dev/null @@ -1,340 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include - -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -/// Identify a particular line in a source file. -class src_location { - public: - /** src_location constructor - * @param[in] file The source file name, typically __FILE__. - * @param[in] fn The current function, typically __func__. - * @param[in] line The current line number, typically __LINE__. - */ - src_location(const char *file, const char *fn, int line) noexcept; - - src_location(const src_location &other) noexcept; - - src_location &operator=(const src_location &other) noexcept; - - /** Retrieve the file name component of the location. - */ - const char *file() const noexcept; - - /** Retrieve the function name component of the location. - */ - const char *fn() const noexcept { return fn_; } - - /** Retrieve the line number component of the location. - */ - int line() const noexcept { return line_; } - - private: - const char *file_; - const char *fn_; - int line_; -}; - -/// Construct a src_location object for the current source line. -#define OPAECXX_HERE \ - opae::fpga::types::src_location(__FILE__, __func__, __LINE__) - -/** Generic OPAE exception - * - * An except tracks the source line of origin - * and an optional fpga_result. If no fpga_result - * is given, then FPGA_EXCEPTION is used. - */ -class except : public std::exception { - public: - static const std::size_t MAX_EXCEPT = 256; - - /** except constructor - * The fpga_result value is FPGA_EXCEPTION. - * - * @param[in] loc Location where the exception was constructed. - */ - except(src_location loc) noexcept; - - /** except constructor - * - * @param[in] res The fpga_result value associated with this exception. - * @param[in] loc Location where the exception was constructed. - */ - except(fpga_result res, src_location loc) noexcept; - - /** except constructor - * - * @param[in] res The fpga_result value associated with this exception. - * @param[in] msg The error message as a string - * @param[in] loc Location where the exception was constructed. - */ - except(fpga_result res, const char *msg, src_location loc) noexcept; - - /** Convert this except to an informative string. - */ - virtual const char *what() const noexcept override; - - /** Convert this except to its fpga_result. - */ - operator fpga_result() const noexcept { return res_; } - - protected: - fpga_result res_; - const char *msg_; - src_location loc_; - mutable char buf_[MAX_EXCEPT]; -}; - -/** invalid_param exception - * - * invalid_param tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_INVALID_PARAM is returned from a call to - * an OPAE C API function - */ -class invalid_param : public except { - public: - /** invalid_param constructor - * - * @param[in] loc Location where the exception was constructed. - */ - invalid_param(src_location loc) noexcept - : except(FPGA_INVALID_PARAM, "failed with return code FPGA_INVALID_PARAM", - loc) {} -}; - -/** busy exception - * - * busy tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_BUSY is returned from a call to - * an OPAE C API function - */ -class busy : public except { - public: - /** busy constructor - * - * @param[in] loc Location where the exception was constructed. - */ - busy(src_location loc) noexcept - : except(FPGA_BUSY, "failed with return code FPGA_BUSY", loc) {} -}; - -/** exception exception - * - * exception tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_EXCEPTION is returned from a call to - * an OPAE C API function - */ -class exception : public except { - public: - /** exception constructor - * - * @param[in] loc Location where the exception was constructed. - */ - exception(src_location loc) noexcept - : except(FPGA_EXCEPTION, "failed with return code FPGA_EXCEPTION", loc) {} -}; - -/** not_found exception - * - * not_found tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_NOT_FOUND is returned from a call to - * an OPAE C API function - */ -class not_found : public except { - public: - /** not_found constructor - * - * @param[in] loc Location where the exception was constructed. - */ - not_found(src_location loc) noexcept - : except(FPGA_NOT_FOUND, "failed with return code FPGA_NOT_FOUND", loc) {} -}; - -/** no_memory exception - * - * no_memory tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_NO_MEMORY is returned from a call to - * an OPAE C API function - */ -class no_memory : public except { - public: - /** no_memory constructor - * - * @param[in] loc Location where the exception was constructed. - */ - no_memory(src_location loc) noexcept - : except(FPGA_NO_MEMORY, "failed with return code FPGA_NO_MEMORY", loc) {} -}; - -/** not_supported exception - * - * not_supported tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_NOT_SUPPORTED is returned from a call to - * an OPAE C API function - */ -class not_supported : public except { - public: - /** not_supported constructor - * - * @param[in] loc Location where the exception was constructed. - */ - not_supported(src_location loc) noexcept - : except(FPGA_NOT_SUPPORTED, "failed with return code FPGA_NOT_SUPPORTED", - loc) {} -}; - -/** no_driver exception - * - * no_driver tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_NO_DRIVER is returned from a call to - * an OPAE C API function - */ -class no_driver : public except { - public: - /** no_driver constructor - * - * @param[in] loc Location where the exception was constructed. - */ - no_driver(src_location loc) noexcept - : except(FPGA_NO_DRIVER, "failed with return code FPGA_NO_DRIVER", loc) {} -}; - -/** no_daemon exception - * - * no_daemon tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_NO_DAEMON is returned from a call to - * an OPAE C API function - */ -class no_daemon : public except { - public: - /** no_daemon constructor - * - * @param[in] loc Location where the exception was constructed. - */ - no_daemon(src_location loc) noexcept - : except(FPGA_NO_DAEMON, "failed with return code FPGA_NO_DAEMON", loc) {} -}; - -/** no_access exception - * - * no_access tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_NO_ACCESS is returned from a call to - * an OPAE C API function - */ -class no_access : public except { - public: - /** no_access constructor - * - * @param[in] loc Location where the exception was constructed. - */ - no_access(src_location loc) noexcept - : except(FPGA_NO_ACCESS, "failed with return code FPGA_NO_ACCESS", loc) {} -}; - -/** reconf_error exception - * - * reconf_error tracks the source line of origin - * for exceptions thrown when the error code - * FPGA_RECONF_ERROR is returned from a call to - * an OPAE C API function - */ -class reconf_error : public except { - public: - /** reconf_error constructor - * - * @param[in] loc Location where the exception was constructed. - */ - reconf_error(src_location loc) noexcept - : except(FPGA_RECONF_ERROR, "failed with return code FPGA_RECONF_ERROR", - loc) {} -}; - -namespace detail { - -/** typedef function pointer that returns bool if result is FPGA_OK - */ -typedef bool (*exception_fn)(fpga_result, - const opae::fpga::types::src_location &loc); - -/** is_ok is a template function that throws an excpetion of its template - * argument type - * if the result code is not FPGA_OK. Otherwise it returns true. - */ -template -constexpr bool is_ok(fpga_result result, - const opae::fpga::types::src_location &loc) { - return result == FPGA_OK ? true : throw T(loc); -} - -static exception_fn opae_exceptions[12] = { - is_ok, - is_ok, - is_ok, - is_ok, - is_ok, - is_ok, - is_ok, - is_ok, - is_ok, - is_ok}; - -static inline void assert_fpga_ok(fpga_result result, - const opae::fpga::types::src_location &loc) { - if (result > FPGA_OK && result <= FPGA_RECONF_ERROR) - // our exception table above starts at invalid_param with index 0 - // but FPGA_INVALID_PARAM is actually enum 1 - let's account for that - opae_exceptions[result - 1](result, loc); -} - -} // end of namespace detail - -/// Macro to check of result is FPGA_OK -/// If not, throw exception that corresponds -/// to the result code -#define ASSERT_FPGA_OK(r) \ - opae::fpga::types::detail::assert_fpga_ok( \ - r, opae::fpga::types::src_location(__FILE__, __func__, __LINE__)); - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/handle.h b/sw/include/opae/cxx/core/handle.h deleted file mode 100644 index 4c5013201..000000000 --- a/sw/include/opae/cxx/core/handle.h +++ /dev/null @@ -1,198 +0,0 @@ -// Copyright(c) 2018-2021, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include -#include - -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -/** An allocated accelerator resource - * - * Represents an accelerator resource that has - * been allocated by OPAE. Depending on the type - * of resource, its register space may be - * read/written using a handle object. - */ -class handle { - public: - typedef std::shared_ptr ptr_t; - - handle(const handle &) = delete; - handle &operator=(const handle &) = delete; - - virtual ~handle(); - - /** Retrieve the underlying OPAE handle. - */ - fpga_handle c_type() const { return handle_; } - - /** Retrieve the underlying OPAE handle. - */ - operator fpga_handle() const { return handle_; } - - /** - * @brief Load a bitstream into an FPGA slot - * - * @param slot The slot number to program - * @param bitstream The bitstream binary data - * @param size The size of the bitstream - * @param flags Flags that control behavior of reconfiguration. - * Value of 0 indicates no flags. FPGA_RECONF_FORCE - * indicates that the bitstream is programmed into - * the slot without checking if the resource is - * currently in use. - * - * @throws invalid_param if the handle is not an FPGA device handle - * or if the other parameters are not valid. - * @throws exception if an internal error is encountered. - * @throws busy if the accelerator for the given slot is in use. - * @throws reconf_error if errors are reported by the driver - * (CRC or protocol errors). - */ - void reconfigure(uint32_t slot, const uint8_t *bitstream, size_t size, - int flags); - - /** - * @brief Read 32 bits from a CSR belonging to a resource associated - * with a handle. - * - * @param[in] offset The register offset - * @param[in] csr_space The CSR space to read from. Default is 0. - * - * @return The 32-bit value read from the CSR - */ - uint32_t read_csr32(uint64_t offset, uint32_t csr_space = 0) const; - - /** - * @brief Write 32 bit to a CSR belonging to a resource associated - * with a handle. - * - * @param[in] offset The register offset. - * @param[in] value The 32-bit value to write to the register. - * @param[in] csr_space The CSR space to read from. Default is 0. - * - */ - void write_csr32(uint64_t offset, uint32_t value, uint32_t csr_space = 0); - - /** - * @brief Read 64 bits from a CSR belonging to a resource associated - * with a handle. - * - * @param[in] offset The register offset - * @param[in] csr_space The CSR space to read from. Default is 0. - * - * @return The 64-bit value read from the CSR - */ - uint64_t read_csr64(uint64_t offset, uint32_t csr_space = 0) const; - - /** - * @brief Write 64 bits to a CSR belonging to a resource associated - * with a handle. - * - * @param[in] offset The register offset. - * @param[in] value The 64-bit value to write to the register. - * @param[in] csr_space The CSR space to read from. Default is 0. - * - */ - void write_csr64(uint64_t offset, uint64_t value, uint32_t csr_space = 0); - - /** - * @brief Write 512 bits to a CSR belonging to a resource associated - * with a handle. - * - * @param[in] offset The register offset. - * @param[in] value Pointer to the 512-bit value to write to the register. - * @param[in] csr_space The CSR space to read from. Default is 0. - * - */ - void write_csr512(uint64_t offset, const void *value, uint32_t csr_space = 0); - - /** Retrieve a pointer to the MMIO region. - * @param[in] offset The byte offset to add to MMIO base. - * @param[in] csr_space The desired CSR space. Default is 0. - * @return MMIO base + offset - */ - uint8_t *mmio_ptr(uint64_t offset, uint32_t csr_space = 0) const; - - /** Open an accelerator resource, given a raw fpga_token - * - * @param[in] token A token describing the accelerator - * resource to be allocated. - * - * @param[in] flags The flags parameter to fpgaOpen(). - * - * @return pointer to the mmio base + offset for the given - * csr space - * - */ - static handle::ptr_t open(fpga_token token, int flags); - - /** Open an accelerator resource, given a token object - * - * @param[in] token A token object describing the - * accelerator resource to be allocated. - * - * @param[in] flags The flags parameter to fpgaOpen(). - * - * @return shared ptr to a handle object - */ - static handle::ptr_t open(token::ptr_t token, int flags); - - /** Reset the accelerator identified by this handle - */ - virtual void reset(); - - /** Close an accelerator resource (if opened) - * - * @return fpga_result indication the result of closing the - * handle or FPGA_EXCEPTION if handle is not opened - * - * @note This is available for explicitly closing a handle. - * The destructor for handle will call close. - */ - fpga_result close(); - - /** Retrieve the token corresponding to this handle - * object. - */ - token::ptr_t get_token() const; - - private: - handle(fpga_handle h); - - fpga_handle handle_; - fpga_token token_; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/properties.h b/sw/include/opae/cxx/core/properties.h deleted file mode 100644 index 17d045098..000000000 --- a/sw/include/opae/cxx/core/properties.h +++ /dev/null @@ -1,143 +0,0 @@ -// Copyright(c) 2018-2022, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include - -#include -#include -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -class token; -class handle; -/** Wraps an OPAE fpga_properties object. - * - * properties are information describing an - * accelerator resource that is identified by - * its token. The properties are used during - * enumeration to narrow the search for an - * accelerator resource, and after enumeration - * to provide the configuration of that - * resource. - */ -class properties { - public: - typedef std::shared_ptr ptr_t; - - /** An empty vector of properties. - * Useful for enumerating based on a - * "match all" criteria. - */ - const static std::vector none; - - properties(const properties &p) = delete; - - properties &operator=(const properties &p) = delete; - - ~properties(); - - /** Get the underlying fpga_properties object. - */ - fpga_properties c_type() const { return props_; } - - /** Get the underlying fpga_properties object. - */ - operator fpga_properties() const { return props_; } - - /** Create a new properties object. - * @return A properties smart pointer. - */ - static properties::ptr_t get(); - - /** Create a new properties object from a guid. - * @param guid_in A guid to set in the properties - * @return A properties smart pointer with its guid initialized to guid_in - */ - static properties::ptr_t get(fpga_guid guid_in); - - /** Create a new properties object from an fpga_objtype. - * @param objtype An object type to set in the properties - * @return A properties smart pointer with its object type set to objtype. - */ - static properties::ptr_t get(fpga_objtype objtype); - - /** Retrieve the properties for a given token object. - * @param[in] t A token identifying the accelerator resource. - * @return A properties smart pointer for the given token. - */ - static properties::ptr_t get(std::shared_ptr t); - - /** Retrieve the properties for a given fpga_token. - * @param[in] t An fpga_token identifying the accelerator resource. - * @return A properties smart pointer for the given fpga_token. - */ - static properties::ptr_t get(fpga_token t); - - /** Retrieve the properties for a given handle object. - * @param[in] h A handle identifying the accelerator resource. - * @return A properties smart pointer for the given handle. - */ - static properties::ptr_t get(std::shared_ptr h); - - private: - properties(bool alloc_props = true); - fpga_properties props_; - - public: - pvalue type; - pvalue num_errors; - pvalue segment; - pvalue bus; - pvalue device; - pvalue function; - pvalue socket_id; - pvalue num_slots; - pvalue bbs_id; - pvalue bbs_version; - pvalue vendor_id; - pvalue device_id; - pvalue subsystem_vendor_id; - pvalue subsystem_device_id; - pvalue model; - pvalue local_memory_size; - pvalue capabilities; - pvalue num_mmio; - pvalue num_interrupts; - pvalue accelerator_state; - pvalue object_id; - pvalue parent; - pvalue interface; - guid_t guid; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/pvalue.h b/sw/include/opae/cxx/core/pvalue.h deleted file mode 100644 index b8fa2f511..000000000 --- a/sw/include/opae/cxx/core/pvalue.h +++ /dev/null @@ -1,278 +0,0 @@ -// Copyright(c) 2018-2020, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -/** Representation of the guid member of a properties object. - */ -struct guid_t { - /** Construct the guid_t given its containing fpga_properties. - */ - guid_t(fpga_properties *p) : props_(p), is_set_(false) {} - - /** Update the local cached copy of the guid. - */ - void update() { - fpga_result res = fpgaPropertiesGetGUID( - *props_, reinterpret_cast(data_.data())); - ASSERT_FPGA_OK(res); - is_set_ = true; - } - - /** Return a raw pointer to the guid. - * @retval nullptr if the guid could not be queried. - */ - operator uint8_t *() { - update(); - return data_.data(); - } - - /** Return a raw pointer to the guid. - */ - const uint8_t *c_type() const { return data_.data(); } - - /** Assign from fpga_guid - * Sets the guid field of the associated properties - * object using the OPAE properties API. - * @param[in] g The given fpga_guid. - * @return a reference to this guid_t. - */ - guid_t &operator=(fpga_guid g) { - is_set_ = false; - ASSERT_FPGA_OK(fpgaPropertiesSetGUID(*props_, g)); - is_set_ = true; - uint8_t *begin = &g[0]; - uint8_t *end = begin + sizeof(fpga_guid); - std::copy(begin, end, data_.begin()); - return *this; - } - - /** Compare contents with an fpga_guid. - * @retval The result of memcmp of the two objects. - */ - bool operator==(const fpga_guid &g) { - return is_set() && (0 == std::memcmp(data_.data(), g, sizeof(fpga_guid))); - } - - /** Convert a string representation of a guid to binary. - * @param[in] str The guid string. - */ - void parse(const char *str) { - is_set_ = false; - if (0 != uuid_parse(str, data_.data())) { - throw except(OPAECXX_HERE); - } - ASSERT_FPGA_OK(fpgaPropertiesSetGUID(*props_, data_.data())); - is_set_ = true; - } - - /** Send the string representation of the guid_t to the given stream. - */ - friend std::ostream &operator<<(std::ostream &ostr, const guid_t &g) { - fpga_properties props = *g.props_; - fpga_guid guid_value; - fpga_result res; - if ((res = fpgaPropertiesGetGUID(props, &guid_value)) == FPGA_OK) { - char guid_str[84]; - uuid_unparse(guid_value, guid_str); - ostr << guid_str; - } else if (FPGA_NOT_FOUND == res) { - std::cerr << "[guid_t::<<] GUID property not set\n"; - } else { - ASSERT_FPGA_OK(res); - } - return ostr; - } - - /** Tracks whether the cached local copy of the guid is valid. - */ - bool is_set() const { return is_set_; } - - /** Invalidate the cached local copy of the guid. - */ - void invalidate() { is_set_ = false; } - - private: - fpga_properties *props_; - bool is_set_; - std::array data_; -}; - -/** - * @brief Wraps OPAE properties defined in the OPAE C API - * by associating an `fpga_properties` reference - * with the getters and setters defined for a property - * - * @tparam T The type of the property value being wrapped - */ -template -struct pvalue { - /** - * @brief Define getter function as getter_t - * For `char*` types, do not use T* as the second argument - * but instead use T - */ - typedef typename std::conditional< - std::is_same::value, fpga_result (*)(fpga_properties, T), - fpga_result (*)(fpga_properties, T *)>::type getter_t; - - /** - * @brief Define the setter function as setter_t - * - */ - typedef fpga_result (*setter_t)(fpga_properties, T); - - /** - * @brief Define the type of our copy variable - * For `char*` types use std::string as the copy - */ - typedef typename std::conditional::value, - typename std::string, T>::type copy_t; - - pvalue() : props_(0), is_set_(false), get_(nullptr), set_(nullptr), copy_() {} - - /** - * @brief pvalue contructor that takes in a reference to fpga_properties - * and corresponding accessor methods for a property - * - * @param p A reference to an fpga_properties - * @param g The getter function - * @param s The setter function - */ - pvalue(fpga_properties *p, getter_t g, setter_t s) - : props_(p), is_set_(false), get_(g), set_(s), copy_() {} - - /** - * @brief Overload of `=` operator that calls the wrapped setter - * - * @param v The value to set - * - * @return A reference to itself - */ - pvalue &operator=(const T &v) { - is_set_ = false; - ASSERT_FPGA_OK(set_(*props_, v)); - is_set_ = true; - copy_ = v; - return *this; - } - - /** - * @brief Compare a property for equality with a value - * - * @param other The value being compared to - * - * @return Whether or not the property is equal to the value - */ - bool operator==(const T &other) { return is_set() && (copy_ == other); } - - void update() { - ASSERT_FPGA_OK(get_(*props_, ©_)); - is_set_ = true; - } - - /** - * @brief Implicit converter operator - calls the wrapped getter - * - * @return The property value after calling the getter or a default - * value of the value type - */ - operator copy_t() { - update(); - return copy_; - } - - // TODO: Remove this once all properties are tested - fpga_result get_value(T &value) const { return get_(*props_, &value); } - - /** - * @brief Stream overalod operator - * - * @param ostr The output stream - * @param p A reference to a pvalue object - * - * @return The stream operator after streaming the property value - */ - friend std::ostream &operator<<(std::ostream &ostr, const pvalue &p) { - T value; - fpga_properties props = *p.props_; - fpga_result res; - if ((res = p.get_(props, &value)) == FPGA_OK) { - ostr << +(value); - } else if (FPGA_NOT_FOUND == res) { - std::cerr << "property getter returned (" << res << ") " - << fpgaErrStr(res); - } else { - ASSERT_FPGA_OK(res); - } - return ostr; - } - - /** Tracks whether the cached local copy of the pvalue is valid. - */ - bool is_set() const { return is_set_; } - - /** Invalidate the cached local copy of the pvalue. - */ - void invalidate() { is_set_ = false; } - - private: - fpga_properties *props_; - bool is_set_; - getter_t get_; - setter_t set_; - copy_t copy_; -}; - -/** - * @brief Template specialization of `char*` type property updater - * - * @return The result of the property getter function. - */ -template <> -inline void pvalue::update() { - char buf[256]; - ASSERT_FPGA_OK(get_(*props_, buf)); - copy_.assign(buf); - is_set_ = true; -} - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/shared_buffer.h b/sw/include/opae/cxx/core/shared_buffer.h deleted file mode 100644 index f3fd17b1f..000000000 --- a/sw/include/opae/cxx/core/shared_buffer.h +++ /dev/null @@ -1,177 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -/** Host/AFU shared memory blocks - * - * shared_buffer abstracts a memory block that may be shared - * between the host cpu and an accelerator. The block may - * be allocated by the shared_buffer class itself (see allocate), - * or it may be allocated elsewhere and then attached to - * a shared_buffer object via attach. - */ -class shared_buffer { - public: - typedef std::size_t size_t; - typedef std::shared_ptr ptr_t; - - shared_buffer(const shared_buffer &) = delete; - shared_buffer &operator=(const shared_buffer &) = delete; - - /** shared_buffer destructor. - */ - virtual ~shared_buffer(); - - /** shared_buffer factory method - allocate a shared_buffer. - * @param[in] handle The handle used to allocate the buffer. - * @param[in] len The length in bytes of the requested buffer. - * @return A valid shared_buffer smart pointer on success, or an - * empty smart pointer on failure. - */ - static shared_buffer::ptr_t allocate(handle::ptr_t handle, size_t len, - bool read_only = false); - - /** Attach a pre-allocated buffer to a shared_buffer object. - * - * @param[in] handle The handle used to attach the buffer. - * @param[in] base The base of the pre-allocated memory. - * @param[in] len The size of the pre-allocated memory, - * which must be a multiple of the page size. - * @return A valid shared_buffer smart pointer on success, or an - * empty smart pointer on failure. - */ - static shared_buffer::ptr_t attach(handle::ptr_t handle, uint8_t *base, - size_t len, bool read_only = false); - - /** - * @brief Disassociate the shared_buffer object from the resource used to - * create it. If the buffer was allocated using the allocate function then - * the buffer is freed. - */ - void release(); - - /** Retrieve the virtual address of the buffer base. - * - * @note Instances of a shared buffer can only be created using either - * 'allocate' or 'attach' static factory function. Because these - * functions return a shared pointer (std::shared_ptr) to the instance, - * references to an instance are counted automatically by design of the - * shared_ptr class. Calling 'c_type()' function is provided to get access - * to the raw data but isn't used in tracking its reference count. - * Assigning this to a variable should be done in limited scopes as this - * variable can be defined in an outer scope and may outlive the - * shared_buffer object. Once the reference count in the shared_ptr reaches - * zero, the shared_buffer object will be released and deallocated, turning - * any variables assigned from a call to 'c_type()' into dangling pointers. - */ - volatile uint8_t *c_type() const { return virt_; } - - /** Retrieve the handle smart pointer associated with - * this buffer. - */ - handle::ptr_t owner() const { return handle_; } - - /** Retrieve the length of the buffer in bytes. - */ - size_t size() const { return len_; } - - /** Retrieve the underlying buffer's workspace id. - */ - uint64_t wsid() const { return wsid_; } - - /** Retrieve the address of the buffer suitable for - * programming into the accelerator device. - */ - uint64_t io_address() const { return io_address_; } - - /** Write c to each byte location in the buffer. - */ - void fill(int c); - - /** Compare this shared_buffer (the first len bytes) - * to that held in other, using memcmp(). - */ - int compare(ptr_t other, size_t len) const; - - /** Read a T-sized block of memory at the given location. - * @param[in] offset The byte offset from the start of the buffer. - * @return A T from buffer base + offset. - */ - template - T read(size_t offset) const { - if ((offset < len_) && (virt_ != nullptr)) { - return *reinterpret_cast(virt_ + offset); - } else if (offset >= len_) { - throw except(OPAECXX_HERE); - } else { - throw except(OPAECXX_HERE); - } - return T(); - } - - /** Write a T-sized block of memory to the given location. - * @param[in] value The value to write. - * @param[in] offset The byte offset from the start of the buffer. - */ - template - void write(const T &value, size_t offset) { - if ((offset < len_) && (virt_ != nullptr)) { - *reinterpret_cast(virt_ + offset) = value; - } else if (offset >= len_) { - throw except(OPAECXX_HERE); - } else { - throw except(OPAECXX_HERE); - } - } - - protected: - shared_buffer(handle::ptr_t handle, size_t len, uint8_t *virt, uint64_t wsid, - uint64_t io_address); - - handle::ptr_t handle_; - size_t len_; - uint8_t *virt_; - uint64_t wsid_; - uint64_t io_address_; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/sysobject.h b/sw/include/opae/cxx/core/sysobject.h deleted file mode 100644 index 83316947f..000000000 --- a/sw/include/opae/cxx/core/sysobject.h +++ /dev/null @@ -1,200 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include -#include - -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -/** Wraps the OPAE fpga_object primitive. - * sysobject's are created from a call to fpgaTokenGetObject, - * fpgaHandleGetObject, or fpgaObjectGetObject - */ -class sysobject { - public: - typedef std::shared_ptr ptr_t; - - sysobject() = delete; - - sysobject(const sysobject &o) = delete; - - sysobject &operator=(const sysobject &o) = delete; - - /** - * @brief Get a sysobject from a token. This will be read-only. - * - * @param[in] t Token object representing a resource. - * @param[in] name An identifier representing an object belonging to a - * resource represented by the token. - * @param[in] flags Control behavior of object identification and creation. - * FPGA_OBJECT_GLOB is used to indicate that the name should be treated as a - * globbing expression. FPGA_OBJECT_RECURSE_ONE indicates that subobjects be - * created for objects one level down from the object identified by name. - * FPGA_OBJECT_RECURSE_ALL indicates that subobjects be created for all - * objects below the current object identified by name. - * - * @return A shared_ptr to a sysobject instance. - */ - static sysobject::ptr_t get(token::ptr_t t, const std::string &name, - int flags = 0); - - /** - * @brief Get a sysobject from a handle. This will be read-write. - * - * @param[in] h Handle object representing an open resource. - * @param[in] name An identifier representing an object belonging to a - * resource represented by the handle. - * @param[in] flags Control behavior of object identification and creation. - * FPGA_OBJECT_GLOB is used to indicate that the name should be treated as a - * globbing expression. FPGA_OBJECT_RECURSE_ONE indicates that subobjects be - * created for objects one level down from the object identified by name. - * FPGA_OBJECT_RECURSE_ALL indicates that subobjects be created for all - * objects below the current object identified by name. - * - * @return A shared_ptr to a sysobject instance. - */ - static sysobject::ptr_t get(handle::ptr_t h, const std::string &name, - int flags = 0); - - /** - * @brief Get a sysobject from an object. This will be read-write if its - * parent was created from a handle.. - * - * @param[in] name An identifier representing an object belonging to this - * object. - * @param[in] flags Control behavior of object identification and creation. - * FPGA_OBJECT_GLOB is used to indicate that the name should be treated as a - * globbing expression. FPGA_OBJECT_RECURSE_ONE indicates that subobjects be - * created for objects one level down from the object identified by name. - * FPGA_OBJECT_RECURSE_ALL indicates that subobjects be created for all - * objects. Flags are defaulted to 0 meaning no flags. - * - * @return A shared_ptr to a sysobject instance. - */ - sysobject::ptr_t get(const std::string &name, int flags = 0); - - /** - * @brief Get a sysobject from a container object. This will be read-write if - * its parent was created from a handle.. - * - * @param[in] index An index number to get. - * - * @return A shared_ptr to a sysobject instance. - */ - sysobject::ptr_t get(int index); - - virtual ~sysobject(); - - /** - * @brief Get the size (in bytes) of the object. - * - * @return The number of bytes that the object occupies in memory. - */ - uint32_t size() const; - - /** - * @brief Read a 64-bit value from an FPGA object. - * The value is assumed to be in string format and will be parsed. See flags - * below for changing that behavior. - * - * @param[in] flags Flags that control how the object is read - * If FPGA_OBJECT_SYNC is used then object will update its buffered copy - * before retrieving the data. If FPGA_OBJECT_RAW is used, then the data - * will be read as raw bytes into the uint64_t pointer variable. Flags - * are defaulted to 0 meaning no flags. - * - * @return A 64-bit value from the object. - */ - uint64_t read64(int flags = 0) const; - - /** - * @brief Write 64-bit value to an FPGA object. - * The value will be converted to string before writing. See flags below for - * changing that behavior. - * - * @param[in] value The value to write to the object. - * @param[in] flags Flags that control how the object is written - * If FPGA_OBJECT_RAW is used, then the value will be written as raw bytes. - * Flags are defaulted to 0 meaning no flags. - * - * @note This operation will force a sync operation to update its cached - * buffer - */ - void write64(uint64_t value, int flags = 0) const; - - /** - * @brief Get all raw bytes from the object. - * - * @param[in] flags Flags that control how object is read - * If FPGA_OBJECT_SYNC is used then object will update its buffered copy - * before retrieving the data. - * - * @return A vector of all bytes in the object. - */ - std::vector bytes(int flags = 0) const; - - /** - * @brief Get a subset of raw bytes from the object. - * - * @param[in] offset The bytes offset for the start of the returned vector. - * @param[in] size The number of bytes for the returned vector. - * @param[in] flags Flags that control how object is read - * If FPGA_OBJECT_SYNC is used then object will update its buffered copy - * before retrieving the data. - * - * @return A vector of size bytes in the object starting at offset. - */ - std::vector bytes(uint32_t offset, uint32_t size, - int flags = 0) const; - - /** Get the object type (attribute or container) - */ - enum fpga_sysobject_type type() const; - - /** Retrieve the underlying fpga_object primitive. - */ - fpga_object c_type() const { return sysobject_; } - - /** Retrieve the underlying fpga_object primitive. - */ - operator fpga_object() const { return sysobject_; } - - private: - sysobject(fpga_object sysobj, token::ptr_t token, handle::ptr_t hnd); - fpga_object sysobject_; - token::ptr_t token_; - handle::ptr_t handle_; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/token.h b/sw/include/opae/cxx/core/token.h deleted file mode 100644 index a456e5f4f..000000000 --- a/sw/include/opae/cxx/core/token.h +++ /dev/null @@ -1,81 +0,0 @@ -// Copyright(c) 2018-2021, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include -#include -#include -#include - -#include -#include - -namespace opae { -namespace fpga { -namespace types { - -/** Wraps the OPAE fpga_token primitive. - * token's are created from an enumeration operation - * that uses properties describing an accelerator resource - * as search criteria. - */ -class token { - public: - typedef std::shared_ptr ptr_t; - - /** Obtain a vector of token smart pointers - * for given search criteria. - * @param[in] props The search criteria. - * @return A set of known tokens that match the search. - */ - static std::vector enumerate( - const std::vector& props); - - ~token(); - - /** Retrieve the underlying fpga_token primitive. - */ - fpga_token c_type() const { return token_; } - - /** Retrieve the underlying fpga_token primitive. - */ - operator fpga_token() const { return token_; } - - /** Retrieve the parent token, or an empty pointer - * if there is none. - */ - ptr_t get_parent() const; - - private: - token(fpga_token tok); - - fpga_token token_; - - friend class handle; -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/cxx/core/version.h b/sw/include/opae/cxx/core/version.h deleted file mode 100644 index 4c938e151..000000000 --- a/sw/include/opae/cxx/core/version.h +++ /dev/null @@ -1,55 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#pragma once -#include - -#include - -namespace opae { -namespace fpga { -namespace types { - -class version { - public: - /// @brief Get the package version information as a struct - /// - /// @return The package version as an `fpga_version` struct - static fpga_version as_struct(); - - /// @brief Get the package version information as a string - /// - /// @return The package version as an `std::string` object - static std::string as_string(); - - /// @brief Get the package build information as a string - /// - /// @return The package build as an `std::string` object - static std::string build(); -}; - -} // end of namespace types -} // end of namespace fpga -} // end of namespace opae diff --git a/sw/include/opae/enum.h b/sw/include/opae/enum.h deleted file mode 100644 index fd3426f84..000000000 --- a/sw/include/opae/enum.h +++ /dev/null @@ -1,140 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file enum.h - * @brief APIs for resource enumeration and managing tokens - * - * These APIs are the first step for any application using OPAE to discover - * resources that are present on the system. They allow selective enumeration - * (i.e. getting a list of resources that match a given list of criteria) and - * methods to manage the lifecycle of tokens generated by fpgaEnumerate(). - */ - -#ifndef __FPGA_ENUM_H__ -#define __FPGA_ENUM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Enumerate FPGA resources present in the system - * - * This call allows the user to query the system for FPGA resources that match - * a certain set of criteria, e.g. all accelerators that are assigned to a host - * interface and available, all FPGAs of a specific type, etc. - * - * fpgaEnumerate() will create a number of `fpga_token`s to represent the - * matching resources and populate the array `tokens` with these tokens. The - * `max_tokens` argument can be used to limit the number of tokens - * allocated/returned by fpgaEnumerate(); i.e., the number of tokens in the - * returned `tokens` array will be either `max_tokens` or `num_matches` (the - * number of resources matching the filter), whichever is smaller. Use - * fpgaDestroyToken() to destroy tokens that are no longer needed. - * - * To query the number of matches for a particular set of filters (e.g. to - * allocate a `tokens` array of the appropriate size), call fpgaEnumerate() - * with the parameter `tokens` set to NULL; this will only return the number of - * matches in `num_matches`. - * - * @note fpgaEnumerate() will allocate memory for the created tokens returned - * in `tokens`. It is the responsibility of the using application to free this - * memory after use by calling fpgaDestroyToken() for each of the returned - * tokens. - * - * @param[in] filters Array of `fpga_properties` objects describing the - * properties of the objects that should be returned. A - * resource is considered matching if its properties - * match any one of the supplied filters. To match all - * FPGA resources, pass an empty filters object (one - * without any filter criteria set) or pass a NULL - * filters parameter with num_filters set to 0. - * @param[in] num_filters Number of entries in the `filters` array, or 0 to - * match all FPGA resources when `filters` is NULL. - * @param[out] tokens Pointer to an array of fpga_token variables to be - * populated. If NULL is supplied, fpgaEnumerate() will - * not create any tokens, but it will return the - * number of possible matches in `num_match`. - * @param[in] max_tokens Maximum number of tokens that fpgaEnumerate() shall - * return (length of `tokens` array). There may be more - * or fewer matches than this number; `num_matches` is - * set to the number of actual matches. - * @param[out] num_matches Number of resources matching the `filter` criteria. - * This number can be higher than the number of tokens - * returned in the `tokens` array (depending on the - * value of `max_tokens`). - * @returns FPGA_OK on success. - * FPGA_INVALID_PARAM if invalid pointers or objects - * are passed into the function. - * FPGA_NO_DRIVER if OPAE can't find the respective - * enumeration data structures usually provided by the - * driver. - * FPGA_NO_MEMORY if there was not enough memory to - * create tokens. - */ -fpga_result fpgaEnumerate(const fpga_properties *filters, - uint32_t num_filters, fpga_token *tokens, - uint32_t max_tokens, uint32_t *num_matches); - -/** - * Clone a fpga_token object - * - * Creates a copy of an fpga_token object. - * - * @note This call creates a new token object and allocates memory for it. It - * is the responsibility of the using application to free this memory after use - * by calling fpgaDestroyToken() for the cloned token. - * - * @param[in] src fpga_token object to copy - * @param[out] dst New fpga_token object cloned from 'src' - * @returns FPGA_OK on success - */ -fpga_result fpgaCloneToken(fpga_token src, fpga_token *dst); - -/** - * Destroy a Token - * - * This function destroys a token created by fpgaEnumerate() and frees the - * associated memory. - * - * @note fpgaDestroyToken() requires the address of an fpga_token as - * previously created by fpgaEnumerate() or fpgaCloneToken(). Passing - * any other value results in undefined behavior. - * - * @param[in] token fpga_token to destroy - * @returns FPGA_OK on success - */ -fpga_result fpgaDestroyToken(fpga_token *token); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_ENUM_H__ - diff --git a/sw/include/opae/error.h b/sw/include/opae/error.h deleted file mode 100644 index 7802a576f..000000000 --- a/sw/include/opae/error.h +++ /dev/null @@ -1,113 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file error.h - * @brief Functions for reading and clearing errors in resources - * - * Many FPGA resources have the ability to track the occurrence of errors. - * This file provides functions to retrieve information about errors within - * resources. - */ - -#ifndef __FPGA_ERROR_H__ -#define __FPGA_ERROR_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * Read error value - * - * This function will read the value of error register `error_num` of - * the resource referenced by `token` into the memory location pointed to - * by `value`. - * - * @param[in] token Token to accelerator resource to query - * @param[in] error_num Number of error register to read - * @param[out] value Pointer to memory to store error value into (64 bit) - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the token. - */ -fpga_result fpgaReadError(fpga_token token, uint32_t error_num, uint64_t *value); - -/** - * Clear error register - * - * This function will clear the error register `error_num` of the resource - * referenced by `token`. - * - * @param[in] token Token to accelerator resource to query - * @param[in] error_num Number of error register to clear - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the token, and FPGA_BUSY if error could not be - * cleared. - */ -fpga_result fpgaClearError(fpga_token token, uint32_t error_num); - -/** - * Clear all error registers of a particular resource - * - * This function will clear all error registers of the resource referenced by - * `token`, observing the necessary order of clearing errors, if any. - * - * @param[in] token Token to accelerator resource to query - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the token, and FPGA_BUSY if error could not be - * cleared. - */ -fpga_result fpgaClearAllErrors(fpga_token token); - -/** - * Get information about a particular error register - * - * This function will populate a `fpga_error_info` struct with information - * about error number `error_num` of the resource referenced by `token`. - * - * @param[in] token Token to accelerator resource to query - * @param[in] error_num Error register to retrieve information about - * @param[out] error_info Pointer to memory to store information into - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the token. - */ -fpga_result fpgaGetErrorInfo(fpga_token token, - uint32_t error_num, - struct fpga_error_info *error_info); - - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_ERROR_H__ diff --git a/sw/include/opae/event.h b/sw/include/opae/event.h deleted file mode 100644 index f755c61df..000000000 --- a/sw/include/opae/event.h +++ /dev/null @@ -1,160 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file event.h - * @brief Functions for registering events and managing the lifecycle for - * `fpga_event_handle`s. - * - * OPAE provides an interface to asynchronous events that can be generated by - * different FPGA resources. The event API provides functions to register for - * these events; associated with every event a process has registered for is an - * fpga_event_handle, which encapsulates the OS-specific data structure for - * event objects. On Linux, an fpga_event_handle can be used as a file - * descriptor and passed to select(), poll(), epoll() and similar functions to - * wait for asynchronous events. - */ - -#ifndef __FPGA_EVENT_H__ -#define __FPGA_EVENT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Initialize an event_handle - * - * Platform independent way to initialize an event_handle used for - * notifications from the driver to application. For Linux, this function - * creates an eventfd and returns the eventfd file descriptor in - * `*event_handle`. - * - * @param[out] event_handle Pointer to event handle variable. - * - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `event_handle` is NULL. - * FPGA_NOT_SUPPORTED if platform does not support events. - */ -fpga_result fpgaCreateEventHandle(fpga_event_handle *event_handle); - -/** - * Destroy an event_handle - * - * Destroy handle and free resources. On Linux this corresponds - * to closing the file descriptor pointed to by handle - * - * @note fpgaDestroyEventHandle() requires the address of an - * event_handle as created by fpgaCreateEventHandle(). Passing - * any other value results in undefined behavior. - * - * @param[in] event_handle Pointer to handle to be destroyed - * - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `event_handle` is NULL. - */ -fpga_result fpgaDestroyEventHandle(fpga_event_handle *event_handle); - - -/** - * Get OS object from event handle - * - * Check validity of event handle, and get the OS object used to - * subscribe and unsubscribe to events. On Linux, the object corresponds - * to a file descriptor. - * - * @param[in] eh Event handle to get the descriptor value from - * @param[out] fd integer to store the descriptor value - * - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `event_handle` is invalid. - */ -fpga_result fpgaGetOSObjectFromEventHandle(const fpga_event_handle eh, int *fd); - -/** - * Register an FPGA event - * - * This function tells the driver that the caller is interested in notification - * for the event specified by the type and flags pair. - * - * The event_handle points to an OS specific mechanism for event notification. - * An event_handle is associated with only a single event. - * - * In case of user interrupts, the flags parameter will be used to specify - * the vector ID. The value of the flags parameter indicates the vector ID, - * no bit encoding is used. - * - * @todo define if calling fpgaRegisterEvent multiple times with the - * same event_handle is an error condition or if it is silently ignored. - * - * @param[in] handle Handle to previously opened FPGA resource. - * @param[in] event_type Type of event - * @param[in] event_handle Handle to previously opened resource for event - * notification. - * @param[in] flags Optional argument for specifying additional - * information about event. For example irq number - * for interrupt events. - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does not refer to - * a resource supporting the requested event, or if event_handle is not valid. - * FPGA_EXCEPTION if an internal exception occurred while accessing the handle - * or the event_handle. On Linux: FPGA_NO_DAEMON if the driver does not support - * the requested event and there is no FPGA Daemon (fpgad) running to proxy it. - */ -fpga_result fpgaRegisterEvent(fpga_handle handle, - fpga_event_type event_type, - fpga_event_handle event_handle, - uint32_t flags); - -/** - * Unregister an FPGA event - * - * This function tells the driver that the caller is no longer interested in - * notification for the event associated with the event_handle - * - * The event_handle points to an OS specific mechanism for event notification. - * An event_handle is associated with only a single event. - * - * @todo define if calling fpgaUnregisterEvent multiple times with the - * same event_handle is an error condition or if it is silently ignored. - * - * @param[in] handle Handle to previously opened FPGA resource. - * @param[in] event_type Type of event to unregister. - * @param[in] event_handle Handle to previously registered resource for event - * notification. - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does - * not refer to a resource supporting the requested event, - * or if event_handle is not valid. FPGA_EXCEPTION if an - * internal error occurred accessing the handle or the - * event_handle. - */ -fpga_result fpgaUnregisterEvent(fpga_handle handle, - fpga_event_type event_type, - fpga_event_handle event_handle); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_EVENT_H__ diff --git a/sw/include/opae/fpga.h b/sw/include/opae/fpga.h deleted file mode 100644 index 2b020325a..000000000 --- a/sw/include/opae/fpga.h +++ /dev/null @@ -1,57 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * \file fpga.h - * \brief FPGA API - * - * This conveniently includes all APIs that a part of the OPAE release (base and - * extensions). - */ - -#ifndef __FPGA_FPGA_H__ -#define __FPGA_FPGA_H__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif // __FPGA_FPGA_H__ - diff --git a/sw/include/opae/hash_map.h b/sw/include/opae/hash_map.h deleted file mode 100644 index 414e98eac..000000000 --- a/sw/include/opae/hash_map.h +++ /dev/null @@ -1,235 +0,0 @@ -// Copyright(c) 2022-2023, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file opae/hash_map.h - * @brief A general-purpose hybrid array/list hash map implementation. - * - * Presents a generic interface for mapping key objects to value objects. - * Both keys and values may be arbitrary data structures. The user supplies - * the means by which the hash of values is generated and by which the - * keys are compared to each other. - */ - -#ifndef __OPAE_HASH_MAP_H__ -#define __OPAE_HASH_MAP_H__ -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -/** Flags used to initialize a hash map. - * - * OPAE_HASH_MAP_UNIQUE_KEYSPACE says that the user provides - * a guarantee that the key space is truly unique. In other words, when - * the provided hash function for keys A and B returns the same bucket - * index, the key comparison function when comparing A and B will never - * return a result saying that the keys are equal in value. This is helpful - * in situations where the key space is guaranteed to produce unique values, - * for example a memory allocator. When the key space is guaranteed to be - * unique, opae_hash_map_add() can implement a small performance improvement. - */ -typedef enum _opae_hash_map_flags { - OPAE_HASH_MAP_UNIQUE_KEYSPACE = (1u << 0) -} opae_hash_map_flags; - -/** - * List link item. - * - * This structure provides the association between key and value. - * When the supplied hash function for keys A and B returns the same - * bucket index, both A and B can co-exist on the same list rooted - * at the bucket index. - */ -typedef struct _opae_hash_map_item { - void *key; - void *value; - struct _opae_hash_map_item *next; -} opae_hash_map_item; - -/** - * Hash map object. - * - * This structure defines the internals of the hash map. Each of the - * parameters supplied to opae_hash_map_init() is stored in the structure. - * All parameters are required, except key_cleanup and value_cleanup, - * which may optionally be NULL. - */ -typedef struct _opae_hash_map { - uint32_t num_buckets; - uint32_t hash_seed; - opae_hash_map_item **buckets; - int flags; - void *cleanup_context; ///< Optional second parameter to key_cleanup and value_cleanup - uint32_t (*key_hash)(uint32_t num_buckets, ///< (required) - uint32_t hash_seed, - void *key); - int (*key_compare)(void *keya, void *keyb); ///< (required) - void (*key_cleanup)(void *key, void *context); ///< (optional) - void (*value_cleanup)(void *value, void *context); ///< (optional) -} opae_hash_map; - -/** - * Initialize a hash map - * - * Populates the hash map data structure and allocates the buckets - * array. - * - * @param[out] hm A pointer to the storage for the hash map object. - * @param[in] num_buckets The desired size of the buckets array. Each array - * entry may be empty (NULL), or may contain a list - * of opae_hash_map_item structures for which the given - * key_hash function returned the same key hash value. - * @param[in] hash_seed A seed value used during key hash computation. This - * value will be the hash_seed parameter to the key hash - * function. - * @param[in] flags Initialization flags. See opae_hash_map_flags. - * @param[in] key_hash A pointer to a function that produces the hash value, - * given the number of buckets, the hash seed, and the key. - * Valid values are between 0 and num_buckets - 1, inclusively. - * @param[in] key_compare A pointer to a function that compares two keys. The return - * value is similar to that of strcmp(), where a negative value - * means that keya < keyb, 0 means that keya == keyb, and a positive - * values means that keya > keyb. - * @param[in] key_cleanup A pointer to a function that is called when a key is being - * removed from the map. This function is optional and may be - * NULL. When supplied, the function is responsible for freeing - * any resources allocated when the key was created. - * @param[in] value_cleanup A pointer to a function that is called when a value is - * being removed from the map. This function is optional and may - * be NULL. When supplied, the function is responsible for freeing - * any resources allocated when the value was created. - * @returns FPGA_OK on success, FPGA_INVALID_PARAM if any of the required parameters are - * NULL, or FPGA_NO_MEMORY if the bucket array could not be allocated. - */ -fpga_result opae_hash_map_init(opae_hash_map *hm, - uint32_t num_buckets, - uint32_t hash_seed, - int flags, - uint32_t (*key_hash)(uint32_t num_buckets, - uint32_t hash_seed, - void *key), - int (*key_compare)(void *keya, void *keyb), - void (*key_cleanup)(void *key, void *context), - void (*value_cleanup)(void *value, void *context)); - -/** - * Map a key to a value - * - * Inserts a mapping from key to value in the given hash map object. - * Subsequent calls to opae_hash_map_find() that are given the key - * will retrieve the value. - * - * @param[in, out] hm A pointer to the storage for the hash map object. - * @param[in] key The hash map key. - * @param[in] value The hash map value. - * @returns FPGA_OK on success, FPGA_INVALID_PARAM if hm is NULL, FPGA_NO_MEMORY - * if malloc() fails when allocating the list item, or FPGA_INVALID_PARAM - * if the key hash produced by key_hash is out of bounds. - */ -fpga_result opae_hash_map_add(opae_hash_map *hm, - void *key, - void *value); - -/** - * Retrieve the value for a given key - * - * Given a key that was previously passed to opae_hash_map_add(), retrieve - * its associated value. - * - * @param[in] hm A pointer to the storage for the hash map object. - * @param[in] key The hash map key. - * @param[in] value A pointer to receive the hash map value. - * @returns FPGA_OK on success, FPGA_INVALID_PARAM if hm is NULL or if the - * key hash produced by key_hash is out of bounds, or FPGA_NOT_FOUND - * if the given key was not found in the hash map. - */ -fpga_result opae_hash_map_find(opae_hash_map *hm, - void *key, - void **value); - -/** - * Remove a key/value association - * - * Given a key that was previously passed to opae_hash_map_add(), remove the - * key and its associated value, calling the cleanup functions as needed. - * - * @param[in, out] hm A pointer to the storage for the hash map object. - * @param[in] key The hash map key. - * @returns FPGA_OK on success, FPGA_INVALID_PARAM when hm is NULL or when the - * key hash produced by key_hash is out of bounds, or FPGA_NOT_FOUND if - * the key is not found in the hash map. - */ -fpga_result opae_hash_map_remove(opae_hash_map *hm, - void *key); - -/** - * Tear down a hash map - * - * Given a hash map that was previously initialized by opae_hash_map_init(), - * destroy the hash map, releasing all keys, values, and the bucket array. - * - * @param[in, out] hm A pointer to the storage for the hash map object. - * @returns FPGA_OK on success or FPGA_INVALID_PARAM is hm is NULL. - */ -fpga_result opae_hash_map_destroy(opae_hash_map *hm); - -/** - * Determine whether a hash map is empty - * - * @param[in] hm A pointer to the storage for the hash map object. - * @returns true if there are no key/value mappings present, false - * otherwise. - */ -bool opae_hash_map_is_empty(opae_hash_map *hm); - -/** - * Convenience hash function for arbitrary pointers/64-bit values. - * - * Simply converts the key to a uint64_t and then performs the - * modulus operation with the configured num_buckets. hash_seed is - * unused. - */ -uint32_t opae_u64_key_hash(uint32_t num_buckets, - uint32_t hash_seed, - void *key); - -/** - * Convenience key comparison function for 64-bit values. - * - * Simply converts the key pointers to uint64_t's and performs - * unsigned integer comparison. - */ -int opae_u64_key_compare(void *keya, void *keyb); - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __OPAE_HASH_MAP_H__ diff --git a/sw/include/opae/init.h b/sw/include/opae/init.h deleted file mode 100644 index 9f45d05ac..000000000 --- a/sw/include/opae/init.h +++ /dev/null @@ -1,64 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * \file init.h - * \brief Initialization routine. - */ - -#ifndef __FPGA_INIT_H__ -#define __FPGA_INIT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Initialize the OPAE library. - * - * Initialize OPAE using the given configuration file path, or - * perform default initialization if config_file is NULL. - * - * @param[in] config_file Path to OPAE configuration file. - * @returns Whether OPAE initialized successfully. - */ -fpga_result fpgaInitialize(const char *config_file); - -/** - * Finalize the OPAE library. - * - * @returns Whether OPAE finalized successfully. - */ -fpga_result fpgaFinalize(void); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_INIT_H__ - diff --git a/sw/include/opae/log.h b/sw/include/opae/log.h deleted file mode 100644 index 1b4ab5199..000000000 --- a/sw/include/opae/log.h +++ /dev/null @@ -1,105 +0,0 @@ -// Copyright(c) 2018-2021, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -#ifndef __OPAE_LOG_H__ -#define __OPAE_LOG_H__ - -#include -#include -#include -#include - -#include - -/* -* Convenience macros for printing messages and errors. -*/ -#ifdef __SHORT_FILE__ -#undef __SHORT_FILE__ -#endif // __SHORT_FILE__ -#define __SHORT_FILE__ \ - ({ \ - const char *file = __FILE__; \ - const char *p = file; \ - while (*p) \ - ++p; \ - while ((p > file) && ('/' != *p) && ('\\' != *p)) \ - --p; \ - if (p > file) \ - ++p; \ - p; \ - }) - -#ifdef OPAE_MSG -#undef OPAE_MSG -#endif // OPAE_MSG -#define OPAE_MSG(format, ...) \ - opae_print(OPAE_LOG_MESSAGE, "%s:%u:%s() : " format "\n", \ - __SHORT_FILE__, __LINE__, __func__, ##__VA_ARGS__) - -#ifdef OPAE_ERR -#undef OPAE_ERR -#endif // OPAE_ERR -#define OPAE_ERR(format, ...) \ - opae_print(OPAE_LOG_ERROR, \ - "%s:%u:%s() **ERROR** : " format "\n", \ - __SHORT_FILE__, __LINE__, __func__, ##__VA_ARGS__) - -#ifdef OPAE_DBG -#undef OPAE_DBG -#endif // OPAE_DBG -#ifdef LIBOPAE_DEBUG -#define OPAE_DBG(format, ...) \ - opae_print(OPAE_LOG_DEBUG, \ - "%s:%u:%s() *DEBUG* : " format "\n", \ - __SHORT_FILE__, __LINE__, __func__, ##__VA_ARGS__) -#else -#define OPAE_DBG(format, ...) \ -{ } -#endif // LIBOPAE_DEBUG - -/* -* Logging functions -*/ -enum opae_loglevel { - OPAE_LOG_ERROR = 0, /* critical errors (always print) */ - OPAE_LOG_MESSAGE, /* information (i.e. explain return code */ - OPAE_LOG_DEBUG /* debugging (also needs #define DEBUG 1) */ -}; - -#define OPAE_DEFAULT_LOGLEVEL OPAE_LOG_ERROR - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -void opae_print(int loglevel, const char *fmt, ...); - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __OPAE_LOG_H__ diff --git a/sw/include/opae/manage.h b/sw/include/opae/manage.h deleted file mode 100644 index 12ae211ec..000000000 --- a/sw/include/opae/manage.h +++ /dev/null @@ -1,148 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file manage.h - * @brief Functions for managing FPGA configurations - * - * FPGA accelerators can be reprogrammed at run time by providing new partial - * bitstreams ("green bitstreams"). This file defines API functions for - * programming green bitstreams as well as for assigning accelerators to host - * interfaces for more complex deployment setups, such as virtualized systems. - */ - -#ifndef __FPGA_MANAGE_H__ -#define __FPGA_MANAGE_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* Assign Port to a host interface. -* -* This function assign Port to a host interface for subsequent use. Only -* Port that have been assigned to a host interface can be opened by -* fpgaOpen(). -* -* @param[in] fpga Handle to an FPGA object previously opened that -* both the host interface and the slot belong to -* @param[in] interface_num Host interface number -* @param[in] slot_num Slot number -* @param[in] flags Flags (to be defined) -* @returns FPGA_OK on success -* FPGA_INVALID_PARAM if input parameter combination -* is not valid. -* FPGA_EXCEPTION if an exception occcurred accessing -* the `fpga` handle. -* FPGA_NOT_SUPPORTED if driver does not support -* assignment. -*/ -fpga_result fpgaAssignPortToInterface(fpga_handle fpga, - uint32_t interface_num, - uint32_t slot_num, - int flags); - -/** - * Assign an accelerator to a host interface - * - * This function assigns an accelerator to a host interface for subsequent use. Only - * accelerators that have been assigned to a host interface can be opened by - * fpgaOpen(). - * - * @note This function is currently not supported. - * - * @param[in] fpga Handle to an FPGA object previously opened that - * both the host interface and the accelerator belong to - * @param[in] accelerator accelerator to assign - * @param[in] host_interface Host interface to assign accelerator to - * @param[in] flags Flags (to be defined) - * @returns FPGA_OK on success - */ -fpga_result fpgaAssignToInterface(fpga_handle fpga, - fpga_token accelerator, - uint32_t host_interface, - int flags); - -/** - * Unassign a previously assigned accelerator - * - * This function removes the assignment of an accelerator to an host interface (e.g. to - * be later assigned to a different host interface). As a consequence, the accelerator - * referred to by token 'accelerator' will be reset during the course of this function. - * - * @note This function is currently not supported. - * - * @param[in] fpga Handle to an FPGA object previously opened that - * both the host interface and the accelerator belong to - * @param[in] accelerator accelerator to unassign/release - * @returns FPGA_OK on success - */ -fpga_result fpgaReleaseFromInterface(fpga_handle fpga, - fpga_token accelerator); - -/** - * Reconfigure a slot - * - * Sends a green bitstream file to an FPGA to reconfigure a specific slot. This - * call, if successful, will overwrite the currently programmed AFU in that - * slot with the AFU in the provided bitstream. - * - * As part of the reconfiguration flow, all accelerators associated with this slot will - * be unassigned and reset. - * - * @param[in] fpga Handle to an FPGA object previously opened - * @param[in] slot Token identifying the slot to reconfigure - * @param[in] bitstream Pointer to memory holding the bitstream - * @param[in] bitstream_len Length of the bitstream in bytes - * @param[in] flags Flags that control behavior of reconfiguration. - * Value of 0 indicates no flags. FPGA_RECONF_FORCE - * indicates that the bitstream is programmed into - * the slot without checking if the resource is - * currently in use. - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if the provided parameters - * are not valid. FPGA_EXCEPTION if an internal error occurred accessing the - * handle or while sending the bitstream data to the driver. FPGA_BUSY if the - * accelerator for the given slot is in use. FPGA_RECONF_ERROR on errors - * reported by the driver (such as CRC or protocol errors). - * - * @note By default, fpgaReconfigureSlot will not allow reconfiguring a slot - * with an accelerator in use. Add the flag FPGA_RECONF_FORCE to force - * reconfiguration without checking for accelerators in use. - */ -fpga_result fpgaReconfigureSlot(fpga_handle fpga, - uint32_t slot, - const uint8_t *bitstream, - size_t bitstream_len, int flags); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_MANAGE_H__ - diff --git a/sw/include/opae/mem_alloc.h b/sw/include/opae/mem_alloc.h deleted file mode 100644 index 5b53db648..000000000 --- a/sw/include/opae/mem_alloc.h +++ /dev/null @@ -1,176 +0,0 @@ -// Copyright(c) 2020, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -#ifndef __OPAE_MEM_ALLOC_H__ -#define __OPAE_MEM_ALLOC_H__ - -/** -* Provides an API for allocating/freeing a logical address space. There -* is no interaction with any OS memory allocation infrastructure, whether -* malloc, mmap, etc. The "address ranges" tracked by this allocator are -* arbitrary 64-bit integers. The allocator simply provides the bookeeping -* logic that ensures that a unique address with the appropriate size is -* returned for each allocation request, and that an allocation can be freed, -* ie released back to the available pool of logical address space for future -* allocations. The memory backing the allocator's internal data structures -* is managed by malloc()/free(). -*/ - -#include - -struct mem_link { - uint64_t address; - uint64_t size; - struct mem_link *prev; - struct mem_link *next; -}; - -struct mem_alloc { - struct mem_link free; - struct mem_link allocated; -}; - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -/** - * Initialize a memory allocator object - * - * After the call, the allocator is initialized but "empty". To add - * allocatable memory regions, further initialize the allocator with - * mem_alloc_add_free(). - * - * @param[out] m The address of the memory allocator to initialize. - */ -void mem_alloc_init(struct mem_alloc *m); - -/** - * Destroy a memory allocator object - * - * Frees all of the allocator's internal resources. - * - * @param[in] m The address of the memory allocator to destroy. - */ -void mem_alloc_destroy(struct mem_alloc *m); - -/** - * Add a memory region to an allocator. - * - * The memory region is added to the allocatable space and is - * immediately ready for allocation. - * - * @param[in, out] m The memory allocator object. - * @param[in] address The beginning address of the memory region. - * @param[in] size The size of the memory region. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.c} - * struct mem_alloc m; - * - * mem_alloc_init(&m); - * - * if (mem_alloc_add_free(&m, 0x4000, 4096)) { - * // handle error - * } - * @endcode - */ -int mem_alloc_add_free(struct mem_alloc *m, - uint64_t address, - uint64_t size); - -/** Allocate memory - * - * Retrieve an available memory address for a free block - * that is at least size bytes. - * - * @param[in, out] m The memory allocator object. - * @param[out] address The retrieved address for the allocation. - * @param[in] size The request size in bytes. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.c} - * struct mem_alloc m; - * uint64_t addr = 0; - * - * mem_alloc_init(&m); - * - * if (mem_alloc_add_free(&m, 0x4000, 4096)) { - * // handle error - * } - * - * ... - * - * if (mem_alloc_get(&m, &addr, 4096)) { - * // handle allocation error - * } - * @endcode - */ -int mem_alloc_get(struct mem_alloc *m, - uint64_t *address, - uint64_t size); - -/** Free memory - * - * Release a previously-allocated memory block. - * - * @param[in, out] m The memory allocator object. - * @param[in] address The address to free. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.c} - * struct mem_alloc m; - * uint64_t addr = 0; - * - * mem_alloc_init(&m); - * - * if (mem_alloc_add_free(&m, 0x4000, 4096)) { - * // handle error - * } - * - * ... - * - * if (mem_alloc_get(&m, &addr, 4096)) { - * // handle allocation error - * } - * - * ... - * - * if (mem_alloc_put(&m, addr)) { - * // handle free error - * } - * @endcode - */ -int mem_alloc_put(struct mem_alloc *m, - uint64_t address); - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __OPAE_MEM_ALLOC_H__ diff --git a/sw/include/opae/metrics.h b/sw/include/opae/metrics.h deleted file mode 100644 index c83d3278b..000000000 --- a/sw/include/opae/metrics.h +++ /dev/null @@ -1,139 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** -* @file metrics.h -* @brief Functions for Discover/ Enumerates metrics and retrieves values -* -* -* -* -*/ - -#ifndef __FPGA_METRICS_H__ -#define __FPGA_METRICS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Enumerates number of metrics - * - * @param[in] handle Handle to previously opened fpga resource - * @param[inout] num_metrics Number of metrics are discovered in - * fpga resource - * - * @returns FPGA_OK on success. FPGA_NOT_FOUND if the Metrics are not - * discovered - * - */ -fpga_result fpgaGetNumMetrics(fpga_handle handle, - uint64_t *num_metrics); - -/** - * Retrieve metrics information - * - * @param[in] handle Handle to previously opened fpga resource - * @param[inout] metric_info Pointer to array of metric info struct - * user allocates metrics info array - * - * @param[inout] num_metrics Size of metric info array - * - * @returns FPGA_OK on success. FPGA_NOT_FOUND if the Metrics are not - * found. FPGA_NO_MEMORY if there was not enough memory to enumerates - * metrics. - * - */ -fpga_result fpgaGetMetricsInfo(fpga_handle handle, - fpga_metric_info *metric_info, - uint64_t *num_metrics); - -/** - * Retrieve metrics values by index - * - * @param[in] handle Handle to previously opened fpga resource - * @param[inout] metric_num Pointer to array of metric index - * user allocates metric array - * @param[inout] num_metric_indexes Size of metric array - * @param[inout] metrics pointer to array of metric struct - * - * @returns FPGA_OK on success. FPGA_NOT_FOUND if the Metrics are not - * found. FPGA_NO_MEMORY if there was not enough memory to enumerates - * metrics. - * - */ -fpga_result fpgaGetMetricsByIndex(fpga_handle handle, - uint64_t *metric_num, - uint64_t num_metric_indexes, - fpga_metric *metrics); - -/** - * Retrieve metric values by names - * - * @param[in] handle Handle to previously opened fpga resource - * @param[inout] metrics_names Pointer to array of metrics name - * user allocates metrics name array - * @param[inout] num_metric_names Size of metric name array - * @param[inout] metrics Pointer to array of metric struct - * - * @returns FPGA_OK on success. FPGA_NOT_FOUND if the Metrics are not - * found - * - */ -fpga_result fpgaGetMetricsByName(fpga_handle handle, - char **metrics_names, - uint64_t num_metric_names, - fpga_metric *metrics); - - -/** - * Retrieve metrics / sendor threshold information and values - * - * @param[in] handle Handle to previously opened fpga resource - * @param[inout] metrics_threshold pointer to array of metric thresholds - * user allocates threshold array memory - * Number of thresholds returns enumerated thresholds if user pass - * NULL metrics_thresholds - * @param[inout] num_thresholds number of thresholds - * - * - * @returns FPGA_OK on success. FPGA_NOT_FOUND if the Metrics are not - * found. FPGA_NO_MEMORY if there was not enough memory to enumerates - * metrics. - * - */ -fpga_result fpgaGetMetricsThresholdInfo(fpga_handle handle, - struct metric_threshold *metric_thresholds, - uint32_t *num_thresholds); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_METRICS_H__ diff --git a/sw/include/opae/mmio.h b/sw/include/opae/mmio.h deleted file mode 100644 index fc45da9e7..000000000 --- a/sw/include/opae/mmio.h +++ /dev/null @@ -1,207 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file mmio.h - * @brief Functions for mapping and accessing MMIO space - * - * Most FPGA accelerators provide access to control registers through - * memory-mappable address spaces, commonly referred to as "MMIO spaces". This - * file provides functions to map, unmap, read, and write MMIO spaces. - * - * Note that an accelerator may have multiple MMIO spaces, denoted by the - * `mmio_num` argument of the APIs below. The meaning and properties of each - * MMIO space are up to the accelerator designer. - */ - -#ifndef __FPGA_MMIO_H__ -#define __FPGA_MMIO_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Write 64 bit value to MMIO space - * - * This function will write to MMIO space of the target object at a specified - * offset. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] mmio_num Number of MMIO space to access - * @param[in] offset Byte offset into MMIO space - * @param[in] value Value to write (64 bit) - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. - */ -fpga_result fpgaWriteMMIO64(fpga_handle handle, - uint32_t mmio_num, uint64_t offset, - uint64_t value); - -/** - * Read 64 bit value from MMIO space - * - * This function will read from MMIO space of the target object at a specified - * offset. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] mmio_num Number of MMIO space to access - * @param[in] offset Byte offset into MMIO space - * @param[out] value Pointer to memory where read value is returned (64 bit) - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. - */ -fpga_result fpgaReadMMIO64(fpga_handle handle, - uint32_t mmio_num, - uint64_t offset, uint64_t *value); - -/** - * Write 32 bit value to MMIO space - * - * This function will write to MMIO space of the target object at a specified - * offset. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] mmio_num Number of MMIO space to access - * @param[in] offset Byte offset into MMIO space - * @param[in] value Value to write (32 bit) - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. - */ -fpga_result fpgaWriteMMIO32(fpga_handle handle, - uint32_t mmio_num, uint64_t offset, - uint32_t value); - -/** - * Read 32 bit value from MMIO space - * - * This function will read from MMIO space of the target object at a specified - * offset. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] mmio_num Number of MMIO space to access - * @param[in] offset Byte offset into MMIO space - * @param[out] value Pointer to memory where read value is returned (32 bit) - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. - */ -fpga_result fpgaReadMMIO32(fpga_handle handle, - uint32_t mmio_num, - uint64_t offset, uint32_t *value); - -/** - * Write 512 bit value to MMIO space - * - * 512 bit MMIO writes may not be supported on all platforms. - * - * This function will write to MMIO space of the target object at a specified - * offset. - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] mmio_num Number of MMIO space to access - * @param[in] offset Byte offset into MMIO space - * @param[in] value Pointer to memory holding value to write (512 bits) - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. - */ -fpga_result fpgaWriteMMIO512(fpga_handle handle, - uint32_t mmio_num, uint64_t offset, - const void *value); - -/** - * Map MMIO space - * - * This function will return a pointer to the specified MMIO space of the - * target object in process virtual memory, if supported by the target. Some - * MMIO spaces may be restricted to privileged processes, depending on the used - * handle and type. - * - * After mapping the respective MMIO space, you can access it through direct - * pointer operations (observing supported access sizes and alignments of the - * target platform and accelerator). - * - * @note Some targets (such as the ASE simulator) do not support memory-mapping - * of IO register spaces and will not return a pointer to an actually mapped - * space. Instead, they will return `FPGA_NOT_SUPPORTED`. Usually, these - * platforms still allow the application to issue MMIO operations using - * fpgaReadMMIO32(), fpgaWriteMMIO32(), fpgeReadMMIO64(), and - * fpgaWriteMMIO64(). - * - * If the caller passes in NULL for mmio_ptr, no mapping will be performed, and - * no virtual address will be returned, though the call will return `FPGA_OK`. - * This implies that all accesses will be performed through fpgaReadMMIO32(), - * fpgaWriteMMIO32(), fpgeReadMMIO64(), and fpgaWriteMMIO64(). This is the only - * supported case for ASE. - * - * The number of available MMIO spaces can be retrieved through the num_mmio - * property (fpgaPropertyGetNumMMIO()). - * - * @param[in] handle Handle to previously opened resource - * @param[in] mmio_num Number of MMIO space to access - * @param[out] mmio_ptr Pointer to memory where a pointer to the MMIO space - * will be returned. May be NULL, in which case no pointer - * is returned. Returned address may be NULL if underlying - * platform does not support memory mapping for register - * access. - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. FPGA_NO_ACCESS if the process' - * permissions are not sufficient to map the requested MMIO space. - * FPGA_NOT_SUPPORTED if platform does not support memory mapped IO. - */ -fpga_result fpgaMapMMIO(fpga_handle handle, - uint32_t mmio_num, uint64_t **mmio_ptr); - -/** - * Unmap MMIO space - * - * This function will unmap a previously mapped MMIO space of the target object, - * rendering any pointers to it invalid. - * - * @note This call is only supported by hardware targets, not by ASE - * simulation. - * - * @param[in] handle Handle to previously opened resource - * @param[in] mmio_num Number of MMIO space to access - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred - * while trying to access the handle. - */ -fpga_result fpgaUnmapMMIO(fpga_handle handle, - uint32_t mmio_num); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_MMIO_H__ diff --git a/sw/include/opae/properties.h b/sw/include/opae/properties.h deleted file mode 100644 index 41d2eb05a..000000000 --- a/sw/include/opae/properties.h +++ /dev/null @@ -1,825 +0,0 @@ -// Copyright(c) 2017-2021, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file opae/properties.h - * @brief Functions for examining and manipulating `fpga_properties` objects - * - * In OPAE, `fpga_properties` objects are used both for obtaining information - * about resources and for selectively enumerating resources based on their - * properties. This file provides accessor functions (get/set) to allow reading - * and writing individual items of an `fpga_properties` object. Generally, not - * all object types supported by OPAE carry all properties. If you call a - * property accessor method on a `fpga_properties` object that does not support - * this particular property, it will return FPGA_INVALID_PARAM. - * - * # Accessor Return Values - * In addition to the return values specified in the documentation below, all - * accessor functions return FPGA_OK on success, FPGA_INVALID_PARAM if you pass - * NULL or invalid parameters (i.e. non-initialized properties objects), - * FPGA_EXCEPTION if an internal exception occurred trying to access the - * properties object, FPGA_NOT_FOUND if the requested property is not part of - * the supplied properties object. - */ - -#ifndef __FPGA_PROPERTIES_H__ -#define __FPGA_PROPERTIES_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Create a fpga_properties object - * - * Initializes the memory pointed at by `prop` to represent a properties - * object, and populates it with the properties of the resource referred to by - * `handle`. Individual properties can then be queried using fpgaPropertiesGet*() - * accessor functions. - * - * @note fpgaGetPropertiesFromHandle() will allocate memory for the created properties - * object returned in `prop`. It is the responsibility of the caller - * to free this memory after use by calling fpgaDestroyProperties(). - * - * @param[in] handle Open handle to get properties for. - * @param[out] prop Pointer to a variable of type fpga_properties - * @returns FPGA_OK on success. FPGA_NO_MEMORY if no memory could be allocated - * to create the `fpga_properties` object. FPGA_EXCEPTION if an exception - * happend while initializing the `fpga_properties` object. - */ -fpga_result fpgaGetPropertiesFromHandle(fpga_handle handle, fpga_properties *prop); - -/** - * Create a fpga_properties object - * - * Initializes the memory pointed at by `prop` to represent a properties - * object, and populates it with the properties of the resource referred to by - * `token`. Individual properties can then be queried using fpgaPropertiesGet*() - * accessor functions. - * - * If `token` is NULL, an "empty" properties object is created to be used as a - * filter for fpgaEnumerate(). All individual fields are set to `don`t care`, - * which implies that the fpga_properties object would match all FPGA resources - * if used for an fpgaEnumerate() query. The matching criteria can be further - * refined by using fpgaSet* functions on the properties object, or the - * object can be populated with the actual properties of a resource by using - * fpgaUpdateProperties(). - * - * @note fpgaGetProperties() will allocate memory for the created properties - * object returned in `prop`. It is the responsibility of the caller - * to free this memory after use by calling fpgaDestroyProperties(). - * - * @param[in] token Token to get properties for. Can be NULL, which will - * create an empty properties object to be used as a - * filter for fpgaEnumerate(). - * @param[out] prop Pointer to a variable of type fpga_properties - * @returns FPGA_OK on success. FPGA_NO_MEMORY if no memory could be allocated - * to create the `fpga_properties` object. FPGA_EXCEPTION if an exception - * happend while initializing the `fpga_properties` object. - */ -fpga_result fpgaGetProperties(fpga_token token, fpga_properties *prop); - -/** - * Update a fpga_properties object - * - * Populates the properties object 'prop' with properties of the resource - * referred to by 'token'. Unlike fpgaGetProperties(), this call will not create - * a new properties object or allocate memory for it, but use a previously - * created properties object. - * - * @param[in] token Token to retrieve properties for - * @param[in] prop fpga_properties object to update - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `token` or `prop` are not - * valid objects. FPGA_NOT_FOUND if the resource referred to by `token` was - * not found. FPGA_NO_DRIVER if not driver is loaded. FPGA_EXCEPTION if an - * internal exception occured when trying to update `prop`. - */ -fpga_result fpgaUpdateProperties(fpga_token token, fpga_properties prop); - -/** - * Clear a fpga_properties object - * - * Sets all fields of the properties object pointed at by 'prop' to 'don't - * care', which implies that the fpga_properties object would match all FPGA - * resources if used for an fpgaEnumerate() query. The matching criteria can be - * further refined by using fpgaSet* functions on the properties object. - * - * Instead of creating a new fpga_properties object every time, this function - * can be used to re-use fpga_properties objects from previous queries. - * - * @param[in] prop fpga_properties object to clear - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `prop` is not a valid - * object. FPGA_EXCEPTION if an * internal exception occured when trying to - * access `prop`. - */ -fpga_result fpgaClearProperties(fpga_properties prop); - -/** - * Clone a fpga_properties object - * - * Creates a copy of an fpga_properties object. - * - * @note This call creates a new properties object and allocates memory for it. - * Both the 'src' and the newly created 'dst' objects will eventually need to be - * destroyed using fpgaDestroyProperties(). - * - * @param[in] src fpga_properties object to copy - * @param[out] dst New fpga_properties object cloned from 'src' - * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `src` is not a valid - * object, or if `dst` is NULL. FPGA_NO_MEMORY if there was not enough memory - * to allocate an `fpga_properties` object for `dst`. FPGA_EXCEPTION if an - * internal exception occurred either accessing `src` or updating `dst`. - */ -fpga_result fpgaCloneProperties(fpga_properties src, fpga_properties *dst); - -/** - * Destroy a fpga_properties object - * - * Destroys an existing fpga_properties object that the caller has previously - * created using fpgaGetProperties() or fpgaCloneProperties(). - * - * @note fpgaDestroyProperties() requires the address of an fpga_properties - * object, similar to fpgaGetPropertiesFromHandle(), fpgaGetProperties(), - * and fpgaCloneProperties(). Passing any other value results in undefined - * behavior. - * - * @param[inout] prop Pointer to the fpga_properties object to destroy - * @returns FPGA_OK on success. FPGA_INVALID_PARAM is `prop` is not a valid - * object. FPGA_EXCEPTION if an internal exception occurrred while trying to - * access `prop`. - */ -fpga_result fpgaDestroyProperties(fpga_properties *prop); - -/** - * Get the token of the parent object - * - * Returns the token of the parent of the queried resource in '*parent'. - * - * @param[in] prop Properties object to query - * @param[out] parent Pointer to a token variable of the resource 'prop' is - * associated with - * @returns FPGA_NOT_FOUND if resource does not have a - * parent (e.g. an FPGA_DEVICE resource does not have parents). Also see - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetParent(const fpga_properties prop, - fpga_token *parent); - -/** - * Set the token of the parent object - * - * @param[in] prop Properties object to modify - * @param[out] parent Pointer to a token variable of the resource 'prop' is - * associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetParent(fpga_properties prop, - fpga_token parent); -/** - * Get the object type of a resource - * - * Returns the object type of the queried resource. - * - * @param[in] prop Properties object to query - * @param[out] objtype Pointer to an object type variable of the resource - * 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetObjectType(const fpga_properties prop, - fpga_objtype *objtype); - -/** - * Set the object type of a resource - * - * Sets the object type of the resource. * Currently supported object types are - * FPGA_DEVICE and FPGA_ACCELERATOR. - * - * @param[in] prop Properties object to modify - * @param[out] objtype Object type of the resource 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetObjectType(fpga_properties prop, - fpga_objtype objtype); -/** - * Get the PCI segment number of a resource - * - * Returns the segment number of the queried resource. - * - * @param[in] prop Properties object to query - * @param[out] segment Pointer to a PCI segment variable of the resource 'prop' - * is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetSegment(const fpga_properties prop, uint16_t *segment); - -/** - * Set the PCI segment number of a resource - * - * @param[in] prop Properties object to modify - * @param[in] segment PCI segment number of the resource 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetSegment(fpga_properties prop, uint16_t segment); - -/** - * Get the PCI bus number of a resource - * - * Returns the bus number the queried resource. - * - * @param[in] prop Properties object to query - * @param[out] bus Pointer to a PCI bus variable of the resource 'prop' - * is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetBus(const fpga_properties prop, uint8_t *bus); - -/** - * Set the PCI bus number of a resource - * - * @param[in] prop Properties object to modify - * @param[in] bus PCI bus number of the resource 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetBus(fpga_properties prop, uint8_t bus); - -/** - * Get the PCI device number of a resource - * - * Returns the device number the queried resource. - * - * @param[in] prop Properties object to query - * @param[out] device Pointer to a PCI device variable of the resource 'prop' - * is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetDevice(const fpga_properties prop, - uint8_t *device); - -/** - * Set the PCI device number of a resource - * - * Enforces the limitation on the number of devices as specified in the - * PCI spec. - * - * @param[in] prop Properties object to modify - * @param[in] device PCI device number of the resource 'prop' is associated - * with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetDevice(fpga_properties prop, - uint8_t device); - -/** - * Get the PCI function number of a resource - * - * Returns the function number the queried resource. - * - * @param[in] prop Properties object to query - * @param[out] function Pointer to PCI function variable of the - * resource 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetFunction(const fpga_properties prop, - uint8_t *function); - -/** - * Set the PCI function number of a resource - * - * Enforces the limitation on the number of functions as specified in the - * PCI spec. - * - * @param[in] prop Properties object to modify - * @param[in] function PCI function number of the resource 'prop' is - * associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetFunction(fpga_properties prop, - uint8_t function); - -/** - * Get the socket id of a resource - * - * Returns the socket id of the queried resource. - * - * @param[in] prop Properties object to query - * @param[out] socket_id Pointer to a socket id variable of the - * resource 'prop' - * is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - * See also "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetSocketID(const fpga_properties prop, - uint8_t *socket_id); - -/** - * Set the socket id of the resource - * - * @param[in] prop Properties object to modify - * @param[in] socket_id Socket id of the resource 'prop' is - * associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetSocketID(fpga_properties prop, - uint8_t socket_id); - -/** - * Get the device id of the resource - * - * @param[in] prop Properties object to query - * @param[out] device_id Pointer to a device id variable of the - * resource 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetDeviceID(const fpga_properties prop, - uint16_t *device_id); - -/** - * Set the device id of the resource - * - * @param[in] prop Properties object to modify - * @param[in] device_id Device id of the resource 'prop' is associated with - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetDeviceID(fpga_properties prop, - uint16_t device_id); - -/** - * Get the number of slots of an FPGA resource property - * - * Returns the number of slots present in an FPGA. - * - * @param[in] prop Properties object to query - must be of type FPGA_DEVICE - * @param[out] num_slots Pointer to number of slots variable of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetNumSlots(const fpga_properties prop, - uint32_t *num_slots); - -/** - * Set the number of slots of an FPGA resource property - * - * @param[in] prop Properties object to modify - must be of type - * FPGA_DEVICE - * @param[in] num_slots Number of slots of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetNumSlots(fpga_properties prop, - uint32_t num_slots); - -/** - * Get the BBS ID of an FPGA resource property - * - * Returns the blue bitstream id of an FPGA. - * - * @param[in] prop Properties object to query - must be of type FPGA_DEVICE - * @param[out] bbs_id Pointer to a bbs id variable of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetBBSID(const fpga_properties prop, - uint64_t *bbs_id); - - -/** - * Set the BBS ID of an FPGA resource property - * - * @param[in] prop Properties object to modify - must be of type - * FPGA_DEVICE - * @param[in] bbs_id Blue bitstream id of the FPGA resource - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetBBSID(fpga_properties prop, - uint64_t bbs_id); - - -/** - * Get the BBS Version of an FPGA resource property - * - * Returns the blue bitstream version of an FPGA. - * - * @param[in] prop Properties object to query - must be of type - * FPGA_DEVICE - * @param[out] bbs_version Pointer to a bbs version variable of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetBBSVersion(const fpga_properties prop, - fpga_version *bbs_version); - -/** - * Set the BBS Version of an FPGA resource property - * - * @param[in] prop Properties object to modify - must be of type - * FPGA_DEVICE - * @param[in] version Blue bitstream version of the FPGA resource - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetBBSVersion(fpga_properties prop, - fpga_version version); - - -/** - * Get the vendor id of an FPGA resource property - * - * Returns the vendor id of an FPGA. - * - * @param[in] prop Properties object to query - must be of type FPGA_DEVICE - * @param[out] vendor_id Pointer to a vendor id variable of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesGetVendorID(const fpga_properties prop, - uint16_t *vendor_id); - - -/** - * Set the vendor id of an FPGA resource property - * - * @param[in] prop Properties object to modify - must be of type FPGA_DEVICE - * @param[in] vendor_id Vendor id of the FPGA resource - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesSetVendorID(fpga_properties prop, - uint16_t vendor_id); - -/** - * Get the model of an FPGA resource property - * - * Returns the model of an FPGA. - * - * @param[in] prop Properties object to query - must be of type FPGA_DEVICE - * @param[in] model Model of the FPGA resource (string of minimum - * FPGA_MODEL_LENGTH length - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesGetModel(const fpga_properties prop, - char *model); - - -/** - * Set the model of an FPGA resource property - * - * @param[in] prop Properties object to modify - must be of type FPGA_DEVICE - * @param[in] model Model of the FPGA resource (string of maximum - * FPGA_MODEL_LENGTH length - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesSetModel(fpga_properties prop, - char *model); - - -/** - * Get the local memory size of an FPGA resource property - * - * Returns the local memory size of an FPGA. - * - * @param[in] prop Properties object to query - must be of type FPGA_DEVICE - * @param[out] lms Pointer to a memory size variable of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesGetLocalMemorySize(const fpga_properties prop, - uint64_t *lms); - - -/** - * Set the local memory size of an FPGA resource property - * - * @param[in] prop Properties object to modify - must be of type FPGA_DEVICE - * @param[in] lms Local memory size of the FPGA resource - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesSetLocalMemorySize(fpga_properties prop, - uint64_t lms); - -/** - * Get the capabilities FPGA resource property - * - * Returns the capabilities of an FPGA. - * Capabilities is a bitfield value - * - * @param[in] prop Properties object to query - must be of type - * FPGA_DEVICE - * @param[out] capabilities Pointer to a capabilities variable of the FPGA - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesGetCapabilities(const fpga_properties prop, - uint64_t *capabilities); - - -/** - * Set the capabilities of an FPGA resource property - * - * Capabilities is a bitfield value - * - * @param[in] prop Properties object to modify - must be of type - * FPGA_DEVICE - * @param[in] capabilities Capabilities of the FPGA resource - * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also - * "Accessor Return Values" in [properties.h](#properties-h). - * - * @note This API is not currently supported. - */ -fpga_result fpgaPropertiesSetCapabilities(fpga_properties prop, - uint64_t capabilities); - -/** - * Get the GUID of a resource - * - * Returns the GUID of an FPGA or accelerator object. - * - * For an accelerator, the GUID uniquely identifies a specific accelerator context type, - * i.e. different accelerators will have different GUIDs. For an FPGA, the GUID - * is used to identify a certain instance of an FPGA, e.g. to determine whether - * a given bitstream would be compatible. - * - * @param[in] prop Properties object to query - * @param[out] guid Pointer to a GUID of the slot variable - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetGUID(const fpga_properties prop, - fpga_guid *guid); - -/** - * Set the GUID of a resource - * - * Sets the GUID of an FPGA or accelerator object. - * - * For an accelerator, the GUID uniquely identifies a specific accelerator context type, - * i.e. different accelerators will have different GUIDs. For an FPGA, the GUID - * is used to identify a certain instance of an FPGA, e.g. to determine whether - * a given bitstream would be compatible. - * - * @param[in] prop Properties object to modify - * @param[out] guid Pointer to a GUID of the slot variable - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetGUID(fpga_properties prop, fpga_guid guid); - -/** - * Get the number of mmio spaces - * - * Returns the number of mmio spaces of an AFU properties structure. - * - * @param[in] prop Properties object to query - must be of type FPGA_ACCELERATOR - * @param[out] mmio_spaces Pointer to a variable for number of mmio spaces - * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetNumMMIO(const fpga_properties prop, - uint32_t *mmio_spaces); - -/** - * Set the number of mmio spaces - * - * Sets the number of mmio spaces of an AFU properties structure. - * - * @param[in] prop Properties object to modify - must be of type FPGA_ACCELERATOR - * @param[in] mmio_spaces Number of MMIO spaces of the accelerator - * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetNumMMIO(fpga_properties prop, - uint32_t mmio_spaces); - -/** - * Get the number of interrupts - * - * Returns the number of interrupts of an accelerator properties structure. - * - * @param[in] prop Properties object to query - must be of type - * FPGA_ACCELERATOR - * @param[out] num_interrupts Pointer to a variable for number of interrupts - * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetNumInterrupts(const fpga_properties prop, - uint32_t *num_interrupts); - -/** - * Set the number of interrupts - * - * Sets the number of interrupts of an accelerator properties structure. - * - * @param[in] prop Properties object to modify - must be of type - * FPGA_ACCELERATOR - * @param[in] num_interrupts Number of interrupts of the accelerator - * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetNumInterrupts(fpga_properties prop, - uint32_t num_interrupts); - -/** - * Get the state of a accelerator resource property - * - * Returns the accelerator state of a accelerator. - * - * @param[in] prop Properties object to query - must be of type FPGA_ACCELERATOR - * @param[out] state Pointer to a accelerator state variable of the accelerator - * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetAcceleratorState(const fpga_properties prop, - fpga_accelerator_state *state); - - -/** - * Set the state of an accelerator resource property - * - * @param[in] prop Properties object to modify - must be of type FPGA_ACCELERATOR - * @param[in] state accelerator state of the accelerator resource - * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetAcceleratorState(fpga_properties prop, - fpga_accelerator_state state); - -/** - * Get the object ID of a resource - * - * Returns the object ID of a resource. The object ID is a 64 bit identifier - * that is unique within a single node or system. It represents a similar - * concept as the token, but can be used across processes (e.g. passed on the - * command line). - * - * @param[in] prop Properties object to query - * @param[out] object_id Pointer to a 64bit memory location to store the object - * ID in - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetObjectID(const fpga_properties prop, - uint64_t *object_id); - - -/** - * Set the object ID of a resource - * - * Sets the object ID of a resource. The object ID is a 64 bit identifier - * that is unique within a single node or system. It represents a similar - * concept as the token, but can be used across processes (e.g. passed on the - * command line). - * - * @param[in] prop Properties object to query - * @param[in] object_id A 64bit value to use as the object ID - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetObjectID(const fpga_properties prop, - uint64_t object_id); - - -/** - * Get the number of errors that can be reported by a resource - * - * Returns the number of error registers understood by a resource. - * - * @param[in] prop Properties object to query - * @param[out] num_errors Pointer to a 32 bit memory location to store the - * number of supported errors in - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetNumErrors(const fpga_properties prop, - uint32_t *num_errors); - - -/** - * Set the number of error registers - * - * Set the number of error registers understood by a resource to enumerate. - * - * @param[in] prop Properties object to query - * @param[in] num_errors Number of errors - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetNumErrors(const fpga_properties prop, - uint32_t num_errors); - -/** - * Get the OPAE plugin interface implemented by a resource - * - * Returns the plugin interface enumerator. - * - * @param[in] prop Properties object to query - * @param[out] interface Pointer to an fpga_interface location to store the - * interface in - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetInterface(const fpga_properties prop, - fpga_interface *interface); - -/** - * Set the OPAE plugin interface implemented by a resource - * - * Set the plugin interface enumerator. - * - * @param[in] prop Properties object to query - * @param[in] interface The interface enumerator to set - * @returns See "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetInterface(const fpga_properties prop, - fpga_interface interface); - -/** - * Get the subsystem vendor id of an FPGA resource property - * - * Returns the subsystem vendor id of an FPGA. - * - * @param[in] prop Properties object to query - * @param[out] subsystem_vendor_id Pointer to a vendor id variable of the FPGA - * @returns FPGA_OK on success. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetSubsystemVendorID(const fpga_properties prop, - uint16_t *subsystem_vendor_id); - - -/** - * Set the subsystem vendor id of an FPGA resource property - * - * @param[in] prop Properties object to modify - * @param[in] subsystem_vendor_id Subsystem Vendor id of the FPGA resource - * @returns FPGA_OK on success. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetSubsystemVendorID(fpga_properties prop, - uint16_t subsystem_vendor_id); - -/** - * Get the subsystem device id of an FPGA resource property - * - * Returns the subsystem device id of an FPGA. - * - * @param[in] prop Properties object to query - * @param[out] subsystem_device_id Pointer to a device id variable of the FPGA - * @returns FPGA_OK on success. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesGetSubsystemDeviceID(const fpga_properties prop, - uint16_t *subsystem_device_id); - - -/** - * Set the subsystem device id of an FPGA resource property - * - * @param[in] prop Properties object to modify - * @param[in] subsystem_device_id Subsystem Device id of the FPGA resource - * @returns FPGA_OK on success. See also - * "Accessor Return Values" in [properties.h](#properties-h). - */ -fpga_result fpgaPropertiesSetSubsystemDeviceID(fpga_properties prop, - uint16_t subsystem_device_id); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_PROPERTIES_H__ - diff --git a/sw/include/opae/sysobject.h b/sw/include/opae/sysobject.h deleted file mode 100644 index b0872180d..000000000 --- a/sw/include/opae/sysobject.h +++ /dev/null @@ -1,242 +0,0 @@ -// Copyright(c) 2017-2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file opae/sysobject.h - * @brief Functions to read/write from system objects. - * On Linux systems with the OPAE kernel driver, this is used to access sysfs - * nodes created by the driver. - */ -#ifndef __FPGA_SYSOBJECT_H__ -#define __FPGA_SYSOBJECT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Create an `fpga_object` data structures. An `fpga_object` - * is a handle to an FPGA resource which can be an attribute, register or - * a container. This object is read-only. - * - * @param[in] token Token identifying a resource (accelerator or device) - * @param[in] name A key identifying an object belonging to a resource. - * @param[out] object Pointer to memory to store the object in - * @param[in] flags Control behavior of object identification and creation. - * FPGA_OBJECT_GLOB is used to indicate that the name should be treated as a - * globbing expression. FPGA_OBJECT_RECURSE_ONE indicates that subobjects be - * created for objects one level down from the object identified by name. - * FPGA_OBJECT_RECURSE_ALL indicates that subobjects be created for all objects - * below the current object identified by name. - * - * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_NOT_FOUND if an object cannot be found with the - * given key. FPGA_NOT_SUPPORTED if this function is not supported by the - * current implementation of this API. - * - * @note Names that begin with '.' or '/' or contain '..' are not allowed and - * result in FPGA_INVALID_PARAM being returned - * - */ -fpga_result fpgaTokenGetObject(fpga_token token, const char *name, - fpga_object *object, int flags); - -/** - * @brief Create an `fpga_object` data structure from a handle. - * An `fpga_object` is a handle to an FPGA resource which can be an attribute, - * register, or container. This object has read/write access.. - * - * @param[in] handle Handle identifying a resource (accelerator or device) - * @param[in] name A key identifying an object belonging to a resource. - * @param[out] object Pointer to memory to store the object in - * @param[in] flags Control behavior of object identification and creation - * FPGA_OBJECT_GLOB is used to indicate that the name should be treated as a - * globbing expression. FPGA_OBJECT_RECURSE_ONE indicates that subobjects be - * created for objects one level down from the object identified by name. - * FPGA_OBJECT_RECURSE_ALL indicates that subobjects be created for all objects - * below the current object identified by name. - * - * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid. FPGA_NOT_FOUND if an object cannot be found with the - * given key. FPGA_NOT_SUPPORTED if this function is not supported by the - * current implementation of this API. - * - * @note Names that begin with '.' or '/' or contain '..' are not allowed and - * result in FPGA_INVALID_PARAM being returned - * - */ -fpga_result fpgaHandleGetObject(fpga_handle handle, const char *name, - fpga_object *object, int flags); - -/** - * @brief Create an `fpga_object` data structure from a parent object. An - * `fpga_object` is a handle to an FPGA resource which can be an attribute, - * register, or container. If the parent object was created with a handle, - * then the new object will inherit the handle allowing it to have read-write - * access to the object data. - * - * @param[in] parent A parent container `fpga_object`. - * @param[in] name A key identifying a sub-object of the parent container. - * @param[out] object Pointer to memory to store the object in. - * @param[in] flags Control behavior of object identification and creation. - * FPGA_OBJECT_GLOB is used to indicate that the name should be treated as a - * globbing expression. FPGA_OBJECT_RECURSE_ONE indicates that subobjects be - * created for objects one level down from the object identified by name. - * FPGA_OBJECT_RECURSE_ALL indicates that subobjects be created for all objects - * below the current object identified by name. - * - * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid - this includes a parent object that is not a - * container object. FPGA_NOT_FOUND if an object cannot be found with the given - * key. FPGA_NOT_SUPPORTED if this function is not supported by the current - * implementation of this API. - * - * @note Names that begin with '.' or '/' or contain '..' are not allowed and - * result in FPGA_INVALID_PARAM being returned - * - */ -fpga_result fpgaObjectGetObject(fpga_object parent, const char *name, - fpga_object *object, int flags); - -/** - * @brief Create an `fpga_object` data structure from a parent object using a - * given index. An `fpga_object` is a handle to an FPGA resource which can be - * an attribute, register, or container. If the parent object was created with - * a handle, then the new object will inherit the handle allowing it to have - * read-write access to the object data. - * - * @param[in] parent A parent container 'fpga_object' - * @param[in] idx A positive index less than the size reported by the parent. - * @param[out] object Pointer to memory to store the object in. - * - * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid - this includes a parent object that is not a - * container object. FPGA_NOT_FOUND if an object cannot be found with the given - * key. FPGA_NOT_SUPPORTED if this function is not supported by the current - * implementation of this API. - */ -fpga_result fpgaObjectGetObjectAt(fpga_object parent, size_t idx, - fpga_object *object); -/** - * @brief Get the sysobject type (container or attribute) - * - * @param[in] obj An fpga_object instance - * @param[out] type The type of object (FPGA_OBJECT_CONTAINER or - * FPGA_OBJECT_ATTRIBUTE) - * - * @return FPGA_OK on success, FPGA_INVALID_PARAM if any of the supplied - * parameters are null or invalid - */ -fpga_result fpgaObjectGetType(fpga_object obj, enum fpga_sysobject_type *type); - -/** - * @brief Free memory used for the fpga_object data structure - * - * @note fpgaDestroyObject() requires the address of an fpga_object - * as created by fpgaTokenGetObject(), fpgaHandleGetObject(), - * or fpgaObjectGetObject(). Passing any other value results in - * undefind behavior. - * - * @param obj Pointer to the fpga_object instance to destroy - * - * @return FPGA_OK on success, FPGA_INVALID_PARAM if the object is NULL, - * FPGA_EXCEPTION if an internal error is encountered. - */ -fpga_result fpgaDestroyObject(fpga_object *obj); - -/** - * @brief Retrieve the size of the object. - * - * @param[in] obj An fpga_object instance. - * @param[out] value Pointer to variable to store size in. - * @param[in] flags Flags that control how the object is read - * If FPGA_OBJECT_SYNC is used then object will update its buffered copy before - * retrieving the size. - * - * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of supplied parameters - * is invalid. FPGA_EXCEPTION if error occurred. - */ -fpga_result fpgaObjectGetSize(fpga_object obj, uint32_t *value, int flags); - -/** - * @brief Read bytes from an FPGA object - * - * @param[in] obj An fpga_object instance. - * @param[out] buffer Pointer to a buffer to read bytes into. - * @param[in] offset Byte offset relative to objects internal buffer where to - * begin reading bytes from. - * @param[in] len The length, in bytes, to read from the object. - * @param[in] flags Flags that control how object is read - * If FPGA_OBJECT_SYNC is used then object will update its buffered copy before - * retrieving the data. - * - * @return FPGA_OK on success, FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid - */ -fpga_result fpgaObjectRead(fpga_object obj, uint8_t *buffer, size_t offset, - size_t len, int flags); - -/** - * @brief Read a 64-bit value from an FPGA object. - * The value is assumed to be in string format and will be parsed. See flags - * below for changing that behavior. - * - * @param[in] obj An fpga_object instance - * @param[out] value Pointer to a 64-bit variable to store the value in - * @param[in] flags Flags that control how the object is read - * If FPGA_OBJECT_SYNC is used then object will update its buffered copy before - * retrieving the data. If FPGA_OBJECT_RAW is used, then the data will be read - * as raw bytes into the uint64_t pointer variable. - * - * @return FPGA_OK on success, FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid - */ -fpga_result fpgaObjectRead64(fpga_object obj, uint64_t *value, int flags); - -/** - * @brief Write 64-bit value to an FPGA object. - * The value will be converted to string before writing. See flags below for - * changing that behavior. - * - * @param[in] obj An fpga_object instance. - * @param[in] value The value to write to the object - * @param[in] flags Flags that control how the object is written - * If FPGA_OBJECT_RAW is used, then the value will be written as raw bytes. - * - * @return FPGA_OK on success, FPGA_INVALID_PARAM if any of the supplied - * parameters is invalid - * - * @note The object must have been created using a handle to a resource. - */ -fpga_result fpgaObjectWrite64(fpga_object obj, uint64_t value, int flags); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif /* !__FPGA_SYSOBJECT_H__ */ diff --git a/sw/include/opae/types.h b/sw/include/opae/types.h deleted file mode 100644 index f947d244c..000000000 --- a/sw/include/opae/types.h +++ /dev/null @@ -1,295 +0,0 @@ -// Copyright(c) 2018-2022, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file types.h - * @brief Type definitions for FPGA API - * - * OPAE uses the three opaque types fpga_properties, fpga_token, and - * fpga_handle to create a hierarchy of objects that can be used to enumerate, - * reference, acquire, and query FPGA resources. This object model is designed - * to be extensible to account for different FPGA architectures and platforms. - * - * Initialization - * -------------- - * OPAEs management of the opaque types `fpga_properties`, - * `fpga_token`, and `fpga_handle` relies on the proper initialization of - * variables of these types. In other words, before doing anything with a - * variable of one of these opaque types, you need to first initialize them. - * - * The respective functions that initialize opaque types are: - * - * * fpgaGetProperties() and fpgaCloneProperties() for `fpga_properties` - * * fpgaEnumerate() and fpgaCloneToken() for `fpga_token` - * * fpgaOpen() for `fpga_handle` - * - * This should intuitively make sense - fpgaGetProperties() creates - * `fpga_properties` objects, fpgaEnumerate() creates `fpga_token` objects, - * fpgaOpen() creates `fpga_handle` objects, and fpgaCloneProperties() and - * fpgaCloneToken() clone (create) `fpga_properties` and `fpga_token` objects, - * respectively. - * - * Since these opaque types are interpreted as pointers (they are typedef'd to - * a `void *`), passing an uninitialized opaque type into any function except - * the respective initailzation function will result in undefined behaviour, - * because OPAE will try to follow an invalid pointer. Undefined behaviour in - * this case may include an unexpected error code, or an application crash. - * - */ - -#ifndef __FPGA_TYPES_H__ -#define __FPGA_TYPES_H__ - -#include -#include -#include -#include - -/** - * Object for expressing FPGA resource properties - * - * `fpga_properties` objects encapsulate all enumerable information about an - * FPGA resources. They can be used for two purposes: selective enumeration - * (discovery) and querying information about existing resources. - * - * For selective enumeration, usually an empty `fpga_properties` object is - * created (using fpgaGetProperties()) and then populated with the desired - * criteria for enumeration. An array of `fpga_properties` can then be passed - * to fpgaEnumerate(), which will return a list of `fpga_token` objects - * matching these criteria. - * - * For querying properties of existing FPGA resources, fpgaGetProperties() can - * also take an `fpga_token` and will return an `fpga_properties` object - * populated with information about the resource referenced by that token. - * - * After use, `fpga_properties` objects should be destroyed using - * fpga_destroyProperties() to free backing memory used by the - * `fpga_properties` object. - */ -typedef void *fpga_properties; - -/** - * Token for referencing FPGA resources - * - * An `fpga_token` serves as a reference to a specific FPGA resource present in - * the system. Holding an `fpga_token` does not constitute ownership of the - * FPGA resource - it merely allows the user to query further information about - * a resource, or to use fpgaOpen() to acquire ownership. - * - * `fpga_token`s are usually returned by fpgaEnumerate() or - * fpgaPropertiesGetParent(), and used by fpgaOpen() to acquire ownership and - * yield a handle to the resource. Some API calls also take `fpga_token`s as - * arguments if they don't require ownership of the resource in question. - */ -typedef void *fpga_token; - -/** - * Handle to an FPGA resource - * - * A valid `fpga_handle` object, as populated by fpgaOpen(), denotes ownership - * of an FPGA resource. Note that ownership can be exclusive or shared, - * depending on the flags used in fpgaOpen(). Ownership can be released by - * calling fpgaClose(), which will render the underlying handle invalid. - * - * Many OPAE C API functions require a valid token (which is synonymous with - * ownership of the resource). - */ -typedef void *fpga_handle; - -/** - * Globally unique identifier (GUID) - * - * GUIDs are used widely within OPAE for helping identify FPGA resources. For - * example, every FPGA resource has a `guid` property, which can be (and in the - * case of FPGA_ACCELERATOR resource primarily is) used for enumerating a resource of a - * specific type. - * - * `fpga_guid` is compatible with libuuid's uuid_t, so users can use libuuid - * functions like uuid_parse() to create and work with GUIDs. - */ -typedef uint8_t fpga_guid[16]; - -/** - * Semantic version - * - * Data structure for expressing version identifiers following the semantic - * versioning scheme. Used in various properties for tracking component - * versions. - */ -typedef struct { - uint8_t major; /**< Major version */ - uint8_t minor; /**< Minor version */ - uint16_t patch; /**< Revision or patchlevel */ -} fpga_version; - -/** Handle to an event object - * - * OPAE provides an interface to asynchronous events that can be generated by - * different FPGA resources. The event API provides functions to register for - * these events; associated with every event a process has registered for is an - * `fpga_event_handle`, which encapsulates the OS-specific data structure for - * event objects. - * - * After use, `fpga_event_handle` objects should be destroyed using - * fpgaDestroyEventHandle() to free backing memory used by the - * `fpga_event_handle` object. - */ -typedef void *fpga_event_handle; - -/** Information about an error register - * - * This data structure captures information about an error register exposed by - * an accelerator resource. The error API provides functions to retrieve these - * information structures from a particular resource. - */ -#define FPGA_ERROR_NAME_MAX 64 -struct fpga_error_info { - char name[FPGA_ERROR_NAME_MAX]; /** name of the error */ - bool can_clear; /** whether error can be cleared */ -}; - -/** Object pertaining to an FPGA resource as identified by a unique name - * - * An `fpga_object` represents either a device attribute or a container of - * attributes. Similar to filesystems, a '/' may be used to seperate objects in - * an object hierarchy. Once on object is acquired, it may be used to read or - * write data in a resource attribute or to query sub-objects if the object is - * a container object. The data in an object is buffered and will be kept - * around until the object is destroyed. Additionally, the data in an attribute - * can by synchronized from the owning resource using the FPGA_OBJECT_SYNC flag - * during read operations. The name identifying the object is unique with - * respect to the resource that owns it. A parent resource may be identified by - * an `fpga_token` object, by an `fpga_handle` object, or another `fpga_object` - * object. If a handle object is used when opening the object, then the object - * is opened with read-write access. Otherwise, the object is read-only. - */ -typedef void *fpga_object; - -/** FPGA Metric string size - * - * - */ -#define FPGA_METRIC_STR_SIZE 256 -/** Metric value union - * - * - */ -typedef union { - uint64_t ivalue; // Metric integer value - double dvalue; // Metric double value - float fvalue; // Metric float value - bool bvalue; // Metric bool value -} metric_value; - - -/** Metric info struct - * - * - */ -typedef struct fpga_metric_info { - uint64_t metric_num; // Metric index num - fpga_guid metric_guid; // Metric guid - char qualifier_name[FPGA_METRIC_STR_SIZE]; // Metric full name - char group_name[FPGA_METRIC_STR_SIZE]; // Metric group name - char metric_name[FPGA_METRIC_STR_SIZE]; // Metric name - char metric_units[FPGA_METRIC_STR_SIZE]; // Metric units - enum fpga_metric_datatype metric_datatype; // Metric data type - enum fpga_metric_type metric_type; // Metric group type -} fpga_metric_info; - -/** Metric struct - * - * - */ -typedef struct fpga_metric { - uint64_t metric_num; // Metric index num - metric_value value; // Metric value - bool isvalid; // Metric value is valid -} fpga_metric; - - -/** Threshold struct - * - * - */ -typedef struct threshold { - char threshold_name[FPGA_METRIC_STR_SIZE]; // Threshold name - uint32_t is_valid; // Threshold is valid - double value; // Threshold value -} threshold; - -typedef struct metric_threshold { - char metric_name[FPGA_METRIC_STR_SIZE]; // Metric Threshold name - threshold upper_nr_threshold; // Upper Non-Recoverable Threshold - threshold upper_c_threshold; // Upper Critical Threshold - threshold upper_nc_threshold; // Upper Non-Critical Threshold - threshold lower_nr_threshold; // Lower Non-Recoverable Threshold - threshold lower_c_threshold; // Lower Critical Threshold - threshold lower_nc_threshold; // Lower Non-Critical Threshold - threshold hysteresis; // Hysteresis -} metric_threshold; - -/** Internal token type header - * - * Each plugin (dfl: libxfpga.so, vfio: libopae-v.so) implements its own - * proprietary token type. This header _must_ appear at offset zero within - * that structure. - * - * eg, see lib/plugins/xfpga/types_int.h:struct _fpga_token and - * lib/plugins/vfio/opae_vfio.h:struct _vfio_token. - */ -typedef struct _fpga_token_header { - uint64_t magic; - uint16_t vendor_id; - uint16_t device_id; - uint16_t segment; - uint8_t bus; - uint8_t device; - uint8_t function; - fpga_interface interface; - fpga_objtype objtype; - uint64_t object_id; - fpga_guid guid; - uint16_t subsystem_vendor_id; - uint16_t subsystem_device_id; -} fpga_token_header; - -/** Determine token parent/child relationship - * - * Given pointers to two fpga_token_header structs, determine - * whether the first is the parent of the second. A parent will - * have objtype == FPGA_DEVICE. A child will have objtype == - * FPGA_ACCELERATOR. The PCIe address of the two headers will - * match in all but the function fields. - */ -#define fpga_is_parent_child(__parent_hdr, __child_hdr) \ -(((__parent_hdr)->objtype == FPGA_DEVICE) && \ - ((__child_hdr)->objtype == FPGA_ACCELERATOR) && \ - ((__parent_hdr)->segment == (__child_hdr)->segment) && \ - ((__parent_hdr)->bus == (__child_hdr)->bus) && \ - ((__parent_hdr)->device == (__child_hdr)->device)) - -#endif // __FPGA_TYPES_H__ diff --git a/sw/include/opae/types_enum.h b/sw/include/opae/types_enum.h deleted file mode 100644 index e8173f02c..000000000 --- a/sw/include/opae/types_enum.h +++ /dev/null @@ -1,218 +0,0 @@ -// Copyright(c) 2017-2022, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file types_enum.h - * @brief Definitions of enumerated types for the OPAE C API - * - * This file defines return and error codes, event and object types, states, - * and flags as used or reported by OPAE C API functions. - */ - -#ifndef __FPGA_TYPES_ENUM_H__ -#define __FPGA_TYPES_ENUM_H__ - -/** - * OPAE C API function return codes - * - * Every public API function exported by the OPAE C library will return one of - * these codes. Usually, FPGA_OK denotes successful completion of the requested - * operation, while any return code *other* than FPGA_OK indicates an error or - * other deviation from the expected behavior. Users of the OPAE C API should - * always check the return codes of the APIs they call, and not use output - * parameters of functions that did not execute successfully. - - * The fpgaErrStr() function converts error codes into printable messages. - * - * OPAE also has a logging mechanism that allows a developer to get more - * information about why a particular call failed with a specific message. If - * enabled, any function that returns an error code different from FPGA_OK will - * also print out a message with further details. This mechanism can be enabled - * by setting the environment variable `LIBOPAE_LOG` to 1 before running the - * respective application. - */ -typedef enum { - FPGA_OK = 0, /**< Operation completed successfully */ - FPGA_INVALID_PARAM, /**< Invalid parameter supplied */ - FPGA_BUSY, /**< Resource is busy */ - FPGA_EXCEPTION, /**< An exception occurred */ - FPGA_NOT_FOUND, /**< A required resource was not found */ - FPGA_NO_MEMORY, /**< Not enough memory to complete operation */ - FPGA_NOT_SUPPORTED, /**< Requested operation is not supported */ - FPGA_NO_DRIVER, /**< Driver is not loaded */ - FPGA_NO_DAEMON, /**< FPGA Daemon (fpgad) is not running */ - FPGA_NO_ACCESS, /**< Insufficient privileges or permissions */ - FPGA_RECONF_ERROR /**< Error while reconfiguring FPGA */ -} fpga_result; - -/** - * FPGA events - * - * OPAE currently defines the following event types that applications can - * register for. Note that not all FPGA resources and target platforms may - * support all event types. - */ -typedef enum { - FPGA_EVENT_INTERRUPT = 0, /**< Interrupt generated by an accelerator */ - FPGA_EVENT_ERROR, /**< Infrastructure error event */ - FPGA_EVENT_POWER_THERMAL /**< Infrastructure thermal event */ -} fpga_event_type; - -/* TODO: consider adding lifecycle events in the future - * to help with orchestration. Need a complete specification - * before including them in the API. Proposed events: - * FPGA_EVENT_APPEAR - * FPGA_EVENT_DISAPPEAR - * FPGA_EVENT_CHANGE - */ - -/** accelerator state */ -typedef enum { - /** accelerator is opened exclusively by another process */ - FPGA_ACCELERATOR_ASSIGNED = 0, - /** accelerator is free to be opened */ - FPGA_ACCELERATOR_UNASSIGNED -} fpga_accelerator_state; - -/** - * OPAE FPGA resources (objects) - * - * These are the FPGA resources currently supported by the OPAE object model. - */ -typedef enum { - /** FPGA_DEVICE objects represent FPGA devices and their management functionality. - * These objects can be opened (typically requires a certain privilege level or - * access permissions) and used for management functions like fpgaReconfigreSlot(). */ - FPGA_DEVICE = 0, - /** FPGA_ACCELERATOR objects represent allocatable units for accessing - * accelerated functions on the FPGA. They are frequently opened for - * interacting via control registers (MMIO), shared memory, or other, - * possibly platform-specific functions. */ - FPGA_ACCELERATOR -} fpga_objtype; - -/** - * OPAE plugin interface - * - * These are the supported plugin interfaces. - */ -typedef enum { - /** FPGA_IFC_DFL indicates that the plugin interface is the - * Device Feature List driver suite. */ - FPGA_IFC_DFL = 0, - /** FPGA_IFC_VFIO indicates that the plugin interface is the - * vfio-pci driver. */ - FPGA_IFC_VFIO, - /** FPGA_IFC_SIM_DFL indicates that the plugin interface is the - * AFU Simulation Environment simulating DFL drivers. */ - FPGA_IFC_SIM_DFL, - /** FPGA_IFC_SIM_VFIO indicates that the plugin interface is the - * AFU Simulation Environment simulating vfio-pci. */ - FPGA_IFC_SIM_VFIO, - /** FPGA_IFC_UIO indicates that the plugin interface is the - * uio-dfl driver. */ - FPGA_IFC_UIO, -} fpga_interface; - -/** - * Buffer flags - * - * These flags can be passed to the fpgaPrepareBuffer() function. - */ -enum fpga_buffer_flags { - FPGA_BUF_PREALLOCATED = (1u << 0), /**< Use existing buffer */ - FPGA_BUF_QUIET = (1u << 1), /**< Suppress error messages */ - FPGA_BUF_READ_ONLY = (1u << 2) /**< Buffer is read-only */ -}; - -/** - * Open flags - * - * These flags can be passed to the fpgaOpen() function. - */ -enum fpga_open_flags { - /** Open FPGA resource for shared access */ - FPGA_OPEN_SHARED = (1u << 0) -}; - -/** - * Reconfiguration flags - * - * These flags can be passed to the fpgaReconfigureSlot() function. - */ -enum fpga_reconf_flags { - /** Reconfigure the slot without checking if it is in use */ - FPGA_RECONF_FORCE = (1u << 0), - /** Don't configure AFU user clocks as part of PR */ - FPGA_RECONF_SKIP_USRCLK = (1u << 1) -}; - -enum fpga_sysobject_flags { - FPGA_OBJECT_SYNC = (1u << 0), /**< Synchronize data from driver */ - FPGA_OBJECT_GLOB = (1u << 1), /**< Treat names as glob expressions */ - FPGA_OBJECT_RAW = - (1u << 2), /**< Read or write object data as raw bytes */ - FPGA_OBJECT_RECURSE_ONE = - (1u - << 3), /**< Create subobjects one level down from containers */ - FPGA_OBJECT_RECURSE_ALL = - (1u - << 4) /**< Create subobjects all levels from from containers */ -}; - -enum fpga_sysobject_type { - FPGA_OBJECT_CONTAINER = - (1u << 0), /**< Represents a group of objects */ - FPGA_OBJECT_ATTRIBUTE = - (1u << 1) /**< An object with an attribute value that can be - read/written */ -}; - -/** fpga metrics types -* opae defines power,thermal, performance counter -* and afu metric types -*/ -enum fpga_metric_type { - FPGA_METRIC_TYPE_POWER, // Metric power - FPGA_METRIC_TYPE_THERMAL, // Metric Thermal - FPGA_METRIC_TYPE_PERFORMANCE_CTR, // Metric Performance counter - FPGA_METRIC_TYPE_AFU, // Metric AFU - FPGA_METRIC_TYPE_UNKNOWN // Unknown -}; - -/** Metrics data type -* -* -*/ -enum fpga_metric_datatype { - FPGA_METRIC_DATATYPE_INT, // Metric datatype integer - FPGA_METRIC_DATATYPE_FLOAT, // Metric datatype float - FPGA_METRIC_DATATYPE_DOUBLE, // Metric datatype double - FPGA_METRIC_DATATYPE_BOOL, // Metric datatype bool - FPGA_METRIC_DATATYPE_UNKNOWN // Metric datatype unknown -}; - -#endif // __FPGA_TYPES_ENUM_H__ diff --git a/sw/include/opae/uio.h b/sw/include/opae/uio.h deleted file mode 100644 index 8e3be20f2..000000000 --- a/sw/include/opae/uio.h +++ /dev/null @@ -1,175 +0,0 @@ -// Copyright(c) 2020, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file opae/uio.h - * @brief APIs to manage a PCIe device via UIO. - * - * Presents a simple interface for interacting with a DFL device that is - * bound to its UIO driver. - * See https://kernel.org/doc/html/v4.14/driver-api/uio-howto.html for a - * description of UIO. - * - * Provides APIs for opening/closing the device and for querying info about - * the MMIO regions of the device. - */ - -#ifndef __OPAE_UIO_H__ -#define __OPAE_UIO_H__ - -#include -#include - -#define OPAE_UIO_PATH_MAX 256 - -/** - * MMIO region info - * - * Describes a range of mappable MMIO. - */ -struct opae_uio_device_region { - uint32_t region_index; - uint8_t *region_ptr; - size_t region_page_offset; - size_t region_size; - struct opae_uio_device_region *next; -}; - -/** - * OPAE UIO device abstraction - * - * This structure is used to interact with the OPAE UIO API. - * Each UIO device has a file descriptor that is used to mmap its regions - * into user address space. Each device also has one or more MMIO regions. - */ -struct opae_uio { - char device_path[OPAE_UIO_PATH_MAX]; - int device_fd; - struct opae_uio_device_region *regions; -}; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Open and populate a UIO device - * - * Opens the Device Feature List device corresponding to the device name - * given in dfl_device, eg "dfl_dev.10". The device must be bound to the - * dfl-uio-pdev driver prior to opening it. The data structures corresponding - * to the MMIO regions are initialized. - * - * @param[out] u Storage for the device. May be stack-resident. - * @param[in] dfl_device The name of the desired DFL device. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.sh} - * $ sudo opaeuio -i -u lab -g lab dfl_dev.10 - * @endcode - * - * Example - * @code{.c} - * struct opae_uio u; - * - * if (opae_uio_open(&u, "dfl_dev.10")) { - * // handle error - * } - * @endcode - */ -int opae_uio_open(struct opae_uio *u, - const char *dfl_device); - -/** - * Query device MMIO region - * - * Retrieves info describing the MMIO region with the given region index. - * The device structure u must have been previously opened by a call to - * opae_uio_open. - * - * @param[in] u The open OPAE UIO device. - * @param[in] index The zero-based index of the desired MMIO region. - * @param[out] ptr Optional pointer to receive the virtual address for - * the region. Pass NULL to ignore. - * @param[out] size Optional pointer to receive the size of the MMIO region. - * Pass NULL to ignore. - * @returns Non-zero on error (including index out-of-range). Zero on success. - * - * Example - * @code{.c} - * struct opae_uio u; - * - * uint8_t *virt = NULL; - * size_t size = 0; - * - * if (opae_uio_open(&u, "dfl_dev.10")) { - * // handle error - * } else { - * opae_uio_region_get(&u, 0, &virt, &size); - * } - * @endcode - */ -int opae_uio_region_get(struct opae_uio *u, - uint32_t index, - uint8_t **ptr, - size_t *size); - -/** - * Release and close a UIO device - * - * The given device pointer must have been previously initialized by - * opae_uio_open. Releases all data structures. - * - * @param[in] u Storage for the device info. May be stack-resident. - * - * Example - * @code{.c} - * struct opae_uio u; - * - * if (opae_uio_open(&u, "dfl_dev.10")) { - * // handle error - * } else { - * // interact with the device - * ... - * // free the device - * opae_uio_close(&u); - * } - * @endcode - * - * Example - * @code{.sh} - * $ sudo opaeuio -r dfl_dev.10 - * @endcode - */ -void opae_uio_close(struct opae_uio *u); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __OPAE_UIO_H__ diff --git a/sw/include/opae/umsg.h b/sw/include/opae/umsg.h deleted file mode 100644 index 043d8f5ee..000000000 --- a/sw/include/opae/umsg.h +++ /dev/null @@ -1,114 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * \file umsg.h - * \brief FPGA UMsg API - */ - -#ifndef __FPGA_UMSG_H__ -#define __FPGA_UMSG_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Get number of Umsgs - * - * Retuns number of umsg supported by AFU. - * - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[out] value Returns number of UMsgs - * @returns FPGA_OK on success. - * FPGA_INVALID_PARAM if input parameter combination - * is not valid. - * FPGA_EXCEPTION if input parameter fpga handle is not - * valid. - */ -fpga_result fpgaGetNumUmsg(fpga_handle handle, uint64_t *value); - -/** - * Sets Umsg hint - * - * Writes usmg hint bit. - * - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] value Value to use for UMsg hint, Umsg hit is N wide bitvector - * where N = number of Umsgs. - * @returns FPGA_OK on success. - * FPGA_INVALID_PARAM if input parameter combination - * is not valid. - * FPGA_EXCEPTION if input parameter fpga handle is not - * valid. - */ -fpga_result fpgaSetUmsgAttributes(fpga_handle handle, - uint64_t value); - -/** - * Trigger Umsg - * - * Writes a 64-bit value to trigger low-latency accelerator notification mechanism - * (UMsgs). - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[in] value Value to use for UMsg - * @returns FPGA_OK on success. - * FPGA_INVALID_PARAM if input parameter combination - * is not valid. - * FPGA_EXCEPTION if input parameter fpga handle is not - * valid. - */ -fpga_result fpgaTriggerUmsg(fpga_handle handle, uint64_t value); - -/** - * Access UMsg memory directly - * - * This function will return a pointer to the memory allocated for low latency - * accelerator notifications (UMsgs). - * - * @param[in] handle Handle to previously opened accelerator resource - * @param[out] umsg_ptr Pointer to memory where a pointer to the virtual - * address space will be returned - * @returns FPGA_OK on success. - * FPGA_INVALID_PARAM if input parameter combination - * is not valid. - * FPGA_EXCEPTION if input parameter fpga handle is not - * valid. - * FPGA_NO_MEMORY if memory allocation fails or system - * doesn't configure huge pages. - */ -fpga_result fpgaGetUmsgPtr(fpga_handle handle, uint64_t **umsg_ptr); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_UMSG_H__ diff --git a/sw/include/opae/userclk.h b/sw/include/opae/userclk.h deleted file mode 100644 index 3a1879731..000000000 --- a/sw/include/opae/userclk.h +++ /dev/null @@ -1,73 +0,0 @@ -// Copyright(c) 2018, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file userclk.h - * @brief Functions for setting and get afu user clock -*/ - -#ifndef __FPGA_AFU_USER_CLOCK_H__ -#define __FPGA_AFU_USER_CLOCK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * set afu user clock high and low - * @param[in] handle Handle to previously opened accelerator resource. - * @param[in] high_clk AFU High user clock frequency in MHz. - * @param[in] low_clk AFU Low user clock frequency in MHz. - * @param[in] flags Flags Reserved. - * -.*@returns FPGA_OK on success. FPGA_INVALID_PARAM if invalid parameters were provided, or - * if the parameter combination is not valid. FPGA_EXCEPTION if an internal - * exception occurred while trying to access the handle. - */ -fpga_result fpgaSetUserClock(fpga_handle handle, - uint64_t high_clk, uint64_t low_clk, int flags); - -/** - * Get afu user clock high and low - * @param[in] handle Handle to previously opened accelerator resource. - * @param[out] high_clk AFU High user clock frequency in MHz. - * @param[out] low_clk AFU Low user clock frequency in MHz. - * @param[in] flags Flags Reserved. - * - .*@returns FPGA_OK on success. FPGA_INVALID_PARAM if invalid parameters were provided, or - * if the parameter combination is not valid. FPGA_EXCEPTION if an internal - * exception occurred while trying to access the handle. - */ -fpga_result fpgaGetUserClock(fpga_handle handle, - uint64_t *high_clk, uint64_t *low_clk, int flags); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_AFU_USER_CLOCK_H__ diff --git a/sw/include/opae/utils.h b/sw/include/opae/utils.h deleted file mode 100644 index 2675233ab..000000000 --- a/sw/include/opae/utils.h +++ /dev/null @@ -1,58 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * \file utils.h - * \brief Utility functions and macros for the FPGA API - */ - -#ifndef __FPGA_UTILS_H__ -#define __FPGA_UTILS_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Return human-readable error message - * - * Returns a pointer to a human-readable error message corresponding to the - * provided fpga_error error code. - * - * @param[in] e Error code (as returned by another FPGA API function - * @returns Pointer to a descriptive error message string - */ -const char *fpgaErrStr(fpga_result e); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_UTILS_H__ - diff --git a/sw/include/opae/version.h b/sw/include/opae/version.h deleted file mode 100644 index 5f96ecc13..000000000 --- a/sw/include/opae/version.h +++ /dev/null @@ -1,79 +0,0 @@ -// Copyright(c) 2017, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -#ifndef __FPGA_VERSION_H__ -#define __FPGA_VERSION_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Get version information about the OPAE library - * - * Retrieve major version, minor version, and revision information about the - * OPAE library. - * - * @param[out] version FPGA version - * @returns FPGA_INVALID_PARAM if any of the output parameters is NULL, FPGA_OK - * otherwise. - */ -fpga_result fpgaGetOPAECVersion(fpga_version *version); - -/** - * Get version information about the OPAE library as a string - * - * Retrieve major version, minor version, and revision information about the - * OPAE library, encoded in a human-readable string (e.g. "1.0.0"). - * - * @param[out] version_str String to copy version information into - * @param[in] len Length of `version_str` - * @returns FPGA_INVALID_PARAM if `version_str` is NULL, FPGA_EXCEPTION if the - * version string cannot be copied into `version_str`, FPGA_OK otherwise. - */ -fpga_result fpgaGetOPAECVersionString(char *version_str, size_t len); -#define FPGA_VERSION_STR_MAX 10 - -/** - * Get build information about the OPAE library as a string - * - * Retrieve the build identifier of the OPAE library. - * - * @param[out] build_str String to copy build information into - * @param[in] len Length of `build_str` - * @returns FPGA_INVALID_PARAM if `build_str` is NULL, FPGA_EXCEPTION if the - * version string cannot be copied into `build_str`, FPGA_OK otherwise. - */ -fpga_result fpgaGetOPAECBuildString(char *build_str, size_t len); -#define FPGA_BUILD_STR_MAX 41 - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __FPGA_VERSION_H__ diff --git a/sw/include/opae/vfio.h b/sw/include/opae/vfio.h deleted file mode 100644 index b5f617d9b..000000000 --- a/sw/include/opae/vfio.h +++ /dev/null @@ -1,542 +0,0 @@ -// Copyright(c) 2020-2023, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file opae/vfio.h - * @brief APIs to manage a PCIe device via vfio-pci. - * - * Presents a simple interface for interacting with a PCIe device that is - * bound to the vfio-pci driver. - * See https://kernel.org/doc/Documentation/vfio.txt for a description of - * vfio-pci. - * - * Provides APIs for opening/closing the device, querying info about the - * MMIO regions of the device, and allocating/mapping and freeing/unmapping - * DMA buffers. - */ - -#ifndef __OPAE_VFIO_H__ -#define __OPAE_VFIO_H__ - -#include -#include -#include - -#include -#include -#include - -/** - * IO Virtual Address Range - * - * A range of allocatable IOVA offsets. Used for mapping DMA buffers. - */ -struct opae_vfio_iova_range { - uint64_t start; /**< Start of this range of offsets. */ - uint64_t end; /**< End of this range of offsets. */ - struct opae_vfio_iova_range *next; /**< Pointer to next in list. */ -}; - -/** - * VFIO group - * - * Each device managed by vfio-pci belongs to a VFIO group rooted at - * /dev/vfio/N, where N is the group number. - */ -struct opae_vfio_group { - char *group_device; /**< Full path to the group device. */ - int group_fd; /**< File descriptor for the group device. */ -}; - -/** - * MMIO sparse-mappable region info - * - * Describes a range of sparse-mappable MMIO, for MMIO ranges that have - * non-contiguous addresses. - */ -struct opae_vfio_sparse_info { - uint32_t index; /**< Region index, from 0. */ - uint32_t offset; /**< Offset of sparse region. */ - uint32_t size; /**< Size of sparse region. */ - uint8_t *ptr; /**< Virtual address of sparse region. */ - struct opae_vfio_sparse_info *next; /**< Pointer to next in list. */ -}; - -/** - * MMIO region info - * - * Describes a range of mappable MMIO. - */ -struct opae_vfio_device_region { - uint32_t region_index; /**< Region index, from 0. */ - uint8_t *region_ptr; /**< Virtual address of region. */ - size_t region_size; /**< Size of region. */ - struct opae_vfio_sparse_info *region_sparse; /**< For sparse regions. */ - struct opae_vfio_device_region *next; /**< Pointer to next in list. */ -}; - -/** - * Interrupt info - * - * Describes an interrupt capability. - */ -struct opae_vfio_device_irq { - uint32_t flags; /**< Flags. See struct vfio_irq_info. */ - uint32_t index; /**< The IRQ index. */ - uint32_t count; /**< Number of IRQs at this index. */ - int32_t *event_fds; /**< Event file descriptors. */ - int32_t *masks; /**< IRQ masks. */ - struct opae_vfio_device_irq *next; /**< Pointer to next in list. */ -}; - -/** - * VFIO device - * - * Each VFIO device has a file descriptor that is used to query - * information about the device MMIO regions and config space. - */ -struct opae_vfio_device { - int device_fd; /**< Device file descriptor. */ - uint64_t device_config_offset; /**< Offset of PCIe config space. */ - uint32_t device_num_regions; /**< Total MMIO region count. */ - struct opae_vfio_device_region *regions; /**< Region list pointer. */ - uint32_t device_num_irqs; /**< IRQ index count. */ - struct opae_vfio_device_irq *irqs; /**< IRQ list pointer. */ -}; - -/** - * System DMA buffer - * - * Describes a system memory address space that is capable of DMA. - */ -struct opae_vfio_buffer { - uint8_t *buffer_ptr; /**< Buffer virtual address. */ - size_t buffer_size; /**< Buffer size. */ - uint64_t buffer_iova; /**< Buffer IOVA address. */ - int flags; /**< See opae_vfio_buffer_flags. */ -}; - -/** - * OPAE VFIO device abstraction - * - * This structure is used to interact with the OPAE VFIO API. It tracks - * data related to the VFIO container, group, and device. A mutex is - * provided for thread safety. - */ -struct opae_vfio { - pthread_mutex_t lock; /**< For thread safety. */ - char *cont_device; /**< "/dev/vfio/vfio" */ - char *cont_pciaddr; /**< PCIe address, eg 0000:00:00.0 */ - int cont_fd; /**< Container file descriptor. */ - struct opae_vfio_iova_range *cont_ranges; /**< List of IOVA ranges. */ - struct mem_alloc iova_alloc; /**< Allocator for IOVA space. */ - struct opae_vfio_group group; /**< The VFIO device group. */ - struct opae_vfio_device device; /**< The VFIO device. */ - opae_hash_map cont_buffers; /**< Map of allocated DMA buffers. */ -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Open and populate a VFIO device - * - * Opens the PCIe device corresponding to the address given in pciaddr. - * The device must be bound to the vfio-pci driver prior to opening it. - * The data structures corresponding to IOVA space, MMIO regions, - * and DMA buffers are initialized. - * - * @param[out] v Storage for the device info. May be stack-resident. - * @param[in] pciaddr The PCIe address of the requested device. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.sh} - * $ sudo opaevfio -i 0000:00:00.0 -u user -g group - * @endcode - * - * Example - * @code{.c} - * opae_vfio v; - * - * if (opae_vfio_open(&v, "0000:00:00.0")) { - * // handle error - * } - * @endcode - */ -int opae_vfio_open(struct opae_vfio *v, - const char *pciaddr); - -/** - * Open and populate a VFIO device - * - * Opens the PCIe device corresponding to the address given in pciaddr, - * using the VF token (GUID) given in token. - * The device must be bound to the vfio-pci driver prior to opening it. - * The data structures corresponding to IOVA space, MMIO regions, - * and DMA buffers are initialized. - * - * @param[out] v Storage for the device info. May be stack-resident. - * @param[in] pciaddr The PCIe address of the requested device. - * @param[in] token The GUID representing the VF token. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.sh} - * $ sudo opaevfio -i 0000:00:00.0 -u user -g group - * @endcode - * - * Example - * @code{.c} - * opae_vfio v; - * - * if (opae_vfio_secure_open(&v, "0000:00:00.0", - * "00f5ad6b-2edd-422e-9d1e-34124c686fec")) { - * // handle error - * } - * @endcode - */ -int opae_vfio_secure_open(struct opae_vfio *v, - const char *pciaddr, - const char *token); - -/** - * Query device MMIO region - * - * Retrieves info describing the MMIO region with the given region index. - * The device structure v must have been previously opened by a call - * to opae_vfio_open. - * - * @param[in] v The open OPAE VFIO device. - * @param[in] index The zero-based index of the desired MMIO region. - * @param[out] ptr Optional pointer to receive the virtual address - * for the region. Pass NULL to ignore. - * @param[out] size Optional pointer to receive the size of the MMIO - * region. Pass NULL to ignore. - * @returns Non-zero on error (including index out-of-range). Zero on success. - * - * Example - * @code{.c} - * opae_vfio v; - * - * uint8_t *fme_virt = NULL; - * uint8_t *port_virt = NULL; - * size_t fme_size = 0; - * size_t port_size = 0; - * - * if (opae_vfio_open(&v, "0000:00:00.0")) { - * // handle error - * } else { - * opae_vfio_region_get(&v, 0, &fme_virt, &fme_size); - * opae_vfio_region_get(&v, 2, &port_virt, &port_size); - * } - * @endcode - */ -int opae_vfio_region_get(struct opae_vfio *v, - uint32_t index, - uint8_t **ptr, - size_t *size); - -/** - * Allocate and map system buffer - * - * Allocate, map, and retrieve info for a system buffer capable of - * DMA. Saves an entry in the v->cont_buffers list. If the buffer - * is not explicitly freed by opae_vfio_buffer_free, it will be - * freed during opae_vfio_close. - * - * mmap is used for the allocation. If the size is greater than 2MB, - * then the allocation request is fulfilled by a 1GB huge page. Else, - * if the size is greater than 4096, then the request is fulfilled by - * a 2MB huge page. Else, the request is fulfilled by the non-huge - * page pool. - * - * @note Allocations from the huge page pool require that huge pages - * be configured on the system. Huge pages may be configured on the - * kernel boot command prompt. - * Example - * default_hugepagesz=1G hugepagesz=1G hugepages=2 hugepagesz=2M hugepages=8 - * - * @note Huge pages may also be configured at runtime. - * Example - * sudo sh -c 'echo 8 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages' - * sudo sh -c 'echo 2 > /sys/kernel/mm/hugepages/hugepages-1048576kB/nr_hugepages' - * - * @note Be sure that the IOMMU is also enabled using the follow kernel - * boot command: intel_iommu=on - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in, out] size A pointer to the requested size. The size - * may be rounded to the next page size prior - * to return from the function. - * @param[out] buf Optional pointer to receive the virtual address - * for the buffer. Pass NULL to ignore. - * @param[out] iova Optional pointer to receive the IOVA address - * for the buffer. Pass NULL to ignore. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.c} - * opae_vfio v; - * - * size_t sz; - * uint8_t *buf_2m_virt = NULL; - * uint8_t *buf_1g_virt = NULL; - * uint64_t buf_2m_iova = 0; - * uint64_t buf_1g_iova = 0; - * - * if (opae_vfio_open(&v, "0000:00:00.0")) { - * // handle error - * } else { - * sz = 2 * 1024 * 1024; - * if (opae_vfio_buffer_allocate(&v, - * &sz, - * &buf_2m_virt, - * &buf_2m_iova)) { - * // handle allocation error - * } - * - * sz = 1024 * 1024 * 1024; - * if (opae_vfio_buffer_allocate(&v, - * &sz, - * &buf_1g_virt, - * &buf_1g_iova)) { - * // handle allocation error - * } - * } - * @endcode - */ -int opae_vfio_buffer_allocate(struct opae_vfio *v, - size_t *size, - uint8_t **buf, - uint64_t *iova); - -/** Flags for opae_vfio_buffer_allocate_ex(). - */ -enum opae_vfio_buffer_flags { - OPAE_VFIO_BUF_PREALLOCATED = 1, /**< Use existing buffer */ -}; - -/** - * Allocate and map system buffer (extended w/ flags) - * - * Allocate, map, and retrieve info for a system buffer capable of - * DMA. Saves an entry in the v->cont_buffers list. If the buffer - * is not explicitly freed by opae_vfio_buffer_free, it will be - * freed during opae_vfio_close, unless OPAE_VFIO_BUF_PREALLOCATED - * is used in which case the buffer is not freed by this library. - * - * When not using OPAE_VFIO_BUF_PREALLOCATED, mmap is used for the - * allocation. If the size is greater than 2MB, then the allocation - * request is fulfilled by a 1GB huge page. Else, if the size is - * greater than 4096, then the request is fulfilled by a 2MB huge - * page. Else, the request is fulfilled by the non-huge page pool. - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in, out] size A pointer to the requested size. The size - * may be rounded to the next page size prior - * to return from the function. - * @param[out] buf Optional pointer to receive the virtual address - * for the buffer/input buffer pointer when - * using OPAE_VFIO_BUF_PREALLOCATED. Pass NULL - * to ignore. - * @param[out] iova Optional pointer to receive the IOVA address - * for the buffer. Pass NULL to ignore. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.c} - * opae_vfio v; - * - * size_t sz = MY_BUF_SIZE; - * uint8_t *prealloc_virt = NULL; - * uint64_t iova = 0; - * - * prealloc_virt = allocate_my_buffer(sz); - * - * if (opae_vfio_open(&v, "0000:00:00.0")) { - * // handle error - * } else { - * if (opae_vfio_buffer_allocate_ex(&v, - * &sz, - * &prealloc_virt, - * &iova, - * OPAE_VFIO_BUF_PREALLOCATED)) { - * // handle allocation error - * } - * } - * @endcode - */ -int opae_vfio_buffer_allocate_ex(struct opae_vfio *v, - size_t *size, - uint8_t **buf, - uint64_t *iova, - int flags); - -/** - * Extract the internal data structure pointer for the given vaddr - * - * The virtual address vaddr must correspond to a buffer previously - * allocated by opae_vfio_buffer_allocate() or - * opae_vfio_buffer_allocate_ex(). - * - * @param[in] v The open OPAE VFIO device. - * @param[in] vaddr The user virtual address of the desired buffer - * info struct. - * @returns NULL on lookup error. - */ -struct opae_vfio_buffer *opae_vfio_buffer_info(struct opae_vfio *v, - uint8_t *vaddr); - -/** - * Unmap and free a system buffer - * - * The buffer corresponding to buf must have been created by a - * previous call to opae_vfio_buffer_allocate. - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in] buf The virtual address corresponding to - * the buffer to be freed. - * @returns Non-zero on error. Zero on success. - * - * Example - * @code{.c} - * size_t sz; - * uint8_t *buf_2m_virt = NULL; - * uint64_t buf_2m_iova = 0; - * - * sz = 2 * 1024 * 1024; - * if (opae_vfio_buffer_allocate(&v, - * &sz, - * &buf_2m_virt, - * &buf_2m_iova)) { - * // handle allocation error - * } else { - * // use the buffer - * - * if (opae_vfio_buffer_free(&v, buf_2m_virt)) { - * // handle free error - * } - * } - * @endcode - */ -int opae_vfio_buffer_free(struct opae_vfio *v, - uint8_t *buf); - -/** - * Enable an IRQ - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in] index The IRQ category. For MSI-X, - * use VFIO_PCI_MSIX_IRQ_INDEX. - * @param[in] subindex The IRQ to enable. - * @param[in] event_fd The file descriptor, created - * by eventfd(). Interrupts will - * result in this event_fd being - * signaled. - * @returns Non-zero on error. Zero on success. - */ -int opae_vfio_irq_enable(struct opae_vfio *v, - uint32_t index, - uint32_t subindex, - int event_fd); - -/** - * Unmask an IRQ - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in] index The IRQ category. For MSI-X, - * use VFIO_PCI_MSIX_IRQ_INDEX. - * @param[in] subindex The IRQ to unmask. - * @returns Non-zero on error. Zero on success. - */ -int opae_vfio_irq_unmask(struct opae_vfio *v, - uint32_t index, - uint32_t subindex); - -/** - * Mask an IRQ - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in] index The IRQ category. For MSI-X, - * use VFIO_PCI_MSIX_IRQ_INDEX. - * @param[in] subindex The IRQ to mask. - * @returns Non-zero on error. Zero on success. - */ -int opae_vfio_irq_mask(struct opae_vfio *v, - uint32_t index, - uint32_t subindex); - -/** - * Disable an IRQ - * - * @param[in, out] v The open OPAE VFIO device. - * @param[in] index The IRQ category. For MSI-X, - * use VFIO_PCI_MSIX_IRQ_INDEX. - * @param[in] subindex The IRQ to disable. - * @returns Non-zero on error. Zero on success. - */ -int opae_vfio_irq_disable(struct opae_vfio *v, - uint32_t index, - uint32_t subindex); - -/** - * Release and close a VFIO device - * - * The given device pointer must have been previously initialized by - * opae_vfio_open. Releases all data structures, including any DMA - * buffer allocations that have not be explicitly freed by - * opae_vfio_buffer_free. - * - * @param[in] v Storage for the device info. May be stack-resident. - * - * Example - * @code{.c} - * opae_vfio v; - * - * if (opae_vfio_open(&v, "0000:00:00.0")) { - * // handle error - * } else { - * // interact with the device - * ... - * // free the device - * opae_vfio_close(&v); - * } - * @endcode - * - * Example - * @code{.sh} - * $ sudo opaevfio -r 0000:00:00.0 - * @endcode - */ -void opae_vfio_close(struct opae_vfio *v); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // __OPAE_VFIO_H__ diff --git a/sw/install_guide/installation_guide/index.html b/sw/install_guide/installation_guide/index.html deleted file mode 100644 index 3f75038ae..000000000 --- a/sw/install_guide/installation_guide/index.html +++ /dev/null @@ -1,2452 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - OPAE Installation Guide - OFS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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OPAE Installation Guide

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How to download the OPAE SDK

-

OPAE SDK releases are available on GitHub. -Source code for the OPAE DFL device driver for Linux is also available on GitHub.

-

Install the Fedora

-

Download the Fedora (x86_64 version) installation file in fedora, and install the Fedora in yourserver. You can choose Fedora Workstation or Fedora server.

-

Build the kernel and DFL drivers

-

For building the OPAE kernel and kernel driver, the kernel development environment is required. So before you build the kernel, you must install the required packages. Run the following commands:

-
subscription-manager release --set=8.6
-sudo dnf update
-
-# If you require the use of a proxy, add it to DNF using by editing the following file
-sudo nano /etc/dnf/dnf.conf
-# Include your proxy by adding the following line, replacing the URL with your proxy's URL
-# proxy=http://proxy.server.com:port
-sudo dnf update
-subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms
-sudo dnf install https://dl.fedoraproject.org/pub/epel/epel-release-latest-8.noarch.rpm
-
-sudo dnf install -y python3 python3-pip python3-devel \
-gdb vim git gcc gcc-c++ make cmake libuuid-devel rpm-build systemd-devel nmap \
-python3-jsonschema json-c-devel tbb-devel rpmdevtools libcap-devel \
-python3-pyyaml hwloc-devel libedit-devel git kernel-headers kernel-devel elfutils-libelf-devel ncurses-devel openssl-devel bison flex cli11-devel spdlog-devel
-
-python3 -m pip install --user jsonschema virtualenv pudb pyyaml
-
-sudo pip3 uninstall setuptools
-
-sudo pip3 install Pybind11==2.10.0 --proxy http://yourproxy:xxx
-
-sudo pip3 install setuptools==59.6.0 --prefix=/usr --proxy http://yourproxy:xxx
-
-wget http://ftp.pbone.net/mirror/archive.fedoraproject.org/epel/8.4/Everything/x86_64/Packages/p/pybind11-devel-2.4.3-2.el8.x86_64.rpm
-
-wget http://ftp.pbone.net/mirror/archive.fedoraproject.org/epel/8.4/Everything/x86_64/Packages/p/python3-pybind11-2.4.3-2.el8.x86_64.rpm
-
-sudo dnf localinstall ./python3-pybind11-2.4.3-2.el8.x86_64.rpm ./pybind11-devel-2.4.3-2.el8.x86_64.rpm -y
-
-

Download the OPAE upstream kernel tree from github, for example download from fpga-ofs-dev-5.15-lts branch. -

git clone https://github.com/OFS/linux-dfl
-cd linux-dfl
-git checkout tags/ofs-2023.1-6.1-1
-

-

Note: The linux-dfl repository is roughly 5 GB in size

-

Building and Installing the OFS DFL Kernel Drivers from Source

-
    -
  1. The following set of instructions walk you through copying an existing kernel configuration file on your machine and changing the minimal required configuration settings:
    2. -
-
cd linux-dfl
-cp /boot/config-`uname -r` .config
-cat configs/dfl-config >> .config
-echo 'CONFIG_LOCALVERSION="-dfl"' >> .config
-echo 'CONFIG_LOCALVERSION_AUTO=y' >> .config
-sed -i -r 's/CONFIG_SYSTEM_TRUSTED_KEYS=.*/CONFIG_SYSTEM_TRUSTED_KEYS=""/' .config
-sed -i '/^CONFIG_DEBUG_INFO_BTF/ s/./#&/' .config
-echo 'CONFIG_DEBUG_ATOMIC_SLEEP=y' >> .config
-make olddefconfig
-
-
-

Note: The above command may report errors resembling symbol value 'm' invalid for CHELSIO_IPSEC_INLINE. These errors indicate that the nature of the config has changed between the currently executing kernel and the kernel being built. The option "m" for a particular kernel module is no longer a valid option, and the default behavior is to simply turn the option off. However the option can likely be turned back on by setting it to 'y'. If the user wants to turn the option back on, change it to 'y' and re-run "make olddefconfig":

-
cd /home/OFS/linux-dfl
-echo 'CONFIG_CHELSIO_IPSEC_INLINE=y' >> .config
-make olddefconfig
-
-

(Optional) To use the built-in GUI menu for editing kernel configuration parameters, you can opt to run make menuconfig.

-
-

2. Linux kernel builds take advantage of multiple processors to parallelize the build process. Display how many processors are available with the nproc command, and then specify how many make threads to utilize with the -j option. Note that number of threads can exceed the number of processors. In this case, the number of threads are set to the number of processors in the system

-
$ make -j $(nproc)
-$ sudo make modules_install -j $(nproc)
-$ sudo make install
-
-

Build linux DFL Kernel instructions please also refer to: https://github.com/OPAE/linux-dfl/wiki/Build-the-linux-dfl-kernel

-

Locally building a set of RPM/DEP packages.

-
    -
  1. -

    This first flow will directly install the kernel and kernel module files without the need to create a package first:

    -
    cd /<your_path>/linux-dfl
-make INSTALL_MOD_STRIP=1 binrpm-pkg
-
    -
    2. -
  2. -

    By default a directory is created in your home directory called rpmbuild. This directory will house all of the kernel packages which have been built. You need to navigate to the newly built kernel packages and install them. The following files were generated using the build command executed in the previous step:

    -
    cd ~/rpmbuild/RPMS/x86_64
-ls
-kernel-${{ env.DFL_KERNEL_NAME }}.x86_64.rpm  kernel-headers-${{ env.DFL_KERNEL_NAME }}.x86_64.rpm
-sudo dnf localinstall kernel*.rpm
-
    -
    3. -
  3. -

    When install finished, reboot your system. - When the system login again, verify the kernel version is correct. For example:

    -
    4. -
-
[figo@localhost linux-dfl]$ uname -r
-${{ env.DFL_KERNEL_NAME }}
-
-

And also you can check the OPAE dfl drivers have auto-loaded. -

[figo@localhost linux-dfl]$ lsmod | grep fpga
-ifpga_sec_mgr          20480  1 intel_m10_bmc_secure
-fpga_region            20480  3 dfl_fme_region,dfl_fme,dfl
-fpga_bridge            24576  4 dfl_fme_region,fpga_region,dfl_fme,dfl_fme_br
-fpga_mgr               16384  4 dfl_fme_region,fpga_region,dfl_fme_mgr,dfl_fme
-[figo@localhost linux-dfl]$ lsmod | grep dfl
-dfl_eth_group          36864  0
-dfl_fme_region         20480  0
-dfl_emif               16384  0
-dfl_n3000_nios         20480  0
-dfl_fme_br             16384  0
-dfl_fme_mgr            20480  1
-dfl_fme                49152  0
-dfl_afu                36864  0
-dfl_pci                20480  0
-dfl                    40960  7 dfl_pci,dfl_fme,dfl_fme_br,dfl_eth_group,dfl_n3000_nios,dfl_afu,dfl_emif
-fpga_region            20480  3 dfl_fme_region,dfl_fme,dfl
-fpga_bridge            24576  4 dfl_fme_region,fpga_region,dfl_fme,dfl_fme_br
-fpga_mgr               16384  4 dfl_fme_region,fpga_region,dfl_fme_mgr,dfl_fme
-

-
    -
  1. Two kernel parameters must be added to the boot commandline for the newly installed kernel. First, open the file grub:
    2. -
-
sudo vim /etc/default/grub
-
-
    -
  1. In the variable GRUB_CMDLINE_LINUX add the following parameters in bold: GRUB_CMDLINE_LINUX="crashkernel=auto resume=/dev/mapper/cl-swap rd.lvm.lv=cl/root rd.lvm.lv=cl/swap rhgb quiet intel_iommu=on pcie=realloc hugepagesz=2M hugepages=200"
    2. -
-

Note: If you wish to instead set hugepages on a per session bassis, you can perform the following steps. These settings will be lost on reboot.

-
mkdir -p /mnt/huge 
-mount -t hugetlbfs nodev /mnt/huge 
-echo 2048 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages 
-echo 2048 > /sys/devices/system/node/node1/hugepages/hugepages-2048kB/nr_hugepages 
-
-
    -
  1. Save your edits, then apply them to the GRUB2 configuration file.
    2. -
-
sudo grub2-mkconfig
-
-
    -
  1. Warm reboot. Your kernel parameter changes should have taken affect.
    2. -
-
cat /proc/cmdline
-BOOT_IMAGE=(hd1,gpt2)/vmlinuz-${{ env.DFL_KERNEL_NAME }} root=/dev/mapper/cl-root ro crashkernel=auto resume=/dev/mapper/cl-swap rd.lvm.lv=cl/root rd.lvm.lv=cl/swap intel_iommu=on pcie=realloc hugepagesz=2M hugepages=200 rhgb quiet
-
-

Build the OPAE-SDK

-

Before you build the OPAE SDK, you must install the required packages. Run the following commands:

-

Rocky Linux 8.5

-
dnf install -y 'dnf-command(config-manager)'
-dnf config-manager --set-enabled powertools
-dnf install -y epel-release
-dnf check-update
-dnf upgrade -y
-dnf install -y python3 python3-pip python3-devel python3-jsonschema python3-pyyaml python3-pybind11 git gcc gcc-c++ make cmake libuuid-devel json-c-devel hwloc-devel tbb-devel cli11-devel spdlog-devel libedit-devel systemd-devel rpm-build rpmdevtools pybind11-devel yaml-cpp-devel libudev-devel linuxptp rsync 
-python3 -m pip install jsonschema virtualenv pyyaml
-
-

Fedora

-
dnf check-update
-dnf upgrade -y
-dnf install -y python3 python3-pip python3-devel python3-jsonschema python3-pyyaml python3-pybind11 git gcc g++ make cmake libuuid-devel json-c-devel hwloc-devel tbb-devel libedit-devel rpm-build rpmdevtools pybind11-devel yaml-cpp-devel libudev-devel cli11-devel spdlog-devel linuxptp rsync
-pip3 install jsonschema virtualenv pyyaml
-
-

Ubuntu 20.04

-
apt-get update
-apt-get upgrade -y
-apt-get install -y python3 python3-pip python3-dev git gcc g++ make cmake uuid-dev libjson-c-dev libhwloc-dev libtbb-dev libedit-dev libudev-dev linuxptp pandoc devscripts debhelper doxygen rsync
-pip3 install jsonschema virtualenv pyyaml pybind11
-
-

RHEL 8.2

-

Register and enable Red Hat subscription to install any packages on the system.

-
subscription-manager register --proxy=PROXY --username=USER --password=PASSWORD --auto-attach
-
-

Set the RHEL version and install packages. Set proxy name and port number.

-
# If you require the use of a proxy, add it to DNF using by editing the following file
-sudo nano /etc/dnf/dnf.conf
-# Include your proxy by adding the following line, replacing the URL with your proxy's URL
-# proxy=http://proxy.server.com:port
-sudo dnf update
-subscription-manager release --set=8.2 --proxy proxy-name.com:port number
-subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms
-sudo dnf install https://dl.fedoraproject.org/pub/epel/epel-release-latest-8.noarch.rpm
-
-sudo dnf install -y python3 python3-pip python3-devel \
-gdb vim git gcc gcc-c++ make cmake libuuid-devel rpm-build systemd-devel nmap \
-python3-jsonschema json-c-devel tbb-devel rpmdevtools libcap-devel \
-python3-pyyaml hwloc-devel libedit-devel git kernel-headers kernel-devel elfutils-libelf-devel ncurses-devel openssl-devel bison flex cli11-devel spdlog-devel
-
-python3 -m pip install --user jsonschema virtualenv pudb pyyaml
-
-sudo pip3 uninstall setuptools
-
-sudo pip3 install Pybind11==2.10.0 --proxy http://yourproxy:xxx
-
-sudo pip3 install setuptools==59.6.0 --prefix=/usr --proxy http://yourproxy:xxx
-
-wget http://ftp.pbone.net/mirror/archive.fedoraproject.org/epel/8.4/Everything/x86_64/Packages/p/pybind11-devel-2.4.3-2.el8.x86_64.rpm
-
-wget http://ftp.pbone.net/mirror/archive.fedoraproject.org/epel/8.4/Everything/x86_64/Packages/p/python3-pybind11-2.4.3-2.el8.x86_64.rpm
-
-sudo dnf localinstall ./python3-pybind11-2.4.3-2.el8.x86_64.rpm ./pybind11-devel-2.4.3-2.el8.x86_64.rpm -y
-
-

Install the latest version of cmake on top of the outdated cmake package from the package manager.

-
# cd cmake-3.25.1/
-# ./bootstrap --prefix=/usr
-# make
-# make install
-# which cmake
-/usr/bin/cmake
-
-

Create opae-sdk packages

-

Download the OPAE-SDK source code from github. For example, download from Master branch.

-
$ git clone https://github.com/OPAE/opae-sdk.git
-$ cd opae-sdk
-$ git checkout tags/2.5.0-3
-
-

Compile and build the OPAE-SDK RPMs (Fedora, Rocky, RHEL 8.2). -

$ cd opae-sdk/packaging/opae/rpm
-$ ./create fedora
-

-

OPAE Package Description

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Package NameDescription
opaeOPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack.
opae-debuginfoThis package provides debug information for package opae. Debug information is useful when developing applications that use this package or when debugging this package.
opae-debugsourceThis package provides debug sources for package opae. Debug sources are useful when developing applications that use this package or when debugging this package.
opae-develOPAE headers, tools, sample source, and documentation
opae-devel-debuginfoThis package provides debug information for package opae-devel. Debug information is useful when developing applications that use this package or when debugging this package.
opae-toolsThis package contains OPAE base tools binaries
opae-extra-toolsAdditional OPAE tools
opae-extra-tools-debuginfoThis package provides debug information for package opae-extra-tools. Debug information is useful when developing applications that use this package or when debugging this package.
-

Note that if you find that your distribution has changed package names such that there is a conflict -when building RPMs, you can install all of the build dependencies so that the SDK compiles and then -build the RPMs in unrestricted mode:

-
$ cd opae-sdk/packaging/opae/rpm
-$ ./create unrestricted
-
-

After a successful compile, there are 3 rpm packages generated (Fedora, Rocky, RHEL8.2). For example: -

opae-2.5.0-3.fc34.x86_64.rpm
-opae-devel-2.5.0-3.fc34.x86_64.rpm
-opae-extra-tools-2.5.0-3.fc34.x86_64.rpm
-

-

Compile and build the OPAE-SDK deb packages (Ubuntu 22.04). -

$ cd opae-sdk/packaging/opae/deb
-$ ./create
-

-

After a successful compile, there are 3 deb packages generated (Ubuntu 22.04). For example: -

opae_2.5.0-3_amd64.deb  
-opae-devel_2.5.0-3_amd64.deb  
-opae-extra-tools_2.5.0-3_amd64.deb
-

-

OPAE SDK installation with rpm/deb packages

-

The rpm packages generated in the previous step can be installed using these commands:

-
rm -rf opae-2.5.0-3.el8.src.rpm
-sudo dnf localinstall -y opae*.rpm
-
-

Check that all packages have been installed:

-
[user@localhost opae-sdk]# rpm -qa | grep opae
-opae-packager-2.5.0-3.x86_64
-opae-devel-2.5.0-3.x86_64
-opae-PACSign-2.5.0-3.x86_64
-opae-tools-extra-2.5.0-3.x86_64
-opae-2.5.0-3.x86_64
-opae-tools-2.5.0-3.x86_64
-opae-libs-2.5.0-3.x86_64
-opae-opae.admin-2.5.0-3.x86_64
-opae-tests-2.5.0-3.x86_64
-
-

The deb packages generated in the previous step can be installed using these commands:

-
rm -rf opae-2.5.0-3_amd64.deb
-sudo dpkg -i  ./*.deb
-
-

When you installed the rpms, you can run fpgainfo command to check the FPGA FME infomation. For example: -

[figo@localhost install_guide]$ fpgainfo fme
-Board Management Controller, xxxx NIOS FW version: xxxxxx
-Board Management Controller, xxxx Build version: xxxxx
-//****** FME ******//
-Object Id                        : 0xEF00000
-PCIe s:b:d.f                     : 0000:08:00.0
-Device Id                        : 0x0B30
-Socket Id                        : 0x00
-Ports Num                        : 01
-Bitstream Id                     : 0x2300011001030F
-Bitstream Version                : 0.2.3
-Pr Interface Id                  : f3c99413-5081-4aad-bced-07eb84a6d0bb
-Boot Page                        : user
-

-

To uninstall the OPAE rpms, you can use this commands -

$ dnf list installed | grep opae
-$ sudo dnf remove opae*.x86_64
-

-

To uninstall the OPAE deb, you can use this commands -

$ dpkg -l  | grep opae
-$ dpkg -r opae-extra-tools:amd64
-$ dpkg -r opae-devel:amd64
-$ dpkg -r opae
-

-

FPGA Device Access Permissions

-

Access to FPGA accelerators and devices is controlled using file access permissions on the -Intel® FPGA device files, /dev/dfl-fme.* and /dev/dfl-port.*, as well as to the files reachable through /sys/class/fpga_region/.

-

In order to allow regular (non-root) users to access accelerators, you need to grant them read and write permissions on /dev/dfl-port.* (with * denoting the respective socket, i.e. 0 or 1). E.g.:

-
$ sudo chmod a+rw /dev/dfl-port.0
-
-

Memlock limit

-

Depending on the requirements of your application, you may also want to -increase the maximum amount of memory a user process is allowed to lock. The -exact way to do this depends on your Linux distribution.

-

You can check the current memlock limit using

-
$ ulimit -l
-
-

A way to permanently remove the limit for locked memory for a regular user is -to add the following lines to your /etc/security/limits.conf:

-
user1    hard   memlock           unlimited
-user1    soft   memlock           unlimited
-
-

This removes the limit on locked memory for user user1. To remove it for -all users, you can replace user1 with *:

-
*    hard   memlock           unlimited
-*    soft   memlock           unlimited
-
-

Note that settings in the /etc/security/limits.conf file don't apply to -services. To increase the locked memory limit for a service you need to -modify the application's systemd service file and add the line:

-
[Service]
-LimitMEMLOCK=infinity
-
-

Hugepage Settings

-

Users need to configure system hugepages to reserve 2MB-hugepages or -1GB-hugepages. For example, the 'hello_fpga' sample requires several -2MB-hugepages. And the fpgadiag tool requires several 1GB-hugepages.

-

The command below reserves 20 2M-hugepages:

-
$ sudo sh -c 'echo 20 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages'
-
-

The command below reserves 4 1GB-hugepages:

-
$ sudo sh -c 'echo 4 > /sys/kernel/mm/hugepages/hugepages-1048576kB/nr_hugepages'
-
-

For x86_64 architecture processors, user can use following command to find out avaiable hugepage sizes:

-
$ grep pse /proc/cpuinfo | uniq
-flags : ... pse ...
-
-

If this commands returns a non-empty string, 2MB pages are supported.

-
$ grep pse /proc/cpuinfo | uniq
-flags : ... pdpe1gb ...
-
-

If this commands returns a non-empty string, 1GB pages are supported.

- - - - - - -
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OPAE Python Bindings

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OPAE (Open Programmable Acceleration Engine) now includes Python bindings for interacting with FPGA resources. The OPAE Python API is built on top of the OPAE C++ Core API and its object model. Because of this, developing OPAE applications in Python is very similar to developing OPAE applications in C++ which significantly reduces the learning curve required to adapt to the Python API. While the object model remains the same, some static factory functions in the OPAE C++ Core API have been moved to module level methods in the OPAE Python API with the exception of the properties class. The goal of the OPAE Python API is to enable fast prototyping, test automation, infrastructure managment, and an easy to use framework for FPGA resource interactions that don’t rely on software algorithms with a high runtime complexity.

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Currently, the only Python package that is part of OPAE is opae.fpga

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Implementation

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The OPAE Python API is implemented by creating a Python extension using pybind11 <http://pybind11.readthedocs.io/en/stable>. This extension is created by using the pybind11 API which relies mostly on macros and compile time introspection to define the module initialization point as well as type converters between OPAE C++ Core types and OPAE Python types.

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Benefits

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The major benefits of using pybind11 for developing the OPAE Python API include, but are not limited to, the following features of pybind11:

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  • Uses C++ 11 standard library although it can use C++ 14 or C++17.
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  • Interoperable with the Python C API
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Runtime Requirements

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Because opae.fpga is built on top of the opae-cxx-core API, it does require that the runtime libraries for both opae-cxx-core and opae-c be installed on the system (as well as any other libraries they depend on). Those libraries can be installed using the opae-libs package (from either RPM or DEB format - depending on your Linux distribution).

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Installation

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Python Wheels

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The preferred method of installation is to use a binary wheel package for your version of Python.

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The following table lists example names for different Python versions and platforms.

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| Python Version | Python ABI | Linux Platform | Package Name | |—————-|—————–|—————-|————–| | 2.7 | CPython w/ UCS4 | x86_64 | opae.fpga.-cp27-cp27mu-linux_x86_64.whl | | 3.4 | CPython w/ UCS4 | x86_64 | opae.fpga.-cp34-cp34mu-linux_x86_64.whl | | 3.6 | CPython w/ UCS4 | x86_64 | opae.fpga.-cp36-cp36mu-linux_x86_64.whl |

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opae.fpga is currently not available in the Python Package Index but once it does become available, one should be able to install using pip by simply typing the following:

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> pip install --user opae.fpga
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Installing From Source

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In addition to the runtime libraries mentioned above, installing from source does require that the OPAE header files be installed as well as those header files for pybind11. The former can be installed with the opae-devel package and the latter can be installed by installing pybind11 Python module.

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Example Installation

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The following example shows how to build from source by installing the prerequisites before running the setup.py file.

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>sudo yum install opae-libs-<release>.x86_64.rpm
->sudo yum install opae-devel-<release>.x86_64.rpm
->pip install --user pybind11
->pip install --user opae.fpga-<release>.tar.gz
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NOTE: The pip examples above use the --user flag to avoid requiring root permissions. Those packages will be installed in the user’s site-packages directory found in the user’s .local directory.

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Example Scripts

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The following example is an implementation of the sample, hello_fpga.c, which is designed to configure the NLB0 diagnostic accelerator for a simple loopback.

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import time
-from opae import fpga
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-NLB0 = "d8424dc4-a4a3-c413-f89e-433683f9040b"
-CTL = 0x138
-CFG = 0x140
-NUM_LINES = 0x130
-SRC_ADDR = 0x0120
-DST_ADDR = 0x0128
-DSM_ADDR = 0x0110
-DSM_STATUS = 0x40
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-def cl_align(addr):
-    return addr >> 6
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-tokens = fpga.enumerate(type=fpga.ACCELERATOR, guid=NLB0)
-assert tokens, "Could not enumerate accelerator: {}".format(NlB0)
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-with fpga.open(tokens[0], fpga.OPEN_SHARED) as handle:
-    src = fpga.allocate_shared_buffer(handle, 4096)
-    dst = fpga.allocate_shared_buffer(handle, 4096)
-    dsm = fpga.allocate_shared_buffer(handle, 4096)
-    handle.write_csr32(CTL, 0)
-    handle.write_csr32(CTL, 1)
-    handle.write_csr64(DSM_ADDR, dsm.io_address())
-    handle.write_csr64(SRC_ADDR, cl_align(src.io_address())) # cacheline-aligned
-    handle.write_csr64(DST_ADDR, cl_align(dst.io_address())) # cacheline-aligned
-    handle.write_csr32(CFG, 0x42000)
-    handle.write_csr32(NUM_LINES, 4096/64)
-    handle.write_csr32(CTL, 3)
-    while dsm[DSM_STATUS] & 0x1 == 0:
-        time.sleep(0.001)
-    handle.write_csr32(CTL, 7)
-
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This example shows how one might reprogram (Partial Reconfiguration) an accelerator on a given bus, 0x5e, using a bitstream file, m0.gbs.

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from opae import fpga
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-BUS = 0x5e
-GBS = 'm0.gbs'
-tokens = fpga.enumerate(type=fpga.DEVICE, bus=BUS)
-assert tokens, "Could not enumerate device on bus: {}".format(BUS)
-with open(GBS, 'rb') as fd, fpga.open(tokens[0]) as device:
-    device.reconfigure(0, fd)
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- - - - - - - - - \ No newline at end of file diff --git a/sw/samples/hello_events/CMakeLists.txt b/sw/samples/hello_events/CMakeLists.txt deleted file mode 100644 index fdee8994c..000000000 --- a/sw/samples/hello_events/CMakeLists.txt +++ /dev/null @@ -1,46 +0,0 @@ -## Copyright(c) 2014-2023, Intel Corporation -## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions are met: -## -## * Redistributions of source code must retain the above copyright notice, -## this list of conditions and the following disclaimer. -## * Redistributions in binary form must reproduce the above copyright notice, -## this list of conditions and the following disclaimer in the documentation -## and/or other materials provided with the distribution. -## * Neither the name of Intel Corporation nor the names of its contributors -## may be used to endorse or promote products derived from this software -## without specific prior written permission. -## -## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -## POSSIBILITY OF SUCH DAMAGE. - -opae_add_executable(TARGET hello_events - SOURCE - hello_events.c - ${opae-test_ROOT}/framework/mock/opae_std.c - LIBS - argsfilter - opae-c - ${json-c_LIBRARIES} - ${uuid_LIBRARIES} - COMPONENT samplebin -) - -target_include_directories(hello_events - PRIVATE - ${OPAE_LIB_SOURCE}/argsfilter -) - -install(FILES hello_events.c - DESTINATION src/opae/samples/hello_events - COMPONENT samplesrc) diff --git a/sw/samples/hello_events/hello_events.c b/sw/samples/hello_events/hello_events.c deleted file mode 100644 index e8b0cf29c..000000000 --- a/sw/samples/hello_events/hello_events.c +++ /dev/null @@ -1,345 +0,0 @@ -// Copyright(c) 2017-2021, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file hello_events.c - * @brief A code sample of using OPAE event API. - * - * This sample starts two processes. One process injects an artificial fatal - * error to sysfs; while the other tries to asynchronously capture and handle - * the event. This - * sample code exercises all major functions of the event API, including - * creating and destroying event handles, register and unregister events, - * polling on event file descriptor, and getting the OS object associated with - * an event. For a full discussion of OPAE event API, refer to event.h. - * - */ - -#ifdef HAVE_CONFIG_H -#include -#endif // HAVE_CONFIG_H -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "mock/opae_std.h" - -int usleep(unsigned); - -#define FME_SYSFS_INJECT_ERROR "errors/inject_errors" - -#define ON_ERR_GOTO(res, label, desc) \ - do { \ - if ((res) != FPGA_OK) { \ - print_err((desc), (res)); \ - goto label; \ - } \ - } while (0) - -void print_err(const char *s, fpga_result res) -{ - fprintf(stderr, "Error %s: %s\n", s, fpgaErrStr(res)); -} - -// RAS Error Inject CSR -struct ras_inject_error { - union { - uint64_t csr; - struct { - /* Catastrophic error */ - uint64_t catastrophicr_error : 1; - /* Fatal error */ - uint64_t fatal_error : 1; - /* Non-fatal error */ - uint64_t nonfatal_error : 1; - /* Reserved */ - uint64_t rsvd : 61; - }; - }; -}; - -fpga_result inject_ras_fatal_error(fpga_token fme_token, uint8_t err) -{ - fpga_result res1 = FPGA_OK; - fpga_result res2 = FPGA_OK; - fpga_handle fme_handle = NULL; - struct ras_inject_error inj_error = { {0} }; - fpga_object inj_err_object; - - res1 = fpgaOpen(fme_token, &fme_handle, FPGA_OPEN_SHARED); - if (res1 != FPGA_OK) { - OPAE_ERR("Failed to open FPGA"); - return res1; - } - - res1 = fpgaHandleGetObject(fme_handle, FME_SYSFS_INJECT_ERROR, &inj_err_object, 0); - ON_ERR_GOTO(res1, out_close, "Failed to get Handle Object"); - - // Inject fatal error - inj_error.fatal_error = err; - - res1 = fpgaObjectWrite64(inj_err_object, inj_error.csr, 0); - ON_ERR_GOTO(res1, out_destroy_obj, "Failed to Read Object"); - -out_destroy_obj: - res2 = fpgaDestroyObject(&inj_err_object); - ON_ERR_GOTO(res2, out_close, "Failed to Destroy Object"); -out_close: - res2 = fpgaClose(fme_handle); - if (res2 != FPGA_OK) { - OPAE_ERR("Failed to close FPGA"); - } - - return res1 != FPGA_OK ? res1 : res2; -} - -void *error_thread(void *arg) -{ - fpga_token token = (fpga_token) arg; - fpga_result res; - - usleep(5000000); - printf("injecting error\n"); - res = inject_ras_fatal_error(token, 1); - if (res != FPGA_OK) - print_err("setting inject error register", res); - - usleep(5000000); - printf("clearing error\n"); - res = inject_ras_fatal_error(token, 0); - if (res != FPGA_OK) - print_err("clearing inject error register", res); - - return NULL; -} - -void help(void) -{ - printf("\n" - "hello_events\n" - "OPAE Events API sample\n" - "\n" - "Usage:\n" - " hello_events [-hv] [-S ] [-B ] [-D ] [-F ] [PCI_ADDR]\n" - "\n" - " -h,--help Print this help\n" - " -v,--version Print version info and exit\n" - "\n"); -} - -/* - * Parse command line arguments - */ -#define GETOPT_STRING "hv" -fpga_result parse_args(int argc, char *argv[]) -{ - struct option longopts[] = { - { "help", no_argument, NULL, 'h' }, - { "version", no_argument, NULL, 'v' }, - { NULL, 0, NULL, 0 } - }; - - int getopt_ret; - int option_index; - - while (-1 != (getopt_ret = getopt_long(argc, argv, GETOPT_STRING, longopts, &option_index))) { - const char *tmp_optarg = optarg; - /* checks to see if optarg is null and if not goes to value of optarg */ - if ((optarg) && ('=' == *tmp_optarg)) { - ++tmp_optarg; - } - - switch (getopt_ret) { - case 'h': /* help */ - help(); - return -1; - - case 'v': /* version */ - printf("hello_events %s %s%s\n", - OPAE_VERSION, - OPAE_GIT_COMMIT_HASH, - OPAE_GIT_SRC_TREE_DIRTY ? "*":""); - return -1; - - default: /* invalid option */ - fprintf(stderr, "Invalid cmdline options\n"); - return FPGA_EXCEPTION; - } - } - - return FPGA_OK; -} - -fpga_result find_fpga(fpga_properties device_filter, - fpga_token *fpga, - uint32_t *num_matches) -{ - fpga_properties filter = NULL; - fpga_result res = FPGA_OK; - fpga_result dres = FPGA_OK; - - res = fpgaCloneProperties(device_filter, &filter); - ON_ERR_GOTO(res, out, "cloning properties object"); - - res = fpgaPropertiesSetObjectType(filter, FPGA_DEVICE); - ON_ERR_GOTO(res, out_destroy, "setting interface ID"); - - res = fpgaEnumerate(&filter, 1, fpga, 1, num_matches); - ON_ERR_GOTO(res, out_destroy, "enumerating FPGAs"); - -out_destroy: - dres = fpgaDestroyProperties(&filter); - ON_ERR_GOTO(dres, out, "destroying properties object"); -out: - return (res == FPGA_OK) ? dres : res; -} - -int main(int argc, char *argv[]) -{ - fpga_token fpga_device_token = NULL; - fpga_handle fpga_device_handle = NULL; - uint32_t num_matches = 1; - fpga_result res1 = FPGA_OK; - fpga_result res2 = FPGA_OK; - fpga_event_handle eh; - uint64_t count = 0; - int res; - struct pollfd pfd; - int timeout = 10000; - int poll_ret = 0; - ssize_t bytes_read = 0; - pthread_t errthr; - fpga_properties device_filter = NULL; - - res1 = fpgaGetProperties(NULL, &device_filter); - if (res1) { - print_err("failed to alloc properties", res1); - return res1; - } - - if (opae_set_properties_from_args(device_filter, - &res1, - &argc, - argv)) { - print_err("failed arg parse", res1); - res1 = FPGA_EXCEPTION; - goto out_exit; - } else if (res1) { - print_err("failed to set properties", res1); - goto out_exit; - } - - res1 = parse_args(argc, argv); - if ((int)res1 < 0) - goto out_exit; - ON_ERR_GOTO(res1, out_exit, "parsing arguments"); - - res1 = find_fpga(device_filter, &fpga_device_token, &num_matches); - ON_ERR_GOTO(res1, out_exit, "finding FPGA accelerator"); - - if (num_matches < 1) { - fprintf(stderr, "No matches for address provided.\n"); - res1 = FPGA_NOT_FOUND; - goto out_exit; - } - - if (num_matches > 1) { - fprintf(stderr, "Found more than one suitable slot.\n"); - } - - res1 = fpgaOpen(fpga_device_token, &fpga_device_handle, FPGA_OPEN_SHARED); - ON_ERR_GOTO(res1, out_destroy_tok, "opening accelerator"); - - res1 = fpgaCreateEventHandle(&eh); - ON_ERR_GOTO(res1, out_close, "creating event handle"); - - res1 = fpgaRegisterEvent(fpga_device_handle, FPGA_EVENT_ERROR, eh, 0); - ON_ERR_GOTO(res1, out_destroy_eh, "registering an FME event"); - - printf("Waiting for interrupts now...\n"); - - res = pthread_create(&errthr, NULL, error_thread, fpga_device_token); - if (res) { - printf("Failed to create error_thread.\n"); - res1 = FPGA_EXCEPTION; - goto out_destroy_eh; - } - - - res1 = fpgaGetOSObjectFromEventHandle(eh, &pfd.fd); - ON_ERR_GOTO(res1, out_join, "getting file descriptor"); - - pfd.events = POLLIN; - poll_ret = poll(&pfd, 1, timeout); - - if (poll_ret < 0) { - printf("Poll error errno = %s\n", strerror(errno)); - res1 = FPGA_EXCEPTION; - goto out_join; - } else if (poll_ret == 0) { - printf("Poll timeout occurred\n"); - res1 = FPGA_EXCEPTION; - goto out_join; - } else { - printf("FME Interrupt occurred\n"); - bytes_read = opae_read(pfd.fd, &count, sizeof(count)); - if (bytes_read <= 0) - printf("WARNING: error reading from poll fd: %s\n", - bytes_read < 0 ? strerror(errno) : "zero bytes read"); - } - - res1 = fpgaUnregisterEvent(fpga_device_handle, FPGA_EVENT_ERROR, eh); - ON_ERR_GOTO(res1, out_join, "unregistering an FME event"); - - printf("Successfully tested Register/Unregister for FME events!\n"); - -out_join: - pthread_join(errthr, NULL); - -out_destroy_eh: - res2 = fpgaDestroyEventHandle(&eh); - ON_ERR_GOTO(res2, out_close, "deleting event handle"); - -out_close: - res2 = fpgaClose(fpga_device_handle); - ON_ERR_GOTO(res2, out_destroy_tok, "closing accelerator"); - -out_destroy_tok: - res2 = fpgaDestroyToken(&fpga_device_token); - ON_ERR_GOTO(res2, out_exit, "destroying token"); - -out_exit: - fpgaDestroyProperties(&device_filter); - return res1 != FPGA_OK ? res1 : res2; -} diff --git a/sw/samples/hello_fpga/CMakeLists.txt b/sw/samples/hello_fpga/CMakeLists.txt deleted file mode 100644 index bfc985d17..000000000 --- a/sw/samples/hello_fpga/CMakeLists.txt +++ /dev/null @@ -1,46 +0,0 @@ -## Copyright(c) 2014-2023, Intel Corporation -## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions are met: -## -## * Redistributions of source code must retain the above copyright notice, -## this list of conditions and the following disclaimer. -## * Redistributions in binary form must reproduce the above copyright notice, -## this list of conditions and the following disclaimer in the documentation -## and/or other materials provided with the distribution. -## * Neither the name of Intel Corporation nor the names of its contributors -## may be used to endorse or promote products derived from this software -## without specific prior written permission. -## -## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -## POSSIBILITY OF SUCH DAMAGE. - -opae_add_executable(TARGET hello_fpga - SOURCE - hello_fpga.c - ${opae-test_ROOT}/framework/mock/opae_std.c - LIBS - argsfilter - opae-c - ${json-c_LIBRARIES} - ${uuid_LIBRARIES} - COMPONENT samplebin -) - -target_include_directories(hello_fpga - PRIVATE - ${OPAE_LIB_SOURCE}/argsfilter -) - -install(FILES hello_fpga.c - DESTINATION src/opae/samples/hello_fpga - COMPONENT samplesrc) diff --git a/sw/samples/hello_fpga/hello_fpga.c b/sw/samples/hello_fpga/hello_fpga.c deleted file mode 100644 index d017eca23..000000000 --- a/sw/samples/hello_fpga/hello_fpga.c +++ /dev/null @@ -1,544 +0,0 @@ -// Copyright(c) 2017-2022, Intel Corporation -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// * Neither the name of Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -/** - * @file hello_fpga.c - * @brief A code sample illustrates the basic usage of the OPAE C API. - * - * The sample is a host application that demonstrates the basic steps of - * interacting with FPGA using the OPAE library. These steps include: - * - * - FPGA enumeration - * - Resource acquiring and releasing - * - Managing shared memory buffer - * - MMIO read and write - * - * The sample also demonstrates OPAE's object model, such as tokens, handles, - * and properties. - * - * The sample requires a native loopback mode (NLB) test image to be loaded on - * the FPGA. Refer to - * Quick - * Start Guide for full instructions on building, configuring, and running - * this code sample. - * - */ - -#ifdef HAVE_CONFIG_H -#include -#endif // HAVE_CONFIG_H -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "mock/opae_std.h" - -int usleep(unsigned); - -#ifndef TEST_TIMEOUT -#define TEST_TIMEOUT 30000 -#endif // TEST_TIMEOUT - -#ifndef CL -# define CL(x) ((x) * 64) -#endif // CL -#ifndef LOG2_CL -# define LOG2_CL 6 -#endif // LOG2_CL -#ifndef MB -# define MB(x) ((x) * 1024 * 1024) -#endif // MB - -#define CACHELINE_ALIGNED_ADDR(p) ((p) >> LOG2_CL) - -#define LPBK1_BUFFER_SIZE MB(1) -#define LPBK1_BUFFER_ALLOCATION_SIZE MB(2) -#define LPBK1_DSM_SIZE MB(2) -#define CSR_SRC_ADDR 0x0120 -#define CSR_DST_ADDR 0x0128 -#define CSR_CTL 0x0138 -#define CSR_STATUS1 0x0168 -#define CSR_CFG 0x0140 -#define CSR_NUM_LINES 0x0130 -#define DSM_STATUS_TEST_COMPLETE 0x40 -#define CSR_AFU_DSM_BASEL 0x0110 - -/* NLB0 AFU_ID */ -#define NLB0_AFUID "D8424DC4-A4A3-C413-F89E-433683F9040B" - -/* NLB0 AFU_ID for N3000 */ -#define N3000_AFUID "9AEFFE5F-8457-0612-C000-C9660D824272" -#define FPGA_NLB0_UUID_H 0xd8424dc4a4a3c413 -#define FPGA_NLB0_UUID_L 0xf89e433683f9040b - - -/* - * macro to check return codes, print error message, and goto cleanup label - * NOTE: this changes the program flow (uses goto)! - */ -#define ON_ERR_GOTO(res, label, desc) \ - do { \ - if ((res) != FPGA_OK) { \ - print_err((desc), (res)); \ - goto label; \ - } \ - } while (0) - -/* Type definitions */ -typedef struct { - uint32_t uint[16]; -} cache_line; - -void print_err(const char *s, fpga_result res) -{ - fprintf(stderr, "Error %s: %s\n", s, fpgaErrStr(res)); -} - -/* - * Global configuration of bus, set during parse_args() - * */ -struct config { - int open_flags; - int run_n3000; -} - -config = { - .open_flags = 0, - .run_n3000 = 0 -}; - -void help(void) -{ - printf("\n" - "hello_fpga\n" - "OPAE Native Loopback 0 (NLB0) sample\n" - "\n" - "Usage:\n" - " hello_fpga [-schv] [-S ] [-B ] [-D ] [-F ] [PCI_ADDR]\n" - "\n" - " -s,--shared Open accelerator in shared mode\n" - " -c,--n3000 Assume N3000 MMIO layout\n" - " -h,--help Print this help\n" - " -v,--version Print version info and exit\n" - "\n"); -} - -#define GETOPT_STRING "hscv" -fpga_result parse_args(int argc, char *argv[]) -{ - struct option longopts[] = { - { "help", no_argument, NULL, 'h' }, - { "shared", no_argument, NULL, 's' }, - { "n3000", no_argument, NULL, 'c' }, - { "version", no_argument, NULL, 'v' }, - { NULL, 0, NULL, 0 } - }; - - int getopt_ret; - int option_index; - - char version[32]; - char build[32]; - - while (-1 != (getopt_ret = getopt_long(argc, argv, GETOPT_STRING, - longopts, &option_index))) { - const char *tmp_optarg = optarg; - /* Checks to see if optarg is null and if not it goes to value of optarg */ - if ((optarg) && ('=' == *tmp_optarg)) { - ++tmp_optarg; - } - - switch (getopt_ret) { - case 'h': - help(); - return -1; - case 's': - config.open_flags |= FPGA_OPEN_SHARED; - break; - case 'c': - config.run_n3000 = 1; - break; - case 'v': - fpgaGetOPAECVersionString(version, sizeof(version)); - fpgaGetOPAECBuildString(build, sizeof(build)); - printf("hello_fpga %s %s\n", - version, build); - return -1; - - default: /* invalid option */ - fprintf(stderr, "Invalid cmdline option \n"); - return FPGA_EXCEPTION; - } - } - - return FPGA_OK; -} - -fpga_result find_fpga(fpga_properties device_filter, - fpga_guid afu_guid, - fpga_token *accelerator_token, - uint32_t *num_matches_accelerators) -{ - fpga_properties filter = NULL; - fpga_result res1; - fpga_result res2 = FPGA_OK; - - res1 = fpgaCloneProperties(device_filter, &filter); - ON_ERR_GOTO(res1, out, "cloning properties object"); - - res1 = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); - ON_ERR_GOTO(res1, out_destroy, "setting object type"); - - res1 = fpgaPropertiesSetGUID(filter, afu_guid); - ON_ERR_GOTO(res1, out_destroy, "setting GUID"); - - res1 = fpgaEnumerate(&filter, 1, accelerator_token, 1, num_matches_accelerators); - ON_ERR_GOTO(res1, out_destroy, "enumerating accelerators"); - -out_destroy: - res2 = fpgaDestroyProperties(&filter); - ON_ERR_GOTO(res2, out, "destroying properties object"); -out: - return res1 != FPGA_OK ? res1 : res2; -} - -/* Is the FPGA simulated with ASE? */ -bool probe_for_ase(void) -{ - fpga_result r = FPGA_OK; - uint16_t device_id = 0; - fpga_properties filter = NULL; - uint32_t num_matches = 1; - fpga_token fme_token; - - /* Connect to the FPGA management engine */ - fpgaGetProperties(NULL, &filter); - fpgaPropertiesSetObjectType(filter, FPGA_DEVICE); - - /* Connecting to one is sufficient to find ASE */ - fpgaEnumerate(&filter, 1, &fme_token, 1, &num_matches); - if (0 != num_matches) { - /* Retrieve the device ID of the FME */ - fpgaDestroyProperties(&filter); - fpgaGetProperties(fme_token, &filter); - r = fpgaPropertiesGetDeviceID(filter, &device_id); - fpgaDestroyToken(&fme_token); - } - fpgaDestroyProperties(&filter); - - /* ASE's device ID is 0xa5e */ - return ((FPGA_OK == r) && (0xa5e == device_id)); -} - -fpga_result find_nlb_n3000(fpga_handle accelerator_handle, - uint64_t *afu_baddr) -{ - - fpga_result res1 = FPGA_OK; - int end_of_list = 0; - int nlb0_found = 0; - uint64_t header = 0; - uint64_t uuid_hi = 0; - uint64_t uuid_lo = 0; - uint64_t next_offset = 0; - uint64_t nlb0_offset = 0; - - /* find NLB0 in AFU */ - do { - // Read the next feature header - res1 = fpgaReadMMIO64(accelerator_handle, 0, nlb0_offset, &header); - ON_ERR_GOTO(res1, out_exit, "fpgaReadMMIO64"); - res1 = fpgaReadMMIO64(accelerator_handle, 0, nlb0_offset+8, &uuid_lo); - ON_ERR_GOTO(res1, out_exit, "fpgaReadMMIO64"); - res1 = fpgaReadMMIO64(accelerator_handle, 0, nlb0_offset+16, &uuid_hi); - ON_ERR_GOTO(res1, out_exit, "fpgaReadMMIO64"); - // printf("%zx: %zx %zx %zx\n", nlb0_offset, header, uuid_lo, uuid_hi); - if ((((header >> 60) & 0xf) == 0x1) && - (uuid_lo == FPGA_NLB0_UUID_L) && (uuid_hi == FPGA_NLB0_UUID_H)) { - nlb0_found = 1; - break; - } - // End of the list flag - end_of_list = (header >> 40) & 1; - // Move to the next feature header - next_offset = (header >> 16) & 0xffffff; - if ((next_offset == 0xffff) || (next_offset == 0)) { - nlb0_found = 0; - break; - } - nlb0_offset = nlb0_offset + next_offset; - } while (!end_of_list); - - if (!nlb0_found) { - printf("AFU NLB0 not found\n"); - return FPGA_EXCEPTION; - } - - printf("AFU NLB0 found @ %zx\n", nlb0_offset); - *afu_baddr = nlb0_offset; - return FPGA_OK; - -out_exit: - return FPGA_EXCEPTION; -} - -int main(int argc, char *argv[]) -{ - fpga_token accelerator_token; - fpga_handle accelerator_handle; - fpga_guid guid; - uint32_t num_matches_accelerators = 0; - uint32_t use_ase; - - volatile uint64_t *dsm_ptr = NULL; - volatile uint64_t *status_ptr = NULL; - volatile uint64_t *input_ptr = NULL; - volatile uint64_t *output_ptr = NULL; - - uint64_t dsm_wsid; - uint64_t input_wsid; - uint64_t output_wsid; - uint32_t i; - uint32_t timeout; - fpga_result res1 = FPGA_OK; - fpga_result res2 = FPGA_OK; - fpga_properties device_filter = NULL; - - res1 = fpgaGetProperties(NULL, &device_filter); - if (res1 != FPGA_OK) { - print_err("failed to allocate properties.\n", res1); - return 1; - } - - if (opae_set_properties_from_args(device_filter, - &res1, - &argc, - argv)) { - print_err("failed arg parse.\n", res1); - res1 = FPGA_EXCEPTION; - goto out_exit; - } else if (res1) { - print_err("failed to set properties.\n", res1); - goto out_exit; - } - - res1 = parse_args(argc, argv); - if ((int)res1 < 0) - goto out_exit; - ON_ERR_GOTO(res1, out_exit, "parsing arguments"); - - if (config.run_n3000) { - if (uuid_parse(N3000_AFUID, guid) < 0) - res1 = FPGA_EXCEPTION; - } else { - if (uuid_parse(NLB0_AFUID, guid) < 0) - res1 = FPGA_EXCEPTION; - } - - ON_ERR_GOTO(res1, out_exit, "parsing guid"); - - use_ase = probe_for_ase(); - if (use_ase) { - printf("Running in ASE mode\n"); - } - - /* Look for accelerator with NLB0_AFUID */ - res1 = find_fpga(device_filter, - guid, - &accelerator_token, - &num_matches_accelerators); - ON_ERR_GOTO(res1, out_exit, "finding FPGA accelerator"); - - if (num_matches_accelerators == 0) { - res1 = FPGA_NOT_FOUND; - } - ON_ERR_GOTO(res1, out_exit, "no matching accelerator"); - - if (num_matches_accelerators > 1) { - printf("Found more than one suitable accelerator. "); - } - - - /* Open accelerator and map MMIO */ - res1 = fpgaOpen(accelerator_token, &accelerator_handle, config.open_flags); - ON_ERR_GOTO(res1, out_destroy_tok, "opening accelerator"); - - res1 = fpgaMapMMIO(accelerator_handle, 0, NULL); - ON_ERR_GOTO(res1, out_close, "mapping MMIO space"); - - - /* Allocate buffers */ - res1 = fpgaPrepareBuffer(accelerator_handle, LPBK1_DSM_SIZE, - (void **)&dsm_ptr, &dsm_wsid, 0); - ON_ERR_GOTO(res1, out_close, "allocating DSM buffer"); - - res1 = fpgaPrepareBuffer(accelerator_handle, LPBK1_BUFFER_ALLOCATION_SIZE, - (void **)&input_ptr, &input_wsid, 0); - ON_ERR_GOTO(res1, out_free_dsm, "allocating input buffer"); - - res1 = fpgaPrepareBuffer(accelerator_handle, LPBK1_BUFFER_ALLOCATION_SIZE, - (void **)&output_ptr, &output_wsid, 0); - ON_ERR_GOTO(res1, out_free_input, "allocating output buffer"); - - printf("Running Test\n"); - - /* Initialize buffers */ - memset((void *)dsm_ptr, 0, LPBK1_DSM_SIZE); - memset((void *)input_ptr, 0xAF, LPBK1_BUFFER_SIZE); - memset((void *)output_ptr, 0xBE, LPBK1_BUFFER_SIZE); - - cache_line *cl_ptr = (cache_line *)input_ptr; - for (i = 0; i < LPBK1_BUFFER_SIZE / CL(1); ++i) { - cl_ptr[i].uint[15] = i+1; /* set the last uint in every cacheline */ - } - - - /* Reset accelerator */ - res1 = fpgaReset(accelerator_handle); - ON_ERR_GOTO(res1, out_free_output, "resetting accelerator"); - - uint64_t nlb_base_addr = 0; - - if (config.run_n3000) { - res1 = find_nlb_n3000(accelerator_handle, &nlb_base_addr); - ON_ERR_GOTO(res1, out_free_output, "finding nlb in AFU"); - } - - /* Program DMA addresses */ - uint64_t iova = 0; - res1 = fpgaGetIOAddress(accelerator_handle, dsm_wsid, &iova); - ON_ERR_GOTO(res1, out_free_output, "getting DSM IOVA"); - - res1 = fpgaWriteMMIO64(accelerator_handle, 0, nlb_base_addr + CSR_AFU_DSM_BASEL, iova); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_AFU_DSM_BASEL"); - - res1 = fpgaWriteMMIO32(accelerator_handle, 0, nlb_base_addr + CSR_CTL, 0); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_CFG"); - res1 = fpgaWriteMMIO32(accelerator_handle, 0, nlb_base_addr + CSR_CTL, 1); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_CFG"); - - res1 = fpgaGetIOAddress(accelerator_handle, input_wsid, &iova); - ON_ERR_GOTO(res1, out_free_output, "getting input IOVA"); - res1 = fpgaWriteMMIO64(accelerator_handle, 0, nlb_base_addr + CSR_SRC_ADDR, CACHELINE_ALIGNED_ADDR(iova)); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_SRC_ADDR"); - - res1 = fpgaGetIOAddress(accelerator_handle, output_wsid, &iova); - ON_ERR_GOTO(res1, out_free_output, "getting output IOVA"); - res1 = fpgaWriteMMIO64(accelerator_handle, 0, nlb_base_addr + CSR_DST_ADDR, CACHELINE_ALIGNED_ADDR(iova)); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_DST_ADDR"); - - res1 = fpgaWriteMMIO32(accelerator_handle, 0, nlb_base_addr + CSR_NUM_LINES, LPBK1_BUFFER_SIZE / CL(1)); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_NUM_LINES"); - res1 = fpgaWriteMMIO32(accelerator_handle, 0, nlb_base_addr + CSR_CFG, 0x42000); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_CFG"); - - status_ptr = dsm_ptr + DSM_STATUS_TEST_COMPLETE/sizeof(uint64_t); - - - /* Start the test */ - res1 = fpgaWriteMMIO32(accelerator_handle, 0, nlb_base_addr + CSR_CTL, 3); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_CFG"); - - /* Wait for test completion */ - timeout = TEST_TIMEOUT; - while (0 == ((*status_ptr) & 0x1)) { - usleep(100); - if (!use_ase && (--timeout == 0)) { - res1 = FPGA_EXCEPTION; - ON_ERR_GOTO(res1, out_free_output, "test timed out"); - } - } - - /* Stop the device */ - res1 = fpgaWriteMMIO32(accelerator_handle, 0, nlb_base_addr + CSR_CTL, 7); - ON_ERR_GOTO(res1, out_free_output, "writing CSR_CFG"); - - /* Wait for the AFU's read/write traffic to complete */ - uint32_t afu_traffic_trips = 0; - while (afu_traffic_trips < 100) { - /* - * CSR_STATUS1 holds two 32 bit values: num pending reads and writes. - * Wait for it to be 0. - */ - uint64_t s1; - res1 = fpgaReadMMIO64(accelerator_handle, 0, nlb_base_addr + CSR_STATUS1, &s1); - ON_ERR_GOTO(res1, out_free_output, "reading CSR_STATUS1"); - if (s1 == 0) { - break; - } - - afu_traffic_trips += 1; - usleep(1000); - } - - /* Check output buffer contents */ - for (i = 0; i < LPBK1_BUFFER_SIZE; i++) { - if (((uint8_t *)output_ptr)[i] != ((uint8_t *)input_ptr)[i]) { - fprintf(stderr, "Output does NOT match input " - "at offset %i!\n", i); - break; - } - } - - printf("Done Running Test\n"); - - - /* Release buffers */ -out_free_output: - res2 = fpgaReleaseBuffer(accelerator_handle, output_wsid); - ON_ERR_GOTO(res2, out_free_input, "releasing output buffer"); -out_free_input: - res2 = fpgaReleaseBuffer(accelerator_handle, input_wsid); - ON_ERR_GOTO(res2, out_free_dsm, "releasing input buffer"); -out_free_dsm: - res2 = fpgaReleaseBuffer(accelerator_handle, dsm_wsid); - ON_ERR_GOTO(res2, out_unmap, "releasing DSM buffer"); - - /* Unmap MMIO space */ -out_unmap: - res2 = fpgaUnmapMMIO(accelerator_handle, 0); - ON_ERR_GOTO(res2, out_close, "unmapping MMIO space"); - - /* Release accelerator */ -out_close: - res2 = fpgaClose(accelerator_handle); - ON_ERR_GOTO(res2, out_destroy_tok, "closing accelerator"); - - /* Destroy token */ -out_destroy_tok: - res2 = fpgaDestroyToken(&accelerator_token); - ON_ERR_GOTO(res2, out_exit, "destroying token"); - -out_exit: - fpgaDestroyProperties(&device_filter); - return res1 != FPGA_OK ? res1 : res2; -} diff --git a/sw/tod/tod/index.html b/sw/tod/tod/index.html deleted file mode 100644 index f400b6ba9..000000000 --- a/sw/tod/tod/index.html +++ /dev/null @@ -1,2012 +0,0 @@ - - - - - - - - - - - - - - - - - - Time of Day (ToD) # - OFS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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Time of Day (ToD)

-

SYNOPSIS

-

The Intel FPGA ToD driver in the kernel space exposes ToD IP as PHC (PTP Hardware Clock) device to the Linux PTP (Precision Time Protocol) stack to synchronize the system clock to its ToD information. -The phc2sys utility of Linux PTP stack is used to access ToD information and synchronize the system clock.

-

Install the Linux PTP utilities: -

# sudo yum install linuxptp
-

-

phc_ctl and phc2sys utilities (linuxptp package) are used to control the PHC device and synchronize the system clock to its ToD information.

-

phc_ctl: directly controls PHC device clock. -

Usage: phc_ctl [options] <device> -- [command]
-
-    device         ethernet or ptp clock device
-
-Options:
-    -l [num]       set the logging level to 'num'
-    -q             do not print messages to the syslog
-    -Q             do not print messages to stdout
-    -v             prints the software version and exits
-    -h             prints this message and exits
-
-Commands:
- specify commands with arguments. Can specify multiple commands to be executed in order. 
- Seconds are read as double precision floating point values.
-
-    set  [seconds]  set PHC time (defaults to time on CLOCK_REALTIME)
-    get             get PHC time
-    adj  <seconds>  adjust PHC time by offset
-    freq [ppb]      adjust PHC frequency (default returns current offset)
-    cmp             compare PHC offset to CLOCK_REALTIME
-    caps            display device capabilities (default if no command given)
-    wait <seconds>  pause between commands
-                    This command may be useful for sanity checking whether the PHC clock is
-                    running as expected.
-                    The arguments specified in seconds are read as double precision floating point
-                    values, and will scale to nanoseconds. This means providing a value of 5.5 means 5
-                    and one half seconds. This allows specifying fairly precise values for time.
-

-

phc2sys: synchronize two clocks. -

Usage: phc2sys [options]
-
-Automatic configuration:
-    -a             turn on autoconfiguration
-    -r             synchronize system (realtime) clock
-                   repeat -r to consider it also as a time source
-
-Manual configuration:
-    -c [dev|name]  slave clock (CLOCK_REALTIME)
-    -d [dev]       master PPS device
-    -s [dev|name]  master clock
-    -O [offset]    slave-master time offset (0)
-    -w             wait for ptp4l
-
-Options:
-    -f [file]      configuration file
-    -E [pi|linreg] clock servo (pi)
-    -P [kp]        proportional constant (0.7)
-    -I [ki]        integration constant (0.3)
-    -S [step]      step threshold (disabled)
-    -F [step]      step threshold only on start (0.00002)
-    -R [rate]      slave clock update rate in HZ (1.0)
-    -N [num]       number of master clock readings per update (5)
-    -L [limit]     sanity frequency limit in ppb (200000000)
-    -M [num]       NTP SHM segment number (0)
-    -u [num]       number of clock updates in summary stats (0)
-    -n [num]       domain number (0)
-    -x             apply leap seconds by servo instead of kernel
-    -z [path]      server address for UDS (/var/run/ptp4l)
-    -l [num]       set the logging level to 'num' (6)
-    -t [tag]       add tag to log messages
-    -m             print messages to stdout
-    -q             do not print messages to the syslog
-    -v             prints the software version and exits
-    -h             prints this message and exits
-

-

DESCRIPTION

-

The phc2sys utility is used to synchronize the system clock to the PTP Hardware Clock (PHC) or ToD clock. The phc_ctl utility is used to directly control PHC clock device.

-

Configuring the PTP service

-
    -
  1. Install the linuxptp package: -
    # sudo yum install linuxptp
-
    2. -
  2. Check PTP device is created successfully by the ToD driver.
    3. -
-

ToD driver registering as PHC device (clock_name: dfl_tod) to the Linux PTP stack and exposing to the Linux kernel to synchronize the system clock to its ToD information. -

# cat /sys/class/ptp/ptp0/clock_name
-dfl_tod
-

-
    -
  1. Configure phc2sys service on a system:
    2. -
-

The phc2sys service is configured in the /etc/sysconfig/phc2sys configuration file. Define start-up option for phc2sys daemon in /etc/sysconfig/phc2sys. -The master clock is /dev/ptp0 device and the slave clock is system clock/CLOCK_REALTIME: -

 OPTIONS="-s /dev/ptp0 -c CLOCK_REALTIME -r -O 0 -R 16"
-

-
    -
  1. -

    Start phc2sys service: -

    # service phc2sys start
-

    -
    2. -
  2. -

    Stop phc2sys service: -

    # service phc2sys stop
-

    -
    3. -
-

Examples

-

using phc_ctl utility

-

Read the current clock time from the PHC clock device: -

# sudo phc_ctl /dev/ptp0 get
-

-

Set the PHC clock time to CLOCK_REALTIME: -

# sudo phc_ctl /dev/ptp0 set
-

-

Set PHC clock time to 0: -

# sudo phc_ctl /dev/ptp0 set 0.0
-

-

Set PHC clock time to 0 and wait for 10 sec and read the clock time: -

# sudo phc_ctl /dev/ptp0 set 0.0 wait 10.0 get
-

-

Set and compare PHC clock time to CLOCK_REALTIME: -

# sudo phc_ctl /dev/ptp0 set cmp
-

-

Read the PHC device capabilities: -

# sudo phc_ctl /dev/ptp0 caps
-

-

using phc2sys utility

-

To synchronize the system clock to the PHC clock: -

# sudo phc2sys -s /dev/ptp0 -c CLOCK_REALTIME -r -O 0 -R 16 -m
-phc2sys[7896.789]: CLOCK_REALTIME phc offset  -1259509 s0 freq  -31462 delay   1338
-phc2sys[7896.852]: CLOCK_REALTIME phc offset  -1261498 s1 freq  -63144 delay   1328
-phc2sys[7896.914]: CLOCK_REALTIME phc offset       -15 s2 freq  -63159 delay   1328
-phc2sys[7896.977]: CLOCK_REALTIME phc offset       -19 s2 freq  -63167 delay   1327
-phc2sys[7897.039]: CLOCK_REALTIME phc offset       -35 s2 freq  -63189 delay   1328
-phc2sys[7897.102]: CLOCK_REALTIME phc offset       -37 s2 freq  -63201 delay   1331
-phc2sys[7897.165]: CLOCK_REALTIME phc offset       -30 s2 freq  -63205 delay   1328
-phc2sys[7897.227]: CLOCK_REALTIME phc offset       -50 s2 freq  -63234 delay   1331
-phc2sys[7897.290]: CLOCK_REALTIME phc offset       -50 s2 freq  -63249 delay   1329
-phc2sys[7897.353]: CLOCK_REALTIME phc offset       -62 s2 freq  -63276 delay   1334
-phc2sys[7897.415]: CLOCK_REALTIME phc offset       -53 s2 freq  -63286 delay   1335
-phc2sys[7897.478]: CLOCK_REALTIME phc offset       -46 s2 freq  -63295 delay   1325
-phc2sys[7897.541]: CLOCK_REALTIME phc offset       -57 s2 freq  -63320 delay   1334
-phc2sys[7897.603]: CLOCK_REALTIME phc offset       -39 s2 freq  -63319 delay   1327
-phc2sys[7897.666]: CLOCK_REALTIME phc offset       -31 s2 freq  -63323 delay   1328
-phc2sys[7897.728]: CLOCK_REALTIME phc offset       -48 s2 freq  -63349 delay   1327
-phc2sys[7897.791]: CLOCK_REALTIME phc offset       -42 s2 freq  -63357 delay   1323
-phc2sys[7897.854]: CLOCK_REALTIME phc offset       -41 s2 freq  -63369 delay   1324
-phc2sys[7897.916]: CLOCK_REALTIME phc offset       -44 s2 freq  -63384 delay   1328
-phc2sys[7897.979]: CLOCK_REALTIME phc offset       -13 s2 freq  -63366 delay   1327
-phc2sys[7898.042]: CLOCK_REALTIME phc offset       -16 s2 freq  -63373 delay   1327
-phc2sys[7898.104]: CLOCK_REALTIME phc offset       -19 s2 freq  -63381 delay   1328
-phc2sys[7898.167]: CLOCK_REALTIME phc offset       -16 s2 freq  -63384 delay   1327
-phc2sys[7898.229]: CLOCK_REALTIME phc offset         3 s2 freq  -63370 delay   1327
-phc2sys[7898.292]: CLOCK_REALTIME phc offset        16 s2 freq  -63356 delay   1325
-phc2sys[7898.355]: CLOCK_REALTIME phc offset        10 s2 freq  -63357 delay   1319
-phc2sys[7898.417]: CLOCK_REALTIME phc offset        23 s2 freq  -63341 delay   1327
-phc2sys[7898.480]: CLOCK_REALTIME phc offset        13 s2 freq  -63344 delay   1335
-phc2sys[7898.543]: CLOCK_REALTIME phc offset        23 s2 freq  -63330 delay   1323
-phc2sys[7898.605]: CLOCK_REALTIME phc offset        29 s2 freq  -63317 delay   1312
-phc2sys[7898.668]: CLOCK_REALTIME phc offset        22 s2 freq  -63315 delay   1324
-phc2sys[7898.730]: CLOCK_REALTIME phc offset        42 s2 freq  -63289 delay   1325
-phc2sys[7898.793]: CLOCK_REALTIME phc offset        29 s2 freq  -63289 delay   1333
-phc2sys[7898.856]: CLOCK_REALTIME phc offset        34 s2 freq  -63276 delay   1327
-phc2sys[7898.918]: CLOCK_REALTIME phc offset        21 s2 freq  -63278 delay   1331
-phc2sys[7898.981]: CLOCK_REALTIME phc offset        22 s2 freq  -63271 delay   1335
-phc2sys[7899.044]: CLOCK_REALTIME phc offset        30 s2 freq  -63256 delay   1327
-phc2sys[7899.106]: CLOCK_REALTIME phc offset        30 s2 freq  -63247 delay   1328
-phc2sys[7899.169]: CLOCK_REALTIME phc offset        37 s2 freq  -63231 delay   1333
-phc2sys[7899.232]: CLOCK_REALTIME phc offset        29 s2 freq  -63228 delay   1331
-phc2sys[7899.294]: CLOCK_REALTIME phc offset        24 s2 freq  -63225 delay   1330
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