diff --git a/core/arch/arm/tee/entry_fast.c b/core/arch/arm/tee/entry_fast.c
index 24ce3d79a6e..b8966b5ccc3 100644
--- a/core/arch/arm/tee/entry_fast.c
+++ b/core/arch/arm/tee/entry_fast.c
@@ -104,12 +104,14 @@ static void tee_entry_exchange_capabilities(struct thread_smc_args *args)
 	args->a0 = OPTEE_SMC_RETURN_OK;
 	args->a1 = OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM;
 
+#if !defined(CFG_DBG_DISABLE_DYN_SHM_CAP)
 	if (core_mmu_nsec_ddr_is_defined()) {
 		IMSG("NS DDR defined. Enabling dynamic SHM");
 		args->a1 |= OPTEE_SMC_SEC_CAP_DYNAMIC_SHM;
 	} else {
 		IMSG("No NS DDR defined for the platform. Disabling dynamic SHM");
 	}
+#endif
 }
 
 static void tee_entry_disable_shm_cache(struct thread_smc_args *args)
diff --git a/mk/config.mk b/mk/config.mk
index 881190afc39..e252d7f7626 100644
--- a/mk/config.mk
+++ b/mk/config.mk
@@ -263,3 +263,10 @@ CFG_SECURE_DATA_PATH ?= n
 # so its value represents log2(cores/cluster).
 # Default is 2**(2) = 4 cores per cluster.
 CFG_CORE_CLUSTER_SHIFT ?= 2
+
+# Do not report to NW that dynamic shared memory (shared memory outside
+# predefined region) is enabled.
+# Note that you can disable this feature for debug purposes. OP-TEE will not
+# report to Normal World that it support dynamic SHM. But, nevertheles it
+# will accept dynamic SHM buffers.
+CFG_DBG_DISABLE_DYN_SHM_CAP ?= n