plat-vexpress: fvp: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0xa00000000 for FVP. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
OP-TEE · Oct 12, 2017 · 3ff067c · 3ff067c
1 parent cbe4eae
commit 3ff067c
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diff --git a/core/arch/arm/plat-vexpress/conf.mk b/core/arch/arm/plat-vexpress/conf.mk
@@ -69,3 +69,8 @@ CFG_SE_API ?= y
 CFG_SE_API_SELF_TEST ?= y
 CFG_PCSC_PASSTHRU_READER_DRV ?= y
 endif
+
+ifeq ($(PLATFORM_FLAVOR),fvp)
+# DRAM1 is defined above 4G
+$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
+endif
diff --git a/core/arch/arm/plat-vexpress/main.c b/core/arch/arm/plat-vexpress/main.c
@@ -82,6 +82,9 @@ register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE);
 #endif
 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE);
+#ifdef DRAM1_BASE
+register_nsec_ddr(DRAM1_BASE, DRAM1_SIZE);
+#endif
 
 const struct thread_handlers *generic_boot_get_handlers(void)
 {

diff --git a/core/arch/arm/plat-vexpress/platform_config.h b/core/arch/arm/plat-vexpress/platform_config.h
@@ -112,6 +112,9 @@
 #define DRAM0_BASE		0x80000000
 #define DRAM0_SIZE		0x7f000000
 
+#define DRAM1_BASE		0x880000000UL
+#define DRAM1_SIZE		0x180000000UL
+
 #define TZCDRAM_BASE		0xff000000
 #define TZCDRAM_SIZE		0x01000000