From e621e4e553bf9b2cba6150efcc10d396270ba018 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Sat, 26 Aug 2017 12:52:27 +0800
Subject: [PATCH] core: imx: simplify code

Wrap memory registration using macros to make it easy to add new soc/arch
support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
---
 core/arch/arm/plat-imx/imx7.c | 10 ----------
 core/arch/arm/plat-imx/main.c | 37 +++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/core/arch/arm/plat-imx/imx7.c b/core/arch/arm/plat-imx/imx7.c
index 01620628c92..731d28546bf 100644
--- a/core/arch/arm/plat-imx/imx7.c
+++ b/core/arch/arm/plat-imx/imx7.c
@@ -47,16 +47,6 @@
 #include <tee/entry_fast.h>
 #include <util.h>
 
-register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, IOMUXC_BASE, CORE_MMU_DEVICE_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, CCM_BASE, CORE_MMU_DEVICE_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_DEVICE_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, GPC_BASE, CORE_MMU_DEVICE_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, DDRC_BASE, CORE_MMU_DEVICE_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, AIPS1_BASE, AIPS1_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, AIPS2_BASE, AIPS2_SIZE);
-register_phys_mem(MEM_AREA_IO_SEC, AIPS3_BASE, AIPS3_SIZE);
-
 void plat_cpu_reset_late(void)
 {
 	uintptr_t addr;
diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c
index ea43d4b3727..ff2e97ed3d8 100644
--- a/core/arch/arm/plat-imx/main.c
+++ b/core/arch/arm/plat-imx/main.c
@@ -62,9 +62,46 @@ static const struct thread_handlers handlers = {
 
 static struct imx_uart_data console_data;
 
+#ifdef CONSOLE_UART_BASE
 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE);
+#endif
+#ifdef GIC_BASE
 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
+#endif
+#ifdef ANATOP_BASE
 register_phys_mem(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_DEVICE_SIZE);
+#endif
+#ifdef GICD_BASE
+register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
+#endif
+#ifdef AIPS1_BASE
+register_phys_mem(MEM_AREA_IO_SEC, AIPS1_BASE,
+		  ROUNDUP(AIPS1_SIZE, CORE_MMU_DEVICE_SIZE));
+#endif
+#ifdef AIPS2_BASE
+register_phys_mem(MEM_AREA_IO_SEC, AIPS2_BASE,
+		  ROUNDUP(AIPS2_SIZE, CORE_MMU_DEVICE_SIZE));
+#endif
+#ifdef AIPS3_BASE
+register_phys_mem(MEM_AREA_IO_SEC, AIPS3_BASE,
+		  ROUNDUP(AIPS3_SIZE, CORE_MMU_DEVICE_SIZE));
+#endif
+#ifdef IRAM_BASE
+register_phys_mem(MEM_AREA_TEE_COHERENT,
+		  ROUNDDOWN(IRAM_BASE, CORE_MMU_DEVICE_SIZE),
+		  CORE_MMU_DEVICE_SIZE);
+#endif
+#ifdef IRAM_S_BASE
+register_phys_mem(MEM_AREA_TEE_COHERENT,
+		  ROUNDDOWN(IRAM_S_BASE, CORE_MMU_DEVICE_SIZE),
+		  CORE_MMU_DEVICE_SIZE);
+#endif
+
+#if defined(CFG_PL310)
+register_phys_mem(MEM_AREA_IO_SEC,
+		  ROUNDDOWN(PL310_BASE, CORE_MMU_DEVICE_SIZE),
+		  CORE_MMU_DEVICE_SIZE);
+#endif
 
 const struct thread_handlers *generic_boot_get_handlers(void)
 {