diff --git a/core/arch/arm/plat-imx/imx-common.c b/core/arch/arm/plat-imx/imx-common.c
index 3e584e84158..650ddd8119c 100644
--- a/core/arch/arm/plat-imx/imx-common.c
+++ b/core/arch/arm/plat-imx/imx-common.c
@@ -89,36 +89,6 @@ bool soc_is_imx6dqp(void)
 	return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 2);
 }
 
-bool soc_is_imx7s(void)
-{
-	vaddr_t addr = core_mmu_get_va(OCOTP_BASE + 0x450, MEM_AREA_IO_SEC);
-	uint32_t val = read32(addr);
-
-	if (soc_is_imx7ds()) {
-		if (val & 1)
-			return true;
-		else
-			return false;
-	}
-
-	return false;
-}
-
-bool soc_is_imx7d(void)
-{
-	vaddr_t addr = core_mmu_get_va(OCOTP_BASE + 0x450, MEM_AREA_IO_SEC);
-	uint32_t val = read32(addr);
-
-	if (soc_is_imx7ds()) {
-		if (val & 1)
-			return false;
-		else
-			return true;
-	}
-
-	return false;
-}
-
 bool soc_is_imx7ds(void)
 {
 	return imx_soc_type() == SOC_MX7D;
@@ -128,7 +98,7 @@ uint32_t imx_get_src_gpr(int cpu)
 {
 	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
 
-	if (soc_is_imx7d())
+	if (soc_is_imx7ds())
 		return read32(va + SRC_GPR1_MX7 + cpu * 8 + 4);
 	else
 		return read32(va + SRC_GPR1 + cpu * 8 + 4);
@@ -138,7 +108,7 @@ void imx_set_src_gpr(int cpu, uint32_t val)
 {
 	vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC);
 
-	if (soc_is_imx7d())
+	if (soc_is_imx7ds())
 		write32(val, va + SRC_GPR1_MX7 + cpu * 8 + 4);
 	else
 		write32(val, va + SRC_GPR1 + cpu * 8 + 4);
diff --git a/core/arch/arm/plat-imx/imx.h b/core/arch/arm/plat-imx/imx.h
index 953a3b560f8..8f08b8d7cfd 100644
--- a/core/arch/arm/plat-imx/imx.h
+++ b/core/arch/arm/plat-imx/imx.h
@@ -51,8 +51,6 @@ bool soc_is_imx6sdl(void);
 bool soc_is_imx6dq(void);
 bool soc_is_imx6dqp(void);
 bool soc_is_imx7ds(void);
-bool soc_is_imx7d(void);
-bool soc_is_imx7s(void);
 uint32_t imx_soc_type(void);
 void imx_gpcv2_set_core1_pdn_by_software(void);
 void imx_gpcv2_set_core1_pup_by_software(void);
diff --git a/core/arch/arm/plat-imx/pm/psci.c b/core/arch/arm/plat-imx/pm/psci.c
index 40177c09463..220da0f7d61 100644
--- a/core/arch/arm/plat-imx/pm/psci.c
+++ b/core/arch/arm/plat-imx/pm/psci.c
@@ -118,7 +118,7 @@ int psci_affinity_info(uint32_t affinity,
 
 	cpu = affinity;
 
-	if (soc_is_imx7d())
+	if (soc_is_imx7ds())
 		wfi = true;
 	else
 		wfi = read32(gpr5) & ARM_WFI_STAT_MASK(cpu);
@@ -131,7 +131,7 @@ int psci_affinity_info(uint32_t affinity,
 	 * Wait secondary cpus ready to be killed
 	 * TODO: Change to non dead loop
 	 */
-	if (soc_is_imx7d()) {
+	if (soc_is_imx7ds()) {
 		while (read32(va + SRC_GPR1_MX7 + cpu * 8 + 4) != UINT_MAX)
 			;