diff --git a/.travis.yml b/.travis.yml index c835f34fd58..6866dfe6487 100644 --- a/.travis.yml +++ b/.travis.yml @@ -160,7 +160,6 @@ script: - $make CFG_RPMB_FS=y CFG_RPMB_TESTKEY=y - $make CFG_REE_FS=n CFG_RPMB_FS=y - $make CFG_WITH_USER_TA=n CFG_CRYPTO=n CFG_SE_API=n CFG_PCSC_PASSTHRU_READER_DRV=n - - $make CFG_SMALL_PAGE_USER_TA=n - $make CFG_WITH_PAGER=y CFG_WITH_LPAE=y CFG_RPMB_FS=y CFG_DT=y CFG_PS2MOUSE=y CFG_PL050=y CFG_PL111=y CFG_TEE_CORE_LOG_LEVEL=1 CFG_TEE_CORE_DEBUG=y DEBUG=1 - $make CFG_WITH_PAGER=y CFG_WITH_LPAE=y CFG_RPMB_FS=y CFG_DT=y CFG_PS2MOUSE=y CFG_PL050=y CFG_PL111=y CFG_TEE_CORE_LOG_LEVEL=0 CFG_TEE_CORE_DEBUG=n DEBUG=0 - $make CFG_BUILT_IN_ARGS=y CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0 CFG_DT_ADDR=0 CFG_DT=y diff --git a/core/arch/arm/include/kernel/thread.h b/core/arch/arm/include/kernel/thread.h index 5e340d3d652..97c988c926f 100644 --- a/core/arch/arm/include/kernel/thread.h +++ b/core/arch/arm/include/kernel/thread.h @@ -61,9 +61,7 @@ extern struct thread_vector_table thread_vector_table; struct thread_specific_data { TAILQ_HEAD(, tee_ta_session) sess_stack; struct tee_ta_ctx *ctx; -#ifdef CFG_SMALL_PAGE_USER_TA struct pgt_cache pgt_cache; -#endif void *rpc_fs_payload; paddr_t rpc_fs_payload_pa; uint64_t rpc_fs_payload_cookie; diff --git a/core/arch/arm/include/mm/core_mmu.h b/core/arch/arm/include/mm/core_mmu.h index 15d458424ff..0b73e93a9e1 100644 --- a/core/arch/arm/include/mm/core_mmu.h +++ b/core/arch/arm/include/mm/core_mmu.h @@ -59,20 +59,12 @@ #define CORE_MMU_DEVICE_MASK (CORE_MMU_DEVICE_SIZE - 1) /* TA user space code, data, stack and heap are mapped using this granularity */ -#ifdef CFG_SMALL_PAGE_USER_TA #define CORE_MMU_USER_CODE_SHIFT SMALL_PAGE_SHIFT -#else -#define CORE_MMU_USER_CODE_SHIFT CORE_MMU_PGDIR_SHIFT -#endif #define CORE_MMU_USER_CODE_SIZE (1 << CORE_MMU_USER_CODE_SHIFT) #define CORE_MMU_USER_CODE_MASK (CORE_MMU_USER_CODE_SIZE - 1) /* TA user space parameters are mapped using this granularity */ -#ifdef CFG_SMALL_PAGE_USER_TA #define CORE_MMU_USER_PARAM_SHIFT SMALL_PAGE_SHIFT -#else -#define CORE_MMU_USER_PARAM_SHIFT CORE_MMU_PGDIR_SHIFT -#endif #define CORE_MMU_USER_PARAM_SIZE (1 << CORE_MMU_USER_PARAM_SHIFT) #define CORE_MMU_USER_PARAM_MASK (CORE_MMU_USER_PARAM_SIZE - 1) diff --git a/core/arch/arm/include/mm/pgt_cache.h b/core/arch/arm/include/mm/pgt_cache.h index 8812758347e..c300591c6ff 100644 --- a/core/arch/arm/include/mm/pgt_cache.h +++ b/core/arch/arm/include/mm/pgt_cache.h @@ -52,12 +52,9 @@ struct pgt { struct pgt_parent *parent; #endif #endif -#ifdef CFG_SMALL_PAGE_USER_TA SLIST_ENTRY(pgt) link; -#endif }; -#ifdef CFG_SMALL_PAGE_USER_TA /* * Reserve 2 page tables per thread, but at least 4 page tables in total */ @@ -95,14 +92,6 @@ void pgt_transfer(struct pgt_cache *pgt_cache, void *old_ctx, vaddr_t old_va, void pgt_init(void); -#else - -static inline void pgt_init(void) -{ -} - -#endif - #if defined(CFG_PAGED_USER_TA) void pgt_flush_ctx(struct tee_ta_ctx *ctx); diff --git a/core/arch/arm/kernel/thread.c b/core/arch/arm/kernel/thread.c index 6c1451952ea..d71ef827e27 100644 --- a/core/arch/arm/kernel/thread.c +++ b/core/arch/arm/kernel/thread.c @@ -402,9 +402,7 @@ void thread_init_boot_thread(void) for (n = 0; n < CFG_NUM_THREADS; n++) { TAILQ_INIT(&threads[n].mutexes); TAILQ_INIT(&threads[n].tsd.sess_stack); -#ifdef CFG_SMALL_PAGE_USER_TA SLIST_INIT(&threads[n].tsd.pgt_cache); -#endif } for (n = 0; n < CFG_TEE_CORE_NB_CORE; n++) diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c index 8a6fb93faff..beded64b476 100644 --- a/core/arch/arm/mm/core_mmu.c +++ b/core/arch/arm/mm/core_mmu.c @@ -962,7 +962,6 @@ static void set_region(struct core_mmu_table_info *tbl_info, } } -#ifdef CFG_SMALL_PAGE_USER_TA static void set_pg_region(struct core_mmu_table_info *dir_info, struct tee_ta_region *region, struct pgt **pgt, struct core_mmu_table_info *pg_info) @@ -1140,34 +1139,6 @@ void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, } } -#else -void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, - struct user_ta_ctx *utc) -{ - unsigned n; - struct tee_mmap_region r; - size_t offset; - size_t granule = BIT(dir_info->shift); - - memset(&r, 0, sizeof(r)); - for (n = 0; n < ARRAY_SIZE(utc->mmu->regions); n++) { - if (!utc->mmu->regions[n].size) - continue; - - offset = utc->mmu->regions[n].offset; - r.va = utc->mmu->regions[n].va; - r.size = utc->mmu->regions[n].size; - r.attr = utc->mmu->regions[n].attr; - - if (mobj_get_pa(utc->mmu->regions[n].mobj, offset, granule, - &r.pa) != TEE_SUCCESS) - panic("Failed to get PA of unpaged mobj"); - - set_region(dir_info, &r); - } -} -#endif - bool core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, size_t len) { struct core_mmu_table_info tbl_info; diff --git a/core/arch/arm/mm/sub.mk b/core/arch/arm/mm/sub.mk index 71f70f3ee78..293957afc59 100644 --- a/core/arch/arm/mm/sub.mk +++ b/core/arch/arm/mm/sub.mk @@ -8,5 +8,5 @@ else srcs-y += core_mmu_v7.c endif srcs-y += tee_mm.c -srcs-$(CFG_SMALL_PAGE_USER_TA) += pgt_cache.c +srcs-y += pgt_cache.c srcs-y += mobj.c diff --git a/core/arch/arm/mm/tee_mmu.c b/core/arch/arm/mm/tee_mmu.c index f5c6dde549a..b9439cdd9c5 100644 --- a/core/arch/arm/mm/tee_mmu.c +++ b/core/arch/arm/mm/tee_mmu.c @@ -238,7 +238,6 @@ TEE_Result tee_mmu_init(struct user_ta_ctx *utc) return TEE_SUCCESS; } -#ifdef CFG_SMALL_PAGE_USER_TA static TEE_Result alloc_pgt(struct user_ta_ctx *utc __maybe_unused, vaddr_t base, vaddr_t end) { @@ -277,19 +276,6 @@ static void free_pgt(struct user_ta_ctx *utc, vaddr_t base, size_t size) pgt_flush_ctx_range(pgt_cache, &utc->ctx, base, base + size); } -#else -static TEE_Result alloc_pgt(struct user_ta_ctx *utc __unused, - vaddr_t base __unused, vaddr_t end __unused) -{ - return TEE_SUCCESS; -} - -static void free_pgt(struct user_ta_ctx *utc __unused, vaddr_t base __unused, - size_t size __unused) -{ -} -#endif - void tee_mmu_map_stack(struct user_ta_ctx *utc, struct mobj *mobj) { const size_t granule = CORE_MMU_USER_CODE_SIZE; @@ -793,7 +779,6 @@ void tee_mmu_set_ctx(struct tee_ta_ctx *ctx) struct thread_specific_data *tsd = thread_get_tsd(); core_mmu_set_user_map(NULL); -#ifdef CFG_SMALL_PAGE_USER_TA /* * No matter what happens below, the current user TA will not be * current any longer. Make sure pager is in sync with that. @@ -803,7 +788,6 @@ void tee_mmu_set_ctx(struct tee_ta_ctx *ctx) * Save translation tables in a cache if it's a user TA. */ pgt_free(&tsd->pgt_cache, tsd->ctx && is_user_ta_ctx(tsd->ctx)); -#endif if (ctx && is_user_ta_ctx(ctx)) { struct core_mmu_user_map map; diff --git a/core/core.mk b/core/core.mk index 075bc010931..bcf788d1e00 100644 --- a/core/core.mk +++ b/core/core.mk @@ -14,8 +14,7 @@ include core/arch/$(ARCH)/$(ARCH).mk PLATFORM_$(PLATFORM) := y PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) := y -$(call cfg-depends-all,CFG_PAGED_USER_TA,CFG_WITH_PAGER \ - CFG_SMALL_PAGE_USER_TA CFG_WITH_USER_TA) +$(call cfg-depends-all,CFG_PAGED_USER_TA,CFG_WITH_PAGER CFG_WITH_USER_TA) # Setup compiler for this sub module COMPILER_$(sm) ?= $(COMPILER) diff --git a/mk/config.mk b/mk/config.mk index d2afba663b4..b04c2659427 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -169,9 +169,6 @@ CFG_WITH_USER_TA ?= y # case you implement your own TA store CFG_REE_FS_TA ?= y -# Use small pages to map user TAs -CFG_SMALL_PAGE_USER_TA ?= y - # Enable paging, requires SRAM, can't be enabled by default CFG_WITH_PAGER ?= n