Commits on Jan 13, 2018

1. arm: pl310: fix cache sync …

   According to PL310 TRM:
   Atomic operations:
   The following are atomic operations:
       Clean Line by PA or by Set/Way
       Invalidate Line by PA
       Clean and Invalidate Line by PA or by Set/Way
       Cache Sync.
   These operations stall the slave ports until they are complete.
   When these registers are read, bit [0], the C flag, indicates that
   a background operation is in progress. When written, bit 0 must be
   zero.
   
   So write 1 to sync register is not correct.
   
   Signed-off-by: Peng Fan <peng.fan@nxp.com>
   Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
   Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

   

   MrVan committed Jan 13, 2018
   Configuration menu

   • View commit details
   • Copy full SHA for a6cb216
   • Browse repository at this point

   Copy the full SHA

   a6cb216 View commit details

   Browse the repository at this point in the history