esw_uCOS3_cykit.svd

<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
  <name>CY8C5888LTI_LP097</name>
  <version>0.1</version>
  <description>CY8C58LP</description>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <peripherals>
    <peripheral>
      <name>PWM_rgb_green</name>
      <description>No description available</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PWM_rgb_green_COMPARE_Reg_</name>
          <description>UDB.D0 - Assigned Compare Value</description>
          <addressOffset>0x4000652A</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>PWM_rgb_green_Control_Reg</name>
          <description>UDB Control Register - Assigned Control Register Value</description>
          <addressOffset>0x4000657A</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CTRL_ENABLE</name>
              <description>Enable the PWM</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CTRL_CMPMODE2</name>
              <description>Compare mode 2</description>
              <lsb>3</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CTRL_CMPMODE1</name>
              <description>Compare mode 1</description>
              <lsb>0</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWM_rgb_green_STATUS_MASK</name>
          <description>UDB Status bits Interrupt Mask Enable Register</description>
          <addressOffset>0x4000658A</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>PWM_STS_CMP1</name>
              <description>Enables the Interrupt on Compare 1</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_CMP2</name>
              <description>Enables the Interrupt on Compare 2</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_TC</name>
              <description>Enables the Interrupt on Terminal Count</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_FIFO_FULL</name>
              <description>FIFO Full Status Mask </description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_KILL</name>
              <description>Enables the Interrupt on Kill</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWM_rgb_green_STATUS_AUX_CTRL</name>
          <description>UDB Auxilliary Control Register</description>
          <addressOffset>0x4000659A</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>FIFO0_CLR</name>
              <description>FIFO0 clear</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_CLR_0</name>
                  <description>Normal FIFO operation</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_CLR_1</name>
                  <description>Clear FIFO state</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO1_CLR</name>
              <description>FIFO1 clear</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_CLR_0</name>
                  <description>Normal FIFO operation</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_CLR_1</name>
                  <description>Clear FIFO state</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO0_LVL</name>
              <description>FIFO level</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_LVL_0</name>
                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_LVL_1</name>
                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO1_LVL</name>
              <description>FIFO level</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_LVL_0</name>
                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_LVL_1</name>
                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INT_EN</name>
              <description>No description available</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_INT_EN0</name>
                  <description>Interrupt disabled</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_INT_EN1</name>
                  <description>Interrupt enabled</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CNT_START</name>
              <description>FIFO0 clear</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_CNT_START0</name>
                  <description>Disable counter</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_CNT_START1</name>
                  <description>Enable counter</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>PWM_rgb_red</name>
      <description>No description available</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PWM_rgb_red_COMPARE_Reg_</name>
          <description>UDB.D0 - Assigned Compare Value</description>
          <addressOffset>0x4000642D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>PWM_rgb_red_Control_Reg</name>
          <description>UDB Control Register - Assigned Control Register Value</description>
          <addressOffset>0x4000647D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CTRL_ENABLE</name>
              <description>Enable the PWM</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CTRL_CMPMODE2</name>
              <description>Compare mode 2</description>
              <lsb>3</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CTRL_CMPMODE1</name>
              <description>Compare mode 1</description>
              <lsb>0</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWM_rgb_red_STATUS_MASK</name>
          <description>UDB Status bits Interrupt Mask Enable Register</description>
          <addressOffset>0x4000648D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>PWM_STS_CMP1</name>
              <description>Enables the Interrupt on Compare 1</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_CMP2</name>
              <description>Enables the Interrupt on Compare 2</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_TC</name>
              <description>Enables the Interrupt on Terminal Count</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_FIFO_FULL</name>
              <description>FIFO Full Status Mask </description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_KILL</name>
              <description>Enables the Interrupt on Kill</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWM_rgb_red_STATUS_AUX_CTRL</name>
          <description>UDB Auxilliary Control Register</description>
          <addressOffset>0x4000649D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>FIFO0_CLR</name>
              <description>FIFO0 clear</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_CLR_0</name>
                  <description>Normal FIFO operation</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_CLR_1</name>
                  <description>Clear FIFO state</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO1_CLR</name>
              <description>FIFO1 clear</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_CLR_0</name>
                  <description>Normal FIFO operation</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_CLR_1</name>
                  <description>Clear FIFO state</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO0_LVL</name>
              <description>FIFO level</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_LVL_0</name>
                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_LVL_1</name>
                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO1_LVL</name>
              <description>FIFO level</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_LVL_0</name>
                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_LVL_1</name>
                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INT_EN</name>
              <description>No description available</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_INT_EN0</name>
                  <description>Interrupt disabled</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_INT_EN1</name>
                  <description>Interrupt enabled</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CNT_START</name>
              <description>FIFO0 clear</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_CNT_START0</name>
                  <description>Disable counter</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_CNT_START1</name>
                  <description>Enable counter</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>PWM_rgb_blue</name>
      <description>No description available</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PWM_rgb_blue_COMPARE_Reg_</name>
          <description>UDB.D0 - Assigned Compare Value</description>
          <addressOffset>0x40006429</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>PWM_rgb_blue_Control_Reg</name>
          <description>UDB Control Register - Assigned Control Register Value</description>
          <addressOffset>0x40006479</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CTRL_ENABLE</name>
              <description>Enable the PWM</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CTRL_CMPMODE2</name>
              <description>Compare mode 2</description>
              <lsb>3</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CTRL_CMPMODE1</name>
              <description>Compare mode 1</description>
              <lsb>0</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWM_rgb_blue_STATUS_MASK</name>
          <description>UDB Status bits Interrupt Mask Enable Register</description>
          <addressOffset>0x40006489</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>PWM_STS_CMP1</name>
              <description>Enables the Interrupt on Compare 1</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_CMP2</name>
              <description>Enables the Interrupt on Compare 2</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_TC</name>
              <description>Enables the Interrupt on Terminal Count</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_FIFO_FULL</name>
              <description>FIFO Full Status Mask </description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>PWM_STS_KILL</name>
              <description>Enables the Interrupt on Kill</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWM_rgb_blue_STATUS_AUX_CTRL</name>
          <description>UDB Auxilliary Control Register</description>
          <addressOffset>0x40006499</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>FIFO0_CLR</name>
              <description>FIFO0 clear</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_CLR_0</name>
                  <description>Normal FIFO operation</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_CLR_1</name>
                  <description>Clear FIFO state</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO1_CLR</name>
              <description>FIFO1 clear</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_CLR_0</name>
                  <description>Normal FIFO operation</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_CLR_1</name>
                  <description>Clear FIFO state</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO0_LVL</name>
              <description>FIFO level</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_LVL_0</name>
                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_LVL_1</name>
                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FIFO1_LVL</name>
              <description>FIFO level</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_FIFO_LVL_0</name>
                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_FIFO_LVL_1</name>
                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INT_EN</name>
              <description>No description available</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_INT_EN0</name>
                  <description>Interrupt disabled</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_INT_EN1</name>
                  <description>Interrupt enabled</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CNT_START</name>
              <description>FIFO0 clear</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>E_CNT_START0</name>
                  <description>Disable counter</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>E_CNT_START1</name>
                  <description>Enable counter</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>UART_1</name>
      <description>UART</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>TX_UART_1_TX_STATUS</name>
          <description>TX status register</description>
          <addressOffset>0x40006467</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>UART_1_TX_STS_COMPLETE</name>
              <description>No description available</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_TX_STS_FIFO_EMPTY</name>
              <description>No description available</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_TX_STS_FIFO_FULL</name>
              <description>No description available</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_TX_STS_FIFO_NOT_FULL</name>
              <description>No description available</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_UART_1_RX_ADDRESS1</name>
          <description>RX Address1 Register</description>
          <addressOffset>0x4000652B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>RX_UART_1_RX_ADDRESS2</name>
          <description>RX Address2 Register</description>
          <addressOffset>0x4000653B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>TX_UART_1_TX_DATA</name>
          <description>TX Data Register</description>
          <addressOffset>0x40006547</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>RX_UART_1_RX_DATA</name>
          <description>RX Data Register</description>
          <addressOffset>0x4000654B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>RX_UART_1_RX_STATUS</name>
          <description>RX status register</description>
          <addressOffset>0x4000656B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>UART_1_RX_STS_MRKSPC</name>
              <description>No description available</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_BREAK</name>
              <description>No description available</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_PAR_ERROR</name>
              <description>No description available</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_STOP_ERROR</name>
              <description>No description available</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_OVERRUN</name>
              <description>No description available</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_FIFO_NOTEMPTY</name>
              <description>No description available</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_ADDR_MATCH</name>
              <description>No description available</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>