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Add the gates ECR, iSwap, CY, SX, SXdg, DCX to the Clifford class (#9623
) * add SX and SXdg gates * add CY, iSwap and ECR gates * add new gates to the Clifford docs * improve ECR * add more tests for the new gates * add ECR decomposition into Clifford gates to the equivalence library * update ECR in equivalence library * add DCX to clifford_circuits.py * add test for dcx * add release notes * more efficient synthesis of an ECR gate * change the release notes from features to bug fix --------- Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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releasenotes/notes/add-gates-to-Clifford-class-7de8d3213c60836a.yaml
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Original file line number | Diff line number | Diff line change |
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--- | ||
fixes: | ||
- | | ||
Add the following Clifford gates, that already exist in the Circuit Library, | ||
to the :class:`.Clifford` class: | ||
:class:`.SXGate`, :class:`.SXdgGate`, :class:`.CYGate`, :class:`.DCXGate`, | ||
:class:`.iSwapGate` and :class:`.ECRGate`. | ||
- | | ||
Add a decomposition of an :class:`.ECRGate` into Clifford gates (up to a global phase) | ||
into the :class:`.EquivalenceLibrary`. |
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