diff --git a/releasenotes/notes/relax_wire_order_restrictions-ffc0cfeacd7b8d4b.yaml b/releasenotes/notes/relax_wire_order_restrictions-ffc0cfeacd7b8d4b.yaml
index 70f83fdb5c88..c8fd6337fdb7 100644
--- a/releasenotes/notes/relax_wire_order_restrictions-ffc0cfeacd7b8d4b.yaml
+++ b/releasenotes/notes/relax_wire_order_restrictions-ffc0cfeacd7b8d4b.yaml
@@ -17,7 +17,7 @@ features:
       circuit.h(3)
       circuit.x(1)
       circuit.x(3).c_if(cr, 10)
-      circuit.draw('text', wire_order=[2, 3], cregbundle=True)
+      circuit.draw('text', wire_order=[2, 3, 0, 1], cregbundle=True)
 
     .. parsed-literal::