Improve ancilla detection in HighLevelSynthesis

[alexanderivrii]

What should we add?

In #12911 we have added the ability to track the state of each qubit within the HighLevelSynthesis transpiler pass (i.e. whether the qubit is "clean" (in state $|0\rangle$) or "dirty" (in some other state)) and to automatically exploit clean/dirty ancilla qubits with the appropriate synthesis algorithms.

In the following snippet, a circuit with a single MCX-gate

qc = QuantumCircuit(10)
qc.mcx([3, 4, 5, 6, 7], 0)
basis_gates = ["u", "cx"]
tqc = HighLevelSynthesis(basis_gates=basis_gates)(qc)

is synthesized to a circuit with 24 CX-gates and 45 U-gates. Internally the MCX synthesis algorithm has access to $4$ clean ancilla qubits (1, 2, 8, 9).

However, an arguably identical circuit in the following snippet,

inner = QuantumCircuit(6)
inner.mcx([0, 1, 2, 3, 4], 5)
custom_gate = inner.to_gate()
qc = QuantumCircuit(10)
qc.append(custom_gate, [3, 4, 5, 6, 7, 0])
basis_gates = ["u", "cx"]
tqc = HighLevelSynthesis(basis_gates=basis_gates)(qc)

is synthesized to a worse circuit with 84 CX-gates and 127 U-gates. This is due to how the recursion is treated with HighLevelSynthesis, with the synthesis of custom_gate having no access to ancilla qubits outside of its definition.

This issue will be very soon followed by a PR addressing the problem above.