From 915b80180d268cc5c54472b9e625063dd48627f8 Mon Sep 17 00:00:00 2001
From: Runcheng Lu <runcheng.lu@hpmicro.com>
Date: Sun, 15 Sep 2024 21:36:52 +0800
Subject: [PATCH] projects: hslink-pro: improve CLK clock output accuracy

- in SPI mode, SWD can be adjusted from 80M to 100Khz
- in single SPI mode, jtag clk can be adjusted from 80 to 100 khz
---
 projects/HSLink-Pro/src/dp_common.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/projects/HSLink-Pro/src/dp_common.c b/projects/HSLink-Pro/src/dp_common.c
index 02fc55b..b9bc3f3 100644
--- a/projects/HSLink-Pro/src/dp_common.c
+++ b/projects/HSLink-Pro/src/dp_common.c
@@ -9,11 +9,11 @@
 #include "hpm_spi_drv.h"
 
 #define SPI_MAX_SRC_CLOCK 80000000
-#define SPI_MIN_SRC_CLOCK 60000000
-
+#define SPI_MID_SRC_CLOCK 60000000
+#define SPI_MIN_SRC_CLOCK 50000000
 void set_swj_clock_frequency(uint32_t clock)
 {
-    uint8_t div, sclk_div;
+    uint32_t div, sclk_div;
     uint32_t sclk_freq_in_hz;
     sclk_freq_in_hz = clock;
     SPI_Type *spi_base = NULL;
@@ -24,7 +24,7 @@ void set_swj_clock_frequency(uint32_t clock)
     }
     PORT_Mode_t mode;
     if (DAP_Data.debug_port == DAP_PORT_SWD) {
-        if (sclk_freq_in_hz < 1000000) {
+        if (sclk_freq_in_hz < 100000) {
             mode = PORT_MODE_GPIO;
         } else {
             mode = PORT_MODE_SPI;
@@ -39,7 +39,7 @@ void set_swj_clock_frequency(uint32_t clock)
         spi_base = SWD_SPI_BASE;
         clock_name = SWD_SPI_BASE_CLOCK_NAME;
     } else {
-        if (sclk_freq_in_hz < 1000000) {
+        if (sclk_freq_in_hz < 100000) {
             mode = PORT_MODE_GPIO;
         } else {
             mode = PORT_MODE_SPI;
@@ -64,11 +64,16 @@ void set_swj_clock_frequency(uint32_t clock)
     if (sclk_div <= 0xFE) {
         div = 10;
     } else {
+        div = 10;
         src_clock = clk_src_pll0_clk1;                              /* 600M */
-        sclk_div = ((SPI_MIN_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1; /* SCLK = SPI_SRC_CLOK / ((SCLK_DIV + 1) * 2)*/
-        if (sclk_div <= 0xFE) {
+        sclk_div = ((SPI_MID_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1; /* SCLK = SPI_SRC_CLOK / ((SCLK_DIV + 1) * 2)*/
+        if (sclk_div >= 0xFE) {
             div = 10;
-            sclk_div = 0xFE; /* The minimum sclk clock allowed is 117KHz */
+            src_clock = clk_src_pll1_clk2;  /* 500M */
+            sclk_div = ((SPI_MIN_SRC_CLOCK / sclk_freq_in_hz) / 2) - 1;
+            if (sclk_div >= 0xFE) {
+                sclk_div = 0xFE; /* The minimum sclk clock allowed is 98KHz */
+            }
         }
     }
     spi_master_set_sclk_div(spi_base, sclk_div);