From 8887cf55e7b27013a87ae6cab996289a2dea6647 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 3 Feb 2017 18:30:36 +0100 Subject: [PATCH 1/3] cpu/stm32f4: add support for stm32f446ze --- cpu/stm32f4/include/cpu_conf.h | 2 +- cpu/stm32f4/ldscripts/stm32f446ze.ld | 30 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 cpu/stm32f4/ldscripts/stm32f446ze.ld diff --git a/cpu/stm32f4/include/cpu_conf.h b/cpu/stm32f4/include/cpu_conf.h index b563da092f7d..75c0d8cf7d05 100644 --- a/cpu/stm32f4/include/cpu_conf.h +++ b/cpu/stm32f4/include/cpu_conf.h @@ -35,7 +35,7 @@ #include "vendor/stm32f413xx.h" #elif defined(CPU_MODEL_STM32F415RG) #include "vendor/stm32f415xx.h" -#elif defined(CPU_MODEL_STM32F446RE) +#elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE) #include "vendor/stm32f446xx.h" #endif diff --git a/cpu/stm32f4/ldscripts/stm32f446ze.ld b/cpu/stm32f4/ldscripts/stm32f446ze.ld new file mode 100644 index 000000000000..8b6274f11dff --- /dev/null +++ b/cpu/stm32f4/ldscripts/stm32f446ze.ld @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @addtogroup cpu_stm32f4 + * @{ + * + * @file + * @brief Memory definitions for the STM32F446ZE + * + * @author Alexandre Abadie + * + * @} + */ + +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12 +} + +_cpuid_address = ORIGIN(cpuid); + +INCLUDE cortexm_base.ld From 57daad4ed6e5f493e8921ef853fb41c5401ec1d5 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 3 Feb 2017 18:31:03 +0100 Subject: [PATCH 2/3] boards/nucleo144-f446: initial support --- boards/nucleo144-f446/Makefile | 3 + boards/nucleo144-f446/Makefile.dep | 1 + boards/nucleo144-f446/Makefile.features | 14 ++ boards/nucleo144-f446/Makefile.include | 6 + boards/nucleo144-f446/board.c | 31 +++ boards/nucleo144-f446/dist/openocd.cfg | 1 + boards/nucleo144-f446/include/board.h | 45 ++++ boards/nucleo144-f446/include/periph_conf.h | 257 ++++++++++++++++++++ 8 files changed, 358 insertions(+) create mode 100644 boards/nucleo144-f446/Makefile create mode 100644 boards/nucleo144-f446/Makefile.dep create mode 100644 boards/nucleo144-f446/Makefile.features create mode 100644 boards/nucleo144-f446/Makefile.include create mode 100644 boards/nucleo144-f446/board.c create mode 100644 boards/nucleo144-f446/dist/openocd.cfg create mode 100644 boards/nucleo144-f446/include/board.h create mode 100644 boards/nucleo144-f446/include/periph_conf.h diff --git a/boards/nucleo144-f446/Makefile b/boards/nucleo144-f446/Makefile new file mode 100644 index 000000000000..f8fcbb53a065 --- /dev/null +++ b/boards/nucleo144-f446/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo144-f446/Makefile.dep b/boards/nucleo144-f446/Makefile.dep new file mode 100644 index 000000000000..76e2dc17b45c --- /dev/null +++ b/boards/nucleo144-f446/Makefile.dep @@ -0,0 +1 @@ +include $(RIOTBOARD)/nucleo-common/Makefile.dep diff --git a/boards/nucleo144-f446/Makefile.features b/boards/nucleo144-f446/Makefile.features new file mode 100644 index 000000000000..5d69098c65b8 --- /dev/null +++ b/boards/nucleo144-f446/Makefile.features @@ -0,0 +1,14 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_cpuid +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# load the common Makefile.features for Nucleo boards +include $(RIOTBOARD)/nucleo144-common/Makefile.features + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = cortex_m4_3 diff --git a/boards/nucleo144-f446/Makefile.include b/boards/nucleo144-f446/Makefile.include new file mode 100644 index 000000000000..12efc2b3a820 --- /dev/null +++ b/boards/nucleo144-f446/Makefile.include @@ -0,0 +1,6 @@ +# define the cpu used by the nucleo144-f446 board +export CPU = stm32f4 +export CPU_MODEL = stm32f446ze + +# load the common Makefile.include for Nucleo-144 boards +include $(RIOTBOARD)/nucleo144-common/Makefile.include diff --git a/boards/nucleo144-f446/board.c b/boards/nucleo144-f446/board.c new file mode 100644 index 000000000000..b4fc5cb0beec --- /dev/null +++ b/boards/nucleo144-f446/board.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo144-f446 + * @{ + * + * @file + * @brief Board specific implementations for the nucleo144-f446 board + * + * @author Alexandre Abadie + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + /* initialize the CPU */ + cpu_init(); + + /* initialize the boards LEDs */ + gpio_init(LED0_PIN, GPIO_OUT); +} diff --git a/boards/nucleo144-f446/dist/openocd.cfg b/boards/nucleo144-f446/dist/openocd.cfg new file mode 100644 index 000000000000..9a3061f0bf82 --- /dev/null +++ b/boards/nucleo144-f446/dist/openocd.cfg @@ -0,0 +1 @@ +source [find board/st_nucleo_f4.cfg] diff --git a/boards/nucleo144-f446/include/board.h b/boards/nucleo144-f446/include/board.h new file mode 100644 index 000000000000..cf7f93dc8f58 --- /dev/null +++ b/boards/nucleo144-f446/include/board.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup boards_nucleo144-f446 Nucleo144-F446 + * @ingroup boards + * @brief Board specific files for the nucleo144-f446 board + * @{ + * + * @file + * @brief Board specific definitions for the nucleo144-f446 board + * + * @author Alexandre Abadie + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "board_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name xtimer configuration + * @{ + */ +#define XTIMER_DEV TIMER_DEV(0) +#define XTIMER_CHAN (0) +#define XTIMER_OVERHEAD (6) +#define XTIMER_BACKOFF (5) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/nucleo144-f446/include/periph_conf.h b/boards/nucleo144-f446/include/periph_conf.h new file mode 100644 index 000000000000..8c08db678372 --- /dev/null +++ b/boards/nucleo144-f446/include/periph_conf.h @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo144-f446 + * @{ + * + * @file + * @name Peripheral MCU configuration for the nucleo144-f446 board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +#define CLOCK_HSE (8000000U) /* external oscillator */ +#define CLOCK_CORECLOCK (180000000U) /* desired core clock frequency */ + +/* the actual PLL values are automatically generated */ +#define CLOCK_PLL_M (CLOCK_HSE / 1000000) +#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2) +#define CLOCK_PLL_P (2U) +#define CLOCK_PLL_Q (CLOCK_PLL_N / 48) +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 +#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS + +/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM5, + .max = 0xffffffff, + .rcc_mask = RCC_APB1ENR_TIM5EN, + .bus = APB1, + .irqn = TIM5_IRQn + } +}; + +#define TIMER_0_ISR isr_tim5 + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART3, + .rcc_mask = RCC_APB1ENR_USART3EN, + .rx_pin = GPIO_PIN(PORT_D, 9), + .tx_pin = GPIO_PIN(PORT_D, 8), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART3_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 6, + .dma_chan = 4 +#endif + }, + { + .dev = USART2, + .rcc_mask = RCC_APB1ENR_USART2EN, + .rx_pin = GPIO_PIN(PORT_A, 3), + .tx_pin = GPIO_PIN(PORT_A, 2), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART2_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 5, + .dma_chan = 4 +#endif + }, + { + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_A, 10), + .tx_pin = GPIO_PIN(PORT_A, 9), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB2, + .irqn = USART1_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 4, + .dma_chan = 4 +#endif + }, +}; + +#define UART_0_ISR (isr_usart3) +#define UART_0_DMA_ISR (isr_dma1_stream6) +#define UART_1_ISR (isr_usart2) +#define UART_1_DMA_ISR (isr_dma1_stream5) +#define UART_2_ISR (isr_usart1) +#define UART_2_DMA_ISR (isr_dma1_stream4) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @brief PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .dev = TIM2, + .rcc_mask = RCC_APB1ENR_TIM2EN, + .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0}, + { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1}, + { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2}, + { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} }, + .af = GPIO_AF1, + .bus = APB1 + }, + { + .dev = TIM3, + .rcc_mask = RCC_APB1ENR_TIM3EN, + .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 } }, + .af = GPIO_AF2, + .bus = APB1 + }, + { + .dev = TIM8, + .rcc_mask = RCC_APB2ENR_TIM8EN, + .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0}, + { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1}, + { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2}, + { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} }, + .af = GPIO_AF3, + .bus = APB2 + }, +}; + +#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) +/** @} */ + +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 90000000Hz */ + 7, /* -> 351562Hz */ + 7, /* -> 351562Hz */ + 6, /* -> 703125Hz */ + 3, /* -> 5625000Hz */ + 2 /* -> 11250000Hz */ + }, + { /* for APB2 @ 180000000Hz */ + 7, /* -> 703125Hz */ + 7, /* -> 703125Hz */ + 7, /* -> 703125Hz */ + 4, /* -> 5625000Hz */ + 3 /* -> 11250000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + } +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + + +/** + * @name I2C configuration + * @{ + */ +#define I2C_NUMOF (1U) +#define I2C_0_EN 1 +#define I2C_IRQ_PRIO 1 +#define I2C_APBCLK (42000000U) + +/* I2C 0 device configuration */ +#define I2C_0_DEV I2C1 +#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN)) +#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN)) +#define I2C_0_EVT_IRQ I2C1_EV_IRQn +#define I2C_0_EVT_ISR isr_i2c1_ev +#define I2C_0_ERR_IRQ I2C1_ER_IRQn +#define I2C_0_ERR_ISR isr_i2c1_er +/* I2C 0 pin configuration */ +#define I2C_0_SCL_PORT GPIOB +#define I2C_0_SCL_PIN 8 +#define I2C_0_SCL_AF 4 +#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN)) +#define I2C_0_SDA_PORT GPIOB +#define I2C_0_SDA_PIN 9 +#define I2C_0_SDA_AF 4 +#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN)) +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +#define ADC_NUMOF (0) +/** @} */ + +/** + * @name DAC configuration + * @{ + */ +#define DAC_NUMOF (0) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */ From 879fe0c41631c81f8e67770d0e8cf879f5eb27f3 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Thu, 16 Mar 2017 18:22:28 +0100 Subject: [PATCH 3/3] tests/unittests: add nucleo144-f446 to cortexM boards --- tests/unittests/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/unittests/Makefile b/tests/unittests/Makefile index 4e5a94697afe..af9e0bebe750 100644 --- a/tests/unittests/Makefile +++ b/tests/unittests/Makefile @@ -27,9 +27,9 @@ DISABLE_TEST_FOR_ARM7 := tests-relic ARM_CORTEX_M_BOARDS := airfy-beacon arduino-due arduino-zero cc2538dk ek-lm4f120xl \ f4vi1 fox frdm-k64f iotlab-m3 limifrog-v1 mbed_lpc1768 msbiot \ - mulle nrf51dongle nrf6310 nucleo32-f031 nucleo32-f303 nucleo32-l031 \ - nucleo-f030 nucleo-f070 nucleo-f091 nucleo-f302 nucleo-f303 nucleo-f334 \ - nucleo-f401 nucleo-f410 nucleo-f411 nucleo-l053 nucleo-l073 \ + mulle nrf51dongle nrf6310 nucleo144-f446 nucleo32-f031 nucleo32-f303 \ + nucleo32-l031 nucleo-f030 nucleo-f070 nucleo-f091 nucleo-f302 \ + nucleo-f303 nucleo-f334 nucleo-f401 nucleo-f410 nucleo-f411 nucleo-l053 nucleo-l073 \ nucleo-l1 opencm904 openmote-cc2538 pba-d-01-kw2x pca10000 \ pca10005 remote saml21-xpro samr21-xpro slwstk6220a sodaq-autonomo \ spark-core stm32f0discovery stm32f3discovery stm32f4discovery \