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Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.sof + 6. Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Wed Feb 23 14:50:03 2022 ; +; Revision Name ; Lab_2_Assessment ; +; Top-level Entity Name ; Lab_2_Assessment ; +; Family ; FLEX10KE ; +; Device ; EPF10K30ETC144-1 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Low-voltage mode ; On ; On ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Auto-increment JTAG user code for multiple configuration devices ; On ; On ; +; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------------------------------------------------------+ +; File Name ; ++-------------------------------------------------------------------------------------------------+ +; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.sof ; +; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pof ; ++-------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.sof ; ++----------------+----------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------------------------------------------------------+ +; Device ; EPF10K30ETC144-1 ; +; JTAG usercode ; 0x0000007F ; +; Checksum ; 0x0000C455 ; ++----------------+----------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pof ; ++--------------------+------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+------------------------------------------------------------------------------------------------------+ +; Device ; EPC2 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x02581423 ; +; Compression Ratio ; 1 ; ++--------------------+------------------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition + Info: Processing started: Wed Feb 23 14:50:03 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 198 megabytes + Info: Processing ended: Wed Feb 23 14:50:03 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.done b/Assessments/Lab 2 Assessment/Lab_2_Assessment.done new file mode 100644 index 0000000..780c04f --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.done @@ -0,0 +1 @@ +Wed Feb 23 14:55:07 2022 diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.eda.rpt b/Assessments/Lab 2 Assessment/Lab_2_Assessment.eda.rpt new file mode 100644 index 0000000..2aacfdd --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.eda.rpt @@ -0,0 +1,119 @@ +EDA Netlist Writer report for Lab_2_Assessment +Wed Feb 23 14:50:06 2022 +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. Timing Analysis Settings + 6. Timing Analysis Generated Files + 7. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++--------------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Wed Feb 23 14:50:06 2022 ; +; Revision Name ; Lab_2_Assessment ; +; Top-level Entity Name ; Lab_2_Assessment ; +; Family ; FLEX10KE ; +; Simulation Files Creation ; Successful ; +; Timing Analysis Files Creation ; Successful ; ++--------------------------------+---------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++--------------------------------------------------------------------------------------------+--------------------+ +; Option ; Setting ; ++--------------------------------------------------------------------------------------------+--------------------+ +; Tool Name ; Custom Verilog HDL ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; ++--------------------------------------------------------------------------------------------+--------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------------------------------------------------+ +; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/simulation/custom/Lab_2_Assessment.vo ; +; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/simulation/custom/Lab_2_Assessment_v.sdo ; ++---------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------+ +; Timing Analysis Settings ; ++-------------------------------------+--------------------+ +; Option ; Setting ; ++-------------------------------------+--------------------+ +; Tool Name ; Custom Verilog HDL ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; ++-------------------------------------+--------------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Timing Analysis Generated Files ; ++-----------------------------------------------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------------------------------------------+ +; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/timing/custom/Lab_2_Assessment.vo ; +; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/timing/custom/Lab_2_Assessment_v.sdo ; ++-----------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II EDA Netlist Writer + Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition + Info: Processing started: Wed Feb 23 14:50:06 2022 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +Info: Generated files "Lab_2_Assessment.vo" and "Lab_2_Assessment_v.sdo" in directory "C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/simulation/custom/" for EDA simulation tool +Info: Generated files "Lab_2_Assessment.vo" and "Lab_2_Assessment_v.sdo" in directory "C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/timing/custom/" for EDA timing analysis tool +Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 156 megabytes + Info: Processing ended: Wed Feb 23 14:50:06 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.fit.rpt b/Assessments/Lab 2 Assessment/Lab_2_Assessment.fit.rpt new file mode 100644 index 0000000..887efaa --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.fit.rpt @@ -0,0 +1,535 @@ +Fitter report for Lab_2_Assessment +Wed Feb 23 14:50:02 2022 +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Fitter Device Options + 5. Input Pins + 6. Output Pins + 7. All Package Pins + 8. Control Signals + 9. Global & Other Fast Signals + 10. Non-Global High Fan-Out Signals + 11. LAB + 12. Local Routing Interconnect + 13. LAB External Interconnect + 14. Row Interconnect + 15. LAB Column Interconnect + 16. LAB Column Interconnect + 17. Fitter Resource Usage Summary + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pin-Out File + 21. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+-----------------------------------------+ +; Fitter Status ; Successful - Wed Feb 23 14:50:02 2022 ; +; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ; +; Revision Name ; Lab_2_Assessment ; +; Top-level Entity Name ; Lab_2_Assessment ; +; Family ; FLEX10KE ; +; Device ; EPF10K30ETC144-1 ; +; Timing Models ; Final ; +; Total logic elements ; 4 / 1,728 ( < 1 % ) ; +; Total pins ; 10 / 102 ( 10 % ) ; +; Total memory bits ; 0 / 24,576 ( 0 % ) ; +; Total PLLs ; 0 ; ++-----------------------+-----------------------------------------+ + + ++------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------+--------------------+--------------------+ +; Device ; AUTO ; ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Logic Cell Insertion - Individual Logic Cells ; On ; On ; +; Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains ; On ; On ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Auto Global Clock ; On ; On ; +; Auto Global Output Enable ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; ++------------------------------------------------------------+--------------------+--------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; nWS, nRS, nCS, CS ; Unreserved ; +; RDYnBUSY ; Unreserved ; +; Data[7..1] ; Unreserved ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+ +; Name ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; I/O Standard ; ++-------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+ +; d[0] ; 124 ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; load ; 126 ; -- ; -- ; 4 ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; clock ; 55 ; -- ; -- ; 4 ; yes ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; d[1] ; 54 ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; d[2] ; 56 ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; d[3] ; 125 ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; ++-------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+ +; Name ; Pin # ; Row ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ; ++------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+ +; q[0] ; 18 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; q[1] ; 97 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; q[2] ; 96 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; +; q[3] ; 95 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ; ++------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+ + + ++-----------------------------------+ +; All Package Pins ; ++-------+------------+--------------+ +; Pin # ; Usage ; I/O Standard ; ++-------+------------+--------------+ +; 1 ; #TCK ; ; +; 2 ; ^CONF_DONE ; ; +; 3 ; ^nCEO ; ; +; 4 ; #TDO ; ; +; 5 ; VCC_IO ; ; +; 6 ; VCC_INT ; ; +; 7 ; GND* ; ; +; 8 ; GND* ; ; +; 9 ; GND* ; ; +; 10 ; GND* ; ; +; 11 ; GND* ; ; +; 12 ; GND* ; ; +; 13 ; GND* ; ; +; 14 ; GND* ; ; +; 15 ; GND_INT ; ; +; 16 ; GND_INT ; ; +; 17 ; GND* ; ; +; 18 ; q[0] ; LVTTL/LVCMOS ; +; 19 ; GND* ; ; +; 20 ; GND* ; ; +; 21 ; GND* ; ; +; 22 ; GND* ; ; +; 23 ; GND* ; ; +; 24 ; VCC_IO ; ; +; 25 ; VCC_INT ; ; +; 26 ; GND* ; ; +; 27 ; GND* ; ; +; 28 ; GND* ; ; +; 29 ; GND* ; ; +; 30 ; GND* ; ; +; 31 ; GND* ; ; +; 32 ; GND* ; ; +; 33 ; GND* ; ; +; 34 ; #TMS ; ; +; 35 ; ^nSTATUS ; ; +; 36 ; GND* ; ; +; 37 ; GND* ; ; +; 38 ; GND* ; ; +; 39 ; GND* ; ; +; 40 ; GND_INT ; ; +; 41 ; GND* ; ; +; 42 ; GND* ; ; +; 43 ; GND* ; ; +; 44 ; GND* ; ; +; 45 ; VCC_IO ; ; +; 46 ; GND* ; ; +; 47 ; GND* ; ; +; 48 ; GND* ; ; +; 49 ; GND* ; ; +; 50 ; GND_INT ; ; +; 51 ; GND* ; ; +; 52 ; VCC_INT ; ; +; 53 ; VCC_CKLK ; ; +; 54 ; d[1] ; LVTTL/LVCMOS ; +; 55 ; clock ; LVTTL/LVCMOS ; +; 56 ; d[2] ; LVTTL/LVCMOS ; +; 57 ; GND_CKLK ; ; +; 58 ; GND_INT ; ; +; 59 ; GND* ; ; +; 60 ; GND* ; ; +; 61 ; VCC_IO ; ; +; 62 ; GND* ; ; +; 63 ; GND* ; ; +; 64 ; GND* ; ; +; 65 ; GND* ; ; +; 66 ; GND_INT ; ; +; 67 ; GND* ; ; +; 68 ; GND* ; ; +; 69 ; GND* ; ; +; 70 ; GND* ; ; +; 71 ; VCC_IO ; ; +; 72 ; GND* ; ; +; 73 ; GND* ; ; +; 74 ; ^nCONFIG ; ; +; 75 ; VCC_INT ; ; +; 76 ; ^MSEL1 ; ; +; 77 ; ^MSEL0 ; ; +; 78 ; GND* ; ; +; 79 ; GND* ; ; +; 80 ; GND* ; ; +; 81 ; GND* ; ; +; 82 ; GND* ; ; +; 83 ; GND* ; ; +; 84 ; GND_INT ; ; +; 85 ; GND_INT ; ; +; 86 ; GND* ; ; +; 87 ; GND* ; ; +; 88 ; GND* ; ; +; 89 ; GND* ; ; +; 90 ; GND* ; ; +; 91 ; GND* ; ; +; 92 ; GND* ; ; +; 93 ; VCC_INT ; ; +; 94 ; VCC_IO ; ; +; 95 ; q[3] ; LVTTL/LVCMOS ; +; 96 ; q[2] ; LVTTL/LVCMOS ; +; 97 ; q[1] ; LVTTL/LVCMOS ; +; 98 ; GND* ; ; +; 99 ; GND* ; ; +; 100 ; GND* ; ; +; 101 ; GND* ; ; +; 102 ; GND* ; ; +; 103 ; GND_INT ; ; +; 104 ; GND_INT ; ; +; 105 ; #TDI ; ; +; 106 ; ^nCE ; ; +; 107 ; ^DCLK ; ; +; 108 ; ^DATA0 ; ; +; 109 ; GND* ; ; +; 110 ; GND* ; ; +; 111 ; GND* ; ; +; 112 ; GND* ; ; +; 113 ; GND* ; ; +; 114 ; GND* ; ; +; 115 ; VCC_IO ; ; +; 116 ; GND* ; ; +; 117 ; GND* ; ; +; 118 ; GND* ; ; +; 119 ; GND* ; ; +; 120 ; GND* ; ; +; 121 ; GND* ; ; +; 122 ; GND* ; ; +; 123 ; VCC_INT ; ; +; 124 ; d[0] ; LVTTL/LVCMOS ; +; 125 ; d[3] ; LVTTL/LVCMOS ; +; 126 ; load ; LVTTL/LVCMOS ; +; 127 ; GND_INT ; ; +; 128 ; GND* ; ; +; 129 ; GND_INT ; ; +; 130 ; GND* ; ; +; 131 ; GND* ; ; +; 132 ; GND* ; ; +; 133 ; GND* ; ; +; 134 ; VCC_IO ; ; +; 135 ; GND* ; ; +; 136 ; GND* ; ; +; 137 ; GND* ; ; +; 138 ; GND* ; ; +; 139 ; GND_INT ; ; +; 140 ; GND* ; ; +; 141 ; GND* ; ; +; 142 ; GND* ; ; +; 143 ; GND* ; ; +; 144 ; GND* ; ; ++-------+------------+--------------+ + + ++------------------------------------------------+ +; Control Signals ; ++-------+-------+---------+-------+--------------+ +; Name ; Pin # ; Fan-Out ; Usage ; Global Usage ; ++-------+-------+---------+-------+--------------+ +; clock ; 55 ; 4 ; Clock ; Pin ; ++-------+-------+---------+-------+--------------+ + + ++----------------------------------+ +; Global & Other Fast Signals ; ++-------+-------+---------+--------+ +; Name ; Pin # ; Fan-Out ; Global ; ++-------+-------+---------+--------+ +; d[0] ; 124 ; 1 ; no ; +; load ; 126 ; 4 ; no ; +; clock ; 55 ; 4 ; yes ; +; d[1] ; 54 ; 1 ; no ; +; d[2] ; 56 ; 1 ; no ; +; d[3] ; 125 ; 1 ; no ; ++-------+-------+---------+--------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------+-----------------------+ +; Name ; Fan-Out ; ++---------+-----------------------+ +; load ; 4 ; +; q[0]~20 ; 2 ; +; q[2]~22 ; 2 ; +; q[1]~21 ; 2 ; +; q[3]~23 ; 2 ; +; d[1] ; 1 ; +; d[3] ; 1 ; +; d[0] ; 1 ; +; d[2] ; 1 ; ++---------+-----------------------+ + + ++-------------------------------------------+ +; LAB ; ++--------------------------+----------------+ +; Number of Logic Elements ; Number of LABs ; ++--------------------------+----------------+ +; 0 ; 215 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++--------------------------+----------------+ + + ++----------------------------------------------+ +; Local Routing Interconnect ; ++-----------------------------+----------------+ +; Local Routing Interconnects ; Number of LABs ; ++-----------------------------+----------------+ +; 0 ; 215 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++-----------------------------+----------------+ + + ++---------------------------------------------+ +; LAB External Interconnect ; ++----------------------------+----------------+ +; LAB External Interconnects ; Number of LABs ; ++----------------------------+----------------+ +; 0 ; 215 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; ++----------------------------+----------------+ + + ++-----------------------------------------------------------------------------------------+ +; Row Interconnect ; ++-------+--------------------+-----------------------------+------------------------------+ +; Row ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ; ++-------+--------------------+-----------------------------+------------------------------+ +; A ; 0 / 144 ( 0 % ) ; 0 / 72 ( 0 % ) ; 0 / 72 ( 0 % ) ; +; B ; 0 / 144 ( 0 % ) ; 0 / 72 ( 0 % ) ; 0 / 72 ( 0 % ) ; +; C ; 1 / 144 ( < 1 % ) ; 3 / 72 ( 4 % ) ; 0 / 72 ( 0 % ) ; +; D ; 0 / 144 ( 0 % ) ; 0 / 72 ( 0 % ) ; 0 / 72 ( 0 % ) ; +; E ; 0 / 144 ( 0 % ) ; 0 / 72 ( 0 % ) ; 0 / 72 ( 0 % ) ; +; F ; 0 / 144 ( 0 % ) ; 0 / 72 ( 0 % ) ; 0 / 72 ( 0 % ) ; +; Total ; 1 / 864 ( < 1 % ) ; 3 / 432 ( < 1 % ) ; 0 / 432 ( 0 % ) ; ++-------+--------------------+-----------------------------+------------------------------+ + + ++---------------------------+ +; LAB Column Interconnect ; ++-------+-------------------+ +; Col. ; Interconnect Used ; ++-------+-------------------+ +; 1 ; 0 / 24 ( 0 % ) ; +; 2 ; 0 / 24 ( 0 % ) ; +; 3 ; 0 / 24 ( 0 % ) ; +; 4 ; 0 / 24 ( 0 % ) ; +; 5 ; 0 / 24 ( 0 % ) ; +; 6 ; 0 / 24 ( 0 % ) ; +; 7 ; 0 / 24 ( 0 % ) ; +; 8 ; 0 / 24 ( 0 % ) ; +; 9 ; 0 / 24 ( 0 % ) ; +; 10 ; 0 / 24 ( 0 % ) ; +; 11 ; 0 / 24 ( 0 % ) ; +; 12 ; 0 / 24 ( 0 % ) ; +; 13 ; 0 / 24 ( 0 % ) ; +; 14 ; 0 / 24 ( 0 % ) ; +; 15 ; 0 / 24 ( 0 % ) ; +; 16 ; 0 / 24 ( 0 % ) ; +; 17 ; 0 / 24 ( 0 % ) ; +; 18 ; 0 / 24 ( 0 % ) ; +; 19 ; 0 / 24 ( 0 % ) ; +; 20 ; 0 / 24 ( 0 % ) ; +; 21 ; 0 / 24 ( 0 % ) ; +; 22 ; 0 / 24 ( 0 % ) ; +; 23 ; 0 / 24 ( 0 % ) ; +; 24 ; 0 / 24 ( 0 % ) ; +; 25 ; 0 / 24 ( 0 % ) ; +; 26 ; 0 / 24 ( 0 % ) ; +; 27 ; 0 / 24 ( 0 % ) ; +; 28 ; 0 / 24 ( 0 % ) ; +; 29 ; 0 / 24 ( 0 % ) ; +; 30 ; 0 / 24 ( 0 % ) ; +; 31 ; 0 / 24 ( 0 % ) ; +; 32 ; 0 / 24 ( 0 % ) ; +; 33 ; 0 / 24 ( 0 % ) ; +; 34 ; 0 / 24 ( 0 % ) ; +; 35 ; 0 / 24 ( 0 % ) ; +; 36 ; 0 / 24 ( 0 % ) ; +; Total ; 0 / 864 ( 0 % ) ; ++-------+-------------------+ + + ++---------------------------+ +; LAB Column Interconnect ; ++-------+-------------------+ +; Col. ; Interconnect Used ; ++-------+-------------------+ +; 1 ; 0 / 48 ( 0 % ) ; +; Total ; 0 / 48 ( 0 % ) ; ++-------+-------------------+ + + ++---------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-----------------------------------+---------------------+ +; Resource ; Usage ; ++-----------------------------------+---------------------+ +; Total logic elements ; 4 / 1,728 ( < 1 % ) ; +; Registers ; 4 / 1,728 ( < 1 % ) ; +; Logic elements in carry chains ; 0 ; +; User inserted logic elements ; 0 ; +; I/O pins ; 10 / 102 ( 10 % ) ; +; -- Clock pins ; 2 ; +; -- Dedicated input pins ; 4 / 4 ( 100 % ) ; +; Global signals ; 1 ; +; EABs ; 0 / 6 ( 0 % ) ; +; Total memory bits ; 0 / 24,576 ( 0 % ) ; +; Total RAM block bits ; 0 / 24,576 ( 0 % ) ; +; Maximum fan-out node ; load ; +; Maximum fan-out ; 4 ; +; Highest non-global fan-out signal ; load ; +; Highest non-global fan-out ; 4 ; +; Total fan-out ; 20 ; +; Average fan-out ; 1.43 ; ++-----------------------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; |Lab_2_Assessment ; 4 (4) ; 4 ; 0 ; 10 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |Lab_2_Assessment ; work ; ++----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------+ +; Delay Chain Summary ; ++-------+----------+-------------+ +; Name ; Pin Type ; Pad to Core ; ++-------+----------+-------------+ +; d[0] ; Input ; OFF ; +; load ; Input ; OFF ; +; clock ; Input ; OFF ; +; d[1] ; Input ; OFF ; +; d[2] ; Input ; OFF ; +; d[3] ; Input ; ON ; +; q[0] ; Output ; OFF ; +; q[1] ; Output ; OFF ; +; q[2] ; Output ; OFF ; +; q[3] ; Output ; OFF ; ++-------+----------+-------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.pin. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition + Info: Processing started: Wed Feb 23 14:50:01 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +Info: Automatically selected device EPF10K30ETC144-1 for design Lab_2_Assessment +Warning: Feature SignalProbe is not available with your current license +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements + Info: Assuming a global fmax requirement of 1000 MHz + Info: Not setting a global tsu requirement + Info: Not setting a global tco requirement + Info: Not setting a global tpd requirement +Info: Inserted 0 logic cells in first fitting attempt +Info: Started fitting attempt 1 on Wed Feb 23 2022 at 14:50:01 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: Quartus II Fitter was successful. 0 errors, 1 warning + Info: Peak virtual memory: 224 megabytes + Info: Processing ended: Wed Feb 23 14:50:02 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.fit.summary b/Assessments/Lab 2 Assessment/Lab_2_Assessment.fit.summary new file mode 100644 index 0000000..390b188 --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.fit.summary @@ -0,0 +1,11 @@ +Fitter Status : Successful - Wed Feb 23 14:50:02 2022 +Quartus II Version : 8.1 Build 163 10/28/2008 SJ Web Edition +Revision Name : Lab_2_Assessment +Top-level Entity Name : Lab_2_Assessment +Family : FLEX10KE +Device : EPF10K30ETC144-1 +Timing Models : Final +Total logic elements : 4 / 1,728 ( < 1 % ) +Total pins : 10 / 102 ( 10 % ) +Total memory bits : 0 / 24,576 ( 0 % ) +Total PLLs : 0 diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.flow.rpt b/Assessments/Lab 2 Assessment/Lab_2_Assessment.flow.rpt new file mode 100644 index 0000000..37f1304 --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.flow.rpt @@ -0,0 +1,122 @@ +Flow report for Lab_2_Assessment +Wed Feb 23 14:50:06 2022 +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; Flow Summary ; ++-------------------------+-----------------------------------------+ +; Flow Status ; Successful - Wed Feb 23 14:50:06 2022 ; +; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ; +; Revision Name ; Lab_2_Assessment ; +; Top-level Entity Name ; Lab_2_Assessment ; +; Family ; FLEX10KE ; +; Met timing requirements ; Yes ; +; Total logic elements ; 4 / 1,728 ( < 1 % ) ; +; Total pins ; 10 / 102 ( 10 % ) ; +; Total memory bits ; 0 / 24,576 ( 0 % ) ; +; Total PLLs ; 0 ; +; Device ; EPF10K30ETC144-1 ; +; Timing Models ; Final ; ++-------------------------+-----------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 02/23/2022 14:50:00 ; +; Main task ; Compilation ; +; Revision Name ; Lab_2_Assessment ; ++-------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+--------------------------------+---------------+-------------+----------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+--------------------------------+---------------+-------------+----------------------+ +; COMPILER_SIGNATURE_ID ; 66120944015010.164560620008100 ; -- ; -- ; -- ; +; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Custom ; ; -- ; -- ; +; EDA_INPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_design_synthesis ; +; EDA_NETLIST_WRITER_OUTPUT_DIR ; timing/custom ; -- ; -- ; eda_timing_analysis ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog ; -- ; -- ; eda_timing_analysis ; +; EDA_SIMULATION_TOOL ; Custom Verilog HDL ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; EDA_TIMING_ANALYSIS_TOOL ; Custom Verilog HDL ; ; -- ; -- ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+--------------------------------+---------------+-------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 214 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 202 MB ; 00:00:01 ; +; Assembler ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 165 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 150 MB ; 00:00:00 ; +; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-BO7TTK2 ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; DESKTOP-BO7TTK2 ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; DESKTOP-BO7TTK2 ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; DESKTOP-BO7TTK2 ; Windows Vista ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; DESKTOP-BO7TTK2 ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +quartus_fit --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +quartus_asm --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +quartus_tan --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +quartus_eda --read_settings_files=off --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment + + + diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.map.rpt b/Assessments/Lab 2 Assessment/Lab_2_Assessment.map.rpt new file mode 100644 index 0000000..a974311 --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.map.rpt @@ -0,0 +1,197 @@ +Analysis & Synthesis report for Lab_2_Assessment +Wed Feb 23 14:50:00 2022 +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+-----------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Feb 23 14:50:00 2022 ; +; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ; +; Revision Name ; Lab_2_Assessment ; +; Top-level Entity Name ; Lab_2_Assessment ; +; Family ; FLEX10KE ; +; Total logic elements ; 4 ; +; Total pins ; 10 ; +; Total memory bits ; 0 ; +; Total PLLs ; 0 ; ++-----------------------------+-----------------------------------------+ + + ++------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------+------------------+------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------+------------------+------------------+ +; Top-level entity name ; Lab_2_Assessment ; Lab_2_Assessment ; +; Family name ; FLEX10KE ; Stratix II ; +; Type of Retiming Performed During Resynthesis ; Full ; ; +; Resynthesis Optimization Effort ; Normal ; ; +; Physical Synthesis Level for Resynthesis ; Normal ; ; +; Use Generated Physical Constraints File ; On ; ; +; Use smart compilation ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Auto Implement in ROM ; Off ; Off ; +; Optimization Technique ; Area ; Area ; +; Carry Chain Length ; 32 ; 32 ; +; Cascade Chain Length ; 2 ; 2 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++----------------------------------------------------------------+------------------+------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------+ +; Lab_2_Assessment.v ; yes ; User Verilog HDL File ; C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.v ; ++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------+ + + ++---------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++--------------------------------+------------+ +; Resource ; Usage ; ++--------------------------------+------------+ +; Total logic elements ; 4 ; +; Total combinational functions ; 4 ; +; -- Total 4-input functions ; 0 ; +; -- Total 3-input functions ; 4 ; +; -- Total 2-input functions ; 0 ; +; -- Total 1-input functions ; 0 ; +; -- Total 0-input functions ; 0 ; +; Total registers ; 4 ; +; I/O pins ; 10 ; +; Maximum fan-out node ; load ; +; Maximum fan-out ; 4 ; +; Total fan-out ; 20 ; +; Average fan-out ; 1.43 ; ++--------------------------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; |Lab_2_Assessment ; 4 (4) ; 4 ; 0 ; 10 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |Lab_2_Assessment ; work ; ++----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 4 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition + Info: Processing started: Wed Feb 23 14:49:59 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +Info: Found 1 design units, including 1 entities, in source file Lab_2_Assessment.v + Info: Found entity 1: Lab_2_Assessment +Warning: EDA synthesis tool is specified as "Custom", but Library Mapping File is not specified +Warning: EDA synthesis tool is specified as "Custom", but VCC is not specified +Warning: EDA synthesis tool is specified as "Custom", but GND is not specified +Info: Elaborating entity "Lab_2_Assessment" for the top level hierarchy +Info: Implemented 14 device resources after synthesis - the final resource count might be different + Info: Implemented 6 input pins + Info: Implemented 4 output pins + Info: Implemented 4 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 214 megabytes + Info: Processing ended: Wed Feb 23 14:50:00 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.map.summary b/Assessments/Lab 2 Assessment/Lab_2_Assessment.map.summary new file mode 100644 index 0000000..86607dd --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.map.summary @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Wed Feb 23 14:50:00 2022 +Quartus II Version : 8.1 Build 163 10/28/2008 SJ Web Edition +Revision Name : Lab_2_Assessment +Top-level Entity Name : Lab_2_Assessment +Family : FLEX10KE +Total logic elements : 4 +Total pins : 10 +Total memory bits : 0 +Total PLLs : 0 diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.pin b/Assessments/Lab 2 Assessment/Lab_2_Assessment.pin new file mode 100644 index 0000000..6ab98b0 --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.pin @@ -0,0 +1,187 @@ + -- Copyright (C) 1991-2008 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + ------------------------------------------------------------------------------ + + + + ------------------------------------------------------------------------------ + -- NC : No Connect. This pin has no internal connection to the device. + -- VCC_INT : Dedicated power pin, which MUST be connected to VCC (2.5V). + -- VCC_IO : Dedicated power pin, which MUST be connected to VCC (Refer to + -- the table below for voltage). + -- GND : Dedicated ground pin, which MUST be connected to GND. + -- GND+ : Unused input. This pin should be connected to GND. It may also + -- be connected to a valid signal on the board (low, high, or + -- toggling) if that signal is required for a different revision + -- of the design. + -- GND* : Unused I/O pin. This pin can either be left unconnected or + -- connected to GND. Connecting this pin to GND will improve the + -- device's immunity to noise. + ------------------------------------------------------------------------------ + + +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition +CHIP "Lab_2_Assessment" ASSIGNED TO AN: EPF10K30ETC144-1 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +TCK : 1 : input : : : : +CONF_DONE : 2 : bidir : : : : +nCEO : 3 : output : : : : +TDO : 4 : output : : : : +VCC_IO : 5 : power : : 3.3V : : +VCC_INT : 6 : power : : 2.5V : : +GND* : 7 : : : : : +GND* : 8 : : : : : +GND* : 9 : : : : : +GND* : 10 : : : : : +GND* : 11 : : : : : +GND* : 12 : : : : : +GND* : 13 : : : : : +GND* : 14 : : : : : +GND_INT : 15 : gnd : : : : +GND_INT : 16 : gnd : : : : +GND* : 17 : : : : : +q[0] : 18 : output : LVTTL/LVCMOS : : : N +GND* : 19 : : : : : +GND* : 20 : : : : : +GND* : 21 : : : : : +GND* : 22 : : : : : +GND* : 23 : : : : : +VCC_IO : 24 : power : : 3.3V : : +VCC_INT : 25 : power : : 2.5V : : +GND* : 26 : : : : : +GND* : 27 : : : : : +GND* : 28 : : : : : +GND* : 29 : : : : : +GND* : 30 : : : : : +GND* : 31 : : : : : +GND* : 32 : : : : : +GND* : 33 : : : : : +TMS : 34 : input : : : : +nSTATUS : 35 : bidir : : : : +GND* : 36 : : : : : +GND* : 37 : : : : : +GND* : 38 : : : : : +GND* : 39 : : : : : +GND_INT : 40 : gnd : : : : +GND* : 41 : : : : : +GND* : 42 : : : : : +GND* : 43 : : : : : +GND* : 44 : : : : : +VCC_IO : 45 : power : : 3.3V : : +GND* : 46 : : : : : +GND* : 47 : : : : : +GND* : 48 : : : : : +GND* : 49 : : : : : +GND_INT : 50 : gnd : : : : +GND* : 51 : : : : : +VCC_INT : 52 : power : : 2.5V : : +VCC_CKLK : 53 : power : : 2.5V : : +d[1] : 54 : input : LVTTL/LVCMOS : : : N +clock : 55 : input : LVTTL/LVCMOS : : : N +d[2] : 56 : input : LVTTL/LVCMOS : : : N +GND_CKLK : 57 : gnd : : : : +GND_INT : 58 : gnd : : : : +GND* : 59 : : : : : +GND* : 60 : : : : : +VCC_IO : 61 : power : : 3.3V : : +GND* : 62 : : : : : +GND* : 63 : : : : : +GND* : 64 : : : : : +GND* : 65 : : : : : +GND_INT : 66 : gnd : : : : +GND* : 67 : : : : : +GND* : 68 : : : : : +GND* : 69 : : : : : +GND* : 70 : : : : : +VCC_IO : 71 : power : : 3.3V : : +GND* : 72 : : : : : +GND* : 73 : : : : : +nCONFIG : 74 : input : : : : +VCC_INT : 75 : power : : 2.5V : : +MSEL1 : 76 : input : : : : +MSEL0 : 77 : input : : : : +GND* : 78 : : : : : +GND* : 79 : : : : : +GND* : 80 : : : : : +GND* : 81 : : : : : +GND* : 82 : : : : : +GND* : 83 : : : : : +GND_INT : 84 : gnd : : : : +GND_INT : 85 : gnd : : : : +GND* : 86 : : : : : +GND* : 87 : : : : : +GND* : 88 : : : : : +GND* : 89 : : : : : +GND* : 90 : : : : : +GND* : 91 : : : : : +GND* : 92 : : : : : +VCC_INT : 93 : power : : 2.5V : : +VCC_IO : 94 : power : : 3.3V : : +q[3] : 95 : output : LVTTL/LVCMOS : : : N +q[2] : 96 : output : LVTTL/LVCMOS : : : N +q[1] : 97 : output : LVTTL/LVCMOS : : : N +GND* : 98 : : : : : +GND* : 99 : : : : : +GND* : 100 : : : : : +GND* : 101 : : : : : +GND* : 102 : : : : : +GND_INT : 103 : gnd : : : : +GND_INT : 104 : gnd : : : : +TDI : 105 : input : : : : +nCE : 106 : input : : : : +DCLK : 107 : bidir : : : : +DATA0 : 108 : input : : : : +GND* : 109 : : : : : +GND* : 110 : : : : : +GND* : 111 : : : : : +GND* : 112 : : : : : +GND* : 113 : : : : : +GND* : 114 : : : : : +VCC_IO : 115 : power : : 3.3V : : +GND* : 116 : : : : : +GND* : 117 : : : : : +GND* : 118 : : : : : +GND* : 119 : : : : : +GND* : 120 : : : : : +GND* : 121 : : : : : +GND* : 122 : : : : : +VCC_INT : 123 : power : : 2.5V : : +d[0] : 124 : input : LVTTL/LVCMOS : : : N +d[3] : 125 : input : LVTTL/LVCMOS : : : N +load : 126 : input : LVTTL/LVCMOS : : : N +GND_INT : 127 : gnd : : : : +GND* : 128 : : : : : +GND_INT : 129 : gnd : : : : +GND* : 130 : : : : : +GND* : 131 : : : : : +GND* : 132 : : : : : +GND* : 133 : : : : : +VCC_IO : 134 : power : : 3.3V : : +GND* : 135 : : : : : +GND* : 136 : : : : : +GND* : 137 : : : : : +GND* : 138 : : : : : +GND_INT : 139 : gnd : : : : +GND* : 140 : : : : : +GND* : 141 : : : : : +GND* : 142 : : : : : +GND* : 143 : : : : : +GND* : 144 : : : : : diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.qpf b/Assessments/Lab 2 Assessment/Lab_2_Assessment.qpf new file mode 100644 index 0000000..a8bfcfd --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "8.1" +DATE = "14:42:47 February 23, 2022" + + +# Revisions + +PROJECT_REVISION = "Lab_2_Assessment" diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.qsf b/Assessments/Lab 2 Assessment/Lab_2_Assessment.qsf new file mode 100644 index 0000000..157b527 --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.qsf @@ -0,0 +1,43 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# Lab_2_Assessment_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY FLEX10KE +set_global_assignment -name DEVICE AUTO +set_global_assignment -name TOP_LEVEL_ENTITY Lab_2_Assessment +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:42:47 FEBRUARY 23, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION 8.1 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL Custom +set_global_assignment -name EDA_INPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "Custom Verilog HDL" +set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR timing/custom -section_id eda_timing_analysis +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_timing_analysis +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name VERILOG_FILE Lab_2_Assessment.v +set_global_assignment -name SIMULATION_MODE FUNCTIONAL +set_global_assignment -name VECTOR_WAVEFORM_FILE Lab_2_Assessment.vwf \ No newline at end of file diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.qws b/Assessments/Lab 2 Assessment/Lab_2_Assessment.qws new file mode 100644 index 0000000..f74cf7f --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.qws @@ -0,0 +1,16 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=Lab_2_Assessment.v +DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/Assessments/Lab 2 Assessment/Lab_2_Assessment.sim.rpt b/Assessments/Lab 2 Assessment/Lab_2_Assessment.sim.rpt new file mode 100644 index 0000000..903e066 --- /dev/null +++ b/Assessments/Lab 2 Assessment/Lab_2_Assessment.sim.rpt @@ -0,0 +1,182 @@ +Simulator report for Lab_2_Assessment +Wed Feb 23 14:55:07 2022 +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Simulator Summary + 3. Simulator Settings + 4. Simulation Waveforms + 5. Coverage Summary + 6. Complete 1/0-Value Coverage + 7. Missing 1-Value Coverage + 8. Missing 0-Value Coverage + 9. Simulator INI Usage + 10. Simulator Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------+ +; Simulator Summary ; ++-----------------------------+--------------+ +; Type ; Value ; ++-----------------------------+--------------+ +; Simulation Start Time ; 0 ps ; +; Simulation End Time ; 80.0 ns ; +; Simulation Netlist Size ; 18 nodes ; +; Simulation Coverage ; 72.22 % ; +; Total Number of Transitions ; 64 ; +; Simulation Breakpoints ; 0 ; +; Family ; FLEX10KE ; ++-----------------------------+--------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Simulator Settings ; ++--------------------------------------------------------------------------------------------+------------+---------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------------------------------+------------+---------------+ +; Simulation mode ; Functional ; Timing ; +; Start time ; 0 ns ; 0 ns ; +; Simulation results format ; CVWF ; ; +; Add pins automatically to simulation output waveforms ; On ; On ; +; Check outputs ; Off ; Off ; +; Report simulation coverage ; On ; On ; +; Display complete 1/0 value coverage report ; On ; On ; +; Display missing 1-value coverage report ; On ; On ; +; Display missing 0-value coverage report ; On ; On ; +; Detect setup and hold time violations ; Off ; Off ; +; Detect glitches ; Off ; Off ; +; Disable timing delays in Timing Simulation ; Off ; Off ; +; Generate Signal Activity File ; Off ; Off ; +; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ; +; Group bus channels in simulation results ; Off ; Off ; +; Preserve fewer signal transitions to reduce memory requirements ; On ; On ; +; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ; +; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ; +; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ; +; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ; ++--------------------------------------------------------------------------------------------+------------+---------------+ + + ++----------------------+ +; Simulation Waveforms ; ++----------------------+ +Waveform report data cannot be output to ASCII. +Please use Quartus II to view the waveform report data. + + ++--------------------------------------------------------------------+ +; Coverage Summary ; ++-----------------------------------------------------+--------------+ +; Type ; Value ; ++-----------------------------------------------------+--------------+ +; Total coverage as a percentage ; 72.22 % ; +; Total nodes checked ; 18 ; +; Total output ports checked ; 18 ; +; Total output ports with complete 1/0-value coverage ; 13 ; +; Total output ports with no 1/0-value coverage ; 4 ; +; Total output ports with no 1-value coverage ; 5 ; +; Total output ports with no 0-value coverage ; 4 ; ++-----------------------------------------------------+--------------+ + + +The following table displays output ports that toggle between 1 and 0 during simulation. ++------------------------------------------------------------------------------+ +; Complete 1/0-Value Coverage ; ++-----------------------------+-----------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++-----------------------------+-----------------------------+------------------+ +; |Lab_2_Assessment|q[0]~reg0 ; |Lab_2_Assessment|q[0]~reg0 ; regout ; +; |Lab_2_Assessment|q~0 ; |Lab_2_Assessment|q~0 ; out ; +; |Lab_2_Assessment|q~1 ; |Lab_2_Assessment|q~1 ; out ; +; |Lab_2_Assessment|q~2 ; |Lab_2_Assessment|q~2 ; out ; +; |Lab_2_Assessment|q~3 ; |Lab_2_Assessment|q~3 ; out ; +; |Lab_2_Assessment|q[1]~reg0 ; |Lab_2_Assessment|q[1]~reg0 ; regout ; +; |Lab_2_Assessment|q[2]~reg0 ; |Lab_2_Assessment|q[2]~reg0 ; regout ; +; |Lab_2_Assessment|q[3]~reg0 ; |Lab_2_Assessment|q[3]~reg0 ; regout ; +; |Lab_2_Assessment|q[0] ; |Lab_2_Assessment|q[0] ; pin_out ; +; |Lab_2_Assessment|q[1] ; |Lab_2_Assessment|q[1] ; pin_out ; +; |Lab_2_Assessment|q[2] ; |Lab_2_Assessment|q[2] ; pin_out ; +; |Lab_2_Assessment|q[3] ; |Lab_2_Assessment|q[3] ; pin_out ; +; |Lab_2_Assessment|clock ; |Lab_2_Assessment|clock ; out ; ++-----------------------------+-----------------------------+------------------+ + + +The following table displays output ports that do not toggle to 1 during simulation. ++--------------------------------------------------------------------+ +; Missing 1-Value Coverage ; ++------------------------+------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++------------------------+------------------------+------------------+ +; |Lab_2_Assessment|d[0] ; |Lab_2_Assessment|d[0] ; out ; +; |Lab_2_Assessment|d[1] ; |Lab_2_Assessment|d[1] ; out ; +; |Lab_2_Assessment|d[2] ; |Lab_2_Assessment|d[2] ; out ; +; |Lab_2_Assessment|d[3] ; |Lab_2_Assessment|d[3] ; out ; +; |Lab_2_Assessment|load ; |Lab_2_Assessment|load ; out ; ++------------------------+------------------------+------------------+ + + +The following table displays output ports that do not toggle to 0 during simulation. ++--------------------------------------------------------------------+ +; Missing 0-Value Coverage ; ++------------------------+------------------------+------------------+ +; Node Name ; Output Port Name ; Output Port Type ; ++------------------------+------------------------+------------------+ +; |Lab_2_Assessment|d[0] ; |Lab_2_Assessment|d[0] ; out ; +; |Lab_2_Assessment|d[1] ; |Lab_2_Assessment|d[1] ; out ; +; |Lab_2_Assessment|d[2] ; |Lab_2_Assessment|d[2] ; out ; +; |Lab_2_Assessment|d[3] ; |Lab_2_Assessment|d[3] ; out ; ++------------------------+------------------------+------------------+ + + ++---------------------+ +; Simulator INI Usage ; ++--------+------------+ +; Option ; Usage ; ++--------+------------+ + + ++--------------------+ +; Simulator Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Simulator + Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition + Info: Processing started: Wed Feb 23 14:55:06 2022 +Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment +Info: Using vector source file "C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.vwf" +Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled + Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. 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File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 80.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clock") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("d") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("d[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "d"; +} + +SIGNAL("d[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "d"; +} + +SIGNAL("d[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "d"; +} + +SIGNAL("d[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "d"; +} + +SIGNAL("load") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("q") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("q[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "q"; +} + +SIGNAL("q[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "q"; +} + +SIGNAL("q[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "q"; +} + +SIGNAL("q[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "q"; +} + +TRANSITION_LIST("clock") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 8; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("d[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + } +} + +TRANSITION_LIST("d[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + } +} + +TRANSITION_LIST("d[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + } +} + +TRANSITION_LIST("d[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + } +} + +TRANSITION_LIST("load") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 70.0; + } +} + +TRANSITION_LIST("q[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 80.0; + } +} + +TRANSITION_LIST("q[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 80.0; + } +} + +TRANSITION_LIST("q[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 80.0; + } +} + +TRANSITION_LIST("q[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 80.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clock"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "d"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 1; + TREE_LEVEL = 0; + CHILDREN = 2, 3, 4, 5; +} + +DISPLAY_LINE +{ + CHANNEL = "d[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "d[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "d[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "d[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "load"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "q"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 7; + TREE_LEVEL = 0; + CHILDREN = 8, 9, 10, 11; +} + +DISPLAY_LINE +{ + CHANNEL = "q[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 7; +} + +DISPLAY_LINE +{ + CHANNEL = "q[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 7; +} + +DISPLAY_LINE +{ + CHANNEL = "q[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 7; +} + +DISPLAY_LINE +{ + CHANNEL = "q[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 7; +} + +TIME_BAR +{ + TIME = 12725; + MASTER = TRUE; +} +; diff --git a/Assessments/Lab 2 Assessment/db/Lab_2_Assessment.(0).cnf.cdb b/Assessments/Lab 2 Assessment/db/Lab_2_Assessment.(0).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..506abdcea76a63a4cb964cd461739bb9a7746b9c GIT binary patch literal 1014 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Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 23 14:49:59 2022 " "Info: Processing started: Wed Feb 23 14:49:59 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab_2_Assessment -c Lab_2_Assessment" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "Lab_2_Assessment.v(7) " "Warning (10268): Verilog HDL information at Lab_2_Assessment.v(7): always construct contains both blocking and non-blocking assignments" { } { { "Lab_2_Assessment.v" "" { Text "C:/Users/rafsa/OneDrive/Documents/CSE460 Labs/Assessments/Lab 2 Assessment/Lab_2_Assessment.v" 7 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct 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