po74g.lib

library(74series) {
    technology("cmos");

    time_unit: "1ns";
    voltage_unit: "1V";
    current_unit: "1mA";
    capacitive_load_unit(1, pf);

    slew_lower_threshold_pct_fall: 30;
    slew_upper_threshold_pct_fall: 30;
    slew_lower_threshold_pct_rise: 70;
    slew_upper_threshold_pct_rise: 70;

    nom_process: 1;
    nom_temperature: 25;
    nom_voltage: 5;

    // 74AC00 quad 2-input NAND gate
    cell(74AC00_4x1NAND2) {
        area: 3;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(Y) { direction: output; function: "(A*B)'"; }
     }

    // 74AC02 quad 2-input NOR gate
    cell(74AC02_4x1NOR2) {
        area: 3;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(Y) { direction: output; function: "(A+B)'"; }
    }

    // 74AC04 hex inverter
    cell(74AC04_6x1NOT) {
        area: 2;
        pin(A) {
           direction: input;
           capacitance: 3.5;
        }
        pin(Y) {
           direction: output;
           capacitance: 0.0;
           max_capacitance: 29.0;
           function: "A'";
           /* timing() {
               timing_type: "combinational";
               timing_sense: "negative_unate";
               related_pin: "A";
               intrinsic_rise: 1.5;
               intrinsic_fall: 1.5;
           } */
        }
    }

    // 74AC08 quad 2-input AND
    cell(74AC08_4x1AND2) {
        area: 3;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(Y) { direction: output; function: "A*B"; }
    }

    // 74AC10 triple 3-input NAND
    cell(74AC10_3x1NAND3) {
        area: 4;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(C) { direction: input; }
        pin(Y) { direction: output; function: "(A*B*C)'"; }
    }

    // 74AC27 triple 3-input NOR
    cell(74AC27_3x1NOR3) {
        area: 4;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(C) { direction: input; }
        pin(Y) { direction: output; function: "(A+B+C)'"; }
    }

    // 74AC32 quad 2-input OR gate
    cell(74AC32_4x1OR2) {
        area: 3;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(Y) { direction: output; function: "(A+B)"; }
    }

    // 74AC74 dual D flip-flop with set and reset
    cell(74AC74_2x1DFFSR) {
        area: 5;
        ff(IQ, IQN) {
           clocked_on: "CLK";
           next_state: "D";
           clear: "C'";
           preset: "P'";
           clear_preset_var1: H;
           clear_preset_var2: H;
        }
        pin(CLK) { direction: input; clock: true; }
        pin(C) { direction: input; }
        pin(P) { direction: input; }
        pin(D) { direction: input; }
        pin(Q) { direction: output; function: "IQ"; }
    }

    // 74AC86 quad 2-input XOR gate
    cell(74AC86_4x1XOR2) {
        area: 3;
        pin(A) { direction: input; }
        pin(B) { direction: input; }
        pin(Y) { direction: output; function: "(A*B')+(A'*B)"; }
    }

    // A buffer cell needed to make ABC happy
    // Will get optimized away
    cell("$_BUF_") {
        area: 2;
        pin(A) { direction: input; }
        pin(Y) { direction: output; function: "A"; }
    }

    // 74AC374 octal D flip-flop
    cell(74AC374_8x1DFF) {
        area: 2.0625; // amortized clock pin cost
        ff(IQ, IQN) { clocked_on: "CLK"; next_state: "D"; }
        pin(CLK) { direction: input; clock: true; }
        pin(D) { direction: input; }
        pin(Q) { direction: output; function: "IQ"; }
    }
}