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rampe_isa.txt
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rampe_isa.txt
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RAMPE INSTRUCTION SET ARCHITECTURE
-----------------------------------
The RAMPE ISA is a RISC-style, small architecture that
has about 20 instructions. Everything has been designed
to fit into 8 bits, from the registers to memory addresses.
REGISTERS:
size name purpose
8 a accumulator, register 0 (00)
8 b general purpose register 1 (01)
8 c general purpose register 2 (10)
8 d general purpose register 3 (11)
8 pc program counter
8 ir instruction register
MEMORY:
Unified memory for both data and program. Memory consists of 8-bit bytes,
each address holds a byte of data. Address space 2^8 = 256 bytes.
The total memory can be extended by introducing an additional 8-bit memory bank
address. The total amount of memory would then be increased to 2^16 = 65536
bytes. Switching between memory banks would be done using the sw instruction.
INSTRUCTIONS:
Load/store architecture, mostly Intel syntax.
Comments begin with ";", labels use ":". Comments and labels are ignored.
Operands can be separated with "," e.g. "add a, b". Binary can be inserted
inside assembly programs, and this will get loaded directly to memory.
Valid decimal numbers in assembly programs will get converted to binary.
al = accumulator low 4 bits
ah = accumulator high 4 bits
address(reg) = contents of memory at address in reg
i size = 8 mnemonic <args> translation
system:
0 (8) nop ; idle (empty lines/comments)
1 (8) hlt ; stop execution
8 (8) inc ; increment accumulator
9 (8) dec ; decrement accumulator
10 (8) get ; get from memory here (ld a, pc)
11 (8) set ; set memory here (sto a, pc)
12 (8) sw ; optional: switch bank to b and jump to a
14 (8) in ; read value into a from stdin (simulator)
15 (8) out ; outputs/prints the value of a to stdout (simulator)
flow:
16 (4, 2, 0) jmp <reg> ; pc = reg
17 (4, 4) jez <reg1> <reg2> ; if reg1 == 0, pc = reg2
18 (4, 4) jlz <reg1> <reg2> ; if reg1 < 0, pc = reg2
memory:
19 (4, 2, 2) mov <reg1> <reg2> ; reg1 = reg2
20 (4, 4) sto <reg1> <reg2> ; address(reg2) = reg1
21 (4, 4) ld <reg1> <reg2> ; reg1 = address(reg2)
20 (4, 4) ll <val> ; al = val
23 (4, 4) lh <val> ; ah = val
logic and math:
24 (4, 2, 0) not <reg> ; reg = not(reg)
25 (4, 2, 2) and <reg1> <reg2> ; reg1 = and(reg1, reg2)
26 (4, 2, 2) or <reg1> <reg2> ; reg1 = or(reg1, reg2)
27 (4, 2, 2) xor <reg1> <reg2> ; reg1 = xor(reg1, reg2)
28 (4, 2, 2) add <reg1> <reg2> ; reg1 = reg1 + reg2
29 (4, 2, 2) sub <reg1> <reg2> ; reg1 = reg1 - reg2
30 (4, 2, 2) sh <val> <reg> ; reg = sh(reg, val), val = right: 0 (-2), 1 (-1) left: 2 (+1), 3 (+2)
Assembler:
<label>: ; define label
<label> ; label address
@<label> ; label bank
la <label> ; load label address into a
; ll <label>
; lh <label>
lb <label> ; load label bank into a
; ll @<label>
; lh @<label>
lba <label> ; load label bank and address into b and a
; ll @<label>
; lh @<label>
; mov b, a
; ll <label>
; lh <label>
ja <label> ; jump to label address
; ll <label>
; lh <label>
; jmp a
jea <label> ; jump to label if a == 0
; mov b, a
; ll <label>
; lh <label>
; jez b, a
jla <label> ; jump to label if a < 0
; mov b, a
; ll <label>
; lh <label>
; jlz b, a
jeb <label> ; jump to label if b == 0
; ll <label>
; lh <label>
; jez b, a
jlb <label> ; jump to label if b < 0
; ll <label>
; lh <label>
; jlz b, a
jec <label> ; jump to label if c == 0
; ll <label>
; lh <label>
; jez c, a
jlc <label> ; jump to label if c < 0
; ll <label>
; lh <label>
; jlz c, a
jed <label> ; jump to label if d == 0
; ll <label>
; lh <label>
; jez d, a
jld <label> ; jump to label if d < 0
; ll <label>
; lh <label>
; jlz d, a
lda <label> ; load a from label address
; ll <label>
; lh <label>
; ld a, a
ldb <label> ; load b from label address
; ll <label>
; lh <label>
; ld b, a
ldc <label> ; load c from label address
; ll <label>
; lh <label>
; ld c, a
ldd <label> ; load c from label address
; ll <label>
; lh <label>
; ld d, a
sta <label> ; store a to label address
; mov b, a
; ll <label>
; lh <label>
; sto b, a
stb <label> ; store b to label address
; ll <label>
; lh <label>
; sto b, a
stc <label> ; store c to label address
; ll <label>
; lh <label>
; sto c, a
std <label> ; store d to label address
; ll <label>
; lh <label>
; sto d, a
shr <reg> ; shift right
; sh 1, <reg>
shrr <reg> ; shift right twice
; sh 0, <reg>
shl <reg> ; shift left
; sh 2, <reg>
shll <reg> ; shift left twice
; sh 3, <reg>
MACHINE CODES:
0000 0000 nop
0000 0001 hlt
0000 1000 inc
0000 1001 dec
0000 1010 get
0000 1011 set
0000 1100 sw
0000 1101
0000 1110 in
0000 1111 out
0001 jmp
0010 jez
0011 jlz
0100 mov
0101 sto
0110 ld
0111 ll
1000 lh
1001 not
1010 and
1011 or
1100 xor
1101 add
1110 sub
1111 sh