-
Notifications
You must be signed in to change notification settings - Fork 1
/
opfunc.zig
464 lines (381 loc) · 16.3 KB
/
opfunc.zig
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
// (C) 2021 Ronsor Labs.
const std = @import("std");
const decoder = @import("decoder.zig");
const CPU = @import("cpu.zig").CPU;
const Instruction = decoder.Instruction;
pub const OpFuncError = error{
Unimplemented,
};
pub const OpFunc = fn (cpu: *CPU, inst: []Instruction, cur: usize) anyerror!void;
/// Execute next instruction.
pub inline fn next(cpu: *CPU, inst: []Instruction, oldcur: usize) !void {
var cur = oldcur +% 1;
cpu.pc +%= 4;
cpu.cache.exec_counter += 1;
if (cpu.cache.exec_counter > cpu.cache.max_exec) return;
if (cur == cpu.cache.inst.?.len) return;
return @call(.{}, cpu.cache.funcs.?[cur], .{ cpu, inst, cur });
}
/// Attempt to "goto" cached instruction, otherwise return as usual.
pub inline fn goto(cpu: *CPU, inst: []Instruction, oldcur: usize, newpc: CPU.XLEN) !void {
// TODO: support compressed instructions
if (newpc >= cpu.cache.base_pc and newpc < cpu.cache.max_pc and (newpc % 4) == 0) {
cpu.pc = newpc -% 4;
return next(cpu, inst, @truncate(usize, (newpc - cpu.cache.base_pc) / 4) -% 1);
}
cpu.pc = newpc;
cpu.cache.exec_counter += 1;
return;
}
// -- ALU functions with only registers --
pub fn add(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].add;
cpu.setReg(params.rd, cpu.getReg(params.rs1) +% cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
pub fn sub(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sub;
cpu.setReg(params.rd, cpu.getReg(params.rs1) -% cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
pub fn xor(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].xor;
cpu.setReg(params.rd, cpu.getReg(params.rs1) ^ cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
pub fn @"or"(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].@"or";
cpu.setReg(params.rd, cpu.getReg(params.rs1) | cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
pub fn @"and"(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].@"and";
cpu.setReg(params.rd, cpu.getReg(params.rs1) & cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
pub fn sll(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sll;
cpu.setReg(params.rd, cpu.getReg(params.rs1) << @truncate(u6, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
pub fn srl(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].srl;
cpu.setReg(params.rd, cpu.getReg(params.rs1) >> @truncate(u6, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
pub fn sra(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sra;
cpu.setReg(params.rd, cpu.getReg(params.rs1) >> @truncate(u6, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
// -- ALU functions with an immediate value --
// Most of these functions are pretty monotonous, always following the same format
// Immediates are always sign-extended, unless otherwise specified
// at least that was my understanding of the specification.
pub fn addi(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].addi;
cpu.setReg(params.rd, cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()));
return next(cpu, inst, cur);
}
pub fn xori(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].xori;
cpu.setReg(params.rd, cpu.getReg(params.rs1) ^ CPU.util.sext(params.immSigned()));
return next(cpu, inst, cur);
}
pub fn ori(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].ori;
cpu.setReg(params.rd, cpu.getReg(params.rs1) | CPU.util.sext(params.immSigned()));
return next(cpu, inst, cur);
}
pub fn andi(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].andi;
cpu.setReg(params.rd, cpu.getReg(params.rs1) & CPU.util.sext(params.immSigned()));
return next(cpu, inst, cur);
}
pub fn slli(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].slli;
cpu.setReg(params.rd, cpu.getReg(params.rs1) << @intCast(u6, params.imm & 0b1111));
return next(cpu, inst, cur);
}
pub fn srli(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].srli;
cpu.setReg(params.rd, cpu.getReg(params.rs1) >> @intCast(u6, params.imm & 0b1111));
return next(cpu, inst, cur);
}
pub fn srai(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].srai;
cpu.setReg(params.rd, cpu.getReg(params.rs1) >> @intCast(u6, params.imm & 0b1111));
return next(cpu, inst, cur);
}
pub fn slti(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].slti;
// Why @bitCast() & @intCast()? RISC-V manual: "immediates are always sign extended"
cpu.setReg(params.rd, if (cpu.getRegSigned(params.rs1) < @intCast(CPU.SXLEN, params.immSigned())) 1 else 0);
return next(cpu, inst, cur);
}
pub fn sltiu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sltiu;
// Explicitly unsigned, so only zero-extend
// Since this isn't hardware, a simple @intCast() works
cpu.setReg(params.rd, if (cpu.getReg(params.rs1) < @intCast(CPU.XLEN, params.imm)) 1 else 0);
return next(cpu, inst, cur);
}
// -- Load/store --
pub fn lb(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lb;
cpu.setReg(params.rd, CPU.util.sext(try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), i8, .none)));
return next(cpu, inst, cur);
}
pub fn lh(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lh;
cpu.setReg(params.rd, CPU.util.sext(try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), i16, .none)));
return next(cpu, inst, cur);
}
pub fn lw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lw;
cpu.setReg(params.rd, CPU.util.sext(try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), i32, .none)));
return next(cpu, inst, cur);
}
pub fn ld(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].ld;
cpu.setReg(params.rd, CPU.util.sext(try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), i64, .none)));
return next(cpu, inst, cur);
}
pub fn lbu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lbu;
cpu.setReg(params.rd, @intCast(CPU.XLEN, try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), u8, .none)));
return next(cpu, inst, cur);
}
pub fn lhu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lhu;
cpu.setReg(params.rd, @intCast(CPU.XLEN, try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), u16, .none)));
return next(cpu, inst, cur);
}
pub fn lwu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lhu;
cpu.setReg(params.rd, @intCast(CPU.XLEN, try cpu.getMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), u32, .none)));
return next(cpu, inst, cur);
}
pub fn sb(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sb;
try cpu.setMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), @truncate(u8, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
pub fn sh(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sh;
try cpu.setMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), @truncate(u16, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
pub fn sw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sw;
try cpu.setMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), @truncate(u32, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
pub fn sd(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sd;
try cpu.setMem(cpu.getReg(params.rs1) +% CPU.util.sext(params.immSigned()), @truncate(u64, cpu.getReg(params.rs2)));
return next(cpu, inst, cur);
}
// -- Branch functions --
pub fn beq(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].beq;
if (cpu.getReg(params.rs1) == cpu.getReg(params.rs2)) return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
return next(cpu, inst, cur);
}
pub fn bne(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].bne;
if (cpu.getReg(params.rs1) != cpu.getReg(params.rs2)) return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
return next(cpu, inst, cur);
}
pub fn blt(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].blt;
if (cpu.getRegSigned(params.rs1) < cpu.getRegSigned(params.rs2)) return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
return next(cpu, inst, cur);
}
pub fn bge(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].bge;
if (cpu.getRegSigned(params.rs1) > cpu.getRegSigned(params.rs2)) return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
return next(cpu, inst, cur);
}
pub fn bltu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].bltu;
if (cpu.getReg(params.rs1) < cpu.getReg(params.rs2)) return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
return next(cpu, inst, cur);
}
pub fn bgeu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].bgeu;
if (cpu.getReg(params.rs1) > cpu.getReg(params.rs2)) return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
return next(cpu, inst, cur);
}
// -- Jump functions --
pub fn jal(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].jal;
cpu.setReg(params.rd, cpu.pc + 4);
return goto(cpu, inst, cur, cpu.pc +% @intCast(CPU.XLEN, params.imm));
}
pub fn jalr(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].jalr;
cpu.setReg(params.rd, cpu.pc + 4);
return goto(cpu, inst, cur, cpu.getReg(params.rs1) +% @intCast(CPU.XLEN, params.imm));
}
// -- Misc functions --
pub fn lui(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].lui;
cpu.setReg(params.rd, CPU.util.sext(params.imm));
return next(cpu, inst, cur);
}
pub fn auipc(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].auipc;
cpu.setReg(params.rd, cpu.pc + CPU.util.sext(params.imm));
return next(cpu, inst, cur);
}
// -- Specifically 32-bit ALU functions --
pub fn addw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].addw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) +% @truncate(u32, cpu.getReg(params.rs2))));
return next(cpu, inst, cur);
}
pub fn subw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].subw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) -% @truncate(u32, cpu.getReg(params.rs2))));
return next(cpu, inst, cur);
}
pub fn sllw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sllw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) << @truncate(u5, cpu.getReg(params.rs2))));
return next(cpu, inst, cur);
}
pub fn srlw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].srlw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) >> @truncate(u5, cpu.getReg(params.rs2))));
return next(cpu, inst, cur);
}
pub fn sraw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sraw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) >> @truncate(u5, cpu.getReg(params.rs2))));
return next(cpu, inst, cur);
}
// -- 32-bit ALU functions with an immediate value --
pub fn addiw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].addiw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) +% @bitCast(u32, @intCast(i32, params.immSigned()))));
return next(cpu, inst, cur);
}
pub fn slliw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].slliw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) << @truncate(u5, params.shamt)));
return next(cpu, inst, cur);
}
pub fn srliw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].srliw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) >> @truncate(u5, params.shamt)));
return next(cpu, inst, cur);
}
pub fn sraiw(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].sraiw;
cpu.setReg(params.rd, CPU.util.sext(@truncate(u32, cpu.getReg(params.rs1)) >> @truncate(u5, params.shamt)));
return next(cpu, inst, cur);
}
// -- Multiplication (M) extension functions --
pub fn mul(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].mul;
cpu.setReg(params.rd, @intCast(CPU.XLEN, @truncate(u32, cpu.getReg(params.rs1) *% cpu.getReg(params.rs2))));
return next(cpu, inst, cur);
}
pub fn mulh(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].mulh;
cpu.setReg(params.rd, (@bitCast(CPU.XLEN, cpu.getRegSigned(params.rs1) *% cpu.getRegSigned(params.rs2)) & 0xFFFFFFFF_00000000) >> 32);
return next(cpu, inst, cur);
}
pub fn mulsu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].mulsu;
cpu.setReg(params.rd, @intCast(CPU.XLEN, ((cpu.getReg(params.rs1) *% cpu.getReg(params.rs2)) & 0xFFFFFFFF_00000000) >> 32));
return next(cpu, inst, cur);
}
pub fn mulu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].mulu;
cpu.setReg(params.rd, @intCast(CPU.XLEN, ((cpu.getReg(params.rs1) *% cpu.getReg(params.rs2)) & 0xFFFFFFFF_00000000) >> 32));
return next(cpu, inst, cur);
}
pub fn div(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].div;
cpu.setReg(params.rd, @bitCast(CPU.XLEN, try std.math.divFloor(i64, cpu.getRegSigned(params.rs1), cpu.getRegSigned(params.rs2))));
return next(cpu, inst, cur);
}
pub fn divu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].divu;
cpu.setReg(params.rd, cpu.getReg(params.rs1) / cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
pub fn rem(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].rem;
cpu.setReg(params.rd, @bitCast(CPU.XLEN, try std.math.rem(i64, cpu.getRegSigned(params.rs1), cpu.getRegSigned(params.rs2))));
return next(cpu, inst, cur);
}
pub fn remu(cpu: *CPU, inst: []Instruction, cur: usize) !void {
const params = inst[cur].remu;
cpu.setReg(params.rd, cpu.getReg(params.rs1) % cpu.getReg(params.rs2));
return next(cpu, inst, cur);
}
// -- Utilities --
/// Get the function corresponding to an instruction.
pub fn fromInstruction(inst: Instruction) !OpFunc {
return switch (inst) {
.add => add,
.sub => sub,
.xor => xor,
.@"or" => @"or",
.@"and" => @"and",
.sll => sll,
.srl => srl,
.sra => sra,
.addi => addi,
.xori => xori,
.ori => ori,
.andi => andi,
.slli => slli,
.srli => srli,
.srai => srai,
.slti => slti,
.sltiu => sltiu,
.lb => lb,
.lh => lh,
.lw => lw,
.ld => ld,
.lbu => lbu,
.lhu => lhu,
.lwu => lwu,
.sb => sb,
.sh => sh,
.sw => sw,
.sd => sd,
.beq => beq,
.bne => bne,
.blt => blt,
.bge => bge,
.bltu => bltu,
.bgeu => bgeu,
.jal => jal,
.jalr => jalr,
.lui => lui,
.auipc => auipc,
.addw => addw,
.subw => subw,
.sllw => sllw,
.srlw => srlw,
.sraw => sraw,
.addiw => addiw,
.slliw => slliw,
.srliw => srliw,
.sraiw => sraiw,
.mul => mul,
.mulh => mulh,
.mulsu => mulsu,
.mulu => mulu,
.div => div,
.divu => divu,
.rem => rem,
.remu => remu,
else => OpFuncError.Unimplemented,
};
}