diff --git a/suite/cstest/include/test_detail.h b/suite/cstest/include/test_detail.h index f30789af34..83b63a097e 100644 --- a/suite/cstest/include/test_detail.h +++ b/suite/cstest/include/test_detail.h @@ -12,6 +12,7 @@ #include "test_detail_aarch64.h" #include "test_detail_arm.h" #include "test_detail_ppc.h" +#include "test_detail_riscv.h" #include "test_detail_tricore.h" #include "test_detail_systemz.h" #include "test_detail_sh.h" @@ -21,6 +22,7 @@ #include "test_detail_hppa.h" #include "test_detail_xcore.h" #include "test_detail_mips.h" +#include "test_detail_riscv.h" #include "test_compare.h" #include #include @@ -40,16 +42,15 @@ typedef struct { TestDetailXCore *xcore; TestDetailSH *sh; TestDetailMips *mips; + TestDetailRISCV *riscv; // cs_x86_test x86; // cs_m68k_test m68k; - // cs_mips_test mips; // cs_tms320c64x_test tms320c64x; // cs_m680x_test m680x; // cs_evm_test evm; // cs_mos65xx_test mos65xx; // cs_wasm_test wasm; // cs_riscv_test riscv; - // cs_sh_test sh; // cs_loongarch_test loongarch; char **regs_read; @@ -105,6 +106,9 @@ static const cyaml_schema_field_t test_detail_mapping_schema[] = { CYAML_FIELD_MAPPING_PTR( "mips", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, mips, test_detail_mips_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "riscv", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + riscv, test_detail_riscv_mapping_schema), CYAML_FIELD_SEQUENCE("regs_read", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, regs_read, ®_group_schema, 0, 255), diff --git a/suite/cstest/include/test_detail_riscv.h b/suite/cstest/include/test_detail_riscv.h new file mode 100644 index 0000000000..3940271fc2 --- /dev/null +++ b/suite/cstest/include/test_detail_riscv.h @@ -0,0 +1,66 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_RISCV_H +#define TEST_DETAIL_RISCV_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + uint64_t imm; + char *mem_base; + int64_t mem_disp; +} TestDetailRISCVOp; + +static const cyaml_schema_field_t test_detail_riscv_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_riscv_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailRISCVOp, + test_detail_riscv_op_mapping_schema), +}; + +typedef struct { + TestDetailRISCVOp **operands; + uint32_t operands_count; +} TestDetailRISCV; + +static const cyaml_schema_field_t test_detail_riscv_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCV, operands, &test_detail_riscv_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailRISCV *test_detail_riscv_new(); +TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail); +void test_detail_riscv_free(TestDetailRISCV *detail); + +TestDetailRISCVOp *test_detail_riscv_op_new(); +TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *detail); +void test_detail_riscv_op_free(TestDetailRISCVOp *detail); + +bool test_expected_riscv(csh *handle, const cs_riscv *actual, + const TestDetailRISCV *expected); + +#endif // TEST_DETAIL_RISCV_H diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index f5283f21c3..abe27397bc 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -637,6 +637,23 @@ static const cs_enum_id_map cs_enum_map[] = { { .str = "PPC_PRED_Z_MINUS", .val = PPC_PRED_Z_MINUS }, { .str = "PPC_PRED_Z_PLUS", .val = PPC_PRED_Z_PLUS }, { .str = "PPC_PRED_Z_RESERVED", .val = PPC_PRED_Z_RESERVED }, + { .str = "RISCV_GRP_BRANCH_RELATIVE", .val = RISCV_GRP_BRANCH_RELATIVE }, + { .str = "RISCV_GRP_CALL", .val = RISCV_GRP_CALL }, + { .str = "RISCV_GRP_HASSTDEXTA", .val = RISCV_GRP_HASSTDEXTA }, + { .str = "RISCV_GRP_HASSTDEXTC", .val = RISCV_GRP_HASSTDEXTC }, + { .str = "RISCV_GRP_HASSTDEXTD", .val = RISCV_GRP_HASSTDEXTD }, + { .str = "RISCV_GRP_HASSTDEXTF", .val = RISCV_GRP_HASSTDEXTF }, + { .str = "RISCV_GRP_HASSTDEXTM", .val = RISCV_GRP_HASSTDEXTM }, + { .str = "RISCV_GRP_INT", .val = RISCV_GRP_INT }, + { .str = "RISCV_GRP_IRET", .val = RISCV_GRP_IRET }, + { .str = "RISCV_GRP_ISRV32", .val = RISCV_GRP_ISRV32 }, + { .str = "RISCV_GRP_ISRV64", .val = RISCV_GRP_ISRV64 }, + { .str = "RISCV_GRP_JUMP", .val = RISCV_GRP_JUMP }, + { .str = "RISCV_GRP_PRIVILEGE", .val = RISCV_GRP_PRIVILEGE }, + { .str = "RISCV_GRP_RET", .val = RISCV_GRP_RET }, + { .str = "RISCV_OP_IMM", .val = RISCV_OP_IMM }, + { .str = "RISCV_OP_MEM", .val = RISCV_OP_MEM }, + { .str = "RISCV_OP_REG", .val = RISCV_OP_REG }, { .str = "SH_GRP_BRANCH_RELATIVE", .val = SH_GRP_BRANCH_RELATIVE }, { .str = "SH_GRP_CALL", .val = SH_GRP_CALL }, { .str = "SH_GRP_INT", .val = SH_GRP_INT }, diff --git a/suite/cstest/src/test_detail.c b/suite/cstest/src/test_detail.c index 4fc2da07e0..4fd1f3f0d6 100644 --- a/suite/cstest/src/test_detail.c +++ b/suite/cstest/src/test_detail.c @@ -82,6 +82,9 @@ TestDetail *test_detail_clone(TestDetail *detail) if (detail->mips) { clone->mips = test_detail_mips_clone(detail->mips); } + if (detail->riscv) { + clone->riscv = test_detail_riscv_clone(detail->riscv); + } return clone; } @@ -143,6 +146,9 @@ void test_detail_free(TestDetail *detail) if (detail->mips) { test_detail_mips_free(detail->mips); } + if (detail->riscv) { + test_detail_riscv_free(detail->riscv); + } cs_mem_free(detail); } @@ -230,5 +236,9 @@ bool test_expected_detail(csh *handle, const cs_insn *insn, return test_expected_mips(handle, &actual->mips, expected->mips); } + if (expected->riscv) { + return test_expected_riscv(handle, &actual->riscv, + expected->riscv); + } return true; } diff --git a/suite/cstest/src/test_detail_riscv.c b/suite/cstest/src/test_detail_riscv.c new file mode 100644 index 0000000000..1d93e850f5 --- /dev/null +++ b/suite/cstest/src/test_detail_riscv.c @@ -0,0 +1,107 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_riscv.h" +#include +#include +#include + +TestDetailRISCV *test_detail_riscv_new() +{ + return cs_mem_calloc(sizeof(TestDetailRISCV), 1); +} + +void test_detail_riscv_free(TestDetailRISCV *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_riscv_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail) +{ + TestDetailRISCV *clone = test_detail_riscv_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailRISCVOp), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_riscv_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailRISCVOp *test_detail_riscv_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailRISCVOp), 1); +} + +TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *op) +{ + TestDetailRISCVOp *clone = test_detail_riscv_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_riscv_op_free(TestDetailRISCVOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_riscv(csh *handle, const cs_riscv *actual, + const TestDetailRISCV *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_riscv_op *op = &actual->operands[i]; + TestDetailRISCVOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "sh op type %" PRId32 " not handled.\n", + op->type); + return false; + case RISCV_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case RISCV_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case RISCV_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/tests/details/riscv.yaml b/tests/details/riscv.yaml new file mode 100644 index 0000000000..5b079d4585 --- /dev/null +++ b/tests/details/riscv.yaml @@ -0,0 +1,1626 @@ +test_cases: + - + input: + bytes: [ 0x37, 0x34, 0x00, 0x00, 0x97, 0x82, 0x00, 0x00, 0xef, 0x00, 0x80, 0x00, 0xef, 0xf0, 0x1f, 0xff, 0xe7, 0x00, 0x45, 0x00, 0xe7, 0x00, 0xc0, 0xff, 0x63, 0x05, 0x41, 0x00, 0xe3, 0x9d, 0x61, 0xfe, 0x63, 0xca, 0x93, 0x00, 0x63, 0x53, 0xb5, 0x00, 0x63, 0x65, 0xd6, 0x00, 0x63, 0x76, 0xf7, 0x00, 0x03, 0x88, 0x18, 0x00, 0x03, 0x99, 0x49, 0x00, 0x03, 0xaa, 0x6a, 0x00, 0x03, 0xcb, 0x2b, 0x01, 0x03, 0xdc, 0x8c, 0x01, 0x23, 0x86, 0xad, 0x03, 0x23, 0x9a, 0xce, 0x03, 0x23, 0x8f, 0xef, 0x01, 0x93, 0x00, 0xe0, 0x00, 0x13, 0xa1, 0x01, 0x01, 0x13, 0xb2, 0x02, 0x7d, 0x13, 0xc3, 0x03, 0xdd, 0x13, 0xe4, 0xc4, 0x12, 0x13, 0xf5, 0x85, 0x0c, 0x13, 0x96, 0xe6, 0x01, 0x13, 0xd7, 0x97, 0x01, 0x13, 0xd8, 0xf8, 0x40, 0x33, 0x89, 0x49, 0x01, 0xb3, 0x0a, 0x7b, 0x41, 0x33, 0xac, 0xac, 0x01, 0xb3, 0x3d, 0xde, 0x01, 0x33, 0xd2, 0x62, 0x40, 0xb3, 0x43, 0x94, 0x00, 0x33, 0xe5, 0xc5, 0x00, 0xb3, 0x76, 0xf7, 0x00, 0xb3, 0x54, 0x39, 0x01, 0xb3, 0x50, 0x31, 0x00, 0x33, 0x9f, 0x0f, 0x00, 0x73, 0x15, 0x04, 0xb0, 0xf3, 0x56, 0x00, 0x10, 0x33, 0x05, 0x7b, 0x03, 0xb3, 0x45, 0x9c, 0x03, 0x33, 0x66, 0xbd, 0x03, 0x2f, 0xa4, 0x02, 0x10, 0xaf, 0x23, 0x65, 0x18, 0x2f, 0x27, 0x2f, 0x01, 0x43, 0xf0, 0x20, 0x18, 0xd3, 0x72, 0x73, 0x00, 0x53, 0xf4, 0x04, 0x58, 0x53, 0x85, 0xc5, 0x28, 0x53, 0x2e, 0xde, 0xa1, 0xd3, 0x84, 0x05, 0xf0, 0x53, 0x06, 0x05, 0xe0, 0x53, 0x75, 0x00, 0xc0, 0xd3, 0xf0, 0x05, 0xd0, 0xd3, 0x15, 0x08, 0xe0, 0x87, 0xaa, 0x75, 0x00, 0x27, 0x27, 0x66, 0x01, 0x43, 0xf0, 0x20, 0x1a, 0xd3, 0x72, 0x73, 0x02, 0x53, 0xf4, 0x04, 0x5a, 0x53, 0x85, 0xc5, 0x2a, 0x53, 0x2e, 0xde, 0xa3 ] + arch: "riscv" + options: [ CS_OPT_DETAIL, CS_MODE_RISCV32 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lui s0, 3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x3 + access: CS_AC_READ + - + asm_text: "auipc t0, 8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x8 + access: CS_AC_READ + - + asm_text: "jal 8" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x8 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "jal -0x10" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: -0x10 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "jalr ra, a0, 4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x4 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "jalr ra, zero, -4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -4 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "beq sp, tp, 0xa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xa + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bne gp, t1, -6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -6 + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "blt t2, s1, 0x14" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x14 + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bge a0, a1, 6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x6 + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bltu a2, a3, 0xa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xa + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bgeu a4, a5, 0xc" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xc + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "lb a6, 1(a7)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a7 + mem_disp: 0x1 + access: CS_AC_READ + - + asm_text: "lh s2, 4(s3)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s3 + mem_disp: 0x4 + access: CS_AC_READ + - + asm_text: "lw s4, 6(s5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s4 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s5 + mem_disp: 0x6 + access: CS_AC_READ + - + asm_text: "lbu s6, 0x12(s7)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s7 + mem_disp: 0x12 + access: CS_AC_READ + - + asm_text: "lhu s8, 0x18(s9)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s9 + mem_disp: 0x18 + access: CS_AC_READ + - + asm_text: "sb s10, 0x2c(s11)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: s11 + mem_disp: 0x2c + access: CS_AC_WRITE + - + asm_text: "sh t3, 0x34(t4)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t4 + mem_disp: 0x34 + access: CS_AC_WRITE + - + asm_text: "sb t5, 0x1e(t6)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t5 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t6 + mem_disp: 0x1e + access: CS_AC_WRITE + - + asm_text: "addi ra, zero, 0xe" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xe + access: CS_AC_READ + - + asm_text: "slti sp, gp, 0x10" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x10 + access: CS_AC_READ + - + asm_text: "sltiu tp, t0, 0x7d0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x7d0 + access: CS_AC_READ + - + asm_text: "xori t1, t2, -0x230" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -0x230 + access: CS_AC_READ + - + asm_text: "ori s0, s1, 0x12c" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x12c + access: CS_AC_READ + - + asm_text: "andi a0, a1, 0xc8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xc8 + access: CS_AC_READ + - + asm_text: "slli a2, a3, 0x1e" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x1e + access: CS_AC_READ + - + asm_text: "srli a4, a5, 0x19" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x19 + access: CS_AC_READ + - + asm_text: "srai a6, a7, 0xf" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a7 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xf + access: CS_AC_READ + - + asm_text: "add s2, s3, s4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s3 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s4 + access: CS_AC_READ + - + asm_text: "sub s5, s6, s7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s7 + access: CS_AC_READ + - + asm_text: "slt s8, s9, s10" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s9 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + asm_text: "sltu s11, t3, t4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t4 + access: CS_AC_READ + - + asm_text: "sra tp, t0, t1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + asm_text: "xor t2, s0, s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + asm_text: "or a0, a1, a2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_READ + - + asm_text: "and a3, a4, a5" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + asm_text: "srl s1, s2, s3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s3 + access: CS_AC_READ + - + asm_text: "srl ra, sp, gp" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + asm_text: "sll t5, t6, zero" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + asm_text: "csrrw a0, mcycle, s0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ + - + asm_text: "csrrwi a3, sstatus, 0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "mul a0, s6, s7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM ] + - + asm_text: "div a1, s8, s9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s9 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM ] + - + asm_text: "rem a2, s10, s11" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM ] + - + asm_text: "lr.w s0, (t0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTA ] + - + asm_text: "sc.w t2, t1, (a0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a0 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTA ] + - + asm_text: "amoadd.w a4, s2, (t5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t5 + access: CS_AC_READ_WRITE + groups: [ RISCV_GRP_HASSTDEXTA ] + - + asm_text: "fmadd.s ft0, ft1, ft2, ft3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft3 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fadd.s ft5, ft6, ft7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fsqrt.s fs0, fs1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmin.s fa0, fa1, fa2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: fa2 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "feq.s t3, ft8, ft9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft9 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmv.w.x fs1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmv.x.w a2, fa0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fcvt.w.s a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fcvt.s.w ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fclass.s a1, fa6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa6 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "flw fs5, 7(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs5 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fsw fs6, 0xe(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs6 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0xe + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmadd.d ft0, ft1, ft2, ft3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft3 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fadd.d ft5, ft6, ft7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fsqrt.d fs0, fs1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fmin.d fa0, fa1, fa2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: fa2 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "feq.d t3, ft8, ft9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft9 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + input: + bytes: [ 0x13, 0x04, 0xa8, 0x7a, 0xbb, 0x07, 0x9c, 0x02, 0xbb, 0x40, 0x5d, 0x02, 0x3b, 0x63, 0xb7, 0x03, 0x2f, 0xb4, 0x02, 0x10, 0xaf, 0x33, 0x65, 0x18, 0x2f, 0x37, 0x2f, 0x01, 0x53, 0x75, 0x20, 0xc0, 0xd3, 0xf0, 0x25, 0xd0, 0xd3, 0x84, 0x05, 0xf2, 0x53, 0x06, 0x05, 0xe2, 0x53, 0x75, 0x00, 0xc2, 0xd3, 0x80, 0x05, 0xd2, 0xd3, 0x15, 0x08, 0xe2, 0x87, 0xba, 0x75, 0x00, 0x27, 0x37, 0x66, 0x01 ] + arch: "riscv" + options: [ CS_OPT_DETAIL, CS_MODE_RISCV64 ] + address: 0x1000 + expected: + insns: + - + asm_text: "addi s0, a6, 0x7aa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x7aa + access: CS_AC_READ + - + asm_text: "mulw a5, s8, s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ] + - + asm_text: "divw ra, s10, t0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ] + - + asm_text: "remw t1, a4, s11" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ] + - + asm_text: "lr.d s0, (t0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ] + - + asm_text: "sc.d t2, t1, (a0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a0 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ] + - + asm_text: "amoadd.d a4, s2, (t5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t5 + access: CS_AC_READ_WRITE + groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ] + - + asm_text: "fcvt.l.s a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64 ] + - + asm_text: "fcvt.s.l ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64 ] + - + asm_text: "fmv.d.x fs1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64 ] + - + asm_text: "fmv.x.d a2, fa0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64 ] + - + asm_text: "fcvt.w.d a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fcvt.d.w ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fclass.d a1, fa6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa6 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fld fs5, 7(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs5 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fsd fs6, 0xe(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs6 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0xe + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTD ] + - + input: + bytes: [ 0xe8, 0x1f, 0x7d, 0x61, 0x80, 0x25, 0x00, 0x46, 0x88, 0xa2, 0x04, 0xcb, 0x55, 0x13, 0xf2, 0x93, 0x5d, 0x45, 0x19, 0x80, 0x15, 0x68, 0x2a, 0xa4, 0x62, 0x24, 0xa6, 0xff, 0x2a, 0x65, 0x76, 0x86, 0x65, 0xdd, 0x01, 0x00, 0xfd, 0xaf, 0x82, 0x82, 0x11, 0x20, 0x82, 0x94 ] + arch: "riscv" + options: [ CS_OPT_DETAIL, CS_MODE_RISCVC ] + address: 0x1000 + expected: + insns: + - + asm_text: "c.addi4spn a0, sp, 0x3fc" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x3fc + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.addi16sp sp, 0x1f0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: 0x1f0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.fld fs0, 8(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x8 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.lw s0, 8(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0x8 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.fsd fa0, 0(a3)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a3 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.sw s1, 0x10(a4)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a4 + mem_disp: 0x10 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.addi t1, -0xb" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: -0xb + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.add t2, t3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.li a0, 0x17" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x17 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.srli s0, 6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: 0x6 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.lui a6, 5" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x5 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.fsdsp fa0, 8(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: sp + mem_disp: 0x8 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.fldsp fs0, 0x18(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: sp + mem_disp: 0x18 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.fswsp fs1, 0xfc(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xfc + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32 ] + - + asm_text: "c.flwsp fa0, 0x88(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x88 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32 ] + - + asm_text: "c.mv a2, t4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t4 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.beqz a0, -8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -8 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "c.nop" + details: + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.j 0x7fe" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x7fe + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_JUMP ] + - + asm_text: "c.jr t0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_JUMP ] + - + asm_text: "c.jal 4" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x4 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, RISCV_GRP_CALL ] + - + asm_text: "c.jalr s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_CALL ] +