Attiny 826 QFN20 Multiplex Diagram

[dapeake2]

For Spence and the community I created this diagram (in the following post) for the ATtiny826 VQFN20 which I am using on a project. The physical pin assignment differs from the DIP SOIC20 found here https://github.com/SpenceKonde/megaTinyCore/blob/master/megaavr/extras/ATtiny_x26.png

If anyone spots any errors (even minor ones) please let me know, I will quickly update it.

Dan
San Jose, CA

[dapeake2]

Corrected as of 3.24.2022

[SpenceKonde]

Thanks - yeah for whatever reason, they start the pins a little off center rather than on one of the corners, which would make it easier for people to follow. They do it on every device they make too - not just tinyAVR. Physical pin1 on packages with pins on 2 sides corresponds to pin (1+ceiling((pincount/8))) or thereabouts on parts with pins on 4 sides.

A few things - t's CLKI/CLKO (clock in, clock out) not CLK1, CLK0. The reason it looks odd in the other diagram is that I added those labels to the other diagram in the most sophisticated drawing program I know how to use: Microsoft Paint.
PC2 does not have TXD alternate pin on it.
Alternate pins on the other diagrams are shown in ITALIC all-caps, would be nice to match that here. Actually - it looks like the name of ther peripheral for alt pins is shown in slightly smaller typeface too - both of which make a difference because it's easier to see
I spell the name of the core as "megaTiinyCore" (lowercase M), and I don't like the look of the Konde in front of it....

Thinking about it, at some point i ought to add the URL of the github repo to the images, so that when people steal them, the people who see their posts will at least know where they stole them from...

[dapeake2]

Here are improvements: Glad to make more adjustments.