{"payload":{"header_redesign_enabled":false,"results":[{"id":"389361050","archived":false,"color":"#b2b7f8","followers":1,"has_funding_file":false,"hl_name":"SuhailAhamed2000/SIPO","hl_trunc_description":"The shift register, which allows serial input (one bit after the other through a single data line) and produces a parallel output is know…","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":389361050,"name":"SIPO","owner_id":81544828,"owner_login":"SuhailAhamed2000","updated_at":"2021-07-25T14:04:59.669Z","has_issues":true}},"sponsorable":false,"topics":["verilog","shift-register","sipo"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":61,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ASuhailAhamed2000%252FSIPO%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/SuhailAhamed2000/SIPO/star":{"post":"hcEwbF7ktvyGl-mVPNBF_B32V0NGPtQ4-Bq8dWteIllQ494LRiUCmslIsfoDBhQ0LOhnqGYgOE_SqzRvkFEc3w"},"/SuhailAhamed2000/SIPO/unstar":{"post":"DGSlrR8W9xHrzDxgsOYNLSatqm333i4ZSfgvhsO9568wd89IgcjASVH2p5tGw6LOPco_UcwiL3zrn9X-OhyBCg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"FasM2v7EP8MdZQDxSY3_k43x7-1rDVWZmsj1uOfVAl6r0HAkmF7C2-yLCtn_DUAcOnvY7hBLue4ild7gwR4feA"}}},"title":"Repository search results"}