diff --git a/Makefile b/Makefile
index 93f5bc846a6..1e2709a1799 100644
--- a/Makefile
+++ b/Makefile
@@ -649,6 +649,7 @@ SEEDOPT=""
 endif
 
 test: $(TARGETS) $(EXTRA_TARGETS)
+	+cd tests/reference-out && bash run-test.sh
 	+cd tests/round-trip && bash run-test.sh
 	+cd tests/simple && bash run-test.sh $(SEEDOPT)
 	+cd tests/hana && bash run-test.sh $(SEEDOPT)
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 44696e38f79..b31076a0702 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -168,6 +168,11 @@ void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
 		f << stringf("\n");
 	}
 	for (auto &it : cell->connections()) {
+		for (auto &it2 : it.second.attributes) {
+			f << stringf("%s  attribute %s ", indent.c_str(), it2.first.c_str());
+			dump_const(f, it2.second);
+			f << stringf("\n");
+		}
 		f << stringf("%s  connect %s ", indent.c_str(), it.first.c_str());
 		dump_sigspec(f, it.second);
 		f << stringf("\n");
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 56c05b82892..b3f0c922f31 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -137,6 +137,24 @@ struct JsonWriter
 		}
 	}
 
+	void write_connection_attributes(const dict<IdString, Const>& attributes)
+	{
+		bool first = true;
+		for (auto &attr : attributes) {
+			f << stringf("%s\n", first ? "" : ",");
+			f << stringf("                %s: ", get_name(attr.first).c_str());
+			if ((attr.second.flags & RTLIL::ConstFlags::CONST_FLAG_STRING) != 0)
+				f << get_string(attr.second.decode_string());
+			else if (GetSize(attr.second.bits) > 32)
+				f << get_string(attr.second.as_string());
+			else if ((attr.second.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0)
+				f << stringf("%d", attr.second.as_int());
+			else
+				f << stringf("%u", attr.second.as_int());
+			first = false;
+		}
+	}
+
 	void write_module(Module *module_)
 	{
 		module = module_;
@@ -211,7 +229,12 @@ struct JsonWriter
 			bool first2 = true;
 			for (auto &conn : c->connections()) {
 				f << stringf("%s\n", first2 ? "" : ",");
-				f << stringf("            %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
+				f << stringf("            %s: {\n", get_name(conn.first).c_str());
+				f << stringf("              \"bits\": %s,\n",  get_bits(conn.second).c_str());
+				f << stringf("              \"attributes\": {");
+				write_connection_attributes(conn.second.attributes);
+				f << stringf("\n            }\n");
+				f << stringf("            }");
 				first2 = false;
 			}
 			f << stringf("\n          }\n");
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index e2b5bbe0c52..d54bbf24478 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -345,8 +345,27 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
 	}
 }
 
+void dump_attributes(std::ostream &f, std::string indent, const dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false)
+{
+	if (noattr)
+		return;
+	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
+		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
+		f << stringf(" = ");
+		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
+			f << stringf(" 0 ");
+		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
+			f << stringf(" 1 ");
+		else
+			dump_const(f, it->second, -1, 0, false, attr2comment);
+		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
+	}
+}
+
 void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 {
+	dump_attributes(f, "", sig.attributes, ' ');
+
 	if (GetSize(sig) == 0) {
 		f << "\"\"";
 		return;
@@ -364,23 +383,6 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false)
-{
-	if (noattr)
-		return;
-	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
-		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
-		f << stringf(" = ");
-		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
-			f << stringf(" 0 ");
-		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
-			f << stringf(" 1 ");
-		else
-			dump_const(f, it->second, -1, 0, false, attr2comment);
-		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
-	}
-}
-
 void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 {
 	dump_attributes(f, indent, wire->attributes);
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b6f77d3cb05..058b18b88bf 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1554,6 +1554,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					RTLIL::SigSpec sig;
 					if (child->children.size() > 0)
 						sig = child->children[0]->genRTLIL();
+					for (auto &attr : child->attributes) {
+						if (attr.second->type != AST_CONSTANT)
+							log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
+						sig.attributes[attr.first] = attr.second->asAttrConst();
+					}
 					if (child->str.size() == 0) {
 						char buf[100];
 						snprintf(buf, 100, "$%d", ++port_counter);
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 84c8ad11979..67f7c4194e4 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -255,6 +255,7 @@ cell_stmt:
 	} cell_body TOK_END EOL;
 
 cell_body:
+	cell_body attr_stmt |
 	cell_body TOK_PARAMETER TOK_ID constant EOL {
 		current_cell->parameters[$3] = *$4;
 		free($3);
@@ -275,9 +276,11 @@ cell_body:
 	cell_body TOK_CONNECT TOK_ID sigspec EOL {
 		if (current_cell->hasPort($3))
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
+		$4->attributes = attrbuf;
 		current_cell->setPort($3, *$4);
 		delete $4;
 		free($3);
+		attrbuf.clear();
 	} |
 	/* empty */;
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index b91c1c227f1..6bce5b9480e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1528,27 +1528,31 @@ cell_port_list_rules:
 	cell_port | cell_port_list_rules ',' cell_port;
 
 cell_port:
-	/* empty */ {
+	attr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
+		append_attr(node, $1);
 	} |
-	expr {
+	attr expr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
-		node->children.push_back($1);
+		node->children.push_back($2);
+		append_attr(node, $1);
 	} |
-	'.' TOK_ID '(' expr ')' {
+	attr '.' TOK_ID '(' expr ')' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
-		node->str = *$2;
+		node->str = *$3;
 		astbuf2->children.push_back(node);
-		node->children.push_back($4);
-		delete $2;
+		node->children.push_back($5);
+		append_attr(node, $1);
+		delete $3;
 	} |
-	'.' TOK_ID '(' ')' {
+	attr '.' TOK_ID '(' ')' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
-		node->str = *$2;
+		node->str = *$3;
 		astbuf2->children.push_back(node);
-		delete $2;
+		append_attr(node, $1);
+		delete $3;
 	};
 
 always_stmt:
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b75119633ca..a933f105f6f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2795,6 +2795,8 @@ const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
 		check();
 	}
 
+	attributes = other.attributes;
+
 	return *this;
 }
 
@@ -3021,6 +3023,7 @@ void RTLIL::SigSpec::sort()
 	unpack();
 	cover("kernel.rtlil.sigspec.sort");
 	std::sort(bits_.begin(), bits_.end());
+	attributes.sort();
 }
 
 void RTLIL::SigSpec::sort_and_unify()
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f6545079c0b..2267aa49083 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -655,7 +655,7 @@ struct RTLIL::SigSpecConstIterator : public std::iterator<std::input_iterator_ta
 	inline void operator++() { index++; }
 };
 
-struct RTLIL::SigSpec
+struct RTLIL::SigSpec : public RTLIL::AttrObject
 {
 private:
 	int width_;
@@ -701,6 +701,7 @@ struct RTLIL::SigSpec
 		hash_ = other.hash_;
 		chunks_ = std::move(other.chunks_);
 		bits_ = std::move(other.bits_);
+		attributes = std::move(other.attributes);
 	}
 
 	const RTLIL::SigSpec &operator=(RTLIL::SigSpec &&other) {
@@ -708,6 +709,7 @@ struct RTLIL::SigSpec
 		hash_ = other.hash_;
 		chunks_ = std::move(other.chunks_);
 		bits_ = std::move(other.bits_);
+		attributes = std::move(other.attributes);
 		return *this;
 	}
 
diff --git a/tests/reference-out/.gitignore b/tests/reference-out/.gitignore
new file mode 100644
index 00000000000..0b65ccb517a
--- /dev/null
+++ b/tests/reference-out/.gitignore
@@ -0,0 +1,2 @@
+*.out*
+*.log
diff --git a/tests/reference-out/attrib01_module.v.DISABLED b/tests/reference-out/attrib01_module.v.DISABLED
new file mode 100644
index 00000000000..adef34f5b76
--- /dev/null
+++ b/tests/reference-out/attrib01_module.v.DISABLED
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/reference-out/attrib02_port_decl.v b/tests/reference-out/attrib02_port_decl.v
new file mode 100644
index 00000000000..3505e726535
--- /dev/null
+++ b/tests/reference-out/attrib02_port_decl.v
@@ -0,0 +1,25 @@
+module bar(clk, rst, inp, out);
+  (* this_is_clock = 1 *)
+  input  wire clk;
+  (* this_is_reset = 1 *)
+  input  wire rst;
+  input  wire inp;
+  (* an_output_register = 1*)
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  (* this_is_the_master_clock *)
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.il b/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.il
new file mode 100644
index 00000000000..b3236320d92
--- /dev/null
+++ b/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.il
@@ -0,0 +1,63 @@
+# Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
+autoidx 3
+attribute \cells_not_processed 1
+attribute \src "attrib02_port_decl.v:1"
+module \bar
+  attribute \src "attrib02_port_decl.v:10"
+  wire $0\out[0:0]
+  attribute \src "attrib02_port_decl.v:12"
+  wire $not$attrib02_port_decl.v:12$2_Y
+  attribute \src "attrib02_port_decl.v:3"
+  attribute \this_is_clock 1
+  wire input 1 \clk
+  attribute \src "attrib02_port_decl.v:6"
+  wire input 3 \inp
+  attribute \an_output_register 1
+  attribute \src "attrib02_port_decl.v:8"
+  wire output 4 \out
+  attribute \src "attrib02_port_decl.v:5"
+  attribute \this_is_reset 1
+  wire input 2 \rst
+  attribute \src "attrib02_port_decl.v:12"
+  cell $not $not$attrib02_port_decl.v:12$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \inp
+    connect \Y $not$attrib02_port_decl.v:12$2_Y
+  end
+  attribute \src "attrib02_port_decl.v:10"
+  process $proc$attrib02_port_decl.v:10$1
+    assign $0\out[0:0] \out
+    attribute \src "attrib02_port_decl.v:11"
+    switch \rst
+      case 1'1
+        assign $0\out[0:0] 1'0
+      case 
+        assign $0\out[0:0] $not$attrib02_port_decl.v:12$2_Y
+    end
+    sync posedge \clk
+      update \out $0\out[0:0]
+  end
+end
+attribute \cells_not_processed 1
+attribute \src "attrib02_port_decl.v:16"
+module \foo
+  attribute \src "attrib02_port_decl.v:18"
+  attribute \this_is_the_master_clock 1
+  wire input 1 \clk
+  attribute \src "attrib02_port_decl.v:20"
+  wire input 3 \inp
+  attribute \src "attrib02_port_decl.v:21"
+  wire output 4 \out
+  attribute \src "attrib02_port_decl.v:19"
+  wire input 2 \rst
+  attribute \module_not_derived 1
+  attribute \src "attrib02_port_decl.v:23"
+  cell \bar \bar_instance
+    connect $1 \clk
+    connect $2 \rst
+    connect $3 \inp
+    connect $4 \out
+  end
+end
diff --git a/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.json b/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.json
new file mode 100644
index 00000000000..f78a39bc501
--- /dev/null
+++ b/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.json
@@ -0,0 +1,205 @@
+{
+  "creator": "Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)",
+  "modules": {
+    "bar": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib02_port_decl.v:1"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "$not$attrib02_port_decl.v:12$2": {
+          "hide_name": 1,
+          "type": "$not",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "attrib02_port_decl.v:12"
+          },
+          "port_directions": {
+            "A": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 6 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "$0\\out[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:10"
+          }
+        },
+        "$not$attrib02_port_decl.v:12$2_Y": {
+          "hide_name": 1,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:12"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:3",
+            "this_is_clock": 1
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:6"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "an_output_register": 1,
+            "src": "attrib02_port_decl.v:8"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:5",
+            "this_is_reset": 1
+          }
+        }
+      }
+    },
+    "foo": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib02_port_decl.v:16"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "bar_instance": {
+          "hide_name": 0,
+          "type": "bar",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "attrib02_port_decl.v:23"
+          },
+          "port_directions": {
+            "$1": "output",
+            "$2": "output",
+            "$3": "output",
+            "$4": "output"
+          },
+          "connections": {
+            "$1": {
+              "bits": [ 2 ],
+              "attributes": {
+            }
+            },
+            "$2": {
+              "bits": [ 3 ],
+              "attributes": {
+            }
+            },
+            "$3": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "$4": {
+              "bits": [ 5 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:18",
+            "this_is_the_master_clock": 1
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:20"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:21"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib02_port_decl.v:19"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.v b/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.v
new file mode 100644
index 00000000000..2f03ce80464
--- /dev/null
+++ b/tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.v
@@ -0,0 +1,57 @@
+/* Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+(* cells_not_processed =  1  *)
+(* src = "attrib02_port_decl.v:1" *)
+module bar(clk, rst, inp, out);
+  (* src = "attrib02_port_decl.v:10" *)
+  reg _0_;
+  (* src = "attrib02_port_decl.v:12" *)
+  wire _1_;
+  (* src = "attrib02_port_decl.v:3" *)
+  (* this_is_clock = 32'd1 *)
+  input clk;
+  (* src = "attrib02_port_decl.v:6" *)
+  input inp;
+  (* an_output_register = 32'd1 *)
+  (* src = "attrib02_port_decl.v:8" *)
+  output out;
+  reg out;
+  (* src = "attrib02_port_decl.v:5" *)
+  (* this_is_reset = 32'd1 *)
+  input rst;
+  assign _1_ = ~ (* src = "attrib02_port_decl.v:12" *) inp;
+  always @* begin
+    _0_ = out;
+    casez (rst)
+      1'h1:
+          _0_ = 1'h0;
+      default:
+          _0_ = _1_;
+    endcase
+  end
+  always @(posedge clk) begin
+      out <= _0_;
+  end
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "attrib02_port_decl.v:16" *)
+module foo(clk, rst, inp, out);
+  (* src = "attrib02_port_decl.v:18" *)
+  (* this_is_the_master_clock = 32'd1 *)
+  input clk;
+  (* src = "attrib02_port_decl.v:20" *)
+  input inp;
+  (* src = "attrib02_port_decl.v:21" *)
+  output out;
+  (* src = "attrib02_port_decl.v:19" *)
+  input rst;
+  (* module_not_derived = 32'd1 *)
+  (* src = "attrib02_port_decl.v:23" *)
+  bar bar_instance (
+    clk,
+    rst,
+    inp,
+    out
+  );
+endmodule
diff --git a/tests/reference-out/attrib03_parameter.v b/tests/reference-out/attrib03_parameter.v
new file mode 100644
index 00000000000..562d225cd5b
--- /dev/null
+++ b/tests/reference-out/attrib03_parameter.v
@@ -0,0 +1,28 @@
+module bar(clk, rst, inp, out);
+
+  (* bus_width *)
+  parameter WIDTH = 2;
+
+  (* an_attribute_on_localparam = 55 *)
+  localparam INCREMENT = 5;
+
+  input  wire clk;
+  input  wire rst;
+  input  wire [WIDTH-1:0] inp;
+  output reg  [WIDTH-1:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= inp + INCREMENT;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp;
+  output wire [7:0] out;
+
+  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.il b/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.il
new file mode 100644
index 00000000000..8ed0100c304
--- /dev/null
+++ b/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.il
@@ -0,0 +1,67 @@
+# Generated by Yosys 0.8+498 (git sha1 abef145f, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
+autoidx 3
+attribute \dynports 1
+attribute \cells_not_processed 1
+attribute \src "attrib03_parameter.v:1"
+module \bar
+
+  attribute \bus_width 1
+  parameter \WIDTH
+  attribute \src "attrib03_parameter.v:14"
+  wire width 2 $0\out[1:0]
+  attribute \src "attrib03_parameter.v:16"
+  wire width 32 $add$attrib03_parameter.v:16$2_Y
+  attribute \src "attrib03_parameter.v:9"
+  wire input 1 \clk
+  attribute \src "attrib03_parameter.v:11"
+  wire width 2 input 3 \inp
+  attribute \src "attrib03_parameter.v:12"
+  wire width 2 output 4 \out
+  attribute \src "attrib03_parameter.v:10"
+  wire input 2 \rst
+  attribute \src "attrib03_parameter.v:16"
+  cell $add $add$attrib03_parameter.v:16$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A \inp
+    connect \B 5
+    connect \Y $add$attrib03_parameter.v:16$2_Y
+  end
+  attribute \src "attrib03_parameter.v:14"
+  process $proc$attrib03_parameter.v:14$1
+    assign $0\out[1:0] \out
+    attribute \src "attrib03_parameter.v:15"
+    switch \rst
+      case 1'1
+        assign $0\out[1:0] 2'00
+      case 
+        assign $0\out[1:0] $add$attrib03_parameter.v:16$2_Y [1:0]
+    end
+    sync posedge \clk
+      update \out $0\out[1:0]
+  end
+end
+attribute \cells_not_processed 1
+attribute \src "attrib03_parameter.v:20"
+module \foo
+  attribute \src "attrib03_parameter.v:21"
+  wire input 1 \clk
+  attribute \src "attrib03_parameter.v:23"
+  wire width 8 input 3 \inp
+  attribute \src "attrib03_parameter.v:24"
+  wire width 8 output 4 \out
+  attribute \src "attrib03_parameter.v:22"
+  wire input 2 \rst
+  attribute \module_not_derived 1
+  attribute \src "attrib03_parameter.v:26"
+  cell \bar \bar_instance
+    parameter signed \WIDTH 8
+    connect $1 \clk
+    connect $2 \rst
+    connect $3 \inp
+    connect $4 \out
+  end
+end
diff --git a/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.json b/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.json
new file mode 100644
index 00000000000..5d5d3384b46
--- /dev/null
+++ b/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.json
@@ -0,0 +1,217 @@
+{
+  "creator": "Yosys 0.8+498 (git sha1 abef145f, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)",
+  "modules": {
+    "bar": {
+      "attributes": {
+        "dynports": 1,
+        "cells_not_processed": 1,
+        "src": "attrib03_parameter.v:1"
+      },
+      "parameters": {
+        "WIDTH": {
+          "attributes": {
+            "bus_width": 1
+          },
+          "default": 2
+        }
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4, 5 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 6, 7 ]
+        }
+      },
+      "cells": {
+        "$add$attrib03_parameter.v:16$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 2,
+            "B_SIGNED": 0,
+            "B_WIDTH": 32,
+            "Y_WIDTH": 32
+          },
+          "attributes": {
+            "src": "attrib03_parameter.v:16"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 4, 5 ],
+              "attributes": {
+            }
+            },
+            "B": {
+              "bits": [ "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "$0\\out[1:0]": {
+          "hide_name": 1,
+          "bits": [ 40, 41 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:14"
+          }
+        },
+        "$add$attrib03_parameter.v:16$2_Y": {
+          "hide_name": 1,
+          "bits": [ 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:16"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:9"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4, 5 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:11"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 6, 7 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:12"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:10"
+          }
+        }
+      }
+    },
+    "foo": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib03_parameter.v:20"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ]
+        }
+      },
+      "cells": {
+        "bar_instance": {
+          "hide_name": 0,
+          "type": "bar",
+          "parameters": {
+            "WIDTH": 8
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "attrib03_parameter.v:26"
+          },
+          "port_directions": {
+            "$1": "output",
+            "$2": "output",
+            "$3": "output",
+            "$4": "output"
+          },
+          "connections": {
+            "$1": {
+              "bits": [ 2 ],
+              "attributes": {
+            }
+            },
+            "$2": {
+              "bits": [ 3 ],
+              "attributes": {
+            }
+            },
+            "$3": {
+              "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ],
+              "attributes": {
+            }
+            },
+            "$4": {
+              "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:21"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:23"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:24"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib03_parameter.v:22"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.v b/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.v
new file mode 100644
index 00000000000..6630964d066
--- /dev/null
+++ b/tests/reference-out/attrib03_parameter/attrib03_parameter.ref.v
@@ -0,0 +1,58 @@
+/* Generated by Yosys 0.8+498 (git sha1 abef145f, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+(* dynports =  1  *)
+(* cells_not_processed =  1  *)
+(* src = "attrib03_parameter.v:1" *)
+module bar(clk, rst, inp, out);
+  (* bus_width = 32'd1 *)
+  parameter \WIDTH = 32'd2;
+  (* src = "attrib03_parameter.v:14" *)
+  reg [1:0] _0_;
+  (* src = "attrib03_parameter.v:16" *)
+  wire [31:0] _1_;
+  (* src = "attrib03_parameter.v:9" *)
+  input clk;
+  (* src = "attrib03_parameter.v:11" *)
+  input [1:0] inp;
+  (* src = "attrib03_parameter.v:12" *)
+  output [1:0] out;
+  reg [1:0] out;
+  (* src = "attrib03_parameter.v:10" *)
+  input rst;
+  assign _1_ = inp + (* src = "attrib03_parameter.v:16" *) 32'd5;
+  always @* begin
+    _0_ = out;
+    casez (rst)
+      1'h1:
+          _0_ = 2'h0;
+      default:
+          _0_ = _1_[1:0];
+    endcase
+  end
+  always @(posedge clk) begin
+      out <= _0_;
+  end
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "attrib03_parameter.v:20" *)
+module foo(clk, rst, inp, out);
+  (* src = "attrib03_parameter.v:21" *)
+  input clk;
+  (* src = "attrib03_parameter.v:23" *)
+  input [7:0] inp;
+  (* src = "attrib03_parameter.v:24" *)
+  output [7:0] out;
+  (* src = "attrib03_parameter.v:22" *)
+  input rst;
+  (* module_not_derived = 32'd1 *)
+  (* src = "attrib03_parameter.v:26" *)
+  bar #(
+    .WIDTH(32'sd8)
+  ) bar_instance (
+    clk,
+    rst,
+    inp,
+    out
+  );
+endmodule
diff --git a/tests/reference-out/attrib04_net_var.v b/tests/reference-out/attrib04_net_var.v
new file mode 100644
index 00000000000..8b552340651
--- /dev/null
+++ b/tests/reference-out/attrib04_net_var.v
@@ -0,0 +1,32 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  (* this_is_a_prescaler *)
+  reg [7:0] counter;
+
+  (* temp_wire *)
+  wire out_val;
+
+  always @(posedge clk)
+    counter <= counter + 1;
+
+  assign out_val = inp ^ counter[4];
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= out_val;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.il b/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.il
new file mode 100644
index 00000000000..f48170a4d66
--- /dev/null
+++ b/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.il
@@ -0,0 +1,91 @@
+# Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
+autoidx 5
+attribute \cells_not_processed 1
+attribute \src "attrib04_net_var.v:1"
+module \bar
+  attribute \src "attrib04_net_var.v:13"
+  wire width 8 $0\counter[7:0]
+  attribute \src "attrib04_net_var.v:18"
+  wire $0\out[0:0]
+  attribute \src "attrib04_net_var.v:14"
+  wire width 32 $add$attrib04_net_var.v:14$2_Y
+  attribute \src "attrib04_net_var.v:16"
+  wire $xor$attrib04_net_var.v:16$3_Y
+  attribute \src "attrib04_net_var.v:2"
+  wire input 1 \clk
+  attribute \src "attrib04_net_var.v:8"
+  attribute \this_is_a_prescaler 1
+  wire width 8 \counter
+  attribute \src "attrib04_net_var.v:4"
+  wire input 3 \inp
+  attribute \src "attrib04_net_var.v:5"
+  wire output 4 \out
+  attribute \src "attrib04_net_var.v:11"
+  attribute \temp_wire 1
+  wire \out_val
+  attribute \src "attrib04_net_var.v:3"
+  wire input 2 \rst
+  attribute \src "attrib04_net_var.v:14"
+  cell $add $add$attrib04_net_var.v:14$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A \counter
+    connect \B 1
+    connect \Y $add$attrib04_net_var.v:14$2_Y
+  end
+  attribute \src "attrib04_net_var.v:16"
+  cell $xor $xor$attrib04_net_var.v:16$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \inp
+    connect \B \counter [4]
+    connect \Y $xor$attrib04_net_var.v:16$3_Y
+  end
+  attribute \src "attrib04_net_var.v:13"
+  process $proc$attrib04_net_var.v:13$1
+    assign { } { }
+    assign $0\counter[7:0] $add$attrib04_net_var.v:14$2_Y [7:0]
+    sync posedge \clk
+      update \counter $0\counter[7:0]
+  end
+  attribute \src "attrib04_net_var.v:18"
+  process $proc$attrib04_net_var.v:18$4
+    assign $0\out[0:0] \out
+    attribute \src "attrib04_net_var.v:19"
+    switch \rst
+      case 1'1
+        assign $0\out[0:0] 1'0
+      case 
+        assign $0\out[0:0] \out_val
+    end
+    sync posedge \clk
+      update \out $0\out[0:0]
+  end
+  connect \out_val $xor$attrib04_net_var.v:16$3_Y
+end
+attribute \cells_not_processed 1
+attribute \src "attrib04_net_var.v:24"
+module \foo
+  attribute \src "attrib04_net_var.v:25"
+  wire input 1 \clk
+  attribute \src "attrib04_net_var.v:27"
+  wire input 3 \inp
+  attribute \src "attrib04_net_var.v:28"
+  wire output 4 \out
+  attribute \src "attrib04_net_var.v:26"
+  wire input 2 \rst
+  attribute \module_not_derived 1
+  attribute \src "attrib04_net_var.v:30"
+  cell \bar \bar_instance
+    connect $1 \clk
+    connect $2 \rst
+    connect $3 \inp
+    connect $4 \out
+  end
+end
diff --git a/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.json b/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.json
new file mode 100644
index 00000000000..4d2b508ee83
--- /dev/null
+++ b/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.json
@@ -0,0 +1,275 @@
+{
+  "creator": "Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)",
+  "modules": {
+    "bar": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib04_net_var.v:1"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "$add$attrib04_net_var.v:14$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 8,
+            "B_SIGNED": 0,
+            "B_WIDTH": 32,
+            "Y_WIDTH": 32
+          },
+          "attributes": {
+            "src": "attrib04_net_var.v:14"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 6, 7, 8, 9, 10, 11, 12, 13 ],
+              "attributes": {
+            }
+            },
+            "B": {
+              "bits": [ "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0" ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 ],
+              "attributes": {
+            }
+            }
+          }
+        },
+        "$xor$attrib04_net_var.v:16$3": {
+          "hide_name": 1,
+          "type": "$xor",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "attrib04_net_var.v:16"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "B": {
+              "bits": [ 10 ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 46 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "$0\\counter[7:0]": {
+          "hide_name": 1,
+          "bits": [ 47, 48, 49, 50, 51, 52, 53, 54 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:13"
+          }
+        },
+        "$0\\out[0:0]": {
+          "hide_name": 1,
+          "bits": [ 55 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:18"
+          }
+        },
+        "$add$attrib04_net_var.v:14$2_Y": {
+          "hide_name": 1,
+          "bits": [ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:14"
+          }
+        },
+        "$xor$attrib04_net_var.v:16$3_Y": {
+          "hide_name": 1,
+          "bits": [ 46 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:16"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:2"
+          }
+        },
+        "counter": {
+          "hide_name": 0,
+          "bits": [ 6, 7, 8, 9, 10, 11, 12, 13 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:8",
+            "this_is_a_prescaler": 1
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:4"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:5"
+          }
+        },
+        "out_val": {
+          "hide_name": 0,
+          "bits": [ 46 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:11",
+            "temp_wire": 1
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:3"
+          }
+        }
+      }
+    },
+    "foo": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib04_net_var.v:24"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "bar_instance": {
+          "hide_name": 0,
+          "type": "bar",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "attrib04_net_var.v:30"
+          },
+          "port_directions": {
+            "$1": "output",
+            "$2": "output",
+            "$3": "output",
+            "$4": "output"
+          },
+          "connections": {
+            "$1": {
+              "bits": [ 2 ],
+              "attributes": {
+            }
+            },
+            "$2": {
+              "bits": [ 3 ],
+              "attributes": {
+            }
+            },
+            "$3": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "$4": {
+              "bits": [ 5 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:25"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:27"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:28"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib04_net_var.v:26"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.v b/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.v
new file mode 100644
index 00000000000..0afe9c31612
--- /dev/null
+++ b/tests/reference-out/attrib04_net_var/attrib04_net_var.ref.v
@@ -0,0 +1,71 @@
+/* Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+(* cells_not_processed =  1  *)
+(* src = "attrib04_net_var.v:1" *)
+module bar(clk, rst, inp, out);
+  (* src = "attrib04_net_var.v:13" *)
+  reg [7:0] _0_;
+  (* src = "attrib04_net_var.v:18" *)
+  reg _1_;
+  (* src = "attrib04_net_var.v:14" *)
+  wire [31:0] _2_;
+  (* src = "attrib04_net_var.v:16" *)
+  wire _3_;
+  (* src = "attrib04_net_var.v:2" *)
+  input clk;
+  (* src = "attrib04_net_var.v:8" *)
+  (* this_is_a_prescaler = 32'd1 *)
+  reg [7:0] counter;
+  (* src = "attrib04_net_var.v:4" *)
+  input inp;
+  (* src = "attrib04_net_var.v:5" *)
+  output out;
+  reg out;
+  (* src = "attrib04_net_var.v:11" *)
+  (* temp_wire = 32'd1 *)
+  wire out_val;
+  (* src = "attrib04_net_var.v:3" *)
+  input rst;
+  assign _2_ = counter + (* src = "attrib04_net_var.v:14" *) 32'd1;
+  assign _3_ = inp ^ (* src = "attrib04_net_var.v:16" *) counter[4];
+  always @* begin
+    _0_ = _2_[7:0];
+  end
+  always @(posedge clk) begin
+      counter <= _0_;
+  end
+  always @* begin
+    _1_ = out;
+    casez (rst)
+      1'h1:
+          _1_ = 1'h0;
+      default:
+          _1_ = out_val;
+    endcase
+  end
+  always @(posedge clk) begin
+      out <= _1_;
+  end
+  assign out_val = _3_;
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "attrib04_net_var.v:24" *)
+module foo(clk, rst, inp, out);
+  (* src = "attrib04_net_var.v:25" *)
+  input clk;
+  (* src = "attrib04_net_var.v:27" *)
+  input inp;
+  (* src = "attrib04_net_var.v:28" *)
+  output out;
+  (* src = "attrib04_net_var.v:26" *)
+  input rst;
+  (* module_not_derived = 32'd1 *)
+  (* src = "attrib04_net_var.v:30" *)
+  bar bar_instance (
+    clk,
+    rst,
+    inp,
+    out
+  );
+endmodule
diff --git a/tests/reference-out/attrib05_port_conn.v b/tests/reference-out/attrib05_port_conn.v
new file mode 100644
index 00000000000..e20e6631950
--- /dev/null
+++ b/tests/reference-out/attrib05_port_conn.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.il b/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.il
new file mode 100644
index 00000000000..e9fd0150bb9
--- /dev/null
+++ b/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.il
@@ -0,0 +1,61 @@
+# Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
+autoidx 3
+attribute \cells_not_processed 1
+attribute \src "attrib05_port_conn.v:1"
+module \bar
+  attribute \src "attrib05_port_conn.v:7"
+  wire $0\out[0:0]
+  attribute \src "attrib05_port_conn.v:9"
+  wire $not$attrib05_port_conn.v:9$2_Y
+  attribute \src "attrib05_port_conn.v:2"
+  wire input 1 \clk
+  attribute \src "attrib05_port_conn.v:4"
+  wire input 3 \inp
+  attribute \src "attrib05_port_conn.v:5"
+  wire output 4 \out
+  attribute \src "attrib05_port_conn.v:3"
+  wire input 2 \rst
+  attribute \src "attrib05_port_conn.v:9"
+  cell $not $not$attrib05_port_conn.v:9$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \inp
+    connect \Y $not$attrib05_port_conn.v:9$2_Y
+  end
+  attribute \src "attrib05_port_conn.v:7"
+  process $proc$attrib05_port_conn.v:7$1
+    assign $0\out[0:0] \out
+    attribute \src "attrib05_port_conn.v:8"
+    switch \rst
+      case 1'1
+        assign $0\out[0:0] 1'0
+      case 
+        assign $0\out[0:0] $not$attrib05_port_conn.v:9$2_Y
+    end
+    sync posedge \clk
+      update \out $0\out[0:0]
+  end
+end
+attribute \cells_not_processed 1
+attribute \src "attrib05_port_conn.v:13"
+module \foo
+  attribute \src "attrib05_port_conn.v:14"
+  wire input 1 \clk
+  attribute \src "attrib05_port_conn.v:16"
+  wire input 3 \inp
+  attribute \src "attrib05_port_conn.v:17"
+  wire output 4 \out
+  attribute \src "attrib05_port_conn.v:15"
+  wire input 2 \rst
+  attribute \module_not_derived 1
+  attribute \src "attrib05_port_conn.v:19"
+  cell \bar \bar_instance
+    attribute \clock_connected 1
+    connect $1 \clk
+    connect $2 \rst
+    attribute \this_is_the_input 1
+    connect $3 \inp
+    connect $4 \out
+  end
+end
diff --git a/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.json b/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.json
new file mode 100644
index 00000000000..1bb410ec65b
--- /dev/null
+++ b/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.json
@@ -0,0 +1,203 @@
+{
+  "creator": "Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)",
+  "modules": {
+    "bar": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib05_port_conn.v:1"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "$not$attrib05_port_conn.v:9$2": {
+          "hide_name": 1,
+          "type": "$not",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "attrib05_port_conn.v:9"
+          },
+          "port_directions": {
+            "A": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 6 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "$0\\out[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:7"
+          }
+        },
+        "$not$attrib05_port_conn.v:9$2_Y": {
+          "hide_name": 1,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:9"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:2"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:4"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:5"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:3"
+          }
+        }
+      }
+    },
+    "foo": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib05_port_conn.v:13"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "bar_instance": {
+          "hide_name": 0,
+          "type": "bar",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "attrib05_port_conn.v:19"
+          },
+          "port_directions": {
+            "$1": "output",
+            "$2": "output",
+            "$3": "output",
+            "$4": "output"
+          },
+          "connections": {
+            "$1": {
+              "bits": [ 2 ],
+              "attributes": {
+                "clock_connected": 1
+            }
+            },
+            "$2": {
+              "bits": [ 3 ],
+              "attributes": {
+            }
+            },
+            "$3": {
+              "bits": [ 4 ],
+              "attributes": {
+                "this_is_the_input": 1
+            }
+            },
+            "$4": {
+              "bits": [ 5 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:14"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:16"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:17"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib05_port_conn.v:15"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.v b/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.v
new file mode 100644
index 00000000000..bfb81220028
--- /dev/null
+++ b/tests/reference-out/attrib05_port_conn/attrib05_port_conn.ref.v
@@ -0,0 +1,53 @@
+/* Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+(* cells_not_processed =  1  *)
+(* src = "attrib05_port_conn.v:1" *)
+module bar(clk, rst, inp, out);
+  (* src = "attrib05_port_conn.v:7" *)
+  reg _0_;
+  (* src = "attrib05_port_conn.v:9" *)
+  wire _1_;
+  (* src = "attrib05_port_conn.v:2" *)
+  input clk;
+  (* src = "attrib05_port_conn.v:4" *)
+  input inp;
+  (* src = "attrib05_port_conn.v:5" *)
+  output out;
+  reg out;
+  (* src = "attrib05_port_conn.v:3" *)
+  input rst;
+  assign _1_ = ~ (* src = "attrib05_port_conn.v:9" *) inp;
+  always @* begin
+    _0_ = out;
+    casez (rst)
+      1'h1:
+          _0_ = 1'h0;
+      default:
+          _0_ = _1_;
+    endcase
+  end
+  always @(posedge clk) begin
+      out <= _0_;
+  end
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "attrib05_port_conn.v:13" *)
+module foo(clk, rst, inp, out);
+  (* src = "attrib05_port_conn.v:14" *)
+  input clk;
+  (* src = "attrib05_port_conn.v:16" *)
+  input inp;
+  (* src = "attrib05_port_conn.v:17" *)
+  output out;
+  (* src = "attrib05_port_conn.v:15" *)
+  input rst;
+  (* module_not_derived = 32'd1 *)
+  (* src = "attrib05_port_conn.v:19" *)
+  bar bar_instance (
+    (* clock_connected = 32'd1 *) clk,
+    rst,
+    (* this_is_the_input = 32'd1 *) inp,
+    out
+  );
+endmodule
diff --git a/tests/reference-out/attrib06_operator_suffix.v b/tests/reference-out/attrib06_operator_suffix.v
new file mode 100644
index 00000000000..e21173c58f4
--- /dev/null
+++ b/tests/reference-out/attrib06_operator_suffix.v
@@ -0,0 +1,23 @@
+module bar(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output reg  [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= inp_a + (* ripple_adder *) inp_b;
+
+endmodule
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  bar bar_instance (clk, rst, inp_a, inp_b, out);
+endmodule
+
diff --git a/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.il b/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.il
new file mode 100644
index 00000000000..f631a77ff2f
--- /dev/null
+++ b/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.il
@@ -0,0 +1,68 @@
+# Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
+autoidx 3
+attribute \cells_not_processed 1
+attribute \src "attrib06_operator_suffix.v:1"
+module \bar
+  attribute \src "attrib06_operator_suffix.v:8"
+  wire width 8 $0\out[7:0]
+  attribute \src "attrib06_operator_suffix.v:10"
+  wire width 8 $add$attrib06_operator_suffix.v:10$2_Y
+  attribute \src "attrib06_operator_suffix.v:2"
+  wire input 1 \clk
+  attribute \src "attrib06_operator_suffix.v:4"
+  wire width 8 input 3 \inp_a
+  attribute \src "attrib06_operator_suffix.v:5"
+  wire width 8 input 4 \inp_b
+  attribute \src "attrib06_operator_suffix.v:6"
+  wire width 8 output 5 \out
+  attribute \src "attrib06_operator_suffix.v:3"
+  wire input 2 \rst
+  attribute \ripple_adder 1
+  attribute \src "attrib06_operator_suffix.v:10"
+  cell $add $add$attrib06_operator_suffix.v:10$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 8
+    connect \A \inp_a
+    connect \B \inp_b
+    connect \Y $add$attrib06_operator_suffix.v:10$2_Y
+  end
+  attribute \src "attrib06_operator_suffix.v:8"
+  process $proc$attrib06_operator_suffix.v:8$1
+    assign $0\out[7:0] \out
+    attribute \src "attrib06_operator_suffix.v:9"
+    switch \rst
+      case 1'1
+        assign $0\out[7:0] 8'00000000
+      case 
+        assign $0\out[7:0] $add$attrib06_operator_suffix.v:10$2_Y
+    end
+    sync posedge \clk
+      update \out $0\out[7:0]
+  end
+end
+attribute \cells_not_processed 1
+attribute \src "attrib06_operator_suffix.v:14"
+module \foo
+  attribute \src "attrib06_operator_suffix.v:15"
+  wire input 1 \clk
+  attribute \src "attrib06_operator_suffix.v:17"
+  wire width 8 input 3 \inp_a
+  attribute \src "attrib06_operator_suffix.v:18"
+  wire width 8 input 4 \inp_b
+  attribute \src "attrib06_operator_suffix.v:19"
+  wire width 8 output 5 \out
+  attribute \src "attrib06_operator_suffix.v:16"
+  wire input 2 \rst
+  attribute \module_not_derived 1
+  attribute \src "attrib06_operator_suffix.v:21"
+  cell \bar \bar_instance
+    connect $1 \clk
+    connect $2 \rst
+    connect $3 \inp_a
+    connect $4 \inp_b
+    connect $5 \out
+  end
+end
diff --git a/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.json b/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.json
new file mode 100644
index 00000000000..7cadd61b45c
--- /dev/null
+++ b/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.json
@@ -0,0 +1,238 @@
+{
+  "creator": "Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)",
+  "modules": {
+    "bar": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib06_operator_suffix.v:1"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp_a": {
+          "direction": "input",
+          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ]
+        },
+        "inp_b": {
+          "direction": "input",
+          "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ]
+        }
+      },
+      "cells": {
+        "$add$attrib06_operator_suffix.v:10$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 8,
+            "B_SIGNED": 0,
+            "B_WIDTH": 8,
+            "Y_WIDTH": 8
+          },
+          "attributes": {
+            "ripple_adder": 1,
+            "src": "attrib06_operator_suffix.v:10"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ],
+              "attributes": {
+            }
+            },
+            "B": {
+              "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 28, 29, 30, 31, 32, 33, 34, 35 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "$0\\out[7:0]": {
+          "hide_name": 1,
+          "bits": [ 36, 37, 38, 39, 40, 41, 42, 43 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:8"
+          }
+        },
+        "$add$attrib06_operator_suffix.v:10$2_Y": {
+          "hide_name": 1,
+          "bits": [ 28, 29, 30, 31, 32, 33, 34, 35 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:10"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:2"
+          }
+        },
+        "inp_a": {
+          "hide_name": 0,
+          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:4"
+          }
+        },
+        "inp_b": {
+          "hide_name": 0,
+          "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:5"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:6"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:3"
+          }
+        }
+      }
+    },
+    "foo": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib06_operator_suffix.v:14"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp_a": {
+          "direction": "input",
+          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ]
+        },
+        "inp_b": {
+          "direction": "input",
+          "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ]
+        }
+      },
+      "cells": {
+        "bar_instance": {
+          "hide_name": 0,
+          "type": "bar",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "src": "attrib06_operator_suffix.v:21"
+          },
+          "port_directions": {
+            "$1": "output",
+            "$2": "output",
+            "$3": "output",
+            "$4": "output",
+            "$5": "output"
+          },
+          "connections": {
+            "$1": {
+              "bits": [ 2 ],
+              "attributes": {
+            }
+            },
+            "$2": {
+              "bits": [ 3 ],
+              "attributes": {
+            }
+            },
+            "$3": {
+              "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ],
+              "attributes": {
+            }
+            },
+            "$4": {
+              "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ],
+              "attributes": {
+            }
+            },
+            "$5": {
+              "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:15"
+          }
+        },
+        "inp_a": {
+          "hide_name": 0,
+          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:17"
+          }
+        },
+        "inp_b": {
+          "hide_name": 0,
+          "bits": [ 12, 13, 14, 15, 16, 17, 18, 19 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:18"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 20, 21, 22, 23, 24, 25, 26, 27 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:19"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib06_operator_suffix.v:16"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.v b/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.v
new file mode 100644
index 00000000000..070ebbf6056
--- /dev/null
+++ b/tests/reference-out/attrib06_operator_suffix/attrib06_operator_suffix.ref.v
@@ -0,0 +1,58 @@
+/* Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+(* cells_not_processed =  1  *)
+(* src = "attrib06_operator_suffix.v:1" *)
+module bar(clk, rst, inp_a, inp_b, out);
+  (* src = "attrib06_operator_suffix.v:8" *)
+  reg [7:0] _0_;
+  (* src = "attrib06_operator_suffix.v:10" *)
+  wire [7:0] _1_;
+  (* src = "attrib06_operator_suffix.v:2" *)
+  input clk;
+  (* src = "attrib06_operator_suffix.v:4" *)
+  input [7:0] inp_a;
+  (* src = "attrib06_operator_suffix.v:5" *)
+  input [7:0] inp_b;
+  (* src = "attrib06_operator_suffix.v:6" *)
+  output [7:0] out;
+  reg [7:0] out;
+  (* src = "attrib06_operator_suffix.v:3" *)
+  input rst;
+  assign _1_ = inp_a + (* ripple_adder = 32'd1 *) (* src = "attrib06_operator_suffix.v:10" *) inp_b;
+  always @* begin
+    _0_ = out;
+    casez (rst)
+      1'h1:
+          _0_ = 8'h00;
+      default:
+          _0_ = _1_;
+    endcase
+  end
+  always @(posedge clk) begin
+      out <= _0_;
+  end
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "attrib06_operator_suffix.v:14" *)
+module foo(clk, rst, inp_a, inp_b, out);
+  (* src = "attrib06_operator_suffix.v:15" *)
+  input clk;
+  (* src = "attrib06_operator_suffix.v:17" *)
+  input [7:0] inp_a;
+  (* src = "attrib06_operator_suffix.v:18" *)
+  input [7:0] inp_b;
+  (* src = "attrib06_operator_suffix.v:19" *)
+  output [7:0] out;
+  (* src = "attrib06_operator_suffix.v:16" *)
+  input rst;
+  (* module_not_derived = 32'd1 *)
+  (* src = "attrib06_operator_suffix.v:21" *)
+  bar bar_instance (
+    clk,
+    rst,
+    inp_a,
+    inp_b,
+    out
+  );
+endmodule
diff --git a/tests/reference-out/attrib07_func_call.v.DISABLED b/tests/reference-out/attrib07_func_call.v.DISABLED
new file mode 100644
index 00000000000..f55ef231609
--- /dev/null
+++ b/tests/reference-out/attrib07_func_call.v.DISABLED
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+  input [7:0] inp_a;
+  input [7:0] inp_b;
+
+  do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/reference-out/attrib08_mod_inst.v b/tests/reference-out/attrib08_mod_inst.v
new file mode 100644
index 00000000000..c5a32234eed
--- /dev/null
+++ b/tests/reference-out/attrib08_mod_inst.v
@@ -0,0 +1,22 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  (* my_module_instance = 99 *)
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.il b/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.il
new file mode 100644
index 00000000000..e1d9d056c42
--- /dev/null
+++ b/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.il
@@ -0,0 +1,60 @@
+# Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
+autoidx 3
+attribute \cells_not_processed 1
+attribute \src "attrib08_mod_inst.v:1"
+module \bar
+  attribute \src "attrib08_mod_inst.v:7"
+  wire $0\out[0:0]
+  attribute \src "attrib08_mod_inst.v:9"
+  wire $not$attrib08_mod_inst.v:9$2_Y
+  attribute \src "attrib08_mod_inst.v:2"
+  wire input 1 \clk
+  attribute \src "attrib08_mod_inst.v:4"
+  wire input 3 \inp
+  attribute \src "attrib08_mod_inst.v:5"
+  wire output 4 \out
+  attribute \src "attrib08_mod_inst.v:3"
+  wire input 2 \rst
+  attribute \src "attrib08_mod_inst.v:9"
+  cell $not $not$attrib08_mod_inst.v:9$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \inp
+    connect \Y $not$attrib08_mod_inst.v:9$2_Y
+  end
+  attribute \src "attrib08_mod_inst.v:7"
+  process $proc$attrib08_mod_inst.v:7$1
+    assign $0\out[0:0] \out
+    attribute \src "attrib08_mod_inst.v:8"
+    switch \rst
+      case 1'1
+        assign $0\out[0:0] 1'0
+      case 
+        assign $0\out[0:0] $not$attrib08_mod_inst.v:9$2_Y
+    end
+    sync posedge \clk
+      update \out $0\out[0:0]
+  end
+end
+attribute \cells_not_processed 1
+attribute \src "attrib08_mod_inst.v:13"
+module \foo
+  attribute \src "attrib08_mod_inst.v:14"
+  wire input 1 \clk
+  attribute \src "attrib08_mod_inst.v:16"
+  wire input 3 \inp
+  attribute \src "attrib08_mod_inst.v:17"
+  wire output 4 \out
+  attribute \src "attrib08_mod_inst.v:15"
+  wire input 2 \rst
+  attribute \module_not_derived 1
+  attribute \my_module_instance 99
+  attribute \src "attrib08_mod_inst.v:20"
+  cell \bar \bar_instance
+    connect $1 \clk
+    connect $2 \rst
+    connect $3 \inp
+    connect $4 \out
+  end
+end
diff --git a/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.json b/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.json
new file mode 100644
index 00000000000..a502809729c
--- /dev/null
+++ b/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.json
@@ -0,0 +1,202 @@
+{
+  "creator": "Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)",
+  "modules": {
+    "bar": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib08_mod_inst.v:1"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "$not$attrib08_mod_inst.v:9$2": {
+          "hide_name": 1,
+          "type": "$not",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "attrib08_mod_inst.v:9"
+          },
+          "port_directions": {
+            "A": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "Y": {
+              "bits": [ 6 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "$0\\out[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:7"
+          }
+        },
+        "$not$attrib08_mod_inst.v:9$2_Y": {
+          "hide_name": 1,
+          "bits": [ 6 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:9"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:2"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:4"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:5"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:3"
+          }
+        }
+      }
+    },
+    "foo": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "attrib08_mod_inst.v:13"
+      },
+      "parameters": {
+      },
+      "ports": {
+        "clk": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "rst": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "inp": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "out": {
+          "direction": "output",
+          "bits": [ 5 ]
+        }
+      },
+      "cells": {
+        "bar_instance": {
+          "hide_name": 0,
+          "type": "bar",
+          "parameters": {
+          },
+          "attributes": {
+            "module_not_derived": 1,
+            "my_module_instance": 99,
+            "src": "attrib08_mod_inst.v:20"
+          },
+          "port_directions": {
+            "$1": "output",
+            "$2": "output",
+            "$3": "output",
+            "$4": "output"
+          },
+          "connections": {
+            "$1": {
+              "bits": [ 2 ],
+              "attributes": {
+            }
+            },
+            "$2": {
+              "bits": [ 3 ],
+              "attributes": {
+            }
+            },
+            "$3": {
+              "bits": [ 4 ],
+              "attributes": {
+            }
+            },
+            "$4": {
+              "bits": [ 5 ],
+              "attributes": {
+            }
+            }
+          }
+        }
+      },
+      "netnames": {
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:14"
+          }
+        },
+        "inp": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:16"
+          }
+        },
+        "out": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:17"
+          }
+        },
+        "rst": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "attrib08_mod_inst.v:15"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.v b/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.v
new file mode 100644
index 00000000000..767860c15b5
--- /dev/null
+++ b/tests/reference-out/attrib08_mod_inst/attrib08_mod_inst.ref.v
@@ -0,0 +1,54 @@
+/* Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+(* cells_not_processed =  1  *)
+(* src = "attrib08_mod_inst.v:1" *)
+module bar(clk, rst, inp, out);
+  (* src = "attrib08_mod_inst.v:7" *)
+  reg _0_;
+  (* src = "attrib08_mod_inst.v:9" *)
+  wire _1_;
+  (* src = "attrib08_mod_inst.v:2" *)
+  input clk;
+  (* src = "attrib08_mod_inst.v:4" *)
+  input inp;
+  (* src = "attrib08_mod_inst.v:5" *)
+  output out;
+  reg out;
+  (* src = "attrib08_mod_inst.v:3" *)
+  input rst;
+  assign _1_ = ~ (* src = "attrib08_mod_inst.v:9" *) inp;
+  always @* begin
+    _0_ = out;
+    casez (rst)
+      1'h1:
+          _0_ = 1'h0;
+      default:
+          _0_ = _1_;
+    endcase
+  end
+  always @(posedge clk) begin
+      out <= _0_;
+  end
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "attrib08_mod_inst.v:13" *)
+module foo(clk, rst, inp, out);
+  (* src = "attrib08_mod_inst.v:14" *)
+  input clk;
+  (* src = "attrib08_mod_inst.v:16" *)
+  input inp;
+  (* src = "attrib08_mod_inst.v:17" *)
+  output out;
+  (* src = "attrib08_mod_inst.v:15" *)
+  input rst;
+  (* module_not_derived = 32'd1 *)
+  (* my_module_instance = 32'd99 *)
+  (* src = "attrib08_mod_inst.v:20" *)
+  bar bar_instance (
+    clk,
+    rst,
+    inp,
+    out
+  );
+endmodule
diff --git a/tests/reference-out/attrib09_case.v.DISABLED b/tests/reference-out/attrib09_case.v.DISABLED
new file mode 100644
index 00000000000..8551bf9d0a4
--- /dev/null
+++ b/tests/reference-out/attrib09_case.v.DISABLED
@@ -0,0 +1,26 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [1:0] inp;
+  output reg  [1:0] out;
+
+  always @(inp)
+    (* full_case, parallel_case *)
+    case(inp)
+      2'd0: out <= 2'd3;
+      2'd1: out <= 2'd2;
+      2'd2: out <= 2'd1;
+      2'd3: out <= 2'd0;
+    endcase
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [1:0] inp;
+  output wire [1:0] out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/reference-out/prepare_reference_out.sh b/tests/reference-out/prepare_reference_out.sh
new file mode 100755
index 00000000000..96191aff18e
--- /dev/null
+++ b/tests/reference-out/prepare_reference_out.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+# This script generates reference outpus for testing.
+# Usage: prepare_reference_out.sh <verilog_file_name>
+
+INP_FILE=$1
+
+BASE_NAME=$(basename ${INP_FILE})
+BASE_NAME=${BASE_NAME%.*}
+
+mkdir -p ${BASE_NAME}
+
+# List of backends
+BACKEND=( "verilog" "ilang" "json" )
+EXT=( "v" "il" "json" )
+
+# Generate
+for i in "${!BACKEND[@]}"; do
+    REF_FILE=${BASE_NAME}/${BASE_NAME%.*}.ref.${EXT[i]}    
+    ${YOSYS} -p "read_verilog $1; write_${BACKEND[i]} ${REF_FILE}" >${REF_FILE}.out.log 2>${REF_FILE}.err.log
+done
+
diff --git a/tests/reference-out/run-test.sh b/tests/reference-out/run-test.sh
new file mode 100755
index 00000000000..d2f36d70e09
--- /dev/null
+++ b/tests/reference-out/run-test.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+# This script loops over all verilog files in the current directory. Each one
+# is read by the Yosys and then written back using specified backends. Then
+# each backend output is compared with a reference output. 
+
+set +e
+YOSYS=../../yosys
+
+# List of backends
+BACKEND=( "verilog" "ilang" "json" )
+EXT=( "v" "il" "json" )
+
+# Loop over all verilog files in this folder
+for INP_FILE in *.v; do
+
+    BASE_NAME=$(basename ${INP_FILE})
+    BASE_NAME=${BASE_NAME%.*}
+
+    # Test each backend
+    for i in "${!BACKEND[@]}"; do
+        echo "Checking "${BACKEND[i]}" against "${INP_FILE}" ..."
+
+        REF_FILE=${BASE_NAME}/${BASE_NAME%.*}.ref.${EXT[i]}
+        OUT_FILE=${BASE_NAME}/${BASE_NAME%.*}.out.${EXT[i]}
+
+        # Check if the reference file exists
+        if [ ! -f "${REF_FILE}" ]; then
+            echo "ERROR: Reference file "${REF_FILE}" not found!"
+            exit -1
+        fi
+
+        # Generate output
+        set -e
+        ${YOSYS} -p "read_verilog ${INP_FILE}; write_${BACKEND[i]} ${OUT_FILE}" >${OUT_FILE}.out.log 2>${OUT_FILE}.err.log
+
+        # Compare files
+        set +e
+        diff -q -I "Yosys" ${OUT_FILE} ${REF_FILE}
+
+        # Fail if there is a difference
+        if [ $? -ne 0 ]; then
+            echo "ERROR: output and reference differ!"
+            diff -y --color=auto ${OUT_FILE} ${REF_FILE}
+            exit -1
+        fi
+    done
+done
+
diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
new file mode 100644
index 00000000000..adef34f5b76
--- /dev/null
+++ b/tests/simple/attrib01_module.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
new file mode 100644
index 00000000000..3505e726535
--- /dev/null
+++ b/tests/simple/attrib02_port_decl.v
@@ -0,0 +1,25 @@
+module bar(clk, rst, inp, out);
+  (* this_is_clock = 1 *)
+  input  wire clk;
+  (* this_is_reset = 1 *)
+  input  wire rst;
+  input  wire inp;
+  (* an_output_register = 1*)
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  (* this_is_the_master_clock *)
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
new file mode 100644
index 00000000000..562d225cd5b
--- /dev/null
+++ b/tests/simple/attrib03_parameter.v
@@ -0,0 +1,28 @@
+module bar(clk, rst, inp, out);
+
+  (* bus_width *)
+  parameter WIDTH = 2;
+
+  (* an_attribute_on_localparam = 55 *)
+  localparam INCREMENT = 5;
+
+  input  wire clk;
+  input  wire rst;
+  input  wire [WIDTH-1:0] inp;
+  output reg  [WIDTH-1:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= inp + INCREMENT;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp;
+  output wire [7:0] out;
+
+  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
new file mode 100644
index 00000000000..8b552340651
--- /dev/null
+++ b/tests/simple/attrib04_net_var.v
@@ -0,0 +1,32 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  (* this_is_a_prescaler *)
+  reg [7:0] counter;
+
+  (* temp_wire *)
+  wire out_val;
+
+  always @(posedge clk)
+    counter <= counter + 1;
+
+  assign out_val = inp ^ counter[4];
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= out_val;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
new file mode 100644
index 00000000000..e20e6631950
--- /dev/null
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
new file mode 100644
index 00000000000..e21173c58f4
--- /dev/null
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -0,0 +1,23 @@
+module bar(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output reg  [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= inp_a + (* ripple_adder *) inp_b;
+
+endmodule
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  bar bar_instance (clk, rst, inp_a, inp_b, out);
+endmodule
+
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
new file mode 100644
index 00000000000..f55ef231609
--- /dev/null
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+  input [7:0] inp_a;
+  input [7:0] inp_b;
+
+  do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [7:0] inp_a;
+  input  wire [7:0] inp_b;
+  output wire [7:0] out;
+
+  always @(posedge clk)
+    if (rst) out <= 0;
+    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
new file mode 100644
index 00000000000..c5a32234eed
--- /dev/null
+++ b/tests/simple/attrib08_mod_inst.v
@@ -0,0 +1,22 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output reg  out;
+
+  always @(posedge clk)
+    if (rst) out <= 1'd0;
+    else     out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire inp;
+  output wire out;
+
+  (* my_module_instance = 99 *)
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
new file mode 100644
index 00000000000..8551bf9d0a4
--- /dev/null
+++ b/tests/simple/attrib09_case.v
@@ -0,0 +1,26 @@
+module bar(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [1:0] inp;
+  output reg  [1:0] out;
+
+  always @(inp)
+    (* full_case, parallel_case *)
+    case(inp)
+      2'd0: out <= 2'd3;
+      2'd1: out <= 2'd2;
+      2'd2: out <= 2'd1;
+      2'd3: out <= 2'd0;
+    endcase
+
+endmodule
+
+module foo(clk, rst, inp, out);
+  input  wire clk;
+  input  wire rst;
+  input  wire [1:0] inp;
+  output wire [1:0] out;
+
+  bar bar_instance (clk, rst, inp, out);
+endmodule
+