diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 63b71b80010..d7ef8d7dcea 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2351,7 +2351,7 @@ skip_dynamic_range_lvalue_expansion:;
 					wire->is_input = false;
 					wire->is_output = false;
 					wire->is_reg = true;
-					wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+						wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
 					wire_cache[child->str] = wire;
 
 					current_ast_mod->children.push_back(wire);
@@ -2399,9 +2399,9 @@ skip_dynamic_range_lvalue_expansion:;
 			log_assert(it != current_block->children.end());
 			if (*it == current_block_child) {
 				current_block->children.insert(it, new_stmts.begin(), new_stmts.end());
-				break;
+					break;
+				}
 			}
-		}
 
 	replace_fcall_with_id:
 		if (type == AST_FCALL) {
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt
index f1161114e9b..138540b2dbb 100644
--- a/techlibs/xilinx/brams.txt
+++ b/techlibs/xilinx/brams.txt
@@ -72,13 +72,15 @@ bram $__XILINX_RAMB18_TDP
   clkpol 2 3
 endbram
 
-match $__XILINX_RAMB36_SDP
-  min bits 4096
-  min efficiency 5
-  shuffle_enable B
-  make_transp
-  or_next_if_better
-endmatch
+# Disable RAMB36 synthesis until https://github.com/SymbiFlow/symbiflow-arch-defs/issues/438
+# is solved.
+#match $__XILINX_RAMB36_SDP
+#  min bits 4096
+#  min efficiency 5
+#  shuffle_enable B
+#  make_transp
+#  or_next_if_better
+#endmatch
 
 match $__XILINX_RAMB18_SDP
   min bits 4096
@@ -88,13 +90,13 @@ match $__XILINX_RAMB18_SDP
   or_next_if_better
 endmatch
 
-match $__XILINX_RAMB36_TDP
-  min bits 4096
-  min efficiency 5
-  shuffle_enable B
-  make_transp
-  or_next_if_better
-endmatch
+#match $__XILINX_RAMB36_TDP
+#  min bits 4096
+#  min efficiency 5
+#  shuffle_enable B
+#  make_transp
+#  or_next_if_better
+#endmatch
 
 match $__XILINX_RAMB18_TDP
   min bits 4096
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
index e6635d0e218..6705077d0ee 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/drams.txt
@@ -1,4 +1,17 @@
 
+bram $__XILINX_RAM32X1D
+  init 1
+  abits 5
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
 bram $__XILINX_RAM64X1D
   init 1
   abits 6
@@ -25,6 +38,11 @@ bram $__XILINX_RAM128X1D
   clkpol 0 2
 endbram
 
+match $__XILINX_RAM32X1D
+  make_outreg
+  or_next_if_better
+endmatch
+
 match $__XILINX_RAM64X1D
   make_outreg
   or_next_if_better
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
index 47476b59295..abecc8c4777 100644
--- a/techlibs/xilinx/drams_map.v
+++ b/techlibs/xilinx/drams_map.v
@@ -1,4 +1,38 @@
 
+module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [31:0] INIT = 31'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [4:0] A1ADDR;
+	output A1DATA;
+
+	input [4:0] B1ADDR;
+	input B1DATA;
+	input B1EN;
+
+	RAM32X1D #(
+		.INIT(INIT),
+		.IS_WCLK_INVERTED(!CLKPOL2)
+	) _TECHMAP_REPLACE_ (
+		.DPRA0(A1ADDR[0]),
+		.DPRA1(A1ADDR[1]),
+		.DPRA2(A1ADDR[2]),
+		.DPRA3(A1ADDR[3]),
+		.DPRA4(A1ADDR[4]),
+		.DPO(A1DATA),
+
+		.A0(B1ADDR[0]),
+		.A1(B1ADDR[1]),
+		.A2(B1ADDR[2]),
+		.A3(B1ADDR[3]),
+		.A4(B1ADDR[4]),
+		.D(B1DATA),
+		.WCLK(CLK1),
+		.WE(B1EN)
+	);
+endmodule
+
 module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	parameter [63:0] INIT = 64'bx;
 	parameter CLKPOL2 = 1;