From 946703dabf24df5cf254b3e718da59b8035ebc38 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 13 Jan 2024 19:00:59 +0100 Subject: [PATCH 1/2] genMetrics: less conditional code, less repetition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also, what exactly motivates yosys to output 'top ' here isn't entirely clear. This paves the way for a followup pull request Signed-off-by: Øyvind Harboe --- flow/util/genMetrics.py | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index 21284a752e..0c48114c75 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -251,16 +251,10 @@ def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): hierarchicalSynth = os.environ.get('SYNTH_HIERARCHICAL') - if hierarchicalSynth == '1': - extractTagFromFile('synth__design__instance__area__stdcell', - metrics_dict, - 'Chip area for top module.*: +(\S+)', - rptPath + '/synth_stat.txt') - else: - extractTagFromFile('synth__design__instance__area__stdcell', - metrics_dict, - 'Chip area for module.*: +(\S+)', - rptPath + '/synth_stat.txt') + extractTagFromFile('synth__design__instance__area__stdcell', + metrics_dict, + 'Chip area for (?:top )?module.*: +(\S+)', + rptPath + '/synth_stat.txt') # Clocks # ========================================================================= From 1ca5249d81470824a1119dc518f0bbfb581780aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 15 Jan 2024 18:57:33 +0100 Subject: [PATCH 2/2] genMetrics: nits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/util/genMetrics.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index 0c48114c75..1c3b5c3aa4 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -249,12 +249,10 @@ def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): 'Number of cells: +(\S+)', rptPath + '/synth_stat.txt') - hierarchicalSynth = os.environ.get('SYNTH_HIERARCHICAL') - extractTagFromFile('synth__design__instance__area__stdcell', - metrics_dict, - 'Chip area for (?:top )?module.*: +(\S+)', - rptPath + '/synth_stat.txt') + metrics_dict, + 'Chip area for (?:top )?module.*: +(\S+)', + rptPath + '/synth_stat.txt') # Clocks # =========================================================================