From f6f60923bb6c3826f9367b9ce673180ab5c886cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 13 Jan 2025 14:38:06 +0100 Subject: [PATCH] mock-array: add missing signals in .vcd file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- flow/designs/asap7/mock-array/simulate.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/flow/designs/asap7/mock-array/simulate.sh b/flow/designs/asap7/mock-array/simulate.sh index 43d266e071..38e81028e8 100755 --- a/flow/designs/asap7/mock-array/simulate.sh +++ b/flow/designs/asap7/mock-array/simulate.sh @@ -27,6 +27,7 @@ verilator -Wall --cc \ --Mdir $OBJ_DIR \ --top-module MockArray \ --trace \ + --trace-underscore \ $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v \ $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v \ $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \